Display device

Abstract

To provide a display device capable of simultaneously driving a set of adjacent gate lines in a pixel configuration in which subpixels adjacent in the arrangement direction of gate lines have different colors.SOLUTION: A display device comprises: a plurality of pixels Pix arranged in a first direction and in a second direction intersecting the first direction; a plurality of gate lines SCL extending in the first direction and arranged in the second direction; a plurality of signal lines DTL extending in the second direction and arranged in the first direction; and a drive circuit 40 which drives the pixels Pix via the signal lines DTL and the gate lines SCL. When the total number of pixels Pix arranged in an ascending order from a first column to an m-th column from one end to the other end in the first direction is M, and the total number of pixels Pix arranged in an ascending order from a first row to an n-th row from one end to the other end in the second direction is N, the total number of gate lines SCL is N, and the total number of signal lines DTL is M+1. The n-th gate line SCL is connected to the pixels Pix arranged in the n-th row of each column, and the m-th signal line DTL is connected to the pixels Pix arranged in the m-1-th column of odd-numbered rows and the pixels Pix arranged in the m-th column of even-numbered rows.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a display device.

Background Art

[0002] In recent years, in configurations where display images are magnified and displayed by lenses, such as VR (Virtual Reality), AR (Augmented Reality), and MR (Mixed Reality), further high definition of display panels has been demanded. Conventionally, as a configuration for realizing a high frame rate with such a high-definition panel, a display device capable of simultaneously driving a plurality of sets of adjacent gate lines has been disclosed (for example, Patent Document 1).

[0003] On the other hand, in a pixel configuration of a general square RGB stripe array, the widths of the R, G, and B sub-pixels in the arrangement direction become narrow, making it difficult to secure the aperture area. For this reason, a pixel configuration that easily secures the aperture areas of the R, G, and B sub-pixels with the same pixel area as the pixel configuration of the RGB stripe array has been disclosed (for example, Patent Document 2). In the pixel array described in Patent Document 2, high definition is made possible with respect to the pixel configuration of the RGB stripe array.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the pixel array described in Patent Document 2 above, the colors of sub-pixels adjacent in the arrangement direction of gate lines are different. Also, a common signal line is connected to sub-pixels of different colors. In a display device having such a pixel configuration, it is not possible to adopt a configuration in which a plurality of sets of adjacent gate lines are driven simultaneously.

[0006] An object of the present invention is to provide a display device capable of simultaneously driving a plurality of sets of adjacent gate lines in a pixel configuration in which the colors of sub-pixels adjacent in the arrangement direction of gate lines are different.

Means for Solving the Problems

[0007] A display device according to an aspect of the present disclosure includes a plurality of pixels arranged in a matrix in a first direction of a display area and a second direction intersecting the first direction, a plurality of gate lines extending in the first direction and arranged in the second direction, a plurality of signal lines extending in the second direction and arranged in the first direction, and a driving circuit that supplies a pixel signal to the pixels via the signal lines and drives the pixels via the gate lines. When the total number of pixels arranged in ascending order from the first column to the m-th column (m is a natural number) from one end to the other end in the first direction is M, and the total number of pixels arranged in ascending order from the first row to the n-th row (n is a natural number) from one end to the other end in the second direction is N, the total number of the gate lines is N, the total number of the signal lines is M + 1, the n-th gate line is connected to the pixels arranged in the n-th row of each column, and the m-th signal line is connected to the pixels arranged in the (m - 1)-th column of odd rows and the pixels arranged in the m-th column of even rows.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

BEST MODE FOR CARRYING OUT THE INVENTION

[0009] The mode for carrying out the invention (embodiment) will be described in detail with reference to the drawings. The present invention is not limited by the content described in the following embodiments. In addition, the constituent elements described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the constituent elements described below can be combined as appropriate. Note that the disclosure is merely an example, and those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, for the purpose of making the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part compared to the actual aspect, but this is merely an example and does not limit the interpretation of the present invention. Also, in this specification and each drawing, the same reference numerals may be assigned to the same elements as those described above with respect to the previously shown drawings, and detailed descriptions may be omitted as appropriate.

[0010] FIG. 1 is a diagram showing an example of the schematic configuration of the display device according to the embodiment. FIG. 2 is a diagram showing an example of the pixel configuration in the display area.

[0011] The display device 1 according to this embodiment is, for example, a liquid crystal display device using a liquid crystal display element as a display element. Further, in the present disclosure, as a driving method, the display device 1 can adopt, for example, a column inversion driving method, a frame inversion method, or the like. The driving method in the display device 1 is not limited to the column inversion driving method or the frame inversion method.

[0012] In the display device 1, a display area AA is provided on the display panel 11, and a driving circuit 40 is provided in the peripheral area of the display area AA. The display device 1 is supplied with power from a power supply device 12.

[0013] The driving circuit 40 includes a gate driver 42, a signal line selection circuit 43, and a display control circuit 44. The gate driver 42 and the signal line selection circuit 43 are thin film transistor (TFT) circuits formed in the peripheral area of the display area AA. The display control circuit 44 is included in a driver IC4 mounted in the peripheral area of the display area AA. The driver IC4 is connected to the control device 13 via a relay board composed of, for example, a flexible printed circuit (FPC).

[0014] The control device 13 controls the power supply from the power supply device 12 to the display device 1. Further, the control device 13 controls the power-on and power-off of the display device 1. The power supply device 12 and the control device 13 are mounted, for example, on a device (not shown) on which the display device 1 is mounted.

[0015] In the display area AA, a plurality of pixels Pix arranged in the Dx direction (first direction) and the Dy direction (second direction) are provided. Further, in the display area AA, a gate line SCL that supplies a gate signal GATE to the pixel Pix, a signal line DTL that supplies a pixel signal SIG to the pixel Pix, and a common electrode COML that supplies a common potential VCOM to the pixel Pix are provided. In the present embodiment, the gate line SCL is provided extending in the Dx direction (first direction). Further, in the present embodiment, the signal line DTL is provided extending in the Dy direction (second direction).

[0016] In FIG. 1, the total number of pixels Pix arranged in ascending order from the first column to the m-th column (m is a natural number) from one end to the other end in the Dx direction (first direction) is denoted as M, and the total number of pixels Pix arranged in ascending order from the first row to the n-th row (n is a natural number) from one end to the other end in the Dy direction (second direction) is denoted as N. At this time, in the display device 1 according to the embodiment, the total number of gate lines SCL arranged in the Dy direction (second direction) is N, and the total number of signal lines DTL arranged in the Dx direction (first direction) is M + 1. Hereinafter, the n-th gate line SCL is referred to as "gate line SCL <n>」 is also described, and the m-th signal line is referred to as "signal line DTL" <m>It is also described as "」".

[0017] In the configuration of the display device 1 according to the embodiment shown in FIG. 1, the gate line SCL <n>is connected to the pixel Pix arranged in the n-th row of each column. Also, the signal line DTL <m>is connected to the pixel Pix arranged in the (m-1)-th column of the odd rows and the pixel Pix arranged in the m-th column of the even rows. Hereinafter, the pixel Pix provided in the m-th column of the n-th row will also be simply referred to as "the pixel Pix of the n-th row and m-th column".

[0018] As shown in FIG. 2, each pixel Pix includes a pixel transistor Tr and a pixel electrode PX. The pixel transistor Tr is composed of a thin film transistor (TFT), for example, an n-channel MOS (Metal Oxide Semiconductor) type TFT (hereinafter, also referred to as "n-type TFT").

[0019] In FIG. 2, the pixels Pix arranged from the n-th row to the (n + 3)-th row are illustrated. Also, in FIG. 2, the pixels Pix arranged in the (m-1)-th column and the m-th column are illustrated.

[0020] Also, in FIG. 2, the n-th row ((n + 2)-th row) is an odd row, and the (n + 1)-th row ((n + 3)-th row) is an even row.

[0021] The source of the pixel transistor Tr of the pixel Pix of the n-th row and (m-1)-th column is the signal line DTL <m>is connected, and the gate is the gate line SCL <n>is connected to. Also, the source of the pixel transistor Tr of the pixel Pix of n + 1 rows and m - 1 columns is the signal line DTL <m-1>is connected, and the gate is connected to the gate line SCL<n+1>. Also, the source of the pixel transistor Tr of the pixel Pix in the (n+2)-th row and (m-1)-th column is the signal line DTL <m>is connected, and the gate is connected to the gate line SCL<n+2>. Also, the source of the pixel transistor Tr of the pixel Pix at the (n+3)th row and (m-1)th column is the signal line DTL <m-1>is connected, and the gate is connected to the gate line SCL<n+3>.

[0022] The source of the pixel transistor Tr of the pixel Pix of n rows and m columns is connected to the signal line DTL<m+1>, and the gate is connected to the gate line SCL <n>is connected thereto. Also, the source of the pixel transistor Tr of the pixel Pix of n + 1 rows and m columns is the signal line DTL <m>is connected to, and the gate is connected to the gate line SCL<n+1>. Also, the source of the pixel transistor Tr of the pixel Pix in the n+2-th row and m-th column is connected to the signal line DTL<m+1>, and the gate is connected to the gate line SCL<n+2>. Also, the source of the pixel transistor Tr of the pixel Pix in the n+3-th row and m-th column is the signal line DTL <m>is connected, and the gate is connected to the gate line SCL<n+3>.

[0023] The drain of the pixel transistor Tr of each pixel Pix is connected to the pixel electrode PX. A holding capacitor Cs is formed between the pixel electrode PX and the common electrode COML.

[0024] A gate signal GATE is supplied to the gates of the pixel transistors Tr of the pixels Pix arranged in the Dx direction (first direction) via the gate line SCL, and a pixel signal SIG is supplied to the sources of the pixel transistors Tr of the pixels Pix arranged in the Dy direction (second direction) via the signal line DTL. Hereinafter, the gate signal GATE supplied to the pixels Pix arranged in the nth row is referred to as "gate signal GATE" <n>」 is also described, and the pixel signal SIG supplied to the pixel Pix arranged in the m-th column is "pixel signal SIG" <m>」 is also described.

[0025] For the pixels Pix arranged in the n-th row of each column, the gate line SCL <n>Via the gate signal GATE <n>is supplied.

[0026] Pixels Pix arranged in the m-1 column of odd rows and pixels Pix arranged in the m column of even rows are connected to signal lines DTL <m>Via a common pixel signal SIG <m>is supplied.

[0027] In the present disclosure, the pixel Pix includes, for example, a first pixel PixR for displaying red (R), a second pixel PixG for displaying green (G), and a third pixel PixB for displaying blue (B).

[0028] As shown in FIG. 1, in the present disclosure, the first pixel PixR, the second pixel PixG, and the third pixel PixB are arranged in the order of the first pixel PixR, the second pixel PixG, and the third pixel PixB in ascending order in the Dx direction (first direction).

[0029] Also, as shown in FIG. 1, in the present disclosure, the first pixel PixR, the second pixel PixG, and the third pixel PixB are arranged in the order of the first pixel PixR, the second pixel PixG, and the third pixel PixB in descending order in the Dy direction (second direction).

[0030] In the pixel configuration according to the above-described embodiment, the display colors of the pixels Pix in the n-th row and m-th column and the display colors of the pixels Pix in the n-th row and (m + 1)-th column are different from each other.

[0031] Also, in the pixel configuration according to the above-described embodiment, the display colors of the pixels Pix in the n-th row and m-th column and the display colors of the pixels Pix in the (n + 1)-th row and m-th column are different from each other.

[0032] Also, in the pixel configuration according to the above-described embodiment, the display colors of the pixels Pix in the n-th row and m-th column and the display colors of the pixels Pix in the (n + 1)-th row and (m + 1)-th column are the same.

[0033] The power supply device 12 generates a first potential VGL having a negative value and a second potential VGH having a positive value and supplies them to the display device 1. The first potential VGL is, for example, -8V. The second potential VGH is, for example, +8V. The first potential VGL and the second potential VGH are supplied to the gate driver 42. Note that the first potential VGL supplied to the gate driver 42 is not limited to -8V. Also, the second potential VGH supplied to the gate driver 42 is not limited to +8V.

[0034] In addition, the power supply device 12 generates a negative third potential VL and a positive fourth potential VH and supplies them to the display device 1. The third potential VL is, for example, -5V. The fourth potential VH is, for example, +5V. The third potential VL and the fourth potential VH are supplied to the driver IC 4. Note that the third potential VL supplied to the driver IC 4 is not limited to -5V. Also, the fourth potential VH supplied to the driver IC 4 is not limited to +5V.

[0035] The control device 13 transmits a video signal Source, which is the original signal of the video to be displayed on the display device 1, to the display device 1.

[0036] The control device 13 includes, for example, a CPU (Central Processing Unit) and a storage device such as a memory. The control device 13 can realize the display function of the display device 1 by executing a program using these hardware resources such as the CPU and the storage device. The control device 13 controls the image to be displayed on the display device 1 so that the driver IC 4 can handle it as information on the image input gradation according to the execution result of the program.

[0037] The display control circuit 44 controls the display operation in the display area AA by controlling the gate driver 42 and the signal line selection circuit 43. The display control circuit 44 receives the video signal Source and various control signals from the control device 13. Also, the display control circuit 44 converts the video signal Source from the control device 13 into an image signal Vsig and outputs it. The image signal Vsig is, for example, a signal obtained by time-division multiplexing pixel signals Sig corresponding to the pixel array of RGB(W). Also, the display control circuit 44 supplies a common potential VCOM to the common electrode COML.

[0038] Further, the display control circuit 44 has functions as an interface (I / F) between the signal line selection circuit 43 and the control device 13 and a timing generator. Note that the driver IC 4 including the display control circuit 44 may be mounted not on the display panel 11 but on a relay board connected to the display panel 11. Also, the gate driver 42 and the signal line selection circuit 43 may be included in the driver IC 4.

[0039] Next, the schematic structure of the display device 1 according to the embodiment will be described. FIG. 3 is a cross-sectional view showing the schematic cross-sectional structure of the display device.

[0040] The array substrate 2 includes a first substrate 21 made of glass or a transparent resin, a plurality of pixel electrodes PX, a common electrode COML, and an insulating layer 24 that insulates the pixel electrode PX and the common electrode COML. The plurality of pixel electrodes PX are disposed, for example, in a matrix (matrix) shape above the first substrate 21. The common electrode COML is provided between the first substrate 21 and the pixel electrode PX.

[0041] The pixel electrode PX is provided corresponding to each pixel Pix. A pixel signal SIG for performing a display operation is supplied from the signal line selection circuit 43 to the pixel electrode PX via the signal line DTL and the pixel transistor Tr. Also, during the display operation, a common potential VCOM for display, which is a voltage signal, is supplied from the driver IC 4 to the common electrode COML. The common potential VCOM preferably has a potential different from the GND potential, and is, for example, about -0.08V. The set value of the common potential VCOM is set to an optimum value at which flicker does not occur in a driving method such as a column inversion driving method or a frame inversion driving method. Also, the common potential VCOM is preferably a fixed potential, but may have a configuration having a waveform composed of an alternating rectangular wave.

[0042] The pixel electrode PX and the common electrode COML are made of a conductive material having translucency, such as ITO (Indium Tin Oxide), for example. A polarizing plate 35B is provided below the first substrate 21 via an adhesive layer (not shown).

[0043] The counter substrate 3 includes a second substrate 31 made of glass or a transparent resin, and a color filter 32 and a light-shielding layer (not shown) formed on one surface of the second substrate 31. Further, a polarizing plate 35A is provided above the second substrate 31 via an adhesive layer (not shown).

[0044] The color filter 32 is provided corresponding to each pixel Pix. Specifically, a red (R) color filter is provided at a position corresponding to the pixel electrode PX of the first pixel PixR. Also, a green (G) color filter is provided at a position corresponding to the pixel electrode PX of the second pixel PixG. Further, a blue (B) color filter is provided at a position corresponding to the pixel electrode PX of the third pixel PixB.

[0045] The array substrate 2 and the counter substrate 3 are arranged to face each other with a predetermined interval (cell gap). A liquid crystal layer 6 is provided as a display function layer in the space between the first substrate 21 and the second substrate 31. The liquid crystal layer 6 modulates the light passing through the liquid crystal layer 6 by changing the alignment state of the liquid crystal molecules for each pixel Pix according to the state of the electric field between each pixel electrode PX and the common electrode COML. In the present embodiment, for example, a liquid crystal suitable for a horizontal electric field mode such as IPS (In-Plane Switching) including FFS (Fringe Field Switching) is used.

[0046] The array substrate 2 includes wirings such as a pixel transistor Tr for each pixel Pix, a gate line SCL for supplying a gate signal GATE for driving each pixel transistor Tr, and a signal line DTL for supplying a pixel signal SIG to each pixel electrode PX. The gate line SCL extends in the Dx direction (first direction) on a plane parallel to the surface of the first substrate 21. The signal line DTL extends in the Dy direction (second direction) on a plane parallel to the surface of the first substrate 21.

[0047] FIG. 4 is a block diagram showing a configuration example of a gate driver. As shown in FIG. 4, the gate driver 42 includes a shift register circuit 421 and a gate line driving circuit 422.

[0048] The gate line driving circuit 422 is a circuit that generates a scanning signal GATE to be supplied to the gate of the pixel transistor Tr based on the output signal SRout output from the shift register circuit 421 and the enable signal ENB output from the display control circuit 44. The gate line driving circuit 422 includes gate line driving circuits 422_1, ···, 422_p, ···, 422_P. The shift register circuit 421 includes shift register circuits 421_1, ···, 421_p, ···, 421_P.

[0049] In the configuration example shown in FIG. 4, the total number P of the gate line driving circuits 422 corresponds to 1 / 4 of the total number M of the pixels Pix arranged in the Dy direction (second direction) (P × 4 = M). Each of the gate line driving circuits 422_p (p is a natural number from 1 to P) is a circuit that drives four gate lines SCL arranged continuously in the Dy direction (second direction). Specifically, the gate line driving circuit 422_1 supplies gate signals GATE<1>, GATE<2>, GATE<3>, GATE<4>. The gate line driving circuit 422_p supplies the gate signal GATE <n>, supply GATE<n+1>, GATE<n+2>, GATE<n+3>. The gate line driving circuit 422_P supplies the gate signal GATE <n-3>,GATE <n-2>,GATE <n-1>,GATE <n>It supplies. Note that the number of gate lines SCL to which the gate line driving circuit 422_p supplies the gate signal GATE is not limited to 4. When the number of gate lines SCL to which the gate line driving circuit 422_p supplies the gate signal GATE is Q, the total number P of the gate line driving circuits 422 corresponds to 1 / Q of the total number M of the pixels Pix arranged in the Dy direction (the second direction) (P×Q = M).

[0050] Also, in the configuration example shown in FIG. 4, the shift register circuits 421_1, ···, 421_p, ···, 421_P are respectively provided corresponding to the gate line driving circuits 422_1, ···, 422_p, ···, 422_P. Specifically, the output signal SRout(1) of the shift register circuit 421_1 is supplied to the gate line driving circuit 422_1, the output signal SRout(p) of the shift register circuit 421_p is supplied to the gate line driving circuit 422_p, and the output signal SRout(P) of the shift register circuit 421_P is supplied to the gate line driving circuit 422_P.

[0051] FIG. 5 is a circuit diagram showing an example of the circuit configuration of the shift register circuit. The start pulse signal STV and the shift clock signal CKV are supplied from the display control circuit 44 to the shift register circuit 421.

[0052] The start pulse signal STV and the shift clock signal CKV are binary logic signals of a high potential and a low potential.

[0053] The start pulse signal STV is a signal that defines one frame period 1F of the display device 1. Specifically, one frame period 1F of the display device 1 according to the embodiment is defined starting from the rising edge of the start pulse signal STV. In other words, one frame period 1F is a period for displaying an image signal Vsig for one frame.

[0054] The shift clock signal CKV is a signal that logically inverts at a predetermined period. More specifically, the shift clock signal CKV is a signal that transitions from a low potential to a high potential with one period being the high potential period of the start pulse signal STV.

[0055] A start pulse signal STV and a shift clock signal CKV are input to the shift register circuit 421_1. Instead of the start pulse signal STV, an output signal SROUT(p-1) of the previous-stage shift register circuit 421_p-1 (not shown) is input to the shift register circuit 421_p. Instead of the start pulse signal STV, an output signal SROUT(P-1) of the previous-stage shift register circuit 421_P-1 (not shown) is input to the shift register circuit 421_P.

[0056] The shift register circuits 421_1, ···, 421_p, ···, 421_P each include clocked inverters 51, 53, 54, 56 and inverters 52, 55. The shift register circuits 421_1, ···, 421_p, ···, 421_P generate an inverted shift clock signal xCKV obtained by logically inverting the shift clock signal CKV.

[0057] When the shift clock signal CKV is at a high level and the inverted shift clock signal xCKV is at a low level, the clocked inverters 51, 56 are turned on and the clocked inverters 53, 54 are turned off. At this time, when the start pulse signal STV (or the output signal SROUT(p-1) of the previous-stage shift register circuit 421_p-1 (not shown)) becomes a high level, a high level is held as the output potential of the inverter 52.

[0058] In this state, when the shift clock signal CKV is at a low level and the inverted shift clock signal xCKV is at a high level, the clocked inverters 51, 56 are turned off and the clocked inverters 53, 54 are turned on. As a result, the high level held as the output potential of the inverter 52 becomes the output potential of the output signal SRout(p).

[0059] When the shift clock signal CKV is at a high level and the inverted shift clock signal xCKV is at a low level, the clock inverters 51 and 56 are turned on, and the clock inverters 53 and 54 are turned off. At this time, when the start pulse signal STV (or the output signal SROUT(p - 1) of the previous shift register circuit 421_p - 1 (not shown)) is at a low level, a low level is held as the output potential of the inverter 52.

[0060] In this state, when the shift clock signal CKV is at a low level and the inverted shift clock signal xCKV is at a high level, the clock inverters 51 and 56 are turned off, and the clock inverters 53 and 54 are turned on. As a result, the low level held as the output potential of the inverter 52 becomes the output potential of the output signal SRout(p).

[0061] FIG. 6 is a circuit diagram showing an example of the circuit configuration of the gate line driving circuit. The gate line driving circuit 422 is supplied with a first enable signal ENB1, a second enable signal ENB2, a third enable signal ENB3, and a fourth enable signal ENB4 from the display control circuit 44.

[0062] The output signal SRout(1) of the shift register circuit 421_1 is input to the gate line driving circuit 422_1. The output signal SRout(p) of the shift register circuit 421_p is input to the gate line driving circuit 422_p. The output signal SRout(P) of the shift register circuit 421_P is input to the gate line driving circuit 422_P.

[0063] Hereinafter, the configuration of the gate line driving circuit 422_p will be described. The gate line driving circuit 422_p generates an inverted output signal xSRout(p) obtained by logically inverting the output signal SRout(p) output from the shift register circuit 421_p.

[0064] The gate line driving circuit 422_p supplies a gate signal GATE to the pixel Pix arranged in the Dx direction (first direction) at the nth position in the Dy direction (second direction). <n>A first buffer circuit 61_1 that generates, a second buffer circuit 61_2 that generates a gate signal GATE<n+1> to be supplied to a pixel Pix arranged in the Dx direction (first direction) at the (n+1)-th position in the Dy direction (second direction), a third buffer circuit 61_3 that generates a gate signal GATE<n+2> to be supplied to a pixel Pix arranged in the Dx direction (first direction) at the (n+2)-th position in the Dy direction (second direction), and a fourth buffer circuit 61_4 that generates a gate signal GATE<n+3> to be supplied to a pixel Pix arranged in the Dx direction (first direction) at the (n+3)-th position in the Dy direction (second direction).

[0065] When the output signal SRout(p) output from the shift register circuit 421_p is at a low potential (first potential VGL), the first buffer circuit 61_1 controls the first transistor Tr1 and the second transistor Tr2 to be off and controls the third transistor Tr3 to be on. As a result, the output potential of the first buffer circuit 61_1 becomes the first potential VGL, and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (first direction) at the n-th position in the Dy direction (second direction) is controlled to be off.

[0066] Also, when the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (second potential VGH), the first buffer circuit 61_1 controls the first transistor Tr1 and the second transistor Tr2 to be on and controls the third transistor Tr3 to be off. As a result, the output potential of the first buffer circuit 61_1 becomes a potential (for example, the second potential VGH) depending on the potential of the first enable signal ENB1, and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (first direction) at the n-th position in the Dy direction (second direction) is controlled to be on.

[0067] When the output signal SRout(p) output from the shift register circuit 421_p is at a low potential (the first potential VGL), the first transistor Tr1 and the second transistor Tr2 of the second buffer circuit 61_2 are turned off, and the third transistor Tr3 is turned on. As a result, the output potential of the second buffer circuit 61_2 becomes the first potential VGL, and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (the first direction) at the (n + 1)-th position in the Dy direction (the second direction) is turned off.

[0068] Also, when the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (the second potential VGH), the first transistor Tr1 and the second transistor Tr2 of the second buffer circuit 61_2 are turned on, and the third transistor Tr3 is turned off. As a result, the output potential of the second buffer circuit 61_2 becomes a potential (for example, the second potential VGH) depending on the potential of the second enable signal ENB2, and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (the first direction) at the (n + 1)-th position in the Dy direction (the second direction) is turned on.

[0069] When the output signal SRout(p) output from the shift register circuit 421_p is at a low potential (the first potential VGL), the first transistor Tr1 and the second transistor Tr2 of the third buffer circuit 61_3 are turned off, and the third transistor Tr3 is turned on. As a result, the output potential of the third buffer circuit 61_3 becomes the first potential VGL, and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (the first direction) at the (n + 2)-th position in the Dy direction (the second direction) is turned off.

[0070] Further, when the output signal SRout(p) output from the shift register circuit 421_p is at a high level (second potential VGH), the third buffer circuit 61_3 controls the first transistor Tr1 and the second transistor Tr2 to be turned on, and controls the third transistor Tr3 to be turned off. As a result, the output potential of the third buffer circuit 61_3 becomes a potential (for example, the second potential VGH) depending on the potential of the third enable signal ENB3, and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (first direction) at the (n + 2)-th position in the Dy direction (second direction) is controlled to be turned on.

[0071] When the output signal SRout(p) output from the shift register circuit 421_p is at a low level (first potential VGL), the fourth buffer circuit 61_4 controls the first transistor Tr1 and the second transistor Tr2 to be turned off, and controls the third transistor Tr3 to be turned on. As a result, the output potential of the fourth buffer circuit 61_4 becomes the first potential VGL, and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (first direction) at the (n + 3)-th position in the Dy direction (second direction) is controlled to be turned off.

[0072] Further, when the output signal SRout(p) output from the shift register circuit 421_p is at a high level (second potential VGH), the fourth buffer circuit 61_4 controls the first transistor Tr1 and the second transistor Tr2 to be turned on, and controls the third transistor Tr3 to be turned off. As a result, the output potential of the fourth buffer circuit 61_4 becomes a potential (for example, the second potential VGH) depending on the potential of the fourth enable signal ENB4, and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (first direction) at the (n + 3)-th position in the Dy direction (second direction) is controlled to be turned on.

[0073] FIG. 7 is a timing chart showing a first driving example of the display device according to the embodiment. FIG. 8 is a timing chart showing a second driving example of the display device according to the embodiment.

[0074] In the first driving example shown in FIG. 7, an example is illustrated in which pixels Pix connected to gate lines SCL arranged in the Dy direction (second direction) are sequentially driven every one horizontal period 1H. In the second driving example shown in FIG. 8, an example is illustrated in which pixels Pix connected to two gate lines SCL arranged in the Dy direction (second direction) are simultaneously driven in one horizontal period 1H.

[0075] More specifically, in FIG. 8, in one horizontal period in the first half of two horizontal periods in which the output signal SRout(p) output from the shift register circuit 421_p becomes a high potential (second potential VGH), the gate signal GATE <n>The gate signal GATE<n+1> and the like simultaneously change from a low potential (first potential VGL) to a high potential (second potential VGH). As a result, the pixel transistor Tr of the pixel Pix arranged in the Dx direction (first direction) at the n-th position in the Dy direction (second direction) and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (first direction) at the (n+1)-th position in the Dy direction (second direction) are simultaneously turned on.

[0076] Also, in FIG. 8, in one horizontal period in the first half of the two horizontal periods during which the output signal SRout(p) output from the shift register circuit 421_p becomes a high potential (second potential VGH), the gate signal GATE <n>The gate signal GATE<n+1> and the other signal simultaneously change from the high potential (second potential VGH) to the low potential (first potential VGL). As a result, the pixel transistor Tr of the pixel Pix arranged in the Dx direction (first direction) at the n-th position in the Dy direction (second direction) and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (first direction) at the (n + 1)-th position in the Dy direction (second direction) are simultaneously turned off.

[0077] Also, in the latter half of the two horizontal periods when the output signal SRout(p) output from the shift register circuit 421_p becomes the high potential (second potential VGH), the gate signal GATE<n+2> and the gate signal GATE<n+3> simultaneously change from the low potential (first potential VGL) to the high potential (second potential VGH). As a result, the pixel transistor Tr of the pixel Pix arranged in the Dx direction (first direction) at the (n + 2)-th position in the Dy direction (second direction) and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (first direction) at the (n + 3)-th position in the Dy direction (second direction) are simultaneously turned on.

[0078] Also, in FIG. 8, in the latter half of the two horizontal periods when the output signal SRout(p) output from the shift register circuit 421_p becomes the high potential (second potential VGH), the gate signal GATE<n+2> and the gate signal GATE<n+3> simultaneously change from the high potential (second potential VGH) to the low potential (first potential VGL), and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (first direction) at the (n + 2)-th position in the Dy direction (second direction) and the pixel transistor Tr of the pixel Pix arranged in the Dx direction (first direction) at the (n + 3)-th position in the Dy direction (second direction) are simultaneously turned off.

[0079] As a result, the frame rate can be increased compared to the first example shown in FIG. 7. Specifically, in the driving mode of the second example shown in FIG. 8, the frame rate can be approximately doubled compared to the first example shown in FIG. 7.

[0080] FIG. 9 is a diagram showing an example of the schematic configuration of a display device according to a comparative example. In the configuration of the display device 1a according to the comparative example shown in FIG. 9, the pixel configuration and the gate line SCL <n>The connection mode is the same as the configuration of the display device 1 according to the embodiment shown in FIG. 1.

[0081] In the configuration of the display device 1a according to the comparative example shown in FIG. 9, with respect to the configuration of the display device 1 according to the embodiment shown in FIG. 1, the signal line DTL <m>The connection modes are different. Specifically, in the configuration of the display device 1a according to the comparative example shown in FIG. 9, the signal line DTL <m>is connected to the pixel Pix arranged in the m-th column of each row. As a result, the signal line DTL is connected to the pixel Pix arranged in the m-th column of each row <m>Via, pixel signal SIG <m>is supplied.

[0082] In the configuration of the display device 1a according to the comparative example shown in FIG. 9, when the above-described second driving example is applied, the same pixel signal SIG is applied to pixels Pix that display different colors <m>will be supplied. Specifically, for example, the pixel signal SIG common to both the first pixel PixR in the first row and first column and the third pixel PixB in the first row and second column is supplied. Therefore, in the configuration of the display device 1a according to the comparative example shown in FIG. 9, the above-described second driving example cannot be applied.

[0083] On the other hand, in the configuration of the display device 1 according to the embodiment shown in FIG. 1, as described above, the signal line DTL <m>is connected to the pixel Pix arranged in the (m - 1)-th column of the odd rows and the pixel Pix arranged in the m-th column of the even rows. Thus, as described above, the pixel Pix arranged in the (m - 1)-th column of the odd rows and the pixel Pix arranged in the m-th column of the even rows are connected by the signal line DTL <m>Via a common pixel signal SIG <m>is supplied.

[0084] In the configuration of the display device 1 according to the embodiment shown in FIG. 1, the display color of the pixel Pix arranged in the (m - 1)-th column of odd-numbered rows is the same as the display color of the pixel Pix arranged in the m-th column of even-numbered rows. Therefore, it is possible to apply the second driving example described above. Specifically, in the configuration of the display device 1 according to the embodiment shown in FIG. 1, when the second driving example described above is applied, for example, a common pixel signal SIG is supplied to both the first pixel PixR in the first row and first column and the first pixel PixR in the second row and second column.

[0085] Note that the display device 1 is not limited to a liquid crystal display device, and for example, it may be an organic EL display using an organic light emitting diode (OLED: Organic Light Emitting Diode) as a display element. Also, the display device 1 may be an inorganic EL display using an inorganic light emitting diode (micro LED) as a display element. Further, the display device 1 may be an electrophoretic display (EPD: Electrophoretic Display), or may even be a transparent display that displays an image on a transmissive display surface.

[0086] Also, the display colors of the first pixel PixR, the second pixel PixG, and the third pixel PixB are not limited to red (R), green (G), and blue (B). For example, the display colors of the first pixel PixR, the second pixel PixG, and the third pixel PixB may be cyan (C), magenta (M), and yellow (Y).

[0087] As described above, the preferred embodiments of the present disclosure have been described, but the present disclosure is not limited to such embodiments. The content disclosed in the embodiments is merely an example, and various modifications are possible without departing from the spirit of the present disclosure. Appropriate modifications made without departing from the spirit of the present disclosure also naturally belong to the technical scope of the present disclosure.

Description of Reference Numerals

[0088] 1, 1a Display device 4 Driver IC 11 Display Panel 12 Power Supply Unit 13 Control Unit 40 Drive Circuit 42 Gate Driver 43 Signal Line Selection Circuit 44 Display Control Circuit 421, 421_1, 421_p, 421_P Shift Register Circuit 422, 422_1, 422_p, 422_P Gate Line Driver Circuit AA Display Area Cgs1 First Parasitic Capacitance Cgs2 Second Parasitic Capacitance CKV Shift Clock Signal COML Common Electrode Cs Holding Capacitance DTL Signal Line ENB Enable Signal ENB1 First Enable Signal ENB2 Second Enable Signal ENB3 Third Enable Signal ENB4 Fourth Enable Signal GATE Gate Signal Pix Pixel PX Pixel Electrode Source Video Signal SCL Gate Line SIG Pixel Signal STV Start Pulse Signal Tr Pixel Transistor VCOM Common Potential VGH Second Potential VGL First Potential Vsig Image Signal< / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / n> < / n> < / m> < / n> < / m> < / m> < / n> < / m> < / n> < / m> < / m> < / n> < / m> < / n>

Claims

1. A plurality of pixels arranged in a matrix in a first direction of a display area and a second direction intersecting the first direction, A plurality of gate lines extending in the first direction and arranged in the second direction, A plurality of signal lines extending in the second direction and arranged in the first direction, A driving circuit that supplies a pixel signal to the pixel via the signal line and drives the pixel via the gate line, Comprising, When the total number of pixels arranged in ascending order from the first column to the m-th column (m is a natural number) from one end to the other end in the first direction is M, and the total number of pixels arranged in ascending order from the first row to the n-th row (n is a natural number) from one end to the other end in the second direction is N, The total number of the gate lines is N, and the total number of the signal lines is M + 1, The n-th gate line is connected to the pixels arranged in the n-th row of each column, The m-th signal line is connected to the pixels arranged in the (m - 1)-th column of odd rows and the pixels arranged in the m-th column of even rows, A display device.

2. Pixels of n rows and m columns and pixels of n rows and m + 1 columns display different colors respectively, Pixels of n rows and m columns and pixels of n + 1 rows and m columns display different colors respectively, Pixels of n rows and m columns and pixels of n + 1 rows and m + 1 columns display the same color, The display device according to Claim 1.

3. A plurality of the pixels are, A first pixel that displays a first color, A second pixel that displays a second color different from the first color, A third pixel that displays a third color different from the first color and the second color, Including, The display device according to Claim 2.

4. In ascending order in the first direction, the first pixel, the second pixel, and the third pixel are arranged in this order, In descending order in the second direction, the first pixel, the second pixel, and the third pixel are arranged in this order, The display device according to Claim 3.

5. The first color is red, The second color is green, The third color is blue, The display device according to Claim 4.

6. The driving circuit is, Driving the pixels arranged in ascending order in the second direction sequentially, The display device according to any one of Claims 1 to 5.

7. The driving circuit is, Driving the pixels of odd rows and the pixels of even rows arranged adjacent to each other in ascending order in the second direction simultaneously, The display device according to any one of Claims 1 to 5.

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