Display device

Abstract

To provide a display device of low power consumption.SOLUTION: A display device has an inversion circuit and a pixel having a function of adding data. The inversion circuit has a function of inverting data supplied from a source driver. The pixel has a function of adding data supplied from the source driver and the inversion circuit. Therefore, in the pixel, a voltage being several times an output voltage of the source driver can be generated and supplied to the display device. With this structure, the output voltage of the source driver can be reduced and the display device of low power consumption can be achieved.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification etc. is related to an object, a method, or a manufacturing method. Or, one aspect of the present invention is related to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, more specifically, the technical field of one aspect of the present invention disclosed in this specification includes, as an example, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, storage devices, imaging devices, their operating methods, or their manufacturing methods. can be cited as an example.

[0003] Note that in this specification etc., the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are one aspect of semiconductor devices. Also, storage devices, display devices, imaging devices, and electronic devices may have semiconductor devices.

Background Art

[0004] Techniques for constructing transistors using metal oxides formed on a substrate have attracted attention. For example, techniques for using transistors using zinc oxide or In-Ga-Zn-based oxides as switching elements for pixels of display devices are disclosed in Patent Document 1 and Patent Document 2.

[0005] Also, a storage device configured to use a transistor with an extremely low off-current for a memory cell is disclosed in Patent Document 3.

Prior Art Documents

Patent Document

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0007] Display devices are used in various electronic devices. To reduce the power consumption of electronic devices, low-voltage operation of the display device is one means. device becomes one means.

[0008] The source driver of the display device has a logic section that is fast and has a low drive voltage, and an amplifier section that has a high withstand voltage and outputs a high voltage. The power consumption of the amplifier section, which requires a relatively high power supply voltage, is higher than that of the logic section. is higher than that of the logic section.

[0009] If it is acceptable to reduce the output voltage of the source driver, that is, to reduce the power supply voltage of the amplifier section, the amplifier section can be manufactured using the same technology as the logic section. If it is acceptable to reduce the output voltage of the source driver, that is, to reduce the power supply voltage of the amplifier section, the amplifier section can be manufactured using the same technology as the logic section. By sharing the technologies of the amplifier section and the logic section, the power consumption and manufacturing cost of the source driver can be reduced.

[0010] Also, in the pixel, it is required that the display device operates properly even when the input data is at a low voltage. and is required.

[0011] Therefore, in one aspect of the present invention, one of the objectives is to provide a display device with low power consumption. Or, it is possible to supply a voltage equal to or higher than the output voltage of the source driver to the display device. One of the objectives is to provide a display device that can Another objective is to provide a display device capable of increasing the luminance of the displayed image. Another objective is to provide a display device that operates with a low-cost driver.

[0012] Another objective is to provide a highly reliable display device. Or, one of the objectives is to provide a novel display device or the like. Or, one of the objectives is to provide an operation method of the above display device. Or, one of the objectives is to provide a novel semiconductor device or the like. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

[0013] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. These other problems will naturally become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0014] One aspect of the present invention relates to a display device with low power consumption.

[0015] One aspect of the present invention is a display device having a first circuit, a second circuit, and pixels, The first circuit and the second circuit are electrically connected, the first circuit and the pixels are electrically connected, the second circuit and the pixels are electrically connected, the first circuit has a function of outputting first data to the second circuit, the first circuit has a function of outputting first data to the pixels, and the second ​​The circuit has a function of outputting second data to pixels based on first data, and when the potential of the first data is D1, the potential of the second data is D2, and the reference potential is V0, there is a relationship of V0 = (D1 + D2) / 2. The pixel has a function of generating third data based on the first data and the second data, and a function of performing display according to the third data. When the potential of the first data is D1, the potential of the second data is D2, and the reference potential is V0, there is a relationship of V0 = (D1 + D2) / 2. The pixel has a function of generating third data based on the first data and the second data, and a function of performing display according to the third data. The display device has a function of generating third data based on the first data and the second data, and a function of performing display according to the third data. There is.

[0016] The second circuit can further have a third circuit. The third circuit has a function of selecting an output path. The input terminal of the third circuit is electrically connected to the second circuit, and the output terminal of the third circuit can be electrically connected to the pixel. The second circuit can further have a third circuit. The third circuit has a function of selecting an output path. The input terminal of the third circuit is electrically connected to the second circuit, and the output terminal of the third circuit can be electrically connected to the pixel. The output terminal of the third circuit can be electrically connected to the pixel.

[0017] The pixel has a first transistor, a second transistor, a third transistor, a first capacitor, and a fourth circuit. One electrode of the first capacitor is electrically connected to one of the source or drain of the first transistor. One of the source or drain of the first transistor is electrically connected to the third circuit. The other electrode of the first capacitor is electrically connected to one of the source or drain of the second transistor. One of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor. The other of the source or drain of the first transistor is electrically connected to the other of the source or drain of the second transistor. The other of the source or drain of the second transistor is electrically connected to the second circuit. The other of the source or drain of the second transistor is electrically connected to the first circuit. The other of the source or drain of the third transistor is electrically connected to the second circuit. The fourth circuit is for display. The pixel has a first transistor, a second transistor, a third transistor, a first capacitor, and a fourth circuit. One electrode of the first capacitor is electrically connected to one of the source or drain of the first transistor. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the first transistor. One of the source or drain of the first transistor is electrically connected to the third circuit. The other electrode of the first capacitor is electrically connected to one of the source or drain of the second transistor. One of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor. One of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor. One of the source or drain of the first transistor is electrically connected to the other of the source or drain of the second transistor. One of the source or drain of the first transistor is electrically connected to the other of the source or drain of the second transistor. One of the source or drain of the second transistor is electrically connected to the second circuit. One of the source or drain of the second transistor is electrically connected to the first circuit. One of the source or drain of the third transistor is electrically connected to the second circuit. The fourth circuit is for display. It can have a display device.

[0018] The channel width of the third transistor can be smaller than the channel width of the first transistor and the channel width of the second transistor. It can be made smaller.

[0019] The fourth circuit has a liquid crystal device as a display device, and one electrode of the liquid crystal device can be electrically connected to one of the source or drain of the first transistor. Further, it has a second capacitor, and one electrode of the second capacitor may be electrically connected to one electrode of the liquid crystal device. It can be electrically connected to one of the source or drain of the first transistor. Further, it has a second capacitor, and one electrode of the second capacitor may be electrically connected to one electrode of the liquid crystal device. Further, it has a second capacitor, and one electrode of the second capacitor may be electrically connected to one electrode of the liquid crystal device. It may be electrically connected.

[0020] Alternatively, the fourth circuit has a fourth transistor, a third capacitor, and a light-emitting device as a display device. The gate of the fourth transistor is electrically connected to one of the source or drain of the first transistor. One of the source or drain of the fourth transistor is electrically connected to one electrode of the light-emitting device. One electrode of the light-emitting device is electrically connected to one electrode of the third capacitor. The other electrode of the third capacitor can be electrically connected to the gate of the fourth transistor. The gate of the fourth transistor is electrically connected to one of the source or drain of the first transistor. One of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the first transistor. One of the source or drain of the fourth transistor is electrically connected to one electrode of the light-emitting device. One electrode of the light-emitting device is electrically connected to one electrode of the third capacitor. The other electrode of the third capacitor can be electrically connected to the gate of the fourth transistor.

[0021] The second circuit has a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a fourth capacitor, and a fifth capacitor. One of the source or drain of the fifth transistor is electrically connected to one electrode of the fourth capacitor. One electrode of the fourth capacitor is electrically connected to one of the source or drain of the sixth transistor. The second circuit has a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a fourth capacitor, and a fifth capacitor. One of the source or drain of the fifth transistor is electrically connected to one electrode of the fourth capacitor. One electrode of the fourth capacitor is electrically connected to one of the source or drain of the sixth transistor. One electrode of the fourth capacitor is electrically connected to one of the source or drain of the sixth transistor. The gate of the transistor is electrically connected to the gate of the seventh transistor. One of the source and drain of the transistor is electrically connected to the other electrode of the fourth capacitor. The other electrode of the fourth capacitor is connected to the source or drain of the eighth transistor. The gate of the eighth transistor is electrically connected to the gate of the sixth transistor. The other of the source and drain of the eighth transistor is electrically connected to the ninth transistor. The gate of the ninth transistor is electrically connected to the gate of the fifth capacitor. the other of the source or drain of the ninth transistor is electrically connected to one of the source and drain of the tenth transistor, One of the source and drain of the transistor is electrically connected to the pixel, and the fifth transistor The other of the source or drain of the transistor can be electrically connected to a first circuit.

[0022] The transistors included in the second circuit, the third circuit, and the pixel have a metal oxide in a channel formation region. The metal oxides are In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Z). r, La, Ce, Nd or Hf).

[0023] Another aspect of the present invention is a display device in which a display device is electrically connected to one electrode of a capacitor. A display device having a first data and a second data inverted based on a specific potential. and generating second data by applying the first data to one electrode of the capacitor. A first step of supplying second data to the other electrode of the capacitor; A first data is supplied to the other electrode of the capacitor while the electrode of the capacitor is floating. A method of operating a display device having a second step of performing operations in the above order.

Advantages of the Invention

[0024] By using one aspect of the present invention, a display device with low power consumption can be provided. Or A display device capable of supplying a voltage equal to or higher than the output voltage of the source driver to the display device can be provided. Or, a display device capable of increasing the brightness of a displayed image can be provided . Or, a display device that operates with a low-cost driver can be provided .

[0025] Or, a highly reliable display device can be provided. Or, a novel display device or the like can be provided. Or, a method of operating the above display device can be provided. Also a novel semiconductor device or the like can be provided.

Brief Description of the Drawings

[0026]

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[0027] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various modifications and variations in form and detail may be made without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention should not be construed as being limited to the description of the embodiments. In the configuration, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. The same elements constituting the figures are used throughout the figure, and their repeated explanations may be omitted. Hatching may be omitted or changed as appropriate between different drawings.

[0028] In addition, even if a circuit diagram shows a single element, it may not have any functional problems. If there is no need for a single element, the element may be composed of multiple elements. For example, In some cases, multiple resistors may be connected in series or parallel. In some cases, the signal processing unit 10 may be divided and placed in multiple positions.

[0029] In addition, one conductor may have multiple functions such as wiring, electrodes, and terminals. In this specification, the same element may be referred to by multiple names. Even when it is illustrated on a circuit diagram that elements are directly connected to each other, actually the elements may be connected via a plurality of conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0030] (Embodiment 1) In this embodiment, a display device which is one aspect of the present invention will be described with reference to the drawings.

[0031] One aspect of the present invention is a display device having a circuit (hereinafter referred to as an inversion circuit) having a function of inverting data, and pixels having a function of adding data .

[0032] The inversion circuit has a function of inverting the data supplied from the source driver. Further, the pixel has a function of adding the data supplied from the source driver and the inversion circuit. Thus the pixel can generate a voltage higher than the output voltage of the source driver and supply it to the display device. By using such a configuration, the output voltage of the source driver can be reduced and a display device with low power consumption can be realized.

[0033] In addition, since the inversion circuit can generate positive and negative data potentials, even if the potential that the source driver can output is either positive or negative, it can respond to the positive polarity operation and the negative polarity operation of the liquid crystal device. In this case, the circuit configuration of the source driver can be simplified, so that the chip area can be reduced. Therefore, a display device can be configured with a low-cost source driver.

[0034] Note that the inversion of data means that the absolute value of the difference from the reference potential is the same (or approximately the same), and ​​​It means generating data different from the original data. Let the original data be the first data (D1) , the inverted data be the second data (D2), and the reference potential (for example, the common potential) be V0 . Then, the relationship is V0 = (D1 + D2) / 2. In this embodiment, for ease of understanding , in many explanations, the reference potential is set to 0V, and the absolute values of the first data and the second data are the same , and the expression is that the polarities are opposite, but it is not limited to this. The reference potential can be arbitrarily set according to the design. As long as the above formula is satisfied, the first data and the second data may have the same polarity . Also, the absolute values of the first data and the second data may be different.

[0035] <Display device> FIG. 1 is a diagram for explaining a display device according to an aspect of the present invention. The display device includes a display area 15 having pixels 10 arranged in the column direction and the row direction , a source driver 12, a gate driver 13, and a circuit 11. The source driver 12 is electrically connected to the circuit 11 and the pixels 10. The gate driver 13 is electrically connected to the pixels 10. The circuit 11 is electrically connected to the pixels 10. Note that the source driver 12 and the gate driver 13 may be plural.

[0036] The circuit 11 can be provided, for example, for each column of the pixels 10 and can be electrically connected to the pixels 10 arranged in the same column.

[0037] The circuit 11 is an inversion circuit and has a function of generating an analog potential (second data) obtained by inverting the analog potential (first data) supplied from the source driver 12 .

[0038] Pixel 10 has circuits 20 and 21. Circuit 20 has a function of adding the first data supplied from the source driver 12 and the second data supplied from the circuit 11 by capacitive coupling to generate the third data. Circuit 21 has a display device and has a function of operating the display device according to the third data supplied from circuit 20.

[0039] FIG. 2 is a diagram for explaining the circuit 11 arranged in any one column (the m-th column) of the display device shown in FIG. 1 and the pixels 10 (pixel 10[n,m], pixel 10[n + 1,m] (m, n are natural numbers of 1 or more)) adjacent in the vertical direction (the direction in which the source lines extend).

[0040] <Inversion circuit> FIG. 3 shows an example of the configuration of the circuit 11. The circuit 11 can be configured to include a transistor 111, a transistor 112, a transistor 113, a transistor 114, a transistor 115, a transistor 116, a capacitor 117, and a capacitor 118.

[0041] One of the source or drain of the transistor 111 is electrically connected to one electrode of the capacitor 117. One electrode of the capacitor 117 is electrically connected to one of the source or drain of the transistor 112. One of the source or drain of the transistor 113 is electrically connected to the other electrode of the capacitor 117. The other electrode of the capacitor 117 is electrically connected to one of the source or drain of the transistor 114. The other of the source or drain of the transistor 114 is electrically connected to the gate of the transistor 115. The gate of the transistor 115 is electrically connected to one electrode of the capacitor 118. ​​​​​​​​​​​​It is connected pneumatically. One of the source or drain of transistor 115 is electrically connected to one of the source or drain of transistor 116.

[0042] In this configuration, the other of the source or drain of transistor 111 corresponds to the input terminal and is electrically connected to wiring 127[m_1]. Also, one of the source or drain of transistor 116 corresponds to the output terminal and is electrically connected to wiring 127[m_2]. Note that circuit 11 has an element corresponding to the input terminal and an element corresponding to the output terminal, and as long as it can invert the analog potential input to the input terminal and output it from the output terminal, the above configuration is not limited to the above configuration.

[0043] The gates of transistor 111 and transistor 113 are electrically connected to wiring 128 The gates of transistor 112 and transistor 114 are electrically connected to wiring 129 The other of the source or drain of transistor 112 is electrically connected to wiring 161 The other of the source or drain of transistor 113 is electrically connected to wiring 16 2. The other electrode of capacitor 118 is electrically connected to wiring 163 The other of the source or drain of transistor 115 is electrically connected to wiring 164 The other of the source or drain of transistor 116 is electrically connected to wiring 165 The gate of transistor 116 is electrically connected to wiring 166.

[0044] Wiring 128 and 129 can have the function as a gate line. For example, wiring 12 8 and 129 can be electrically connected to a circuit that controls the operation of circuit 11. Wiring 1 ​61, 162, 163, 164, 165 can have the function as a power line. For example, wirings 161, 163, 165 can be low potential power lines, and wirings 162, 164 can be high potential power lines. Wiring 166 has the function of supplying a fixed potential.

[0045] In addition, as shown in FIG. 4, a configuration in which transistors 112 and tra nsistors 113 are shared by circuits 11 arranged in a plurality of columns may be adopted. In FIG. 4, an example in which transistors 112 and transistors 113 are shared by three or more columns is shown, but a configuration in which they are shared by two columns may also be adopted. In addition, in FIG. 4, transistors 112 and transistors 113 are illustrated outside the frame of circuit 11 However, transistors 112 and transistors 113 are elements shared by each circuit 11 By adopting such a configuration, the number of components of circuit 11 can be reduced, which is effective for narrow bordering.

[0046] <Pixel Circuit> Pixel 10 can have a configuration having a circuit 20 that generates image data and a circuit 21 that performs a display operation.

[0047] Circuit 20 can have a configuration including transistor 101, transistor 102, transistor 103, and ca pacitor 104. One electrode of capacitor 104 is electrically connected to one of the source or drain of transistor 101. One of the source or drain of transistor 1 01 is electrically connected to circuit 21. The other electrode of capacitor 10 4 is electrically connected to one of the source or drain of transistor 102. One of the source or drain of transistor 102 is electrically connected to one of the source of transistor 103 or drain. One of the source or drain of transistor 102 is electrically connected to one of the source or drain of transistor 103. ​

[0048] The circuit 21 may be configured to include a transistor, a capacitive element, a display device, etc., and details will be described later. This is possible, and details will be described later.

[0049] The connection between the elements of each of the circuit 11 and the pixel 10 and various wirings will be described.

[0050] In the pixel 10[n,m], the gate of the transistor 101 is electrically connected to the wiring 126[n]. The gate of the transistor 102 is electrically connected to the wiring 125[n]. The gate of the transistor 103 is electrically connected to the wiring 126[n]. The other of the source or drain of the transistor 101 is electrically connected to the wiring 127[m_1]. The other of the source or drain of the transistor 102 is electrically connected to the wiring 127[m_1]. The other of the source or drain of the transistor 103 is electrically connected to the wiring 127[m_2]. The wirings 125 and 126 can function as gate lines. The wirings 125 and 126 can be electrically connected to the gate driver 13 (see FIG. 1). The wiring 127 (127[m_1], 127[m_2]) can function as a source line. The wiring 127[m_1] can be electrically connected to the output terminal of the source driver 12.

[0051] The connection relationship between the pixel 10 and the wirings 127[m_1] and 127[m_2] is not limited to the above, and a connection relationship in which the wirings 127[m_1] and 127[m_2] are interchanged may also be possible. The wirings 125 and 126 can function as gate lines. The wirings 125 and 126 can be electrically connected to the gate driver 13 (see FIG. 1). The wiring 127 (127[m_1], 127[m_2]) can function as a source line. The wiring 127[m_1] can be electrically connected to the output terminal of the source driver 12. The wirings 125 and 126 can function as gate lines. The wirings 125 and 126 can be electrically connected to the gate driver 13 (see FIG. 1). The wiring 127 (127[m_1], 127[m_2]) can function as a source line. The wiring 127[m_1] can be electrically connected to the output terminal of the source driver 12.

[0052] Note that the connection relationship between the pixel 10 and the wirings 127[m_1] and 127[m_2] is not limited to the above, and a connection relationship in which the wirings 127[m_1] and 127[m_2] are interchanged may also be possible. Note that the connection relationship between the pixel 10 and the wirings 127[m_1] and 127[m_2] is not limited to the above, and a connection relationship in which the wirings 127[m_1] and 127[m_2] are interchanged may also be possible. Note that the connection relationship between the pixel 10 and the wirings 127[m_1] and 127[m_2] is not limited to the above, and a connection relationship in which the wirings 127[m_1] and 127[m_2] are interchanged may also be possible.

[0053] Here, in circuit 11, one of the source or drain of transistor 111, one electrode of capacitor 117, and one of the source or drain of transistor 112 are connected by a wiring which is defined as node NA. One of the source or drain of transistor 113, the other electrode of capacitor 117, and one of the source or drain of transistor 114 are connected by a wiring which is defined as node NB. One of the source or drain of transistor 114, the gate of transistor 115, and one electrode of capacitor 118 are connected by a wiring which is defined as node NC. One of the source or drain of transistor 115, one of the source or drain of transistor 116, and wiring 127[m_2] are connected by a wiring which is defined as node ND. Also, in pixel 10, one electrode of capacitor 104, one of the source or drain of transistor 101, and circuit 21 are connected by a wiring which is defined as node NM. One of the source or drain of transistor 102, one of the source or drain of transistor 103, and the other electrode of capacitor 104 are connected by a wiring which is defined as node NE.

[0054] Node NM can be floating, and the display device included in circuit 21 operates according to the potential of node NM.

[0055] <Explanation of Inversion Operation> In circuit 11, first, “+D” (first data) is written to node NA, and “+V1” (for example, positive power supply potential) is written to node NB. At this time, “+V1 - D1” is held in capacitor 117.

[0056]

[0057] Next, make node NB floating and write “-V1” (for example, negative power supply voltage level) to node NA.

[0058] At this time, let the capacitance value of capacitor 117 be C 117 , and the capacitance value of node NB be C NB . Then , the potential of node NB is “+V1+(C 117 / (C 117 +C NB ))×(-V1 - D1 )”. Here, if the value of C 117 is increased and the value of C NB can be ignored, the potential of node NB becomes “-D1”.

[0059] The potential of node NB is supplied to node NC via a switch (transistor 114) . Also, the potential of node NC is output to node ND via a source follower circuit (transistors 115, 116) . That is, it is possible to output “-D” (the second data), which is the inversion of the “+D” input to node NA at the beginning, to node ND. Note that in the above example, a positive potential was used for the first data, but a negative potential may also be used.

[0060] <Explanation of addition operation (boost operation)> In pixel 10, first, write “+D” (the first data) to node NM and “- D” (the second data) to node NE at overlapping timing. At this time, “+D - (-D) = +2D” is held in capacitor 117. Next, make node NM floating and supply “+D” to node NE.

[0061] At this time, let the capacitance value of capacitor 117 be C 117 , and the capacitance value of node NM be C NM . Then , the potential of node NM is +D1+(C 117 / (C 117 +C NM ))×(+D-(-D) ). Here, if the value of C 117 is increased and the value of C NM can be ignored, the potential of node NM becomes "+D+(+D-(-D))" = "+3D". That is, the third data ("+3D"), which is about three times the potential of the output of the source driver 12, can be supplied to node NM.

[0062] By this action, the voltage supplied from the source driver 12 to drive a general liquid crystal device, a light-emitting device, etc. can be reduced to about 1 / 3 at most. Therefore, the power consumption of the display device can be reduced. Or, even when using a general-purpose driver IC, a high voltage can be generated. For example, a liquid crystal device that requires a high voltage for gradation control, etc. can be driven by a general-purpose driver IC.

[0063] Also, since the power supply voltage of the source driver 12 can be lowered, the power consumption of the source driver can be reduced. Also, the power supply voltages of a plurality of circuits included in the source driver can be made the same, and the plurality of circuits can be manufactured using a common technology. Therefore, the manufacturing process of the source driver can be reduced, and the cost can be reduced.

[0064]

[0065] In one aspect of the present invention, as described above, the inverted data generated by the circuit 11 is supplied to a specific pixel 10 to determine the potential of the node NM. By sequentially performing such an operation for each pixel 10 in the same row, the potential of the node NM of each pixel 10 can be determined. That is, ​ Each pixel 10 can be supplied with different image data.

[0066] Nodes NA, NB, NC, ND, NE, and NM are storage nodes. By turning on the transistors connected to each node, data is transferred to each A data can be written to the node by making the transistor non-conductive. The transistor has an extremely low off-state current. By using a transistor, it is possible to suppress leakage current and to hold the potential of each node for a long time. In the transistor, for example, a metal oxide is formed in a channel formation region. The transistors used in the present invention (hereinafter, referred to as OS transistors) can be used.

[0067] Specifically, transistors 101, 102, 103, 111, 112, 113, 114, It is preferable to use an OS transistor for either or both of 115 and 116. In addition, an OS transistor may be used as an element of the circuit 21. In order to operate within the allowable range, a transistor having a Si channel region ( Hereinafter, a Si transistor may be used. Alternatively, an OS transistor and a Si transistor may be used. The Si transistor may be an amorphous silicon transistor. Transistors with crystalline silicon (microcrystalline silicon, low-temperature polysilicon, single crystal Examples of such transistors include those having GaN (crystalline silicon).

[0068] The semiconductor material used for the OS transistor is preferably a material having an energy gap of 2 eV or more. Alternatively, a metal oxide having a polarization of 2.5 eV or more, more preferably 3 eV or more, can be used. For example, an oxide semiconductor containing indium can be used. For example, CAAC -OS or CAC-OS described later can be used. CAAC-OS is suitable for transistors that value the stability of the atoms that make up the crystal and require high reliability. Also, since CAC-OS exhibits high mobility characteristics, it is suitable for transistors that

[0069] perform high-speed driving. Since the OS transistor has a large energy gap in the semiconductor layer, it can exhibit extremely low off-current characteristics of several yA / μm (current value per μm channel width). Also, the OS transistor has characteristics different from those of Si transistors, such as no occurrence of impact ionization, avalanche breakdown, and short-channel effect, and can form a highly reliable circuit. Also, variations in electrical characteristics due to non-uniform crystallinity, which is a problem in Si transistors, are less likely to occur

[0070] in OS transistors. The semiconductor layer of the OS transistor can be formed as a film represented by an In-M-Zn-based oxide containing, for example, indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). The In-M-Zn-based oxide can be formed, for example, by sputtering, ALD (Atomic layer deposition), or MOCVD (Metal organic chemical vapor deposition). When forming the In-M-Zn-based oxide film by sputtering, the sputtering target

[0071] The atomic ratio of the metal elements preferably satisfies In≥M and Zn≥M. Such a sputtering target preferably has an atomic ratio of metal elements such as In:M:Zn = 1:1:1, In :M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2: 3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn= 5:1:7, In:M:Zn = 5:1:8, etc. Note that the atomic ratio of the semiconductor layer to be formed includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0072] As the semiconductor layer, an oxide semiconductor with a low carrier concentration is used. For example, the semiconductor layer has a carrier concentration of 1×10 / cm 17 or less, preferably 1×10 3 / cm 15 or less, more preferably 1×10 3 / cm or less, still more preferably 1×10 13 / cm 3 or less, even more preferably 1×10 11 / cm 3 or less, and even more preferably less than 1×10 / cm 10 3 -9 3 / cm -9 3

[0073] Note that it is not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. Also, as required In order to obtain the semiconductor characteristics of the transistor, it is preferable to make the carrier concentration, impurity concentration, defect density, atomic number ratio of metal element to oxygen, interatomic distance, density, etc. of the semiconductor layer appropriate.

[0074] In the oxide semiconductor constituting the semiconductor layer, when silicon or carbon, which is one of the Group 14 elements, is contained, oxygen deficiency increases and it becomes n-type. For this reason, the concentration of silicon or carbon in the semiconductor layer (the concentration obtained by secondary ion mass spectrometry) is 2 × 10 18 atom s / cm 3 or less, preferably 2 × 10 17 atoms / cm 3 or less.

[0075] In addition, when an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-current of the transistor may increase. For this reason, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (the concentration obtained by secondary ion mass spectrometry) is 1 × 10 or less, preferably 2 × 10 18 atoms / cm 3 or less, preferably 2 × 10 16 a toms / cm 3 or less.

[0076] In addition, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons as carriers are generated, the carrier concentration increases, and it tends to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer (the concentration obtained by secondary ion mass spectrometry) is preferably 5 × 10 or less. 18 atoms / cm 3 ​​​​​​​​​

[0077] In addition, when the oxide semiconductor constituting the semiconductor layer contains hydrogen, the oxygen that binds to the metal atoms reacts to form water, which may form oxygen vacancies in the oxide semiconductor. When the channel formation region in the oxide semiconductor contains oxygen vacancies, the transistor may have normally-on characteristics. Furthermore, defects with hydrogen incorporated into the oxygen vacancies may function as donors, and electrons that are carriers may be generated. Also, a part of the hydrogen may bind to the oxygen that binds to the metal atoms to generate electrons that are carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics.

[0078] Defects with hydrogen incorporated into the oxygen vacancies may function as donors of the oxide semiconductor. However , it is difficult to quantitatively evaluate such defects. Therefore, in the case of an oxide semiconductor, it may be evaluated by carrier concentration instead of donor concentration. Thus, in this specification and the like, as a parameter of the oxide semiconductor, carrier concentration assuming a state where no electric field is applied may be used instead of donor concentration. That is, the "carrier concentration" described in this specification and the like may sometimes be paraphrased as "donor concentration".

[0079] Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically , in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) is less than 1×10 20 a toms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably​​​ is less than 5×10 18 atoms / cm 3 and more preferably less than 1×10 18 atoms / c m 3 By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0080] In addition, oxide semiconductors (metal oxides) can be divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS ( C-Axis Aligned Crystalline Oxide Semicon ductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS:amorphous-like oxide semiconductor), and amorphous oxide semiconductors. In a non-single crystal structure, the amorphous structure has the highest density of defect energy levels, and CAAC-OS has the lowest density of defect energy levels.

[0081] An oxide semiconductor film with an amorphous structure has, for example, a disordered atomic arrangement and no crystalline components. Or, an oxide film with an amorphous structure has, for example, a completely amorphous structure and no crystalline parts.

[0082] Note that the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC -OS region, and a single crystal structure region. The mixed film may have, for example, a single layer structure or a stacked structure including any two or more of the above-described regions.

[0083] Hereinafter, the configuration of CAC (Cloud-Aligned Composite)-OS, which is one aspect of a non-single-crystalline semiconductor layer, will be described. omposite)-OS will be described.

[0084] CAC-OS refers to, for example, a material composition in which the elements constituting an oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. Hereinafter, in the oxide semiconductor, one or more metal elements are unevenly distributed, and the region having the metal element is in a state of being mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof, and is also referred to as a mosaic state or a patch state. In addition, the oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to these, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included. For example, in In-Ga-Zn oxide, CAC-OS (among CAC-OS, In-Ga-Zn oxide may be particularly referred to as CAC-IGZO) refers to indium oxide (hereinafter, InO (let X1 be a real number greater than 0)), or indium zinc oxide (hereinafter, In Zn

[0085] In addition, the oxide semiconductor preferably contains at least indium. Particularly preferably, it contains indium and zinc. In addition to these, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included. For example, in In-Ga-Zn oxide, CAC-OS (among CAC-OS, In-Ga-Zn oxide may be particularly referred to as CAC-IGZO) refers to indium oxide (hereinafter, InO (let X1 be a real number greater than 0)), or indium zinc oxide (hereinafter, In Zn O may also be included.

[0086] For example, in In-Ga-Zn oxide, CAC-OS (among CAC-OS, In-Ga-Zn oxide may be particularly referred to as CAC-IGZO) refers to indium oxide (hereinafter, InO (X1 is a real number greater than 0)), or indium zinc oxide (hereinafter, In (X1 is a real number greater than 0)), or indium zinc oxide (hereinafter, In X1 (X1 is a real number greater than 0)). (X1 is a real number greater than 0)), or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2(X2, Y2, and Z2 are real numbers greater than 0) Let it be so.) and gallium oxide (hereinafter, GaO X3 (X3 is a real number greater than 0) Let it be .), or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0) Let it be so.) etc., and the material separates into a mosaic pattern and becomes a mosaic-like InO X1 , or In X2 Zn Y2 O Z2 is uniformly distributed in the film configuration (hereinafter, also referred to as cloud-like).

[0087] That is, CAC-OS is a composite oxide semiconductor X3 having a configuration in which a region mainly composed of GaO X2 Zn Y2 O Z2 , or a region mainly composed of InO X1 is mixed. Note that in this specification, for example, the atomic ratio of In to the element M in the first region is greater than the atomic ratio of In to the element M in the second region. The first region is considered to have a higher In concentration compared to the second region.

[0088] Note that IGZO is a common name and refers to a compound composed of In, Ga, Zn, and O in some cases . Representative examples include InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number) and crystalline compounds represented by are listed.

[0089] The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane.

[0090] On the other hand, CAC-OS relates to the material composition of an oxide semiconductor. CAC-OS refers to a structure in which in a material composition containing In, Ga, a, Zn, and O, regions observed as nanoparticle-like regions mainly composed of Ga in part and regions observed as nanoparticle-like regions mainly composed of In in part are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0091] Note that CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, a structure composed of two layers of a film mainly composed of In and a film mainly composed of Ga is not included.

[0092] Note that in some cases, no clear boundary can be observed between the region where GaO X3 is the main component and the region where In X2 Zn Y2 O Z2 or InO X1 is the main component.

[0093] Note that when one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium is included instead of gallium, CAC-OS is partially ​​​​​a region observed as nanoparticles mainly composed of the metal element and a region observed as nanoparticles mainly composed of In in part are randomly dispersed mosaically in a configuration. That is.

[0094] CAC-OS can be formed by a sputtering method, for example, under conditions where the substrate is not intentionally heated. In addition, when forming CAC-OS by a sputtering method, as the film-forming gas one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas may be used. Further, the lower the flow rate ratio of oxygen gas to the total flow rate of the film-forming gas during film formation, the more preferable it is. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0095] CAC-OS has the characteristic that no distinct peak is observed when measured using the θ / 2θ scan by the Out-of-plane method, which is a type of X-ray diffraction (XRD: X-ray diffraction) measurement method. That is, it can be seen from the X-ray diffraction measurement that there is no orientation in the a-b plane direction and the c-axis direction of the measurement region.

[0096] In addition, in the electron diffraction pattern obtained by irradiating CAC-OS with an electron beam having a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high luminance in a ring shape (ring region) and a plurality of bright spots are observed in the ring region. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has a non-oriented nc (nano-crystal) structure in the plane direction and the cross-sectional direction.

[0097] ​​​​​​​Also, for example, in CAC-OS in In-Ga-Zn oxide, by means of EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), regions where GaO is the main component and regions where In Zn X3 O or InO X2 is the main component are unevenly distributed and have a mixed Y2 structure. It can be confirmed that CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed and has properties different from those of an IGZO compound. That is, CAC-OS has a structure in which regions where components such as GaO Z2 are the main components and regions where In X1 Zn O

[0098] or InO are the main components are phase-separated from each other and regions with each element as the main component have a mosaic-like structure. Here, regions where In X3 Zn O X2 or InO Y2 is the main component are regions with higher conductivity compared to regions where components such as GaO Z2 are the main components. That is, conductivity as an oxide semiconductor is exhibited in regions where In X1 Zn 2O

[0099] or InO X2 is the main component due to the flow of carriers. Therefore, regions where In Y2 Zn Z2 O X1 or InO X3 is the main component are regions with higher conductivity compared to regions where components such as GaO X2 are the main components. That is, conductivity as an oxide semiconductor is exhibited in regions where In Y 2O Z2 or InO X1 is the main component due to the flow of carriers. Therefore, regions where In Zn X2 O Y2 or In Z2 O is the main component are regions with higher conductivity compared to regions where components such as GaO X1Regions where [substance] is the main component are distributed in a cloud shape in the oxide semiconductor, resulting in a high electric field Effective mobility (μ) can be achieved.

[0100] On the other hand, regions where GaO X3 etc. are the main components have higher insulation compared to regions where In X2 Zn Y2 O Z2 or InO X 1 is the main component. That is, when regions where GaO X3 etc. are distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0101] Therefore, when CAC-OS is used in a semiconductor device, the insulation X3 caused by GaO and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 complementarily act to achieve a high on-current (I on ) and a high field-effect mobility (μ). This can be achieved.

[0102] In addition, a semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0103] Note that, as shown in FIG. 5A, in one aspect of the display device of the present invention, circuit 11 may be incorporated into source driver 1 2. Alternatively, it may have a stack structure in which regions where source driver 12 and circuit 11 overlap exist. With this configuration, narrow bezelization becomes possible. Note that an external IC chip can be used for source driver 12. Alternatively, it can be formed on the substrate It may be integrated with the prime circuit.

[0104] In addition, in FIG. 1, an example of providing the circuit 11 for each column is shown. However, as shown in FIG. 5B, a selection circuit 16 is provided between the source driver 12 and the pixel 10, and a selection circuit 17 may be provided between the circuit 11 and the pixel 10. With such a configuration, data writing to pixels in a plurality of columns can be performed by one circuit 11. Also, the number of circuits 11 can be reduced, and narrow border formation becomes possible. Note that in FIG. 5B, an example of writing to pixels 10 for three columns (pixels [m] to [m + 2]) by one circuit 11 is shown. However, the present invention is not limited to this, and the number of columns may be determined within a range where the writing time is allowed.

[0105] In addition, as shown in FIG. 5C, the configuration of FIG. 5B may be modified to supply data to the circuit 11 via the selection circuit 18. Note that the configuration of FIG. 5A may be applied to the configurations of FIGS. 5B and 5C.

[0106] Since the transistors 111 to 116 included in the circuit 11 are provided outside the display area 15 (see FIG. 1), they are less restricted by the occupation area of the transistors, and it is easy to make the channel width larger than that of the transistors provided in the pixel 10. By using transistors with a large channel width, the charge and discharge time for the wiring 127 can be shortened, and it becomes easy to increase the frame frequency. Also, it becomes easy to apply to high-definition displays with a large number of pixels and a short horizontal period.

[0107] In addition, by using OS transistors for the transistors 111 to 116, the reliability of the circuit 11 can be improved, and stable operation can be performed even at a relatively high voltage. Also, the t​​​​​​​​​ When the transistors 111 to 116 are Si transistors provided in the IC chip, faster operation can be achieved. Even when the transistors 111 to 1 16 are provided in the IC chip, the transistors may be OS transistors.

[0108] <Modification Example of Display Device> The source driver 12 and the circuit 11 may be provided not only on one end side of the display area 1 5 but also on the opposite other end side as shown in FIGS. 6A, 6B, and 6C.

[0109] Here, the circuit 11 provided on one end side of the display area 15 is the circuit 11A. The circuit 11A is electrically connected to the source driver 12A. Also, the circuit 11 provided on the other end side of the display area 15 is the circuit 11B. The circuit 11B is electrically connected to the source driver 12B. Continued.

[0110] With such a configuration, the wirings 127[1] and 127[2] can be charged and discharged at high speed, making it easier to handle display devices with a large number of pixels and a short horizontal period, large-sized display devices with a large parasitic capacitance of the wiring 127, etc.

[0111] Alternatively, as shown in FIG. 6B, the source driver 12A and the circuit 11A are electrically connected to the pixels 10[1] to 10[x] (x is a natural number of 2 or more, such as, for example, the approximate median value of a row), and the source driver 12B and the circuit 11B may be electrically connected to the pixels 10[x + 1] to 10[y] (y is the final value of the row). 12B and the circuit 11B may be electrically connected.

[0112] The source driver 12A and the circuit 11A charge and discharge the wirings 127[1a] and 127[2a], The source driver 12B and the circuit 11B are connected to the wiring 127[1b] and 127[2b]. By dividing the wiring 127 in this way, the wiring 127 can be charged and discharged at high speed. This makes it easier to support high-speed driving.

[0113] As shown in FIG. 6C, multiple gate drivers (gate drivers 13A and 13B) By using multiple source drivers and multiple gate drivers, Since the wirings 127 connected to each other can be charged and discharged in parallel, This makes it easier to secure space.

[0114] 6B and 6C show a configuration for performing so-called division driving, and are used for displays with a large number of pixels and a short horizontal period. This makes it easier to write data even to a display device.

[0115] <Example of inverter circuit operation> Next, using the timing chart shown in FIG. 7 and the explanatory diagrams of the circuit operation shown in FIGS. 8A and 8B, Next, the inversion operation in the circuit 11 will be described in detail.

[0116] In the following description, high potential is represented by "H" and low potential is represented by "L". The first data supplied from the driver 12 is “+D”, and the negative power supply supplied from the wiring 161 is “+V”. The potential is "-V1", and the positive power supply potential supplied from the wiring 162 is "+V1". "+D[n]" is the pixel data in the nth row, and "+D[n+1]" is the pixel data in the n+1th row. It means ta.

[0117] In addition, in the distribution, coupling, or loss of potential, the circuit configuration, operation timing, etc. Detailed changes due to capacitive coupling using a capacitor are not taken into account. Although the capacitance ratio of the capacitor to the connected element depends on the capacitance ratio of the capacitor, for the sake of clarity, Therefore, the capacitance value of the element is assumed to be sufficiently small.

[0118] At time T1, “+D[n]” is supplied to the wiring 127[m_1], and the potential of the wiring 128 is set to “H”. When the potential of the wiring 129[n] is set to “L”, the transistors 111 and 113 are turned on. The potential of node NA becomes “+D[n]”, and the potential of node NB becomes “+V1” (see FIG. 8A). At this time, the capacitor 117 holds "+V1-D[n]".

[0119] At time T2, when the potential of the wiring 128 is set to "L" and the potential of the wiring 129 is set to "H", the transistor The transistors 111 and 113 are non-conductive, and the transistors 112 and 114 are conductive. The potential of the node NA becomes "-V1", and the potential of the node NB becomes "-V2" due to the capacitive coupling of the capacitor 117. The electric potential is “+V1+(-V1-D[n])”=”-D[n]”.

[0120] In addition, the potential of the node NC becomes “−D[n]” through the transistor 114. The potential of C is supplied to a source follower circuit formed by a transistor 115 and a transistor 116. That is, the circuit 11 reads out the signal from the wiring 127[m_1] to the node ND. The inverted “+D[n]” (first data) input from the ) can be output to wiring 127[m_2] (see FIG. 8B).

[0121] At time T3, when the potential of the wiring 128 is set to "L" and the potential of the wiring 129 is set to "L", the transistor The capacitors 112 and 114 are non-conductive, and the potential of the node NC is maintained. The “-D[n]” output to 7[m_2] is retained.

[0122] At times T4 to T6, “+D[n + 1]” is supplied to wiring 127[m_1], and an operation is performed to generate the inverted data “-D[n + 1]”. As described above, circuit 11 can generate the inverted data of the input data. As described above, circuit 11 can generate the inverted data of the input data. -D[n + 1]”. As described above, circuit 11 can generate the inverted data of the input data.

[0123] <Operation Example of Pixel Circuit> Next, a method of supplying a data potential approximately three times the data potential output by source driver 12 to the display device of pixel 10 will be described using the timing chart shown in FIG. 9 and the circuit operation explanatory diagrams shown in FIGS. 10A and 10B. Note that the description of the generation operation of the second data supplied to pixel 10 is omitted. Next, a method of supplying a data potential approximately three times the data potential output by source driver 12 to the display device of pixel 10 will be described using the timing chart shown in FIG. 9 and the circuit operation explanatory diagrams shown in FIGS. 10A and 10B. Note that the description of the generation operation of the second data supplied to pixel 10 is omitted. Next, a method of supplying a data potential approximately three times the data potential output by source driver 12 to the display device of pixel 10 will be described using the timing chart shown in FIG. 9 and the circuit operation explanatory diagrams shown in FIGS. 10A and 10B. Note that the description of the generation operation of the second data supplied to pixel 10 is omitted. Next, a method of supplying a data potential approximately three times the data potential output by source driver 12 to the display device of pixel 10 will be described using the timing chart shown in FIG. 9 and the circuit operation explanatory diagrams shown in FIGS. 10A and 10B. Note that the description of the generation operation of the second data supplied to pixel 10 is omitted.

[0124] At time T1, when “+D[n]” is supplied to wiring 127[m,1] and “-D[n]” is supplied to wiring 127[m,2], and the potential of wiring 125[n] is set to “L” and the potential of wiring 126[n] is set to “H”, transistors 101 and 103 conduct, the potential of node NM becomes “+D[n]”, and the potential of node NE becomes “-D[n]”. At this time, “+2D[n]” is held in capacitor 104 (see FIG. 10A). At time T1, when “+D[n]” is supplied to wiring 127[m,1] and “-D[n]” is supplied to wiring 127[m,2], and the potential of wiring 125[n] is set to “L” and the potential of wiring 126[n] is set to “H”, transistors 101 and 103 conduct, the potential of node NM becomes “+D[n]”, and the potential of node NE becomes “-D[n]”. At this time, “+2D[n]” is held in capacitor 104 (see FIG. 10A). At time T1, when “+D[n]” is supplied to wiring 127[m,1] and “-D[n]” is supplied to wiring 127[m,2], and the potential of wiring 125[n] is set to “L” and the potential of wiring 126[n] is set to “H”, transistors 101 and 103 conduct, the potential of node NM becomes “+D[n]”, and the potential of node NE becomes “-D[n]”. At this time, “+2D[n]” is held in capacitor 104 (see FIG. 10A). At time T1, when “+D[n]” is supplied to wiring 127[m,1] and “-D[n]” is supplied to wiring 127[m,2], and the potential of wiring 125[n] is set to “L” and the potential of wiring 126[n] is set to “H”, transistors 101 and 103 conduct, the potential of node NM becomes “+D[n]”, and the potential of node NE becomes “-D[n]”. At this time, “+2D[n]” is held in capacitor 104 (see FIG. 10A). At time T1, when “+D[n]” is supplied to wiring 127[m,1] and “-D[n]” is supplied to wiring 127[m,2], and the potential of wiring 125[n] is set to “L” and the potential of wiring 126[n] is set to “H”, transistors 101 and 103 conduct, the potential of node NM becomes “+D[n]”, and the potential of node NE becomes “-D[n]”. At this time, “+2D[n]” is held in capacitor 104 (see FIG. 10A).

[0125] At time T2, when the potential of wiring 125[n] is set to “H” and the potential of wiring 126[n] is set to “L”, transistor 101 becomes non-conductive and node NM becomes floating. Also, transistor 103 becomes non-conductive and transistor 102 becomes conductive, and the potential of node NE is rewritten from “-D[n]” to “+D[n]”. The change amount is added to the potential of node NM according to the capacitance ratio between capacitor 104 and node NM, and the potential of node NM becomes “+D[n]+( At time T2, when the potential of wiring 125[n] is set to “H” and the potential of wiring 126[n] is set to “L”, transistor 101 becomes non-conductive and node NM becomes floating. Also, transistor 103 becomes non-conductive and transistor 102 becomes conductive, and the potential of node NE is rewritten from “-D[n]” to “+D[n]”. The change amount is added to the potential of node NM according to the capacitance ratio between capacitor 104 and node NM, and the potential of node NM becomes “+D[n]+( At time T2, when the potential of wiring 125[n] is set to “H” and the potential of wiring 126[n] is set to “L”, transistor 101 becomes non-conductive and node NM becomes floating. Also, transistor 103 becomes non-conductive and transistor 102 becomes conductive, and the potential of node NE is rewritten from “-D[n]” to “+D[n]”. The change amount is added to the potential of node NM according to the capacitance ratio between capacitor 104 and node NM, and the potential of node NM becomes “+D[n]+( n]” from “+D[n]”. The change amount is added to the potential of node NM according to the capacitance ratio between capacitor 104 and node NM, and the potential of node NM becomes “+D[n]+( n]” from “+D[n]”. The change amount is added to the potential of node NM according to the capacitance ratio between capacitor 104 and node NM, and the potential of node NM becomes “+D[n]+( “+D[n] - (-D[n]))” becomes “+3D[n]” (see Fig. 10B).

[0126] When the potential of wiring 125[n] is set to “L” and the potential of wiring 126[n] is set to “L” at time T3 the transistor 102 becomes non - conductive, and the potentials of node NE and node NM are held .

[0127] At times T4 to T6, “+D[n + 1]” is supplied to wiring 127[m,1] and “-D[n + 1]” is supplied to wiring 127[m, 2], and the same operation as above is performed to carry out the writing operation of pixel [n + 1,m].

[0128] By the operation described above, in pixel 10, a voltage approximately three times the voltage supplied from source driver 12 can be supplied to the display device.

[0129] <Modification Example 1> The configuration shown in Fig. 11A is a configuration in which the connection relationship between pixel 10 and two source lines is interchanged . The other of the source or drain of transistor 103 is electrically connected to wiring 127[m_1]. The other of the source or drain of transistor 101 and the other of the source or drain of transistor 102 are electrically connected to wiring 127[m_2]. .

[0130] In the writing operation of pixel 10 having the configuration shown in Fig. 2, the first data supplied from source driver 12 and the second data supplied from circuit 11 are written simultaneously in the first operation, and the first data is written again in the second operation . In this case, since it is necessary to maintain the output of the first data until the second operation, there is a period during which circuit 11 waits.

[0131] ​​​​On the other hand, in the writing operation of the pixel 10 configured as shown in FIG. 11A, in the first operation, the first data and the second data are written simultaneously, and in the second operation, the second data is written. In this configuration, as shown in the timing chart of FIG. 11B, the writing time of data for the pixels in n rows and the generation period of inverted data for the pixels in n + 1 rows in the circuit 11 can be overlapped. Therefore, even when the number of pixels is large and the horizontal period is short, sufficient writing time can be ensured. Conversely, writing can be performed even when the horizontal period is shortened. In the first operation, the first data and the second data are written simultaneously, and in the second operation, the second data is written. In this configuration, as shown in the timing chart of FIG. 11B, the writing time of data for the pixels in n rows and the generation period of inverted data for the pixels in n + 1 rows in the circuit 11 can be overlapped. Therefore, even when the number of pixels is large and the horizontal period is short, sufficient writing time can be ensured. Conversely, writing can be performed even when the horizontal period is shortened. In the writing operation of the pixel 10 configured as shown in FIG. 11A, in the first operation, the first data and the second data are written simultaneously, and in the second operation, the second data is written. In this configuration, as shown in the timing chart of FIG. 11B, the writing time of data for the pixels in n rows and the generation period of inverted data for the pixels in n + 1 rows in the circuit 11 can be overlapped. Therefore, even when the number of pixels is large and the horizontal period is short, sufficient writing time can be ensured. Conversely, writing can be performed even when the horizontal period is shortened.

[0132] <Modification 2> FIG. 12 shows a configuration in which a selection circuit 19 is provided between the source driver 12, the circuit 11, and the pixel 10. The selection circuit 19 can be configured to include a transistor 131, a transistor 132, a transistor 133, and a transistor 134. One of the source or drain of the transistor 131 is electrically connected to one of the source or drain of the transistor 133. The other of the source or drain of the transistor 133 is electrically connected to one of the source or drain of the transistor 132. The other of the source or drain of the transistor 132 is electrically connected to one of the source or drain of the transistor 134. The other of the source or drain of the transistor 134 is electrically connected to the other of the source or drain of the transistor 131.

[0133] One of the source or drain of the transistor 131 is electrically connected to one of the source or drain of the transistor 133. The other of the source or drain of the transistor 133 is electrically connected to one of the source or drain of the transistor 132. The other of the source or drain of the transistor 132 is electrically connected to one of the source or drain of the transistor 134. The other of the source or drain of the transistor 134 is electrically connected to the other of the source or drain of the transistor 131. One of the source or drain of the transistor 131 is electrically connected to one of the source or drain of the transistor 133. The other of the source or drain of the transistor 133 is electrically connected to one of the source or drain of the transistor 132. The other of the source or drain of the transistor 132 is electrically connected to one of the source or drain of the transistor 134. The other of the source or drain of the transistor 134 is electrically connected to the other of the source or drain of the transistor 131. One of the source or drain of the transistor 131 is electrically connected to one of the source or drain of the transistor 133. The other of the source or drain of the transistor 133 is electrically connected to one of the source or drain of the transistor 132. The other of the source or drain of the transistor 132 is electrically connected to one of the source or drain of the transistor 134. The other of the source or drain of the transistor 134 is electrically connected to the other of the source or drain of the transistor 131. One of the source or drain of the transistor 131 is electrically connected to one of the source or drain of the transistor 133. The other of the source or drain of the transistor 133 is electrically connected to one of the source or drain of the transistor 132. The other of the source or drain of the transistor 132 is electrically connected to one of the source or drain of the transistor 134. The other of the source or drain of the transistor 134 is electrically connected to the other of the source or drain of the transistor 131.

[0134] One of the source or drain of the transistor 131 is electrically connected to the wiring 127[m_1a]. The wiring 127[m_1a] is electrically connected to the output terminal of the source driver 12. The wiring 127[m_1a] is electrically connected to the output terminal of the source driver 12. This continues. The other of the source or drain of transistor 132 is electrically connected to wiring 127[m_2a . Wiring 127[m_2a] is electrically connected to the output terminal of circuit 11 This continues.

[0135] By turning on transistors 131 and 132 of selection circuit 19 and turning off transistors 133 and 134, data “+D” output to wiring 127[m_1a] as shown in FIG. 13A can be output to wiring 127[m_1b], and data “-D” output to wiring 127[m_2a] can be output to wiring 127[m_2b].

[0136] Alternatively, by turning off transistors 131 and 132 and turning on transistors 133 and 134, data “+D” output to wiring 127[m_1a] as shown in FIG. 13B can be output to wiring 127[m_2b], and data “-D” output to wiring 127[m_1b] can be output to wiring 127[m_2a].

[0137] The above operation is effective for the inversion operation (positive polarity operation and negative polarity operation) of the liquid crystal device. Note that since circuit 11 can generate inverted data, the potential that the source driver can output may be either positive or negative. Therefore, a source driver with a simplified function can be used. Since a source driver with a simplified function can simplify the circuit configuration, the manufacturing cost and chip area can be reduced. Therefore, the cost of the display device can also be reduced.

[0138] <Modification Example 3> Source driver 12 can output first data and second data which is the inverted data thereof. ​​​​​​​​​​When it has the function, the configuration may be such that the circuit 11 is omitted as shown in FIG. 14. Note that the above-described Modification Examples 1 to 3 can be combined with each other.

[0139] <Circuit 21> FIGS. 15A to 15D are examples of configurations applicable to the circuit 21 and including a liquid crystal device as a display device. The configuration shown in FIG. 15A has a capacitor 141 and a liquid crystal device 142. One electrode of the liquid crystal device 142 is electrically connected to one electrode of the capacitor 141. One electrode of the capacitor 141 is electrically connected to the node NM.

[0140] The other electrode of the capacitor 141 is electrically connected to the wiring 151. The other electrode of the liquid crystal device 142 is electrically connected to the wiring 152. The wirings 151 and 152 have a function of supplying power. For example, the wirings 151 and 152 can supply a reference potential such as GND or 0V or an arbitrary potential.

[0141]

[0142] Note that the configuration may be such that the capacitor 141 is omitted as shown in FIG. 15B. As described above, an OS transistor can be used for the transistor connected to the node NM. Since the OS transistor has an extremely small leakage current, the display can be maintained for a relatively long time even if the capacitor 141 that functions as a holding capacitor is omitted. Also, regardless of the configuration of the transistor, when the display period can be shortened by high-speed operation such as field sequential driving, it is also effective to omit the capacitor 141. By omitting the capacitor 141, the aperture ratio can be improved. Or, the transmittance of the pixel can be improved. ​​​​​​​​​​​​

[0143] In the configurations of FIGS. 15A and 15B, when the potential of node NM becomes equal to or higher than the operating threshold of liquid crystal device 142, the operation of liquid crystal device 142 starts. Therefore, the display operation may start before the potential of node NM is determined. However, in the case of a transmissive liquid crystal display device, operations such as turning off the backlight are also used until the potential of node NM is determined, so that visual recognition can be suppressed even if an unnecessary display operation is performed. In the above, when the potential of node NM becomes equal to or higher than the operating threshold of liquid crystal device 142, the operation of liquid crystal device 142 starts. Therefore, the display operation may start before the potential of node NM is determined. However, in the case of a transmissive liquid crystal display device, operations such as turning off the backlight are also used until the potential of node NM is determined, so that visual recognition can be suppressed even if an unnecessary display operation is performed. In the above, when the potential of node NM becomes equal to or higher than the operating threshold of liquid crystal device 142, the operation of liquid crystal device 142 starts. Therefore, the display operation may start before the potential of node NM is determined. However, in the case of a transmissive liquid crystal display device, operations such as turning off the backlight are also used until the potential of node NM is determined, so that visual recognition can be suppressed even if an unnecessary display operation is performed. In the above, when the potential of node NM becomes equal to or higher than the operating threshold of liquid crystal device 142, the operation of liquid crystal device 142 starts. Therefore, the display operation may start before the potential of node NM is determined. However, in the case of a transmissive liquid crystal display device, operations such as turning off the backlight are also used until the potential of node NM is determined, so that visual recognition can be suppressed even if an unnecessary display operation is performed. In the above, when the potential of node NM becomes equal to or higher than the operating threshold of liquid crystal device 142, the operation of liquid crystal device 142 starts. Therefore, the display operation may start before the potential of node NM is determined. However, in the case of a transmissive liquid crystal display device, operations such as turning off the backlight are also used until the potential of node NM is determined, so that visual recognition can be suppressed even if an unnecessary display operation is performed.

[0144] FIG. 15C shows a configuration in which transistor 143 is added to the configuration of FIG. 15A. One of the source or drain of transistor 143 is electrically connected to one electrode of capacitor 141. The other of the source or drain of transistor 143 is electrically connected to node NM. In the above, when the potential of node NM becomes equal to or higher than the operating threshold of liquid crystal device 142, the operation of liquid crystal device 142 starts. Therefore, the display operation may start before the potential of node NM is determined. However, in the case of a transmissive liquid crystal display device, operations such as turning off the backlight are also used until the potential of node NM is determined, so that visual recognition can be suppressed even if an unnecessary display operation is performed. In the above, when the potential of node NM becomes equal to or higher than the operating threshold of liquid crystal device 142, the operation of liquid crystal device 142 starts. Therefore, the display operation may start before the potential of node NM is determined. However, in the case of a transmissive liquid crystal display device, operations such as turning off the backlight are also used until the potential of node NM is determined, so that visual recognition can be suppressed even if an unnecessary display operation is performed. In the above, when the potential of node NM becomes equal to or higher than the operating threshold of liquid crystal device 142, the operation of liquid crystal device 142 starts. Therefore, the display operation may start before the potential of node NM is determined. However, in the case of a transmissive liquid crystal display device, operations such as turning off the backlight are also used until the potential of node NM is determined, so that visual recognition can be suppressed even if an unnecessary display operation is performed.

[0145] In this configuration, the potential of node NM is applied to liquid crystal device 142 as transistor 143 conducts. Therefore, the operation of liquid crystal device 142 can be started at an arbitrary timing after the potential of node NM is determined. In this configuration, the potential of node NM is applied to liquid crystal device 142 as transistor 143 conducts. Therefore, the operation of liquid crystal device 142 can be started at an arbitrary timing after the potential of node NM is determined. In this configuration, the potential of node NM is applied to liquid crystal device 142 as transistor 143 conducts. Therefore, the operation of liquid crystal device 142 can be started at an arbitrary timing after the potential of node NM is determined.

[0146] FIG. 15D shows a configuration in which transistor 144 is added to the configuration of FIG. 15C. One of the source or drain of transistor 144 is electrically connected to one electrode of liquid crystal device 142. The other of the source or drain of transistor 144 is electrically connected to wiring 153. In the above, when the potential of node NM becomes equal to or higher than the operating threshold of liquid crystal device 142, the operation of liquid crystal device 142 starts. Therefore, the display operation may start before the potential of node NM is determined. However, in the case of a transmissive liquid crystal display device, operations such as turning off the backlight are also used until the potential of node NM is determined, so that visual recognition can be suppressed even if an unnecessary display operation is performed. In the above, when the potential of node NM becomes equal to or higher than the operating threshold of liquid crystal device 142, the operation of liquid crystal device 142 starts. Therefore, the display operation may start before the potential of node NM is determined. However, in the case of a transmissive liquid crystal display device, operations such as turning off the backlight are also used until the potential of node NM is determined, so that visual recognition can be suppressed even if an unnecessary display operation is performed. In the above, when the potential of node NM becomes equal to or higher than the operating threshold of liquid crystal device 142, the operation of liquid crystal device 142 starts. Therefore, the display operation may start before the potential of node NM is determined. However, in the case of a transmissive liquid crystal display device, operations such as turning off the backlight are also used until the potential of node NM is determined, so that visual recognition can be suppressed even if an unnecessary display operation is performed.

[0147] Circuit 170 electrically connected to wiring 153 can have a function of resetting the potentials supplied to capacitor 141 and liquid crystal device 142. Circuit 170 electrically connected to wiring 153 can have a function of resetting the potentials supplied to capacitor 141 and liquid crystal device 142.

[0148] Figures 16A to 16D are applicable to circuit 21 and include a light-emitting device as a display device. It is an example of a configuration.

[0149] The configuration shown in FIG. 16A includes transistor 145, capacitor 146, and light-emitting device 14 7. One of the source or drain of transistor 145 is electrically connected to one electrode of light-emitting device 147 One electrode of light-emitting device 147 is electrically connected to one electrode of capacitor 1 46. The other electrode of capacitor 146 is electrically connected to the gate of transistor 14 5. The gate of transistor 145 is electrically connected to node NM electrically.

[0150] The other of the source or drain of transistor 145 is electrically connected to wiring 154 . The other electrode of light-emitting device 147 is electrically connected to wiring 155. Wiring 154, 155 has the function of supplying power. For example, wiring 154 can supply a high-potential power supply and. Also, wiring 155 can supply a low-potential power supply.

[0151] In the configuration shown in FIG. 16A, when the potential of node NM becomes equal to or higher than the threshold voltage of transistor 111, current flows through light-emitting device 147.

[0152] Alternatively, as shown in FIG. 16B, one electrode of light-emitting device 147 can be electrically connected to wiring 154, and the other electrode of light-emitting device 147 can be electrically connected to the other of the source or drain of transistor 145. This configuration can also be applied to other circuits 21 having light-emitting device 147.

[0153] ​​Figure 16C shows a configuration in which transistor 148 is added to the configuration of Figure 16A. One of the source or drain of transistor 148 is electrically connected to one of the source or drain of transistor 145. The other of the source or drain of transistor 148 is electrically connected to one of the electrodes of the light-emitting device 147.

[0154] In this configuration, when the potential of node NM is equal to or higher than the threshold voltage of transistor 111 and transistor 148 conducts, current flows through the light-emitting device 147. Therefore, the light emission of the light-emitting device 147 can be started at any timing after the potential of node NM is determined.

[0155] Figure 16D shows a configuration in which transistor 149 is added to the configuration of Figure 16A. One of the source or drain of transistor 149 is electrically connected to one of the source or drain of transistor 145. The other of the source or drain of transistor 149 is electrically connected to the wiring 156.

[0156] The wiring 156 can be electrically connected to a source of a specific potential such as a reference potential. By supplying a specific potential from the wiring 156 to one of the source or drain of transistor 145, the writing of image data can be stabilized. Also, the timing of the light emission of the light-emitting device 147 can be controlled.

[0157] In addition, the wiring 156 can be connected to the circuit 171 and can also function as a monitor line. The circuit 171 can have one or more of the functions of serving as a source of the specific potential, obtaining the electrical characteristics of transistor 145, and generating correction data. ​ It is possible.

[0158] <Modified Example of Transistor> Also, as illustrated in FIG. 17A, in the circuit of one aspect of the present invention, a transistor with a back gate may be used. In FIG. 17A, a configuration is shown in which the back gate is electrically connected to the front gate, and it has the effect of increasing the on-current. Alternatively, a configuration in which the back gate is electrically connected to a wiring capable of supplying a fixed potential may be used. In this configuration, the threshold voltage of the transistor can be controlled. Note that a back gate may also be provided for the transistors included in circuit 11 and circuit 21. Also, as illustrated in FIG. 17A, in the circuit of one aspect of the present invention, a transistor with a back gate may be used. In FIG. 17A, a configuration is shown in which the back gate is electrically connected to the front gate, and it has the effect of increasing the on-current. Alternatively, a configuration in which the back gate is electrically connected to a wiring capable of supplying a fixed potential may be used. In this configuration, the threshold voltage of the transistor can be controlled. Note that a back gate may also be provided for the transistors included in circuit 11 and circuit 21. Also, as illustrated in FIG. 17A, in the circuit of one aspect of the present invention, a transistor with a back gate may be used. In FIG. 17A, a configuration is shown in which the back gate is electrically connected to the front gate, and it has the effect of increasing the on-current. Alternatively, a configuration in which the back gate is electrically connected to a wiring capable of supplying a fixed potential may be used. In this configuration, the threshold voltage of the transistor can be controlled. Note that a back gate may also be provided for the transistors included in circuit 11 and circuit 21. Also, as illustrated in FIG. 17A, in the circuit of one aspect of the present invention, a transistor with a back gate may be used. In FIG. 17A, a configuration is shown in which the back gate is electrically connected to the front gate, and it has the effect of increasing the on-current. Alternatively, a configuration in which the back gate is electrically connected to a wiring capable of supplying a fixed potential may be used. In this configuration, the threshold voltage of the transistor can be controlled. Note that a back gate may also be provided for the transistors included in circuit 11 and circuit 21. Also, as illustrated in FIG. 17A, in the circuit of one aspect of the present invention, a transistor with a back gate may be used. In FIG. 17A, a configuration is shown in which the back gate is electrically connected to the front gate, and it has the effect of increasing the on-current. Alternatively, a configuration in which the back gate is electrically connected to a wiring capable of supplying a fixed potential may be used. In this configuration, the threshold voltage of the transistor can be controlled. Note that a back gate may also be provided for the transistors included in circuit 11 and circuit 21. Also, a back gate may be provided for the transistors included in circuit 11 and circuit 21.

[0159] Also, in pixel 10, transistors 101 and 102 play a role of quickly charging and discharging capacitor 104 having a relatively large capacitance value. Transistor 103 plays a role of charging the combined capacitance C of capacitor 104 and circuit 21. The combined capacitance C is C ×(C / (C1 +C 104 )) when the capacitance value of capacitor 104 is C 21 and the capacitance value of circuit 21 is C 104 and becomes a value smaller than C 21 / (C1 04 +C 21 ). 104 Therefore, as shown in the conceptual diagram of FIG. 17B, a transistor having a smaller current supply capacity than transistors 10

[0160] 1 and 102 can be used for transistor 103. Specifically, the channel width of transistor 103 can be made smaller than the channel widths of transistors 101 and 102. Therefore, the aperture ratio can be increased compared to a configuration in which all are composed of transistors of the same size. the channel width of transistor 103 can be made smaller than the channel widths of transistors 101 and 102. Therefore, the aperture ratio can be increased compared to a configuration in which all are composed of transistors of the same size. the channel width of transistor 103 can be made smaller than the channel widths of transistors 101 and 102. Therefore, the aperture ratio can be increased compared to a configuration in which all are composed of transistors of the same size. Therefore, the aperture ratio can be increased compared to a configuration in which all are composed of transistors of the same size.

[0161] <Simulation result> Next, the simulation results regarding the operation of the pixel will be described. Fig. 18 shows the configuration of pixel 10 used in the simulation. Based on the circuit configuration shown in Fig. 2, for circuit 21, a configuration having a liquid crystal device (Clc) and a capacitor (Cs) was used. The simulation was performed on the voltage change of node NM in the operation of increasing the input voltage by about three times.

[0162] The parameters used in the simulation are as follows. The transistor size is L / W = 3μm / 60μm (transistors Tr1, Tr2), L / W = 3μm / 30μm (transistor Tr3), the capacitance value of capacitor C1 is 14.4 pF, the capacitance value of capacitor Cs is 1.2 pF, and the capacitance value of the liquid crystal element Clc is 1.2 pF. The voltages applied to gate lines GL1 and GL2 are +26V for “H” and -21V for “L”. Also, the potentials of VCOM and TCOM (common voltage) are +8V. Note that SPICE was used for the circuit simulation software.

[0163] Fig. 19 shows the simulation results of the operation according to the timing chart of the pixel shown above, where the horizontal axis represents time (seconds) and the vertical axis represents the voltage (V) of node NM of pixel 10. Note that SL1 corresponds to wiring 127[m_1], SL2 corresponds to wiring 127[m_2], GL1 corresponds to wiring 126 , and GL2 corresponds to wiring 125. Also, during the positive polarity operation, DATA1 is +16V and DAT A2 is 0V. During the negative polarity operation, DATA1 is 0V and DATA2 is +16V.

[0164] As shown in Fig. 19, in both the positive polarity operation and the negative polarity operation, about 21V with reference to the common voltage It was confirmed that the voltage could be boosted (by about 2.6 times or more). Improvement of the electrical characteristics of the transistor and reduction of parasitic capacitance, etc. make it possible to generate a higher voltage .

[0165] From the above simulation results, the effect of one aspect of the present invention could be confirmed.

[0166] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, etc. is possible.

[0167] (Embodiment 2) In this embodiment, a configuration example of a display device using a liquid crystal device and a configuration example of a display device using a light-emitting device will be described. Note that, in this embodiment, the description of the elements, operations, and functions of the display device described in Embodiment 1 is omitted. In the display device described in this embodiment, the pixels described in Embodiment 1 can be used. Note that the scanning line driving circuit described below corresponds to a gate driver, and the signal line driving circuit corresponds to a source driver.

[0168] In the display device described in this embodiment, the pixels described in Embodiment 1 can be used. Note that the scanning line driving circuit described below corresponds to a gate driver, and the signal line driving circuit corresponds to a source driver. corresponds to.

[0169] Figs. 20A to 20C are diagrams showing the configuration of a display device that can use one aspect of the present invention. is.

[0170] In Fig. 20A, a sealing material 4005 is provided so as to surround the display portion 215 provided on the first substrate 4001, and the display portion 215 is sealed by the sealing material 4005 and the second substrate 400 6.

[0171] In Fig. 20A, a scanning line driving circuit 221a, a signal line driving circuit 231a, a signal line driving circuit 23 2a and the common line driving circuit 241a each have a plurality of integrated circuits 4042 provided on the printed circuit board 4041. The integrated circuit 4042 is formed of a single crystal semiconductor or a polycrystalline semiconductor. The common line driving circuit 241a has a function of supplying a prescribed potential to the wirings 151, 152, 129, 154, 155, etc. shown in the first embodiment. The scanning line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and various signals and potentials supplied to the signal line driving circuit 232a are supplied via an FPC (Flexible printed circuit) 4018. The integrated circuits 4042 included in the scanning line driving circuit 221a and the common line driving circuit 241a have a function of supplying a selection signal to the display unit 215. The integrated circuits 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a have a function of supplying image data to the display unit 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. Note that the connection method of the integrated circuit 4042 is not particularly limited, and wire bonding method, COF (Chip On Film) method, COG (Chip On Glass) method, TCP (Tape Carrier Package) method, etc. can be used.

[0172] The scanning line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and various signals and potentials supplied to the signal line driving circuit 232a are supplied via an FPC (Flexible printed circuit) 4018. The scanning line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and various signals and potentials supplied to the signal line driving circuit 232a are supplied via an FPC (Flexible printed circuit) 4018. The scanning line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and various signals and potentials supplied to the signal line driving circuit 232a are supplied via an FPC (Flexible printed circuit) 4018.

[0173] The integrated circuits 4042 included in the scanning line driving circuit 221a and the common line driving circuit 241a have a function of supplying a selection signal to the display unit 215. The integrated circuits 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a have a function of supplying image data to the display unit 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. The integrated circuits 4042 included in the scanning line driving circuit 221a and the common line driving circuit 241a have a function of supplying a selection signal to the display unit 215. The integrated circuits 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a have a function of supplying image data to the display unit 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. The integrated circuits 4042 included in the scanning line driving circuit 221a and the common line driving circuit 241a have a function of supplying a selection signal to the display unit 215. The integrated circuits 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a have a function of supplying image data to the display unit 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. The integrated circuits 4042 included in the scanning line driving circuit 221a and the common line driving circuit 241a have a function of supplying a selection signal to the display unit 215. The integrated circuits 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a have a function of supplying image data to the display unit 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. The integrated circuits 4042 included in the scanning line driving circuit 221a and the common line driving circuit 241a have a function of supplying a selection signal to the display unit 215. The integrated circuits 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a have a function of supplying image data to the display unit 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001.

[0174] Note that the connection method of the integrated circuit 4042 is not particularly limited, and wire bonding method, COF (Chip On Film) method, COG (Chip On Glass) method, TCP (Tape Carrier Package) method, etc. can be used. Note that the connection method of the integrated circuit 4042 is not particularly limited, and wire bonding method, COF (Chip On Film) method, COG (Chip On Glass) method, TCP (Tape Carrier Package) method, etc. can be used. Note that the connection method of the integrated circuit 4042 is not particularly limited, and wire bonding method, COF (Chip On Film) method, COG (Chip On Glass) method, TCP (Tape Carrier Package) method, etc. can be used. Note that the connection method of the integrated circuit 4042 is not particularly limited, and wire bonding method, COF (Chip On Film) method, COG (Chip On Glass) method, TCP (Tape Carrier Package) method, etc. can be used.

[0175] FIG. 20B shows an example of mounting the integrated circuit 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a by the COG method. Also, a part or all of the driving circuit FIG. 20B shows an example of mounting the integrated circuit 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a by the COG method. Also, a part or all of the driving circuit It can be integrally formed on the same substrate as the display unit 215 to form a system-on-panel. .

[0176] In FIG. 20B, an example is shown in which the scanning line driving circuit 221a and the common line driving circuit 241a are formed on the same substrate as the display unit 215. By forming the driving circuit simultaneously with the pixel circuit in the display unit 215, the number of components can be reduced. Therefore, productivity can be increased. .

[0177] Also, in FIG. 20B, a sealing material 4005 is provided so as to surround the display unit 215 provided on the first substrate 4001, the scanning line driving circuit 221a, and the common line driving circuit 241a. Further, a second substrate 4006 is provided on the display unit 215, the scanning line driving circuit 221a, and the common line driving circuit 241a. Therefore, the display unit 215, the scanning line driving circuit 221a, and the common line driving circuit 241a are sealed together with the display device by the first substrate 4001, the sealing material 4005, and the second substrate 4006.

[0178] Also, in FIG. 20B, an example is shown in which the signal line driving circuits 231a and 232a are separately formed and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted. Further, as shown in FIG. 20C, the signal line driving circuits 231a and 232a may be formed on the same substrate as the display unit 215. .

[0179] Also, the display device includes a panel in a state where the display device is sealed, and a control for the panel. It may include a module in a state where an IC or the like including a - la is mounted.

[0180] In addition, the display unit and the scanning line driving circuit provided on the first substrate have a plurality of transistors. As the transistor, the Si transistor or OS transistor shown in Embodiment 1 can be applied. It can be applied.

[0181] The structure of the transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit may be the same or different. All of the transistors included in the peripheral driving circuit may be transistors having the same structure, or may have transistors of two or more types of structures. Similarly, all of the transistors included in the pixel circuit may be transistors having the same structure, or may have transistors of two or more types of structures. The structure of the transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit may be the same or different. All of the transistors included in the peripheral driving circuit may be transistors having the same structure, or may have transistors of two or more types of structures. Similarly, all of the transistors included in the pixel circuit may be transistors having the same structure, or may have transistors of two or more types of structures. The structure of the transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit may be the same or different. All of the transistors included in the peripheral driving circuit may be transistors having the same structure, or may have transistors of two or more types of structures. Similarly, all of the transistors included in the pixel circuit may be transistors having the same structure, or may have transistors of two or more types of structures. The structure of the transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit may be the same or different. All of the transistors included in the peripheral driving circuit may be transistors having the same structure, or may have transistors of two or more types of structures. Similarly, all of the transistors included in the pixel circuit may be transistors having the same structure, or may have transistors of two or more types of structures. The structure of the transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit may be the same or different. All of the transistors included in the peripheral driving circuit may be transistors having the same structure, or may have transistors of two or more types of structures. Similarly, all of the transistors included in the pixel circuit may be transistors having the same structure, or may have transistors of two or more types of structures.

[0182] In addition, an input device 4200 can be provided on the second substrate 4006. The configuration in which the input device 4200 is provided in the display device shown in FIGS. 20A to 20C can function as a touch panel. In addition, an input device 4200 can be provided on the second substrate 4006. The configuration in which the input device 4200 is provided in the display device shown in FIGS. 20A to 20C can function as a touch panel. It can be made to function.

[0183] There is no limitation on the detection device (also referred to as a sensor element) included in the touch panel according to one aspect of the present invention. Various sensors capable of detecting the proximity or contact of a detected object such as a finger or a stylus can be applied as the detection device. There is no limitation on the detection device (also referred to as a sensor element) included in the touch panel according to one aspect of the present invention. Various sensors capable of detecting the proximity or contact of a detected object such as a finger or a stylus can be applied as the detection device. It can be applied as a detection device.

[0184] As the sensor method, for example, various methods such as a capacitance method, a resistive film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure sensitive method can be used. It can be used.

[0185] In this embodiment, a touch panel having a capacitance type detection device will be described as an example. Do it.

[0186] As capacitance methods, there are surface capacitance methods, projection capacitance methods, etc. Also, as for the projection capacitance method, there are self-capacitance methods, mutual-capacitance methods, etc. Using the mutual-capacitance method is preferable because it enables simultaneous multi-point detection.

[0187] The touch panel according to one aspect of the present invention can adopt various configurations, such as a configuration in which a separately manufactured display device and a detection device are bonded together, a configuration in which electrodes and the like constituting the detection device are provided on one or both of a substrate supporting the display device and a counter substrate.

[0188] An example of a touch panel is shown in FIGS. 21A and 21B. FIG. 21A is a perspective view of a touch panel 4210 FIG. 21B is a schematic perspective view of an input device 4200. For clarity, only typical components are shown.

[0189] The touch panel 4210 has a configuration in which a separately manufactured display device and a detection device are bonded together.

[0190] The touch panel 4210 has an input device 4200 and a display device, and these are provided so as to overlap each other.

[0191] The input device 4200 includes a substrate 4263, electrodes 4227, electrodes 4228, a plurality of wirings 4237 a plurality of wirings 4238, and a plurality of wirings 4239. For example, the electrode 4227 can be electrically connected to the wiring 4237 or the wiring 4239. Also, the electrode 4228 can be electrically connected to the wiring 4239. The FPC 4272b is connected to a plurality of wirings 4237 and is electrically connected to each of the plurality of wirings 4238. The FPC 4272b can be provided with an IC 427 3b.

[0192] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. When a touch sensor is provided between the first substrate 4001 and the second substrate 4006, in addition to the capacitance type touch sensor, an optical touch sensor using a photoelectric conversion element may be applied.

[0193] FIGS. 22A and 22B are cross-sectional views of the portion indicated by the chain line N1 - N2 in FIG. 20B. The display device shown in FIGS. 22A and 22B has an electrode 4015, and the electrode 4015 is electrically connected via an anisotropic conductive layer 4019 to the terminal of the FPC 4 018. Also, in FIGS. 22A and 22B, the electrode 4015 is electrically connected to the wiring 4014 at an opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110. In FIGS. 22A and 22B, the electrode 4015 is formed from the same conductive layer as the first electrode layer 4030, and the wiring 4014 is formed from the same conductive layer as the source and drain electrodes of the transistors 4010 and 4011.

[0194] The display unit 215 and the scanning line driving circuit 221a provided on the first substrate 4001 have a plurality of transistors. In FIGS. 22A and 22B, the transistors 4010 included in the display unit 215 and the transistors 4011 included in the scanning line driving circuit 221a are exemplified . Note that in FIGS. 22A and 22B, the transistors 4010 and the transistors 4

[0195] Also, the display unit 215 and the scanning line driving circuit 221a provided on the first substrate 4001 have a plurality of transistors. In FIGS. 22A and 22B, the transistors 4010 included in the display unit 215 and the transistors 4011 included in the scanning line driving circuit 221a are exemplified . In FIGS. 22A and 22B, the transistors 4010 included in the display unit 215 and the transistors 4011 included in the scanning line driving circuit 221a are exemplified . Note that in FIGS. 22A and 22B, the transistors 4010 and the transistors 4 011 are illustrated. Note that in FIGS. 22A and 22B, the transistors 4010 and the transistors 4 Although a bottom-gate type transistor is exemplified as 011, a top-gate type transistor may also be used.

[0196] In FIGS. 22A and 22B, an insulating layer 4112 is provided on transistors 4010 and 4011. In FIG. 22B, a partition wall 4510 is formed on the insulating layer 4112.

[0197] Also, transistors 4010 and 4011 are provided on an insulating layer 4102. Also, transistors 4010 and 4011 have an electrode 4017 formed on an insulating layer 4111. The electrode 4017 can function as a back gate electrode.

[0198] Also, the display device shown in FIGS. 22A and 22B has a capacitor 4020. The capacitor 4020 has an example including an electrode 4021 formed in the same process as the gate electrode of the transistor 4010, an insulating layer 4103, and an electrode formed in the same process as the source electrode and the drain electrode. The configuration of the capacitor 4020 is not limited to this, and it may be formed of other conductive layers and insulating layers.

[0199] The transistor 4010 provided in the display unit 215 is electrically connected to the display device. FIG. 22A is an example of a liquid crystal display device using a liquid crystal device as a display device. In FIG. 22A, the liquid crystal device 4013, which is a display device, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that insulating layers 4032 and 4033 that function as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode ​​​​​Layer 4031 is provided on the side of the second substrate 4006 and overlaps with the first electrode layer 4030 via the liquid crystal layer 4008.

[0200] As the liquid crystal device 4013, a liquid crystal device to which various modes are applied can be used. For example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, an ECB (Electrically Controlled Birefringence) mode, a VA-IPS mode, a guest-host mode, etc. can be applied. A liquid crystal device to which such modes are applied can be used.

[0201] In addition, a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be applied to the liquid crystal display device shown in this embodiment. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, etc. can be used.

[0202] Note that the liquid crystal device controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. It is a vice. The optical modulation effect of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). As the liquid crystal used in the liquid crystal device, thermotropic liquid crystal, low molecular liquid crystal, high molecular liquid crystal, polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions. In FIG. 22A, an example of a liquid crystal display device having a vertical electric field type liquid crystal device is shown. However, in one aspect of the present invention, a liquid crystal display device having a horizontal electric field type liquid crystal device can be applied. When adopting the horizontal electric field method, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric phase transitions from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed and exhibits optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require an alignment treatment and has a small viewing angle dependence. Also, since an alignment film does not need to be provided, a rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced.

[0203] In FIG. 22A, an example of a liquid crystal display device having a vertical electric field type liquid crystal device was shown. However, in one aspect of the present invention, a liquid crystal display device having a horizontal electric field type liquid crystal device can be applied. When adopting the horizontal electric field method, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric phase transitions from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed and exhibits optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require an alignment treatment and has a small viewing angle dependence. Also, since an alignment film does not need to be provided, a rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. When adopting the horizontal electric field method, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric phase transitions from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed and exhibits optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require an alignment treatment and has a small viewing angle dependence. Also, since an alignment film does not need to be provided, a rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric phase transitions from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed and exhibits optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require an alignment treatment and has a small viewing angle dependence. Also, since an alignment film does not need to be provided, a rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed and exhibits optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require an alignment treatment and has a small viewing angle dependence. Also, since an alignment film does not need to be provided, a rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require an alignment treatment and has a small viewing angle dependence. Also, since an alignment film does not need to be provided, a rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. Also, since an alignment film does not need to be provided, a rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. can be reduced.

[0204] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer. The distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0205] If necessary, a black matrix (light-shielding layer), a colored layer (color filter), a polarizing Optical members (optical substrates) such as a member, a phase difference member, and an anti-reflection member may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. In addition, the above-mentioned backlight and sidelight may be used. Micro LEDs or the like may be used as the light source.

[0206] In the display device shown in FIG. 22A, a light-shielding layer 4006 is provided between the second substrate 4006 and the second electrode layer 4031. A layer 4132, a coloring layer 4131, and an insulating layer 4133 are provided.

[0207] Materials that can be used for the light-shielding layer include carbon black, titanium black, gold, etc. Examples of the material for the light-shielding layer include metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The film may be a film containing a resin material, or may be a thin film of an inorganic material such as a metal. In addition, a laminated film of a film containing the material of the colored layer may be used for the light-shielding layer. A film containing a material for a colored layer that transmits light of a certain color and a material for a colored layer that transmits light of a different color are used. By using the same material for the colored layer and the light-shielding layer, This is preferable because it allows the equipment to be standardized and the process to be simplified.

[0208] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, or dyes. Examples include the resin material thus obtained. The light-shielding layer and the coloring layer can be formed, for example, by an inkjet method or the like.

[0209] Further, the display device shown in FIGS. 22A and 22B has an insulating layer 4111 and an insulating layer 4104. As the insulating layer 4111 and the insulating layer 4104, an insulating layer that hardly transmits impurity elements is used. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, intrusion of external impurities can be prevented.

[0210] Further, a light-emitting device can be used as the display device included in the display device. As the light-emitting device, for example, an EL device that utilizes electroluminescence can be applied. The EL device has a layer containing a light-emitting compound (also referred to as an "EL layer") between a pair of electrodes. When a potential difference larger than the threshold voltage of the EL device is generated between the pair of electrodes, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the light-emitting compound contained in the EL layer emits light.

[0211] As the EL device, for example, an organic EL device or an inorganic EL device can be used. Note that an LED (including a micro LED) using a compound semiconductor as the light-emitting material can also be used.

[0212] Note that the EL layer may have, in addition to the light-emitting compound, a substance with high hole injection property, a substance with high hole transport property, a hole blocking material, a substance with high electron transport property, a substance with high electron injection property, or a bipolar substance (a substance with high electron transport property and high hole transport property).

[0213] The EL layer can be formed by a variety of methods, including deposition (including vacuum deposition), transfer, printing, inkjet, and coating. It can be formed in any way.

[0214] Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices depending on the element structure. Dispersion-type inorganic EL devices are classified into two types: dispersed-type and non-dispersion-type. Dispersion-type inorganic EL devices have particles of light-emitting material dispersed in a binder. The light-emitting mechanism utilizes the donor and acceptor levels. The thin-film inorganic EL device uses a donor-acceptor recombination type luminescence. The structure is sandwiched between dielectric layers, which are then sandwiched between electrodes. The light-emitting mechanism is metal ions. This is a localized emission that utilizes the inner-shell electron transition of fluorine. An explanation will be given using an organic EL device.

[0215] In a light-emitting device, at least one of a pair of electrodes needs to be transparent in order to extract light. Then, a transistor and a light-emitting device are formed on the substrate, and the substrate is Top emission structure that extracts light, or emits light from the substrate side Bottom emission structure and dual emission structure that emits light from both sides There are light-emitting devices with a mission structure, and any light-emitting device with an injection structure can be applied. can.

[0216] FIG. 22B shows a light-emitting display device ("EL display device") that uses a light-emitting device as a display device. The light-emitting device 4513, which is a display device, is an example of the display unit 215. The light emitting device 4513 is electrically connected to the transistor 4010 provided in the light emitting device 4513. The structure is a stacked structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031. However, it is not limited to this structure. Depending on the direction of the light extracted from the light-emitting device 4513, etc., the structure of the light-emitting device 4513 can be appropriately changed.

[0217] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, using a photosensitive resin material, an opening is formed on the first electrode layer 4030, and it is preferably formed such that the side surface of the opening becomes an inclined surface formed with a continuous curvature.

[0218] The light-emitting layer 4511 may be composed of a single layer or may be configured such that a plurality of layers are stacked. Either is acceptable.

[0219] The emission color of the light-emitting device 4513 can be white, red, green, blue, cyan, magenta, or yellow, etc., depending on the material constituting the light-emitting layer 4511.

[0220] As a method for realizing color display, there are a method of combining a light-emitting device 4513 with an emission color of white and a coloring layer, and a method of providing light-emitting devices 4513 with different emission colors for each pixel. The former method has higher productivity than the latter method. On the other hand, in the latter method, since it is necessary to separately produce the light-emitting layer 4511 for each pixel, the productivity is inferior to the former method. However, in the latter method, an emission color with higher color purity can be obtained than in the former method. In addition to the latter method, by imparting a microcavity structure to the light-emitting device 4513, the color purity can be further enhanced.

[0221] Note that the light-emitting layer 4511 may contain an inorganic compound such as quantum dots. For example, the amount The child dots can be used in a light-emitting layer to function as a light-emitting material.

[0222] The second electrode is disposed in order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting device 4513. A protective layer may be formed on the electrode layer 4031 and the partition wall 4510. The protective layer may be silicon nitride. Silicon, silicon oxide nitride, aluminum oxide, aluminum nitride, aluminum oxynitride Aluminum, aluminum oxide nitride, DLC (Diamond Like Carbon), etc. Also, the first substrate 4001, the second substrate 4006, and the seal The space sealed by the material 4005 is sealed with a filler 4514. To prevent exposure to the outside air, a protective film (lamination) with high airtightness and low outgassing is used. packaging (enclosure) in a covering material (such as a protective film or ultraviolet curing resin film) is preferred.

[0223] Filler 4514 can be inert gas such as nitrogen or argon, or ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resins, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Also, filler 4514 may contain a desiccant.

[0224] The sealing material 4005 is made of glass materials such as glass frit, or two-liquid mixed resin. Resin materials such as heat-curable resin, photocurable resin, and thermosetting resin can be used. Also, the sealant 4005 may contain a desiccant.

[0225] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be installed on the exit surface of the light-emitting device. Optical films such as retardation films (lambda / 4 plates, lambda / 2 plates), and color filters are appropriately installed. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. The convex surface can be used to diffuse reflected light and reduce glare with an anti-glare treatment.

[0226] In addition, by making the light-emitting device into a microcavity structure, light with high color purity can be extracted. In addition, by combining a microcavity structure with a color filter, This reduces glare and improves visibility of the displayed image.

[0227] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer) that apply a voltage to the display device In the case of the layer (also called the counter electrode layer, etc.), the direction of the light to be extracted and the location where the electrode layer is provided The light transmitting property or the light reflective property can be selected depending on the pattern structure of the electrode layer.

[0228] The first electrode layer 4030 and the second electrode layer 4031 are made of indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide In addition, a conductive material having light transmitting properties, such as indium tin oxide doped with silicon oxide, is used. This can be done.

[0229] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) or molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b) Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), etc. , or an alloy thereof, or one or more can be formed using a metal nitride thereof. .

[0230] Also, as the first electrode layer 4030 and the second electrode layer 4031, a conductive composition containing a conductive polymer (also referred to as a conductive polymer) can be used. As the conductive polymer , a so-called π-electron conjugated system conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives , or a copolymer or its derivatives composed of two or more of aniline, pyrrole, and thiophene, etc. can be mentioned.

[0231] Also, since the transistor is easily damaged by static electricity, etc., it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably configured using a non-linear element.

[0232] In addition, as shown in FIG. 23, a stack structure having a region where a transistor and a capacitor overlap in the height direction may be used. For example, if the transistors 4011 and 4022 constituting the drive circuit are stacked and arranged, a display device with a narrow bezel can be obtained. Also, if the transistors 4010, 4023, and capacitor 4 020 constituting the pixel circuit are arranged so as to have a region where they partially overlap, the aperture ratio and resolution can be improved. In addition, although FIG. 23 shows an example in which the stack structure is applied to the liquid crystal display device shown in FIG. 22A, it may also be applied to the EL display device shown in FIG. 22B.

[0233] In the pixel circuit, by using a transparent conductive film with high transparency to visible light for electrodes and wirings, the transmittance of light within the pixel can be increased, and the aperture ratio can be substantially improved. When using an OS transistor, since the semiconductor layer also has transparency, the aperture ratio can be further increased. These are effective even when the transistor or the like is not in a stack structure.

[0234] Also, a display device may be configured by combining a liquid crystal display device and a light-emitting device.

[0235] The light-emitting device is disposed on the reverse side of the display surface or at the end of the display surface. The light-emitting device has a function of supplying light to the display device. The light-emitting device can also be called a backlight.

[0236] Here, the light-emitting device can have a plate-shaped or sheet-shaped light guide part (also referred to as a light guide plate) and a plurality of light-emitting devices that exhibit different colors of light. When the light-emitting devices are disposed near the side surface of the light guide part, light can be emitted from the side surface of the light guide part into the interior. The light guide part has a mechanism for changing the optical path (also referred to as a light extraction mechanism), whereby the light-emitting device can uniformly irradiate the pixel part of the display panel with light. Or, a configuration may be adopted in which the light guide part is not provided and the light-emitting device is disposed directly below the pixel.

[0237] The light-emitting device preferably has light-emitting devices of three colors: red (R), green (G), and blue (B). Further, it may have a white (W) light-emitting device. It is preferable to use a light-emitting diode (LED) as these light-emitting devices.

[0238] ​​​​​​​​​​Furthermore, the light-emitting device preferably has a full width at half maximum (FWHM) of its emission spectrum of 50 nm or less, more preferably 40 nm or less, even more preferably 30 nm or less, and still more preferably 20 nm or less, being a light-emitting device with extremely high color purity. Note that the smaller the full width at half maximum of the emission spectrum, the better, but it can be, for example, 1 nm or more. Thereby, when performing color display, a vivid display with high color reproducibility can be achieved. In addition, for the red light-emitting device, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 625 nm or more and 650 nm or less. For the green light-emitting device, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 515 nm or more and 540 nm or less. For the blue light-emitting device,

[0239] it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 445 nm or more and 470 nm or less. The display device can perform color display based on the sequential addition color mixing method by sequentially turning on and off the three-color light-emitting devices and driving the pixels in synchronization therewith. This driving method can also be called field-sequential driving. In field-sequential driving, a vivid color image can be displayed. Also, a smooth moving image can be displayed. Also, by using the above driving method, it is not necessary to configure one pixel with a plurality of sub-pixels of different colors, and the effective reflection area (also referred to as the effective display area or aperture ratio) of one pixel can be increased,

[0240] so that a bright display can be achieved. Furthermore, the driving method can be called field-sequential driving. In field-sequential driving, a vivid color image can be displayed. Also,

[0241] a smooth moving image can be displayed. Also, by using the above driving method, it is not necessary to configure one pixel with a plurality of sub-pixels of different colors, and the effective reflection area (also referred to as the effective display area or aperture ratio) of one pixel can be increased, so that a bright display can be achieved. Furthermore, it is not necessary to configure one pixel with a plurality of sub-pixels of different colors, and the effective reflection area (also referred to as the effective display area or aperture ratio) of one pixel can be increased, so that a bright display can be achieved. Furthermore, , since there is no need to provide a color filter for the pixel, the transmittance of the pixel can also be improved , and a brighter display can be achieved. Also, the manufacturing process can be simplified, and the manufacturing cost can be reduced.

[0242] FIGS. 24A and 24B are schematic cross-sectional views of a display device capable of field-sequential driving as an example. On the side of the first substrate 4001 of the display device, a backlight unit capable of emitting light of each of the RGB colors is provided. In field-sequential driving, since colors are expressed by time-division emission of each of the RGB colors, a color filter is not required.

[0243] The backlight unit 4340a shown in FIG. 24A has a configuration in which a plurality of light-emitting devices 4342 are provided via a diffusion plate 4352 directly below the pixel. The diffusion plate 4352 diffuses the light emitted from the light-emitting device 4342 toward the first substrate 4001 side and has a function of equalizing the luminance within the display area. A polarizing plate may be provided between the light-emitting device 4342 and the diffusion plate 4352 as needed. Also, if the diffusion plate 4352 is not necessary, it may not be provided. Further, a configuration in which the light-shielding layer 4132 is omitted may be adopted.

[0244]

[0244] Since the backlight unit 4340a can mount a large number of light-emitting devices 4342, a bright display can be achieved. Also, a light guide plate is not required, and there is an advantage that the efficiency of the light of the light-emitting device 4342 is hardly impaired. Note that a lens 4344 for light diffusion may be provided for the light-emitting device 4342 as needed.

[0245]

[0245] The backlight unit 4340b shown in FIG. 24B has a configuration in which a diffusion plate 4352 is provided via a diffusion plate 4352 directly below the pixel. The light guide plate 4341 is provided at the end of the light guide plate 4341. The light guide plate 4341 has an uneven shape on the side opposite to the diffusion plate 4352. The guided light can be scattered by the uneven surface and emitted in the direction of the diffusion plate 4352.

[0246] The light emitting device 4342 can be fixed to a printed circuit board 4347. In B, the light emitting devices 4342 for each of the R, G, and B colors are illustrated as overlapping, but The light emitting devices 4342 of each color of R, G, and B may be arranged side by side. In the case of 341, a reflective layer that reflects visible light is provided on the side opposite to the light emitting device 4342. 4348 may also be provided.

[0247] The backlight unit 4340b can reduce the number of light-emitting devices 4342. Therefore, it is possible to achieve a low-cost and thin structure.

[0248] The liquid crystal device may be a light scattering type liquid crystal device. It is preferable to use an element having a composite material of liquid crystal and polymer. A polymer network type liquid crystal device can be used. Using LC (Polymer Network Liquid Crystal) elements This is also fine.

[0249] The light-scattering liquid crystal device is a device in which liquid is injected into the three-dimensional network structure of a resin part sandwiched between a pair of electrodes. The material used for the liquid crystal portion is, for example, nematic liquid crystal. The resin portion can be made of a photocurable resin. The resin may be, for example, a monofunctional monomer such as acrylate or methacrylate, a polyfunctional monomer such as diacrylate, triacrylate, dimethacrylate, trimethacrylate, etc., or a polymerizable compound obtained by mixing these may be used.

[0250] The light-scattering type liquid crystal device utilizes the anisotropy of the refractive index of the liquid crystal material to transmit or scatter light for display. Also, the resin portion may have anisotropy of refractive index. When the liquid crystal molecules are aligned in a certain direction according to the voltage applied to the light-scattering type liquid crystal device, a direction in which the difference in refractive index between the liquid crystal portion and the resin portion becomes small is generated, and light incident along the direction is transmitted through the liquid crystal portion without being scattered. Therefore, the light-scattering type liquid crystal device is visually recognized as a transparent state from that direction. On the other hand, when the alignment of the liquid crystal molecules becomes random according to the applied voltage, since there is no significant change in the difference in refractive index between the liquid crystal portion and the resin portion, the incident light is scattered by the liquid crystal portion. Therefore, the light-scattering type liquid crystal device becomes opaque regardless of the viewing direction.

[0251] FIG. 25A shows a configuration in which the liquid crystal device 4013 of the display device in FIG. 24A is replaced with a light-scattering type liquid crystal device 401 6. The light-scattering type liquid crystal device 4016 has a composite layer 4009 having a liquid crystal portion and a resin portion, and a first electrode layer 4030 and a second electrode layer 4031. The elements related to field sequential driving are the same as those in FIG. 24A, but when using the light-scattering type liquid crystal device 4016, the alignment film and the polarizing plate become unnecessary. Note that the spacer 4035 is illustrated in a spherical form, but it may be columnar.

[0252] FIG. 25B shows a configuration in which the liquid crystal device 4013 of the display device in FIG. 24B is replaced with a light-scattering type liquid crystal device 401 It is a configuration replaced by 6. In the configuration of FIG. 24B, the voltage is applied to the light-scattering type liquid crystal device 4016 When not applied, light is transmitted, and when a voltage is applied, it operates in a mode of scattering light It is preferably configured. By adopting this configuration, a transparent display device can be obtained in the normal state (a state where display is not performed ). In this case, color display can be performed when the operation of scattering light is performed .

[0253] A modified example of the display device shown in FIG. 25B is shown in FIGS. 26A to 26E. In FIGS. 26A to 26E, for clarity, some elements of FIG. 25B are used and other elements are omitted for illustration .

[0254] FIG. 26A shows a configuration in which the first substrate 4001 has a function as a light guide plate. An uneven shape may be provided on the outer surface of the first substrate 4001. In this configuration, since there is no need to separately provide a light guide plate, the manufacturing cost can be reduced. Also, since attenuation of light by the light guide plate is eliminated, the light emitted by the light emitting device 4342 can be efficiently utilized . .

[0255] FIG. 26B shows a configuration in which light is incident from the vicinity of the end of the composite layer 4009. Total reflection at the interface between the composite layer 4009 and the second substrate 4006, and at the interface between the composite layer 4009 and the first substrate 4001 is utilized, and light can be emitted from the light-scattering type liquid crystal device to the outside. In the resin portion of the composite layer 4 009, a material having a refractive index larger than that of the first substrate 4001 and the second substrate 4006 is used.

[0256] Note that the light emitting device 4342 is not only provided on one side of the display device, but also as shown in FIG. 26C ​​​It may be provided on two sides facing each other. Further, it may be provided on three sides or four sides. The light-emitting device 4342 can be provided on a plurality of sides to compensate for light attenuation, and a large-area display device can also be supported.

[0257] FIG. 26D shows a configuration in which light emitted from the light-emitting device 4342 is guided to the display device through the mirror 4345. With this configuration, it is easy to guide light to the display device at a certain angle so that total reflection light can be obtained efficiently.

[0258] FIG. 26E shows a configuration having a stack of the layer 4003 and the layer 4004 on the composite layer 4009 . One of the layer 4003 and the layer 4004 is a support such as a glass substrate, and the other can be formed of an inorganic film, a coating film or a film of an organic resin, etc. A material having a refractive index larger than that of the layer 4004 is used for the resin portion of the composite layer 4009. Also, a material having a refractive index larger than that of the layer 4003 is used for the layer 4004.

[0259] A first interface is formed between the composite layer 4009 and the layer 4004, and a second interface is formed between the layer 4004 and the layer 400 3. With this configuration, light that has passed through without being totally reflected at the first interface can be totally reflected at the second interface and returned to the composite layer 4009. Therefore, the light emitted from the light-emitting device 4342 can be used efficiently.

[0260] Note that the configurations in FIGS. 25B and 26A to 26E can be combined with each other.

[0261] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like. ​​​​​

[0262] (Embodiment 3) In this embodiment, an example of a transistor that can be used in place of each transistor shown in the above embodiment will be described with reference to the drawings.

[0263] The display device according to one aspect of the present invention can be manufactured using various types of transistors such as bottom-gate type transistors and top-gate type transistors. Therefore, it is possible to easily replace the material of the semiconductor layer and the transistor structure to be used according to the existing manufacturing line.

[0264] 〔Bottom-gate type transistor〕 FIG. 27A1 is a cross-sectional view of a channel protection type transistor 810, which is a type of bottom-gate type transistor, in the channel length direction. In FIG. 27A1, the transistor 810 is formed on a substrate 771. Further, the transistor 810 has an electrode 746 on the substrate 771 via an insulating layer 772. Further, a semiconductor layer 742 is provided on the electrode 746 via an insulating layer 726. The electrode 746 can function as a gate electrode. The insulating layer 726 can function as a gate insulating layer.

[0265]

[0266] ​​​​​​​​​​​​​​The insulating layer 741 can function as a channel protection layer. By providing the electrode 744a and the electrode 744b, the exposure of the semiconductor layer 742 that occurs during the formation of the electrode 744a and the electrode 744b is suppressed. Therefore, when the electrodes 744a and 744b are formed, the semiconductor layer This can prevent the channel formation region 742 from being etched. According to this, a transistor having good electrical characteristics can be realized.

[0267] The transistor 810 includes an insulating layer 741 and an electrode 744a. A layer 728 is provided, and an insulating layer 729 is provided on the insulating layer 728 .

[0268] When an oxide semiconductor is used for the semiconductor layer 742, at least At least in the portion in contact with the semiconductor layer 742, oxygen is taken from a portion of the semiconductor layer 742, and oxygen vacancies are formed. It is preferable to use a material capable of generating oxygen vacancies in the semiconductor layer 742. The resulting region has an increased carrier concentration, which makes it n-type, and the region is called an n-type region (n + area) Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, oxygen is taken from the semiconductor layer 742, and oxygen vacancies occur. Examples of materials capable of generating this include tungsten and titanium. Cut.

[0269] The source region and the drain region are formed in the semiconductor layer 742, whereby the electrode 744a In addition, the contact resistance between the electrode 744b and the semiconductor layer 742 can be reduced. The electrical characteristics of the transistor, such as the effective mobility and threshold voltage, can be improved. can.

[0270] When using a semiconductor such as silicon for the semiconductor layer 742, between the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b, it is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor. The layer that functions as an n-type semiconductor or a p-type semiconductor can function as the source region or the drain region of a transistor.

[0271] The insulating layer 729 is preferably formed using a material having a function of preventing or reducing the diffusion of impurities from the outside into the transistor. Note that the insulating layer 729 can be omitted if necessary.

[0272] The transistor 811 shown in FIG. 27A2 is different from the transistor 810 in that it has an electrode 723 that can function as a back gate electrode on the insulating layer 729. The electrode 723 can be formed by the same materials and methods as the electrode 74 6.

[0273] Generally, the back gate electrode is formed of a conductive layer and is arranged so as to sandwich the channel formation region of the semiconductor layer between the gate electrode and the back gate electrode. Therefore, the back gate electrode can function in the same manner as the gate electrode. The potential of the back gate electrode may be the same as the potential of the gate electrode or may be the ground potential (GND potential) or any arbitrary potential. Also, by changing the potential of the back gate electrode independently without linking it to the potential of the gate electrode, the threshold voltage of the transistor can be changed.

[0274] Both the electrode 746 and the electrode 723 can function as gate electrodes. Therefore, the insulating layer 726, the insulating layer 728, and the insulating layer 729 can each serve as a gate insulating layer ​ It can function. Note that the electrode 723 may be provided between the insulating layer 728 and the insulating layer 729. It may be.

[0275] When one of the electrode 746 or the electrode 723 is referred to as the "gate electrode", the other is referred to as the "back gate electrode". For example, in the transistor 811, when the electrode 723 is referred to as the "gate electrode", the electrode 746 is referred to as the "back gate electrode". Also, when the electrode 723 is used as the "gate electrode", the transistor 811 can be considered as a type of top gate transistor. Further, in some cases, one of the electrode 746 and the electrode 723 is referred to as the "first gate electrode" and the other is referred to as the "second gate electrode".

[0276] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, and further by setting the electrode 746 and the electrode 723 to the same potential, the region where carriers flow in the semiconductor layer 742 becomes larger in the film thickness direction, so that the amount of carrier movement increases. As a result, the on-current of the transistor 811 increases and the field effect mobility becomes higher.

[0277]

[0278] Also, since the gate electrode and the back gate electrode are formed of a conductive layer, outside the transistorA function that prevents the generated electric field from acting on the semiconductor layer where the channel is formed (especially an electric field shielding function against static electricity, etc.) is provided. Note that by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be enhanced. In addition, by forming the back gate electrode with a conductive film having light-shielding properties, it is possible to prevent light from entering the semiconductor layer from the side of the back gate electrode. Therefore, it is possible to prevent light deterioration of the semiconductor layer and deterioration of electrical characteristics such as a shift in the threshold voltage of the transistor. According to one aspect of the present invention, a transistor with good reliability can be realized. Also, a semiconductor device with good reliability can be realized.

[0279] Moreover, by forming the back gate electrode with a conductive film having light-shielding properties, it is possible to prevent light from entering the semiconductor layer from the side of the back gate electrode. Thus, it is possible to prevent light deterioration of the semiconductor layer and deterioration of electrical characteristics such as a shift in the threshold voltage of the transistor.

[0280] According to one aspect of the present invention, a highly reliable transistor can be realized. Also, a highly reliable semiconductor device can be realized.

[0281] FIG. 27B1 is a cross-sectional view of the transistor 820 of the channel protection type having a configuration different from that of FIG. 27A1 in the channel length direction. The transistor 820 has substantially the same structure as the transistor 810, but is different in that the insulating layer 741 covers the end of the semiconductor layer 742. Also, at the opening formed by selectively removing a part of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a are electrically connected. Further, at another opening formed by selectively removing a part of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 and the electrode 744b are electrically connected. The region of the insulating layer 741 overlapping the channel formation region can function as a channel protection layer.

[0282] The transistor 821 shown in FIG. 27B2 functions as a back gate electrode on the insulating layer 729. ​​​​​​​​​​​​The transistor 820 differs from the transistor 820 in that it has an electrode 723 that can be connected.

[0283] By providing the insulating layer 741, the semiconductor generated when the electrodes 744a and 744b are formed can be prevented. Therefore, when the electrode 744a and the electrode 744b are formed, the layer 742 can be prevented from being exposed. In addition, the semiconductor layer 742 can be prevented from becoming thin.

[0284] In addition, the transistors 820 and 821 are the same as the transistors 810 and The distance between the electrodes 744a and 746 and the distance between the electrodes 744b and 746 are smaller than the distance between the electrodes 744a and 746 and the distance between the electrodes 744b and 746. Therefore, the distance between the electrodes 744a and 746 is increased. In addition, the parasitic capacitance between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. Cut.

[0285] FIG. 27C1 shows a channel-etched transistor, which is one of the bottom-gate transistors. 7 is a cross-sectional view in the channel length direction of the transistor 825. The transistor 825 is The electrodes 744a and 744b are formed without using any of the electrodes 744a and 744b. A part of the semiconductor layer 742 that is exposed when the electrode 744b is formed may be etched. On the other hand, since the insulating layer 741 is not provided, productivity of the transistor can be increased.

[0286] The transistor 826 shown in FIG. 27C2 has a back gate electrode formed on an insulating layer 729. The transistor 825 differs from the transistor 825 in that it has an electrode 723 that can be connected.

[0287] 28A1 to 28C2 show transistors 810, 811, 820, 821, 825, and 826. Each shows a cross-sectional view in the channel width direction of 26.

[0288] In the structures shown in FIGS. 28B2 and 28C2, the gate electrode and the back gate electrode are connected, and the potentials of the gate electrode and the back gate electrode become the same potential. Also, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0289] The length of each of the gate electrode and the back gate electrode in the channel width direction is longer than the length of the semiconductor layer 74 2 in the channel width direction, and the entire channel width direction of the semiconductor layer 742 is covered by the gate electrode and the back gate electrode with the insulating layers 726, 741, 728, and 729 interposed therebetween. It is configured in this way.

[0290] By adopting such a configuration, the semiconductor layer 742 included in the transistor can be electrically surrounded by the electric fields of the gate electrode and the back gate electrode.

[0291] A device structure of a transistor in which a semiconductor layer 742 in which a channel formation region is formed is electrically surrounded by the electric fields of a gate electrode and a back gate electrode, such as transistor 821 or transistor 826, can be called a Surrounded channel (S-channel) structure. el) structure. By adopting the S-channel structure, an electric field for inducing a channel can be effectively applied to the semiconductor layer 742 by one or

[0292] both of the gate electrode and the back gate electrode, so that the current driving ability of the transistor can be improved and high on-current characteristics can be obtained. Also, since it is possible to increase the on-current, it is possible to miniaturize the transistor. This makes it possible. Moreover, since it is possible to increase the on-current, This becomes possible. Also, by adopting an S-channel structure, the mechanical strength of the transistor can be enhanced.

[0293] 〔Top-gate type transistor〕 The transistor 842 illustrated in FIG. 29A1 is one of the top-gate type transistors. The electrodes 744a and 744b are electrically connected to the semiconductor layer 742 at the openings formed in the insulating layer 728 and the insulating layer 729.

[0294] Also, by removing a part of the insulating layer 726 that does not overlap with the electrode 746 and introducing impurities into the semiconductor layer 742 using the remaining insulating layer 726 as a mask, an impurity region can be formed self-alignedly in the semiconductor layer 742. The transistor 842 has a region where the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration in the region of the semiconductor layer 742 where impurities are introduced through the insulating layer 726 is lower than that in the region where impurities are introduced without passing through the insulating layer 726. Therefore, an LDD (Lightly Doped Drain) region is formed in the region of the semiconductor layer 742 that overlaps with the insulating layer 726 and does not overlap with the electrode 746.

[0295] The transistor 843 shown in FIG. 29A2 differs from the transistor 842 in that it has an electrode 723. The transistor 843 has an electrode 723 formed on the substrate 771. The electrode 723 has a region that overlaps with the semiconductor layer 742 through the insulating layer 772. The electrode 723 can function as a back gate electrode.

[0296] Also, the transistors 844 shown in FIG. 29B1 and the transistors 845 shown in FIG. 29B2 As shown in FIG. 29C1, all of the insulating layer 726 in the region that does not overlap with the electrode 746 may be removed. Also, as shown in the transistor 846 shown in FIG. 29C1 and the transistor 847 shown in FIG. 29C2,

[0297] the insulating layer 726 may be left. After forming the electrode 746, the transistors 842 to 847 also use the electrode 746 as a mask to introduce impurities into the semiconductor layer 742, so that self-aligned impurity regions can be formed in the semiconductor layer 742. According to one aspect of the present invention, transistors with good electrical characteristics can be realized. Also, according to one aspect of the present invention, a semiconductor device with high integration can be realized.

[0298] Cross-sectional views in the channel width direction of the transistors 842, 843, 844, 845, 846, and 8 47 are shown in FIGS. 30A1 to 30C2, respectively.

[0299] The transistors 843, 845, and 847 each have the S-channel structure described above. However, the present invention is not limited to this, and the transistors 84 3, 845, and 847 do not necessarily have to have the S-channel structure.

[0300] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0301] (Embodiment 4) As electronic devices that can use the display device according to one aspect of the present invention, there are display devices, personal computers, image storage devices or image playback devices equipped with recording media, mobile phones, and portable Game machines, portable data terminals, e-book terminals, video cameras, digital still cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers fax machines, printers, multifunction printers, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in Fig. 31.

[0302] Fig. 31A is a digital camera, having a housing 961, a shutter button 962, a microphone 963 , a speaker 967, a display unit 965, operation keys 966, a zoom lever 968, a lens 969 etc. By using the display device of one aspect of the present invention for the display unit 965, various images can be displayed.

[0303] Fig. 31B is a portable data terminal, having a housing 911, a display unit 912, a speaker 913 , an operation button 914, a camera 919, etc. Information can be input and output by the touch panel function of the display unit 912. By using the display device of one aspect of the present invention for the display unit 912, various images can be displayed.

[0304] Fig. 31C is a mobile phone, having a housing 951, a display unit 952, operation buttons 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The mobile phone is provided with a touch sensor on the display unit 952. Any operation such as making a call or inputting characters can be performed by touching the display unit 952 with a finger or a stylus. Also, the housing 951 and the display unit 952 are flexible and can be used after being folded as shown. It can be done. By using the display device of one aspect of the present invention for the display unit 952, various images can be displayed. can be displayed.

[0305] FIG. 31D is a video camera, which includes a first housing 901, a second housing 902, a display unit 903, an operation key 904, a lens 905, a connection part 906, a speaker 907, etc. The operation key 904 and the lens 905 are provided on the first housing 901, and the display unit 903 is provided on the second housing 902. By using the display device of one aspect of the present invention for the display unit 903, various images can be displayed. It can be done. By using the display device of one aspect of the present invention for the display unit 903, various images can be displayed.

[0306] FIG. 31E is a television, which includes a housing 971, a display unit 973, operation buttons 974, a speaker 97 5, a communication connection terminal 976, a light sensor 977, etc. A touch sensor is provided for the display unit 973, and an input operation can also be performed. By using the display device of one aspect of the present invention for the display unit 973, various images can be displayed. It can be done. By using the display device of one aspect of the present invention for the display unit 973, various images can be displayed.

[0307] FIG. 31F is a digital signage, which has a large display unit 922. For the digital signage, for example, a large display unit 922 is attached to the side surface of a pillar 921. By using the display device of one aspect of the present invention for the display unit 922, a display with high display quality can be performed. It can be done. By using the display device of one aspect of the present invention for the display unit 922, a display with high display quality can be performed.

[0308] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

Explanation of Reference Numerals

[0309] 10: Pixel, 11: Circuit, 11A: Circuit, 11B: Circuit, 12: Source Driver, 12A : Source Driver, 12B: Source Driver, 13: Gate Driver, 13A: Gate Driver River, 13B: Gate driver, 15: Display area, 16: Selection circuit, 17: Selection circuit, 18: Selection circuit, 19: Selection circuit, 20: Circuit, 21: Circuit, 101: Transistor, 1 02: Transistor, 103: Transistor, 104: Capacitor, 111: Transistor Ta, 112: Transistor, 113: Transistor, 114: Transistor, 115: T ransistor, 116: Transistor, 117: Capacitor, 118: Capacitor, 125 : Wiring, 126: Wiring, 127: Wiring, 128: Wiring, 129: Wiring, 131: Trans istor, 132: Transistor, 133: Transistor, 134: Transistor, 141: Capacitor, 142: Liquid crystal device, 143: Transistor, 144: Transistor, 1 45: Transistor, 146: Capacitor, 147: Light emitting device, 148: Transistor Ta, 149: Transistor, 151: Wiring, 152: Wiring, 153: Wiring, 154: Wiring 、155: Wiring, 156: Wiring, 161: Wiring, 162: Wiring, 163: Wiring, 164: Wiring, 165: Wiring, 166: Wiring, 170: Circuit, 171: Circuit, 215: Display unit, 2 21a: Scanning line drive circuit, 231a: Signal line drive circuit, 232a: Signal line drive circuit, 24 1a: Common line drive circuit, 723: Electrode, 726: Insulating layer, 728: Insulating layer, 729: Insulating Layer, 741: Insulating layer, 742: Semiconductor layer, 744a: Electrode, 744b: Electrode, 746: Elect rode, 771: Substrate, 772: Insulating layer, 810: Transistor, 811: Transistor, 8 20: Transistor, 821: Transistor, 825: Transistor, 826: Transistor Ta, 842: Transistor, 843: Transistor, 844: Transistor, 845: Transistor, 846: Transistor, 847: Transistor, 901: Housing, 902: Housing, 903: Display unit, 904: Operation key, 905: Lens, 906: Connection part, 907: Speaker, 911: Housing, 912: Display unit, 913: Speaker, 914: Operation button, 9 19: Camera, 921: Column, 922: Display unit, 951: Housing, 952: Display unit, 953: Operation button, 954: External connection port, 955: Speaker, 956: Microphone, 957: Ca mera, 961: Housing, 962: Shutter button, 963: Microphone, 965: Display unit, 9 66: Operation key, 967: Speaker, 968: Zoom lever, 969: Lens, 971: Housing, 973: Display unit, 974: Operation button, 975: Speaker, 976: Communication connection ter minal, 977: Light sensor, 4001: Substrate, 4003: Layer, 4004: Layer, 4005: She et material, 4006: Substrate, 4008: Liquid crystal layer, 4009: Composite layer, 4010: Transistor , 4011: Transistor, 4013: Liquid crystal device, 4014: Wiring, 4015: Electrode , 4016: Light-scattering type liquid crystal device, 4017: Electrode, 4018: FPC, 4019: Dif ferent anisotropic conductive layer, 4020: Capacitor, 4021: Electrode, 4022: Transistor, 402 3: Transistor, 4030: Electrode layer, 4031: Electrode layer, 4032: Insulating layer, 4033 : Insulating layer, 4035: Spacer, 4041: Printed circuit board, 4042: Integrated circuit, 410 2: Insulating layer, 4103: Insulating layer, 4104: Insulating layer, 4110: Insulating layer, 4111: Insul ating layer, 4112: Insulating layer, 4131: Coloring layer, 4132: Light-shielding layer, 4133: Insulating layer, 42 00: Input device, 4210: Touch panel, 4227: Electrode, 4228: Electrode, 4237 : Wiring, 4238: Wiring, 4239: Wiring, 4263: Substrate, 4272b: FPC, 42 73b: IC, 4340a: Backlight unit, 4340b: Backlight unit , 4341: Light guide plate, 4342: Light emitting device, 4344: Lens, 4345: Mirror, 4347: Printed circuit board, 4348: Reflective layer, 4352: Diffuser plate, 4510: Partition, 45 11: Light emitting layer, 4513: Light emitting device, 4514: Filling material

Claims

【Claim 1】 A display device having a first circuit, a second circuit, and pixels, wherein the first circuit and the second circuit are electrically connected, the first circuit and the pixels are electrically connected, the second circuit and the pixels are electrically connected, the first circuit has a function of outputting first data to the second circuit, the first circuit has a function of outputting the first data to the pixels, the second circuit has a function of outputting second data to the pixels based on the first data, when the potential of the first data is D1, the potential of the second data is D2, and the reference potential is V0, they satisfy the relationship V0 = (D1 + D2) / 2, and the pixels have a function of generating third data based on the first data and the second data, and a function of performing display according to the third data.

Images