Semiconductor device

Abstract

To provide a novel semiconductor device.SOLUTION: A semiconductor device has: a first transistor provided between a wire to which a video signal is supplied and a gate of a second transistor; a third transistor provided between the gate and a source of the second transistor; a fourth transistor connected to a back gate of the second transistor; a fifth transistor provided between the source of the second transistor and a light-emitting element; a sixth transistor connected to the source of the second transistor; and a seventh transistor connected to a gate of the fifth transistor. A channel length of the first transistor is longer than a channel length of each of the third transistor, the fourth transistor, and the seventh transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] In recent years, electronic devices such as smartphones and tablet computers have become widespread. In addition, goggle-type devices and eyeglass-type devices have been developed as electronic devices for virtual reality (VR), augmented reality (AR), and mixed reality (MR).

[0004] Examples of display devices included in these electronic devices include liquid crystal display devices, self-luminous display devices, etc. Self-luminous display devices include light-emitting elements such as organic EL (Electro Luminescence) elements and light-emitting diodes (LEDs).

[0005] For example, an organic EL element has a configuration in which a layer containing a light-emitting organic compound is sandwiched between a pair of electrodes. Light can be emitted by generating a potential difference between the pair of electrodes and passing a current through the layer containing the light-emitting organic compound. A display device using such an organic EL element does not require a backlight, which is necessary in liquid crystal display devices and the like, and therefore can realize a thin, lightweight, high-contrast, and low-power display device. For example, an example of a display device using an organic EL element is described in Patent Document 1.

[0006] Furthermore, Patent Document 2 discloses a circuit configuration that corrects variations in threshold voltage of transistors for each pixel in a pixel circuit that controls the light emission brightness of an organic EL element, thereby improving the display quality of a display device. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-324673 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-132816 Summary of the Invention [Problem to be solved by the invention]

[0008] On the other hand, depending on the configuration of the organic EL element, a high voltage may be required to achieve the required brightness. Therefore, a high voltage may be applied to at least some of the transistors that make up the pixel circuit. If a high voltage is applied to a transistor for a long period of time, the transistor's electrical characteristics may easily change. Such changes in the transistor's electrical characteristics can lead to a deterioration in the display quality of the display device, an increase in power consumption, and a decrease in reliability.

[0009] An object of one embodiment of the present invention is to provide a display device with high display quality. Another object of one embodiment of the present invention is to provide a high-resolution display device. Another object of one embodiment of the present invention is to provide a highly reliable display device. Another object of one embodiment of the present invention is to provide a display device with reduced power consumption. Another object of one embodiment of the present invention is to provide a novel display device. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0010] Note that the description of the above-mentioned problems does not preclude the existence of other problems. Those skilled in the art can naturally derive the other problems from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these problems (the above-mentioned problems and other problems). [Means for solving the problem]

[0011] (1) One embodiment of the present invention includes first to seventh transistors, first to third capacitors, and a light-emitting element, wherein the first to seventh transistors each have a gate, a first terminal, and a second terminal, the first to third capacitors and the light-emitting element each have a first terminal and a second terminal, the second transistor has a back-gate, and the second terminal of the first transistor is electrically connected to the gate of the second transistor, the first terminal of the third transistor, and the first terminal of the first capacitor, and the back-gate of the second transistor is electrically connected to the second terminal of the fourth transistor and the first terminal of the second capacitor. a gate of the fifth transistor is electrically connected to the first terminal of the third transistor, the second terminal of the first capacitance element, the second terminal of the second capacitance element, the first terminal of the fifth transistor, and the first terminal of the sixth transistor; a gate of the fifth transistor is electrically connected to the first terminal of the third capacitance element and the second terminal of the seventh transistor; and a second terminal of the fifth transistor is electrically connected to the second terminal of the third capacitance element and the first terminal of the light-emitting element; and a channel length of the first transistor is longer than the channel lengths of the third transistor, the fourth transistor, and the seventh transistor.

[0012] (2) Another embodiment of the present invention includes first to seventh transistors, first to third capacitors, and a light-emitting element, wherein the first to seventh transistors each have a gate, a first terminal, and a second terminal, the first to third capacitors and the light-emitting element each have a first terminal and a second terminal, the second transistor has a back-gate, and the second terminal of the first transistor is electrically connected to a gate of the second transistor, a first terminal of the third transistor, and a first terminal of the first capacitor, the back-gate of the second transistor is electrically connected to a second terminal of the fourth transistor and a first terminal of the second capacitor, and the second terminal of the second transistor is electrically connected to a gate of the third transistor, a first terminal of the fourth transistor, and a first terminal of the second capacitor. a gate of the fifth transistor is electrically connected to a first terminal of the third capacitive element and a second terminal of the seventh transistor; a second terminal of the fifth transistor is electrically connected to a second terminal of the seventh transistor; and a second terminal of the fifth transistor is electrically connected to the second terminal of the third capacitive element and a first terminal of the light-emitting element; the first transistor is a multi-gate transistor having a series number of three or more; and each of the third transistor, the fourth transistor, and the seventh transistor is a multi-gate transistor having a series number equal to or less than the series number of the first transistor.

[0013] Also, for example, the gate of the first transistor is electrically connected to the first wiring, the gate of the third transistor and the gate of the fourth transistor are electrically connected to the second wiring, the first terminal of the seventh transistor is electrically connected to the third wiring, the gate of the sixth transistor and the gate of the seventh transistor are electrically connected to the fourth wiring, the first terminal of the first transistor is electrically connected to the fifth wiring, the first terminal of the second transistor is electrically connected to the sixth wiring, the first terminal of the fourth transistor is electrically connected to the seventh wiring, the second terminal of the sixth transistor is electrically connected to the eighth wiring, and the second terminal of the light-emitting element is electrically connected to the ninth wiring.

[0014] The first transistor is preferably a transistor containing an oxide semiconductor in a semiconductor layer in which a channel is formed.The light-emitting element may be, for example, an organic EL element. [Effects of the Invention]

[0015] According to one embodiment of the present invention, a display device with high display quality can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, one embodiment of the present invention can provide a display device with reduced power consumption. Alternatively, a novel display device can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

[0016] Note that the description of the above effects does not preclude the existence of other effects. Those skilled in the art can naturally derive the other effects from the description in the specification, drawings, claims, etc., and can extract other effects from the description in the specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have all of these effects (the above effects and other effects). [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a diagram showing an example of a circuit configuration of a semiconductor device. [Figure 2] FIG. 2 is a diagram illustrating an example of a circuit configuration of a semiconductor device. [Figure 3] FIG. 3 is a diagram illustrating an example of a circuit configuration of a semiconductor device. [Figure 4] FIG. 4 is a diagram illustrating an example of a circuit configuration of a semiconductor device. [Figure 5] 5A and 5B are diagrams illustrating examples of the structure of a transistor. [Figure 6] FIG. 6 is a diagram illustrating an example of a circuit configuration of a semiconductor device. [Figure 7] FIG. 7 is a diagram illustrating an example of a circuit configuration of a semiconductor device. [Figure 8] FIG. 8 is a diagram illustrating an example of a circuit configuration of a semiconductor device. [Figure 9] FIG. 9 is a diagram illustrating an example of a circuit configuration of a semiconductor device. [Figure 10] FIG. 10 is a diagram illustrating an example of a circuit configuration of a semiconductor device. [Figure 11] FIG. 11 is a diagram illustrating an example of a circuit configuration of a semiconductor device. [Figure 12] FIG. 12 is a diagram illustrating an example of a circuit configuration of a semiconductor device. [Figure 13] FIG. 13 is a diagram illustrating an example of a circuit configuration of a semiconductor device. [Figure 14] FIG. 14 is a diagram illustrating an example of a circuit configuration of a semiconductor device. [Figure 15] FIG. 15 is a timing chart illustrating an example of the operation of the semiconductor device. [Figure 16] FIG. 16 is a diagram illustrating an example of the operation of the semiconductor device. [Figure 17] FIG. 17 is a diagram illustrating an example of the operation of the semiconductor device. [Figure 18] FIG. 18 is a diagram illustrating an example of the operation of the semiconductor device. [Figure 19] FIG. 19 is a diagram illustrating an example of the operation of the semiconductor device. [Figure 20] FIG. 20 is a diagram illustrating an example of the operation of the semiconductor device. [Figure 21] FIG. 21 is a diagram illustrating an example of the operation of the semiconductor device. [Figure 22] 22(A1) to (A7) and (B1) to (B6) are diagrams for explaining electrical connections. [Figure 23] 23A to 23C illustrate examples of the structure of a transistor. [Figure 24] 24A to 24C illustrate examples of the structure of a transistor. [Figure 25] 25A and 25B are diagrams illustrating examples of the structure of a transistor. [Figure 26] 26A and 26B are diagrams illustrating examples of the structure of a transistor. [Figure 27]27A and 27B are diagrams illustrating examples of the structure of a transistor. [Figure 28] 28A to 28C illustrate examples of the structure of a transistor. [Figure 29] 29A to 29C illustrate examples of the structure of a transistor. [Figure 30] 30A to 30C illustrate examples of the structure of a transistor. [Figure 31] 31A to 31E illustrate examples of the structure of a transistor. [Figure 32] 32A and 32B are diagrams illustrating examples of the structure of a transistor. [Figure 33] 33A to 33E illustrate examples of the structure of a transistor. [Figure 34] FIG. 34 is a diagram illustrating a configuration example of a transistor. [Figure 35] 35A to 35E illustrate examples of the structure of a transistor. [Figure 36] 36(A) to 36(D) are cross-sectional views illustrating a method for forming a metal oxide film. [Figure 37] 37(A) to 37(D) are cross-sectional views illustrating a method for forming a metal oxide film. [Figure 38] FIG. 38 is a diagram illustrating an example of a planar layout of a semiconductor device. [Figure 39] 39(A) and (B) are diagrams illustrating an example of a cross-sectional configuration of a semiconductor device. [Figure 40] FIG. 40 is a diagram illustrating an example of a planar layout of a semiconductor device. [Figure 41] FIG. 41 is a diagram illustrating an example of a planar layout of a semiconductor device. [Figure 42] FIG. 42 is a diagram illustrating an example of a planar layout of a semiconductor device. [Figure 43] 43(A) and (B) are diagrams illustrating an example of a cross-sectional configuration of a semiconductor device. [Figure 44]Fig. 44(A) is a perspective view showing an example of the configuration of a display device, and Figs. 44(B) to 44(F) are plan views showing an example of a pixel arrangement. [Figure 45] 45(A) to 45(D) are diagrams illustrating configuration examples of light-emitting elements. [Figure 46] 46(A) to 46(D) are diagrams illustrating configuration examples of light-emitting elements. [Figure 47] 47A to 47D are diagrams illustrating examples of the configuration of a light-emitting element. [Figure 48] 48(A) to 48(C) are diagrams illustrating examples of the configuration of a light-emitting element. [Figure 49] FIG. 49 is a block diagram showing an example of the configuration of a display device. [Figure 50] 50(A) and (B) are block diagrams showing examples of the configuration of a display device. [Figure 51] 51(A) and (B) are block diagrams showing examples of the configuration of a display device. [Figure 52] 52A to 52E are circuit diagrams showing configuration examples of a semiconductor device, and Fig. 52D is a timing chart showing an operation example of the semiconductor device. [Figure 53] 53(A) and (B) are diagrams showing configuration examples of a display device. [Figure 54] 54(A) to 54(D) are diagrams showing examples of electronic devices. [Figure 55] 55(A) to 55(F) are diagrams showing examples of electronic devices. [Figure 56] 56(A) to 56(G) are diagrams showing examples of electronic devices. [Figure 57] 57(A) and (B) are diagrams showing the reliability evaluation results of the transistors. [Figure 58] 58(A) and (B) are diagrams showing the reliability evaluation results of the transistors. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0019] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0020] In the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size, aspect ratio, etc. are not necessarily limited. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0021] In the configuration of the invention of the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, plan views, etc.

[0022] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components. Therefore, they do not limit the number of components or the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0023] In this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0024] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0025] In this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0026] In this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, depending on the situation or circumstances, terms such as "film" and "layer" may be interchanged with other terms without using terms such as "film" and "layer." For example, the term "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, the term "conductor" may be interchanged with the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" may be interchanged with the term "insulator." Or, the term "insulator" may be interchanged with the term "insulating layer" or "insulating film."

[0027] In this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" and "conductive layer" depending on the situation.

[0028] In this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Furthermore, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true, and terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Similarly, the reverse is also true, and terms such as "signal" may be changed to the term "potential."

[0029] In this specification, the term "source" refers to a source region, a source electrode, or a source wiring. The source region refers to one of two regions in a semiconductor layer that are adjacent to a channel formation region. The source electrode refers to a conductive layer that includes a portion connected to the source region.

[0030] In this specification, the term "drain" refers to a drain region, a drain electrode, or a drain wiring. The drain region refers to the other of two regions of a semiconductor layer that are adjacent to a channel formation region. The drain electrode refers to a conductive layer that includes a portion connected to the drain region.

[0031] In this specification, the term "gate" refers to a gate electrode or a gate wiring. The gate electrode is an electrode that overlaps with a semiconductor layer of a transistor and has a function of controlling the resistance between the source and drain of the transistor depending on a supplied voltage.

[0032] In this specification, one of the source or the drain of a transistor may be referred to as a "first terminal of the transistor", and the other of the source or the drain of the transistor may be referred to as a "second terminal of the transistor".

[0033] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -15° or more and 15° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0034] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchangeable. In this specification and elsewhere, unless otherwise specified, voltage and potential can be interchangeable.

[0035] In this specification, the high power supply potential VDD (hereinafter simply referred to as "VDD") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter simply referred to as "VSS"). The ground potential GND (hereinafter simply referred to as "GND") can also be used as VDD or VSS. For example, when VDD is GND, VSS is a lower potential than GND, and when VSS is GND, VDD is a higher potential than GND.

[0036] In this specification, the "on state" of a transistor means that the source and drain of the transistor are in a conductive state (a state in which electricity can pass through), and the "off state" of a transistor means that the source and drain of the transistor are in a non-conductive state (a state that can be considered to be electrically cut off).

[0037] In this specification, the term "on-state current" refers to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" refers to a current that flows between a source and a drain when a transistor is off.

[0038] In this specification and the like, potential H is a potential that turns on an n-channel field effect transistor (also referred to as an "n-type transistor") and turns off a p-channel field effect transistor (also referred to as a "p-type transistor"). Potential L is a potential that turns off an n-type transistor and turns on a p-type transistor. Therefore, potential H is a potential higher than potential L. Potential H may be equal to VDD. Potential L may be equal to VSS. Unless otherwise specified, the transistors described in this specification are enhancement-type (normally-off) n-type transistors.

[0039] In addition, in drawings and the like, to clearly indicate the potential of wiring, electrodes, etc., an "H" indicating a potential H or an "L" indicating a potential L may be added next to the wiring, electrode, etc. Furthermore, wiring, electrodes, etc. where a potential change has occurred may be marked with "H" or "L" in a box. Furthermore, when a transistor is in an off state, an "x" symbol may be added over the transistor. Furthermore, an arrow may be added to indicate the direction of current flow.

[0040] In this specification, when referring to counting values and measurement values, terms such as "same," "equal," or "uniform" (including synonyms thereof) are used, this includes a margin of error of plus or minus 10%, unless otherwise specified.

[0041] In addition, in the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, or Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0042] Generally, "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator. Furthermore, in this specification, one electrode of a capacitance element may be referred to as a "first terminal of the capacitance element," and the other electrode may be referred to as a "second terminal of the capacitance element."

[0043] Furthermore, in this specification, a "switch" has multiple terminals and has the function of switching (selecting) between a conductive state and a non-conductive state between the terminals. For example, when a switch has two terminals and both terminals are in a conductive state, the switch is said to be in an "on state." When both terminals are in a non-conductive state, the switch is said to be in an "off state." Note that switching to either a conductive state or a non-conductive state, or maintaining either a conductive state or a non-conductive state, may sometimes be referred to as "controlling the conductive state." Furthermore, in this specification, for example, when a switch has two terminals, one terminal may be referred to as a "first terminal of the switch," and the other terminal may be referred to as a "second terminal of the switch."

[0044] In other words, a switch is a device that has the function of controlling a conduction state. Alternatively, a switch is a device that has the function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, etc. can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0045] The switch may be an electrical switch, a mechanical switch, or the like. Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source and drain of the transistor can be considered to be short-circuited. The "non-conductive state" of the transistor refers to a state in which the source and drain of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0046] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. The switch has a mechanically movable electrode, and the movement of the electrode selects a conductive or non-conductive state.

[0047] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, or "[m,n]” may be added to the symbol.

[0048] In this specification, "connection" includes, for example, "electrical connection." When the term "electrical connection" is used to define the connection relationship between circuit elements as an object, "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, and conductive layers.

[0049] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signals or potential interactions occur between A and B, the circuit can be defined as "A and B are indirectly connected." Even if there is a time during the operation of the circuit when electrical signals or potential interactions do not occur between A and B, it can still be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as a thing. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can still be defined as "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signals or potential interactions occur between A and B when a power supply voltage is supplied to the circuit and the circuit is operating).

[0050] Specific examples of "indirect connection" are given below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in Figures 22(A1) and 22(A2). Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," assuming that the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes times when one transistor between A and B is in an off state or a non-conductive state. In the case where "A and B are indirectly connected," if multiple transistors are connected between A and B, each of the multiple transistors between A and B is assumed to be in an on state, a conductive state, or a state in which current can flow at least once, assuming that the circuit is operating. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," the multiple transistors between A and B may be in an off state or a non-conductive state at the same time or at different times. As another example, as shown in Figure 22(A3), if A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, this can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, if a constant potential V is supplied to C from a power supply or GND, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0051] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the circuit operation period, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitor is connected between A and B, as shown in Figure 22(A4). Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in Figure 22(A5). In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0052] Another example of a case where it cannot be said that "A and B are indirectly connected" is when there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 22(A6) and 22(A7), multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 22(A3), if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, the connection relationship will be the same as Figure 22(A6) and Figure 22(A7), so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0053] Although an example of "indirect connection" has been given above, as an example, the provision of "indirect connection" is included in the provision of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0054] Next, specific examples of "direct connection" are shown. An example of "A and B are directly connected" is when A and B are connected without any circuit element between them, as shown in Figures 22(B1), 22(B2), and 22(B3). When A and B are connected to a power supply that supplies a constant potential V or GND without any circuit element between them, as shown in Figures 22(B4) and 22(B5), it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." When A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in Figure 22(B6), it can also be said that "A and B are directly connected." Because A and V or B and V are connected via the source and drain of a transistor, it cannot be said that they are directly connected; instead, it can be said that "A and V are indirectly connected" or "B and V are indirectly connected."

[0055] Although an example of a "direct connection" has been given above, as an example, the provision of a "direct connection" is included in the provision of an "electrical connection," so if "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0056] Note that one embodiment of the present invention includes a configuration in which at least one of a gate, a source, and a drain of one or more transistors is not connected to anything or is connected to any node.Furthermore, one embodiment of the present invention includes a configuration in which nothing is input to one or more wirings or any signal or voltage is input to the wirings.

[0057] (Embodiment 1) A semiconductor device 10A according to one embodiment of the present invention will be described with reference to the drawings. The semiconductor device 10A can be used, for example, in a pixel of a display device.

[0058] <Configuration example> An example circuit configuration of a semiconductor device 10A is shown in Fig. 1. The semiconductor device 10A includes a pixel circuit 51A and a light-emitting element 61. The pixel circuit 51A includes transistors M1 to M7 and capacitors C1 to C3. In the semiconductor device 10A shown in Fig. 1, the transistors M1 to M7 are n-type transistors, and each of them has a threshold voltage (also referred to as "Vth") greater than 0V.

[0059] The gate of the transistor M1 is connected to the wiring GLa, one of the source and the drain is connected to the wiring DL, and the other of the source and the drain is connected to the gate of the transistor M2. The transistor M1 has a function of selecting whether to bring the gate of the transistor M2 and the wiring DL into a conductive state or a non-conductive state.

[0060] The gate of the transistor M2 is connected to one terminal of the capacitor C1, one of the source and the drain is connected to the wiring 101, and the other of the source and the drain is connected to the other terminal of the capacitor C1 (see FIG. 1). The transistor M2 also has a backgate. The backgate of the transistor M2 is connected to one terminal of the capacitor C2. The other terminal of the capacitor C2 is connected to the other of the source and the drain of the transistor M2.

[0061] The gate of the transistor M3 is connected to the wiring GLb, one of the source and the drain is connected to one terminal of the capacitor C1, and the other of the source and the drain is connected to the other terminal of the capacitor C1. The transistor M3 has a function of selecting whether to bring the gate of the transistor M2 and the other of the source and the drain into a conductive state or a non-conductive state.

[0062] The gate of the transistor M4 is connected to the wiring GLb, one of the source and the drain is connected to the wiring 102, and the other of the source and the drain is connected to one terminal of the capacitor C2 and the back gate of the transistor M2. The transistor M4 has a function of selecting whether to bring the wiring 102 and the one terminal of the capacitor C2 into a conductive state or a non-conductive state. The transistor M4 also has a function of selecting whether to bring the wiring 102 and the back gate of the transistor M2 into a conductive state or a non-conductive state.

[0063] The gate of the transistor M5 is connected to one terminal of the capacitance element C3, and one of the source or drain is connected to the other of the source or drain of the transistor M2, the other of the source or drain of the transistor M3, the other terminal of the capacitance element C1, the other terminal of the capacitance element C2, and one of the source or drain of the transistor M6. The other of the source or drain of the transistor M5 is connected to the other terminal of the capacitance element C3 and a first terminal (e.g., an anode terminal) of the light-emitting element 61. The second terminal (e.g., a cathode terminal) of the light-emitting element 61 is connected to the wiring 104.

[0064] The gate of the transistor M6 is connected to the wiring GLd, and the other of the source and the drain is connected to the wiring 103. The transistor M6 has a function of selecting whether to bring the other of the source and the drain of the transistor M2 and the wiring 103 into an electrically conductive state or an electrically non-conductive state.

[0065] The gate of the transistor M7 is connected to the wiring GLd, one of the source and the drain is connected to the wiring GLc, and the other of the source and the drain is connected to the gate of the transistor M5. The transistor M7 has a function of selecting whether to bring the gate of the transistor M5 and the wiring GLc into a conductive state or a non-conductive state.

[0066] In addition, the other terminals of the capacitance elements C1 and C2, the other of the source or drain of the transistor M2, the other of the source or drain of the transistor M3, one of the source or drain of the transistor M5, and one of the source or drain of the transistor M6 are connected, and the region where these are always at the same potential during circuit operation is called node ND1.

[0067] A region where one terminal of the capacitance element C2, the back gate of the transistor M2, and the other of the source or drain of the transistor M4 are connected and where these are always at the same potential during circuit operation is called a node ND2.

[0068] The other of the source and drain of the transistor M1, one of the source and drain of the transistor M3, one terminal of the capacitor C1, and the gate of the transistor M2 are connected together, and the region where these are always at the same potential during circuit operation is also referred to as a node ND3.

[0069] A region where the gate of the transistor M5, one terminal of the capacitor C3, and the other of the source and drain of the transistor M7 are connected and always have the same potential during circuit operation is also referred to as a node ND4.

[0070] The capacitor C1 has a function of maintaining a potential difference between the other of the source or drain of the transistor M2 and the gate of the transistor M2 when the node ND3 is floating. The capacitor C2 has a function of maintaining a potential difference between the other of the source or drain of the transistor M2 and the back gate of the transistor M2 when the node ND2 is floating. The capacitor C3 has a function of maintaining a potential difference between the other of the source or drain of the transistor M5 and the gate of the transistor M5 when the node ND4 is floating.

[0071] The transistor M2 has a function of controlling the amount of current Ie flowing through the light-emitting element 61. That is, the transistor M2 has a function of controlling the amount of light emitted by the light-emitting element 61. Therefore, the transistor M2 is also referred to as a "drive transistor." Among the transistors constituting the pixel circuit 51A, the transistor M1, the transistor M3, the transistor M4, the transistor M5, the transistor M6, and the transistor M7 function as switches.

[0072] The transistor M5 has the function of switching between conduction and non-conduction between the transistor M2 and the light-emitting element 61. When the transistor M5 is in the off state, the light-emitting element 61 does not emit light, and when the transistor M5 is in the on state, the light-emitting element 61 can emit light. Therefore, the transistor M5 is also called a "light-emitting transistor." In order to reliably pass the amount of current determined by the drive transistor to the light-emitting element 61, the transistor M5 must be reliably in the on state regardless of the values of the source potential and drain potential. The capacitive element C3 is a capacitive element for reliably turning the transistor M5 in the on state.

[0073] It is generally known that increasing the channel length L of a transistor improves the electrical characteristics (also called saturation characteristics) of the transistor in its saturation region. The driving transistor of the semiconductor device 10A operates in the saturation region, so saturation characteristics are important. On the other hand, saturation characteristics are not as important for a transistor functioning as a switch. Therefore, it is preferable that the channel length L of the driving transistor be longer than the channel length L of a transistor functioning as a switch. For example, among the transistors constituting the pixel circuit 51A, it is preferable that the channel length L of transistor M2 be longer than the channel lengths L of transistors M1, M3, M4, M5, M6, and M7.

[0074] The channel length L of the transistor M2 may be set to be the same as the channel length L of at least one of the transistors M1, M3, M4, M5, M6, and M7. The channel length L of the transistor M2 may also be set to be shorter than the channel length L of at least one of the transistors M1, M3, M4, M5, M6, and M7.

[0075] The inventors also found that increasing the channel length L of a transistor not only improves saturation characteristics but also increases transistor reliability. For example, when a potential lower than that of the source is applied to the gate of a transistor, the "Id-Vg characteristics," which are one of the transistor's electrical characteristics and indicate the change in drain current (Id) relative to the change in gate voltage (Vg), tend to shift in the negative direction. This makes the transistor more likely to become a normally-on transistor. Note that in this specification, applying a potential lower than that of the source to the gate of a transistor is also referred to as "a negative bias being applied to the gate." Also, applying a potential higher than that of the source to the gate of a transistor is also referred to as "a positive bias being applied to the gate."

[0076] The amount of shift in the electrical characteristics of a transistor is determined by the magnitude of the negative bias applied to the gate, the application time, the temperature, etc. The inventors have found that by increasing the channel length L of the transistor, the shift in the electrical characteristics that can occur when a negative bias is applied to the gate is less likely to occur.

[0077] Due to the operation of the semiconductor device 10A, a strong negative bias is likely to be applied to the gate of the transistor M1. If the electrical characteristics of the transistor M1 change and it becomes a normally-on type, it becomes difficult to maintain the potential of the node ND3, which is one of the causes of a decrease in the display quality of a display device using the semiconductor device 10A. Furthermore, if an even stronger negative bias is applied to the gate of the transistor M1 to reliably turn off the normally-on transistor M1, power consumption also increases. The inventors have found that by using a transistor with a long channel length L as the transistor M1, the effects of the negative bias can be mitigated, thereby improving the reliability and display quality of a display device using the semiconductor device 10A and reducing power consumption.

[0078] As described above, the strongest negative bias is likely to be applied to the gate of transistor M1 in the operation of semiconductor device 10A. Therefore, it is preferable that the channel length L of transistor M1 be longer than the channel lengths L of transistors M3, M4, M5, M6, and M7.

[0079] The channel length L of the transistor M1 may be set to be the same as the channel length L of at least one of the transistors M3, M4, M5, M6, and M7. The channel length L of the transistor M1 may also be set to be shorter than the channel length L of at least one of the transistors M3, M4, M5, M6, and M7.

[0080] Among the transistors constituting the semiconductor device 10A, the transistors most likely to be subjected to a strong negative bias after transistor M1 during circuit operation are transistors M3, M4, and M7 (see FIG. 2). However, the negative bias applied to the gates of transistors M3, M4, and M7 is weaker than the negative bias applied to the gate of transistor M1, and therefore they are less susceptible to the negative bias than transistor M1. Therefore, the channel length L of each of transistors M3, M4, and M7 can be made shorter than the channel length L of transistor M1.

[0081] Furthermore, among the transistors constituting the semiconductor device 10A, the transistors M5 and M6 are less susceptible to the negative bias in terms of circuit operation, and therefore the channel length L of each of the transistors M5 and M6 can be made shorter than the channel length L of each of the transistors M3, M4, and M7.

[0082] In this way, by setting the channel length L for each transistor constituting the semiconductor device 10A, the area occupied by the semiconductor device 10A can be reduced, the power consumption of the semiconductor device 10A can be reduced, and one or both of the resolution and definition of a display device using the semiconductor device 10A as a pixel can be improved.

[0083] 1 and 2 show an example in which the semiconductor device 10A is connected to four wirings GL (wirings GLa to GLd), but the wiring GLd can be omitted by connecting the gates of the transistors M6 and M7 to the wiring GLa. By not providing the wiring GLd, it is possible to improve one or both of the resolution and definition of a display device using the semiconductor device 10A as a pixel (see FIG. 3).

[0084] Furthermore, by not providing the wiring GLd, the occupation area of the semiconductor device 10A functioning as a pixel can be increased. Increasing the occupation area of the semiconductor device 10A improves the design freedom of the semiconductor device 10A, and the productivity of the semiconductor device 10A can be improved. Increasing the occupation area of the semiconductor device 10A can also increase the light-emitting area of the light-emitting element 61. Therefore, the light-emitting luminance of the light-emitting element 61 can be increased without changing the current density supplied to the light-emitting element 61. Furthermore, since the same light-emitting luminance can be obtained with a lower current density, the reliability of the light-emitting element 61 can be improved. Therefore, the reliability of the semiconductor device 10A can be improved. Furthermore, the reliability of a display device using the semiconductor device 10A as a pixel can be improved.

[0085] The inventors have also found that a multi-gate transistor, in which multiple transistors are connected in series and function essentially as a single transistor, can achieve the same effect as when the channel length L is increased. That is, the inventors have found that the saturation characteristics of the multi-gate transistor are also improved. The inventors have also found that a shift in electrical characteristics, which can occur when a negative bias is applied to the gate, is less likely to occur in the multi-gate transistor.

[0086] 4 shows an example of the circuit configuration of the semiconductor device 10B. The semiconductor device 10B includes a pixel circuit 51B and a light-emitting element 61. The semiconductor device 10B has the same configuration as the semiconductor device 10A. The pixel circuit 51B has the same circuit configuration as the pixel circuit 51A. Therefore, to reduce repetition of explanation, differences between the semiconductor device 10B and the semiconductor device 10A will be mainly described.

[0087] 4 has a configuration in which three transistors are connected in series. The semiconductor device 10B differs from the semiconductor device 10A in that the transistor M1 is a multi-gate transistor in which three or more transistors are connected in series and function essentially as one transistor.

[0088] [Multi-gate transistor] 5A and 5B show a configuration example of a transistor Mx that is a multi-gate transistor applicable to the transistor M1.

[0089] 5A has a configuration in which a transistor Mm[1], a transistor Mm[2], and a transistor Mm[3] are connected in series. Specifically, the transistor Mx shown in FIG. 5A has a configuration in which one of the source or the drain of the transistor Mm[1] is connected to a terminal S, the other of the source or the drain of the transistor Mm[1] is connected to one of the source or the drain of the transistor Mm[2], the other of the source or the drain of the transistor Mm[2] is connected to one of the source or the drain of the transistor Mm[3], and the other of the source or the drain of the transistor Mm[3] is connected to a terminal D. In addition, the gates of the transistors Mm[1], Mm[2], and Mm[3] are connected to each other and to a terminal G.

[0090] 5A has a function of switching conduction or non-conduction between the terminal S and the terminal D by changing the potential of the terminal G. Therefore, the transistor Mx shown in FIG. 5A includes the transistor Mm[1], the transistor Mm[2], and the transistor Mm[3] and functions as one transistor.

[0091] That is, in FIG. 5A, one of the source or the drain of the transistor Mx is connected to the terminal S, the other of the source or the drain is connected to the terminal D, and the gate is connected to the terminal G. A transistor that includes three transistors and essentially functions as one transistor, such as the transistor Mx shown in FIG. 5A, is also called a triple-gate transistor. Note that a transistor that includes two transistors and essentially functions as one transistor is also called a double-gate transistor. A transistor that includes multiple transistors and essentially functions as one transistor is called a "multi-gate transistor" or a "multi-gate transistor."

[0092] In this specification, the number of transistors contained in a transistor Mx and connected in series is referred to as the "series number." Fig. 5B shows an example of the configuration of a transistor Mx when the series number is n (n is an integer of 2 or more). In Fig. 5B, the i-th transistor Mm (i is an integer of 2 or more and less than n) when n is 3 or more is represented as transistor Mm[i].

[0093] In the transistor Mx shown in FIG. 5B, one of the source and drain of the transistor Mm[1] is connected to the terminal S, and one of the source and drain of the transistor Mm[i] is connected to the other of the source and drain of the transistor Mm[i-1]. The other of the source and drain of the transistor Mm[i] is connected to the source or drain of the transistor Mm[i+1]. The other of the source and drain of the transistor Mm[n] is connected to the terminal D. The gates of the transistors Mm[1] to Mm[n] are connected to each other and to the terminal G.

[0094] The number of series-connected transistors Mx applicable to the transistor M1 may be 2 or more, but is preferably 3 or more. By using three or more series-connected transistors Mx as the transistor M1, fluctuations in the electrical characteristics of the transistor M1 can be suppressed, and the reliability of the semiconductor device 10B can be improved.

[0095] As with the semiconductor device 10A, a strong negative bias is likely to be applied to the gate of the transistor M1 in the semiconductor device 10B due to circuit operation. Therefore, when the transistor M1 becomes a normally-on type, it becomes difficult to maintain the potential of the node ND3, which is one of the causes of a decrease in display quality of a display device using the semiconductor device 10B. It is also one of the causes of an increase in power consumption of a display device using the semiconductor device 10B.

[0096] The inventors have found that using a multi-gate transistor for transistor M1 can mitigate the effects of a negative bias, improve the display quality of a display device using semiconductor device 10B, and reduce power consumption. The inventors have also found that using three or more series-connected transistors Mx is particularly effective in mitigating the effects of a negative bias. Using three or more series-connected transistors Mx for transistor M1 can improve the reliability and display quality of a display device using semiconductor device 10B and reduce power consumption. The number of series-connected transistors Mx and their reliability will be described in the Examples.

[0097] Note that a transistor having a back gate can also be used as a transistor other than the transistor M2.

[0098] The gate and back gate of a transistor are arranged to sandwich a channel formation region of a semiconductor layer. Both the gate and back gate are formed of a conductive layer or a semiconductor layer with low resistivity. The back gate can function in the same way as the gate.

[0099] When the gate is used to control the on / off state of a transistor, the potential of the back gate can be the same as that of the gate. For example, when a transistor is turned on, supplying a potential that turns the transistor on to both the gate and the back gate can increase the on-state current compared to when a potential is supplied to only one of them. In addition, controlling the potential of the back gate independently of the gate can adjust the threshold voltage of the transistor.

[0100] Since the gate and the back gate are formed of a conductive layer or the like, sandwiching the channel formation region of the semiconductor layer between the gate and the back gate makes it difficult for an electric field generated outside the transistor to act on the channel formation region (also referred to as an "electric field shielding effect"). Therefore, providing a back gate in a transistor stabilizes the operation of the transistor. Furthermore, providing a back gate in a transistor reduces variations in characteristics among multiple transistors. Providing a back gate in a transistor can improve the reliability of the transistor. Therefore, the reliability of a semiconductor device including the transistor can be improved. Note that the electric field shielding effect can be obtained even when one or both of the gate and the back gate are in an electrically floating state (also referred to as a "floating state"), but the effect can be enhanced by supplying a potential to the gate and the back gate.

[0101] Furthermore, when a channel formation region of a transistor is irradiated with light, the electrical characteristics of the transistor may fluctuate. Furthermore, when the channel formation region of the transistor is irradiated with light while a voltage is applied to the transistor, the electrical characteristics of the transistor may deteriorate. That is, the reliability of the transistor may decrease. By using a light-blocking conductive material for both the gate and the back gate, deterioration of the electrical characteristics of the transistor can be suppressed and the reliability can be improved.

[0102] 6 shows an example of a circuit configuration of a semiconductor device 10C in which not only the transistor M2 but also the transistors M1 and M3 to M7 are configured as transistors having back gates. The semiconductor device 10C includes a pixel circuit 51C and a light-emitting element 61. The semiconductor device 10C has the same circuit configuration as the semiconductor device 10B, but differs in that all the transistors configuring the circuit use transistors having back gates.

[0103] 6 shows an example in which the gate and the back gate are connected in each of the transistors M1 and M3 to M7, but it is not necessary to provide a back gate in all transistors included in the semiconductor device.

[0104] Although the transistor M1 is shown as a multi-gate transistor with a back gate in FIG. 6, it is possible to make the transistor M1 a single-gate transistor with a back gate, as shown in FIG.

[0105] Furthermore, the gate and the back gate are not connected, and any potential can be supplied to the back gate. Note that the potential supplied to the back gate is not limited to a fixed potential. The potential supplied to the back gate of each transistor included in the semiconductor device may be different for each transistor or may be the same for each transistor.

[0106] [Variations] In the semiconductor device 10B shown in FIG. 4, the transistor Mx is used as the transistor M1, but the transistor Mx can also be used as another transistor.

[0107] 8 shows an example of the circuit configuration of a semiconductor device 10D, which is a variation of the semiconductor device 10B. The semiconductor device 10D includes a pixel circuit 51D and a light-emitting element 61. The semiconductor device 10D has the same circuit configuration as the semiconductor device 10B, but differs in that in addition to the transistor M1, the semiconductor device 10D uses multi-gate transistors with three transistors connected in series as the transistors M2, M3, M4, and M7.

[0108] By using a multi-gate transistor for the transistor M2, which is the drive transistor, the saturation characteristics of the transistor M2 can be improved. In the semiconductor device 10D, the transistors M3, M4, and M7 are also transistors that are most susceptible to negative bias after the transistor M1. By using multi-gate transistors for the transistors M3, M4, and M7 in addition to the transistor M1, the semiconductor device 10D can be made more reliable than the semiconductor device 10B.

[0109] As described above, the transistors M3, M4, and M7 are less susceptible to the effects of a negative bias than the transistor M1. Therefore, it is possible to use multi-gate transistors, which are connected in series with fewer transistors than the transistor M1, as the transistors M3, M4, and M7. Furthermore, the transistors M5 and M6 are less susceptible to the effects of a negative bias. Therefore, it is possible to use single-gate transistors as the transistors M5 and M6.

[0110] Furthermore, transistors having back gates can be used as the transistors constituting the semiconductor device 10D. Fig. 9 shows an example of the circuit configuration of a semiconductor device 10E, which is a modification of the semiconductor device 10D. The semiconductor device 10E includes a pixel circuit 51E and a light-emitting element 61. The semiconductor device 10E differs from the semiconductor device 10D in that transistors having back gates are used as the transistors M1, M3, M4, M5, M6, and M7 constituting the semiconductor device 10E.

[0111] FIG. 10 shows an example of the circuit configuration of a semiconductor device 10F, which is a variation of the semiconductor device 10D. The semiconductor device 10F includes a pixel circuit 51F and a light-emitting element 61. The semiconductor device 10F differs from the semiconductor device 10D in that three multi-gate transistors are used for the transistors M1 and M2, and two multi-gate transistors are used for the transistors M3, M4, and M7. By reducing the number of multi-gate transistors connected in series for the transistors M3, M4, and M7, the area occupied by the semiconductor device 10F can be reduced. This allows for improved resolution and / or definition of a display device using the semiconductor device 10F as a pixel.

[0112] Furthermore, transistors having back gates can be used as the transistors constituting the semiconductor device 10F. Fig. 11 shows an example of the circuit configuration of a semiconductor device 10G, which is a variation of the semiconductor device 10F. The semiconductor device 10G includes a pixel circuit 51G and a light-emitting element 61. The semiconductor device 10G differs from the semiconductor device 10F in that transistors having back gates are used as the transistors M1, M3, M4, M5, M6, and M7 constituting the semiconductor device 10G.

[0113] 12, multi-gate transistors can also be used for transistors M1 to M7. FIG. 12 shows an example of the circuit configuration of a semiconductor device 10H, which is a modification of the semiconductor device 10B. The semiconductor device 10H is also a modification of the semiconductor device 10D. The semiconductor device 10H includes a pixel circuit 51H and a light-emitting element 61. The semiconductor device 10H has the same circuit configuration as the semiconductor device 10B, but differs in that three multi-gate transistors connected in series are used for transistors M1 to M7.

[0114] By using multi-gate transistors for all the transistors that make up the pixel circuit 51H, it is possible to realize a semiconductor device 10H that is more reliable than the semiconductor device 10B. It is also possible to realize a semiconductor device 10H that is even more reliable than the semiconductor device 10D.

[0115] 13 shows an example of a circuit configuration of a semiconductor device 10I, which is a modification of the semiconductor device 10H. The semiconductor device 10I includes a pixel circuit 51I and a light-emitting element 61. The semiconductor device 10I differs from the semiconductor device 10H in that the transistors M1 to M7 include multi-gate transistors with back gates.

[0116] Although this embodiment shows an example in which the semiconductor device 10 (semiconductor devices 10A to 10I) is configured using n-channel transistors, one embodiment of the present invention is not limited thereto. P-channel transistors can also be used for some or all of the transistors included in the semiconductor device 10.

[0117] The pixel circuit 51 (pixel circuits 51A to 51I) according to one embodiment of the present invention can use transistors with various structures. For example, transistors with various structures such as planar type, FIN type, TRI-GATE type, top-gate type, bottom-gate type, and tandem type (structure in which gates are arranged above and below a channel) can be used. Furthermore, as the transistor according to one embodiment of the present invention, a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used.

[0118] For example, an OS transistor (a transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed) can be used as a transistor included in the pixel circuit 51. Since an oxide semiconductor has a band gap of 2 eV or more, its off-state current is extremely small.

[0119] The off-state current of an OS transistor per 1 μm of channel width at room temperature is 1 aA (1 × 10 -18 A) Below, 1zA(1×10 -21 A) or less, or 1yA (1 x 10 -24 The off-state current of a Si transistor (a transistor containing silicon in a semiconductor layer in which a channel is formed) per 1 μm of channel width at room temperature can be 1 fA (1×10 -15 A) More than 1pA (1×10 -12 Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude lower than that of a Si transistor.

[0120] Using OS transistors as the transistors that make up the pixel circuit 51 allows the charge written to each node to be retained for a long period of time. For example, when displaying a still image that does not require rewriting for each frame, it is possible to continue displaying the image even if the operation of the peripheral driving circuit is stopped. This driving method of stopping the operation of the peripheral driving circuit while displaying a still image is also called "idling stop driving." By performing idling stop driving, the power consumption of the display device can be reduced.

[0121] By using an OS transistor as the transistor M1, the charge written to the node ND3 can be held for a long period of time. Furthermore, by using OS transistors as the transistors M1 and M3, the charge written to the node ND3 can be held for a longer period of time. By using an OS transistor as the transistor M4, the charge written to the node ND2 can be held for a long period of time. By using an OS transistor as the transistor M7, the charge written to the node ND4 can be held for a long period of time.

[0122] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range of room temperature to 200°C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. A semiconductor device including an OS transistor operates stably and has high reliability even in a high-temperature environment.

[0123] In addition, OS transistors have a high withstand voltage between the source and drain. By using OS transistors as transistors constituting the pixel circuit 51, operation is stable even when there is a large potential difference between the wiring 101 and the wiring 104, and a highly reliable semiconductor device can be realized. In particular, it is preferable to use OS transistors as one or both of the transistors M2 and M5.

[0124] As described above, among the transistors constituting the pixel circuit 51, the transistors M1, M3, M4, M5, M6, and M7 function as switches. Therefore, the semiconductor device 10 can be shown as in FIG.

[0125] In FIG. 14, switch SW1 corresponds to transistor M1, switch SW3 corresponds to transistor M3, switch SW4 corresponds to transistor M4, switch SW5 corresponds to transistor M5, switch SW6 corresponds to transistor M6, and switch SW7 corresponds to transistor M7.

[0126] Therefore, the first terminal of the switch SW1 corresponds to one of the source and drain of the transistor M1, and the second terminal of the switch SW1 corresponds to the other of the source and drain of the transistor M1, as do the switches SW3 to SW7.

[0127] As the light-emitting element 61, various display elements can be used, such as EL elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), micro LEDs, QLEDs (Quantum-dot Light Emitting Diodes), electron-emitting elements, etc.

[0128] <Example of operation> Next, an operation example of the semiconductor device 10B will be described with reference to the drawings. FIG. 15 is a timing chart illustrating an operation example of the semiconductor device 10B. FIGS. 16 to 21 are circuit diagrams illustrating an operation example of the semiconductor device 10B. Note that one embodiment of the present invention is all or part of the circuit configuration described in this specification, etc. Therefore, one embodiment of the present invention satisfies the support requirement and the clarity requirement even if it does not include all or part of the operations described in this specification, etc.

[0129] A video signal Vdata is supplied to the wiring DL. A potential Va is supplied to the wiring 101, a potential V1 is supplied to the wiring 102, a potential V0 is supplied to the wiring 103, and a potential Vc is supplied to the wiring 104. Either a potential H or a potential L is supplied to each of the wirings GLa, GLb, GLc, and GLd.

[0130] The potential Va is an anode potential, and the potential Vc is a cathode potential. The potential V1 is a potential higher than the potential V0, and is a potential at which a transistor can be turned on by supplying the potential V1 to the gate of the transistor. The potential V0 is a potential at which a transistor can be turned off by supplying the potential V0 to the gate of the transistor. The potential V0 is, for example, 0 V or a potential L. In this embodiment, the potential V0 is set to 0 V, and the potential V1 is set to 3 V. The potential Va is set to 15 V, and the potential Vc is set to 0 V. The gate capacitance and backgate capacitance of the transistor M2 are assumed to be equal to each other.

[0131] The semiconductor device 10B has a function of controlling, in response to a video signal Vdata supplied from the wiring DL, the magnitude of a current Ie (see FIG. 20) flowing through the light-emitting element 61. The light emission brightness of the light-emitting element 61 is controlled by the magnitude of the current Ie.

[0132] The current Ie flowing through the light-emitting element 61 is mainly determined by the video signal Vdata and the Vth of the transistor M2. Therefore, even if the same video signal Vdata is supplied to multiple pixel circuits, if the Vth of the transistor M2 included in each pixel circuit differs, the current Ie will differ for each pixel. Therefore, variations in the Vth of the transistor M2 are one cause of deterioration in display quality.

[0133] Therefore, the variation in the current Ie is reduced by obtaining the Vth of the transistor M2 for each pixel. Note that the operation of obtaining the Vth of the transistor M2 is sometimes called a "threshold correction operation."

[0134] In an initial state, a potential L is supplied to the wirings GLa, GLb, and GLc, and a potential H is supplied to the wiring GLd.

[0135] [Vth correction operation] First, in period T11, a reset operation is performed. Specifically, a potential H is supplied to the wiring GLb, the wirings GLa and GLc are kept at potential L, and the wiring GLd is kept at potential H (see FIGS. 15 and 16). In period T11, the transistors M1 and M5 are off, the transistors M3 and M4 are on, and the transistors M6 and M7 are on.

[0136] The node ND1 is supplied with a potential V0 via a transistor M6, the node ND3 is supplied with a potential V0 via a transistor M6 and a transistor M3, and the node ND2 is supplied with a potential V1 via a transistor M4.

[0137] Next, in a period T12, the potential L is supplied to the wiring GLd (see FIGS. 15 and 17), which turns off the transistors M6 and M7.

[0138] Because the potential V1 is supplied to the node ND2 through the transistor M4, the transistor M2 is on. Therefore, the potential of the node ND1 increases through the wiring 101 and the transistor M2. In addition, because the transistor M3 is also on, the potential of the node ND3 also increases. Specifically, the potentials of the nodes ND1 and ND3 increase to a value obtained by subtracting the Vth of the transistor M2 from the potential V1.

[0139] Next, in a period T13, a potential L is supplied to the wiring GLb (see FIGS. 15 and 18). As a result, the transistors M3 and M4 are turned off. Therefore, the nodes ND1, ND2, and ND3 are brought into a floating state, and the charges supplied to the respective nodes are held.

[0140] [Video signal writing operation] In a period T14, a potential H is supplied to the wirings GLa, GLc, and GLd (see FIGS. 15 and 19). When the potential H is supplied to the wiring GLa, the transistor M1 is turned on, and the video signal Vdata is supplied to the node ND3. When the potential H is supplied to the wiring GLd, the transistors M6 and M7 are turned on.

[0141] When the transistor M6 is turned on, a potential V0 is supplied to the node ND1. The node ND2 is in a floating state, and the nodes ND1 and ND2 are capacitively coupled via the capacitive element C2. Therefore, when the potential of the node ND1 changes from V1-Vth to V0, the potential of the node ND2 also changes. In this embodiment, the potential V0 is 0V, so the potential of the node ND2 becomes the potential V1- (potential V1-Vth). That is, the potential of the node ND2 becomes Vth.

[0142] Furthermore, when the transistor M7 is turned on, charge is supplied to the node ND4 from the wiring GLc. The potential of the node ND4 rises to a value obtained by subtracting the Vth of the transistor M7 from the potential H. In this embodiment and other cases, if the potential H is 6 V and the Vth of the transistors M5 and M7 is 1 V, the potential of the node ND4 (potential H-Vth) becomes 5 V. Therefore, the transistor M5 is turned on.

[0143] [Light Emitting Operation] In period T15, a potential L is supplied to the wirings GLa and GLd (see FIGS. 15 and 20). As a result, the transistors M1 and M6 are turned off, and a current flows from the wiring 101 to the wiring 104. That is, a current Ie flows to the light-emitting element 61, and the light-emitting element 61 emits light with a luminance corresponding to the current Ie. Furthermore, when a current flows from the wiring 101 to the wiring 104, the potentials of the node ND1 and the anode terminal of the light-emitting element 61 increase.

[0144] Also, node ND3 is in a floating state, and nodes ND1 and ND3 are capacitively coupled via capacitance element C1. As described above, node ND2 is in a floating state, and nodes ND1 and ND2 are capacitively coupled via capacitance element C2. When the potential of node ND1 changes from potential V0 to potential Va1, the potentials of nodes ND2 and ND3 also change in the same way. Here, the potential of node ND3 becomes video signal Vdata+potential Va1. Also, the potential of node ND2 becomes Vth+potential Va1.

[0145] That is, even if the source potential of transistor M2 changes, the potential difference between the gate and source of transistor M2 remains at the video signal Vdata. Similarly, the potential difference between the back gate and source of transistor M2 remains at Vth. Capacitor C1 has the function of maintaining the potential difference between nodes ND1 and ND3. Capacitor C2 has the function of maintaining the potential difference between nodes ND1 and ND2.

[0146] Furthermore, the anode terminal of the light-emitting element 61 and node ND4 are capacitively coupled via the capacitive element C3. Therefore, when the potential of the anode terminal of the light-emitting element 61 changes from potential V0 to potential Va2, the potential of node ND4 also changes similarly. Here, the potential of node ND4 becomes potential H-Vth+potential Va2. That is, even if the potential of the anode terminal of the light-emitting element 61 changes, the potential difference between the gate and source of transistor M5 is maintained at potential H-Vth.

[0147] For example, if the gate of transistor M5 is at a fixed potential, an increase in the source potential of transistor M5 reduces the potential difference between the gate and source. When the potential difference between the gate and source falls below the threshold voltage of transistor M5, transistor M5 turns off. Therefore, when the anode potential of light-emitting element 61 is increased, a high potential must also be supplied to the gate of transistor M5, and an additional power supply or power supply circuit is required for this purpose.

[0148] In the semiconductor device 10B according to one embodiment of the present invention, a capacitive element C3 is provided between the gate and source of the transistor M5 to form a bootstrap circuit, so that the transistor M5 can be kept on even if the anode potential is increased without adding a power supply circuit. Therefore, the current Ie can be stably supplied to the light-emitting element 61. The capacitive element C3 may be referred to as a "bootstrap capacitance." The capacitive elements C1 and C2 also function as bootstrap capacitances.

[0149] The semiconductor device 10B according to one aspect of the present invention is suitable not only for a light emitting device with a single structure, but also for a light emitting device with a tandem structure that requires a higher driving voltage than a light emitting device with a single structure.

[0150] As described above, the amount of current Ie flowing through the light-emitting element 61 is determined by the video signal Vdata and the Vth of the transistor M2. In the semiconductor device 10B according to one aspect of the present invention, the influence of variations in the Vth of the transistor M2 is mitigated, so that the current Ie corresponding to the video signal Vdata can be supplied to the light-emitting element 61 more accurately. Furthermore, accurate control of the current Ie can be achieved, which can improve color reproducibility of intermediate tones. This can improve the display quality of the display device.

[0151] [Extinguishing operation] In period T16, a potential L is supplied to the wiring GLc, and a potential H is supplied to the wiring GLd (see FIGS. 15 and 21). As a result, the transistors M6 and M7 are turned on. When the transistor M6 is turned on, a potential V0 is supplied to the node ND1 from the wiring 103. When the transistor M7 is turned on, the potential L is supplied to the node ND4 from the wiring GLc, and the transistor M5 is turned off. When the transistor M5 is turned off, no current flows to the light-emitting element 61, and the light-emitting element 61 stops emitting light.

[0152] When the potential of the node ND1 changes from the potential Va1 to the potential V0, the potential of the node ND2 becomes Vth and the potential of the node ND3 becomes Vdata.

[0153] Display devices that use light-emitting elements such as EL elements as display elements can keep the light-emitting elements lit during one frame period. This type of driving method is also called "hold type" or "hold type driving." By using hold type driving as the driving method for a display device, it is possible to reduce flickering on the display screen. On the other hand, hold type driving is prone to causing afterimages and blurred images when displaying moving images. The resolution perceived by humans when displaying moving images is also called "video resolution." In other words, hold type driving is prone to reducing video resolution.

[0154] Also known is "black insertion driving," which improves image blur and afterimages in moving image displays. "Black insertion driving" is also called "pseudo-impulse type" or "pseudo-impulse type driving." Black insertion driving is a driving method in which black is displayed every other frame, or for a certain period of time within one frame.

[0155] The semiconductor device 10B according to one embodiment of the present invention can easily realize black insertion driving by the extinction operation. A display device using the semiconductor device 10B according to one embodiment of the present invention is less likely to experience a decrease in moving image resolution, and can realize moving image display with high display quality.

[0156] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0157] (Embodiment 2) In this embodiment, a transistor that can be used in a semiconductor device according to one embodiment of the present invention will be described.

[0158] <Transistor configuration example 1> 23A is a plan view of a transistor 200A that can be used for a semiconductor device of one embodiment of the present invention. The transistor 200A is an example of a planar transistor. In this specification, a planar transistor refers to a transistor in which a source electrode and a drain electrode are located at the same height or approximately the same height and a current flowing through a semiconductor has a lateral component.

[0159] Figure 23(B) is a cross-sectional view taken along the line A1-A2 indicated by the dashed line in Figure 23(A). Figure 23(C) is a cross-sectional view taken along the line A3-A4 indicated by the dashed line in Figure 23(A). Note that in the plan view of Figure 23(A), some elements are omitted for clarity. Some elements may also be omitted in other plan views.

[0160] The transistor 200A has an insulating layer 202 over a substrate 201 and a semiconductor layer 203 over the insulating layer 202. The transistor 200A also has an insulating layer 204 over the insulating layer 202 and the semiconductor layer 203. The transistor 200A also has a conductive layer 205 over the insulating layer 204. The semiconductor layer 203 and the conductive layer 205 have a region where they overlap with each other with the insulating layer 204 interposed therebetween.

[0161] The semiconductor layer 203 has a region 203a, a channel formation region 203b, and a region 203c. The region 203a functions as either a source region or a drain region. The region 203c functions as the other of the source region and the drain region. In the semiconductor layer 203, a region overlapping with the conductive layer 205 functions as the channel formation region 203b. Therefore, the conductive layer 205 functions as the gate electrode of the transistor 200A. The insulating layer 204 functions as a gate insulating layer of the transistor 200A.

[0162] The length of the channel formation region 203b in the X direction is the channel length L of the transistor 200A (see FIG. 23B). The length of the channel formation region 203b in the Y direction is the channel width W of the transistor 200A (see FIG. 23C).

[0163] An insulating layer 206 is provided over the insulating layer 204 and the conductive layer 205. An opening 207a is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with a region 203a of the semiconductor layer 203. An opening 207b is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with a region 203c of the semiconductor layer 203.

[0164] A conductive layer 208a is provided overlapping the insulating layer 206 and the opening 207a, and a conductive layer 208b is provided overlapping the insulating layer 206 and the opening 207b. The conductive layer 208a is connected to the region 203a of the semiconductor layer 203 at the bottom of the opening 207a. The conductive layer 208b is connected to the region 203c of the semiconductor layer 203 at the bottom of the opening 207b. Thus, the conductive layer 208a functions as one of the source and drain electrodes of the transistor 200A, and the conductive layer 208b functions as the other of the source and drain electrodes of the transistor 200A.

[0165] Furthermore, an insulating layer 209 is provided on the insulating layer 206 and the conductive layer 208 (conductive layer 208a and conductive layer 208b).

[0166] <Transistor configuration example 2> 24A is a plan view of a transistor 200B that can be used for a semiconductor device of one embodiment of the present invention. The transistor 200B is a variation of the transistor 200A. To avoid repetition, differences between the transistor 200B and the transistor 200A will be mainly described.

[0167] Fig. 24(B) is a cross-sectional view taken along the line A1-A2 indicated by the dashed line in Fig. 24(A), and Fig. 24(C) is a cross-sectional view taken along the line A3-A4 indicated by the dashed line in Fig. 24(A).

[0168] The transistor 200B differs from the transistor 200A in that a conductive layer 219 is provided between the substrate 201 and the insulating layer 202. The conductive layer 219 functions as a backgate electrode of the transistor 200B. Therefore, the conductive layer 219 has a region that overlaps with the channel formation region 203b in a planar view. The conductive layer 219 preferably has a region that extends beyond the end of the channel formation region 203b in a planar view. By surrounding the channel formation region 203b with the conductive layer 205 and the conductive layer 219, the electric field shielding effect described in the above embodiment can be improved.

[0169] <Transistor configuration example 3> 25A is a plan view of a transistor 200C that can be used in a semiconductor device according to one embodiment of the present invention, and FIG 25B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in FIG 25A.

[0170] The transistor 200C includes an insulating layer 202 over a substrate 201 and a conductive layer 255 over the insulating layer 202. The transistor 200C also includes an insulating layer 257 over the conductive layer 255, an insulating layer 258 over the insulating layer 257, and an insulating layer 259 over the insulating layer 258. Note that in this specification, the insulating layer 257, the insulating layer 258, and the insulating layer 259 may be collectively referred to as an insulating layer 256 or a spacer layer. The transistor 200C also includes a conductive layer 261 over the insulating layer 259.

[0171] An opening 262 penetrating the conductive layer 261, the insulating layer 259, the insulating layer 258, and the insulating layer 257 is provided in a region overlapping with part of the conductive layer 255. A semiconductor layer 263 is provided to cover the inner wall of the opening 262.

[0172] The semiconductor layer 263 has a region overlapping the bottom of the opening 262 and a region overlapping the side surface of the opening 262. That is, the semiconductor layer 263 has a region in contact with the insulating layer 256 inside the opening 262. The semiconductor layer 263 also has a region in contact with the conductive layer 255 and a region in contact with the conductive layer 261 inside the opening 262.

[0173] An insulating layer 264 is provided over the insulating layer 259, the conductive layer 261, and the semiconductor layer 263. A conductive layer 265 is provided over the insulating layer 264. The conductive layer 265 has a region overlapping with the semiconductor layer 263. The conductive layer 265 has a region overlapping with the semiconductor layer 263 with the insulating layer 264 interposed therebetween.

[0174] The insulating layer 264 and the conductive layer 265 each have a region that overlaps with the opening 262. The insulating layer 264 and the conductive layer 265 each have a region that overlaps with the inside of the opening 262. Inside the opening 262, the semiconductor layer 263 has a region that overlaps with the conductive layer 265 via the insulating layer 264 and a region that overlaps with the side surface of the opening 262 (the side surface of the insulating layer 256).

[0175] Furthermore, an insulating layer 266 is provided on the insulating layer 264. The upper surface of the insulating layer 266 is preferably flat. Alternatively, it is preferable that the heights (positions in the Z direction) of the upper surfaces of the insulating layer 266 and the conductive layer 265 are the same or approximately the same. For example, the flatness of the upper surface of the insulating layer 266 can be improved by performing a chemical mechanical polishing (CMP) process or the like. Furthermore, the CMP process can make the positions of the upper surfaces of the insulating layer 266 and the conductive layer 265 the same or approximately the same. By performing the CMP process, unevenness on the sample surface is reduced, and the coverage of the insulating layer and conductive layer to be formed subsequently can be improved.

[0176] When an oxide semiconductor is used for the semiconductor layer 263, the conductive layer 255 in contact with the semiconductor layer 263 and the conductive layer 261 in contact with the semiconductor layer 263 are preferably formed using a conductive material that makes the oxide semiconductor n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Alternatively, another conductive material may be provided over the conductive material containing nitrogen.

[0177] When an oxide semiconductor is used for the semiconductor layer 263, it is preferable to use a material containing oxygen and in which hydrogen is reduced for the insulating layer 258. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide, silicon oxynitride, or the like may be used. Since hydrogen is an impurity element in an oxide semiconductor, contact between the semiconductor layer 263, which is an oxide semiconductor, and the insulating layer 258 in which hydrogen is reduced makes it difficult for the semiconductor layer 263 to become n-type. Furthermore, contact between the semiconductor layer 263, which is an oxide semiconductor, and the insulating layer 258 containing oxygen reduces oxygen vacancies in the semiconductor layer 263, thereby stabilizing the characteristics of the transistor and improving its reliability.

[0178] In addition, when an oxide semiconductor is used for the semiconductor layer 263, the insulating layer 258 preferably contains excess oxygen. In this specification, excess oxygen refers to oxygen that is released by heating. A material that releases oxygen by heating is a material that releases oxygen in an amount of 1.0×10 converted into oxygen atoms by thermal desorption spectroscopy (TDS). 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more than 3.0 x 10 20 atoms / cm 3 The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0179] When a material containing excess oxygen is used for the insulating layer 258, a material that is impermeable to oxygen may be used for the insulating layers 257 and 259. Examples of the material that is impermeable to oxygen include an oxide containing one or both of aluminum and hafnium, and a silicon nitride. By using a material that is impermeable to oxygen for the insulating layers 257 and 259, the excess oxygen contained in the insulating layer 258 is less likely to be released to the lower or upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, a structure in which an insulating layer containing silicon and oxygen (the insulating layer 258) is provided between two insulating layers containing silicon and nitrogen (the insulating layer 257 and the insulating layer 259) is preferable. Silicon nitride, silicon nitride oxide, or the like can be used as the insulating layer containing silicon and oxygen. Silicon oxide, silicon oxynitride, or the like can be used as the insulating layer containing silicon and oxygen.

[0180] When an oxide semiconductor is used for the semiconductor layer 263, by using a material containing hydrogen for the insulating layers 257 and 259, hydrogen is supplied to a region of the semiconductor layer 263 in contact with the insulating layer 257 and a region of the semiconductor layer 263 in contact with the insulating layer 259, and each region of the semiconductor layer 263 becomes n-type. Therefore, the region of the semiconductor layer 263 in contact with the conductive layer 261 and the region of the semiconductor layer 263 in contact with the insulating layer 259 function as one of a source region and a drain region. The region of the semiconductor layer 263 in contact with the conductive layer 255 and the region of the semiconductor layer 263 in contact with the insulating layer 257 function as the other of the source region and the drain region.

[0181] The conductive layer 261 functions as one of the source electrode and the drain electrode of the transistor 200C. The conductive layer 255 functions as the other of the source electrode and the drain electrode of the transistor 200C. The transistor 200C is a transistor in which the source electrode and the drain electrode are arranged in the Z direction. That is, the source and the drain of the transistor 200C are arranged at different heights. In other words, the source and the drain of the transistor 200C are arranged at different positions in the Z direction. Such a transistor is also called a "vertical channel transistor," "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

[0182] In the above configuration, in the transistor 200C, which is a VFET, the length of the side surface of the insulating layer 258 as viewed from the X direction or the Y direction is the channel length L (channel length L1) (see FIG. 25(B)). Therefore, the channel length L of the transistor 200C is determined according to the thickness t1 of the insulating layer 258.

[0183] Furthermore, the insulating layers 257 and 259 are preferably formed using a material that does not contain hydrogen or contains very little hydrogen. For example, silicon nitride or silicon nitride oxide containing very little hydrogen is preferably used. In this case, the region of the semiconductor layer 263 in contact with the insulating layer 257 and the region of the semiconductor layer 263 in contact with the insulating layer 259 are not made n-type. Therefore, the region of the semiconductor layer 263 in contact with the conductive layer 261 functions as one of the source region and the drain region. The region of the semiconductor layer 263 in contact with the conductive layer 255 functions as the other of the source region and the drain region. The region of the semiconductor layer 263 in contact with the insulating layer 258 functions as a channel formation region.

[0184] In this case, the sum of the lengths of the side surfaces of insulating layer 257, insulating layer 258, and insulating layer 259 as viewed from the X direction or Y direction is channel length L (channel length L2). Therefore, the channel length L of transistor 200C is determined according to thickness t2, which is the sum of the thicknesses of insulating layer 257, insulating layer 258, and insulating layer 259. In this way, transistor 200C has a region where the channel formation region is along the side surface of insulating layer 256.

[0185] Furthermore, since the semiconductor layer 263 is provided in the opening 262, the perimeter of the opening 262 when viewed from the Z direction is the channel width W of the transistor 200C (see FIG. 25A). The perimeter may be determined, for example, at a position halfway through the thickness t1 or halfway through the thickness t2 of the insulating layer 258. If necessary, the perimeter of any position of the opening 262 can be set to the channel width W. For example, the perimeter of the bottom of the opening 262 can be set to the channel width W, or the perimeter of the top of the opening 262 can be set to the channel width W. Although the outline (planar shape) of the opening 262 when viewed from the Z direction is shown as a circle in FIG. 25A, this is not limiting. For example, the outline of the opening 262 when viewed from the Z direction can be an ellipse, a rectangle, or the like.

[0186] In the semiconductor device of one embodiment of the present invention, the channel length L is preferably at least shorter than the channel width W. In one embodiment of the present invention, the channel length L is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W.

[0187] To improve coverage of the semiconductor layer 263, the insulating layer 264, and the conductive layer 265 formed inside the opening 262, the taper angle θ of the side surface of the opening 262, i.e., the taper angle θ of each of the side surfaces of the insulating layer 257, the insulating layer 258, and the insulating layer 259, is set to 45° or more and less than 90°, preferably 50° or more and 75° or less. The taper angles θ of the side surfaces of the insulating layer 257, the insulating layer 258, and the insulating layer 259 can be the same angle or different angles. Note that the taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle between the bottom surface and the side surface of the layer (see FIG. 25(B)).

[0188] A vertical transistor can occupy a smaller area than a transistor (also called a "horizontal transistor") in which a channel formation region, a source region, and a drain region are separately provided on the XY plane. Therefore, by using a vertical channel transistor in a semiconductor device, the area occupied by the semiconductor device can be reduced. Furthermore, by using a vertical channel transistor in a semiconductor device, high integration of the semiconductor device can be achieved.

[0189] Furthermore, in a lateral transistor, the channel length is limited by the exposure limit of photolithography. In a vertical channel transistor according to one embodiment of the present invention, the channel length can be set by the film thickness of the insulating layer 256 or 258. Therefore, the channel length of the transistor can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more). This increases the on-state current of the transistor 200C, thereby improving frequency characteristics. By using a vertical channel transistor, a semiconductor device with high operating speed can be provided.

[0190] 26(A) and 26(B), when forming the opening 262, a part of the conductive layer 255 may be removed depending on the etching conditions for the conductive layer 261 and the insulating layer 256. Also, the bottom of the opening 262 may include a curved portion.

[0191] <Transistor configuration example 4> 27A is a plan view of a transistor 200D that can be used in a semiconductor device of one embodiment of the present invention. FIG. 27B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in FIG. 27A. The transistor 200D is a variation of the transistor 200C. To avoid repetition, differences between the transistor 200D and the transistor 200C will be mainly described.

[0192] The transistor 200D includes insulating layers 258a and 258b between the insulating layers 257 and 259, and a conductive layer 267 between the insulating layers 258a and 258b. The insulating layers 258a and 258b can be formed using a material and method similar to that of the insulating layer 258. The opening 262 of the transistor 200D is provided to penetrate the conductive layer 261, the insulating layer 259, the insulating layer 258b, the conductive layer 267, the insulating layer 258a, and the insulating layer 257 in a region overlapping with part of the conductive layer 255.

[0193] Furthermore, in transistor 200D, insulating layer 268 is provided along the side surface of opening 262. Inside opening 262, insulating layer 268 has a region overlapping with a side surface of conductive layer 261, a region overlapping with a side surface of insulating layer 259, a region overlapping with a side surface of insulating layer 258b, a region overlapping with a side surface of conductive layer 267, a region overlapping with a side surface of insulating layer 258a, and a region overlapping with a side surface of insulating layer 257.

[0194] Furthermore, inside the opening 262, the semiconductor layer 263 in the transistor 200D has a region that overlaps with the side surface of the conductive layer 261 via the insulating layer 268, a region that overlaps with the side surface of the insulating layer 259 via the insulating layer 268, a region that overlaps with the side surface of the insulating layer 258b via the insulating layer 268, a region that overlaps with the side surface of the conductive layer 267 via the insulating layer 268, a region that overlaps with the side surface of the insulating layer 258a via the insulating layer 268, and a region that overlaps with the side surface of the insulating layer 257 via the insulating layer 268.

[0195] When the conductive layer 265 is used as a gate electrode, the conductive layer 267 functions as a back gate electrode. When the conductive layer 267 is used as a gate electrode, the conductive layer 265 functions as a back gate electrode. One of the insulating layer 264 and the insulating layer 268 functions as a gate insulating layer, and the other functions as a back gate insulating layer. The insulating layer 268 can be formed using a material and a method similar to those of the insulating layer 264.

[0196] <Transistor configuration example 5> 28A is a plan view of a transistor 200E that can be used in a semiconductor device according to one embodiment of the present invention. FIG. 28B is a cross-sectional view taken along the line A1-A2 indicated by the dashed-dotted line in FIG. 28A. FIG. 28C is a cross-sectional view taken along the line A3-A4 indicated by the dashed-dotted line in FIG. 28A. Note that FIG. 28B is a cross-sectional view of the transistor 200E in the channel length direction, and FIG. 28C is a cross-sectional view of the transistor 200E in the channel width direction.

[0197] 28(A) to 28(C), the transistor 200E includes a semiconductor layer 520a disposed on a substrate 201, a semiconductor layer 520b disposed on the semiconductor layer 520a, conductive layers 542a and 542b disposed apart from each other on the semiconductor layer 520b, an insulating layer 580 disposed on the conductive layers 542a and 542b and having an opening formed between the conductive layers 542a and 542b, a conductive layer 560 disposed in the opening, an insulating layer 550 disposed among the semiconductor layer 520b, the conductive layer 542a, the conductive layer 542b, and the insulating layer 580, and the conductive layer 560, and a semiconductor layer 520c disposed among the semiconductor layer 520b, the conductive layer 542a, the conductive layer 542b, the insulating layer 580, and the insulating layer 550.

[0198] 28(B) and 28(C), the upper surface of the conductive layer 560 is substantially coincident with the upper surfaces of the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580. Note that hereinafter, the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c may be collectively referred to as the semiconductor layer 520.

[0199] The conductive layer 542a functions as one of a source electrode and a drain electrode of the transistor 200E. The conductive layer 542b functions as the other of the source electrode and the drain electrode of the transistor 200E. In this specification, the conductive layer 542a and the conductive layer 542b may be collectively referred to as the conductive layer 542.

[0200] 28A to 28C, an insulating layer 554 is disposed between the insulating layer 524, the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542a, the conductive layer 542b, and the semiconductor layer 520c and the insulating layer 580. The insulating layer 554 is in contact with the side surfaces of the semiconductor layer 520c, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524.

[0201] The channel of the transistor 200E is formed in a region of the semiconductor layer 520 that overlaps with the conductive layer 560. Therefore, the channel length L of the transistor 200E can be expressed as the length of the conductive layer 560 in the X direction in the region that overlaps with the semiconductor layer 520. The channel of the transistor 200E is formed between a region that functions as a source and a region that functions as a drain of the semiconductor layer 520. Therefore, the channel length L of the transistor 200E can be expressed as the distance from the end of the conductive layer 542a to the end of the conductive layer 542b.

[0202] The channel width W of the transistor 200E can be expressed as the length of the semiconductor layer 520 in the Y direction in the region where the semiconductor layer 520 overlaps with the conductive layer 560.

[0203] Although the transistor 200E has a three-layer structure including a semiconductor layer 520a, a semiconductor layer 520b, and a semiconductor layer 520c in the channel formation region and its vicinity, the present invention is not limited to this structure. For example, a two-layer structure including the semiconductor layer 520b and the semiconductor layer 520c or a stacked structure of four or more layers may be used. Furthermore, each of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c may also have a stacked structure of two or more layers.

[0204] For example, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer 520, and the semiconductor layer 520c has a layered structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has a composition similar to that of the semiconductor layer 520b, and the second metal oxide has a composition similar to that of the semiconductor layer 520a.

[0205] Here, the conductive layer 560 functions as a gate electrode of the transistor, and the conductive layers 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductive layer 560 is formed to fill the opening of the insulating layer 580 and the region sandwiched between the conductive layers 542a and 542b. Here, the conductive layers 560, 542a, and 542b are arranged in a self-aligned manner with respect to the opening of the insulating layer 580. That is, in the transistor 200E, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductive layer 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 200E. This reduces the area occupied by the semiconductor device. Furthermore, the integration degree of the semiconductor device can be increased.

[0206] 28A to 28C, the conductive layer 560 includes a conductive layer 560a provided inside the insulating layer 550 and a conductive layer 560b provided to be embedded in the conductive layer 560a. Although the conductive layer 560 in the transistor 200E has a two-layer stacked structure, the present invention is not limited to this. For example, the conductive layer 560 may have a single-layer structure or a three- or more-layer stacked structure.

[0207] The transistor 200E has an insulating layer 202 disposed on the substrate 201, an insulating layer 514 disposed on the insulating layer 202, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 505, and an insulating layer 524 disposed on the insulating layer 522. Furthermore, a semiconductor layer 520a is disposed on the insulating layer 524.

[0208] Further, insulating layers 574 and 581 functioning as interlayer films are provided over the transistor 200E. The insulating layer 574 is provided in contact with top surfaces of the conductive layer 560, the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580.

[0209] When an oxide semiconductor is used for the semiconductor layer 520, an insulating layer having a function of suppressing diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, and the like) is preferably used for the insulating layer 522, the insulating layer 554, and the insulating layer 574. For example, an insulating layer having lower hydrogen permeability than the insulating layer 524, the insulating layer 550, and the insulating layer 580 is preferably used for the insulating layer 522, the insulating layer 554, and the insulating layer 574. For example, silicon nitride, silicon nitride oxide, or the like can be used.

[0210] Furthermore, an insulating layer having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) is preferably used for the insulating layer 522 and the insulating layer 554. For example, an insulating layer having lower oxygen permeability than the insulating layer 524, the insulating layer 550, and the insulating layer 580 is preferably used for the insulating layer 522 and the insulating layer 554. For example, silicon nitride, silicon nitride oxide, or the like can be used.

[0211] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are separated from layers above the insulating layer 574 and below the insulating layer 522 by the insulating layer 522 and the insulating layer 574. Therefore, impurities such as hydrogen and excess oxygen contained in layers above the insulating layer 574 and below the insulating layer 522 can be prevented from mixing into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0212] 28B illustrates an example in which a conductive layer 545 (conductive layer 545a and conductive layer 545b) connected to the transistor 200E and functioning as a plug is provided. Note that an example in which an insulating layer 541 (insulating layer 541a and insulating layer 541b) is provided in contact with a side surface of the conductive layer 545 functioning as a plug is illustrated. That is, the insulating layer 541 is provided in contact with inner walls of openings of the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. In addition, in FIG. 28B, a first conductive layer of the conductive layer 545 is provided in contact with a side surface of the insulating layer 541, and a second conductive layer of the conductive layer 545 is provided further inside.

[0213] Here, the height of the top surface of the conductive layer 545 can be approximately the same as the height of the top surface of the insulating layer 581. Note that although the transistor 200E has a structure in which the first conductive layer of the conductive layer 545 and the second conductive layer of the conductive layer 545 are stacked, the present invention is not limited to this. For example, the conductive layer 545 can be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0214] Furthermore, the thickness of the semiconductor layer 520b in a region that does not overlap with the conductive layer 542 may be thinner than the thickness of the region that overlaps with the conductive layer 542. This is achieved by removing part of the top surface of the semiconductor layer 520b when forming the conductive layers 542a and 542b. When a conductive film that will become the conductive layer 542 is formed on the top surface of the semiconductor layer 520b, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region of the semiconductor layer 520b that is located between the conductive layer 542a and the conductive layer 542b in a plan view, it is possible to prevent a channel from being formed in that region.

[0215] Next, the detailed structure of the transistor 200E that can be used in the semiconductor device of one embodiment of the present invention will be described.

[0216] The conductive layer 505 is arranged to have a region overlapping with the conductive layer 560 with the semiconductor layer 520 interposed therebetween. By providing the conductive layer 505 so as to be embedded in the insulating layer 516, unevenness on the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, and coverage with layers formed in later steps can be improved.

[0217] The conductive layer 505 includes a conductive layer 505a, a conductive layer 505b, and a conductive layer 505c. The conductive layer 505a is provided in contact with the bottom surface and sidewalls of an opening provided in the insulating layer 516. The conductive layer 505b is provided so as to fill a recess formed in the conductive layer 505a. The top surface of the conductive layer 505b is lower than the top surfaces of the conductive layer 505a and the insulating layer 516. The conductive layer 505c is provided in contact with the top surface of the conductive layer 505b and the side surface of the conductive layer 505a. The height of the top surface of the conductive layer 505c is equal to or approximately equal to the height of the top surface of the conductive layer 505a and the top surface of the insulating layer 516. That is, the conductive layer 505b is surrounded by the conductive layers 505a and 505c.

[0218] When an oxide semiconductor is used for the semiconductor layer 520, the conductive layers 505a and 505c are formed using a conductive material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms, or a conductive material that has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0219] By using a conductive material that can reduce hydrogen diffusion for the conductive layers 505a and 505c, impurities such as hydrogen contained in the conductive layer 505b can be prevented from diffusing into the semiconductor layer 520 through the insulating layer 524 or the like. Furthermore, by using a conductive material that can reduce oxygen diffusion for the conductive layers 505a and 505c, it is possible to prevent the conductive layer 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can reduce oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductive layer 505a can be formed as a single layer or a stack of any of the above conductive materials. For example, titanium nitride can be used for the conductive layer 505a.

[0220] The conductive layer 505b may be formed using a conductive material containing tungsten, copper, or aluminum as its main component. For example, the conductive layer 505b may be formed using tungsten. When the conductive layer 560 is used as a gate electrode, the conductive layer 505 functions as a backgate electrode.

[0221] 28C, the conductive layer 505 preferably extends to a region outside an end portion of the semiconductor layer 520 that intersects with the channel width direction. That is, the conductive layer 505 and the conductive layer 560 preferably overlap with each other with an insulating layer interposed therebetween on the outside of the side surface of the semiconductor layer 520 in the channel width direction.

[0222] With the above structure, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560 functioning as a gate electrode and the electric field of the conductive layer 505 functioning as a back gate electrode.

[0223] The conductive layer 505 can be used as wiring by extending it beyond the edge of the semiconductor layer 520. However, without being limited thereto, a conductive layer that functions as wiring can also be provided under the conductive layer 505.

[0224] The insulating layer 514 is preferably made of an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200E from the substrate side. Therefore, the insulating layer 514 is preferably made of an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms (i.e., the impurities are less likely to permeate through the insulating layer). Alternatively, the insulating layer 514 is preferably made of an insulating material that has a function of preventing the diffusion of oxygen (i.e., the oxygen is less likely to permeate through the insulating layer).

[0225] For example, aluminum oxide, silicon nitride, or the like is used for the insulating layer 514. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulating layer 514 to the transistor 200E side. Alternatively, it can prevent oxygen contained in the insulating layer 524 or the like from diffusing from the insulating layer 514 to the substrate side.

[0226] The insulating layer 516, the insulating layer 580, and the insulating layer 581, which function as interlayer films, are preferably made of an insulating material having a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, the insulating layer 516, the insulating layer 580, and the insulating layer 581 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0227] When the conductive layer 560 is used as a gate electrode, the insulating layers 522 and 524 function as gate insulating layers.

[0228] Here, the insulating layer 524 in contact with the semiconductor layer 520 preferably contains excess oxygen. For example, silicon oxide, silicon oxynitride, or the like may be used as appropriate for the insulating layer 524. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, oxygen vacancies in the semiconductor layer 520 are reduced, and the reliability of the transistor 200E is improved.

[0229] 28C, the insulating layer 524 may have a smaller thickness in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b than in other regions. The insulating layer 524 preferably has a thickness in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b that allows the oxygen to diffuse sufficiently.

[0230] As for the insulating layer 522, like the insulating layer 514, a material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200E from the substrate side is used. For example, the insulating layer 522 is made of a material that has lower hydrogen permeability than the insulating layer 524. By surrounding the insulating layer 524, the semiconductor layer 520, the insulating layer 550, and the like with the insulating layer 522, the insulating layer 554, and the insulating layer 574, impurities such as water or hydrogen can be prevented from entering the transistor 200E from the outside.

[0231] Furthermore, the insulating layer 522 is preferably made of a material that has a function of suppressing oxygen diffusion (the material is less permeable to the oxygen). For example, the insulating layer 522 is made of a material that has lower oxygen permeability than the insulating layer 524. The insulating layer 522 has a function of suppressing the diffusion of oxygen and impurities, which can reduce oxygen diffusing from the semiconductor layer 520 to the substrate. Furthermore, the conductive layer 505 can be prevented from reacting with oxygen contained in the insulating layer 524 or the semiconductor layer 520.

[0232] An insulating layer containing an oxide of one or both of aluminum and hafnium, which are insulating materials, may be used as the insulating layer 522. Examples of the insulating layer containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate). When the insulating layer 522 is formed using such a material, the insulating layer 522 functions as a layer that suppresses oxygen release from the semiconductor layer 520 and the intrusion of impurities such as hydrogen into the semiconductor layer 520 from the periphery of the transistor 200E.

[0233] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to the insulating layer 522. Alternatively, the insulating layer 522 can be subjected to nitriding treatment. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride can be stacked as the insulating layer 522. For example, the insulating layer 522 can have a three-layer structure in which silicon nitride, silicon oxide, and aluminum oxide are stacked in this order.

[0234] The insulating layer 522 can be a single layer or a multilayer of insulating layers containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinner gate insulating layers can cause problems such as leakage current. Using a high-k material for the insulating layer that functions as the gate insulating layer makes it possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0235] Note that each of the insulating layer 522 and the insulating layer 524 can have a stacked structure of two or more layers. In this case, the insulating layer 522 and the insulating layer 524 are not limited to a stacked structure made of the same material, and can have a stacked structure made of different materials.

[0236] The semiconductor layer 520 includes a semiconductor layer 520a, a semiconductor layer 520b on the semiconductor layer 520a, and a semiconductor layer 520c on the semiconductor layer 520b. By providing the semiconductor layer 520a below the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed below the semiconductor layer 520a to the semiconductor layer 520b. Furthermore, by providing the semiconductor layer 520c on the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed above the semiconductor layer 520c to the semiconductor layer 520b.

[0237] When an oxide semiconductor is used for the semiconductor layer 520, the semiconductor layer 520 preferably has a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. For example, when the semiconductor layer 520 contains at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the semiconductor layer 520a to the number of atoms of all elements constituting the semiconductor layer 520a is made higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520a to In is made higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In. Here, the semiconductor layer 520c can use the metal oxide used for the semiconductor layer 520a or the semiconductor layer 520b.

[0238] The energy of the conduction band minimum of the semiconductor layer 520a and the semiconductor layer 520c is preferably higher than the energy of the conduction band minimum of the semiconductor layer 520b. In other words, the electron affinity of the semiconductor layer 520a and the semiconductor layer 520c is preferably lower than the electron affinity of the semiconductor layer 520b. In this case, the semiconductor layer 520c may be made of a metal oxide that can be used for the semiconductor layer 520a. Specifically, the ratio of the number of atoms of the element M contained in the semiconductor layer 520c to the number of atoms of all elements constituting the semiconductor layer 520c is preferably higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520c to In is preferably higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In.

[0239] Here, the energy level of the conduction band minimum changes gradually at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c. In other words, the energy level of the conduction band minimum at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c changes continuously or can be said to be a continuous junction. To achieve this, it is preferable that the defect level density of the mixed layer formed at the interface between the semiconductor layer 520a and the semiconductor layer 520b and the interface between the semiconductor layer 520b and the semiconductor layer 520c is low.

[0240] Specifically, the semiconductor layers 520a and 520b, and the semiconductor layers 520b and 520c, can form a mixed layer with a low defect level density by having a common element other than oxygen (as a main component). For example, if the semiconductor layer 520b is an In-Ga-Zn oxide, the semiconductor layers 520a and 520c can be made of In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, or the like. The semiconductor layer 520c can also have a stacked structure. For example, a stacked structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide, or a stacked structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide, can be used. In other words, a stacked structure of In-Ga-Zn oxide and an oxide not containing In can be used as the semiconductor layer 520c.

[0241] Specifically, the semiconductor layer 520a may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of 1:1:0.5 or thereabouts. The semiconductor layer 520b may be made of a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of 3:1:2 or thereabouts, or an atomic ratio of 1:1:1 or thereabouts. The semiconductor layer 520c may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of Ga:Zn=2:1 or thereabouts, or an atomic ratio of Ga:Zn=2:5 or thereabouts. Specific examples of the semiconductor layer 520c having a stacked structure include a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or its vicinity and Ga:Zn=2:1 [atomic ratio] or its vicinity, a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or its vicinity and Ga:Zn=2:5 [atomic ratio] or its vicinity, and a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or its vicinity and gallium oxide.

[0242] In this case, the main carrier path is the semiconductor layer 520b. By configuring the semiconductor layers 520a and 520c as described above, the defect level density at the interface between the semiconductor layers 520a and 520b and at the interface between the semiconductor layers 520b and 520c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 200E to achieve high on-state current and high frequency characteristics. Note that if the semiconductor layer 520c has a stacked structure, in addition to the effect of reducing the defect level density at the interface between the semiconductor layers 520b and 520c, it is expected that the diffusion of constituent elements of the semiconductor layer 520c toward the insulating layer 550 can be suppressed. More specifically, the semiconductor layer 520c has a stacked structure, and an oxide not containing In is positioned above the stacked structure, thereby suppressing In diffusion toward the insulating layer 550. The insulating layer 550 functions as a gate insulating layer, and diffusion of In can cause poor transistor characteristics. Therefore, by forming the semiconductor layer 520c into a stacked structure, it is possible to provide a highly reliable semiconductor device.

[0243] A conductive layer 542 (a conductive layer 542a and a conductive layer 542b) functioning as a source electrode and a drain electrode is provided over the semiconductor layer 520b. When an oxide semiconductor is used for the semiconductor layer 520b, the conductive layer 542 is preferably made of a conductive material that is not easily oxidized or that maintains its conductivity even when it absorbs oxygen.

[0244] A region of the semiconductor layer 520 in contact with the conductive layer 542 functions as a source region or a drain region of the transistor 200E. Here, the region between the conductive layer 542a and the conductive layer 542b is formed to overlap with the opening of the insulating layer 580. This allows the conductive layer 560 to be disposed in a self-aligned manner between the conductive layer 542a and the conductive layer 542b.

[0245] The insulating layer 550 functions as a gate insulating layer. The insulating layer 550 is disposed in contact with the top surface of the semiconductor layer 520c. The insulating layer 550 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. For example, silicon oxide or silicon oxynitride is used as the insulating layer 550.

[0246] The insulating layer 550 is formed using an insulating material in which the concentration of impurities such as water or hydrogen is reduced, similarly to the insulating layer 524. The thickness of the insulating layer 550 is 1 nm to 20 nm.

[0247] A metal oxide is preferably provided between the insulating layer 550 and the conductive layer 560. The metal oxide suppresses oxygen diffusion from the insulating layer 550 to the conductive layer 560. This can suppress oxidation of the conductive layer 560 due to oxygen contained in the insulating layer 550.

[0248] Although the conductive layer 560 has a two-layer structure in FIGS. 28A to 28C, it can also have a single-layer structure or a stacked structure of three or more layers.

[0249] The conductive layer 560a may be formed using any of the above-mentioned conductive materials that have a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms, or may be formed using any of the above-mentioned conductive materials that have a function of suppressing diffusion of oxygen.

[0250] The conductive layer 560a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity of the conductive layer 560b due to oxidation caused by oxygen contained in the insulating layer 550. Examples of conductive materials that can suppress oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0251] The conductive layer 560b can be formed using a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layer 560 also functions as a wiring, so it is preferable to use a conductive layer with high conductivity. The conductive layer 560b can have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-mentioned conductive material.

[0252] 28(B) and 28(C), the conductive layer 560 is disposed to cover the side surface of the semiconductor layer 520 in a region of the semiconductor layer 520b that does not overlap with the conductive layer 542, in other words, in the channel formation region of the semiconductor layer 520. This makes it easier for the electric field of the conductive layer 560, which functions as the gate electrode of the transistor 200E, to act on the side surface of the semiconductor layer 520. This increases the on-state current of the transistor 200E, and improves its frequency characteristics.

[0253] Like the insulating layer 514, the insulating layer 554 is made of an insulating material that prevents impurities such as water or hydrogen from entering the transistor 200E from the insulating layer 580 side. For example, the insulating layer 554 is made of an insulating material that has lower hydrogen permeability than the insulating layer 524. Furthermore, as shown in FIGS. 28B and 28C, the insulating layer 554 is provided in contact with the side surface of the semiconductor layer 520c, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524. With this structure, hydrogen contained in the insulating layer 580 can be prevented from entering the semiconductor layer 520 from the top surfaces or side surfaces of the conductive layer 542a, the conductive layer 542b, the semiconductor layer 520a, the semiconductor layer 520b, and the insulating layer 524.

[0254] Furthermore, an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., oxygen is less likely to permeate) is used for the insulating layer 554. For example, an insulating material with lower oxygen permeability than the insulating layer 580 or the insulating layer 524 is used for the insulating layer 554.

[0255] When an oxide semiconductor is used for the semiconductor layer 520, the insulating layer 554 can be formed by a sputtering method. By forming the insulating layer 554 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 524 near a region in contact with the insulating layer 554. This allows oxygen to be supplied from this region into the semiconductor layer 520 through the insulating layer 524. The insulating layer 554 has a function of suppressing upward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 to the insulating layer 580. The insulating layer 522 has a function of suppressing downward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the semiconductor layer 520. This reduces oxygen vacancies in the semiconductor layer 520, thereby preventing the transistor from becoming normally on.

[0256] For example, an insulating layer containing an oxide of one or both of aluminum and hafnium is deposited as the insulating layer 554. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like can be used.

[0257] The insulating layer 580 is provided over the insulating layer 524, the semiconductor layer 520, and the conductive layer 542 with the insulating layer 554 interposed therebetween. For example, the insulating layer 580 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly suitable because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly suitable because they can easily form a region containing oxygen that is released by heating.

[0258] The insulating layer 574, like the insulating layer 514, is formed using an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulating layer 580 from above. The insulating layer 574 is formed using an insulating material that can be used for the insulating layer 514, the insulating layer 554, and the like, for example.

[0259] 28A to 28C show an example in which an insulating layer 581 functioning as an interlayer film is provided over the insulating layer 574. As the insulating layer 581, an insulating material in which the concentration of impurities such as water or hydrogen is reduced is used, similar to the insulating layer 524 and the like.

[0260] The conductive layers 545a and 545b are disposed in openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554. The conductive layers 545a and 545b are provided so as to sandwich the conductive layer 560 in a plan view. Note that top surfaces of the conductive layers 545a and 545b are preferably flush with the top surface of the insulating layer 581.

[0261] Note that insulating layer 541a is provided in contact with the inner walls of the openings of insulating layer 581, insulating layer 574, insulating layer 580, and insulating layer 554, and a first conductive layer of conductive layer 545a is formed in contact with the side surface of insulating layer 541a. Conductive layer 542a is located on at least a portion of the bottom of the opening, and conductive layer 545a is in contact with conductive layer 542a. Similarly, insulating layer 541b is provided in contact with the inner walls of the openings of insulating layer 581, insulating layer 574, insulating layer 580, and insulating layer 554, and a first conductive layer of conductive layer 545b is formed in contact with the side surface of insulating layer 541b. Conductive layer 542b is located on at least a portion of the bottom of the opening, and conductive layer 545b is in contact with conductive layer 542b.

[0262] The conductive layers 545a and 545b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Each of the conductive layers 545a and 545b can have a stacked structure of two or more layers.

[0263] When the conductive layer 545 has a stacked-layer structure, a conductive material that has a function of suppressing diffusion of impurities such as water or hydrogen may be used for conductive layers in contact with the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542, the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide can be used. The use of such a conductive material can suppress absorption of oxygen contained in the insulating layer 580 by the conductive layers 545a and 545b. Furthermore, impurities such as water or hydrogen from layers above the insulating layer 581 can be suppressed from entering the semiconductor layer 520 through the conductive layers 545a and 545b.

[0264] The insulating layer 541a and the insulating layer 541b may be, for example, an insulating layer that can be used for the insulating layer 554. The insulating layer 541a and the insulating layer 541b are provided in contact with the insulating layer 554, and therefore impurities such as water or hydrogen from the insulating layer 580 or the like can be prevented from entering the semiconductor layer 520 through the conductive layers 545a and 545b. Furthermore, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b.

[0265] <Transistor configuration example 6> FIG. 29 shows a modification of transistor 200E shown in FIG. 28. FIG. 29(A) is a plan view of transistor 200F, which is a modification of transistor 200E. FIG. 29(B) is a cross-sectional view taken along line A1-A2 indicated by the dashed-dotted line in FIG. 29(A). FIG. 29(C) is a cross-sectional view taken along line A3-A4 indicated by the dashed-dotted line in FIG. 29(A). Because transistor 200F is a modification of transistor 200E, differences between transistor 200F and transistor 200E will be mainly described.

[0266] The transistor 200F has a configuration in which the semiconductor layer 520c and the conductive layer 505c are removed from the configuration of the transistor 200E. Reducing the number of transistor components reduces production costs. Furthermore, reducing the number of transistor components shortens the manufacturing process, improving manufacturing yield.

[0267] Furthermore, the transistor 200F has a region where the insulating layer 554 and the insulating layer 522 are in contact with each other outside the semiconductor layer 520, and has a structure in which the side surface of the insulating layer 524 is covered with the insulating layer 554. When an oxide semiconductor is used for the semiconductor layer 520, covering the side surface of the insulating layer 524 with the insulating layer 554 not only prevents oxygen from diffusing to the outside through the insulating layer 524 but also prevents excessive oxygen from being supplied to the semiconductor layer 520 from the insulating layer 524 side.

[0268] Note that an insulating layer is preferably provided between the insulating layer 580, the insulating layer 554, the conductive layer 542, and the semiconductor layer 520b and the insulating layer 550. Aluminum oxide, hafnium oxide, or the like is preferably used for the insulating layer. By providing the insulating layer, it is possible to suppress desorption of oxygen from the semiconductor layer 520 to the insulating layer 550, excessive supply of oxygen from the insulating layer 550 to the semiconductor layer 520, oxidation of the conductive layer 542, and the like.

[0269] <Transistor configuration example 7> FIG. 30 shows a modification of transistor 200F shown in FIG. 29. FIG. 30(A) is a plan view of transistor 200G, which is a modification of transistor 200F. FIG. 30(B) is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in FIG. 30(A). FIG. 30(C) is a cross-sectional view taken along the line A3-A4 indicated by the dashed dotted line in FIG. 30(A). Because transistor 200G is a modification of transistor 200F, differences between transistor 200G and transistor 200F will be mainly described.

[0270] The transistor 200G differs from the transistor 200F in that the conductive layer 542 has a stacked structure of two conductive layers. In Figure 30B, the conductive layer 542a is shown as a conductive layer 542a1 and a conductive layer 542a2, and the conductive layer 542b is shown as a conductive layer 542b1 and a conductive layer 542b2. More specifically, the conductive layer 542a1 is provided on part of the semiconductor layer 520, and the conductive layer 542a2 is provided on the conductive layer 542a1. Furthermore, the conductive layer 542b1 is provided on another part of the semiconductor layer 520, and the conductive layer 542b2 is provided on the conductive layer 542b1.

[0271] 30B, the end of the conductive layer 542a1 has a region that extends beyond the end of the conductive layer 542a2 and overlaps with the conductive layer 560 with the insulating layer 550 interposed therebetween. The end of the conductive layer 542b1 has a region that extends beyond the end of the conductive layer 542b2 and overlaps with the conductive layer 560 with the insulating layer 550 interposed therebetween.

[0272] Such a structure allows the distance between the source and drain to be shorter, thereby shortening the channel length L accordingly. The channel length L of the transistor 200G is determined by the distance from the end of the conductive layer 542a1 to the end of the conductive layer 542b1 (see FIG. 30B). By shortening the channel length L, the on-state current of the transistor 200G increases, and the operating speed of the transistor 200G can be increased. Therefore, the operating speed of a semiconductor device including the transistor 200G can be increased.

[0273] <Transistor configuration example 8> FIG. 31A is a plan view of a transistor 200H that can be used in a semiconductor device according to one embodiment of the present invention. FIG. 31B is a schematic perspective view of the transistor 200H. FIGS. 31C to 31E are cross-sectional views of the transistor 200H. FIG. 31C is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 31A and is also a cross-sectional view of the transistor 200H in the channel width direction (Y direction). FIG. 31D is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 31A and is also a cross-sectional view of the transistor 200H in the channel width direction. FIG. 31E is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 31A and is also a cross-sectional view of the transistor 200H in the channel length direction (X direction). Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that some components are omitted from the plan view of FIG. 31(A) and the perspective schematic view of FIG. 31(B). FIG. 32(A) shows an enlarged view of the vicinity of the conductive layer 260 in FIG. 31(E). FIG. 32(B) shows an enlarged view of the vicinity of the semiconductor layer 230 in FIG. 31(C).

[0274] The transistor 200H according to this embodiment includes an insulating layer 295 on a substrate (not shown), an insulating layer 296 on the insulating layer 295, an insulating layer 291 on the insulating layer 296, an insulating layer 292 on the insulating layer 291, a semiconductor layer 230 on the insulating layer 292, conductive layers 242a and 242b on the semiconductor layer 230 and the insulating layer 292, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 (conductive layer 260a and conductive layer 260b) on the insulating layer 250. Note that in this specification, the conductive layer 242a and the conductive layer 242b may be collectively referred to as the conductive layer 242.

[0275] An insulating layer 235 is provided on the conductive layer 242, and an insulating layer 280 is provided on the insulating layer 235. The insulating layer 250 and the conductive layer 260 are provided inside a first opening that penetrates the insulating layer 280 and the insulating layer 235 and reaches the semiconductor layer 230. In a plan view, the first opening has a region that overlaps with the semiconductor layer 230 and a region that extends along the Y direction beyond the edge of the semiconductor layer 230. Therefore, in a plan view, the insulating layer 250 and the conductive layer 260 provided inside the first opening also have a region that overlaps with the semiconductor layer 230 and a region that extends along the Y direction beyond the edge of the semiconductor layer 230. The conductive layer 260 also functions as wiring. The insulating layer 250 has a region that contacts the semiconductor layer 230 within the first opening. In addition, an insulating layer 297 is provided on the insulating layer 280 and the conductive layer 260. In addition, an insulating layer 298 is provided on the insulating layer 297.

[0276] Furthermore, insulating layer 241a is provided in contact with the inner wall of the second opening that penetrates insulating layer 298, insulating layer 297, insulating layer 280, and insulating layer 235 to reach conductive layer 242a, and conductive layer 245a is provided in contact with insulating layer 241a. Conductive layer 245a has a region that contacts conductive layer 242a at the bottom of the first opening.

[0277] Furthermore, insulating layer 241b is provided in contact with the inner wall of a third opening that penetrates insulating layer 298, insulating layer 297, insulating layer 280, and insulating layer 235 to reach conductive layer 242b, and conductive layer 245b is provided in contact with insulating layer 241b. Conductive layer 245b has a region that contacts conductive layer 242b at the bottom of the second opening.

[0278] In this specification, the conductive layer 245a and the conductive layer 245b may be collectively referred to as the conductive layer 245. Furthermore, the insulating layer 241a and the insulating layer 241b may be collectively referred to as the insulating layer 241.

[0279] The semiconductor layer 230 includes a channel formation region of the transistor 200H. The conductive layer 260 has a region that functions as a gate electrode of the transistor 200H. The insulating layer 250 has a region that functions as a gate insulating layer of the transistor 200H. In the transistor 200H, a region of the semiconductor layer 230 that overlaps with the conductive layer 260 functions as a channel formation region. A region of the conductive layer 260 that overlaps with the semiconductor layer 230 functions as a gate electrode. A region of the insulating layer 250 where the insulating layer 250 and the semiconductor layer 230 overlap and where the insulating layer 250 and the conductive layer 260 overlap functions as a gate insulating layer.

[0280] The conductive layer 242a has a region functioning as one of the source electrode and the drain electrode of the transistor 200H. The conductive layer 245a functions as a plug connected to the conductive layer 242a. The conductive layer 242b has a region functioning as the other of the source electrode and the drain electrode of the transistor 200H. The conductive layer 245b functions as a plug connected to the conductive layer 242b.

[0281] The semiconductor layer 230 is formed on the insulating layer 292. As shown in FIG. 32(B), the semiconductor layer 230 has a shape with a high aspect ratio in a cross-sectional view in the channel width direction. For this reason, the semiconductor layer 230 can also be said to have a fin-like shape. A transistor whose semiconductor layer is fin-shaped is also called a "fin transistor," "fin type transistor," or "fin transistor."

[0282] Specifically, a fin transistor is a transistor in which, in a cross-sectional view in the channel width direction (Y direction), the channel formation region of the semiconductor layer has two regions (two surfaces) extending in the Z direction, and has a shape in which a length H (described later) is greater than a length Lx (described later). In a cross-sectional view in the channel width direction, a shape in which the length H is greater than the length Lx is preferable because it allows the channel width per unit area to be increased.

[0283] In this specification, the maximum length of the semiconductor layer 230 in the channel formation region in the Y direction is defined as length Lx, and the maximum length of the semiconductor layer 230 in the channel formation region in the direction perpendicular to the surface on which it is to be formed (e.g., the upper surface of the insulating layer 292) is defined as length H.

[0284] The length Lx can also be considered to be the maximum width of the semiconductor layer 230 in the channel formation region. Therefore, "length Lx" can be read as "width Lx." The length H can also be considered to be the maximum height of the semiconductor layer 230 in the channel formation region. Therefore, "length H" can be read as "height H."

[0285] The ratio of the length H to the length Lx is referred to as the aspect ratio of the semiconductor layer 230. The aspect ratio of the semiconductor layer 230 is preferably as large as possible without causing the semiconductor layer 230 to collapse during the fabrication process of the transistor 200H. The aspect ratio of the semiconductor layer 230 is preferably greater than 1 and less than 400, more preferably greater than 2 and less than 100, more preferably greater than 5 and less than 40, and even more preferably greater than 10 and less than 20. That is, in the channel formation region of the semiconductor layer 230, the height H of the semiconductor layer 230 is preferably at least longer than the length Lx of the semiconductor layer 230. The height H of the semiconductor layer 230 is preferably greater than 1 and less than 400 times the length Lx of the semiconductor layer 230, more preferably greater than 2 and less than 100 times, more preferably greater than 5 and less than 40 times, and even more preferably greater than 10 and less than 20 times. Alternatively, for example, the height H may be greater than 2 and less than 10 times the length Lx. For example, the length Lx is preferably 5 nm or more and 100 nm or less, more preferably 5 nm or more and 50 nm or less, and even more preferably 10 nm or more and 30 nm or less. Also, for example, the height H is preferably 50 nm or more and 2000 nm or less, and more preferably 100 nm or more and 1000 nm or less. Also, for example, the height H can be 50 nm or more and 100 nm or less.

[0286] 32(B), in a cross-sectional view in the channel width direction, the angle θ formed between the formation surface of the semiconductor layer 230 on the insulating layer 292 and the side surface of the semiconductor layer 230 is preferably perpendicular or approximately perpendicular. For example, the angle θ is preferably 80° or more and 100° or less, and more preferably 85° or more and 95° or less.

[0287] An insulating layer 250, a conductive layer 260, and a conductive layer 242 are provided to cover the semiconductor layer 230 having such an aspect ratio. In the transistor 200H, as shown in FIG. 32(B), a portion of the insulating layer 250 and a portion of the conductive layer 260 are provided so as to sandwich the semiconductor layer 230 in two. As a result, in a cross-sectional view in the channel width direction, the semiconductor layer 230 and the conductive layer 260 are provided facing each other with the insulating layer 250 sandwiched between the upper portion, the A1-side side surface, and the A2-side side surface of the semiconductor layer 230. In other words, the upper portion, the A1-side side surface, and the A2-side side surface of the semiconductor layer 230 each function as a channel formation region. Therefore, compared to when the semiconductor layer 230 is formed in a planar shape, the channel width of the transistor 200H is larger by the amount of the A1-side side surface and the A2-side side surface of the semiconductor layer 230.

[0288] By increasing the channel width as described above, the on-state current, transconductance, frequency characteristics, and the like of the transistor 200H can be improved. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, in the above structure, by providing the semiconductor layer 230, the channel width can be increased without increasing the area occupied by the transistor 200H. This allows for miniaturization or high integration of the semiconductor device.

[0289] Furthermore, as shown in FIG. 32(B) and other figures, it is preferable that the upper portion of the semiconductor layer 230 has a curved shape. Such a curved shape can prevent defects such as voids from being formed in the insulating layer 250 and the conductive layer 242 near the upper portion of the semiconductor layer 230. Note that in FIG. 32(B) and other figures, a symmetrical structure is shown in which curved shapes are provided on both the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the semiconductor layer 230, but the present invention is not limited to this. For example, an asymmetrical structure may also be used in which a curved shape is provided on either the A1 side (A3 side) or the A2 side (A4 side) of the upper portion of the semiconductor layer 230.

[0290] When an oxide semiconductor is used for the semiconductor layer 230, a structure including the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c disclosed in Embodiment 3 can be applied, as shown in FIGS.

[0291] 32A and 32B, when an oxide semiconductor is used for the semiconductor layer 230, the insulating layer 250 preferably has a stacked structure of an insulating layer 250a in contact with the semiconductor layer 230, an insulating layer 250b on the insulating layer 250a, an insulating layer 250c on the insulating layer 250b, and an insulating layer 250d on the insulating layer 250c. In this case, the insulating layer 250a and the insulating layer 250c preferably have a function of capturing hydrogen or fixing hydrogen.

[0292] Examples of insulating layers capable of capturing or fixing hydrogen include metal oxides having an amorphous structure. For the insulating layer 250a and the insulating layer 250c, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure have a high ability to capture or fix hydrogen.

[0293] Furthermore, it is preferable to use a high-dielectric-constant (high-k) material for the insulating layer 250a and the insulating layer 250c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material for the insulating layer 250a and the insulating layer 250c, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. It is also possible to reduce the equivalent oxide thickness (EOT) of the insulating layer that functions as the gate insulating layer.

[0294] For the insulating layer 250a and the insulating layer 250c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0295] In this embodiment, aluminum oxide is used as the insulating layer 250a. The aluminum oxide preferably has an amorphous structure. By providing the insulating layer 250a in contact with the semiconductor layer 230, hydrogen contained in the semiconductor layer 230 and the like can be more effectively captured and fixed to the insulating layer 250a.

[0296] In this embodiment, hafnium oxide is used as the insulating layer 250c. Here, by providing the insulating layer 250c between the insulating layer 250b and the insulating layer 250d, hydrogen contained in the insulating layer 250b and the like can be more effectively captured and fixed.

[0297] Next, the insulating layer 250b is preferably an insulating layer that is stable to heat, such as silicon oxide or silicon oxynitride, etc. The silicon oxide film used as the insulating layer 250b is preferably formed using the PEALD method.

[0298] In order to suppress oxidation of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260, it is preferable to provide a barrier insulating layer against oxygen near each of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260. In the semiconductor device described in this embodiment, the insulating layer is, for example, the insulating layer 250a, the insulating layer 250d, the insulating layer 250c, and the insulating layer 235.

[0299] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. In this specification and the like, having barrier properties means having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulating layer having barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulating layer. Furthermore, for example, an insulating layer having barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulating layer.

[0300] Examples of the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulating layer 250a, the insulating layer 250c, the insulating layer 250d, and the insulating layer 235 each preferably have a single-layer structure or a multilayer structure of the oxygen barrier insulating layer.

[0301] The insulating layer 250a preferably has a barrier property against oxygen. The insulating layer 250a is preferably at least less permeable to oxygen than the insulating layer 280. The insulating layer 250a has regions in contact with the side surfaces of the conductive layer 242a and the conductive layer 242b. The insulating layer 250a has a barrier property against oxygen, which can prevent the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and forming an oxide film on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200H.

[0302] The insulating layer 250a is provided in contact with the upper surface and side surfaces of the semiconductor layer 230 and the upper surface of the insulating layer 292. The insulating layer 250a has a barrier property against oxygen, which can prevent oxygen from being released from the channel formation region of the semiconductor layer 230 when heat treatment or the like is performed. Therefore, oxygen vacancies can be reduced in the semiconductor layer 230.

[0303] Furthermore, providing the insulating layer 250a prevents an excessive amount of oxygen from being supplied from the insulating layer 280 to the semiconductor layer 230, and allows an appropriate amount of oxygen to be supplied to the semiconductor layer 230. This prevents the source and drain regions from being excessively oxidized, thereby preventing a decrease in the on-state current or field-effect mobility of the transistor 200H.

[0304] Oxides containing one or both of aluminum and hafnium have barrier properties against oxygen and are therefore suitable for the insulating layer 250a.

[0305] The insulating layer 250d also preferably has a barrier property against oxygen. The insulating layer 250d is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260 and between the insulating layer 280 and the conductive layer 260. This structure can prevent oxygen contained in the channel formation region of the semiconductor layer 230 from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. Furthermore, it can prevent oxygen contained in the semiconductor layer 230 and oxygen contained in the insulating layer 280 from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250d is preferably at least less permeable to oxygen than the insulating layer 280. For example, a silicon nitride film is preferably used as the insulating layer 250d. In this case, the insulating layer 250d is an insulating layer containing at least nitrogen and silicon.

[0306] Furthermore, the insulating layer 250d preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230.

[0307] The insulating layer 235 also preferably has a barrier property against oxygen. The insulating layer 235 is provided between the insulating layer 280 and the conductive layer 242a and between the insulating layer 280 and the conductive layer 242b. The insulating layer 235 is provided in contact with the side surface of the conductive layer 242, the side surface of the semiconductor layer 230, and the top surface of the insulating layer 292. This structure can prevent oxygen contained in the insulating layer 280 from diffusing into the conductive layer 242. Therefore, it is possible to prevent the conductive layer 242 from being oxidized by the oxygen contained in the insulating layer 280 and its resistivity from increasing. The insulating layer 235 is preferably at least less permeable to oxygen than the insulating layer 280. For example, silicon nitride is preferably used as the insulating layer 235. In this case, the insulating layer 235 is an insulating layer containing at least nitrogen and silicon.

[0308] To suppress a decrease in the hydrogen concentrations in the source and drain regions in the semiconductor layer 230, it is preferable to provide a barrier insulating layer against hydrogen near each of the source and drain regions. In the semiconductor device described in this embodiment, the barrier insulating layer against hydrogen is, for example, the insulating layer 235.

[0309] Examples of the barrier insulating layer against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulating layer 235 preferably has a single-layer structure or a multilayer structure of the above-mentioned barrier insulating layers against hydrogen.

[0310] By providing the insulating layer 235 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentration in the source and drain regions, thereby making the source and drain regions n-type.

[0311] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, with the above structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200H can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0312] The insulating layers 250a to 250d function as part of a gate insulating layer. The insulating layers 250a to 250d, together with the conductive layer 260, are provided in an opening formed in the insulating layer 280. To miniaturize the transistor 200H, it is preferable that the insulating layers 250a to 250d each have a thin thickness. The insulating layers 250a to 250d each have a thickness of preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulating layers 250a to 250d may have a region with the above thickness at least in part.

[0313] The thickness of the silicon oxide film used as the insulating layer 250 is preferably 0.7 nm or more and 3 nm or less.

[0314] In order to thin the film thicknesses of the insulating layers 250a to 250d as described above, it is preferable to form the insulating layers 250a to 250d by using the ALD method. Furthermore, it is preferable to form the insulating layers 250a to 250d by using the ALD method in order to provide the insulating layers 250a to 250d in openings in the insulating layer 280, etc. By forming the insulating layers 250 by using the ALD method, it is possible to form the insulating layer 250 with good coverage on the side surfaces of the first openings formed in the insulating layer 280, the side edges of the conductive layers 242a and 242b, and the like.

[0315] Although the insulating layer 250 has been described above as having a four-layer structure of insulating layers 250a to 250d, the present invention is not limited to this. The insulating layer 250 can also have a structure including at least one of the insulating layers 250a to 250d. By forming the insulating layer 250 using one, two, or three of the insulating layers 250a to 250d, the manufacturing process of the transistor 200H can be simplified and the productivity of a semiconductor device including the transistor 200H can be improved.

[0316] As shown in FIG. 31(A), the shape of the semiconductor layer 230 in a plan view is preferably a circumferential shape (which can also be referred to as a frame shape, an annular shape, a doughnut shape, or a closed curve shape) with both ends coinciding. That is, it is preferable that the semiconductor layer 230 has a structure including a plurality of portions extending in the channel width direction (A1-A2 direction) and a plurality of portions extending in the channel length direction (A5-A6 direction). This can prevent the semiconductor layer 230 from collapsing during the transistor fabrication process when the aspect ratio of the semiconductor layer 230 is increased. Note that the semiconductor layer 230 shown in FIG. 31(A) can also be said to have a shape with an opening in the center. In FIG. 31(A), the shape of the semiconductor layer 230 in a plan view is line-symmetrical about the A1-A2 axis, but the present invention is not limited to this. For example, the shape of the semiconductor layer 230 in a plan view may be asymmetrical.

[0317] The structure shown in Fig. 31(A) is a structure in which two circumferential semiconductor layers 230 are formed in the Y direction. As shown in Fig. 31(A), the semiconductor layer 230 preferably overlaps with the conductive layer 260 at two or more locations in a plan view. Therefore, the conductive layer 260 preferably has two or more regions that overlap with the semiconductor layer 230. In other words, it is preferable that the semiconductor layer 230 and the conductive layer 260 have two or more regions where they overlap with each other.

[0318] With this structure, as shown in FIG. 31B, a plurality of fin-shaped semiconductor layers 230 are formed in a cross section in the channel width direction. Each of the plurality of fin-shaped semiconductor layers 230 includes a channel formation region. That is, the transistor 200H functions as a multi-channel transistor. Therefore, the channel width of the transistor 200H can be further increased, thereby increasing the on-state current. Therefore, the operating speed of a semiconductor device including the transistor 200H can be increased.

[0319] Although the above description has been given of a configuration in which two circumferential semiconductor layers 230 are provided, the present invention is not limited to this. For example, a configuration in which one or three or more circumferential semiconductor layers 230 are provided is possible. Furthermore, it is possible to combine circumferential semiconductor layers 230 to form a semiconductor layer 230 having a shape with a plurality of openings. Furthermore, it is possible to use a semiconductor layer 230 in a lattice shape in plan view.

[0320] <Transistor configuration example 9> Next, a transistor 200I, which is a variation of the transistor 200H, will be described. FIG. 33A is a plan view of the transistor 200I that can be used in a semiconductor device according to one embodiment of the present invention. FIG. 33B is a schematic perspective view of the transistor 200I. FIGS. 33C to 33E are cross-sectional views of the transistor 200I. FIG. 33C is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 33A and is also a cross-sectional view of the transistor 200I in the channel width direction (Y direction). FIG. 33D is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 33A and is also a cross-sectional view of the transistor 200I in the channel width direction. FIG. 33E is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 33A and is also a cross-sectional view of the transistor 200I in the channel length direction (X direction). Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the plan view of Figure 33(A) and the perspective schematic view of (B), some components are omitted. Also, Figure 34 shows an enlarged view of the semiconductor layer 230 of Figure 33(C).

[0321] As shown in FIGS. 33(B) to 33(E), an insulating layer 294 can be provided under the semiconductor layer 230. The planar shape of the insulating layer 294 (the shape when viewed from the Z direction) is the same as that of the semiconductor layer 230. Therefore, in a planar view, the insulating layer 294 overlaps with the semiconductor layer 230. The lower surface of the insulating layer 294 contacts the insulating layer 292, the side surfaces of the insulating layer 294 contact the insulating layer 250 and the conductive layer 242a, and the upper surface of the insulating layer 294 contacts the lower surface of the semiconductor layer 230. The insulating layer 294 may be made of an insulating material that can be used for the insulating layer 250b. For example, silicon oxide can be used for the insulating layer 294.

[0322] Note that Figures 33(A) to 33(E) correspond to Figures 31(A) to 31(E). Also, Figure 34 corresponds to Figure 32(B). Therefore, matters not explained below regarding the configurations of Figures 33(A) to 33(E) and 34 can be understood by referring to the explanations of Figures 31(A) to 31(E) and 32(B) above.

[0323] 34, it is preferable that the thickness t2 of the insulating layer 250 at the bottom of the first opening is thinner than the thickness t1 (the length of the insulating layer 294 in the direction perpendicular to the surface on which it is formed) of the insulating layer 294. With this configuration, the lower surface of the conductive layer 260 (conductive layer 260a) located in the first opening can be positioned lower than the lower surface of the semiconductor layer 230 by the difference (t1-t2) between the thickness t1 and the thickness t2.

[0324] By positioning the lower surface of the conductive layer 260 below the lower surface of the semiconductor layer 230, a sufficient gate electric field can be applied from the upper end to the lower end of the semiconductor layer 230. In other words, within an opening in the insulating layer 280 or the like, the entire semiconductor layer 230 is electrically surrounded by the electric field of the conductive layer 260, allowing it to function as a channel formation region. This configuration prevents the lower end of the semiconductor layer 230 from functioning as a parasitic channel, thereby reducing leakage current between the source electrode and the drain electrode. Furthermore, it is possible to suppress poor characteristics, such as normally-on of the transistor, that are caused by the parasitic channel. In other words, it is possible to improve the electrical characteristics of the transistor 200I.

[0325] Furthermore, as described above, the channel width can be increased by making the semiconductor layer 230 function as a channel formation region from the top to the bottom, thereby improving the on-state current, transconductance, frequency characteristics, and the like of the transistor 200I.

[0326] In this specification and the like, a transistor structure in which the electric field of the gate electrode electrically surrounds the channel formation region as described above is referred to as a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is arranged so as to surround at least two sides of the channel (specifically, two, three, or four sides, etc.). By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to provide a transistor in which the short channel effect is less likely to occur.

[0327] Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be considered to be substantially equivalent to a GAA (gate all around) structure or an LGAA (lateral gate all around) structure. By forming the transistor 200I in the S-channel, GAA, or LGAA structure, the channel formation region formed at or near the interface between the semiconductor layer 230 and the insulating layer 250, which functions as a gate insulating layer, can be the entire bulk of the semiconductor layer 230. This increases the current density flowing through the transistor, which is expected to improve the on-state current or field-effect mobility of the transistor. In one embodiment of the present invention, the semiconductor layer 230 has a CAAC structure and a fin-like structure. This structure allows the current path flowing through the source and drain of the transistor to be parallel to the ab-plane of the crystal axis. In other words, an oxide semiconductor having a CAAC structure and a fin-like structure has a conduction path equivalent to that of a two-dimensional semiconductor material. Furthermore, by using such an oxide semiconductor, a device with two-dimensional conduction can be fabricated.

[0328] <Transistor configuration example 10> 35(A) to 35(E) show a transistor 200J, which is a variation of the transistor 200H. The transistor 200J differs from the transistor 200H in that a conductive layer 205 is provided below an insulating layer 291. Note that FIGS. 35(A) to 35(E) correspond to FIGS. 31(A) to 31(E). Matters not described below regarding the configurations shown in FIGS. 35(A) to 35(E) can be understood with reference to the description of FIGS. 31(A) to 31(E) above.

[0329] The conductive layer 205 has a region overlapping with the channel formation region of the semiconductor layer 230. Thus, the conductive layer 205 has a region that functions as a gate electrode, similar to the conductive layer 260. The conductive layer 260 may be referred to as a first gate electrode (upper gate electrode) of the transistor 200J, and the conductive layer 205 may be referred to as a second gate electrode (lower gate electrode) of the transistor 200J. When the conductive layer 260 is referred to as a gate electrode of the transistor 200J, the conductive layer 205 may be referred to as a backgate electrode of the transistor 200J.

[0330] When the conductive layer 205 is provided under the insulating layer 291 like the transistor 200J, each of the insulating layer 292 and the insulating layer 291 has a region that functions as a gate insulating layer, similar to the insulating layer 250. Specifically, the region of each of the insulating layer 292 and the insulating layer 291 that overlaps with the conductive layer 205 functions as a gate insulating layer. The insulating layer 250 may be referred to as a first gate insulating layer (upper gate insulating layer), and the insulating layer 292 and the insulating layer 291 may be referred to as a second gate insulating layer (lower gate insulating layer).

[0331] In the transistor 200J, the conductive layer 205 is disposed so as to overlap with the semiconductor layer 230 and the conductive layer 260. In FIGS. 35(C) and 35(E), the conductive layer 205 is provided inside a fourth opening that penetrates the insulating layer 296 and reaches the insulating layer 295. In addition, the fourth opening has, in a plan view, a region that overlaps with the semiconductor layer 230 and a region that extends in the Y direction beyond the end of the semiconductor layer 230. Therefore, in a plan view, the conductive layer 205 provided inside the fourth opening also has a region that overlaps with the semiconductor layer 230 and a region that extends in the Y direction beyond the end of the semiconductor layer 230. The conductive layer 205 also functions as wiring.

[0332] As shown in Figures 35(C) and 35(E), the conductive layer 205 preferably includes conductive layer 205a and conductive layer 205b. The conductive layer 205a is provided in contact with the bottom and sidewall of the fourth opening. The conductive layer 205b is provided so as to fill a recess in the conductive layer 205a formed along the bottom and sidewall of the fourth opening. Here, it is preferable that the top surface of the conductive layer 205 coincides or substantially coincides with the top surface of the insulating layer 296. In other words, when viewed from the Y direction, it is preferable that the shortest distance from the top surface of the substrate (not shown) to the top surface of the insulating layer 296 coincides or substantially coincides with the shortest distance from the top surface of the substrate to the top surface of the conductive layer 205.

[0333] Here, the conductive layer 205a preferably includes a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it preferably includes a conductive material that has a function of suppressing the diffusion of oxygen.

[0334] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 205a, impurities such as hydrogen contained in the conductive layer 205b can be prevented from diffusing into the semiconductor layer 230 via the insulating layer 296 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductive layer 205a, it is possible to prevent the conductive layer 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 205a preferably contains titanium nitride.

[0335] The conductive layer 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0336] As described above, the conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200J can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200J and reduce its off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential of the conductive layer 260 is 0 V compared to not applying a negative potential to the conductive layer 205.

[0337] The electrical resistivity of the conductive layer 205 is designed in consideration of the potential applied to the conductive layer 205, and the film thickness of the conductive layer 205 is set to match the electrical resistivity. The film thickness of the insulating layer 296 is approximately the same as that of the conductive layer 205. Here, it is preferable to make the film thicknesses of the conductive layer 205 and the insulating layer 296 thin within the range permitted by the design of the conductive layer 205. By making the film thickness of the insulating layer 296 thin, the absolute amount of impurities such as hydrogen contained in the insulating layer 296 can be reduced, and therefore, the diffusion of the impurities into the semiconductor layer 230 can be suppressed.

[0338] Although the above describes a stacked structure of the conductive layer 205a and the conductive layer 205b, the present invention is not limited to this. The conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductive layer 205 has a three-layer stacked structure, the stacked structure of the conductive layer 205a and the conductive layer 205b may further include a conductive layer made of the same material as the conductive layer 205a on the conductive layer 205b. In this case, the conductive layer 205b may be formed so that the top surface of the conductive layer 205b is lower than the top of the conductive layer 205a, and the recess formed by the conductive layer 205a and the conductive layer 205b is filled.

[0339] In addition to the materials disclosed in this embodiment, the materials for conductive layers shown in other embodiments can be used as materials for conductive layers 205, 242, 245, and 260. In addition to the materials disclosed in this embodiment, the materials for insulating layers shown in other embodiments can be used as materials for insulating layers 295, 296, 291, 292, 241, 250, 235, 280, 297, and 298.

[0340] The transistor 200J described in this embodiment can be used as a transistor included in the semiconductor device 10. The transistor 200J can have a large on-state current without increasing the occupation area.

[0341] <Transistor constituent materials> Next, constituent materials that can be used for the transistor 200 (transistor 200A, transistor 200B, transistor 200C, transistor 200D, transistor 200E, transistor 200F, transistor 200G, transistor 200H, transistor 200I, and transistor 200J) will be described.

[0342] [substrate] When a transistor is provided on a substrate, the material used for the substrate is not particularly limited. The material used for the substrate is determined depending on the purpose, taking into consideration the presence or absence of light transparency and heat resistance sufficient to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used as the substrate. Examples of insulating substrates that can be used include glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (such as yttria-stabilized zirconia substrates). Furthermore, semiconductor substrates, flexible substrates, resin substrates, and the like can also be used as the substrate.

[0343] Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having an insulator region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Furthermore, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0344] Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Also, there are substrates having metal nitrides, substrates having metal oxides, etc. Furthermore, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulator substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate.

[0345] Examples of materials that can be used for flexible substrates or resin substrates include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofiber.

[0346] By using the above materials for the substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is resistant to impact can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is less likely to break can be provided. Furthermore, it is also possible to use a substrate on which elements are provided. Elements that can be provided on the substrate include capacitance elements, resistance elements, switching elements, light-emitting elements, memory elements, and the like.

[0347] [Insulating layer] An inorganic insulating film is used for each of the insulating layers (insulating layer 202, insulating layer 204, insulating layer 206, insulating layer 209, insulating layer 295, insulating layer 296, insulating layer 291, insulating layer 292, insulating layer 294, insulating layer 241, insulating layer 257, insulating layer 250, insulating layer 258, insulating layer 258a, insulating layer 258b, insulating layer 259, insulating layer 264, insulating layer 266, insulating layer 268, insulating layer 516, insulating layer 235, insulating layer 280, insulating layer 297, insulating layer 298, insulating layer 522, insulating layer 524, insulating layer 541, insulating layer 554, insulating layer 580, insulating layer 574, insulating layer 581, etc.). Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminate films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of nitride oxide insulating films include silicon nitride oxide films and aluminum nitride oxide films. Furthermore, organic insulating films can also be used for insulating layers included in semiconductor devices.

[0348] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0349] For example, as transistors become more miniaturized and highly integrated, thinner gate insulating layers can cause problems such as leakage current. Using high-k materials for insulating layers that function as gate insulating layers, such as insulating layer 204 and insulating layer 264, enables lower voltage operation of the transistor while maintaining the physical film thickness. It also enables thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for insulating layers that function as interlayer films can reduce the parasitic capacitance that occurs between wiring. Therefore, it is important to select materials according to the function of the insulating layer. Materials with a low dielectric constant also have high dielectric strength.

[0350] Examples of high-k materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0351] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other examples of inorganic insulating materials with a low relative dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0352] [Conductive layer] For the conductive layers (conductive layer 205, conductive layer 208, conductive layer 219, conductive layer 242, conductive layer 245, conductive layer 255, conductive layer 260, conductive layer 267, conductive layer 261, conductive layer 265, conductive layer 505, conductive layer 545, conductive layer 560, etc.) used in the transistor 200, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. As the alloy containing any of the above metal elements, nitrides of the alloys or oxides of the alloys can be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Also, it is possible to use semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0353] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, silicon-doped indium tin oxide (also referred to as ITSO), indium zinc oxide (also referred to as IZO®), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive layer formed using a conductive material containing oxygen may be referred to as an oxide conductive layer.

[0354] Conductive materials containing tungsten, copper or aluminum as a main component are preferred because they have high conductivity.

[0355] It is also possible to use a plurality of conductive layers formed from the above materials in a stacked state. For example, a stacked structure can be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. It is also possible to use a stacked structure by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. It is also possible to use a stacked structure by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0356] For example, when an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 203 of the transistor 200A or 200B, a conductive layer functioning as a gate electrode, such as the conductive layer 205 or the conductive layer 219, may have a stacked structure in which a material containing the metal element described above and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the semiconductor layer 203 side. By providing the conductive material containing oxygen on the semiconductor layer 203 side, oxygen desorbed from the conductive material is easily supplied to a channel formation region of the semiconductor layer 203.

[0357] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 203, the semiconductor layer 263, or the semiconductor layer 520, the conductive layers 208a, 208b, 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b are conductive layers in contact with the semiconductor layer 203, the semiconductor layer 263, or the semiconductor layer 520, and therefore, a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion may be used for each of them. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b.

[0358] By using a conductive material containing oxygen for the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductivity can be maintained even if the conductive layers 208a, 208b, 255, 261, 542a, and 542b absorb oxygen. For example, even when insulating layers containing excess oxygen are used as insulating layers in contact with the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductivity of the conductive layers 208a, 208b, 255, 261, 542a, and 542b can be maintained, which is preferable. For example, ITO, ITSO, IZO (registered trademark), or the like can be used for each of the conductive layer 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b.

[0359] [Semiconductor layer] As the semiconductor layers (semiconductor layer 203, semiconductor layer 230, semiconductor layer 263, semiconductor layer 520, etc.), a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, silicon, germanium, or the like can be used. In addition, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors can also be used. As the compound semiconductor, an organic substance having semiconductor properties or a metal oxide (also referred to as an oxide semiconductor) having semiconductor properties can be used. Note that these semiconductor materials can also contain impurities as dopants.

[0360] The semiconductor layer can be made of a semiconductor made of a single element or a compound semiconductor. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that oxide semiconductors are also a type of compound semiconductor. Note that it is also possible to incorporate impurities as dopants into these semiconductor materials.

[0361] When silicon is used for the semiconductor layer, examples of silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0362] For example, by using silicon for the semiconductor layer 203 of the transistor 200A or 200B and adding phosphorus or arsenic as an n-type dopant to the regions 203a and 203c of the semiconductor layer 203, the transistor can function as an n-type transistor. Also, by adding boron as a p-type dopant to the regions 203a and 203c of the semiconductor layer 203, the transistor can function as a p-type transistor. When the regions 203a and 203c of the semiconductor layer 203 contain both an n-type dopant and a p-type dopant, the conductivity type with the higher dopant concentration is more likely to be realized.

[0363] Two-dimensional materials that function as semiconductors can also be used as the semiconductor layer of a transistor. Two-dimensional materials, also known as layered materials, are a general term for a group of materials with a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. Layered materials have high electrical conductivity within each layer, i.e., high two-dimensional electrical conductivity. Using a material that functions as a semiconductor and has high two-dimensional electrical conductivity for the semiconductor layer can provide a transistor with a high on-state current.

[0364] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides applicable to the semiconductor layer of a transistor include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0365] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer, the band gap of the metal oxide is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the semiconductor layer, the off-state current of the transistor can be significantly reduced. Since an OS transistor has a small off-state current, the power consumption of the semiconductor device can be reduced. Note that the oxide semiconductor will be described in detail in Embodiment 3.

[0366] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0367] (Embodiment 3) In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0368] [Oxide semiconductor layer] An oxide semiconductor layer used as a semiconductor layer of a transistor preferably contains a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (Polycrystalline) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor using the oxide semiconductor layer can be improved, and the reliability of a memory device including the transistor can be improved.

[0369] An oxide semiconductor layer used as a semiconductor layer of a transistor preferably contains a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) are c-axially oriented and connected without being oriented in the ab plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0370] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED), or a combination of these techniques may be used.

[0371] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0372] Examples of metal oxides used for the oxide semiconductor layer include indium oxide (InOx, where X is an arbitrary number), gallium oxide (GaOx, where X is an arbitrary number), and zinc oxide (ZnOx, where X is an arbitrary number). The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0373] Examples of metal oxides according to an embodiment of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), and indium Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0374] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics. Note that even when the metal oxide is indium oxide, the transistor can have a large on-state current and high frequency characteristics.

[0375] The metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0376] The metal oxide may contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0377] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0378] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies is suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0379] In the present embodiment, an In-Ga-Zn oxide may be used as an example of the metal oxide.

[0380] An oxide semiconductor layer used as a semiconductor layer of a transistor preferably has crystallinity, and particularly preferably has a CAAC structure.

[0381] The oxide semiconductor layer can be fabricated by forming a metal oxide using at least two film formation methods. For example, the oxide semiconductor layer can be fabricated by forming a metal oxide using a first film formation method and a second film formation method. Note that an oxide semiconductor layer formed using at least two film formation methods may be referred to as a hybrid OS.

[0382] The oxide semiconductor layer can be manufactured by forming a metal oxide as a first layer by a first deposition method, and then forming a metal oxide as a second layer on the first layer by a second deposition method. In this case, it is preferable to use a deposition method that causes less damage to the surface on which the oxide semiconductor layer is to be formed compared to the second deposition method as the first deposition method. By using a deposition method that causes less damage to the surface on which the oxide semiconductor layer is to be formed as the first deposition method, it is possible to suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is to be formed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer, which can increase the crystallinity of the oxide semiconductor layer.

[0383] Examples of the first film formation method include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-CVD, and metal organic CVD (MOCVD). Examples of wet methods include spray coating. Compared to the sputtering method described below, the ALD and CVD methods are suitable as the first film formation method because they can reduce damage to the surface to be formed.

[0384] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0385] The ALD method allows for the deposition of atoms layer by layer, which allows for the formation of ultrathin films, the formation of films on high-aspect-ratio structures or surfaces with large steps, the formation of films with fewer defects such as pinholes, the formation of films with excellent coverage, and the formation of films at low temperatures. Furthermore, the PEALD method may be preferable because it utilizes plasma, allowing for film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain higher amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In one embodiment of the present invention, a metal oxide film is formed using an ALD method. However, because the ALD method employs one or both of a high substrate temperature condition and an impurity removal treatment during film formation, the amount of carbon and chlorine contained in the film may be smaller than in the case of using an ALD method without these conditions.

[0386] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0387] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. Furthermore, the thermal CVD method produces films with fewer defects because no plasma damage occurs during film formation.

[0388] Examples of the second film formation method include sputtering, pulsed laser deposition (PLD), etc. Metal oxides formed using the second film formation method tend to have a CAAC structure.

[0389] The first layer may be a metal oxide having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure. The crystallinity of the first layer may be increased by forming a second layer having high crystallinity on the first layer having low crystallinity, or by forming the second layer and then performing heat treatment on the second layer. This can increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0390] Furthermore, a third layer can be formed on the second layer. Because the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0391] For example, an oxide semiconductor layer used as a semiconductor layer of a transistor can be fabricated by forming a metal oxide as a first layer using a first deposition method, forming a metal oxide as a second layer using a second deposition method, and forming a metal oxide as a third layer using the first deposition method. Specifically, an ALD method can be used as the first deposition method, and a sputtering method can be used as the second deposition method. The ALD method has better coverage than the sputtering method, and the use of the ALD method as the deposition method for the first layer and the third layer can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0392] [Method for producing oxide semiconductor layer] The semiconductor layer 230, which is an oxide semiconductor layer, can be manufactured by, for example, forming a semiconductor layer 230a on the layer 229, which is a surface to be formed, by an ALD method, forming a semiconductor layer 230b, which is an oxide semiconductor layer, on the semiconductor layer 230a, which is an oxide semiconductor layer, by a sputtering method, and forming a semiconductor layer 230c, which is an oxide semiconductor layer, on the semiconductor layer 230b, by an ALD method. Furthermore, after forming the semiconductor layer 230, which is an oxide semiconductor layer, it is preferable to perform heat treatment. The heat treatment can improve the crystallinity of the semiconductor layer 230. The heat treatment here is not limited to heating treatment. For example, it may be heat applied during the manufacturing process.

[0393] The layer 229 corresponds to the insulating layer 202, the insulating layer 256, the insulating layer 258, or the like described in the above embodiments. The layer 229 does not need to be crystalline. When the layer 229 is crystalline, it may have a crystal structure with low lattice matching with the metal oxide of the semiconductor layer 230.

[0394] An example of a method for manufacturing the semiconductor layer 230 will be described with reference to FIGS. 36A to 36D and 37A to 37D.

[0395] When a metal oxide film is formed by a sputtering method, alloying may occur between components contained in the metal oxide film and components contained in the layer on which the film is formed due to damage caused by sputtering particles on the surface on which the film is formed or by energy imparted to the substrate by the sputtering particles, etc. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. Furthermore, there is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between components contained in the metal oxide film and components contained in the layer on which the film is formed.

[0396] Therefore, first, a semiconductor layer 230a is formed on the layer 229 by ALD (FIG. 36(A)). Subsequently, a semiconductor layer 230b is formed on the semiconductor layer 230a by sputtering (FIG. 36(B)).

[0397] In the above-described method for forming an oxide semiconductor layer, the semiconductor layer 230a is formed between the semiconductor layer 230b and the layer 229 using a film formation method that causes little damage to the surface on which the semiconductor layer 230a is formed. This suppresses alloying of the components contained in the semiconductor layer 230 and the components contained in the layer 229, thereby enabling the crystallinity of the semiconductor layer 230 to be increased.

[0398] By using the above configuration, the thickness of the alloyed region can be reduced, or made so thin that it is difficult to observe. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that Figures 36(A) and 36(B) show an example in which no alloyed region is formed between the layer 229 and the semiconductor layer 230a.

[0399] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0400] For example, EDX line analysis is performed on the above region and its periphery, with the direction perpendicular to the surface of the semiconductor layer 230a to be formed as the depth direction. Next, in the profile of the quantitative values of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (In, if the semiconductor layer 230a contains In) that is the main component of the semiconductor layer 230a but is not the main component of the layer that will become the surface to be formed (here, layer 229) becomes half-value is defined as the depth (position) of the interface between the above region and the semiconductor layer 230a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface to be formed but is not the main component of the semiconductor layer 230a becomes half-value is defined as the depth (position) of the interface between the above region and the layer that will become the surface to be formed. From the above, the thickness of the alloyed region can be calculated.

[0401] When the thickness of the alloyed region in the oxide semiconductor layer is observed by EDX analysis, the thickness is, for example, 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0402] For example, when a silicon oxide layer is used as the layer 229 and a SIMS analysis is performed on the semiconductor layer 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 21 atoms / cm 3 , preferably 5.0 x 10 20 atoms / cm 3 , more preferably 1.0 × 10 20 atoms / cm 3 The distance between the depth at which the thickness decreases and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0403] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0404] By reducing the alloyed region, it becomes possible to form the CAAC structure near the surface to be formed. Here, "near the surface to be formed" refers to, for example, a region from more than 0 nm to 3 nm, preferably more than 0 nm to 2 nm, more preferably 1 nm to 2 nm, approximately perpendicular to the surface to be formed of the semiconductor layer 230.

[0405] The CAAC structure near the surface to be formed can sometimes be confirmed by observation using a TEM. For example, in cross-sectional observation of the semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers parallel to the surface to be formed are confirmed near the surface to be formed.

[0406] When the semiconductor layer 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed. That is, at the manufacturing stage shown in FIG. 36(A), the semiconductor layer 230a may have a region having lower crystallinity than the semiconductor layer 230b.

[0407] The semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure.

[0408] When the semiconductor layer 230b is formed by sputtering, the mixed layer 231 is formed on or near the surface of the semiconductor layer 230a. Furthermore, when the semiconductor layer 230b is formed, sputtering particles or energy imparted to the substrate by the sputtering particles or the like may form minute crystalline regions in the mixed layer 231. In a subsequent heat treatment step, the mixed layer 231 or the minute crystalline regions formed in the mixed layer 231 may act as nuclei to crystallize at least a portion of the semiconductor layer 230a.

[0409] It is preferable to heat the substrate when forming the semiconductor layer 230b by sputtering. In forming the metal oxide, by increasing the substrate temperature (stage temperature) during the formation of the metal oxide, it may be possible to form a metal oxide with high crystallinity.

[0410] Next, the semiconductor layer 230c is formed on the semiconductor layer 230b by the ALD method (FIG. 36(C)). For the formation of the semiconductor layer 230c by the ALD method, the method for forming the semiconductor layer 230a can be referred to.

[0411] When the semiconductor layer 230c is formed on the semiconductor layer 230b having the CAAC structure by the ALD method, the semiconductor layer 230c may grow epitaxially using the semiconductor layer 230b as a nucleus. Therefore, when the semiconductor layer 230c is formed, the semiconductor layer 230c may have a region having the CAAC structure. Furthermore, it is preferable that the region having the CAAC structure is formed over the entire semiconductor layer 230c.

[0412] Next, a heat treatment process may be performed. This heat treatment process may enhance the crystallinity of the region having the CAAC structure in the semiconductor layer 230c. Furthermore, if the region is formed only below the semiconductor layer 230c after film formation by the ALD method, this heat treatment process may cause the region to expand upward (FIG. 36(D)). That is, this heat treatment may cause the region having the CAAC structure to be formed throughout the entire semiconductor layer 230c.

[0413] Furthermore, it is preferable that at least a portion of the semiconductor layer 230a is converted into CAAC by this heat treatment process (FIG. 36(D)). It is expected that the CAAC formation is facilitated by the mixed layer 231 formed in the semiconductor layer 230a during the deposition of the semiconductor layer 230b acting as a nucleus or seed. It is preferable that the region in the semiconductor layer 230a that is converted into CAAC is wide, and it is preferable that the CAAC formation extend to the vicinity of the layer 229.

[0414] Furthermore, because the CAAC process is performed from the top to the bottom of the semiconductor layer 230a, the CAAC process can be performed up to the vicinity of the layer 229, regardless of the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the semiconductor layer 230a can be formed with high crystallinity. Therefore, the method for manufacturing an oxide semiconductor layer disclosed in this embodiment is particularly suitable for the case where a layer on which the oxide semiconductor layer is to be formed has an amorphous structure.

[0415] 36(A) to 36(D) are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. Also, FIGS. 36(A) to 36(D) can be regarded as conceptual diagrams illustrating a film formation model of a metal oxide according to one embodiment of the present invention. As shown in FIGS. 36(A) to 36(D), the semiconductor layers 230a and 230c each have high crystallinity using the highly crystalline semiconductor layer 230b as a nucleus or seed. Specifically, the crystallinity of the semiconductor layer 230a may be increased by heat treatment during or after the formation of the semiconductor layer 230b. The crystallinity of the semiconductor layer 230c may be increased by heat treatment during or after the formation of the semiconductor layer 230c. The heat treatment has an assisting effect of increasing crystallinity.

[0416] As described above, in the method for forming a metal oxide film according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (the semiconductor layers 230a and 230c here) can be increased by using the semiconductor layer 230b (i.e., CAAC) with high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown in a solid phase using the semiconductor layer 230b as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method, that is, a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC). Note that although the structures including the semiconductor layers 230a, 230b, and 230c are illustrated in FIGS. 37A to 37D, the present invention is not limited thereto. For example, the structure including the semiconductor layers 230a and 230b can also be an AG CAAC.

[0417] In the semiconductor layer 230, it is preferable that a region having a CAAC structure is widely present throughout the layer. FIG. 37(A) shows the state in which the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c are each crystallized. At this time, the boundary between the semiconductor layer 230a and the semiconductor layer 230b may not be observed. Also, the boundary between the semiconductor layer 230b and the semiconductor layer 230c may not be observed. The semiconductor layer 230 may be expressed as a single layer whose interface is not clearly observed. The semiconductor layer 230 may be expressed as a single layer.

[0418] Furthermore, there are cases where a portion of the semiconductor layer 230a or the semiconductor layer 230c is not crystallized. The example shown in Figure 37(B) shows that the vicinity of the interface with the layer 229 in the semiconductor layer 230a is not crystallized. Figure 37(C) shows that the vicinity of the surface in the semiconductor layer 230c is not crystallized. Figure 37(D) shows that the vicinity of the interface with the layer 229 in the semiconductor layer 230a and the vicinity of the surface of the semiconductor layer 230c are not crystallized.

[0419] By increasing the crystallinity of the oxide semiconductor layer, an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, which is expected to make the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0420] The oxide semiconductor layer formed by the manufacturing method disclosed in this embodiment has high crystallinity throughout the layer. Therefore, in the semiconductor layer 230, the boundaries between the stacked films of the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c may not be visible. In particular, after heat treatment, it may be difficult to identify the boundaries between the stacked films. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, a TEM or the like.

[0421] As described above, using a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, oxide semiconductors with a high In content tend to become polycrystalline. Using a metal oxide with a polycrystalline structure in a transistor can adversely affect the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the semiconductor layer 230a and the semiconductor layer 230c, crystals that reflect the crystal orientation of the semiconductor layer 230b are formed, thereby suppressing polycrystallization.

[0422] Furthermore, it is preferable that the lattice mismatch between the crystals of the semiconductor layer 230b and the crystals of the semiconductor layer 230a or the semiconductor layer 230c is small. This allows the semiconductor layer 230a or the semiconductor layer 230c to form crystals that reflect the orientation of the crystals of the semiconductor layer 230b. In this case, for example, when a cross section of the semiconductor layer 230 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the semiconductor layer 230a or the semiconductor layer 230c.

[0423] As long as the lattice mismatch between the crystals of the semiconductor layer 230b and the crystals of the semiconductor layer 230a or 230c is small, the crystal structure of the semiconductor layer 230a or 230c is not particularly limited. The crystal structure of the semiconductor layer 230a or 230c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0424] [Composition of oxide semiconductor layer] As described above, the semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. The semiconductor layer 230b can be formed by, for example, sputtering. The semiconductor layer 230b preferably contains, for example, zinc. The inclusion of zinc results in a metal oxide with high crystallinity. The semiconductor layer 230b preferably contains, in addition to zinc, the element M. The inclusion of the element M in the semiconductor layer 230b can, for example, prevent oxygen vacancies from being formed in the metal oxide. Therefore, the reliability of a transistor using an oxide semiconductor layer can be improved. Specifically, the semiconductor layer 230b may be made of a metal oxide having an In:M:Zn=1:1:1 atomic ratio or a similar composition, an In:M:Zn=1:1:1.2 atomic ratio or a similar composition, an In:M:Zn=1:1:0.5 atomic ratio or a similar composition, an In:M:Zn=1:1:2 atomic ratio or a similar composition, an In:M:Zn=4:2:3 atomic ratio or a similar composition, an In:M:Zn=1:3:2 atomic ratio or a similar composition, or an In:M:Zn=1:3:4 atomic ratio or a similar composition. Note that a similar composition includes a ±30% range of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0425] The semiconductor layer 230b may be configured to not contain the element M. For example, In-Zn oxide may be used. Specifically, the composition may be In:Zn=1:1 (atomic ratio) or a composition close thereto, In:Zn=2:1 (atomic ratio) or a composition close thereto, or In:Zn=4:1 (atomic ratio) or a composition close thereto. Alternatively, indium oxide may be used. The semiconductor layer 230b may also be configured to contain a trace amount of the element M. For example, the composition may be In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, or In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition close thereto. Furthermore, the composition may be In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, or In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition close thereto.

[0426] The semiconductor layer 230a and the semiconductor layer 230c can be made of a metal oxide having a high proportion of In. The semiconductor layer 230a and the semiconductor layer 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-current can be increased and the frequency characteristics can be improved.

[0427] The semiconductor layer 230a and the semiconductor layer 230c may be configured to not contain the element M. For example, In-Zn oxide may be used. Specifically, the composition may be an In:Zn=1:1 atomic ratio or a composition thereabout, an In:Zn=2:1 atomic ratio or a composition thereabout, or an In:Zn=4:1 atomic ratio or a composition thereabout. Alternatively, indium oxide may be used. The semiconductor layer 230a and the semiconductor layer 230c may be configured to contain a trace amount of the element M. Specifically, the composition may be an In:Ga:Zn=4:0.1:1 atomic ratio or a composition thereabout, an In:Ga:Zn=2:0.1:1 atomic ratio or a composition thereabout, an In:Sn:Zn=4:0.1:1 atomic ratio or a composition thereabout, or an In:Sn:Zn=2:0.1:1 atomic ratio or a composition thereabout.

[0428] Increasing the proportion of zinc in the oxide semiconductor can improve the crystallinity of the oxide semiconductor. It is particularly preferable that the semiconductor layer 230a contains zinc. For example, when the semiconductor layer 230a is formed by an ALD method and the semiconductor layer 230b is formed by a sputtering method, zinc contained in the semiconductor layer 230a may diffuse into the semiconductor layer 230b. This diffusion may occur during sputtering or subsequent heat treatment. The diffusion of zinc from the semiconductor layer 230a to the semiconductor layer 230b is expected to improve the crystallinity. Alternatively, the diffusion of zinc from the semiconductor layer 230a to the semiconductor layer 230b is expected to promote the lateral growth of crystals with c-axis orientation, thereby promoting the formation of CAAC.

[0429] Furthermore, the semiconductor layer 230a and the semiconductor layer 230c can be made of a metal oxide having a higher proportion of In than the semiconductor layer 230b.

[0430] Alternatively, for example, a metal oxide having a higher Ga content than that of the semiconductor layer 230b may be used for the semiconductor layer 230a and the semiconductor layer 230c. For example, the semiconductor layer 230a and the semiconductor layer 230c may preferably be a metal oxide having an In:Ga:Zn=1:1:1 atomic ratio or a composition similar thereto, a metal oxide having an In:Ga:Zn=1:3:2 atomic ratio or a composition similar thereto, or a metal oxide having an In:Ga:Zn=1:3:4 atomic ratio or a composition similar thereto. Increasing the Ga content may result in the band gaps of the semiconductor layer 230a and the semiconductor layer 230c being larger than that of the semiconductor layer 230b. This allows the semiconductor layer 230b to be sandwiched between the semiconductor layer 230a and the semiconductor layer 230c, which have larger band gaps, and the semiconductor layer 230b functions primarily as a current path (channel). By sandwiching the semiconductor layer 230b between the semiconductor layers 230a and 230c, it is possible to reduce trap levels at the interface of the semiconductor layer 230b and in the vicinity thereof, thereby realizing a buried channel type transistor in which the channel is kept away from the insulating layer interface, and thus increasing the field effect mobility.

[0431] Furthermore, even when the semiconductor layers 230a and 230c are made of a composition that makes it difficult to form a CAAC structure when formed as a single layer, crystal growth occurs with the semiconductor layer 230b as a nucleus, so that the entire oxide semiconductor layer, including the semiconductor layers 230a and 230c, can have a CAAC structure. Alternatively, the CAAC structure can be formed in a region that includes at least a portion of each of the semiconductor layers 230a and 230c and the semiconductor layer 230b.

[0432] In particular, even when the semiconductor layers 230a and 230c have a composition with a high In content, they can have suitable crystallinity for use as semiconductor layers of transistors. In an oxide semiconductor layer used as a semiconductor layer of a transistor, the increase in the In content can improve the on-state characteristics of the transistor, while the CAAC structure with high crystallinity can improve reliability.

[0433] The semiconductor layer 230a and the semiconductor layer 230c may have different compositions.

[0434] The semiconductor layer 230a and the semiconductor layer 230c can be made of a metal oxide having the same composition as the semiconductor layer 230b.

[0435] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods in a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a transistor with high reliability, etc.) can be realized.

[0436] The composition of the metal oxide used in the semiconductor layer 230 can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0437] [c-axis orientation rate] The degree of crystallinity of an oxide semiconductor layer having a CAAC structure can be evaluated using, for example, crystal orientation.

[0438] Crystal orientation can be determined from the Fast Fourier Transform (FFT) pattern obtained by processing a TEM image. Specifically, the direction of the crystal axis can be determined using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice spatial information similar to that of an electron diffraction pattern.

[0439] By performing FFT processing on each region in a TEM image of an oxide semiconductor layer, the crystalline orientation of each region can be obtained. For example, by obtaining the crystalline orientation for each region within a certain area, a map showing the crystalline orientation can be created. Specifically, two spots with high intensity are observed in the FFT pattern of a region having layered crystalline parts. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0440] The c-axis orientation rate can be calculated by calculating the percentage of c-axis oriented regions in a map showing crystal orientation. Here, the c-axis oriented regions are defined as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20° or less.

[0441] The c-axis orientation rate of an oxide semiconductor layer can be calculated, for example, by performing TEM observation of a cross section or a plane of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. The region where FFT is performed is not limited to a circle.

[0442] In an oxide semiconductor layer having a CAAC structure, the c-axis orientation rate is preferably 60% or more, more preferably 70% or more, even more preferably 80% or more, very preferably 90% or more, and most preferably 95% or more.

[0443] The c-axis orientation rates of the region formed as semiconductor layer 230a, the region formed as semiconductor layer 230b, and the region formed as semiconductor layer 230c are defined as Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are each 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0444] After the semiconductor layer 230 is fabricated, the boundaries between the semiconductor layers 230a, 230b, and 230c may not be clearly observed.

[0445] The semiconductor layer 230 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, starting from the top of the layer 229. Each region is a layer-like region.

[0446] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rates of the second region and the third region are each 80% or higher, more preferably 90% or higher, and even more preferably 95% or higher.

[0447] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229, and the third region is located at a distance of 0 nm to 3 nm from the top surface of the semiconductor layer 230.

[0448] Alternatively, the layer thickness in each region may be approximately the same, for example.

[0449] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0450] (Fourth embodiment) In this embodiment, an example of a planar layout and an example of a cross-sectional structure of a semiconductor device 10 according to one embodiment of the present invention will be described. Note that in one embodiment of the present invention, the planar layout and cross-sectional structure of transistors constituting the semiconductor device 10 will be described. To facilitate understanding of the arrangement of transistors constituting the semiconductor device 10, descriptions of insulating layers, capacitors, light-emitting elements, and the like will be omitted. In addition, to reduce repetition of explanation, matters not described in other embodiments will be mainly described. For matters not described in this embodiment, the other embodiments can be referred to.

[0451] 38 and 40 are diagrams showing an example of a planar layout of the semiconductor device 10A shown in FIG. 1. Fig. 39(A) is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in Fig. 38. Fig. 39(B) is a cross-sectional view taken along the line A3-A4 indicated by the dashed dotted line in Fig. 38. In this embodiment, the transistor 200F shown in Fig. 29 is used as the transistor constituting the semiconductor device 10.

[0452] Fig. 41 is a diagram showing an example of a planar layout of the semiconductor device 10E shown in Fig. 9. Fig. 42 is a diagram showing an example of a planar layout of the semiconductor device 10G shown in Fig. 11. Fig. 43(A) is a cross-sectional view taken along line B1-B2 indicated by a dashed line in Fig. 42. Fig. 43(B) is a cross-sectional view taken along line B3-B4 indicated by a dashed line in Fig. 42.

[0453] 38, 39(A) and 39(B) show examples of the planar layout and cross-sectional configuration of the semiconductor device 10A when the channel length L of the transistors M1 and M2 is longer than the channel length L of the transistors M3 to M7.

[0454] The planar layout of the semiconductor device 10A shown in Figure 40 shows an example in which the channel length L of transistors M3, M4, and M7 is set longer than the channel length L of transistors M5 and M6, and the channel length L of transistors M1 and M2 is set longer than the channel length L of transistors M3, M4, and M7.

[0455] FIG. 41 shows a planar layout of a semiconductor device 10E in which the transistors M1, M2, M3, M4, and M7 are multi-gate transistors with three transistors connected in series, and the transistors M5 and M6 are single-gate transistors.

[0456] Figures 42, 43(A), and 43(B) show the planar layout of a semiconductor device 10G in which transistors M1 and M2 are multi-gate transistors with three transistors connected in series, transistors M3, M4, and M7 are multi-gate transistors with two transistors connected in series, and transistors M5 and M6 are single-gate transistors.

[0457] The examples of planar layouts and cross-sectional structures shown in this embodiment differ in the channel length L of the transistor or the number of series-connected multi-gate transistors, but the connection structures of wiring and the like are similar. Therefore, in this embodiment, Figures 38, 39(A), and 39(B) will be described as representative examples.

[0458] 38 includes a conductive layer 211, a conductive layer 212, a conductive layer 213, a conductive layer 214, a conductive layer 215, and a conductive layer 216 over an insulating layer 514. Also includes a conductive layer 221, a conductive layer 222, a conductive layer 223, a conductive layer 224, and a conductive layer 225 over an insulating layer 550. Also includes a conductive layer 271, a conductive layer 272, a conductive layer 273, a conductive layer 274, a conductive layer 275, a conductive layer 276, a conductive layer 277, a conductive layer 278, a conductive layer 279, a conductive layer 281, and a conductive layer 282 over an insulating layer 581. These conductive layers can be formed using the materials shown in Embodiment 2.

[0459] In addition, an insulating layer 248 is provided over the conductive layer 271, the conductive layer 272, the conductive layer 273, the conductive layer 274, the conductive layer 275, the conductive layer 276, the conductive layer 277, the conductive layer 278, the conductive layer 279, the conductive layer 281, and the conductive layer 282 (see Figures 39(A) and (B)).

[0460] 39A shows an example cross-sectional structure of the transistor M1. Part of the conductive layer 216 functions as the conductive layer 505. Therefore, part of the conductive layer 216 functions as the back gate of the transistor M1. Furthermore, part of the conductive layer 225 functions as the conductive layer 560. Therefore, part of the conductive layer 225 functions as the gate of the transistor M1. The conductive layer 216 and the conductive layer 225 are connected to each other through the conductive layer 281.

[0461] The conductive layer 216 and the conductive layer 225 are connected to a wiring GLa (not shown in FIG. 38). Note that the conductive layer 216 and the conductive layer 225 can also function as a wiring GLa. The conductive layer 282 is connected to one of the source and the drain of the transistor M1. Specifically, the conductive layer 282 is connected to the semiconductor layer 520[1] through the conductive layer 545a[1] and the conductive layer 542a[1] (see FIG. 39(A)). The conductive layer 282 is connected to a wiring DL. Note that the conductive layer 282 can also function as a wiring DL.

[0462] The conductive layer 274 is connected to the other of the source and the drain of the transistor M1. Specifically, the conductive layer 274 is connected to the semiconductor layer 520[1] through the conductive layer 545b[1] and the conductive layer 542b[1] (see FIG. 39A).

[0463] The conductive layer 274 is connected to the conductive layer 222. A part of the conductive layer 222 functions as the gate of the transistor M2. The conductive layer 275 is connected to one of the source and the drain of the transistor M2. The conductive layer 275 is also connected to the wiring 101 (not shown in FIG. 38). The conductive layer 273 is connected to the other of the source and the drain of the transistor M2.

[0464] A part of the conductive layer 211 functions as the back gate of the transistor M4, and another part functions as the back gate of the transistor M3. A part of the conductive layer 221 functions as the gate of the transistor M4, and another part functions as the gate of the transistor M3. The conductive layer 211 and the conductive layer 221 are connected to the wiring GLb (not shown in FIG. 38). The conductive layer 211 and the conductive layer 221 can also function as the wiring GLb.

[0465] 39B shows an example cross-sectional structure of the transistor M3. Part of the conductive layer 211 functions as the conductive layer 505. Part of the conductive layer 221 functions as the conductive layer 560. The conductive layer 274 is connected to one of the source and drain of the transistor M3. Specifically, the conductive layer 274 is connected to the semiconductor layer 520[3] through the conductive layer 545b[3] and the conductive layer 542b[3] (see FIG. 39B).

[0466] The conductive layer 273 is connected to the other of the source and the drain of the transistor M3. Specifically, the conductive layer 273 is connected to the semiconductor layer 520[3] through the conductive layer 545a[3] and the conductive layer 542a[3] (see FIG. 39B).

[0467] The conductive layer 271 is connected to one of the source and drain of the transistor M4. The conductive layer 271 is connected to the wiring 102 (not shown in FIG. 38). The conductive layer 271 can also function as the wiring 102.

[0468] The conductive layer 272 is connected to the other of the source and the drain of the transistor M4. The conductive layer 272 is also connected to the conductive layer 212. A part of the conductive layer 212 functions as the back gate of the transistor M2.

[0469] The conductive layer 273 is connected to one of the source and drain of the transistor M5. The conductive layer 276 is connected to the other of the source and drain of the transistor M5. The conductive layer 276 is connected to a first terminal of the light-emitting element 61. The conductive layer 276 can also function as the first terminal of the light-emitting element 61.

[0470] The conductive layer 273 is connected to one of the source and the drain of the transistor M6. The conductive layer 279 is connected to the other of the source and the drain of the transistor M6. The conductive layer 279 is connected to the wiring 103 (not shown in FIG. 38). The conductive layer 279 can also function as the wiring 103.

[0471] A part of the conductive layer 214 functions as the back gate of the transistor M6, and another part functions as the back gate of the transistor M7. A part of the conductive layer 224 functions as the gate of the transistor M6, and another part functions as the gate of the transistor M7. The conductive layer 214 and the conductive layer 224 are connected to the wiring GLd (not shown in FIG. 38). The conductive layer 214 and the conductive layer 224 can also function as the wiring GLd.

[0472] The conductive layer 215 is connected to one of the source and drain of the transistor M7 via a conductive layer 278. The conductive layer 215 is connected to a wiring GLc (not shown in FIG. 38). The conductive layer 215 can also function as the wiring GLc.

[0473] The conductive layer 277 is connected to the other of the source and the drain of the transistor M7. The conductive layer 277 is also connected to the conductive layers 213 and 223. A part of the conductive layer 213 functions as the back gate of the transistor M5. A part of the conductive layer 223 functions as the gate of the transistor M5.

[0474] Although not shown in this embodiment, a capacitor C1 is provided between the conductive layer 273 and the conductive layer 274. A capacitor C2 is provided between the conductive layer 272 and the conductive layer 273. A capacitor C3 is provided between the conductive layer 276 and the conductive layer 277.

[0475] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0476] (Embodiment 5) A semiconductor device according to one embodiment of the present invention can be applied to a display device or the like. Furthermore, a semiconductor device according to one embodiment of the present invention can be applied to a module (also referred to as a "display module") including the display device. In this embodiment, a display device including a semiconductor device according to one embodiment of the present invention will be described.

[0477] Examples of display modules include a module in which a connector such as a flexible printed circuit (FPC) or a TCP (Tape Carrier Package) is attached to a display device, or a module in which an IC (integrated circuit) chip is mounted using a COG (Chip On Glass) method or a COF (Chip On Film) method.

[0478] <Example of display device configuration> FIG. 44A is a perspective view illustrating a configuration example of a display device 400 according to one embodiment of the present invention.

[0479] The display device 400 has a structure in which a substrate 411 and a substrate 451 are bonded together. In Fig. 44(A), the substrate 411 is indicated by a dashed line.

[0480] The display device 400 includes a display portion 452, a circuit portion 454a, a circuit portion 454b, a connection portion 457, and a wiring portion 458. Fig. 44A shows an example in which an IC 456 and an FPC 459 are mounted on the display device 400. Therefore, the configuration shown in Fig. 44A can also be said to be a display module including the display device 400, an IC, and an FPC.

[0481] The circuit portion 454a includes, for example, a scan line driver circuit (also referred to as a gate driver or a scan driver), and the circuit portion 454b includes, for example, a signal line driver circuit (also referred to as a source driver or a data driver).

[0482] The wiring portion 458 has a function of supplying signals and power to the display portion 452, the circuit portion 454a, and the circuit portion 454b. The signals and power are input to the wiring portion 458 from the outside of the display device 400 via an FPC 459. Alternatively, the signals and power are input to the wiring portion 458 from an IC 456.

[0483] 44A shows an example in which an IC 456 is provided on a substrate 451 by a COG method, a COF method, or the like. For example, an IC having one or both of a scan line driver circuit and a signal line driver circuit can be used as the IC 456. Note that the display device 400 and the display module can be configured without an IC. Furthermore, the IC 456 can also be mounted on an FPC by a COF method or the like.

[0484] It is possible to configure a scanning line driver circuit using either or both of IC 456 and circuit unit 454a. In this case, IC 456 may be referred to as a gate driver IC. It is also possible to configure a signal line driver circuit using either or both of IC 456 and circuit unit 454b. In this case, IC 456 may be referred to as a source driver IC.

[0485] The display section 452 is a region in the display device 400 that displays an image, and has a plurality of periodically arranged pixels 455. An enlarged view of one pixel 455 is shown in FIG.

[0486] The pixel 455 shown in FIG. 44A includes a pixel 453R that emits red (R) light, a pixel 453G that emits green (G) light, and a pixel 453B that emits blue (B) light. A full-color display can be achieved by configuring one pixel 455 with the pixels 453R, 453G, and 453B. The pixels 453R, 453G, and 453B each function as a sub-pixel. The display device 400 shown in FIG. 44A illustrates an example in which the pixels 453R, 453B, and 453G that function as sub-pixels are arranged in a stripe array. The number of sub-pixels that configure one pixel 455 is not limited to three and can be four or more. For example, the pixel 455 can have four sub-pixels that emit R, G, B, and white (W) light, respectively. Alternatively, the pixel 455 can have four sub-pixels that emit R, G, B, and yellow (Y) light, respectively.

[0487] In this specification, elements relating to red light may be identified by the identification symbol "R," elements relating to green light by the identification symbol "G," and elements relating to blue light by the identification symbol "B," and these elements may be described separately. Also, common elements may be described without identifying the elements. For example, when it is necessary to distinguish between multiple pixels 453, they may be referred to as pixel 453R, pixel 453G, or pixel 453B. Furthermore, when it is not necessary to distinguish between pixel 453R, pixel 453G, and pixel 453B, they may be simply referred to as pixel 453.

[0488] Each of the pixels 453R, 453G, and 453B includes a light-emitting element and a circuit (pixel circuit) that controls the light-emitting luminance of the light-emitting element. The semiconductor device 10 of one embodiment of the present invention can be used as the pixel 453.

[0489] The connection portion 457 is provided outside the display portion 452. The connection portion 457 can be provided along one side or multiple sides of the display portion 452. The connection portion 457 may be single or multiple. FIG. 44A shows an example in which the connection portion 457 is provided so as to surround the four sides of the display portion. The connection portion 457 connects a common electrode of a display element and a wiring portion 458, and can supply a potential to the common electrode.

[0490] Here, for example, the transistor described in any of the above embodiments can be used in at least part of the display portion 452, the circuit portion 454a, and the circuit portion 454b included in the display device 400.

[0491] For example, by using a vertical transistor such as the above-described transistor 200C for one or both of the circuit portion 454a and the circuit portion 454b, the area occupied by the circuit portion 454a and the circuit portion 454b can be reduced, resulting in a display device with a narrow frame.

[0492] Furthermore, for example, by using a vertical transistor such as the transistor 200C or the transistor 200D described above in a pixel circuit included in the display portion 452, the area occupied by the pixel circuit can be reduced, and the resolution of the display device can be increased. For example, a display device with a resolution of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be realized.

[0493] Note that the display device of one embodiment of the present invention can also function as a touch panel. For example, various sensing elements (also referred to as sensor elements) that can detect the proximity or contact of a sensed object such as a finger can be applied to the display device.

[0494] Examples of sensor types include capacitance type, resistive film type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type.

[0495] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0496] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that the in-cell type touch panel has a configuration in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element (also called a display device) and an opposing substrate.

[0497] [Pixel array] 44(B) to 44(F) are plan views illustrating pixel arrays. In a display device according to one embodiment of the present invention, the pixel array is not particularly limited, and various arrays can be applied. Examples of pixel arrays include a stripe array (see FIG. 44(B)), an S-stripe array (see FIG. 44(C)), a delta array (see FIG. 44(D)), a zigzag array (see FIG. 44(E)), and a Pentile array (see FIG. 44(F)). Other examples include a mosaic array, a diamond array, and a Bayer array.

[0498] 44(B) to 44(F), examples of the top surface shape of each subpixel (pixel 453R, pixel 453G, and pixel 453B) include a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon, shapes with rounded corners of these polygons, an ellipse, and a circle. Here, the top surface shape of each subpixel corresponds to the top surface shape of the display area of the display element included in each subpixel. The top surface shape and size of each subpixel can be determined independently. Note that the arrangements of the pixel 453R, pixel 453G, and pixel 453B may be interchanged as appropriate. The display elements and pixel circuits may be arranged in the same manner or in different manners.

[0499] Here, the pentile arrangement is a special pixel arrangement that artificially enhances the resolution. Therefore, a stripe arrangement, for example, can be adopted in a display device. In one embodiment of the present invention, vertical transistors such as the above-described transistor 200C or transistor 200D are used for some or all of the transistors constituting a pixel circuit, thereby reducing the area occupied by the pixel circuit. Therefore, the pixel arrangement can be changed from the pentile arrangement to, for example, a stripe arrangement without reducing the resolution of the display device.

[0500] [Light-emitting element] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs, organic EL elements (also called OLEDs (organic LEDs)), and semiconductor lasers. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0501] Examples of light-emitting materials that light-emitting elements have include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (quantum dot materials, etc.).

[0502] The light emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light emitting element with a microcavity structure.

[0503] One of a pair of electrodes or a pair of terminals included in a light-emitting element functions as an anode (also referred to as an anode electrode), and the other functions as a cathode (also referred to as a cathode electrode).

[0504] In this embodiment, an example in which an organic EL element is used as a light-emitting element will be described. Therefore, a display device 400 according to one embodiment of the present invention is a display device using an organic EL element.

[0505] The display device 400 according to one embodiment of the present invention is suitable for any of a top emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed, a bottom emission type that emits light toward the substrate on which the light-emitting element is formed, and a dual emission type that emits light on both sides.

[0506] For example, by using a vertical transistor such as the above-described transistor 200C or transistor 200D, the area occupied by the pixel circuit can be reduced, thereby increasing the aperture ratio of the pixel, particularly in bottom-emission display devices and dual-emission display devices, and realizing a display device with an aperture ratio of, for example, 50% or more, 55% or more, or 60% or more.

[0507] In this specification and the like, the aperture ratio refers to the ratio of the area of the region from which light is emitted per pixel to the area occupied by one pixel.

[0508] <Configuration example of light-emitting element> A light-emitting element 61 that can be used in a display device according to one embodiment of the present invention will be described.

[0509] As shown in FIG. 45A, the light-emitting element 61 includes an EL layer 172 between a conductive layer 171 and a conductive layer 173. The EL layer 172 can be composed of a plurality of layers, such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can include, for example, a layer containing a substance with high electron-injecting properties (electron-injecting layer) and a layer containing a substance with high electron-transporting properties (electron-transporting layer). The light-emitting layer 4411 includes, for example, a light-emitting compound. The layer 4430 can include, for example, a layer containing a substance with high hole-injecting properties (hole-injecting layer) and a layer containing a substance with high hole-transporting properties (hole-transporting layer).

[0510] A structure including the layer 4420 provided between the conductive layer 171 and the conductive layer 173 functioning as electrodes, the light-emitting layer 4411, and the layer 4430 can function as a single light-emitting unit, and in this specification, the structure of Figure 45(A) is called a single structure.

[0511] 45(B) shows a modified example of the EL layer 172 included in the light-emitting element 61 shown in Fig. 45(A). Specifically, the light-emitting element 61 shown in Fig. 45(B) includes a layer 4430-1 on the conductive layer 171, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and a conductive layer 173 on the layer 4420-2. For example, when the conductive layer 171 is an anode and the conductive layer 173 is a cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. Alternatively, when the conductive layer 171 is used as a cathode and the conductive layer 173 is used as an anode, the layer 4430-1 functions as an electron injection layer, the layer 4430-2 functions as an electron transport layer, the layer 4420-1 functions as a hole transport layer, and the layer 4420-2 functions as a hole injection layer. By using such a layer structure, it is possible to efficiently inject carriers into the light-emitting layer 4411 and increase the efficiency of carrier recombination in the light-emitting layer 4411.

[0512] Note that a structure in which a plurality of light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between the layer 4420 and the layer 4430 as shown in FIG. 45C is also an example of a single structure.

[0513] 45(D), a configuration in which a plurality of light-emitting units (EL layers 172a and 172b) are connected in series via an intermediate layer (charge generation layer) 4440 is referred to as a tandem structure or a stack structure in this specification and the like. Note that the tandem structure makes it possible to realize a light-emitting element capable of emitting light with high brightness.

[0514] 45(D), the EL layers 172a and 172b preferably emit the same light. For example, the EL layers 172a and 172b preferably emit green light.

[0515] Note that a full-color display can be achieved by using three sub-pixels: a light-emitting element 61 emitting red light (R), a light-emitting element 61 emitting green light (G), and a light-emitting element 61 emitting blue light (B). When a pixel includes three sub-pixels of R, G, and B, it is preferable that the light-emitting elements 61 be arranged in tandem. Specifically, the EL layer 172a and the EL layer 172b of the R sub-pixel each contain a material capable of emitting red light, the EL layer 172a and the EL layer 172b of the G sub-pixel each contain a material capable of emitting green light, and the EL layer 172a and the EL layer 172b of the B sub-pixel each contain a material capable of emitting blue light. In other words, the light-emitting layer 4411 and the light-emitting layer 4412 can be made of the same material. By making the EL layer 172a and the EL layer 172b emit the same light, the current density per unit of luminance can be reduced. Therefore, the reliability of the light emitting element 61 can be improved.

[0516] The light-emitting element can emit light in red, green, blue, cyan, magenta, yellow, or white, depending on the material of the EL layer 172. Furthermore, the color purity can be further improved by providing the light-emitting element with a microcavity structure.

[0517] The light-emitting layer can contain two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. For example, a light-emitting element that emits white light preferably has a configuration in which the light-emitting layer contains two or more types of light-emitting materials. To obtain white light emission, light-emitting materials are selected such that the emissions of two light-emitting materials have a complementary color relationship, or light-emitting materials are selected such that the emissions of two or more light-emitting materials combine to produce white light. For example, when white light emission is obtained using two light-emitting layers, a light-emitting element that emits white light as a whole can be obtained by adjusting the emission colors of the two light-emitting layers to have a complementary color relationship. Furthermore, when white light emission is obtained using three or more light-emitting layers, a light-emitting element that emits white light as a whole can be obtained by combining the emission colors of the three or more light-emitting layers.

[0518] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0519] Examples of light-emitting substances include fluorescent materials, phosphorescent materials, and thermally activated delayed fluorescence (TADF materials). Light-emitting substances used in EL elements include not only organic compounds but also inorganic compounds (such as quantum dot materials).

[0520] <Method for forming light-emitting element> An example of a method for forming the light emitting element 61 will be described below.

[0521] FIG. 46(A) shows a schematic top view of a light-emitting element 61. The light-emitting element 61 has a plurality of light-emitting elements 61R that emit red light, a plurality of light-emitting elements 61G that emit green light, and a plurality of light-emitting elements 61B that emit blue light. In FIG. 46(A), the symbols R, G, and B are assigned within the light-emitting region of each light-emitting element to easily distinguish between the light-emitting elements. Also, FIG. 46(A) illustrates a configuration having three emitted light colors, red (R), green (G), and blue (B), but this is not limiting. For example, a configuration having four or more colors is also possible.

[0522] The light emitting elements 61R, 61G, and 61B are arranged in a matrix. Fig. 46(A) shows a so-called stripe arrangement in which light emitting elements of the same color are arranged in one direction, but the arrangement of the light emitting elements is not limited to this.

[0523] As the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B, it is preferable to use an organic EL device such as an OLED or a QLED. Examples of the light-emitting substance contained in the EL element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF material). As the light-emitting substance contained in the EL element, not only organic compounds but also inorganic compounds (such as quantum dot materials) can be used.

[0524] FIG. 46(B) is a schematic cross-sectional view corresponding to the dashed line A1-A2 in FIG. 46(A). FIG. 46(B) shows cross sections of the light-emitting elements 61R, 61G, and 61B. The light-emitting elements 61R, 61G, and 61B are each provided on an insulating layer 363 and include a conductive layer 171 functioning as a pixel electrode and a conductive layer 173 functioning as a common electrode. The insulating layer 363 can be an inorganic insulating film or an organic insulating film, or both. It is preferable to use an inorganic insulating film as the insulating layer 363. Examples of inorganic insulating films include oxide insulating films and nitride insulating films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film.

[0525] The light-emitting element 61R has an EL layer 172R between the conductive layer 171 functioning as a pixel electrode and the conductive layer 173 functioning as a common electrode. The EL layer 172R contains a light-emitting organic compound that emits light having a peak in at least the red wavelength range. The EL layer 172G of the light-emitting element 61G contains a light-emitting organic compound that emits light having a peak in at least the green wavelength range. The EL layer 172B of the light-emitting element 61B contains a light-emitting organic compound that emits light having a peak in at least the blue wavelength range.

[0526] The EL layer 172R, the EL layer 172G, and the EL layer 172B may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting substance (light-emitting layer).

[0527] The conductive layer 171 functioning as a pixel electrode is provided for each light-emitting element. The conductive layer 173 functioning as a common electrode is provided as a continuous layer common to each light-emitting element. A conductive film that is transparent to visible light is used for either the conductive layer 171 functioning as a pixel electrode or the conductive layer 173 functioning as a common electrode, and a conductive film that is reflective is used for the other. By making the conductive layer 171 functioning as a pixel electrode light-transmitting and the conductive layer 173 functioning as a common electrode light-reflective, a bottom-emission display device can be obtained. Conversely, by making the conductive layer 171 functioning as a pixel electrode light-transmitting and the conductive layer 173 functioning as a common electrode light-transmitting, a top-emission display device can be obtained. Note that by making both the conductive layer 171 functioning as a pixel electrode and the conductive layer 173 functioning as a common electrode light-transmitting, a dual-emission display device can also be obtained.

[0528] For example, when the light emitting element 61R is a top emission type, the light 175R emitted from the light emitting element 61R is emitted toward the conductive layer 173. When the light emitting element 61G is a top emission type, the light 175G emitted from the light emitting element 61G is emitted toward the conductive layer 173. When the light emitting element 61B is a top emission type, the light 175B emitted from the light emitting element 61B is emitted toward the conductive layer 173.

[0529] An insulator 372 is provided to cover an edge portion of the conductive layer 171 functioning as a pixel electrode. The edge portion of the insulator 372 preferably has a tapered shape. The insulator 372 can be formed using a material similar to that of the insulating layer 363.

[0530] The insulator 372 is provided to prevent erroneous light emission due to unintentional electrical short circuit between adjacent light-emitting elements 61. In addition, when a metal mask is used to form the EL layer 172, the insulator 372 also functions to prevent the metal mask from coming into contact with the conductive layer 171.

[0531] The EL layer 172R, the EL layer 172G, and the EL layer 172B each have a region in contact with the upper surface of the conductive layer 171 that functions as a pixel electrode, and a region in contact with the surface of the insulator 372. In addition, the ends of the EL layer 172R, the EL layer 172G, and the EL layer 172B are located on the insulator 372.

[0532] As shown in Figure 46(B), a gap is provided between the two EL layers of light-emitting elements that emit different colors of light. In this way, it is preferable that the EL layer 172R, the EL layer 172G, and the EL layer 172B are provided so as not to be in contact with each other. This makes it possible to effectively prevent current from flowing through two adjacent EL layers, resulting in unintended light emission (also known as crosstalk). This allows for increased contrast, resulting in a display device with high display quality.

[0533] The EL layer 172R, the EL layer 172G, and the EL layer 172B can be separately fabricated by vacuum deposition using a shadow mask such as a metal mask. Alternatively, they can be separately fabricated by photolithography. By using photolithography, it is possible to realize a high-definition display device that is difficult to achieve using a metal mask.

[0534] In this specification, etc., a device fabricated using a metal mask or FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or FMM may be referred to as a device with an MML (metal maskless) structure. Because a display device with an MML structure is fabricated without using a metal mask, it has a higher degree of design freedom for pixel arrangement, pixel shape, etc. than a display device with an MM structure.

[0535] In addition, a protective layer 371 is provided on the conductive layer 173, which functions as a common electrode, to cover the light-emitting elements 61R, 61G, and 61B. The protective layer 371 has a function of preventing impurities such as water from diffusing from above into each light-emitting element.

[0536] The protective layer 371 may have, for example, a single-layer structure or a stacked structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide (IGZO) may be used for the protective layer 371. The protective layer 371 may be formed by an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, or a sputtering method. Although the protective layer 371 includes an inorganic insulating film, the present invention is not limited to this. For example, the protective layer 371 may have a stacked structure including an inorganic insulating film and an organic insulating film.

[0537] In this specification, "nitride oxide" refers to a compound containing more nitrogen than oxygen. "Oxynitride" refers to a compound containing more oxygen than nitrogen. The content of each element can be measured, for example, by Rutherford Backscattering Spectrometry (RBS).

[0538] When indium gallium zinc oxide is used for the protective layer 371, it can be processed using a wet etching method or a dry etching method. For example, when IGZO is used for the protective layer 371, a chemical solution such as oxalic acid, phosphoric acid, or a mixed chemical solution (for example, a mixed chemical solution of phosphoric acid, acetic acid, nitric acid, and water (also called a mixed acid aluminum etchant)) can be used. The mixed acid aluminum etchant can have a volume ratio of phosphoric acid:acetic acid:nitric acid:water=53.3:6.7:3.3:36.7 or a similar ratio.

[0539] The structure shown in FIG. 46(B) may be called an SBS structure, which will be described later.

[0540] 46C shows a different example. Specifically, FIG. 46C shows a light-emitting element 61W that emits white light. The light-emitting element 61W has an EL layer 172W that emits white light between a conductive layer 171 that functions as a pixel electrode and a conductive layer 173 that functions as a common electrode.

[0541] The EL layer 172W may be configured by stacking two or more light-emitting layers selected so that the emitted light colors are complementary to each other. Alternatively, a stacked EL layer may be used in which a charge generating layer is sandwiched between light-emitting layers.

[0542] FIG. 46(C) shows three light-emitting elements 61W lined up. A colored layer 264R is provided above the left light-emitting element 61W. The colored layer 264R functions as a bandpass filter that transmits red light. Similarly, a colored layer 264G that transmits green light is provided above the center light-emitting element 61W, and a colored layer 264B that transmits blue light is provided above the right light-emitting element 61W. This allows the display device to display color images.

[0543] Here, the EL layer 172W and the conductive layer 173 functioning as a common electrode are separated between two adjacent light-emitting elements 61W. This prevents unintended light emission due to current flowing through the EL layer 172W between the two adjacent light-emitting elements 61W. In particular, when a stacked EL layer in which a charge-generating layer is provided between two light-emitting layers is used as the EL layer 172W, the higher the resolution, i.e., the smaller the distance between adjacent pixels, the more pronounced the effect of crosstalk becomes, resulting in a decrease in contrast. Therefore, by using this configuration, a display device that combines high resolution and high contrast can be realized.

[0544] The EL layer 172W and the conductive layer 173 functioning as a common electrode are preferably separated by photolithography, which allows the distance between light-emitting elements to be narrowed, thereby realizing a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0545] In the case of a bottom-emission light-emitting element, a colored layer may be provided between the conductive layer 171 functioning as a pixel electrode and the insulating layer 363 .

[0546] FIG. 46D shows an example different from the above. Specifically, FIG. 46D shows a configuration in which the insulator 372 is not provided between the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B. This configuration allows a display device with a high aperture ratio. Furthermore, omitting the insulator 372 reduces the unevenness of the light-emitting element 61, thereby improving the viewing angle of the display device. Specifically, the viewing angle can be set to 150 degrees or more and less than 180 degrees, preferably 160 degrees or more and less than 180 degrees.

[0547] Furthermore, the protective layer 371 covers the side surfaces of the EL layer 172R, the EL layer 172G, and the EL layer 172B. This configuration can suppress impurities (typically, water, etc.) that can enter from the side surfaces of the EL layer 172R, the EL layer 172G, and the EL layer 172B. Furthermore, since the leakage current between adjacent light-emitting elements 61 is reduced, the color saturation and contrast ratio are improved and power consumption is reduced.

[0548] 46(D), the planar shapes of the conductive layer 171, the EL layer 172R, and the conductive layer 173 are approximately the same. Such a structure can be formed collectively by using a resist mask or the like after the conductive layer 171, the EL layer 172R, and the conductive layer 173 are formed. This process can also be called self-aligned patterning because the EL layer ...

Claims

1. The light emitting device includes first to seventh transistors, first to third capacitance elements, and a light emitting element, each of the first to seventh transistors has a gate, a first terminal, and a second terminal; each of the first to third capacitance elements and the light emitting element has a first terminal and a second terminal; the second transistor has a back gate; a second terminal of the first transistor is electrically connected to a gate of the second transistor, a first terminal of the third transistor, and a first terminal of the first capacitive element; a back gate of the second transistor is electrically connected to a second terminal of the fourth transistor and a first terminal of the second capacitive element; a second terminal of the second transistor is electrically connected to a second terminal of the third transistor, a second terminal of the first capacitance element, a second terminal of the second capacitance element, a first terminal of the fifth transistor, and a first terminal of the sixth transistor; a gate of the fifth transistor is electrically connected to a first terminal of the third capacitance element and a second terminal of the seventh transistor; a second terminal of the fifth transistor is electrically connected to a second terminal of the third capacitance element and a first terminal of the light emitting element; A semiconductor device in which the channel length of the first transistor is longer than the channel length of each of the third transistor, the fourth transistor, and the seventh transistor.

2. The light emitting device includes first to seventh transistors, first to third capacitance elements, and a light emitting element, each of the first to seventh transistors has a gate, a first terminal, and a second terminal; each of the first to third capacitance elements and the light emitting element has a first terminal and a second terminal; the second transistor has a back gate; a second terminal of the first transistor is electrically connected to a gate of the second transistor, a first terminal of the third transistor, and a first terminal of the first capacitive element; a back gate of the second transistor is electrically connected to a second terminal of the fourth transistor and a first terminal of the second capacitive element; a second terminal of the second transistor is electrically connected to a second terminal of the third transistor, a second terminal of the first capacitance element, a second terminal of the second capacitance element, a first terminal of the fifth transistor, and a first terminal of the sixth transistor; a gate of the fifth transistor is electrically connected to a first terminal of the third capacitance element and a second terminal of the seventh transistor; a second terminal of the fifth transistor is electrically connected to a second terminal of the third capacitance element and a first terminal of the light emitting element; the first transistor is a multi-gate transistor connected in series three or more times, The third transistor, the fourth transistor, and the seventh transistor are each a multi-gate transistor whose number of series connections is equal to or less than the number of series connections of the first transistor.

3. In claim 1 or claim 2, a gate of the first transistor electrically connected to a first wiring; a gate of the third transistor and a gate of the fourth transistor are electrically connected to a second wiring; a first terminal of the seventh transistor is electrically connected to a third wiring; a gate of the sixth transistor and a gate of the seventh transistor are electrically connected to a fourth wiring; a first terminal of the first transistor is electrically connected to a fifth wiring; a first terminal of the second transistor is electrically connected to a sixth wiring; a first terminal of the fourth transistor is electrically connected to a seventh wiring; a second terminal of the sixth transistor is electrically connected to an eighth wiring; The second terminal of the light emitting element is electrically connected to a ninth wiring.

4. In claim 1 or claim 2, A semiconductor device in which a semiconductor layer in which a channel of the first transistor is formed includes an oxide semiconductor.

5. In claim 1 or claim 2, The light-emitting element is an organic EL element.

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