Driver, electro-optical device, and electronic device

Abstract

To provide a driver or the like capable of correcting a data voltage error because of a charge error when switching a data line in capacity drive.SOLUTION: A driver 100 includes a capacitor drive circuit 20, a capacitor circuit 10, and a control circuit 40. The control circuit 40 obtains correction data on the basis of first gradation data when a first period is switched to a second period. During the first period, a first switch between a signal supply line and a first data line is on and the first gradation data is used. During the second period, a second switch between the signal supply line and a second data line is on and second gradation data is used. The correction data corrects a voltage error for a target voltage corresponding to the second gradation data that is generated when the first data line is switched to the second data line. The control circuit 40 outputs capacity drive data during the second period on the basis of capacity drive data and correction data during the first period.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to a driver, an electro-optical device, an electronic device, and the like. [Background technology]

[0002] Patent Document 1 discloses a driver that capacitively drives an electro-optical panel. The driver in Patent Document 1 includes a capacitor circuit connected to a data voltage output terminal, a capacitor drive circuit that drives the capacitor circuit, and a variable capacitance circuit connected to the data voltage output terminal. The capacitance of the variable capacitance circuit is set so that the capacitance obtained by adding the capacitance of the variable capacitance circuit and the capacitance of the electro-optical panel has a given capacitance ratio relationship with the capacitance of the capacitor circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-80805 Summary of the Invention [Problem to be solved by the invention]

[0004] To improve display quality, the driver applies a precharge voltage to the data lines before writing data voltages to the pixels. Also, methods such as demultiplexing and phase-expansion driving are known in which one driver output drives multiple data lines in a time-division manner. In these driving methods, one driver output is connected to multiple data lines during precharge and to a single data line during pixel writing.

[0005] In capacitive driving, such as that described in Patent Document 1, data voltages are supplied to pixels through charge redistribution, and when charge is conserved, an appropriate data voltage is written to the pixel. Charge conservation is considered to be achieved when there is no charge supply or discharge from the driver output other than from the capacitive driving. However, in demultiplexing driving, multiple data lines are connected sequentially to the driver output, and each data line maintains a precharge voltage. As a result, charge is not completely conserved, and this charge error may result in an error between the data voltage written to the pixel and the target voltage. [Means for solving the problem]

[0006] One aspect of the present disclosure relates to a driver for driving an electro-optical panel including a signal supply line, a plurality of data lines, and a plurality of switches provided between the signal supply line and the plurality of data lines, the driver including: a capacitor drive circuit that outputs first to n-th capacitor drive voltages (n is a natural number greater than or equal to 2) corresponding to capacitive drive data to first to n-th capacitor drive nodes; a capacitor circuit having first to n-th capacitors provided between the first to n-th capacitor drive nodes and an output terminal; and a control circuit that, when switching from a first period in which a first switch between the signal supply line and a first data line is on and first gradation data is used to a second period in which a second switch between the signal supply line and a second data line is on and second gradation data is used, calculates correction data based on the first gradation data to correct a voltage error with respect to a target voltage corresponding to the second gradation data, the voltage error being caused by switching from the first data line to the second data line, and outputs the capacitive drive data for the first period based on the correction data.

[0007] Another aspect of the present disclosure relates to an electro-optical device including the driver and the electro-optical panel.

[0008] Yet another aspect of the present disclosure relates to an electronic device including the driver described above. [Brief explanation of the drawings]

[0009] [Figure 1] 1 shows an example of the configuration of an electro-optical device. [Figure 2] An example of pixel configuration. [Figure 3] Detailed driver configuration example. [Figure 4] 10 shows an example of detailed configurations of a capacitor circuit, a capacitor driving circuit, and a variable capacitance circuit. [Figure 5] FIG. 2 is a diagram illustrating capacitances related to capacitive driving. [Figure 6] 1A and 1B are diagrams showing a configuration example of a driver circuit and a connection relationship between the driver circuit and a capacitor; [Figure 7] 10A and 10B are diagrams for explaining voltage errors that occur in demultiplex driving using capacitive driving. [Figure 8] 10A and 10B are diagrams for explaining voltage errors that occur in demultiplex driving using capacitive driving. [Figure 9] 5A and 5B are diagrams illustrating a capacitive driving method according to the present embodiment. [Figure 10] 5A and 5B are diagrams illustrating a capacitive driving method according to the present embodiment. [Figure 11] 10A and 10B are diagrams for explaining a method for correcting an error in the data voltage amplitude according to the operating state. [Figure 12] 10 is a specific example of capacitance drive amplitude when the capacitance value of a variable capacitance circuit does not change regardless of the operating state. [Figure 13] 10 shows a specific example of capacitance drive amplitude when the capacitance value of a variable capacitance circuit is changed according to the operating state. [Figure 14] An example of the configuration of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0010] Preferred embodiments of the present disclosure will be described in detail below. Note that the embodiments described below do not unduly limit the scope of the claims, and not all of the configurations described in the embodiments are necessarily essential components.

[0011] 1. Electro-optical devices 1 shows an example of the configuration of an electro-optical device. The electro-optical device 400 includes a driver 100 and an electro-optical panel 200. In the following, an electro-optical device 400 using a demultiplexing drive system will be described as an example, but the present invention is not limited to this. For example, the electro-optical device 400 may use a phase expansion drive system. In the following, an example in which the number of demultiplexes is 8 will be described, but the number of demultiplexes may be p, where p is an integer of 2 or greater.

[0012] The driver 100 includes a control circuit 40, output circuits DD1 to DDk, output terminals TQ1 to TQk, and control signal output terminals SQ1 to SQ8, where k is an integer equal to or greater than 2. The driver 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate.

[0013] The electro-optical panel 200 includes input terminals TI1 to TIk, signal supply lines SL1 to SLk, demultiplexers DM1 to DMk, data lines DL11 to DL18, DL21 to DL28, ..., DLk1 to DLk8, and control signal input terminals SI1 to SI8. The electro-optical panel 200 is an active matrix liquid crystal display panel, an EL display panel using self-luminous elements, or the like. EL is an abbreviation for Electro-Luminescence.

[0014] The control circuit 40 outputs corresponding grayscale data to the output circuit DD1. The output circuit DD1 converts the grayscale data into a data voltage and outputs the data voltage to the output terminal TQ1. The output terminal TQ1 is connected to the input terminal TI1, and the input terminal TI1 is connected to the signal supply line SL1. The same applies to the output circuits DD2 to DDk, the output terminals TQ2 to TQk, the input terminals TI2 to TIk, and the signal supply lines SL2 to SLk.

[0015] The demultiplexer DM1 includes switches SW11 to SW18. Each switch is, for example, a TFT. TFT stands for Thin Film Transistor. One end of the switch SW11 is connected to a signal supply line SL1, and the other end is connected to a data line DL11. The switch SW11 is controlled to be turned on or off by a control signal S1. Similarly, one end of the switches SW12 to SW18 is connected to the signal supply line SL1, and the other end is connected to data lines DL12 to DL18. The switches SW12 to SW18 are controlled to be turned on or off by control signals S2 to S8. The same applies to the demultiplexers DM2 to DMk, the switches SW21 to SW28, ..., SWk1 to SWk8, and the data lines DL21 to DL28, ..., DLk1 to DLk8. The number of switches and the number of data lines in each demultiplexer may be p, which is the same as the number of demultiplexers.

[0016] Although not shown in FIG. 1, the electro-optical panel 200 has a plurality of pixels arranged in a matrix. FIG. 2 shows an example of a pixel configuration. A pixel 1 includes a pixel transistor 2, a pixel electrode 3, and a storage capacitor 4. The pixel transistor 2 is, for example, a TFT. The source of the pixel transistor 2 is connected to a data line DLx, and the gate is connected to a scan line GLy. DLx is one of the data lines shown in FIG. 1. GLy is one of the multiple scan lines provided in the electro-optical panel 200. The pixel electrode 3 has two electrodes facing each other. In a liquid crystal display panel, the two electrodes face each other across the liquid crystal. One of the electrodes of the pixel electrode 3 and the storage capacitor 4 is connected to the drain of the pixel transistor 2, and the other is connected to a node of a common voltage VCOM. The scan line is selected by a scan line drive circuit (not shown). The scan line drive circuit may be included in the driver 100 or may be provided externally to the driver 100.

[0017] Demultiplex driving will be explained using output circuit DD1 as an example. During one horizontal scanning period, switches SW11, SW12, ..., SW18 are sequentially turned on. When switch SW11 is on, output circuit DD1 writes data voltages to pixels connected to data line DL11. Similarly, when switches SW12, ..., SW18 are on, output circuit DD1 writes data voltages to pixels connected to data lines DL12, ..., DL1k. Note that rotation may be performed in demultiplex driving, and the order in which switches SW11, SW12, ..., SW18 are turned on may be arbitrary. A data voltage is a voltage written to one pixel at a time. Eight pixels are driven in a time-series manner by demultiplex driving, and the data voltages for each pixel are output to a signal supply line as a time-series signal. This signal is referred to as a data signal. In addition to pixel driving, precharging and other operations are also performed during the horizontal scanning period, which will be described later.

[0018] 2. Detailed driver configuration example Fig. 3 shows a detailed configuration example of a driver. Fig. 3 shows an output circuit DDj, which is any one of the output circuits DD1 to DDk, and a control circuit 40. j is an integer between 1 and k. The output circuit DDj includes a capacitor circuit 10, a capacitor driving circuit 20, and a variable capacitance circuit 30. The control circuit 40 includes a processing circuit 42, an interface circuit 44, and a register circuit 48.

[0019] The interface circuit 44 performs interface processing between the driver 100 and the display controller 300 that controls the driver 100. The interface circuit 44 outputs the grayscale data GD[9:0] received from the display controller 300 to the processing circuit 42. The number of bits of the received grayscale data may be arbitrary. The interface circuit 44 is, for example, an image interface circuit of the LVDS system, parallel RGB system, or display port system. LVDS is an abbreviation for Low Voltage Differential Signaling.

[0020] The processing circuit 42 outputs capacitive driving data DTH[10:0] to the capacitor driving circuit 20 based on the gradation data GD[9:0]. The capacitor driving circuit 20 drives the capacitor circuit 10 based on the capacitive driving data DTH[10:0]. The capacitor circuit 10 and the variable capacitance circuit 30 are connected to an output node NVQ, which is connected to the output terminal TQj. When the capacitor circuit 10 is driven, charge is injected from the capacitor circuit 10 to the output node NVQ, or charge is discharged from the output node NVQ to the capacitor circuit 10. This charge transfer is redistributed to the variable capacitance circuit 30 and the internal capacitance of the electro-optical panel 200, and the output voltage VQ of the output node NVQ becomes a data voltage corresponding to the capacitive driving data DTH[10:0]. The relationship between the gradation data GD[9:0], the capacitive driving data DTH[10:0], and the data voltage will be described later.

[0021] The register circuit 48 stores setting data CSW[4:0] that sets the capacitance value of the variable capacitance circuit 30. For example, the display controller 300 writes the setting data CSW[4:0] to the register circuit 48 via the interface circuit 44. Alternatively, the driver 100 may include a nonvolatile memory (not shown) that stores the setting data CSW[4:0] in advance, and the setting data CSW[4:0] may be loaded from the nonvolatile memory to the register circuit 48.

[0022] The processing circuit 42 sets the capacitance value of the variable capacitance circuit 30 by outputting the setting data CSW[4:0] read from the register circuit 48 to the variable capacitance circuit 30. The value of the setting data CSW[4:0] may be constant for all operation states of the driver 100. Alternatively, as will be described later with reference to FIG. 11 and the like, the value of the setting data CSW[4:0] may be set for each operation state of the driver 100. In this case, the processing circuit 42 outputs the setting data CSW[4:0] corresponding to each operation state to the variable capacitance circuit 30 in each operation state, thereby changing the capacitance value of the variable capacitance circuit 30 in each operation state. The operation states include precharge and pixel drive. The operation states may also include postcharge.

[0023] FIG. 4 shows an example of detailed configurations of the capacitor circuit, the capacitor driving circuit, and the variable capacitance circuit.

[0024] The capacitor circuit 10 includes capacitors CD1 to CD11. The capacitor driving circuit 20 includes driving circuits DR1 to DR11. However, the number of capacitors and driving circuits may be n, where n is an integer equal to or greater than 2. Similarly, the number of bits of the capacitive driving data DTH[10:0] may be n.

[0025] One end of the capacitor CDi is connected to the output node NVQ, and the other end is connected to the capacitor drive node NDRi. i is an integer between 1 and 11. The capacitors CD1 to CD11 have binary-weighted capacitance values. Specifically, the capacitance value of the capacitor CDi is 2 (i-1) ×CD1.

[0026] The processing circuit 42 outputs the ith bit DTH[i-1] of the capacitive driving data DTH[10:0] to the input node of the driving circuit DRi. The driving circuit DRi outputs a capacitor driving voltage corresponding to the logic level of the ith bit DTH[i-1] to the capacitor driving node NDRi. That is, when the bit DTH[i-1] is at a first logic level, the driving circuit DRi outputs a first voltage level to the capacitor driving node NDRi, and when the bit DTH[i-1] is at a second logic level, the driving circuit DRi outputs a second voltage level to the capacitor driving node NDRi. For example, the first logic level is "0" and the second logic level is "1," the first voltage level is a low-potential power supply voltage, and the second voltage level is a high-potential power supply voltage. The driving circuit DRi is composed of, for example, a level shifter that shifts the input logic level to the output voltage level of the driving circuit DRi and a buffer circuit that buffers the output of the level shifter.

[0027] When the drive circuits DR1 to DR11 drive the capacitors CD1 to CD11, charge redistribution occurs between the capacitors CD1 to CD11, the variable capacitance circuit 30, and the capacitance on the electro-optical panel side, and as a result, a data voltage is written to the pixel.

[0028] The variable capacitance circuit 30 includes adjustment switches SWA1 to SWA5 and adjustment capacitors CA1 to CA5, where the number of switches and adjustment capacitors is m, where m is an integer of 2 or greater.

[0029] One end of the adjustment switches SWAs is connected to the output node NVQ, and the other end is connected to one end of the adjustment capacitor CAs. The other end of the adjustment capacitor CAs is connected to the low-potential side power supply. s is an integer between 1 and 5. The adjustment switches SWA1 to SWA5 are, for example, P-type MOS transistors, N-type MOS transistors, or transfer gates. The adjustment capacitors CA1 to CA5 have binary-weighted capacitance values. Specifically, the capacitance value of the adjustment capacitor CAs is 2 (s-1) ×CA1.

[0030] The adjustment switches SWAs are controlled to be on or off by the s-th bit CSW[s-1] of CSW[4:0]. When the adjustment switches SWAs are on, the adjustment capacitor CAs is connected to the output node NVQ, and the capacitance value of the adjustment capacitor CAs is added to the capacitance value of the variable capacitance circuit 30. That is, the capacitance value of the variable capacitance circuit 30 is set according to the on / off states of the adjustment switches SWA1 to SWA5.

[0031] The output circuit DDj may further include a gradation voltage generation circuit and an amplifier circuit. The gradation voltage generation circuit performs D / A conversion on the capacitive drive data DTH[10:0] and outputs a gradation voltage corresponding to the capacitive drive data DTH[10:0]. The gradation voltage generation circuit includes, for example, ladder resistors that generate voltages corresponding to each gradation value, and a selection circuit that selects from those voltages a voltage corresponding to the capacitive drive data DTH[10:0]. The amplifier circuit amplifies or buffers the gradation voltage output by the gradation voltage generation circuit and outputs it to the output node NVQ. The amplifier circuit is, for example, a voltage follower circuit. The voltage output by the amplifier circuit and the voltage output by capacitive drive are basically the same.

[0032] Alternatively, the output circuit DDj may include a gradation voltage generation circuit but not an amplifier circuit. The gradation voltage generation circuit performs D / A conversion on the capacitive drive data DTH[10:0] and outputs a gradation voltage corresponding to the capacitive drive data DTH[10:0] to the output node NVQ.

[0033] Alternatively, the driver 100 may include a precharge terminal to which a precharge voltage is applied from outside. The output circuit DDj may include a precharge switch connected between the precharge terminal and the output node NVQ, and the precharge switch may be turned on during the precharge period. The precharge terminal and the precharge switch are applicable to any of the following cases: when the output circuit DDj does not include a gradation voltage generation circuit and an amplifier circuit; when it includes a gradation voltage generation circuit and an amplifier circuit; and when it includes a gradation voltage generation circuit but does not include an amplifier circuit.

[0034] 3. Method for correcting data voltage errors caused by charge errors 5 is a diagram for explaining capacitances involved in capacitive driving, in which the capacitor driving circuit 20 is shown in a simplified form.

[0035] If the total capacitance of the capacitors CD1 to CD11 in the capacitor circuit 10 is CD, the capacitance of the capacitor CDi is CD / 2 (12-i) If the total capacitance of the adjustment capacitors CA1 to CA5 in the variable capacitance circuit 30 is CAall, the capacitance value of the adjustment capacitor CAs is CAall / 2 (6-s) The capacitance value CA of the variable capacitance circuit 30 is obtained by adding the capacitance values of the adjustment capacitors connected to the output node NVQ by the adjustment switches SWA1 to SWA5.

[0036] The capacitance when the electro-optical panel 200 is viewed from the output terminal TQj is referred to as the electro-optical panel-side capacitance CLCD. The capacitance value of the signal supply line SLj is CP, and the capacitance value of each of the data lines DLj1 to DLj8 is CL. These are parasitic capacitances between the wiring and the substrate, etc. Of the switches SWj1 to SWj8 of the demultiplexer, the number of switches that are on is α. In this case, the electro-optical panel-side capacitance is CLCD = CP + α × CL.

[0037] Figure 6 shows an example of the configuration of a driver circuit and the connection relationship between the driver circuit and the capacitor. Here, the voltage of the low-potential power supply is the ground voltage, and the voltage of the high-potential power supply is VDH. The driver circuit DRi may further include a level shifter, etc., but only the final-stage buffer portion is shown here.

[0038] The drive circuit DRi includes a P-type MOS transistor TPD and an N-type MOS transistor TND connected in an inverter configuration. The bit DTH[i-1] is input to the gates of these transistors. A capacitor CDi and a capacitance CLDC+CA are connected in series between the output of the drive circuit DRi and the ground voltage node. The capacitance CLDC+CA is the capacitance obtained by connecting the electro-optical panel-side capacitance CLCD and the variable capacitance circuit 30 in parallel.

[0039] Before describing the method of this embodiment, a voltage error that occurs in demultiplex driving using capacitive driving will be described with reference to FIGS.

[0040] 7, the operating states of the driver 100 during a horizontal scanning period are precharge and pixel drive in that order. The period during the horizontal scanning period during which precharge is performed is called the precharge period. The period during the horizontal scanning period during which pixel drive is performed is called the pixel drive period.

[0041] During the precharge period, the control circuit 40 outputs control signals S1 to S8 indicating ON, which turns on all of the switches SWj1 to SWj8 of the demultiplexer DMj, and the precharge voltage is applied to all eight data lines DLj1 to DLj8.

[0042] During the pixel driving period, the following control is performed. The control circuit 40 outputs a control signal S1 indicating ON and outputs control signals S2 to S7 indicating OFF. As a result, the switch SWj1 of the demultiplexer DMj turns ON and the switches SWj2 to SWj8 turn OFF, a data voltage due to capacitive driving is applied to the data line DLj1, and the data voltage is written to the pixels connected to the data line DLj1. Similarly, the control circuit 40 sequentially outputs control signals S2, ..., S8 indicating ON. A data voltage is applied to each of the data lines DLj2, DLj3, ..., DLj8, and the data voltage is written to the pixels connected to that data line.

[0043] 8 shows the correspondence between the grayscale data GD[9:0], the capacitive driving data DTH[10:0], and the data voltage. However, the relationship between DTH[10:0] and the data voltage is ideal, and the capacitance error described below is not taken into consideration here.

[0044] For GD[9:0]=000h, 001h, 002h,..., 33Fh, the control circuit 40 outputs DTH[10:0]=400h, 401h, 402h,..., 7FFh in positive polarity drive, and DTH[10:0]=3FFh, 3FEh, 3FDh,..., 000h in negative polarity drive. The "h" at the end of the value indicates that the value is in hexadecimal. The data voltage output by capacitive drive has a linear characteristic with DTH[10:0], ranging from 7.5V to 12.5V with a 5V amplitude in positive polarity drive, and from 7.5V to 2.5V with a 5V amplitude in negative polarity drive.

[0045] FIG. 7 shows an example in which the gradation data GD[9:0] is 000h during precharge and 3FFh during pixel drive. In this example, the gradation data GD[9:0] during pixel drive is all 3FFh. However, the control circuit 40 always outputs capacitive drive data DTH[10:0]=7FFh for positive drive and always outputs capacitive drive data DTH[10:0]=000h for negative drive. That is, when converting the gradation data GD[9:0] to capacitive drive data DTH[10:0], the control circuit 40 does not perform correction, but instead uniquely associates the gradation data GD[9:0] with the capacitive drive data DTH[10:0]. ΔGD indicates the amount of change in the gradation data GD[9:0], i.e., the value obtained by subtracting the previous GD[9:0] from the current GD[9:0]. ΔDTH indicates the amount of change in the capacitive driving data DTH[10:0], that is, the value obtained by subtracting the previous DTH[10:0] from the current DTH[10:0].

[0046] In Fig. 7, the target voltage for positive drive is denoted as VTP, and the target voltage for negative drive is denoted as VTN. Referring to Fig. 8, for the gradation data GD[9:0]=3FFh, the target voltage for positive drive is VTP=12.5V, and the target voltage for negative drive is VTN=2.5V. However, as will be explained below, when the gradation data GD[9:0] and the capacitive drive data DTH[10:0] are uniquely associated, a charge error occurs in the capacitive drive, and this charge error causes an error in the data voltage.

[0047] Specifically, when the control signals S1, S2, ..., S8 are ON in pixel driving, the data voltages output by capacitive driving are VS1, VS2, ..., VS8. During the precharge period, the capacitive driving output and the data lines DLj1 to DLj8 are all at a precharge voltage VPR = 7.5V. Therefore, when the control signal S1 is ON in pixel driving and the data line DLj1 is connected, there is no potential difference between the capacitive driving output and the data line DLj1, and charge is preserved. Therefore, there is no charge error in capacitive driving, and the data voltage VS1 becomes the target voltage VTP = 12.5V. Next, when the control signal S2 is ON and the data line DLj2 is connected, the capacitive driving output is VS1 = 12.5V, while the data line DLj2 is at a precharge voltage VPR = 7.5V. Therefore, charge redistribution occurs by the potential difference, and charge is not preserved. Therefore, there is a charge error in capacitive driving, and the data voltage VS2 becomes a voltage VS2 lower than the target voltage VTP = 12.5V. The voltage error between voltage VS2 and voltage VS1 is defined as VC2. Hereinafter, the voltage errors between voltage VS3 and voltage VS2, voltage VS4 and voltage VS3, ..., voltage VS8 and voltage VS7 are defined as VC3, VC4, ..., VC8.

[0048] 5, the data voltage VSq is expressed by the following formula (1), and the voltage error VCq is expressed by the following formula (2), where q is an integer between 2 and 8. VSq=VS(q-1)+VCq (1) VCq=CL / (CD+CA+CP+CL)×(VPR-VS(q-1))...(2)

[0049] As described above, when ΔGD=000h, the data voltage should not change, but voltage errors VC2, VC3, ..., VC8 occur due to switching of data lines in demultiplex driving. This causes the problem that the data voltage becomes a different voltage from the target voltage VTP=12.5 for the grayscale data GD[9:0]. Note that while positive polarity driving has been used as an example here, the same applies to negative polarity driving.

[0050] The capacitive driving method in this embodiment will be described with reference to Figures 9 and 10. In Figure 9, the operations of the control signals S1 to S8 and the switches SWj1 to SWj8 in each operating state are the same as in Figure 7.

[0051] Fig. 10 shows the correspondence between the grayscale data GD[9:0], the capacitive driving data DTH[10:0], and the data voltage output by capacitive driving. However, Fig. 10 shows the correspondence when there is no capacitance error, that is, when the capacitive driving data DTH[10:0] is not corrected.

[0052] For GD[9:0]=000h, 001h, 002h,..., 33Fh, the control circuit 40 outputs DTH[10:0]=000h, 001h, 002h,..., 3FFh in positive drive, and outputs DTH[10:0]=5FFh, 5FEh, 5FDh,..., 200h in negative drive. The data voltage output by capacitive drive has a linear characteristic with DTH[10:0], ranging from 7.5V to 12.5V with a 5V amplitude in positive drive, and from 7.5V to 2.5V with a 5V amplitude in negative drive.

[0053] FIG. 9 shows an example in which the grayscale data GD[9:0] is 000h during precharge for positive polarity drive, 200h during precharge for negative polarity drive, and changes in the order of 3FFh, 3FFh, 3FFh, 000h, 200h, 200h, 300h, and 3FFh during pixel drive for positive polarity drive and negative polarity drive. In this embodiment, the control circuit 40 performs correction according to charge error when converting the grayscale data GD[9:0] to capacitive drive data DTH[10:0]. Therefore, even if the grayscale data GD[9:0] is the same during pixel drive, the capacitive drive data DTH[10:0] is not necessarily the same. In FIG. 7 described above, if GD[9:0] is the same, DTH[10:0] is the same, so when ΔGD=0, ΔDTH=0. However, in FIG. 9 of this embodiment, even if ΔGD=0, ΔDTH=0 does not necessarily mean ΔGD=0.

[0054] In this embodiment, the control circuit 40 calculates the capacitive driving data DTH[10:0] using the following formula (3). The "±" in the second term on the right side means "+" for positive driving and "-" for negative driving. q is an integer between 2 and 8. DTHq is the capacitive driving data DTH[10:0] for the qth pixel driving. ΔGD is GDq-GD(q-1) when the gradation data GD[9:0] for the qth pixel driving is GDq. DCq is the correction data for the qth pixel driving. The following formula (3) is obtained by replacing the above formula (1) with data. Note that the above formula (1) was based on the assumption that the gradation data GD[9:0] does not change, so the term corresponding to ΔGD is omitted. DTHq=DTH(q-1)±(ΔGD-DCq)...(3)

[0055] 9 is expressed by the following equation (4), and the above equation (3) can be rewritten as the following equation (5). In FIG. 7, ΔDTH=ΔGD, but in FIG. 9 of this embodiment, ΔDTH≠ΔGD due to the correction data DCq. ΔDTH=DTHq-DTH(q-1)=ΔGD-DCq...(4) DTHq = DTH(q-1) ± ΔDTH (5)

[0056] The control circuit 40 calculates the correction data DCq using the following equation (6). DPR is the grayscale data GD[9:0] in precharge. In the example of FIG. 9, DPR=000h in positive polarity drive and DPR=200h in negative polarity drive. The following equation (6) is obtained by substituting the above equation (2) with data. DCq=CL / (CD+CA+CP+CL)×(DPR-GD(q-1))...(6)

[0057] FIG. 9 shows an example where CL / (CD+CA+CP+CL)=1 / 16.8. For example, in pixel driving with q=4, DC4, ΔDTH, and DTH4 have the following values. In positive polarity driving, from equation (6) above, DC4=1 / 16.8×(000h-3FFh)≒-3Dh. From equation (4) above, ΔDTH=-3FFh-(-3Dh)=-3C2h. From equation (5) above, DTH4=479h+(-3C2h)=0B7h. In negative polarity driving, from equation (6) above, DC4=1 / 16.8×(200h-3FFh)≒-1Eh. From equation (4) above, ΔDTH=-3FFh-(-1Eh)=-3E1h. From the above equation (5), DTH4 = 1C4h - (-3E1h) = 5A5h.

[0058] The capacitance ratio, CL / (CD+CA+CP+CL), is determined in advance, for example, by measurement using a product sample or by circuit simulation. For example, a processing device such as a display controller 300 provided outside the driver 100 writes the predetermined capacitance ratio to the register circuit 48 via the interface circuit 44. Alternatively, the driver 100 may include a nonvolatile memory (not shown) that stores the predetermined capacitance ratio, and the capacitance ratio may be loaded from the nonvolatile memory to the register circuit 48. The control circuit 40 reads the capacitance ratio from the register circuit 48 and performs the above-mentioned correction.

[0059] As described above, the control circuit 40 corrects the capacitive driving data DTH[10:0] using the correction data DCq corresponding to the data voltage error VCq due to the charge error described in Fig. 7. As a result, the data voltage error VCq is corrected, and the correct data voltage VSq is output for the input grayscale data GD[9:0].

[0060] Furthermore, if an amplifier circuit is added to the output circuit DDj, charge can be supplied from the amplifier circuit without correcting the capacitive drive data DTH[10:0], thereby eliminating the voltage error VCq in FIG. 7. However, in this embodiment, the voltage error VCq in FIG. 7 can be corrected by data processing alone without providing an amplifier circuit, making it possible to reduce power consumption, heat generation, or circuit area. However, the correction method of the present application does not prevent the addition of an amplifier circuit. Even if an amplifier circuit is provided, the correction of this embodiment reduces the amount of charge that the amplifier circuit must supply, thereby reducing the power consumption, heat generation, or circuit area of the amplifier circuit.

[0061] In the following description, in the pixel driving period of Figure 9, the period during which the control signal S1 is on will be referred to as the first period, and the period during which the control signal S2 is on will be referred to as the second period. This corresponds to the case where q = 2 in the above equation (6). However, the first period may be any period during which any pixel is driven in the pixel driving period, and the second period may be any period during which the pixel following the first period is driven.

[0062] In this embodiment, the driver 100 drives the electro-optical panel 200. The electro-optical panel 200 includes a signal supply line SLj, a plurality of data lines DLj1 to DLj8, and a plurality of switches SWj1 to SWj8 provided between the signal supply line SLj and the plurality of data lines DLj1 to DLj8. The driver 100 includes a capacitor driving circuit 20, a capacitor circuit 10, and a control circuit 40.

[0063] The capacitor driving circuit 20 outputs first to n-th capacitor driving voltages corresponding to the capacitive driving data DTH[n-1:0] to the first to n-th capacitor driving nodes NDR1 to NDRn, where n is an integer equal to or greater than 2. The capacitor circuit 10 has first to n-th capacitors CA1 to CAn provided between the first to n-th capacitor driving nodes NDR1 to NDRn and the output terminal TQj.

[0064] As explained in the above equation (6), when switching from the first period to the second period, the control circuit 40 obtains the correction data DC2 based on the first gradation data GD1. The first period is a period during which the first switch SWj1 between the signal supply line SLj and the first data line DLj1 is on and the first gradation data GD1 is used. The second period is a period during which the second switch SWj2 between the signal supply line SLj and the second data line DLj2 is on and the second gradation data GD2 is used. The correction data DC2 corrects a voltage error VC2 with respect to the target voltage corresponding to the second gradation data GD2, which occurs when the first data line DLj1 is switched to the second data line DLj2. As explained in the above equations (3) to (5), the control circuit 40 outputs the capacitive driving data DTH2 for the second period based on the capacitive driving data DTH1 and the correction data DC2 for the first period.

[0065] According to this embodiment, the voltage error VC2 relative to the target voltage corresponding to the second gradation data GD2 is corrected by the correction data DC2. As a result, the correct data voltage VS2 is output for the second gradation data GD2. Furthermore, as described above, by correcting the error, it is no longer necessary to provide an amplifier circuit in the output circuit DDj. Alternatively, even if an amplifier circuit is provided, the correction of this embodiment reduces the amount of charge that the amplifier circuit must supply, thereby reducing the power consumption, heat generation, or circuit area of the amplifier circuit.

[0066] In addition, in this embodiment, the control circuit 40 may determine the correction data DC2 based on the ratio of the capacitance of the signal supply line SLj, which includes the capacitance CD of the capacitor circuit 10 connected to the signal supply line SLj and the capacitance CL of one data line, to the capacitance CL of one data line.

[0067] Specifically, the driver 100 may include a variable capacitance circuit 30 connected to the output terminal TQj. As described in FIG. 5, the capacitance of the capacitor circuit 10 is CD, the capacitance of the variable capacitance circuit 30 is CA, the capacitance of the signal supply line SLj is CP, and the capacitance of one data line is CL. The gradation data corresponding to the precharge voltage is DPR. The first gradation data is GD1, and the correction data is DC2. As described in equation (6) above, the control circuit 40 may calculate the correction data DC2 by DC2={CL / (CD+CA+CP+CL)}×(DPR-GD1).

[0068] According to this embodiment, when the second data line DLj2 is connected, the second data line DLj2 holds the precharge voltage VPR corresponding to the gradation data DPR, and the signal supply line SLj is at the voltage VS1 corresponding to the previous gradation data GD1. The data voltage error due to this voltage difference is VC2={CL / (CD+CA+CP+CL)}×(VPR-VS1), as explained in the above equation (2). When this is substituted into data, the correction data DC2={CL / (CD+CA+CP+CL)}×(DPR-GD1), as explained in the above equation (6). In this way, by using the capacitance ratio CL / (CD+CA+CP+CL), correction data corresponding to the data voltage error can be obtained.

[0069] Furthermore, in this embodiment, as explained in the above equation (3), the control circuit 40 may obtain the capacitive driving data DTH2 in the second period using the capacitive driving data DTH1 in the first period, the difference ΔGD between the first gradation data GD1 and the second gradation data GD2, and the correction data DC2.

[0070] If correction is not taken into consideration, the difference between the capacitive driving data DTH1 in the first period and the capacitive driving data DTH2 in the second period is equal to the difference ΔGD between the first gradation data GD1 and the second gradation data GD2. That is, the capacitive driving data DTH2 in the second period is calculated from the capacitive driving data DTH1 in the first period and the difference ΔGD between the first gradation data GD1 and the second gradation data GD2. According to this embodiment, by further using the correction data DC2, the capacitive driving data DTH2 in the second period is corrected, and the data voltage error is corrected.

[0071] In this embodiment, in a precharge period before the first period and the second period, the switches SWj1 to SWj8 may be on, and the precharge voltage VPR may be supplied to the signal supply line SLj and the data lines DLj1 to DLj8.

[0072] In this embodiment, the control circuit 40 may output the capacitive driving data DTH[10:0] according to the precharge voltage VPR during the precharge period.

[0073] In this embodiment, the precharge voltage VPRP in the positive polarity driving period may be different from the precharge voltage VPRN in the negative polarity driving period. In this case, the control circuit 40 may output different capacitive driving data DTH[10:0] for the precharge period in the positive polarity driving period and the precharge period in the negative polarity driving period.

[0074] As described above, a data voltage error occurs in capacitive driving due to the data lines being precharged, but according to this embodiment, the data voltage error is corrected by correcting the capacitive driving data using correction data.

[0075] In this embodiment, the number of bits of the capacitive driving data DTH[10:0] may be larger than the number of bits of the first gradation data GD[9:0]=GD1 and the second gradation data GD[9:0]=GD2.

[0076] In this embodiment, the capacitive drive data DTH[10:0] is corrected using correction data, so the range of the capacitive drive data DTH[10:0] is larger than the range of the gradation data GD[9:0]. According to this embodiment, the capacitive drive data DTH[10:0] has a larger number of bits, so the range expansion due to correction can be absorbed. For example, in the example of FIG. 10, if correction is not taken into account, the maximum values of both the gradation data GD[9:0] and the capacitive drive data DTH[10:0] are 3FFh in positive drive. If correction is taken into account as in the example of FIG. 9, the value of the capacitive drive data DTH[10:0] is corrected to a larger value in positive drive, and may exceed 3FFh. Since the upper limit of the capacitive drive data DTH[10:0] is 7FFh, the range expansion due to correction can be absorbed. In negative polarity driving, the value of the capacitive driving data DTH[10:0] may be corrected in either an upward or downward direction, but as shown in Figure 10, the range of the capacitive driving data DTH[10:0] when correction is not taken into account is set to 200h to 5FFh, so there is a margin between the lower limit of 000h and the upper limit of 7FFh, and range expansion in both the upward and downward directions can be accommodated.

[0077] 4. Method for correcting errors in data voltage amplitude according to operating state Figure 11 is a diagram explaining a method for correcting errors in data voltage amplitude according to the operating state. The operating states during a horizontal scanning period are precharge, pixel drive, and postcharge in that order. The period during which postcharge is performed within the horizontal scanning period is called the postcharge period.

[0078] During the precharge period, all eight data lines are connected to the signal supply line SLj. As explained in FIG. 5, the capacitance of the electro-optical panel is CLCD=CP+α×CL, where α is the number of connected data lines. Therefore, during the precharge period, the capacitance of the electro-optical panel is CLCD=CP+8CL.

[0079] During the pixel driving period, one data line is connected to the signal supply line SLj, so the capacitance on the electro-optical panel side is CLCD=CP+CL.

[0080] During the postcharge period, the control circuit 40 outputs control signals S1 to S8 indicating off. As a result, all of the switches SWj1 to SWj8 of the demultiplexer DMj are turned off. Since all eight data lines are not connected to the signal supply line SLj, the capacitance on the electro-optical panel side is CLCD=CP.

[0081] The variable capacitance circuit 30 and the electro-optical panel-side capacitance CLCD are referred to as capacitances other than the capacitor circuit 10. The capacitance value of the variable capacitance circuit 30 is adjusted so that an appropriate data voltage is written to the pixel at least during pixel drive. If the capacitance value of the variable capacitance circuit 30 were constant regardless of the operating state, the electro-optical panel-side capacitance CLCD would change depending on the operating state, and therefore capacitances other than the capacitor circuit 10 would also change. This would cause a change in the distribution ratio between the capacitor circuit 10 and capacitances other than the capacitor circuit 10, making it impossible to generate appropriate voltages during pre-charge and post-charge.

[0082] In this embodiment, the control circuit 40 controls the capacitance value of the variable capacitance circuit 30 so that the capacitances of the circuits other than the capacitor circuit 10 are constant during pre-charge, pixel drive, and post-charge.

[0083] During precharge, the control circuit 40 sets the adjustment switches SWA1 to SWA5 of the variable capacitance circuit 30 to connection state 1. Connection state 1 is a state in which the variable capacitance circuit 30 is set to a capacitance value CA(0). The number in parentheses of CA(0) indicates how many data lines the capacitance value corresponds to. CA(0) is a capacitance value corresponding to 0 data lines, for example, 0 pF. However, an offset of CA(0) > 0 pF is also acceptable. The capacitance other than that of the capacitor circuit 10 is CP + 8CL + CA(0).

[0084] The control circuit 40 sets the adjustment switches SWA1 to SWA5 of the variable capacitance circuit 30 to connection state 2 during pixel driving. Connection state 2 is a state in which the variable capacitance circuit 30 is set to a capacitance value CA(7). CA(7) is the capacitance value corresponding to seven data lines, and is equal to CA(0)+7CL. However, CA(7) does not need to be exactly the same as CA(0)+7CL, as long as it is approximately the same. The capacitance other than that of the capacitor circuit 10 is CP+CL+CA(7)≈CP+8CL+CA(0).

[0085] The control circuit 40 sets the adjustment switches SWA1 to SWA5 of the variable capacitance circuit 30 to connection state 3 during post-charge. Connection state 3 is a state in which the variable capacitance circuit 30 is set to a capacitance value CA(8). CA(8) is the capacitance value corresponding to the eight data lines, and is equal to CA(0)+8CL. However, CA(8) does not need to be exactly the same as CA(0)+8CL, as long as it is approximately the same. The capacitance other than that of the capacitor circuit 10 is CP+CA(8)≈CP+8CL+CA(0).

[0086] As described above, the capacitances of the components other than the capacitor circuit 10 are constant at CP+8CL+CA(0) regardless of the operating state.

[0087] 12 shows a specific example of the capacitance driving amplitude when the capacitance value of the variable capacitance circuit is not changed regardless of the operating state. Here, the capacitance driving amplitude for pixel driving is set to 10 V, and this capacitance driving amplitude is obtained when the capacitance value of the variable capacitance circuit 30 is 0 pF.

[0088] If the capacitance value CP of the signal supply line is 10 pF and the capacitance CL of each data line is 5 pF, then the capacitance CLCD on the electro-optical panel side is CP+8CL=50 pF during precharge, CP+CL=15 pF during pixel drive, and CP=10 pF during postcharge.

[0089] If the voltage VDH of the high-potential power supply is 15 V, the capacitive drive amplitude is CD / (CD+CA+CLCD)×15 V. If the capacitive drive amplitude for pixel drive is 10 V, then CD / (CD+15 pF)×15 V=10 V, so CD=30 pF. In other words, the total capacitance CD of the capacitor circuit 10 required to achieve a capacitive drive amplitude of 10 V is 30 pF.

[0090] If the capacitance value CA of the variable capacitance circuit 30 is not changed from 0 pF, the capacitance CA+CLCD other than that of the capacitor circuit 10 is 50 pF during pre-charge, 15 pF during pixel drive, and 10 pF during post-charge. Therefore, the capacitance drive amplitude is 5.63 V during pre-charge, 10 V during pixel drive, and 11.25 V during post-charge.

[0091] In pre-charging to reduce pixel leakage, for example, the lowest voltage of the voltage range is used, 2.5V. However, because the capacitive drive amplitude is only 5.63V, even if 2.5V is output by capacitive drive, it only drops to 4.69V. This reduces the effectiveness of pre-charging and may result in a decrease in image quality. Similarly, in post-charging, there is a risk that the target voltage may not be output.

[0092] If an amplifier circuit is added to the output circuit DDj, the above precharge voltage error can be eliminated by the amplifier circuit, making it possible to output a precharge voltage of 2.5 V. However, to do this, the amplifier circuit needs to charge a capacitance of 50 pF + 30 pF, which requires a large current supply capability and increases the power consumption of the amplifier circuit.

[0093] 13 shows a specific example of the capacitance drive amplitude when the capacitance value of the variable capacitance circuit is changed according to the operating state. The capacitance of the signal supply line CP=10 pF, the capacitance of the data line CL=5 pF, the high-potential power supply voltage VDH=15 V, and the capacitance drive amplitude for pixel driving 10 V are the same as those in FIG.

[0094] The capacitance value of the variable capacitance circuit 30 during pre-charge is set to CA(0) = 0 pF. At this time, the capacitance CA+CLCD other than that of the capacitor circuit 10 is 50 pF. The capacitance value CA of the variable capacitance circuit 30 is controlled so that the capacitance CA+CLCD is constant, so that it is 50 pF-15 pF=35 pF during pixel drive and 50 pF-40 pF=10 pF during post-charge.

[0095] As described above, the capacitive drive amplitude is CD / (CD+CA+CLCD)×15V. The total capacitance of the capacitor circuit 10 to achieve a capacitive drive amplitude of 10V is CD / (CD+50pF)×15V=10V, so CD=100pF. Since CA+CLCD is constant regardless of the operating state, the capacitive drive amplitude is constant at 10V during precharge, pixel drive, and postcharge.

[0096] Furthermore, when the amplifier circuit described above is added, the precharge voltage error is either zero or very small. The amplifier circuit needs to charge a capacitance of 50 pF + 100 pF, but because the voltage error in driving the capacitance is small, only a small current supply capacity is required, allowing the power consumption of the amplifier circuit to be reduced.

[0097] In this embodiment, the driver 100 includes a variable capacitance circuit 30 connected to the output terminal TQj. The control circuit 40 sets the variable capacitance circuit 30 to a first capacitance value CA(7) during a driving period of the pixels of the electro-optical panel 200, and sets the variable capacitance circuit 30 to a second capacitance value CA(0) smaller than the first capacitance value CA(7) during a pre-charge period of the electro-optical panel 200.

[0098] 11 and other drawings, the electro-optical panel capacitance CLCD during the precharge period is larger than the electro-optical panel capacitance CLCD during the pixel drive period. According to this embodiment, the capacitance CA+CLCD other than that of the capacitor circuit 10 during the pixel drive period can be made closer to the capacitance CA+CLCD other than that of the capacitor circuit 10 during the precharge period than when the capacitance value of the variable capacitance circuit 30 is fixed. This allows an appropriate capacitance drive amplitude to be obtained even during precharge, and a highly accurate precharge voltage to be applied to the data line.

[0099] In this embodiment, the capacitance value of the variable capacitance circuit 30 is CA, and the capacitance value of the electro-optical panel-side capacitance is CLCD. In this case, the control circuit 40 may set the first capacitance value CA(7) and the second capacitance value CA(0) so that CA+CLCD during the precharge period approaches CA+CLCD during the pixel drive period.

[0100] By setting the capacitance value of the variable capacitance circuit 30 in this way, the capacitance CA+CLCD other than that of the capacitor circuit 10 during the precharge period can be made closer to the capacitance CA+CLCD other than that of the capacitor circuit 10 during the pixel drive period.

[0101] 5.Electronic equipment 14 shows an example of the configuration of an electronic device including a driver according to this embodiment. Various electronic devices incorporating a display device can be envisioned as examples of the electronic device according to this embodiment. For example, the electronic device may be a projector, a television device, an information processing device, a portable information terminal, a car navigation system, or a portable game terminal.

[0102] The electronic device 500 includes an electro-optical device 400, a display controller 300, a processing unit 310, a storage unit 320, a user interface unit 330, and a data interface unit 340. The electro-optical device 400 includes a driver 100 and an electro-optical panel 200.

[0103] The user interface unit 330 is an interface unit that accepts various operations from the user. For example, it may be configured with buttons, a mouse, a keyboard, or a touch panel attached to the electro-optical panel 200. The data interface unit 340 is an interface unit that inputs and outputs image data or control data. For example, it may be a wired communication interface such as a USB, or a wireless communication interface such as a wireless LAN. The memory unit 320 stores image data input from the data interface unit 340. Alternatively, the memory unit 320 functions as a working memory for the processing device 310 or the display controller 300. The processing device 310 performs control processing of each component of the electronic device and various data processing. The processing device 310 is, for example, a processor such as a CPU or a microcomputer. The display controller 300 performs control processing for the driver 100. For example, the display controller 300 converts image data transferred from the data interface unit 340 or the memory unit 320 into a format acceptable to the driver 100 and outputs the converted image data to the driver 100. The driver 100 drives the electro-optical panel 200 based on image data transferred from the display controller 300 .

[0104] Although the present embodiment has been described in detail above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be within the scope of the present disclosure. For example, a term described at least once in the specification or drawings with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, the configurations and operations of the control circuit, output circuit, driver, electro-optical panel, electro-optical device, and electronic device are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0105] 1...pixel, 2...pixel transistor, 3...pixel electrode, 4...storage capacitor, 10...capacitor circuit, 20...capacitor drive circuit, 30...variable capacitance circuit, 40...control circuit, 42...processing circuit, 44...interface circuit, 48...register circuit, 100...driver, 200...electro-optical panel, 300...display controller, 310...processing device, 320...memory unit, 330...user interface unit, 340...data interface unit, 400...electrical Optical device, 500...electronic device, CA...variable capacitance circuit capacitance, CD...capacitor circuit capacitance, CL...data line capacitance, CLCD...electro-optical panel side capacitance, CP...signal supply line capacitance, DC...correction data, DLj1 to DLj8...data lines, DTH[10:0]...capacitive drive data, GD[9:0]...grayscale data, SLj...signal supply line, SWj1 to SWj8...switches, VC1 to VC8...error voltage, VPR, VPRP, VPRN...precharge voltage, VS1 to VS8...data voltage

Claims

1. A driver for driving an electro-optical panel including a signal supply line, a plurality of data lines, and a plurality of switches provided between the signal supply line and the plurality of data lines, a capacitor driving circuit that outputs first to n-th capacitor driving voltages (n is a natural number of 2 or more) corresponding to the capacitive driving data to first to n-th capacitor driving nodes; a capacitor circuit having first to n-th capacitors provided between the first to n-th capacitor driving nodes and an output terminal; a control circuit that, when switching from a first period in which a first switch between the signal supply line and a first data line is on and first gradation data is used to a second period in which a second switch between the signal supply line and a second data line is on and second gradation data is used, calculates correction data based on the first gradation data to correct a voltage error with respect to a target voltage corresponding to the second gradation data, which is caused by switching from the first data line to the second data line, and outputs the capacitive driving data for the second period based on the capacitive driving data for the first period and the correction data; A driver comprising:

2. 2. The driver according to claim 1, The control circuit A driver characterized in that the correction data is obtained based on a ratio between the capacitance of the signal supply line, which includes the capacitance of the capacitor circuit connected to the signal supply line and the capacitance of one data line, and the capacitance of the one data line.

3. 3. The driver according to claim 2, a variable capacitance circuit connected to the output terminal; When the capacitance of the capacitor circuit is CD, the capacitance of the variable capacitance circuit is CA, the capacitance of the signal supply line is CP, the capacitance of the one data line is CL, the gradation data corresponding to the precharge voltage is DPR, the first gradation data is GD1, and the correction data is DC2, The control circuit DC2={CL / (CD+CA+CP+CL)}×(DPR-GD1) A driver characterized in that the correction data is obtained by:

4. 2. The driver according to claim 1, The control circuit a driver that calculates the capacitive driving data in the second period using the capacitive driving data in the first period, a difference between the first gradation data and the second gradation data, and the correction data.

5. 2. The driver according to claim 1, A driver characterized in that, during a precharge period preceding the first period and the second period, the plurality of switches are on and a precharge voltage is supplied to the signal supply line and the plurality of data lines.

6. 6. The driver according to claim 5, The control circuit A driver that outputs the capacitive driving data according to the precharge voltage during the precharge period.

7. 6. The driver according to claim 5, When the precharge voltage in the positive polarity driving period is different from the precharge voltage in the negative polarity driving period, The control circuit A driver that outputs different capacitive driving data during the precharge period in the positive driving period and during the precharge period in the negative driving period.

8. 2. The driver according to claim 1, The driver, wherein the number of bits of the capacitive driving data is greater than the number of bits of the first grayscale data and the second grayscale data.

9. 2. The driver according to claim 1, a variable capacitance circuit connected to the output terminal; The control circuit A driver characterized in that the variable capacitance circuit is set to a first capacitance value during a driving period of a pixel of an electro-optical panel, and the variable capacitance circuit is set to a second capacitance value smaller than the first capacitance value during a precharge period of the electro-optical panel.

10. 10. The driver according to claim 9, When the capacitance value of the variable capacitance circuit is CA and the capacitance value of the electro-optical panel side capacitance is CLCD, The control circuit a driver, wherein the first capacitance value and the second capacitance value are set so that CA+CLCD during the precharge period approaches CA+CLCD during a drive period of the pixel;

11. A driver according to any one of claims 1 to 10; the electro-optical panel; An electro-optical device comprising:

12. 11. An electronic device comprising a driver according to any one of claims 1 to 10.

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