Liquid crystal display device

Abstract

To provide a liquid crystal display device capable of suppressing an increase in size.SOLUTION: A liquid crystal display device comprises a second IC that constitutes part of a liquid crystal panel. A first IC comprises a first frame buffer having a memory capacity that can store image data corresponding to an image in a plurality of colors to be displayed on the liquid crystal panel. The second IC comprises pixel electrodes and a second frame buffer having a memory capacity that can store image data corresponding to a partial color image among the images in the plurality of colors to be displayed on the liquid crystal panel. The first IC and the second IC are electrically connected to each other. Image data input from outside to the first IC is written into the first frame buffer, and image data in each color written in the first frame buffer is read out from the first frame buffer in a predetermined order and written into the second frame buffer. A color image is displayed on the liquid crystal panel on the basis of the image data written into the second frame buffer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a liquid crystal display device. [Background technology]

[0002] FIG. 5 is a longitudinal cross-sectional view showing the basic structure of a conventional LCOS display panel. LCOS stands for Liquid Crystal on Silicon, and an LCOS display panel refers to a display panel with an LCOS structure. As shown in FIG. 5, an LCOS display panel is configured by filling a liquid crystal 502, such as a ferroelectric liquid crystal, between a backplane IC 501 made of single-crystal silicon and provided with pixel electrodes 504 and an opposing glass 503 provided with transparent electrodes 505. The transmittance of the liquid crystal 502 is controlled by controlling the voltage applied between the pixel electrodes 504 and the transparent electrode 505. The backplane IC 501 and the opposing glass 503 are bonded together with a roughly frame-shaped peripheral seal containing multiple spacers, and the liquid crystal 502 is sealed in the area surrounded by this peripheral seal. Wire pads are provided on the surface of the backplane IC 501 located outside the perimeter of the peripheral seal, and the backplane IC 501 is electrically connected to an external circuit via these wire pads.

[0003] LCOS display panels use single-crystal silicon as the control semiconductor, which allows for extremely high-speed control and the formation of finer pixels than the TFTs (Thin Film Transistors) used in large LCD panels, and are therefore widely used as display panels for digital still camera viewfinders, head-mounted displays, and other devices.

[0004] In particular, LCOS display panels using ferroelectric liquid crystal as the liquid crystal 502 have been attracting attention in recent years due to their features such as high speed response, less crosstalk between pixels, and the ability to form finer pixels.

[0005] There are two methods for displaying color gradations in an LCOS display panel: a voltage control method and a pulse width control method.

[0006] The voltage control method is a method of producing gradation display by controlling the transmittance of the liquid crystal 502 according to the strength of the voltage applied to the pixel electrode 504. The voltage control method has the advantage that it can produce gradation display of color with a relatively simple circuit configuration.

[0007] On the other hand, the pulse width control method controls the average transmittance by adjusting the length of time the voltage is applied (pulse width), thereby achieving gray scale display. Although the circuit configuration of the pulse width control method is more complex than that of the voltage control method, the gray scale display is less susceptible to the influence of external factors such as temperature, and it is possible to accurately display gray scales of color with higher resolution.

[0008] The above-mentioned ferroelectric liquid crystal is not capable of displaying halftone gradations by voltage control, but it is possible to display halftone gradations by using pulse width control.

[0009] FIG. 6 is a diagram schematically illustrating the circuit configuration of a backplane IC used in a conventional LCOS display panel. As shown in FIG. 6, the backplane IC 501 used in a conventional LCOS display panel mainly includes an external interface circuit 601, a video data conversion circuit 602, a frame buffer 603, and a pulse width control circuit 604. Video data input from the outside through the external interface circuit 601 is typically an RGB data sequence for each pixel (R1, G1, B1, R2, G2, B2, . . .). The video data conversion circuit 602 converts this data into a data sequence grouped by color (R1, R2, . . ., G1, G2, . . ., B1, B2, . . .) and stores it in the frame buffer 603. The frame buffer 603 and pulse width control circuit 604 are provided above and below the display pixel 605, respectively, and the ones provided on the upper and lower sides are identical. Each of the two frame buffers 603 has a bank (memory area) for storing data for each of the RGB colors, i.e., the two frame buffers 603 as a whole have two banks (3 colors x 2 banks) for storing data for each of the RGB colors, and while new data is being written to one bank, data already stored in the other bank is read out and sent to the pulse width control circuit 604. Based on the data sent to the pulse width control circuit 604 in this way, the pulse width control circuit 604 applies a voltage of an appropriate pulse width to the display pixels 605.

[0010] In FIG. 6, two sets of frame buffer 603 and pulse width control circuit 604 are provided, one above the other, as a device for shortening the wiring length from pulse width control circuit 604 to display pixel 605, and this is not an essential requirement.

[0011] An LCOS display panel having the above-described configuration is described in, for example, Patent Documents 1 and 2. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] Patent No. 4846571 [Patent Document 2] Patent No. 6824676 Summary of the Invention [Problem to be solved by the invention]

[0013] The frame buffer provided in the backplane IC for the pulse width control method requires a memory capacity expressed by the following formula: Memory capacity = number of pixels x number of colors x color depth x number of banks

[0014] Here, the number of pixels refers to the total number of pixels in the LCOS display panel. For example, a panel with 720 vertical pixels and 1280 horizontal pixels, commonly referred to as HD standard, would have a total of 921,600 pixels. The number of colors refers to the number of primary colors, usually the three colors of RGB. The color depth refers to the color resolution, usually 8 bits, but for applications requiring even greater clarity, 10 bits or even more may be used. There are usually two banks, and while an image is being displayed using image data stored in one memory bank, the next frame's image data is written to the other memory bank, allowing for continuous image display.

[0015] From the above, for example, in the case of an LCOS display panel that conforms to the HD standard and has a color depth of 8 bits, it is necessary to mount a frame buffer with a memory capacity of approximately 44 megabits in the backplane IC.

[0016] In recent years, especially in the fields of virtual reality (VR) and augmented reality (AR), there has been a demand for higher resolution LCOS display panels, as well as a growing demand for higher color depths. These demands have led to a steady increase in the required frame buffer capacity, which has resulted in an increase in the area of the backplane IC. One of the attractions of LCOS display panels is their small physical size, so increasing the frame buffer capacity and the resulting increase in product size would significantly diminish their appeal.

[0017] The present invention has been made in view of the above problems, and has an object to provide a liquid crystal display device that can prevent the liquid crystal panel from becoming large. [Means for solving the problem]

[0018] a first IC separated from the liquid crystal panel and a second IC constituting part of the liquid crystal panel, the first IC comprising a first frame buffer having a memory capacity capable of storing all image data corresponding to a plurality of color images to be displayed on the liquid crystal panel; the second IC comprising pixel electrodes and a second frame buffer having a memory capacity capable of storing only image data corresponding to some of the color images to be displayed on the liquid crystal panel; the first IC and the second IC being electrically connected to each other; image data input from outside to the first IC being written into the first frame buffer as image data for each color; the image data for each color written into the first frame buffer being read from the first frame buffer in a predetermined order and written into the second frame buffer; and a color image being displayed on the liquid crystal panel based on the image data written into the second frame buffer. [Effects of the Invention]

[0019] In the liquid crystal display device of the present invention, the capacity of the frame buffer of the backplane IC is reduced compared to conventional backplane ICs, so it is possible to keep the size of the backplane IC small, which means that the liquid crystal panel does not need to be large. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1 is a diagram schematically illustrating a circuit configuration of a liquid crystal display device according to an embodiment of the present invention. [Figure 2] 2 is a diagram schematically illustrating the configuration of a frame buffer and the timing of writing / reading data in an embodiment of the present invention. FIG. [Figure 3] FIG. 10 is a diagram schematically illustrating a circuit configuration of a liquid crystal display device according to another embodiment of the present invention. [Figure 4] FIG. 10 is a diagram illustrating the internal structure of a full-color frame buffer according to another embodiment of the present invention. [Figure 5] FIG. 1 is a vertical cross-sectional view showing the basic structure of a conventional LCOS display panel. [Figure 6] FIG. 1 is a diagram schematically illustrating the circuit configuration of a backplane IC used in a conventional LCOS display panel. DETAILED DESCRIPTION OF THE INVENTION

[0021] Examples of the present invention will be described below. [Example]

[0022] FIG. 1 is a diagram schematically illustrating the circuit configuration of a liquid crystal display device according to an embodiment of the present invention. As shown in FIG. 1, the liquid crystal display device according to the embodiment of the present invention includes two ICs (integrated circuits): a backplane IC 102 that constitutes part of the LCOS display panel, and a control IC 101 that is mounted on a circuit board or the like that is separate from the LCOS display panel. The backplane IC 102 and the control IC 101 are made of, for example, single-crystal silicon. The liquid crystal display device according to the embodiment of the present invention also includes light sources that emit light of each color of RGB, and a light source control circuit that sequentially turns on these light sources in a predetermined order (neither of which is shown). The basic structure of the LCOS display panel is the same as that of a conventional LCOS display panel shown in FIG. 5.

[0023] The control IC 101 includes an external interface circuit 103, a video data conversion circuit 104, a full-color frame buffer 105 that stores video data for all colors, and an inter-chip interface circuit 106. On the other hand, the backplane IC 102 includes the inter-chip interface circuit 106, monochrome frame buffers 108 (one on the upper side and one on the lower side) that store video data for a single color, pulse width control circuits 109 (one on the upper side and one on the lower side), and display pixels 110. The inter-chip interface circuit 106 of the control IC 101 and the inter-chip interface circuit 106 of the backplane IC 102 are connected to each other by an inter-chip cable 107. The control IC 101 and the backplane IC 102 are provided with other circuit configurations necessary for operating the liquid crystal display device, as appropriate.

[0024] Inside control IC 101, external interface circuit 103 is connected to video data conversion circuit 104, video data conversion circuit 104 is connected to full-color frame buffer 105, and full-color frame buffer 105 is connected to inter-chip interface circuit 106. Inside backplane IC 102, inter-chip interface circuit 106 is connected in parallel to upper and lower monochrome frame buffers 108, which are connected to upper pulse width control circuit 109, which is connected to lower pulse width control circuit 109, which are connected to display pixels 110.

[0025] FIG. 2 is a diagram showing the configuration of a frame buffer and the timing of data read / write in an embodiment of the present invention. The flow of video data within a liquid crystal display device will be described below with reference to FIG. 2. Video data input from an external device to control IC 101 is converted into one screen's worth of data for each of RGB colors by data conversion circuit 104, and stored in full-color frame buffer 105. Full-color frame buffer 105 has two banks for each of RGB colors, each capable of storing one screen's worth of data (R-B1, R-B2, G-B1, G-B2, B-B1, and B-B2 in FIG. 2). The converted data is stored in one bank for each color (R-B1, G-B1, and B-B1 in FIG. 2). Note that full-color frame buffer 105 corresponds to two frame buffers 603 in the prior art shown in FIG. 6, integrated into a single frame buffer.

[0026] At the same time that data is written to one bank for each color in all-color frame buffer 105 as described above, data already written from the other bank for each color in all-color frame buffer 105 (R-B2, G-B2, and B-B2 in FIG. 2) is read out in a predetermined order, sent to backplane IC 102 via inter-chip cable 107, and written to monochrome frame buffer 108. Monochrome frame buffer 108 has a capacity sufficient to store data for only one color, RGB (one-third the capacity of all-color frame buffer 105), and has two banks in total (S-B1 and S-B2 in FIG. 2). Monochrome data sent from control IC 101 is stored in one of the two banks (S-B1 in FIG. 2). Note that S-B1 and S-B2 in FIG. 2 correspond to the upper and lower monochrome frame buffers 108 in FIG. 1, respectively.

[0027] At the same timing as above, the monochrome data that has already been written is read from the other bank (S-B2 in FIG. 2) of the monochrome frame buffer 108, and the read monochrome data is sent to the pulse width control circuit 109 and supplied to the display pixels 110 (not shown) as voltages having a predetermined pulse width. For ease of explanation, the upper and lower pulse width control circuits 109 in FIG. 1 are collectively shown as a single pulse width control circuit 109 in FIG. 2.

[0028] The table at the bottom of Figure 2 shows an example of the timing of the above data transfer, where the top row shows data transfer from the data conversion circuit 104 (conversion circuit) to the all-color frame buffer 105 (all-color FB), the middle row shows data transfer from the all-color frame buffer 105 (all-color FB) to the monochrome frame buffer 108 (monochrome FB), and the bottom row shows data transfer from the monochrome frame buffer 108 (monochrome FB) to the pulse width control circuit 109 (PW circuit).

[0029] As shown in the table at the bottom of Fig. 2, data transfer from data conversion circuit 104 to all-color frame buffer 105 is performed sequentially from timing 1 to timing 3. Data transfer from all-color frame buffer 105 to monochrome frame buffer 108 is performed sequentially for each color (in the order of RGB in Fig. 2), while switching banks of monochrome frame buffer 108. Data transfer from monochrome frame buffer 108 to pulse width control circuit 109 is performed while switching banks for each timing, for the monochrome data stored in monochrome frame buffer 108 at the previous timing.

[0030] Specifically, from timing 1 to timing 3, data is transferred (written) from the data conversion circuit 104 to the R-B1, G-B1, and B-B1 banks of the all-color frame buffer 105. At the same time, at timing 1, data is transferred (written) from R-B2 of the all-color frame buffer 105 to S-B1 of the monochrome frame buffer 108, and simultaneously, data is transferred (read) from S-B2 of the monochrome frame buffer 108 to the pulse width control circuit 109. At timing 2, data is transferred (written) from G-B2 of the all-color frame buffer 105 to S-B2 of the monochrome frame buffer 108, and simultaneously, data is transferred (read) from S-B1 of the monochrome frame buffer 108 to the pulse width control circuit 109. Furthermore, at timing 3, data is transferred (written) from B-B2 of full-color frame buffer 105 to S-B1 of monochrome frame buffer 108, and simultaneously, data is transferred (read) from S-B2 of monochrome frame buffer 108 to pulse width control circuit 109. After timing 3, the same process as above is repeated, with alternating switching between R-B1, G-B1, B-B1 and R-B2, G-B2, B-B3 of full-color frame buffer 105. These operations are synchronized with the emission of light from the light sources of each of the RGB colors, thereby displaying a color image using the field sequential method.

[0031] In this way, each data transfer is synchronized at each timing and occurs without any bottlenecks, so there are no data delays and continuous images are displayed on the LCOS display panel screen in response to continuous video data input from outside.

[0032] Because the majority of the control IC 101 circuitry is composed of logic circuits and volatile memory, it can be fabricated using a micro-semiconductor process. Using a micro-semiconductor process can reduce chip size and chip costs, and also reduce power consumption. In recent years, micro-semiconductor processes have been used only for large-diameter (e.g., 12-inch) silicon wafers. However, the control IC 101 in the present embodiment is not integrated into the LCOS display panel body but is mounted on a circuit board or the like separate from the LCOS display panel. This eliminates production problems even if the LCOS display panel manufacturing equipment is not compatible with large-diameter wafers.

[0033] On the other hand, the backplane IC 102 according to the embodiment of the present invention has a frame buffer capacity that is one-third that of the backplane IC of the conventional LCOS display panel shown in FIG. 6, which allows the chip area to be reduced accordingly. This contributes to the miniaturization of LCOS display panels. Furthermore, because the backplane IC 102 can have a small chip area as described above, it can be supplied on small-diameter (e.g., 8-inch) silicon wafers that do not use fine semiconductor processes, rather than large-diameter (e.g., 12-inch) silicon wafers that use fine semiconductor processes. In other words, LCOS display panels using the backplane IC 102 according to the embodiment of the present invention can be produced using inexpensive manufacturing equipment for small-diameter silicon wafers, rather than using manufacturing equipment (such as a wafer dividing device) for expensive large-diameter silicon wafers. This contributes to the reduction of costs for LCOS display panels. [Example]

[0034] In the conventional LCOS display panel shown in Fig. 5, for example, if a product with higher resolution or finer pixels is required, it is necessary to completely redesign the backplane IC 501. In contrast, in the LCOS display panel according to the embodiment of the present invention shown in Fig. 1, if only the backplane IC 102 is redesigned to meet the required specifications, the control IC 101 can be used in common without being redesigned.

[0035] FIG. 3 is a diagram schematically illustrating the circuit configuration of a liquid crystal display device according to another embodiment of the present invention. As shown in FIG. 3, a control IC 201 according to another embodiment of the present invention has a circuit configuration different from that of the control IC 101 according to the embodiment of the present invention shown in FIG. 1. The control IC 201 includes a setting circuit 211 for setting the resolution of the connected LCOS display panel, a setting interface circuit 212 for writing the setting information, a nonvolatile memory 213 for storing the set information, and a setting interface circuit 212 for writing the setting information. The setting interface circuit 212 is connected to the setting circuit 211. The nonvolatile memory 213 is connected to the setting circuit 211. The setting circuit 211 is connected in parallel to the data conversion circuit 204 and the full-color frame buffer 205. The nonvolatile memory 213 may be external. If a circuit for setting the specifications of the LCOS display panel is already provided, that circuit may be used in place of the setting circuit 211.

[0036] 3 shows three LCOS display panels 214 to 216 (LCOS-1 to 3) as examples of LCOS display panels that can be connected to the common control IC 201. However, the types of LCOS display panels that can be connected are not limited to the three shown in the figure. The LCOS display panels 214 to 216 (hereinafter referred to as LCOS-1 to 3) have, for example, the following resolutions and pixel pitches: LCOS-1 Resolution: 1280 x 720 Pixel pitch: 6 micrometers LCOS-2 Resolution: 1280 x 720 Pixel pitch: 4 micrometers LCOS-3 Resolution: 1600 x 1200 Pixel pitch: 6 micrometers

[0037] LCOS-1 and LCOS-2 have the same resolution and only the pixel pitch is different, so either LCOS can be connected to the control IC 201 without changing the resolution setting. On the other hand, LCOS-3 has a different resolution from LCOS-1 and LCOS-2, so it can be connected to the control IC 201 by changing the resolution setting using the setting circuit 211.

[0038] FIG. 4 is a diagram illustrating the internal structure of a full-color frame buffer according to another embodiment of the present invention. As shown in FIG. 4, the capacity of the full-color frame buffer 205 is designed with a margin, taking into account the expected future use of high-resolution LCOS display panels. For example, when an LCOS-1 is connected to the control IC 201, the buffer area from the memory start position to the usable range of the LCOS-1 is used, and the remaining buffer area is unused. Similarly, when an LCOS-3 is connected to the control IC 201, the buffer area from the memory start position to the usable range of the LCOS-3 is used, and the remaining buffer area is unused. Note that it is also possible to connect an LCOS display panel with a higher resolution than the LCOS-3, as long as the used buffer area does not exceed the memory upper limit.

[0039] In this embodiment, not only the full-color frame buffer 205 but also the data conversion circuit 204 performs operations (data conversion, etc.) in accordance with the resolution set by the setting circuit 211.

[0040] The present invention is not limited to the above examples and may take other forms. For example, the present invention can be applied to a liquid crystal display device in which the backplane IC is made of a material other than single-crystal silicon. Furthermore, the present invention is not limited to liquid crystal display devices using ferroelectric liquid crystals, but can also be applied to liquid crystal display devices using other liquid crystals (nematic liquid crystals, etc.). Furthermore, the present invention is not limited to liquid crystal display devices that display images of three colors (RGB) using a field sequential system, but can also be applied to liquid crystal display devices that display images of other colors using a field sequential system. [Explanation of symbols]

[0041] 101, 201 control IC 102 Backplane IC 103 External interface circuit 104, 204 Data conversion circuit 105, 205 full color frame buffer 106 Chip-to-chip interface circuit 107 Chip-to-chip cable 108 monochrome frame buffer 109 Pulse width control circuit 211 Setting circuit 212 Setting interface circuit 213 Non-volatile memory 214 LCOS display panel (LCOS-1) 215 LCOS display panel (LCOS-2) 216 LCOS display panel (LCOS-3)

Claims

1. A liquid crystal display device having a liquid crystal panel that displays color images by a field sequential method, a first IC separated from the liquid crystal panel and a second IC constituting a part of the liquid crystal panel; the first IC includes a first frame buffer having a memory capacity capable of storing all image data corresponding to a plurality of color images to be displayed on the liquid crystal panel; the second IC includes pixel electrodes and a second frame buffer having a memory capacity capable of storing only image data corresponding to images of some colors among images of a plurality of colors displayed on the liquid crystal panel; the first IC and the second IC are electrically connected to each other; Image data input from the outside to the first IC is written into the first frame buffer as image data for each color, the image data for each color written in the first frame buffer is read from the first frame buffer in a predetermined order and written in the second frame buffer; a color image is displayed on the liquid crystal panel based on the image data written in the second frame buffer; A liquid crystal display device characterized by:

2. 2. The liquid crystal display device according to claim 1, wherein the second frame buffer has a memory capacity capable of storing only image data corresponding to an image of one of three colors of RGB.

3. 2. The liquid crystal display device according to claim 1, wherein the first IC includes a video data conversion circuit that converts video data input from outside into the image data for each color, and the data conversion operation of the image data conversion circuit and the memory usage area of the first frame buffer can be changed according to the number of pixels of the liquid crystal panel.

Images