Electroluminescent display apparatus and method of driving electroluminescent display apparatus

Abstract

To decrease a luminance deviation occurring between a sensing pixel and a non-sensing pixel.SOLUTION: An electroluminescent display apparatus comprises: a display panel including a target pixel for sensing; a data driver that supplies display data voltage to the target pixel in an image writing period of one frame, supplies sensing data voltage to the target pixel in a sensing period, supplies luminance compensation data voltage to the target pixel in a sensing line compensation period, and supplies luminance recovery data voltage to the target pixel in a recovery period; and a sensing circuit that obtains an electrical characteristic of the target pixel in the sensing period. The image writing period, the sensing period, the sensing line compensation period, and the recovery period are sequentially arranged. The luminance compensation data voltage has a voltage level higher than display data voltage, and the luminance recovery data voltage is set within a predetermined recovery voltage range including the display data voltage and the luminance compensation data voltage.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present specification relates to an electroluminescent display device and a method for driving an electroluminescent display device. [Background technology]

[0002] Each pixel of the electroluminescence display includes a light emitting element that emits light by itself, and the electroluminescence display adjusts brightness by controlling the amount of light emitted by the light emitting element according to a data voltage corresponding to the gray level of image data.

[0003] An electroluminescent display device employs an external compensation technique to improve image quality, which senses the electrical characteristics of pixels during image display and adjusts input image data based on the sensed results to compensate for electrical characteristic deviations between pixels.

[0004] The electrical characteristics of a pixel may be sensed while the input image is being displayed. At this time, the sensing pixel stops emitting light for a while during the sensing period. In other words, the electrical characteristics of the pixel are in a non-emitting state. This can cause brightness deviation between the sensing pixel and the non-sensing pixel. This problem becomes even more pronounced when using VRR (Variable Refresh Rate) driving, where the frame frequency changes depending on the input image. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, the present invention provides an electroluminescent display device and a method for driving the electroluminescent display device that can reduce the luminance deviation between the sensing pixel and the non-sensing pixel. [Means for solving the problem]

[0006] The electroluminescence display device according to the present embodiment includes a display panel having a target pixel to be sensed; a data driver that supplies a display data voltage to the target pixel in an image writing period of one frame, a sensing data voltage to the target pixel in a sensing period, a luminance compensation data voltage to the target pixel in a sensing line compensation period, and a luminance recovery data voltage to the target pixel in a recovery period; and a sensing circuit that senses an electrical characteristic of the target pixel in response to the sensing data voltage in the sensing period, wherein the image writing period, the sensing period, the sensing line compensation period, and the recovery period are arranged in this order, the luminance compensation data voltage has a voltage level higher than the display data voltage, and the luminance recovery data voltage is determined within a predetermined recovery voltage range including the display data voltage and the luminance compensation data voltage.

[0007] According to an embodiment of the present invention, a driving method for an electroluminescent display device having a display panel including a target pixel to be sensed includes the steps of: supplying a display data voltage to the target pixel in an image writing period of one frame; supplying a sensing data voltage to the target pixel in a sensing period; supplying a luminance compensation data voltage to the target pixel in a sensing line compensation period; and supplying a luminance recovery data voltage to the target pixel in a recovery period; and sensing an electrical characteristic of the target pixel in response to the sensing data voltage in the sensing period, wherein the image writing period, the sensing period, the sensing line compensation period, and the recovery period are arranged in this order; the luminance compensation data voltage has a higher voltage level than the display data voltage; and the luminance recovery data voltage is determined within a predetermined recovery voltage range including the display data voltage and the luminance compensation data voltage. [Effects of the Invention]

[0008] This embodiment can effectively reduce the brightness deviation between the sensing pixels and the non-sensing pixels.

[0009] The effects of this embodiment are not limited to the above examples, and various other effects are included within the present specification. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram showing an electroluminescent display device according to an embodiment of the present invention; [Figure 2] 2 is a diagram showing a pixel array included in the electroluminescent display device of FIG. 1; [Figure 3] 3 is a diagram showing one pixel included in the pixel array of FIG. 2 and a sensing circuit connected thereto. [Figure 4] FIG. 10 is a diagram for explaining VRR driving. [Figure 5] FIG. 10 is a diagram for explaining VRR driving. [Figure 6] FIG. 10 is a diagram showing how RT sensing driving, SLC driving, and recovery driving progress for one sensing pixel line at different positions for each frame. [Figure 7] 10A and 10B are diagrams illustrating an example in which a compensation gain is differentially set according to the length of the SLC section. [Figure 8] FIG. 10 illustrates display driving of non-sensing pixel lines. [Figure 9] FIG. 10 illustrates display driving of non-sensing pixel lines. [Figure 10] 10 is a diagram illustrating, as a comparative example, a case in which RT sensing driving is performed on a sensing pixel line followed by long-term SLC driving. [Figure 11] 10 is a diagram illustrating, as a comparative example, a case in which RT sensing driving is performed on a sensing pixel line followed by long-term SLC driving. [Figure 12] FIG. 10 is a diagram illustrating RT sensing drive, SLC drive, and recovery RECV drive of a sensing pixel line as an embodiment. [Figure 13]FIG. 10 is a diagram illustrating RT sensing drive, SLC drive, and recovery RECV drive of a sensing pixel line as an embodiment. [Figure 14] 5A to 5C are diagrams illustrating a method for driving an electroluminescence display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] The advantages and features of the present specification, as well as methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, and may be embodied in various forms. The present embodiment is provided so that the disclosure of the present specification will be complete and will fully convey the scope of the specification to those skilled in the art, and the present specification is defined only by the scope of the claims.

[0012] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of the present specification are merely exemplary and are not intended to limit the scope of the present specification. The same reference numerals refer to the same components throughout the specification. When "comprises," "has," "achieves," etc. are used in this specification, other parts may be added unless "only" is used. When an element is expressed in the singular, it also includes the plural unless otherwise explicitly stated.

[0013] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0014] When describing the location of two parts, for example, "above," "on top," "below," or "next to," there may be one or more other parts located between the two parts, unless "immediately" or "directly" is used.

[0015] Although terms such as "first" and "second" may be used to describe various components, these components are not limited by these terms. These terms are used to distinguish only one component from another. Therefore, a first component referred to below may be a second component within the technical concept of this specification.

[0016] Throughout the specification, the same reference numerals refer to substantially the same components. The pixel circuits and gate drivers formed on the substrate of the display panel in this specification may be realized with transistors having an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, but are not limited thereto and can also be realized with transistors having a p-type MOSFET structure. A transistor is a three-electrode element including a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. That is, carriers in a MOSFET flow from the source to the drain. In the case of an n-type transistor (NMOS), the carriers are electrons, so the source voltage is lower than the drain voltage so that electrons flow from the source to the drain. In an n-type transistor, electrons flow from the source to the drain, so the direction of current flows from the drain to the source. In contrast, in the case of a p-type transistor (PMOS), the carriers are holes, so the source voltage is higher than the drain voltage so that holes flow from the source to the drain. In a p-type transistor, holes flow from the source to the drain, causing current to flow from the source to the drain. It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can change depending on the applied voltage. Therefore, in the description of the embodiments herein, one of the source and drain will be referred to as a first electrode and the other as a second electrode.

[0017] In the following description, if it is determined that a detailed description of known functions or configurations related to this specification may unnecessarily obscure the gist of this specification, the detailed description will be omitted. Hereinafter, embodiments of this specification will be described in detail with reference to the accompanying drawings.

[0018] Fig. 1 is a diagram showing an electroluminescent display device according to the present embodiment. Fig. 2 is a diagram showing a pixel array included in the electroluminescent display device of Fig. 1. Fig. 3 is a diagram showing one pixel included in the pixel array of Fig. 2 and a sensing circuit connected thereto. Figs. 4 and 5 are diagrams for explaining VRR driving.

[0019] 1 and 2, the electroluminescence display device according to the present embodiment may include a display panel 10, a timing controller 11, a data driver 12, a gate driver 13, and a sensing circuit 122.

[0020] The display panel 10 may include a plurality of data lines 15, readout lines 16, and a plurality of gate lines 17. Pixels PXL may be arranged at the intersections of the data lines 15, readout lines 16, and gate lines 17. The pixels PXL arranged in a matrix form a pixel array as shown in FIG. 2 in the display area AA of the display panel 10.

[0021] In the pixel array, pixel lines PL1 to PL4 may be realized by pixels PXL adjacent in the extension direction of the gate line 17 (i.e., the X-axis direction). Each of the pixel lines PL1 to PL4 includes a plurality of pixels PXL adjacent in the X-axis direction. The pixels PXL constituting the same pixel line PL may be connected to the same gate line 17 and connected to different data lines 15. The pixels PXL constituting the same pixel line PL may be connected to different readout lines 16. However, this is not limited thereto, and a plurality of pixels PXL constituting different colors may share a single readout line 16.

[0022] In the pixel array, each pixel PXL may be connected to a data voltage supply DAC 121 via any one of the data lines 15, to a sensing circuit 122 via any one of the readout lines 16, and to a gate driver 13 via any one of the gate lines 17. Each pixel PXL may also be connected to a high-potential pixel power supply EVDD via a high-potential power supply line 18.

[0023] In the pixel array, the pixels PXL may include a pixel that realizes a first color, a pixel that realizes a second color, a pixel that realizes a third color, and may further include a pixel that realizes a fourth color, where the first to fourth colors may be any one of red, green, blue, and white.

[0024] Each pixel PXL may be implemented as shown in FIG.

[0025] Referring to FIG. 3, one pixel PXL arranged in the kth (k is an integer) pixel line PLk may include a light-emitting element EL, a driving transistor DT, a storage capacitor Cst, a first switch transistor ST1, and a second switch transistor ST2, and the first switch transistor ST1 and the second switch transistor ST2 are connected to the same gate line 17(k).

[0026] The light-emitting element EL emits light in response to the pixel current. The light-emitting element EL includes an anode electrode connected to a source node Ns, a cathode electrode connected to a low-potential pixel power supply EVSS, and organic or inorganic compound layers located between the anode and cathode electrodes. The organic or inorganic compound layers consist of a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The light-emitting element EL turns on when the voltage applied to the anode electrode exceeds the EL operating point voltage compared to the low-potential pixel power supply EVSS applied to the cathode electrode. When the light-emitting element EL turns on, holes that have passed through the hole transport layer HTL and electrons that have passed through the electron transport layer ETL migrate to the emission layer EML to form excitons, resulting in light generation in the emission layer EML.

[0027] The driving transistor DT is a driving element. The driving transistor DT generates a pixel current to be supplied to the light-emitting element EL according to the voltage difference between the gate node Ng and the source node Ns. The driving transistor DT includes a gate electrode connected to the gate node Ng, a first electrode connected to a high-potential pixel power supply EVDD, and a second electrode connected to the source node Ns.

[0028] The storage capacitor Cst is connected between the gate node Ng and the source node Ns to store the gate-source voltage of the driving transistor DT.

[0029] The first switch transistor ST1 electrically connects the data line 15 and the gate node Ng in response to the gate signal SCAN(k) and applies the data voltage VDATA charged on the data line 15 to the gate node Ng. The first switch transistor ST1 has a gate electrode connected to the gate line 17(k), a first electrode connected to the data line 15, and a second electrode connected to the gate node Ng.

[0030] The second switch transistor ST2 electrically connects the readout line 16 and the source node Ns in response to the gate signal SCAN(k) to transfer the voltage of the source node Ns corresponding to the pixel current to the readout line 16 or apply the reference voltage Vref charged in the readout line 16 to the source node Ns. The second switch transistor ST2 has a gate electrode connected to the gate line 17(k), a first electrode connected to the source node Ns, and a second electrode connected to the readout line 16.

[0031] This pixel structure is merely an example, and the technical concept of this specification is not limited to this pixel structure. It should be noted that the technical concept of this specification can be applied to various pixel structures that can sense the electrical characteristics (threshold voltage or electron mobility) of the drive transistor DT.

[0032] The timing controller 11 may be connected to the host system 14 via a first interface circuit and to the data driver 12 via a second interface circuit. The first interface circuit and the second interface circuit may be the same or different.

[0033] The timing controller 11 receives a vertical synchronization signal Vsync, a data enable signal DE, input video data DATA, and the like from a host system 14 via a first interface circuit.

[0034] As shown in Figure 4, one frame is defined by a vertical synchronization signal Vsync and a data enable signal DE, and a vertical active interval ACT and a vertical blank interval BLK are also defined within one frame. One frame can be defined as one period of the vertical synchronization signal Vsync. The vertical active interval ACT can be defined as a period during which the data enable signal DE transitions between logic high and logic low within one frame. The vertical blank interval BLK can be defined as a period during which the data enable signal DE is maintained at logic low within one frame.

[0035] The length of the vertical blanking interval BLK can be varied by the vertical synchronization signal Vsync and the data enable signal DE. The host system 14 can vary the length of the vertical blanking interval BLK based on the complexity of the input video data DATA, the amount of change between frames of the input video data DATA, etc., to change the frame frequency during driving.

[0036] When the input video data DATA is complex and the amount of change between frames is large (e.g., game video with frequent scene changes), the host system 14 may increase the frame frequency by shortening the length of the vertical blank interval BLK belonging to each frame. In contrast, when the amount of change between frames is small or absent, as in still images, the host system 14 may increase the length of the vertical blank interval BLK belonging to each frame to decrease the frame frequency. Varying the frame frequency by adjusting the length of the vertical blank interval BLK in this way is called VRR (Variable Refresh Rate) technology. VRR technology is used to ensure sufficient rendering time for graphics processing in the host system 14, suppressing image tearing, and providing smoother images.

[0037] The electroluminescent display device of this embodiment may be a variable frequency display device operating in a VRR mode, in which the frame frequency can be varied within a preset frequency variable range.

[0038] For example, the frame frequency can be changed to A, B, or C Hz as shown in Figure 5. The length of the vertical active interval ACT is determined based on the maximum frame frequency REF within the frequency variable range. The length of the vertical active interval ACT is fixed regardless of changes in the frame frequency. In contrast, the length of the vertical blank interval BLK changes according to the frame frequency. The lower the frame frequency, the longer the length of the vertical blank interval BLK. In Figure 5, the length of the vertical blank interval BLK is BLK1 for A Hz, BLK2 for B Hz, and BLK3 for C Hz. Since the relative magnitudes of the frame frequencies are A>B>C, BLK1 <BLK2<BLK3となる。

[0039] The host system 14 may be mounted on a system board. The host system 14 may include an input unit for receiving user commands / data, a main power supply unit for generating main power, a VRR control circuit for varying the frame frequency according to the input video, an output unit for outputting a transmission signal, etc. The host system 14 may be implemented as, but is not limited to, an application processor, a personal computer, a set-top box, a graphics processor unit, etc.

[0040] The timing controller 11 generates timing control signals required for display driving, real time (RT) sensing driving, sensing line compensation (SLC) driving, and recovery driving, and can provide these timing control signals to the data driver 12 and gate driver 13 via a second interface circuit. The timing control signals include a data timing control signal (DDC) for controlling the operation timing of the data driver 12 and a gate timing control signal (GDC) for controlling the operation timing of the gate driver 13.

[0041] 4, display driving is for image writing and is performed during a vertical active interval ACT. During the vertical active interval ACT, image writing is performed sequentially for all pixels PXL of the pixel array. That is, all pixels PXL emit light during the vertical active interval ACT according to the image writing order, which proceeds sequentially in pixel line units.

[0042] RT sensing is performed during the vertical blank period (BLK) when no image is written. RT sensing is performed on one pixel line at a predetermined position to sense the electrical characteristics (i.e., the threshold voltage or electron mobility of the driving transistor) of the target pixel belonging to that pixel line. The position of the pixel line driven by RT sensing changes every frame. To improve sensing capability, the target pixel stops emitting light during the RT sensing period.

[0043] The RT sensing drive may be performed sequentially or non-sequentially for each pixel line in the vertical blanking section BLK of each frame. The remaining pixel lines except for the one pixel line that is driven by the RT sensing drive in the vertical blanking section BLK of each frame maintain the light emitting state (i.e., display state) of the previous vertical active section ACT.

[0044] SLC driving is performed on target pixels in one pixel line (i.e., sensing pixel line) where RT sensing driving has been completed. SLC driving is intended to compensate for brightness loss caused by the target pixels not emitting light during the RT sensing period. The brightness compensation data voltage for SLC driving is higher than the display data voltage written for display driving.

[0045] Recovery RECV driving is performed on target pixels in a sensing pixel line where SLC driving has been completed. Because SLC driving boosts the brightness of the target pixels, SLC driving is performed for a predetermined short time, and recovery driving is performed for the remaining time. The recovery period for recovery driving can continue until the image of the subsequent frame is written.

[0046] Recovery RECV drive helps reduce the luminance of the target pixel from the boost level to the display drive level. The data voltage of luminance recovery for recovery drive can be the same as or higher than the data voltage for the display. In long-term SLC drive, the luminance boost can cause the sensing pixel line to be perceived as a bright line, but recovery drive combined with short-term SLC drive is effective in improving this side effect.

[0047] The timing controller 11 receives sensing data corresponding to the RT sensing drive from the data driver 12 via the second interface circuit. The sensing data reflects the electrical characteristics of the driving transistor DT included in the sensed pixel PXL. The timing controller 11 calculates a pixel compensation value capable of compensating for the electrical characteristic deviation of the pixel PXL based on the sensing data, and corrects the input image data DATA based on this pixel compensation value. The timing controller 11 supplies the video data DATA corrected with the pixel compensation value to the data driver 12 via the second interface circuit.

[0048] The gate driver 13 may be formed in the non-display area NA of the display panel 10 according to a gate-driver in panel (GIP) scheme. The gate driver 13 generates a gate signal SCAN that swings between an ON voltage and an OFF voltage based on a gate timing control signal GDC. The gate driver 13 sequentially supplies the gate signal SCAN to gate lines 17(1) to 17(4), ..., during a vertical active period ACT of each frame. The gate driver 13 supplies the gate signal SCAN to the gate lines 17 connected to pixels PXL of the sensing pixel line during a vertical blank period BLK of each frame.

[0049] The data driver 12 may be implemented as a data integrated circuit. The data driver 12 includes a data voltage supply unit DAC 121 that generates a data voltage VDATA based on a data timing control signal DDC, and a sensing circuit SU 122. The data voltage (VDATA) may be divided into a voltage for display, a voltage for sensing, a voltage for brightness compensation, and a voltage for brightness recovery.

[0050] The data voltage supplier DAC 121 is connected to the pixel array via one of the data lines 15. The data voltage supplier DAC 121 generates display data voltages with different voltage levels according to the gray levels of the video data DATA for display driving during the vertical active period ACT of each frame and supplies the display data voltages to the data lines 15. The display data voltages are supplied to the gate nodes Ng of all pixels PXL in synchronization with the gate signal SCAN. The data voltage supplier DAC 121 generates sensing data voltages for RT sensing driving during the vertical blank period BLK of each frame and supplies the sensing data voltages to the data lines 15, generates brightness compensation data voltages for SLC driving and supplies the brightness compensation data voltages to the data lines 15, and generates brightness recovery data voltages for recovery driving and supplies the brightness compensation data voltages to the data lines 15. The sensing data voltages, brightness compensation data voltages, and brightness recovery data voltages are supplied to the gate nodes Ng of the target pixels PXL in synchronization with different pulses of the gate signal SCAN.

[0051] The sensing circuit SU 122 is connected to the target pixel PXL of the sensing pixel line via the readout line 18. The sensing circuit SU senses the pixel current flowing through the target pixel PXL in response to the sensing data voltage, or the source node voltage of the target pixel PXL corresponding to the pixel current, via the readout line 18. The pixel current or the source node voltage varies depending on the degree of degradation of the target pixel PXL.

[0052] The sensing circuit SU, 122 may be realized as a voltage sensing type that samples the source node voltage, or as a current sensing type that samples the pixel current.

[0053] The voltage-sensing circuit SU, 122 may include a sampling circuit SAM and an analog-to-digital converter ADC, as in Fig. 3. The sampling circuit SAM directly samples the source node voltage of the sensing target pixel PXL stored in the parasitic capacitor of the readout line 16. The analog-to-digital converter ADC converts the analog voltage sampled by the sampling circuit SAM into a digital sensing result value, and then transmits it to the timing controller 11.

[0054] The current-sensing circuit SU, 122 may include a current integrator, a sampling circuit, and an analog-to-digital converter. The current integrator integrates the pixel current flowing through the sensing target pixel PXL to output a sensing voltage. The sampling circuit samples the sensing voltage output from the current integrator. The analog-to-digital converter converts the analog voltage sampled by the sampling circuit into a digital sensing result value and then transmits it to the timing controller 11.

[0055] In each of the display driving, RT sensing driving, SLC driving, and recovery RECV driving, the sensing circuit SU 122 turns on the first switch SW1 to supply the reference voltage Vref to the readout line 16 in synchronization with the timing at which the data voltage VDATA is supplied to the data line 15. The reference voltage Vref charged to the readout line 16 is supplied to the source node Ns of the pixel PXL in synchronization with the gate signal SCAN.

[0056] 6 is a diagram illustrating how the RT sensing drive, SLC drive, and recovery drive proceed for one sensing pixel line at different positions in each frame. FIG. 7 is a diagram illustrating an example in which compensation gains are differentially set according to the length of the SLC section.

[0057] 6, display driving DIS for all pixel lines in an image writing period belonging to a vertical active period ACT of the Nth frame is performed in a line-sequential manner. RT sensing driving is performed for the sensing pixel line PLx in a sensing period belonging to a vertical blank period BLK of the Nth frame. Then, SLC driving is performed for the sensing pixel line PLx in a sensing line compensation period following the sensing period, and recovery RECV driving is performed for the sensing pixel line PLx in a recovery period following the sensing line compensation period.

[0058] In a video writing period belonging to a vertical active period ACT of the (N+1)th frame, display driving DIS for all pixel lines is performed in a line-sequential manner. In a sensing period belonging to a vertical blank period BLK of the (N+1)th frame, RT sensing driving is performed for the sensing pixel line PLy. Then, in an SLC period following the sensing period, SLC driving is performed for the sensing pixel line PLy, and in a recovery period following the SLC period, recovery RECV driving is performed for the sensing pixel line PLy.

[0059] The length of the SLC period is shortest at the top of the panel, where the display driving DIS sequence is earliest, and the length of the SLC period is longest at the bottom of the panel, where the display driving DIS sequence is latest. For uniform compensation at all panel positions, the compensation gain may be set differently depending on the length of the SLC period, as shown in Fig. 7. That is, the compensation gain may be set largest corresponding to the top of the panel, where the SLC period is shortest, and smallest corresponding to the bottom of the panel, where the SLC period is longest.

[0060] 8 and 9 are diagrams illustrating display driving of non-sensing pixel lines.

[0061] Referring to Figures 8 and 9, during the image writing periods of the Nth frame and the N+1th frame, the non-sensing pixels included in the non-sensing pixel line PLa are supplied with a display data voltage VD-DIS synchronized with the first gate pulse GP1, thereby driving the display DIS.

[0062] The luminance of the non-sensing pixel may vary depending on the level of the display data voltage VD-DIS. The luminance of the non-sensing pixel in the Nth frame may be L1, and the luminance of the non-sensing pixel in the (N+1)th frame may be Lx. The luminance of the non-sensing pixel is updated in the vertical active period ACT of each frame, and the updated pixel luminance is maintained in the vertical blank period BLK.

[0063] 10 and 11 are diagrams illustrating, as a comparative example, a case where RT sensing driving is performed on a sensing pixel line followed by long-term SLC driving. Referring to Figures 10 and 11, during the image writing period within the vertical active period ACT of the Nth frame, the target pixel (i.e., sensing pixel) included in the sensing pixel line PLb is supplied with the display data voltage VD-DIS synchronous with the first gate pulse GP1, thereby driving the display DIS.

[0064] Then, in a sensing period within the vertical blanking period BLK of the Nth frame, the target pixel is supplied with a sensing data voltage VD-RT synchronized with the second gate pulse GP2 and driven as an RT sensing. Then, in an SLC period following the sensing period, the target pixel is supplied with a brightness compensation data voltage VD-SLC synchronized with the third gate pulse GP3 and driven as an SLC. The SLC period may continue until before the image of the N+1th frame is written.

[0065] The luminance of the target pixel may be L1 in the image writing period, L2 corresponding to the black gradation in the sensing period, and L3 greater than L1 in the SLC period. By boosting the luminance of the target pixel to L3 greater than L1 through SLC driving, it is possible to compensate for the luminance loss due to non-emission in the sensing period.

[0066] According to this comparative example, when the frame frequency is low in the VRR mode, the SLC period in which the luminance is boosted becomes long, and the sensing pixel line PLb may be recognized as a bright line.

[0067] 12 and 13 are diagrams showing RT sensing drive, SLC drive, and recovery RECV drive of a sensing pixel line as an embodiment.

[0068] Referring to Figures 12 and 13, during the image writing period within the vertical active period ACT of the Nth frame, the target pixel (i.e., sensing pixel) included in the sensing pixel line PLb is supplied with the synchronous display data voltage VD-DIS by the first gate pulse GP1, thereby performing display driving DIS.

[0069] Then, in the sensing period in the vertical blank period BLK of the Nth frame, the target pixel is supplied with a sensing data voltage VD-RT synchronized with the second gate pulse GP2 to perform RT sensing driving. Then, in the SLC period following the sensing period, the target pixel is supplied with a brightness compensation data voltage VD-SLC synchronized with the third gate pulse GP3 to perform SLC driving. Then, in the recovery RECV period following the SLC period, the target pixel is supplied with a brightness recovery data voltage VD-RECV synchronized with the fourth gate pulse GP4 to perform recovery RECV driving.

[0070] The video writing section, the sensing section, the SLC section, and the recovery RECV section are successive in sequence.

[0071] The brightness compensation data voltage VD-SLC is for brightness boosting and has a voltage level greater than the display data voltage VD-DIS, whereas the brightness recovery data voltage VD-RECV is for preventing the sensing pixel line PLb from being recognized as a bright line and has the same voltage level as the display data voltage VD-DIS.

[0072] The luminance of the target pixel is L1 during the image writing period and recovery period (RECV), L2 corresponding to the black gradation during the sensing period, and L3 greater than L1 during the SLC period. By boosting the luminance of the target pixel to L3 greater than L1 through SLC driving, it is possible to compensate for the luminance loss due to non-emission during the sensing period.

[0073] In the comparative example described above, the length of the SLC section for the sensing pixel line PLb at the same position increases depending on the frame frequency, which is a problem. In the present embodiment, the length of the SLC section for the sensing pixel line PLb at the same position is fixed regardless of changes in the frame frequency. That is, in the present embodiment, the length of the SLC section for the sensing pixel line PLb at the same position is fixed based on the maximum frame frequency REF Hz within a preset frequency variable range. However, the SLC sections have different fixed lengths depending on the position of the sensing pixel line PLb.

[0074] As described above, in this embodiment, SLC driving is performed for only a predetermined short time, and recovery RECV driving is performed for the remaining time. The recovery RECV period may continue until before the image of the (N+1)th frame is written. The recovery RECV driving serves to lower the luminance of the target pixel from the boost level L3 to the display drive level L1. While the length of the SLC period targeting the sensing pixel line PLb at the same position is fixed regardless of changes in the frame frequency, the length of the recovery RECV period targeting the sensing pixel line PLb at the same position changes according to changes in the frame frequency. The lower the frame frequency, the longer the recovery RECV period, and the higher the frame frequency, the shorter the recovery RECV period.

[0075] Meanwhile, in the above-described embodiment, the brightness recovery data voltage VD-RECV has the same voltage level as the display data voltage VD-DIS. However, the brightness recovery data voltage VD-RECV may be applied at a voltage level greater than the display data voltage VD-DIS depending on the gray level of the display data voltage VD-DIS. For example, when the gray level of the display data voltage VD-DIS is an intermediate gray level or higher, the brightness recovery data voltage VD-RECV has the same voltage level as the display data voltage VD-DIS. On the other hand, when the gray level of the display data voltage VD-DIS is a low gray level, the brightness recovery data voltage VD-RECV may be further adjusted to have a voltage level between the display data voltage VD-DIS and the brightness compensation data voltage VD-SLC. This is because, in low gray levels, brightness differences occur due to changes in the frame frequency, causing the sensing pixel lines to appear relatively dark. However, this problem does not occur in gray levels higher than the intermediate gray level.

[0076] FIG. 14 is a diagram showing a method of driving the electroluminescent display device according to this embodiment.

[0077] 14, in the driving method of this embodiment, a display data voltage VD-DIS synchronized with a first gate pulse GP1 is applied to a target pixel (i.e., a sensing pixel) included in a sensing pixel line PLb during an image writing period within a vertical active period ACT, thereby driving the target pixel (S1, S2). The target pixel emits light as a result of the display driving.

[0078] Next, the driving method of this embodiment applies a sensing data voltage VD-RT synchronized with the second gate pulse GP2 to the target pixel during a sensing period within the vertical blanking period BLK, thereby driving the target pixel in RT sensing mode (S3, S4). During RT sensing, the target pixel ceases to emit light. To stop the target pixel from emitting light, this embodiment may increase the low-potential pixel power supply (EVSS, FIG. 3) applied to the cathode electrode of the light-emitting element during the sensing period above the reference voltage (Vref, FIG. 3).

[0079] After the RT sensing of the non-emission state is completed (S5), the driving method of this embodiment applies a brightness compensation data voltage VD-SLC synchronized with the third gate pulse GP3 to the target pixel during the SLC period following the sensing period, thereby driving the target pixel in SLC mode (S6). The length of the SLC period is fixed to a short time regardless of changes in the frame frequency. The SLC driving compensates for brightness loss due to non-emission during the sensing period.

[0080] Next, in the driving method of this embodiment, a brightness recovery data voltage VD-RECV synchronized with the fourth gate pulse GP4 is applied to the target pixel in the recovery RECV period following the SLC period, thereby driving the target pixel with the recovery RECV (S7). Since the brightness recovery data voltage VD-REC has the same magnitude as the display data voltage VD-DIS, the brightness of the target pixel can be reduced to the display driving level at the boost level.

[0081] From the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the technical spirit of the present specification. Therefore, the technical scope of the present specification should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims. [Explanation of symbols]

[0082] 10 Display panel 11 Timing Controller 12 Data Driver 13 Gate Driver 121 Data voltage supply unit 122 Sensing Circuit

Claims

1. a display panel having a target pixel to be sensed; a data driver that supplies a display data voltage to the target pixel in an image writing period of one frame, supplies a sensing data voltage to the target pixel in a sensing period, supplies a brightness compensation data voltage to the target pixel in a sensing line compensation period, and supplies a brightness recovery data voltage to the target pixel in a recovery period; a sensing circuit configured to sense an electrical characteristic of the target pixel in response to the sensing data voltage during the sensing period; the image writing section, the sensing section, the sensing line compensation section, and the recovery section are arranged in this order, the brightness compensation data voltage has a voltage level higher than the display data voltage; The luminance recovery data voltage is within a predetermined recovery voltage range including the display data voltage and the luminance compensation data voltage.

2. The electroluminescent display device of claim 1 , wherein the brightness recovery data voltage has the same voltage level as the display data voltage.

3. 2. The electroluminescent display device of claim 1, wherein the length of the sensing line compensation section is constant regardless of a change in frame frequency.

4. 2. The electroluminescent display device of claim 1, wherein the length of the sensing line compensation section is constant based on a maximum frame frequency within a preset frequency variable range.

5. 2. The electroluminescent display device according to claim 1, wherein the length of the recovery period varies according to a change in frame frequency.

6. The electroluminescent display device of claim 5 , wherein the length of the recovery period is increased as the frame frequency is decreased.

7. 2. The electroluminescence display device of claim 1, wherein a compensation gain that determines the magnitude of the brightness compensation data voltage is set differently depending on the position of the pixel line including the target pixel.

8. 2. The electroluminescent display device of claim 1, further comprising a gate driver that supplies a first gate pulse synchronized with the display data voltage to the target pixel in the image writing period, supplies a second gate pulse corresponding to the sensing data voltage to the target pixel in the sensing period, supplies a third gate pulse corresponding to the brightness compensation data voltage to the target pixel in the sensing line compensation period, and supplies a fourth gate pulse corresponding to the brightness recovery data voltage to the target pixel in the recovery period.

9. A method for driving an electroluminescent display device having a display panel with a target pixel to be sensed, supplying a display data voltage to the target pixel in an image writing period of one frame, supplying a sensing data voltage to the target pixel in a sensing period, supplying a brightness compensation data voltage to the target pixel in a sensing line compensation period, and supplying a brightness recovery data voltage to the target pixel in a recovery period; sensing an electrical characteristic of the target pixel in response to the sensing data voltage during the sensing period; the image writing section, the sensing section, the sensing line compensation section, and the recovery section are arranged in this order, the brightness compensation data voltage has a voltage level higher than the display data voltage; The brightness recovery data voltage is within a predetermined recovery voltage range including the display data voltage and the brightness compensation data voltage.

10. 10. The method of claim 9, wherein the brightness recovery data voltage has the same voltage level as the display data voltage.

11. 9. The method of claim 8, wherein the length of the sensing line compensation section is constant regardless of a change in frame frequency.

12. 10. The method of claim 9, wherein the length of the sensing line compensation section is constant based on a maximum frame frequency within a preset frequency variable range.

13. 10. The method of claim 9, wherein the length of the recovery period varies according to a change in frame frequency.

14. The method of claim 13, wherein the length of the recovery period is increased as the frame frequency is decreased.

15. 10. The method of claim 9, wherein a compensation gain that determines the magnitude of the brightness compensation data voltage is set differently depending on the position of the pixel line including the target pixel.

16. 10. The method of claim 9, further comprising: supplying a first gate pulse synchronized with the display data voltage to the target pixel in the image writing period; supplying a second gate pulse corresponding to the sensing data voltage to the target pixel in the sensing period; supplying a third gate pulse corresponding to the brightness compensation data voltage to the target pixel in the sensing line compensation period; and supplying a fourth gate pulse corresponding to the brightness recovery data voltage to the target pixel in the recovery period.

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