Duty cycle calibration for phase-locked loop

Abstract

To provide a method and circuit for calibrating a phase-locked loop (PLL) duty cycle.SOLUTION: A duty cycle tuning circuit 200 within a phase-locked loop (PLL) includes a level shifter 204 for tuning one or more of a voltage level and a duty cycle of a clock signal; and comparison logic 206 coupled to an output of the level shifter 204. The comparison logic compares the duty cycle to a target duty cycle and generates a difference value. Tuning logic 202 coupled to an amplifier tunes the duty cycle based on the difference value.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to duty cycle calibration for phase locked loops. [Background technology]

[0002] A phase-locked loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. In many instances, the output signal generated by a PLL is a clock having a duty cycle. For some applications in which a PLL is used, a particular duty cycle for the clock output by the PLL may be required for reasons such as power consumption, signal integrity, heat dissipation, or clock frequency. In other applications, a precise duty cycle of the clock output by the PLL may be required due to design constraints.

[0003] To easily identify the discussion of any particular element or operation, the most significant digit(s) of a reference number refers to the number of the figure in which that element is first introduced. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 is a simplified block diagram of a digital phase-locked loop (DPLL) used in certain electronic devices. [Figure 2] 1 is a block diagram illustrating a duty cycle adjustment circuit within a phase-locked loop (PLL) according to one embodiment. [Figure 3] FIG. 1 is a circuit diagram illustrating adjustment logic and a level shifter according to one embodiment. [Figure 4] FIG. 1 is a circuit diagram illustrating comparison logic according to one embodiment. [Figure 5] 1 illustrates a method for calibrating the duty cycle of a PLL according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0005] The following description sets forth numerous specific details, such as examples of particular systems, components, methods, etc., to provide a better understanding of various embodiments of circuits configured to calibrate duty cycles within phase-locked loops (PLLs) described herein. Such PLLs may be used in Internet of Things (IoT) applications or in any number of other applications, such as home automation and security. However, it will be apparent to those skilled in the art that at least some embodiments may be practiced without these specific details. In other instances, well-known components, elements, or methods are not described in detail or are presented in simple block diagram form to avoid unnecessarily obscuring the subject matter described herein. Therefore, the specific details described below are merely exemplary. Particular implementations may vary from these example details and still be considered to be within the spirit and scope of the present embodiments.

[0006] In the description, references to "an embodiment," "one embodiment," "exemplary embodiment," "some embodiments," and "various embodiments" mean that the particular feature, structure, step, act, or characteristic described in connection with the embodiment(s) is / are included in at least one embodiment. Moreover, the appearances of the phrases "an embodiment," "one embodiment," "exemplary embodiment," "some embodiments," and "various embodiments" in various places in the description do not necessarily all refer to the same embodiments.

[0007] The description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show illustrative examples in accordance with exemplary embodiments. These embodiments, which may also be referred to herein as "examples," are described in sufficient detail to enable one of ordinary skill in the art to practice embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the spirit and scope of the claimed subject matter. It is understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable one of ordinary skill in the art to practice, make, and / or use the subject matter.

[0008] Techniques for calibrating phase-locked loop (PLL) duty cycles are described. In many PLL circuit applications, such as Internet of Things (IoT) applications, designers strive to generate PLL output duty cycles as close as possible to approximately 50%. Maintaining the duty cycle can enable precise timing and frequency control to be maintained, ensuring equal high and low periods of the clock signal, which can result in reliable data transmission and synchronization across devices. Particularly in IoT devices and other applications, including battery-powered devices, maintaining a 50% duty cycle helps minimize power consumption.

[0009] Traditional methods for achieving a clock with a 50% duty cycle include designing a PLL at twice the target frequency and using a flip-flop-based divider to divide the frequency by two and ensure equal high and low periods of the output clock signal. However, using a flip-flop-based divider has a large power impact due to dynamic power used during frequent switching and static power due to leakage current of the flip-flops that form the divider.

[0010] Aspects and embodiments of the present disclosure introduce a power-efficient circuit for calibrating a PLL duty cycle, referred to herein as a duty cycle adjustment circuit, which enables control of the duty cycle toward 50% or other target duty cycle without the inefficient and power-hungry approach of doubling the frequency at which the PLL operates. In various embodiments, the duty cycle adjustment circuit includes comparison logic and adjustment logic. The comparison logic compares the duty cycle of the signal output by the PLL to the target duty cycle. The adjustment logic adjusts the duty cycle of the signal output by the PLL based on the output by the comparison logic. The adjustment logic may adjust the duty cycle by modifying a bias voltage introduced into the signal output by the PLL. In some embodiments, a level shifter receives a first signal (e.g., a first clock) having a first duty cycle from an oscillator and level-shifts the first signal to a second signal having a second duty cycle. The second duty cycle may be compared to the target duty cycle by the comparison logic, which generates a difference value. The adjustment logic may use the difference value to adjust a second duty cycle of a second signal generated by the level shifter.

[0011] 1 is a simplified block diagram of a digital phase-locked loop (DPLL) 100 used in a particular electronic device. The DPLL 100 may include a phase detector (PD) and time-to-digital converter (TDC) 110, a digital loop filter (DLF) 120, an oscillator 130, a duty cycle adjustment circuit 140, and a divider 150 (e.g., an N-divider), which are generally coupled together in a loop as shown. In this type of DPLL 100, the PD (of the PD and TDC 110) is configured to detect the phase and frequency of an input reference clock (REFCLCK) and a feedback clock (FBCLK). Furthermore, in the DPLL 100, the PD and the TDC of the TDC 110 are configured to determine a time difference (e.g., a phase error) between a reference frequency (Fref) of the input reference clock and a feedback frequency (Ffb) of the feedback clock.

[0012] The TDC of the PD and TDC 110 is designed to generate a multi-bit code that digitally encodes the time difference (e.g., quantifies the phase error) and trigger the oscillator 130 to adjust the output frequency (Fout) of the alternating current (AC) output signal of the DPLL 100. In some embodiments, the oscillator 130 is a digital oscillator (DCO). The DPLL's oscillator 130 is generally implemented as a code-to-frequency circuit, such that for each input code (e.g., set of digital bits), there is a unique output frequency of the oscillator 130. The DLF 120, coupled between the TDC and the oscillator 130, is configured to digitally filter the multi-bit code to ensure accurate delivery of individual bits of the multi-bit code to the oscillator 130.

[0013] In at least some embodiments, duty cycle adjustment circuit 140 monitors and adjusts the duty cycle of the oscillating signal generated by oscillator 130. To monitor the duty cycle, duty cycle adjustment circuit 140 may compare the duty cycle to a target duty cycle. If the duty cycle differs from the target duty cycle, duty cycle adjustment circuit 140 may change or modify the duty cycle to be as close as possible to the target duty cycle, for example, in a feedback control loop, as described in further detail with reference to FIGS. 2-5.

[0014] In various applications, where low cost, low power, a smaller board of materials (BOM), and smaller size are highly desirable, DPLL 100 may be used in battery-powered consumer electronics, low-power wireless sensors, home automation systems, remote controls, and automotive memory management units (MCUs). DLF 120 is typically implemented as an on-chip integrated loop filter to further keep the design smaller than analog filters. Divider 150 divides the output frequency of the AC output signal by an integer value (N) to generate a feedback clock that feeds into PD and TDC 110. In some embodiments, divider 150 can be eliminated, or the frequency division can be reduced by a factor of two when implementing duty cycle adjustment circuit 140. In this way, DPLL 100 need not be designed at twice the frequency, to then use divider 150 (or a different divider) to adjust the frequency to the original frequency with an adjusted duty cycle. Therefore, DPLL 100 is designed to operate in a feedback loop in which the time difference between the input reference clock and the feedback clock is minimized until it "locks" to the frequency and phase of the input reference clock.

[0015] In many applications of DPLLs, the time required for the oscillator 130 to lock onto the frequency / phase of the reference clock is referred to as the locking time. For the oscillator 130 to finally achieve this lock, the DPLL 100 typically undergoes many iterations through the loop of the DPLL 100.

[0016] FIG. 2 is a block diagram illustrating a duty cycle adjustment circuit 200 within a phase-locked loop (PLL) according to one embodiment. The circuit 200 may be one embodiment of the duty cycle adjustment circuit 140. In various embodiments, the circuit 200 includes an oscillator 130 that generates an oscillating signal (e.g., an oscillator clock) that is sent to a level shifter 204. In one embodiment, the oscillator 130 may be a ring oscillator. The oscillating signal may be a first clock signal. The first clock signal may be sensitive to variations in process, voltage, or temperature (PVT). PVT variations may occur due to factors such as manufacturing defects (e.g., semiconductor dopant concentration, oxide thickness, etc.), power supply variations, or temperature sensitivity. The first clock signal generated by the oscillator 130 may have a first duty cycle that is also sensitive to PVT variations. Unless otherwise specified, duty cycles in this disclosure are referred to as a percentage (e.g., 52%), meaning the percentage of the duty cycle that is toggled high. For example, a clock with a 75% duty cycle means that the high duty cycle is 75% and the low duty cycle is 25%.

[0017] In some embodiments, the first clock signal is transmitted to a level shifter 204. The level shifter 204 may include one or more amplifiers and a feedback resistor. The level shifter 204 may adjust characteristics of the first clock signal toward desired characteristics. For example, the level shifter may adjust one or more of a first duty cycle and a voltage level of the first clock signal. In some embodiments, the level shifter 204 may be said to generate a second clock signal (e.g., a second oscillating signal) by adjusting characteristics of the first duty cycle toward desired characteristics. The level shifter 204 may adjust characteristics of the first duty cycle by receiving a bias voltage from the adjustment logic 202. In some embodiments, the adjustment logic 202 may include a bias voltage generator. The bias voltage generator may generate a bias voltage that causes the level shifter 204 to adjust the first clock signal toward desired characteristics. The bias voltage generator is described in further detail below.

[0018] The bias voltage generator may generate a bias voltage based on the difference value provided by the comparison logic 206. The comparison logic 206 receives a second clock signal (e.g., the adjusted first clock signal) from the level shifter 204 and compares a second duty cycle of the second clock signal with a target duty cycle. The target duty cycle may be expressed by a reference voltage (e.g., a direct current (DC) voltage). In some embodiments, the reference voltage may be a portion of a supply voltage corresponding to the target duty cycle. For example, if the target duty cycle is 50%, the reference voltage is half (or substantially half) of the supply voltage. If the target duty cycle is 75%, the reference voltage is three-quarters of the supply voltage.

[0019] The comparison logic 206 may compare the second duty cycle of the second clock signal with the target duty cycle by converting the second duty cycle to a direct current voltage or a signal that resembles a DC voltage (e.g., with negligible alternating current (AC) or noise). The comparison logic 206 may convert the second duty cycle to a first voltage by passing the second clock signal through a low-pass filter (LPF). The first voltage may be a fraction of a supply voltage corresponding to the second duty cycle, just as the reference voltage is a fraction of a supply voltage corresponding to the target duty cycle. Once the second duty cycle is converted to the first voltage, the first voltage and the reference voltage are sent to a comparator.

[0020] 3 is a circuit diagram 300 illustrating the adjustment logic 202 and the level shifter 204 according to one embodiment. The level shifter 204 may be used to convert a first clock signal (e.g., an input signal) having a first amplitude received from an upstream oscillator to a second clock signal (e.g., an output signal) having a second amplitude. The second clock signal is then transmitted to downstream circuitry, such as the comparison logic 206. In some embodiments, the level shifter 204 may be an amplifier-based level shifter that uses a feedback resistor to set the gain and other operating characteristics of the amplifier. In these embodiments, the level shifter 204 may include an amplifier 302 and a feedback resistor 304. A capacitor 306 may be coupled to the input of the level shifter 204. The capacitor 306 may help prevent the DC bias of the upstream oscillator (e.g., oscillator 130) from being reached or exceeded by the amplifier 302.

[0021] When level-shifting a clock signal from a first amplitude to a second amplitude, the duty cycle of the clock signal may be inadvertently changed in several ways. First, the level shifter may be coupled to a capacitor to form a resistor-capacitor (RC) circuit. For example, as shown, the amplifier 302, feedback resistor 304, and capacitor 306 may be coupled together to form an RC circuit. In this manner, the level-shifted clock signal generated by the level shifter 204 may have a different frequency than the original clock signal received by the level shifter 204. The change in frequency may change the duty cycle of the clock signal.

[0022] Second, the clock signal may be characterized as being "high" or "low." Generally, when a predetermined voltage threshold is met, the clock signal is high (e.g., enabled or on), and when the predetermined voltage threshold is not met, the clock signal is low (e.g., disabled or off). Thus, the percentage of the clock's duty cycle that is high can be unintentionally (or intentionally) modified depending on whether the predetermined voltage threshold is (i) before the level shift and (ii) after the level shift.

[0023] Third, a level shifter may introduce different delays on the rising edge (e.g., when the clock goes from low to high) and the falling edge (e.g., when the clock goes from high to low) of a clock signal. These delays can be caused by factors such as the difference in the supply voltage and output of the level shifter, the inherent capacitance of the level shifter, and the time required to level shift from one voltage level to another. These delays can affect the rising and falling edges differently and also affect the duty cycle of the level-shifted clock signal.

[0024] The duty cycle of the level-shifted clock signal may be affected by any of the examples above, which are not exhaustive. Instead, the level shifter may affect the duty cycle of the level-shifted clock signal in a variety of ways, including the three examples above.

[0025] In some embodiments, it is desirable for the duty cycle of a clock signal to be modified (e.g., changed) by a level shifter. For example, the clock signal may be generated by an oscillator (e.g., a ring oscillator) that is vulnerable to some PVT variations. The duty cycle of this type of clock signal may not be identical or substantially similar to the target duty cycle. In these embodiments, it is desirable to have the ability to intentionally modify the duty cycle to be identical or substantially similar to the target duty cycle.

[0026] In the illustrated example, the level shifter 204 level-shifts a first clock signal (e.g., an input signal) having a first frequency and a first duty cycle to a second clock signal (e.g., an output signal) having a second frequency and a second duty cycle. The capacitor 306 and the level shifter 204 combine to form an RC circuit, causing the second frequency to differ from the first frequency. After level-shifting the first clock signal to the second clock signal, the second duty cycle may not be identical to or substantially similar to the target duty cycle. This may be caused by either (i) a PVT change caused by an upstream oscillator (e.g., oscillator 130) or (ii) a transition from the first clock signal to the second clock signal.

[0027] In various embodiments, the adjustment logic 202 is coupled to the level shifter 204 and is designed to adjust the second duty cycle of the second clock cycle based on a difference between the second duty cycle and the target duty cycle. This difference may be represented by a difference value. In some embodiments, the difference value may be based on the output of the comparison logic 206. In other embodiments, the comparison logic 206 may output the difference value. The comparison logic 206 is described in further detail below with reference to FIG. 4.

[0028] In some embodiments, the adjustment logic 202 includes a low-power bias generator 308 configured to generate a bias voltage. In some embodiments, the feedback resistor 304 is a potentiometer (e.g., a trimmer potentiometer) that is tapped at positions along various resistance components, thus allowing the resistance of the feedback resistor to be adjusted. In at least some embodiments, the bias voltage generated by the low-power bias generator 308 is provided to the level shifter 204 at a tap position on the feedback resistor 304. The tap position may be adjusted based on the difference value. For example, the low-power bias generator 308 may be coupled to a wiper of a potentiometer. In other embodiments, the feedback resistor 304 may be adjusted based on instructions from a controller (e.g., a microcontroller) based on the difference value. The potentiometer may be iteratively adjusted (e.g., adjusted multiple times) until the second duty cycle (from the output of the comparison logic 206) is the same as or similar to the target duty cycle. Notwithstanding the above description of a potentiometer, any embodiment capable of coupling a low power bias generator 308 to a feedback resistor 304 at an adjustable tap position may be used.

[0029] In some embodiments, the low-power bias generator 308 may generate and / or adjust the bias voltage based on the difference value. For example, the bias voltage may be increased or decreased based on the difference value. In some embodiments, a controller or other logic may increase or decrease the bias voltage based on the difference value. The low-power bias generator 308 may iteratively increase or decrease the bias voltage until the second duty cycle is the same as or similar to the target duty cycle.

[0030] In some embodiments, a combination of (i) adjusting the tap position where the bias voltage is introduced to the feedback resistor 304 and (ii) adjusting the bias voltage based on the difference value may be used.

[0031] 4 is a circuit diagram illustrating comparison logic 206 according to one embodiment. In at least some embodiments, comparison logic 206 includes a reference voltage source 402. Reference voltage source 402 may receive a supply voltage of the circuit and, when compared to the supply voltage, may generate a reference voltage associated with (e.g., corresponding to) the target duty cycle. In other words, the reference voltage may be a portion of the supply voltage that is proportional to the target duty cycle. For example, if the target duty cycle is 50%, reference voltage source 402 generates a reference voltage that is half the supply voltage. As another example, if the target duty cycle is 75%, reference voltage source 402 generates a reference voltage that is ¾ the supply voltage.

[0032] In various embodiments, the comparison logic 206 also includes a low-pass filter (LPF) 404. The LPF 404 may receive an oscillating signal from an upstream circuit and output a first voltage. In some embodiments, the oscillating signal received by the LPF 404 is the second clock signal described above with respect to FIGS. 2-3. In response to receiving the second clock signal, the LPF 404 may be designed such that, when compared to a supply voltage, the first voltage corresponds to the second duty cycle of the second clock signal. In other words, the first voltage may be a fraction of the supply voltage proportional to the second duty cycle. For example, if the second duty cycle is 25%, the first voltage is ¼ of the supply voltage. As another example, if the second duty cycle is 50%, the first voltage is half the supply voltage.

[0033] In some embodiments, once the first voltage is generated by passing the second clock signal through LPF 404, the reference voltage and the first voltage are compared in comparator 408. Comparator 408 determines whether the first voltage is (i) greater than the reference voltage, (ii) less than the reference voltage, or (iii) substantially equal to the reference voltage. In some embodiments, to be (iii) substantially equal to the reference voltage, comparator 408 may determine that the first voltage is within a target range of voltages around the reference voltage. In these embodiments, comparator 408 may include a hysteresis comparator or a Schmitt trigger. A hysteresis comparator may include a gap near the comparator threshold to provide hysteresis, which prevents fast switching of the output due to changes in the input of the hysteresis comparator. For example, if the reference voltage is 50% of the supply voltage and the first voltage is greater than or equal to 48% of the supply voltage and less than or equal to 52% of the supply voltage, the comparator 408 may determine that the first voltage is substantially equal to the reference voltage. This, in turn, indicates that the target duty cycle is 50% and the second duty cycle of the second clock is between 48 and 52%. This example assumes that the error tolerance of the second duty cycle is within 2% of the target duty cycle. However, the error tolerance of the second duty cycle may be set to a different value, such as 1%, 0.5%, or 5%, depending on the requirements of the PLL.

[0034] If the comparator 408 determines that the first voltage is not substantially equal to the reference voltage, a difference value may be calculated based on the digital output 208. The digital output 208 represents the difference between the first voltage and the reference voltage, and thus the difference between the second duty cycle and the target duty cycle. The comparator 408 may output the digital output 208. The digital output 208 may be a difference value. The difference value may be transmitted from the comparator 408 to the adjustment logic 202. The adjustment logic 202 may include a controller (e.g., a microcontroller) that receives the difference value and adjusts the second duty cycle of the second clock signal based on the difference value.

[0035] In some embodiments, the comparator 408 is a low-offset comparator having a first input terminal 410a and a second input terminal 410b. Low-offset comparators are generally designed to have a very small input offset voltage, typically in the microvolt range, allowing them to accurately compare very close voltages. This differs from regular comparators, which have a higher input offset voltage and may be less accurate at detecting small differences between input voltages. The low-offset comparator 408 may be particularly useful in applications requiring high precision, such as PLLs.

[0036] In at least some embodiments, the comparison logic 206 further includes a switching circuit 406 that receives the reference voltage from the reference voltage source 402 and the first voltage from the LPF 404. The comparison logic 206 includes a switching circuit 406 that may alternately switch the reference voltage and the first voltage between a first input terminal 410a and a second input terminal 410b, where the switching circuit 406 may provide, for example, offset cancellation capabilities to the comparison logic 206. The switching circuit 406 is coupled to the input terminals 410a, 410b and may reduce noise and improve the accuracy and overall resolution of the voltage comparison by the comparator 408. For example, the switching circuit 406 may reset or correct any voltage drift or voltage surge. Each time the input of the switching circuit 406 switches between the first voltage and the reference voltage, the digital output 208 may be inverted. This inversion may be accounted for by a controller receiving the digital output 208. For example, the controller may be a programmed processor, central processing unit (CPU), graphics processing unit (GPU), microcontroller, or other logic that accounts for the inversion and also uses an output voltage with an optional regulated duty cycle. In some embodiments, this type of controller or other circuitry that receives an output voltage with a regulated duty cycle generates a stable clock from a less stable signal. Other applications for DPLL 100 include, but are not limited to, frequency synthesis, data recovery, jitter reduction, modulation and demodulation of other signals, and other frequency control and signal generation applications.

[0037] Figure 5 illustrates a method 500 for calibrating the duty cycle of a signal in a PLL according to one embodiment. Method 500 may be performed by circuit 200 of Figure 2 in conjunction with the accompanying description of Figures 3-4. Unless expressly disclosed as requiring such a step, operations do not have to be performed in any particular order.

[0038] At operation 502, the method 500 includes generating, by the oscillator 130, an oscillating clock having a first duty cycle.

[0039] At operation 504 , the method 500 further includes receiving the oscillating clock by the amplifier 302 of the level shifter 204 .

[0040] At operation 506, the method 500 further includes outputting, by the amplifier 302 of the level shifter 204, a level-shifted clock having a second duty cycle.

[0041] At operation 508 , the method 500 further includes receiving the level-shifted clock by the comparison logic 206 .

[0042] At operation 510, the method 500 further includes generating, by the comparison logic 206, a difference value based on a comparison of the second duty cycle and the target duty cycle.

[0043] At operation 512, the method 500 further includes adjusting, by the adjustment logic 202, the second duty cycle produced by the amplifier toward the target duty cycle.

[0044] Various embodiments of calibrating the duty cycle of a signal in a PLL described herein may include various operations. These operations may be performed and / or controlled by hardware components, digital hardware and / or firmware, and / or combinations thereof. As used herein, the term "coupled to" may mean directly connected or indirectly connected through one or more intervening components. Any signals provided through buses on various dies may be time-multiplexed with other signals and provided through buses on one or more common dies. Additionally, interconnections between components or blocks of a circuit may be depicted as buses or as single signal lines. Each of the buses may alternatively be one or more single signal lines, and each single signal line may alternatively be a bus.

[0045] Certain embodiments may be implemented by firmware instructions stored on a non-transitory computer-readable medium, such as, for example, volatile and / or non-volatile memory. These instructions may be used to program and / or configure one or more devices including a processor (e.g., CPU) or equivalent thereof (e.g., processing core, processing engine, microcontroller, etc.), such that, when executed by the processor or equivalent thereof, the instructions cause the device to perform the described operations for the USB-C mode transition architecture described herein. Non-transitory computer-readable storage media may include, but are not limited to, electromagnetic storage media, read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or other media of any now known or later developed non-transitory type suitable for storing information.

[0046] Although the operations of the circuits and blocks herein are illustrated and described in a particular order, in some embodiments, the order of operations of each circuit / block may be changed such that certain operations may be performed in reverse order or such that certain operations may be performed at least partially simultaneously and / or in parallel with other operations. In other embodiments, instructions or sub-operations of different operations may be performed in an intermittent and / or alternating manner.

[0047] In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be apparent that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. An amplifier that receives an oscillating clock having a first duty cycle and outputs a level-shifted clock having a second duty cycle, The adjustment logic coupled to the amplifier, A comparison logic coupled between the output of the amplifier and the adjustment logic, A circuit comprising, The comparison logic generates a difference value based on the difference between the second duty cycle and the target duty cycle. The adjustment logic adjusts the second duty cycle generated by the amplifier based on the difference value. The comparison logic includes a low-pass filter (LPF), which receives the level-shifted clock and generates a first voltage proportional to the second duty cycle. The comparison logic compares the first voltage with a reference voltage associated with the target duty cycle. circuit.

2. The first voltage generated by the LPF is a first portion of the supply voltage, and the first portion corresponds to the second duty cycle. The circuit according to claim 1.

3. The aforementioned comparison logic is, A low-offset comparator including a first input terminal and a second input terminal, A switching circuit coupled between the LPF and the low-offset comparator, Furthermore, The low-offset comparator compares the voltages of the first input terminal and the second input terminal, The switching circuit is configured to alternately switch the first voltage and the reference voltage between the first input terminal and the second input terminal. The circuit according to claim 1.

4. The aforementioned target duty cycle is 48 to 52 percent. The circuit according to claim 1.

5. The circuit further comprises a feedback resistor coupled between the input and output of the amplifier, the feedback resistor being tapped to receive a bias voltage, The adjustment logic is configured to generate the bias voltage based on the difference value. The circuit according to claim 1.

6. The circuit further comprises a feedback resistor coupled between the input and output of the amplifier, the feedback resistor being tapped to receive a bias voltage, The position where the feedback resistor is tapped is adjusted based on the difference value. The circuit according to claim 1.

7. An oscillator that generates an oscillating clock having a first duty cycle, An amplifier coupled to the oscillator, the amplifier receiving the oscillation clock and outputting a level-shifted clock having a second duty cycle, The adjustment logic coupled to the amplifier, A comparison logic coupled between the output of the amplifier and the adjustment logic, A phase-locked loop (PLL) comprising, The comparison logic generates a difference value based on the difference between the second duty cycle and the target duty cycle. The adjustment logic adjusts the second duty cycle generated by the amplifier based on the difference value. The comparison logic includes a low-pass filter (LPF), which receives the level-shifted clock and generates a first voltage proportional to the second duty cycle. The comparison logic compares the first voltage with a reference voltage associated with the target duty cycle. PLL.

8. The first voltage generated by the LPF is a first portion of the supply voltage, and the first portion corresponds to the second duty cycle. The PLL according to claim 7.

9. The aforementioned comparison logic is, A low-offset comparator including a first input terminal and a second input terminal, A switching circuit coupled between the LPF and the low-offset comparator, Furthermore, The low-offset comparator compares the voltages of the first input terminal and the second input terminal, The switching circuit is configured to alternately switch the first voltage and the reference voltage between the first input terminal and the second input terminal. The PLL according to claim 7.

10. The aforementioned target duty cycle is 48 to 52 percent. The PLL according to claim 7.

11. The PLL further comprises a feedback resistor coupled between the input and output of the amplifier, the feedback resistor being tapped to receive a bias voltage, The adjustment logic is configured to generate the bias voltage based on the difference value. The PLL according to claim 7.

12. The PLL further comprises a feedback resistor coupled between the input and output of the amplifier, the feedback resistor being tapped to receive a bias voltage, The position where the feedback resistor is tapped is adjusted based on the difference value. The PLL according to claim 7.

13. The oscillator is a ring oscillator. The PLL according to claim 7.

14. A method for operating a phase-locked loop (PLL) circuit comprising an amplifier, an oscillator coupled to the amplifier, adjustment logic coupled to the amplifier, and comparison logic coupled between the amplifier and the adjustment logic, wherein the method for operating the PLL circuit is: The steps include generating an oscillator clock having a first duty cycle using the oscillator, The steps include receiving the aforementioned oscillation clock with the amplifier, The steps include outputting a level-shifted clock having a second duty cycle through the amplifier, The steps include receiving the level-shifted clock using the comparison logic, The steps include generating a difference value based on a comparison between the second duty cycle and the target duty cycle using the comparison logic, The steps include adjusting the second duty cycle generated by the amplifier toward the target duty cycle using the adjustment logic, Includes, The step of generating the difference value is: The steps include inputting the level-shifted clock to a low-pass filter (LPF), The LPF outputs a first voltage proportional to the second duty cycle, A step of comparing the first voltage with a reference voltage associated with the target duty cycle, including, method.

15. The comparison logic further comprises a switching circuit and a low-offset comparator including a first input terminal and a second input terminal. The step of comparing the first voltage with the reference voltage is: The steps include comparing the voltages of the first input terminal and the second input terminal using the low-offset comparator, The switching circuit receives the first voltage and the reference voltage, The switching circuit alternately switches the first voltage and the reference voltage between the first input terminal and the second input terminal, including, The method according to claim 14.

16. The aforementioned target duty cycle is 48 to 52 percent. The method according to claim 14.

17. The PLL circuit further comprises a feedback resistor coupled between the input and output of the amplifier, the feedback resistor being tapped to receive a bias voltage, The step of adjusting the second duty cycle to the target duty cycle includes the step of generating the bias voltage based on the difference value using the adjustment logic. The method according to claim 14.

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