Imaging device and driving method for imaging device

Abstract

To provide an imaging device capable of high speed operation.SOLUTION: In a first mode, an analog-digital conversion part respectively generates first pixel data and second pixel data by performing analog-digital conversion of pixel signals from a first output line and a second output line, a first memory stores the first pixel data, a second memory stores the second pixel data, a scan circuit causes the first memory to output the first pixel data and causes the second memory to output the second pixel data. In a second mode, the analog-digital conversion part respectively generates third pixel data and fourth pixel data by performing analog-digital conversion of pixel signals from the first output line and the second output line, the first memory stores the third pixel data and the fourth pixel data, the scan circuit causes the first memory to output the third pixel data and the fourth pixel data.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device and a method for driving an imaging device. [Background technology]

[0002] Patent Document 1 proposes an imaging device that can appropriately select a frame readout speed and gradation fineness depending on the application or situation. This imaging device includes a plurality of pixels that convert the amount of incident light into an analog electrical signal, an analog-to-digital converter (ADC) that converts the analog signal from the pixels into a digital signal, and an output control circuit that outputs the digital signal converted by the ADC to an output line. The ADC is configured to be able to switch the number of bits of the converted digital signal between at least two predetermined number of bits. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-333316 Summary of the Invention [Problem to be solved by the invention]

[0004] In an imaging device capable of switching the number of bits of an output digital signal as in Patent Document 1, there are cases where even faster operation is required.

[0005] An object of the present invention is to provide an imaging device capable of high-speed operation and a method for driving the imaging device. [Means for solving the problem]

[0006] According to one disclosure of the present specification, a digital video signal processing device includes a plurality of pixels each outputting a pixel signal, first and second output lines connected to corresponding pixels, an analog-to-digital converter that performs analog-to-digital conversion on the pixel signals to generate pixel data, a first memory and a second memory that respectively store the pixel data, and a scanning circuit that performs scanning to output the pixel data from the first memory and the second memory, wherein in a first mode, the analog-to-digital converter performs analog-to-digital conversion on the pixel signals from the first output line to generate first pixel data, and analog-to-digital conversion on the pixel signals from the second output line to generate second pixel data, and the first memory the second memory stores the first pixel data, the second memory stores the second pixel data, the scanning circuit causes the first pixel data to be output from the first memory and the second pixel data to be output from the second memory, in a second mode the analog-to-digital conversion unit analog-to-digital converts pixel signals from the first output line to generate third pixel data and analog-to-digital converts pixel signals from the second output line to generate fourth pixel data, the first memory stores the third pixel data and the fourth pixel data, and the scanning circuit causes the first memory to output the third pixel data and the fourth pixel data.

[0007] According to one disclosure of the present specification, there is provided a method for driving an imaging device having a plurality of pixels each outputting a pixel signal, first and second output lines to which corresponding pixels are respectively connected, and first and second memories each holding pixel data generated by analog-to-digital conversion of the pixel signals, the method comprising: in a first mode, performing analog-to-digital conversion on the pixel signals from the first output line to generate first pixel data and storing the first memory, and performing analog-to-digital conversion on the pixel signals from the second output line to generate second pixel data and storing the second memory; and outputting the first pixel data from the first memory and outputting the second pixel data from the second memory; and in a second mode, performing analog-to-digital conversion on the pixel signals from the first output line to generate third pixel data and storing the third memory, and performing analog-to-digital conversion on the pixel signals from the second output line to generate fourth pixel data and storing the first memory; and outputting the third pixel data and the fourth pixel data from the first memory. [Effects of the Invention]

[0008] According to the present invention, an imaging device capable of high-speed operation and a method for driving an imaging device are provided. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram schematically illustrating the overall configuration of an imaging device according to a first embodiment. [Figure 2] 4 is a timing chart showing an example of the operation of the imaging device according to the first embodiment. [Figure 3] 2 is a circuit diagram showing an example of an equivalent circuit of the signal processing circuit according to the first embodiment. FIG. [Figure 4] 3 is a schematic diagram showing an example of storing pixel data in an S memory group according to the first embodiment; FIG. [Figure 5] 4 is a timing chart showing an example of the operation of the imaging device according to the first embodiment. [Figure 6]3 is a circuit diagram showing a configuration example of a writing unit of an S memory group according to the first embodiment; FIG. [Figure 7] 3 is a circuit diagram showing a configuration example of a readout unit of an S memory group according to the first embodiment. FIG. [Figure 8] 10 is a timing chart showing an example of the operation of a read unit of the S memory group according to the first embodiment. [Figure 9] FIG. 10 is a block diagram schematically illustrating the overall configuration of an imaging device according to a second embodiment. [Figure 10] FIG. 10 is a circuit diagram showing an example of an equivalent circuit of a signal processing circuit according to a second embodiment. [Figure 11] FIG. 11 is a schematic diagram showing an example of storing pixel data in an S memory group according to the second embodiment. [Figure 12] 10 is a timing chart showing an example of the operation of the imaging device according to the second embodiment. [Figure 13] 13 is a schematic diagram showing an example of storing pixel data in an S memory group and an N memory group according to the third embodiment. FIG. [Figure 14] 10 is a timing chart showing an example of the operation of the imaging device according to the third embodiment. [Figure 15] FIG. 10 is a block diagram schematically showing the overall configuration of an imaging device according to a fourth embodiment. [Figure 16] FIG. 10 is a block diagram schematically showing the overall configuration of an imaging device according to a fifth embodiment. [Figure 17] FIG. 10 is a block diagram schematically showing the overall configuration of an imaging device according to a sixth embodiment. [Figure 18] FIG. 13 is a block diagram showing a schematic configuration of a device according to a seventh embodiment. [Figure 19] FIG. 13 is a block diagram showing a schematic configuration of a device according to an eighth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same or corresponding elements in multiple drawings are designated by common reference numerals, and their description may be omitted or simplified.

[0011] [First embodiment] An imaging device 100 according to the first embodiment will be described with reference to FIGS. 1 to 8(b). FIG. 1 is a block diagram schematically illustrating the overall configuration of the imaging device 100 according to this embodiment. The imaging device 100 includes a pixel array 110, a vertical scanning circuit 120, a horizontal scanning circuit 130, a signal processing circuit 140, a counter 160, a reference signal generating circuit 170, a memory group 180, a timing control unit 190, an arithmetic processing circuit 191, and an output unit 192. The imaging device 100 also includes a row control line 112, an output line 113, a reference signal line 171, a count signal line 181, and latch pulse signal lines 182-1 to 182-12. Note that the suffixes "-1" to "-12" at the end of the reference numerals indicate column numbers.

[0012] A plurality of pixels 111 are arranged in the pixel array 110. Each pixel 111 outputs a pixel signal based on an electric charge generated by photoelectrically converting incident light. The plurality of pixels 111 are arranged in a plurality of rows and a plurality of columns. For the sake of simplicity, FIG. 1 illustrates an example of 7 rows and 12 columns of pixels 111, but the number of rows and columns of the pixels 111 is not limited to this.

[0013] In the following description, unless otherwise specified, the pixels 111 are assumed to be pixels that detect light using photoelectric conversion elements, but the configuration of the pixels 111 is not limited to this. For example, the pixels 111 may be radiation detection elements that are sensitive to radiation such as alpha rays, beta rays, gamma rays, and X-rays. The radiation detection elements may include, for example, a scintillator that converts radiation into light and a photoelectric conversion element that detects the converted light. In other words, the imaging device 100 may be a radiation imaging device. In this case, the term "light" in the following description may be appropriately interpreted as "radiation."

[0014] The plurality of output lines 113 are provided corresponding to the plurality of pixel columns, respectively. Each of the plurality of output lines 113 outputs a pixel signal from the pixels 111 in the corresponding column. Note that types of pixel signals include optical signals output by the pixels 111 based on charges generated by photoelectric conversion and noise signals output by the pixels 111 in a reset state. The correspondence between the pixels 111 and the output lines 113 may be, but is not limited to, a configuration in which one output line 113 is arranged corresponding to one column, as shown in FIG. 1 . For example, a configuration in which multiple output lines 113 are arranged corresponding to one column may also be possible. In this case, the number of pixels 111 read out at one time can be increased, thereby improving the frame readout speed.

[0015] The vertical scanning circuit 120 is electrically connected to the plurality of pixels 111 via a plurality of row control lines 112. One row control line 112 is arranged in common to the plurality of pixels 111 in a corresponding row. The vertical scanning circuit 120 supplies control signals to the plurality of row control lines 112 based on control signals supplied from the timing control unit 190. When the control signal supplied to the row control line 112 is activated, the pixel 111 connected to that row control line 112 outputs a pixel signal to the corresponding output line 113. The vertical scanning circuit 120 sequentially activates the control signals of the plurality of row control lines 112, thereby sequentially outputting pixel signals from the plurality of pixels 111 to the output line 113. The vertical scanning circuit 120 may include a shift register or an address decoder.

[0016] The reference signal generation circuit 170 generates a ramp signal. The ramp signal is a reference signal having a signal level that changes monotonically over time. The reference signal generation circuit 170 supplies the ramp signal to each of the multiple signal processing circuits 140 via a reference signal line 171. The reference signal generation circuit 170 starts changing the signal level of the ramp signal based on a control signal supplied from the timing control unit 190.

[0017] Each of the multiple signal processing circuits 140 is electrically connected to a corresponding one of the multiple output lines 113. That is, one signal processing circuit 140 is configured to process a pixel signal output from at least one pixel 111. The processing performed by the signal processing circuit 140 includes analog-to-digital conversion (hereinafter referred to as AD conversion) of the pixel signal.

[0018] The output nodes of the signal processing circuits 140 are electrically connected to the memory group 180 via corresponding latch pulse signal lines 182-1 to 182-12. Each of the signal processing circuits 140 supplies a latch pulse signal to the memory group 180 via a corresponding one of the latch pulse signal lines 182-1 to 182-12. As will be described later, the signal processing circuit 140 outputs a latch pulse signal based on the result of comparing the pixel signal from the pixel 111 with a ramp signal. The latch pulse signal has a predetermined pulse width. In other words, the latch pulse signal is in an active state for a predetermined period. The signal levels of the active and inactive states of the latch pulse signal are set appropriately depending on the downstream circuit.

[0019] The memory group 180 includes an S memory group 180S (first memory area) and an N memory group 180N (second memory area). The S memory group 180S stores S signals (optical data) generated by AD converting optical signals. A write unit MW, indicated by a dashed rectangle in FIG. 1, is a part that writes S signals to the S memory group 180S. The N memory group 180N stores N signals (noise data) generated by AD converting noise signals. As will be described in detail later, the S memory group 180S has a plurality of S memories corresponding to the plurality of signal processing circuits 140, respectively. Furthermore, the N memory group 180N has a plurality of N memories corresponding to the plurality of signal processing circuits 140, respectively.

[0020] The counter 160 supplies a count signal to each of the multiple memories included in the memory group 180 via a count signal line 181. The counter 160 outputs the count signal by counting pulses of a clock signal supplied from the timing control unit 190. The count signal line 181 also includes a multi-bit bus line. In this embodiment, the count signal line 181 includes a 12-bit bus line.

[0021] In the imaging device 100 of this embodiment, the reference signal generating circuit 170, the signal processing circuit 140, and the counter 160 function as an AD conversion unit (analog-to-digital conversion unit).

[0022] Although the imaging device 100 of this embodiment includes one counter 160 and a memory group 180 including a plurality of memories, the number of counters 160 and the number of memories are not particularly limited. For example, the imaging device 100 may include a plurality of counters. In this modification, each of the plurality of counters is electrically connected to a corresponding one of the plurality of signal processing circuits 140. Each of the plurality of counters starts or stops counting in response to a latch pulse signal output from the signal processing circuit 140.

[0023] The horizontal scanning circuit 130 sequentially scans the multiple memories included in the memory group 180, and sequentially transfers the multiple S signals and multiple N signals held in the memory group 180 to the arithmetic processing circuit 191. The horizontal scanning circuit 130 may include a shift register or an address decoder.

[0024] The arithmetic processing circuit 191 performs noise correction to generate a differential signal between the S signal and the N signal. This makes it possible to correct noise such as fixed pattern noise. The arithmetic processing circuit 191 may also perform further processing such as gain multiplication and offset addition. The arithmetic processing circuit 191 outputs the processed signal to the output unit 192. The output unit 192 is an interface that outputs the signal obtained by these processes to the outside of the imaging device 100.

[0025] Next, the operation of the AD conversion unit in the imaging device 100 of Fig. 1 will be described with reference to Fig. 2. Fig. 2 shows a timing chart of each signal when the AD conversion unit converts the pixel signal PIXSIG into a digital signal. Fig. 2 also shows the signal levels of the ramp signal RAMP and the pixel signal PIXSIG. Fig. 2 also shows the pulse timings of the clock signal CLK and the latch pulse signal LATCH. Fig. 2 also shows the value of the count signal COUNT and the value of the 12-bit digital signal DATA held in the memory group 180.

[0026] For simplicity of illustration, the values of the count signal COUNT and the digital signal DATA are expressed in decimal numbers in Fig. 2. However, these signals can actually be expressed in 12-bit Gray code.

[0027] First, at time t0, an AD conversion operation starts. At time t0, the pixel 111 outputs a pixel signal PIXSIG to the output line 113. Also at time t0, the reference signal generation circuit 170 starts changing the signal level of the ramp signal RAMP based on a control signal supplied from the timing control unit 190. After time t0, the signal level of the ramp signal RAMP increases over time. Also at time t0, the counter 160 starts counting pulses of the clock signal CLK. As a result, the value of the count signal COUNT changes from "0" to "1" at time t0. Thereafter, the value of the count signal COUNT increases by 1 with each rising edge of the pulse of the clock signal CLK. Note that at time t0, the signal level of the pixel signal PIXSIG is greater than the signal level of the ramp signal RAMP.

[0028] At time t1, the relationship between the signal level of the pixel signal PIXSIG and the signal level of the ramp signal RAMP is reversed, and the signal level of the ramp signal RAMP becomes greater than the signal level of the signal PIXSIG. This causes the signal processing circuit 140 to transition the latch pulse signal LATCH from an inactive state to an active state. In this embodiment, the inactive state is a low level, and the active state is a high level. At time t2, a predetermined time after time t1, the signal processing circuit 140 transitions the latch pulse signal LATCH from an active state to an inactive state. In this way, the signal level of the latch pulse signal LATCH changes depending on the result of the comparison performed by the signal processing circuit 140.

[0029] When the latch pulse signal LATCH is in an active state, the memory group 180 receives the count signal COUNT supplied to the memory group 180 at that time. Therefore, at time t2, when the signal level of the latch pulse signal LATCH changes from an active state to an inactive state, the memory group 180 retains the count signal COUNT supplied to the memory group 180 at that time. As a result, the memory group 180 retains, as the digital signal DATA, a count value corresponding to the length of the period from time t0, when the signal level of the ramp signal RAMP begins to change, to time t2, when the signal level of the latch pulse signal LATCH transitions to an inactive state. In the example of FIG. 2, the value of the count signal COUNT at time t2 is "867," and therefore the value of the digital signal DATA is "867." This digital signal DATA is pixel data obtained by AD conversion of the pixel signal PIXSIG.

[0030] At time t3, the reference signal generation circuit 170 finishes changing the signal level of the ramp signal RAMP over time. After that, the horizontal scanning circuit 130 sequentially scans the memories of the memory group 180 and sequentially transfers the digital signal DATA stored in the memory group 180 to the arithmetic processing circuit 191.

[0031] Next, the configuration of the signal processing circuit 140 will be described. The signal processing circuit 140 of this embodiment is a circuit that performs part of the AD conversion process. Fig. 3 is a circuit diagram showing an example of an equivalent circuit of the signal processing circuit 140. The signal processing circuit 140 includes a comparator 141 and a pulse generation circuit 142. The pulse generation circuit 142 may include logic circuits such as an AND circuit, a NAND circuit, a NOR circuit, and a latch circuit.

[0032] The pixel signal PIXSIG and ramp signal RAMP shown in FIG. 2 are input to the comparator 141. Based on the result of comparing the pixel signal PIXSIG with the ramp signal RAMP, the comparator 141 outputs an output signal COMP_OUT to the pulse generation circuit 142. The pulse generation circuit 142 outputs a latch pulse signal LATCH having a predetermined pulse width based on the output signal COMP_OUT. The latch pulse signal LATCH is output to latch pulse signal lines 182-1 to 182-12. When the signal level of the ramp signal RAMP becomes higher than the signal level of the pixel signal PIXSIG, the latch pulse signal LATCH transitions from an inactive state to an active state. After a predetermined period has elapsed, the latch pulse signal LATCH returns to an inactive state. In this way, the pulse generation circuit 142 generates a pulse of the latch pulse signal LATCH.

[0033] Next, a method of storing data in the memory group 180 in this embodiment will be described. The imaging device 100 in this embodiment can operate in a first mode and a second mode in which the number of bits of pixel data is reduced compared to the first mode. In this embodiment, the number of bits of pixel data in the first mode is 12 bits, and the number of bits of pixel data in the second mode is 4 bits. In this embodiment, the method of storing data in the S memory group 180S in the memory group 180 differs between the first mode and the second mode.

[0034] 4(a) and 4(b) are schematic diagrams showing examples of storing pixel data in the S memory group 180S. Fig. 4(a) shows an example of storing pixel data in the S memory group 180S in the first mode, and Fig. 4(b) shows an example of storing pixel data in the S memory group 180S in the second mode.

[0035] The S memory group 180S has a plurality of S memories arranged to correspond to each of the plurality of signal processing circuits 140. In the example of FIGS. 4(a) and 4(b), the S memory group 180S is composed of a first S memory 201 to a twelfth S memory 212. FIGS. 4(a) and 4(b) show an example of storing pixel data in the first S memory 201 to the twelfth S memory 212. Each of the first S memory 201 to the twelfth S memory 212 has memory cells for 12 bits. That is, each of the first S memory 201 to the twelfth S memory 212 has a storage capacity of 12 bits. One block among the first S memory 201 to the twelfth S memory 212 schematically shows memory cells for 1 bit. Hatched memory cells indicate memory cells in which pixel data are stored.

[0036] In this embodiment, the multiple output lines 113 are designated as the first to twelfth output lines. In the first mode, pixel data output from the pixels via the first to twelfth output lines are designated as DS1 to DS12, respectively. In the second mode, pixel data output from the pixels via the first to twelfth output lines are designated as DS1A to DS12A, respectively.

[0037] 4(a), in the first mode, 12-bit pixel data for one pixel is stored in one memory. That is, the first S memory 201 to the twelfth S memory 212 store pixel data DS1 to DS12, respectively.

[0038] As shown in Figure 4(b), in the second mode, pixel data for three pixels is stored in one memory. That is, the first S memory 201 stores pixel data DS1A, DS2A, and DS3A for three pixels. The fourth S memory 204 stores pixel data DS4A, DS5A, and DS6A for three pixels. The seventh S memory 207 stores pixel data DS7A, DS8A, and DS9A for three pixels. The tenth S memory 210 stores pixel data DS10A, DS11A, and DS12A for three pixels. Each of the pixel data DS1A to DS12A is 4-bit digital data.

[0039] Dummy data of fixed values such as zero is stored in the second S memory 202, the third S memory 203, the fifth S memory 205, the sixth S memory 206, the eighth S memory 208, the ninth S memory 209, the eleventh S memory 211, and the twelfth S memory 212. Storing dummy data in these S memories suppresses changes in voltage within the memory, thereby reducing power consumption and noise.

[0040] Fig. 5 is a timing chart showing an example of the operation of the imaging device 100 according to this embodiment. Fig. 5 shows the timing of the operation of reading out pixel data stored in the S memory group 180S and transferring it to the arithmetic processing circuit 191. "First mode" in Fig. 5 shows the timing of the operation in the first mode, and "second mode" in Fig. 5 shows the timing of the operation in the second mode.

[0041] In the first mode, the first S memory 201 to the twelfth S memory 212 are scanned in this order, and the pixel data DS1 to DS12 are transferred in this order to the arithmetic processing circuit 191. As shown in Fig. 5, if the time required to transfer one pixel data is Δt, the time required to transfer all of the pixel data DS1 to DS12 is Δt × 12.

[0042] In the second mode, the 1st S memory 201, the 4th S memory 204, the 7th S memory 207, and the 10th S memory 210 are scanned in this order, and pixel data DS1A to DS12A are transferred to the arithmetic processing circuit 191. First, the 1st S memory 201 is read, and pixel data DS1A to DS3A are transferred to the arithmetic processing circuit 191. Next, the 4th S memory 204 is read, and pixel data DS4A to DS6A are transferred to the arithmetic processing circuit 191. Next, the 7th S memory 207 is read, and pixel data DS7A to DS9A are transferred to the arithmetic processing circuit 191. Subsequently, the 10th S memory 210 is read, and pixel data DS10A to DS12A are transferred to the arithmetic processing circuit 191. Other S memories in which dummy data are stored are skipped during scanning, so no dummy data is read. As shown in the "second mode" in Fig. 5, the time required to transfer all of the pixel data DS1 to DS12 is Δt × 4. Therefore, in the second mode, the time required to transfer the pixel data is reduced to one-third compared to the first mode.

[0043] In this embodiment, in the second mode, pixel data is stored in the 1st S memory 201, the 4th S memory 204, the 7th S memory 207, and the 10th S memory 210, but pixel data may also be stored in other memories.

[0044] Next, the configuration of the write unit MW of the S memory group 180S in this embodiment will be described. FIG. 6 is a circuit diagram showing an example of the configuration of the write unit MW of the S memory group 180S. FIG. 6 illustrates the detailed configuration and connection relationship of the write units MW of the first S memory 201, second S memory 202, and third S memory 203 shown in FIG. 4. In the S memory group 180S, the configuration shown in FIG. 6 is repeatedly arranged for every three S memories. Each S memory has 12-bit memory cells m0 to m11. The write unit MW also has switch groups 302, 303, and 304 and switches 305 and 306.

[0045] Each of the memory cells m0 to m11 has a data input terminal and a latch terminal. The count signal COUNT is input to the data input terminal, and the latch pulse signal LATCH is input to the latch terminal. Each of the memory cells m0 to m11 holds the count signal COUNT when the latch pulse signal LATCH changes from an active state to an inactive state.

[0046] The count signal line 181 is a 12-bit bus line consisting of the 0th bit line C0 to the 11th bit line C11, and is connected to the counter 160 in Fig. 1. The counter 160 outputs a signal for each bit of the count signal COUNT to the 0th bit line C0 to the 11th bit line C11.

[0047] A mode switching signal is input to the write unit MW via a mode signal line 301. The mode switching signal is a signal that switches between the first mode and the second mode described with reference to FIGS. 4(a), 4(b), and 5. The mode switching signal may be input from the timing control unit 190 or from outside the imaging device 100. The mode switching signal is a 1-bit signal, and is set, for example, to a low level in the first mode and a high level in the second mode. The mode signal line 301 is connected to a switch group 302, a switch group 303, a switch group 304, a switch 305, and a switch 306. These switches switch their connections depending on the level of the mode switching signal. That is, these switches function as a mode switching unit that switches the connections within the write unit MW between the first mode and the second mode depending on the level of the mode switching signal.

[0048] First, the connections in the first mode will be explained using Fig. 6. When each switch is switched by a mode switching signal, the write unit MW has the following connections in the first mode.

[0049] The 0th bit line C0 to the 11th bit line C11 of the count signal line 181 are connected to the memory cells m0 to m11 of each of the first S memory 201 to the third S memory 203, respectively.

[0050] A latch pulse signal line 182-1 is commonly connected to memory cells m0 to m11 of the first S memory 201. A latch pulse signal line 182-2 is commonly connected to memory cells m0 to m11 of the second S memory 202, and a latch pulse signal line 182-3 is commonly connected to memory cells m0 to m11 of the third S memory 203.

[0051] The connections between the second S memory 202 and the third S memory 203 and the latch pulse signal lines 182-2 and 182-3 are the same in the first mode and the second mode.

[0052] In this connection configuration, in response to a latch pulse signal, a 12-bit count signal for the corresponding column is stored in each of the first S memory 201 to the third S memory 203. That is, pixel data for one pixel is stored in each of the S memories.

[0053] Next, the connection relationships in the second mode will be described. By switching each switch in response to a mode switching signal, the write unit MW is connected as follows in the second mode.

[0054] The connection between the first S memory 201 and the count signal line 181 will be described. Memory cells m0 to m3 are connected to the 0th bit line C0 to the 3rd bit line C3, respectively. Memory cells m4 to m7 are also connected to the 0th bit line C0 to the 3rd bit line C3, respectively. Memory cells m8 to m11 are also connected to the 0th bit line C0 to the 3rd bit line C3.

[0055] The connection between the first S memory 201 and the latch pulse signal line will be described. Memory cells m0 to m3 are connected to a latch pulse signal line 182-1. Memory cells m4 to m7 are connected to a latch pulse signal line 182-2. Memory cells m8 to m11 are connected to a latch pulse signal line 182-3.

[0056] In this connection configuration, in response to the latch pulse signal, 4-bit count signals for three columns are stored in memory cells m0 to m3, memory cells m4 to m7, and memory cells m8 to m11 of the first S memory 201. Since the 4-bit count signal corresponds to pixel data for one pixel, pixel data for three pixels is stored in the first S memory 201.

[0057] Furthermore, a fixed potential node 307 is connected to memory cells m0 to m11 of the second S memory 202 and the third S memory 203. With this configuration, fixed values that are dummy data are stored in memory cells m0 to m11. While an example is shown in Fig. 6 in which the fixed potential node 307 is a ground potential node, the fixed potential node 307 may also be a power supply potential node.

[0058] The configuration for storing fixed values in the memory cells m0 to m11 of the second S memory 202 and the third S memory 203 is not limited to this. For example, the memory cells m0 to m11 may have a reset function for storing a low-level signal or a set function for storing a high-level signal.

[0059] Since the write unit MW of the S memory group 180S is configured as shown in Figure 6, when it is set to the first mode, the operation shown in Figure 4(a) is performed, and when it is set to the second mode, the operation shown in Figure 4(b) is performed.

[0060] In this embodiment, pixel data for one pixel is set to four bits in the second mode, so that pixel data for three pixels is stored in one memory. However, the number of bits of pixel data in the second mode is not limited to this. The number of bits of pixel data in the second mode may be appropriately changed, and the number of pixel data stored in the memory may also be appropriately changed by further changing the configuration of the wiring and switches.

[0061] Next, the configuration of the read section of the S memory group 180S in this embodiment will be described. Figure 7 is a circuit diagram showing an example of the configuration of the read section of the S memory group 180S in this embodiment. Figure 7 illustrates the detailed configuration and connection relationship of the read sections of the first S memory 201, second S memory 202, and third S memory 203 shown in Figure 6. In the S memory group 180S, a plurality of buffers 308 and a plurality of tri-state buffers 309 are arranged so as to correspond to memory cells m0 to m11.

[0062] The output section of each of memory cells m0 to m11 is connected to the input terminal of a corresponding buffer 308. The output terminal of each buffer 308 is connected to the input terminal of a corresponding tri-state buffer 309. The output terminal of each tri-state buffer 309 is connected to the signal line of the corresponding bit among the 12 signal lines that make up output line 311, which outputs a 12-bit signal. Output line 311 transmits signals from m0 to m11 to the arithmetic processing circuit 191.

[0063] The selection signal line 312 is connected to memory cells m0 to m11 of the first S memory 201. The selection signal line 313 is connected to memory cells m0 to m11 of the second S memory 202. The selection signal line 314 is connected to memory cells m0 to m11 of the third S memory 203. The horizontal scanning circuit 130 shown in FIG. 1 outputs selection signals to memory cells m0 to m11 of the corresponding S memories via the selection signal lines 312 to 314. The S memories selected by the selection signals output image data.

[0064] A control signal is input to the readout unit via a buffer control line 310. The buffer control line 310 is connected to each tri-state buffer 309. The tri-state buffer 309 switches between a signal output state and a high impedance state in response to the control signal input via the buffer control line 310. This control signal may be input from the timing control unit 190 or may be input from outside the imaging device 100.

[0065] 8(a) and 8(b) are timing charts showing an example of the operation of the readout section of the S memory group 180S according to this embodiment. To simplify the explanation, FIGS. 8(a) and 8(b) only show the waveforms of the selection signals HS1 to HS6 input to the first S memory 201 to the sixth S memory 206 shown in FIG. 4. When the selection signals HS1 to HS6 are at a high level, the corresponding S memory is selected and pixel data is read out.

[0066] Figure 8(a) shows the waveforms of the selection signals HS1 to HS6 when the first mode is set. As shown in Figure 4(a), when the first mode is set, pixel data is stored in each of the first S memory 201 to the sixth S memory 206. The selection signals HS1 to HS6 sequentially go high, causing pixel data to be sequentially read out from the first S memory 201 to the sixth S memory 206. Furthermore, at the timing when the selection signals HS1 to HS6 go high, the tri-state buffers 309 are controlled to sequentially go into a signal output state.

[0067] FIG. 8(b) shows the waveforms of the selection signals HS1 to HS6 when the second mode is set. As shown in FIG. 4(b), when the second mode is set, pixel data is stored in the first S memory 201 and the fourth S memory 204. Dummy data is stored in the second S memory 202, the third S memory 203, the fifth S memory 205, and the sixth S memory 206. As shown in FIG. 8(b), after the selection signal HS1 goes high, the selection signal HS4 goes high. Meanwhile, the selection signals HS2, HS3, HS5, and HS6 remain low. Therefore, pixel data is sequentially read from the first S memory 201 and the fourth S memory 204. In contrast, no read operation is performed from the second S memory 202, the third S memory 203, the fifth S memory 205, and the sixth S memory 206.

[0068] In this way, the operation of the readout section of the S memory group 180S differs between the first mode and the second mode due to the different selection signals HS1 to HS6. However, as shown in Figure 7, the circuit configuration of the readout section of the S memory group 180S is the same in both the first mode and the second mode, and it is possible to switch the operation by changing the input signal.

[0069] In this embodiment, the S memory group 180S that stores the S signals has been described, but the N memory group 180N that stores the N signals can also be configured and operated in the same manner as the S memory group 180S. Furthermore, the imaging device 100 may also be provided with a memory group that stores noise correction signals obtained by subtracting the N signals from the S signals, and the same configuration and operation as the S memory group 180S can be applied to this memory group.

[0070] In the imaging device 100 of this embodiment, a memory stores pixel data corresponding to one pixel in the first mode, and stores pixel data corresponding to two or more pixels in the second mode. The number of bits of a memory cell in each memory is equal to or greater than the number of bits of pixel data in the first mode. In the examples of Figures 4(a) and 4(b), the number of bits of pixel data in the second mode is a divisor of the number of bits of pixel data in the first mode, but the number of bits of pixel data in the second mode is not limited to this.

[0071] For example, if each memory has 12-bit memory cells, the pixel data in the first mode may be 11 bits. Alternatively, if each memory has 12-bit memory cells, the pixel data in the second mode may be 3 bits, and pixel data for four pixels may be stored in one memory.

[0072] The operation of this embodiment will be outlined below by generalizing the number of memory bits and the number of pixel data bits. When each memory has k-bit (k is an integer equal to or greater than 2) memory cells, the pixel data in the first mode is m-bit (m is an integer equal to or greater than 2 and equal to or less than k). In the second mode, pixel data for two or more pixels is stored in one memory, so the pixel data in the second mode is n-bit (n is an integer equal to or greater than 1 and equal to or less than m / 2).

[0073] In the first mode, the pixel signal from the first output line is AD converted into m-bit first pixel data and stored in the first memory. Also, the pixel signal from the second output line is AD converted into m-bit second pixel data and stored in the second memory. Then, the first pixel data is read from the first memory, and the second pixel data is read from the second memory.

[0074] In the second mode, the pixel signal from the first output line is AD converted to n-bit third pixel data and stored in the first memory. Also, the pixel signal from the second output line is AD converted to n-bit fourth pixel data and stored in the first memory. Then, the third pixel data and the fourth pixel data are read out from the first memory. The third pixel data and the fourth pixel data can be read out simultaneously.

[0075] In this way, by storing pixel data corresponding to one pixel in a memory in the first mode and storing multiple pixel data in a memory in the second mode, it is possible to read multiple pixel data by performing a read operation on a single memory. This makes it possible to speed up the read operation and improve the frame read speed. Therefore, according to this embodiment, an imaging device capable of high-speed operation and a driving method for an imaging device are provided.

[0076] This embodiment can also be applied to an imaging device that counts the number of incident quanta by determining the incidence of quanta such as photons or electrons from pixel data. In such an imaging device, setting the second mode to improve the frame readout speed can shorten the shooting time and reduce blur.

[0077] Another factor that can improve the readout speed in the imaging device of this embodiment is described below. One horizontal scanning period is the time from when a pixel row is activated to when the next pixel row is activated among multiple pixels 111 arranged in multiple rows and columns. When AD-converting pixel signals and writing them to memory, multiple signal processing circuits 140 execute the write operation for one pixel row in parallel. That is, the entire horizontal scanning period can be allocated to the write operation for one pixel. Meanwhile, when reading pixel data from memory, the output line is shared by multiple memories, so the pixel data for one pixel row is transferred to the arithmetic processing circuit 191 in a time-division manner. For these reasons, the time allocated to the readout operation for one pixel within one horizontal scanning period is shorter than the time allocated to the write operation for one pixel within one horizontal scanning period. Therefore, high-speed operation is required for the readout operation. Furthermore, to increase the readout speed, the output line that reads out the pixel data must have low parasitic capacitance. In an imaging device that changes the allocation of output lines that output pixel data from a memory when the number of bits is changed as in Patent Document 1, parasitic capacitance can increase because switches and the like are added to the output lines.

[0078] In contrast, in the imaging device 100 of this embodiment, a mode switching switch is provided in the writing section of the memory. Therefore, the parasitic capacitance of the output line is reduced compared to a configuration in which a mode switching switch is provided in the reading section of the memory. Therefore, the read operation can be performed at a higher speed.

[0079] [Second embodiment] An imaging device 100A according to the second embodiment will be described with reference to FIGS. 9 to 12. In this embodiment, the number of bits of pixel data in the first mode is 12, similar to the first embodiment. In contrast, the number of bits of pixel data in the second mode is 1, unlike the first embodiment. In this embodiment, descriptions of elements common to the first embodiment may be omitted or simplified.

[0080] 9 is a block diagram schematically showing the overall configuration of an image pickup device 100A according to this embodiment. The image pickup device 100A according to this embodiment differs from the image pickup device 100 according to the first embodiment in the configuration of a signal processing circuit 140A. The signal processing circuit 140A is connected to a memory group 180 via a latch pulse signal line 182 and a binary output signal line 183.

[0081] In the first mode, the signal processing circuit 140A supplies a latch pulse signal to the memory group 180 via a latch pulse signal line 182. In the second mode, the signal processing circuit 140A supplies a binary signal, which is 1-bit digital data, to the memory group 180 via a binary output signal line 183.

[0082] FIG. 10 is a circuit diagram showing an example of an equivalent circuit of a signal processing circuit 140A according to this embodiment. The signal processing circuit 140A includes a comparator 141, a pulse generating circuit 142, and a switch group 143. The pixel signal PIXSIG is input to the comparator 141. Furthermore, either a ramp signal RAMP or a reference voltage VREF, which is a fixed voltage, is input to the comparator 141. In the first mode, the ramp signal RAMP is input to the comparator 141, as in the first embodiment. In the second mode, the reference voltage VREF is input to the comparator 141. In this embodiment, the ramp signal RAMP and the reference voltage VREF are switched by the switch group 143, which operates based on a control signal indicating the mode. Alternatively, the ramp signal RAMP and the reference voltage VREF may be switched on the output side of the reference signal generating circuit 170. The operation in the first mode is similar to that in the first embodiment, and therefore a description thereof will be omitted.

[0083] In the second mode, the comparator 141 outputs the output signal COMP_OUT to the binary output signal line 183 based on the result of comparing the pixel signal PIXSIG with the reference voltage VREF. The output signal COMP_OUT is 1-bit digital data. When the potential of the pixel signal PIXSIG is higher than the reference voltage VREF, the output signal COMP_OUT is at a low level. When the potential of the pixel signal PIXSIG is lower than the reference voltage VREF, the output signal COMP_OUT is at a high level. This output signal COMP_OUT is stored in the S memory group 180S as 1-bit pixel data.

[0084] 11(a) and 11(b) are schematic diagrams showing examples of storing pixel data in the S memory group 180S in this embodiment. Fig. 11(a) shows an example of storing pixel data in the S memory group 180S in the first mode, and Fig. 11(b) shows an example of storing pixel data in the S memory group 180S in the second mode.

[0085] Similar to FIGS. 4(a) and 4(b) in the first embodiment, FIGS. 11(a) and 11(b) illustrate an example in which the S memory group 180S is composed of a first S memory 201 to a twelfth S memory 212. Each of the first S memory 201 to the twelfth S memory 212 has memory cells worth 12 bits. One block among the first S memory 201 to the twelfth S memory 212 schematically shows memory cells worth 1 bit. Hatched memory cells indicate memory cells in which pixel data is stored.

[0086] Similarly to the first embodiment, the plurality of output lines 113 in this embodiment are designated as the first to twelfth output lines. In the first mode, pixel data output from the pixels via the first to twelfth output lines are designated as DS1 to DS12, respectively. In the second mode, pixel data output from the pixels via the first to twelfth output lines are designated as DS1B to DS12B, respectively.

[0087] 11(a), in the first mode, 12 bits of pixel data for one pixel are stored in one memory. That is, the first S memory 201 to the twelfth S memory 212 store pixel data DS1 to DS12, respectively.

[0088] 11(b), in the second mode, pixel data DS1B to DS12B for 12 pixels are stored in the first S memory 201. Dummy data is stored in the second S memory 202 to the twelfth S memory 212. Each of the pixel data DS1B to DS12B is 1-bit digital data.

[0089] Fig. 12 is a timing chart showing an example of the operation of the imaging device 100A according to this embodiment. Fig. 12 shows the timing of the operation of reading out pixel data stored in the S memory group 180S and transferring it to the arithmetic processing circuit 191. "First mode" in Fig. 12 shows the timing of the operation in the first mode, and "second mode" in Fig. 12 shows the timing of the operation in the second mode.

[0090] In the first mode, the first S memory 201 to the twelfth S memory 212 are scanned in this order, and the pixel data DS1 to DS12 are transferred in this order to the arithmetic processing circuit 191. As shown in Fig. 12, if the time required to transfer one pixel data is Δt, the time required to transfer all of the pixel data DS1 to DS12 is Δt × 12.

[0091] In the second mode, when the first S memory 201 is read, the pixel data DS1B to DS12B are transferred to the arithmetic processing circuit 191. As shown in Fig. 12, the time required to transfer all of the pixel data DS1B to DS12B is Δt. Therefore, in the second mode, the time required to transfer the pixel data is reduced to one-twelfth of that in the first mode.

[0092] In this embodiment, pixel data is stored in the first S memory 201 in the second mode, but pixel data may be stored in another memory.

[0093] According to this embodiment, an imaging device capable of high-speed operation and a driving method for the imaging device are provided, similar to the first embodiment. Furthermore, in this embodiment, since the pixel data in the second mode is 1 bit, the readout operation can be performed at a higher speed than when the pixel data is multiple bits.

[0094] This embodiment can also be applied to an imaging device that counts the number of incident quanta by determining the incidence of quanta such as photons or electrons from 1-bit pixel data. In such an imaging device, setting the second mode to improve the frame readout speed can shorten the shooting time and reduce blur.

[0095] [Third embodiment] An imaging device according to the third embodiment will be described with reference to FIGS. 13(a) to 14. In this embodiment, the number of bits of pixel data of the S signal in the first mode is 12 bits, and the number of bits of pixel data of the N signal in the first mode is 8 bits. Because the N signal is an output signal from a pixel in a reset state, the signal range of the N signal is smaller than the signal range of the S signal. Therefore, the number of bits of pixel data of the N signal is smaller than the number of bits of pixel data of the S signal. Furthermore, the number of bits of pixel data of the S signal in the second mode is 4 bits. In this embodiment, the method of storing pixel data in the memory group 180 differs from that in the first embodiment, and in the second mode, pixel data of the S signal is stored in the N memory group 180N. In this embodiment, descriptions of elements common to the first embodiment may be omitted or simplified.

[0096] 13(a) and 13(b) are schematic diagrams showing an example of pixel data storage in the S memory group 180S and the N memory group 180N according to this embodiment. Fig. 13(a) shows an example of pixel data storage in the S memory group 180S and the N memory group 180N in the first mode, and Fig. 13(b) shows an example of pixel data storage in the S memory group 180S and the N memory group 180N in the second mode.

[0097] 13(a) and 13(b) illustrate an example in which the S memory group 180S is composed of 12 first S memories 201 to 12th S memories 212, and the N memory group 180N is composed of 12 first N memories 221 to 12th N memories 232. Each of the first S memories 201 to 12th S memories 212 has 12-bit memory cells. Each of the first N memories 221 to 12th N memories 232 has 8-bit memory cells. Hatched memory cells indicate memory cells in which pixel data is stored.

[0098] Similarly to the first embodiment, the plurality of output lines 113 in this embodiment are designated as the first to twelfth output lines. In the first mode, the pixel data of the S signal output from the pixel via the first to twelfth output lines are designated as DS1 to DS12, respectively, and the pixel data of the N signal output from the pixel via the first to twelfth output lines are designated as DN1 to DN12, respectively. In the second mode, the pixel data of the S signal output from the pixel via the first to twelfth output lines are designated as DS1A to DS12A, respectively.

[0099] 13(a), in the first mode, pixel data of one pixel's worth of S signal is stored in one S memory. That is, the first S memory 201 to the twelfth S memory 212 store pixel data DS1 to DS12, respectively.

[0100] 13(a), in the first mode, pixel data of one pixel's worth of N signals is stored in one N memory. That is, the 1N memory 221 to the 12N memory 232 store pixel data DN1 to DN12, respectively.

[0101] As shown in FIG. 13(b), in the second mode, one S memory stores pixel data of S signals for three pixels, and one N memory stores pixel data of S signals for two pixels. That is, the first S memory 201 stores pixel data DS1A, DS2A, and DS3A for three pixels. The first N memory 221 stores pixel data DS4A and DS5A for two pixels. The sixth S memory 206 stores pixel data DS6A, DS7A, and DS8A for three pixels. The sixth N memory 226 stores pixel data DS9A and DS10A for two pixels. The eleventh S memory 211 stores pixel data DS11A and DS12A for two pixels. Each of the pixel data DS1A to DS12A is 4-bit digital data. Dummy data is stored in memories that do not store pixel data. Depending on the number of output lines 113 and the number of memories, both pixel data and dummy data may be stored in one memory, such as the 11S memory 211.

[0102] In the second mode of this embodiment, pixel data of the S signal is stored in the N memory group 180N as described above, and therefore pixel data of the N signal is not acquired. Alternatively, in this embodiment, an S signal may be acquired when no light is incident on the pixel array 110, and the S signal may be used as the N signal. This S signal is called a dark signal. The dark signal is stored in a dark signal storage unit provided separately from the memory group 180. The dark signal storage unit may be built into the image capture device 100, or may be provided in a storage device externally connected to the image capture device 100. In the second mode, the arithmetic processing circuit 191 performs differential calculation processing between the S signal and the dark signal, thereby correcting noise such as fixed pattern noise.

[0103] Fig. 14 is a timing chart showing an example of the operation of the imaging device 100 according to this embodiment. Fig. 14 shows the timing of the operation of reading out pixel data stored in the S memory group 180S and the N memory group 180N and transferring it to the arithmetic processing circuit 191. "First mode" in Fig. 14 shows the timing of the operation in the first mode, and "second mode" in Fig. 14 shows the timing of the operation in the second mode. "NULL" in "second mode" in Fig. 14 indicates dummy data.

[0104] In the first mode, the 1S memory 201 to the 12S memory 212 are scanned in this order, and the pixel data DS1 to DS12 are transferred in this order to the arithmetic processing circuit 191. In parallel with this, the 1N memory 221 to the 12N memory 232 are scanned in this order, and the pixel data DN1 to DN12 are also transferred in this order to the arithmetic processing circuit 191. The time required to transfer all of the pixel data DS1 to DS12 and DN1 to DN12 is Δt×12.

[0105] In the second mode, the 1S memory 201, the 1N memory 221, the 6S memory 206, the 6N memory 226, the 11S memory 211, and the 11N memory 231 are scanned, and pixel data DS1A to DS12A are transferred to the arithmetic processing circuit 191. First, the 1S memory 201 and the 1N memory 221 are read out simultaneously, and pixel data DS1A to DS5A are transferred to the arithmetic processing circuit 191. Next, the 6S memory 206 and the 6N memory 226 are read out simultaneously, and pixel data DS6A to DS10A are transferred to the arithmetic processing circuit 191. Next, the 11S memory 211 and the 11N memory 231 are read out simultaneously, and pixel data DS11A, DS12A, and dummy data are transferred to the arithmetic processing circuit 191. Dummy data is stored in some memory cells of the 11S memory 211, but by simultaneously reading the dummy data, exceptional operations for the memory cells storing the dummy data are not required, thereby simplifying circuit operation and circuit configuration. Furthermore, by simultaneously reading the 11N memory 231, in which dummy data is stored, with the 11S memory 211, exceptional operations for the 11N memory 231 are not required, thereby simplifying circuit operation and circuit configuration. Since memories storing other dummy data are skipped during scanning, dummy data is not read from those memories. As shown in the "second mode" of Figure 14, the time required to transfer all of the pixel data DS1A to DS12A is Δt × 3. Therefore, in the second mode, the time required to transfer pixel data is reduced to one-fourth of that in the first mode.

[0106] In this embodiment, in the second mode, pixel data is stored in the 1st S memory 201, the 1st N memory 221, the 4th S memory 204, the 6th S memory 206, the 6th N memory 226, and the 11th S memory 211, but pixel data may also be stored in other memories.

[0107] The operation of this embodiment will be outlined below by more generalizing the number of memory bits and the number of pixel data bits. The number of bits of the memory cells in each of the S memory and the N memory is equal to or greater than the number of pixel data bits in the first mode. Each S memory has i-bit (i is an integer equal to or greater than 2) memory cells, and each N memory has j-bit (j is an integer equal to or greater than 2) memory cells. In this case, the pixel data of the S signal (first optical data) in the first mode is p bits (p is an integer equal to or greater than 2 and equal to i), and the pixel data of the N signal (first noise data) in the first mode is q bits (q is an integer equal to or greater than 1 and equal to j).

[0108] In the second mode, pixel data (third optical data, fourth optical data) of two or more pixels of S signals are stored in one S memory, and pixel data (third optical data, fourth optical data) of one or more pixels of S signals are stored in one N memory. Therefore, the pixel data in the second mode is r bits (r is an integer not less than 1, not more than p / 2, and not more than q).

[0109] In the first mode, an optical signal based on the charge generated by photoelectric conversion is AD converted into p-bit pixel data (p is an integer greater than or equal to 2 and less than or equal to i) and stored in the S memory. Then, a noise signal output from a pixel in a reset state is AD converted into q-bit pixel data (q is an integer greater than or equal to 1 and less than or equal to j) and stored in the N memory. In the second mode, an optical signal based on the charge generated by photoelectric conversion is AD converted into r-bit pixel data (r is an integer greater than or equal to 1 and less than or equal to p / 2 and less than or equal to q) and stored in the S memory and the N memory.

[0110] According to this embodiment, an imaging device and a driving method for an imaging device capable of high-speed operation are provided, similarly to the first embodiment. Furthermore, in this embodiment, pixel data of S signals are stored in both the S memory and the N memory in the second mode, so that the number of pixel data that can be read simultaneously can be increased, and the read operation can be further accelerated.

[0111] [Fourth embodiment] An image pickup device 100B according to the fourth embodiment will be described with reference to FIG. 15. FIG. 15 is a block diagram schematically showing the overall configuration of the image pickup device 100B according to this embodiment. In the first embodiment, a configuration in which the reference signal generation circuit 170, the signal processing circuit 140, and the counter 160 function as an AD conversion unit was described. In this embodiment, instead of these, the image pickup device 100B includes a pipelined AD conversion unit 144. In this embodiment, descriptions of elements common to the first embodiment may be omitted or simplified.

[0112] The AD conversion unit 144 has a plurality of pipelined AD conversion circuits 144A (analog-to-digital conversion circuits). Each of the plurality of AD conversion circuits 144A is electrically connected to a corresponding one of the plurality of output lines 113. That is, one AD conversion circuit 144A is configured to process a pixel signal output from at least one pixel 111.

[0113] An output node of the AD conversion circuit 144A is electrically connected to a corresponding memory group 180. The AD conversion circuit 144A performs AD conversion on the pixel signal and supplies the AD-converted pixel data to a corresponding memory in the memory group 180.

[0114] The AD conversion circuit 144A has a switch or the like that switches connections depending on the mode. By switching the memory to which pixel data is output from the AD conversion circuit 144A between the first mode and the second mode, it is possible to realize the pixel data storage method shown in Fig. 4, as in the first embodiment. That is, a memory that stores pixel data corresponding to one pixel in the first mode can store pixel data corresponding to multiple pixels in the second mode.

[0115] According to this embodiment, similar to the first embodiment, an imaging device capable of high-speed operation and a method for driving an imaging device are provided. Furthermore, in this embodiment, a pipelined AD conversion circuit 144A is used. A pipelined AD conversion circuit has the advantages of high speed, low power consumption, and a small area. Therefore, according to this embodiment, a high-speed, low-power, and compact imaging device is realized.

[0116] Furthermore, when the imaging device of this embodiment is an imaging device for detecting radiation, in addition to the above-mentioned effects, the probability of radiation being incident on the circuit elements is reduced, thereby achieving the effect of reducing radiation degradation.

[0117] [Fifth embodiment] An imaging device 100C according to the fifth embodiment will be described with reference to FIG. 16. FIG. 16 is a block diagram schematically showing the overall configuration of the imaging device 100C according to this embodiment. In the first embodiment, one signal processing circuit 140 is connected to one output line 113. In contrast, in this embodiment, one signal processing circuit 140 is shared by multiple output lines 113. In this embodiment, descriptions of elements common to the first embodiment may be omitted or simplified.

[0118] The imaging device 100C has a switch group 114 and a switch group 115. Each of the switch group 114 and the switch group 115 includes a plurality of switches. The plurality of switches are controlled by control signals supplied from a timing control unit 190. The switch group 114 connects one of a plurality of output lines 113 to one signal processing circuit 140. The switch group 115 connects an output terminal of the signal processing circuit 140 to one memory of a plurality of memory groups 180.

[0119] By appropriately switching the connections of the switch group 114 and the switch group 115, a plurality of output lines 113 can share one signal processing circuit 140. Although Fig. 16 illustrates a configuration in which four output lines 113 share one signal processing circuit 140, the number of output lines 113 that share one signal processing circuit 140 may be other than four.

[0120] In this embodiment, the switches in the switch group 114 are controlled to sequentially switch the output lines 113 connected to the signal processing circuit 140. In addition, the switches in the switch group 115 are controlled to sequentially switch the memories to which the signal processing circuit 140 is output, in synchronization with the switching of the switches in the switch group 114.

[0121] According to this embodiment, similar to the first embodiment, an imaging device capable of high-speed operation and a method for driving an imaging device are provided. Furthermore, in this embodiment, multiple output lines 113 share one signal processing circuit 140, so the ratio of the number of signal processing circuits 140 to the number of multiple output lines 113 can be reduced. Therefore, the area occupied by the signal processing circuit 140 is reduced. This provides the effect of miniaturizing the device and reducing costs by reducing the chip size.

[0122] Furthermore, when the imaging device of this embodiment is an imaging device for detecting radiation, in addition to the above-mentioned effects, the probability of radiation being incident on the circuit elements is reduced, thereby achieving the effect of reducing radiation degradation.

[0123] In this embodiment, the AD conversion unit may be configured as a pipeline AD conversion circuit as explained in the fourth embodiment, and in that case, the same effects as those of the fourth embodiment can be obtained.

[0124] [Sixth embodiment] An imaging device 100D according to the sixth embodiment will be described with reference to FIG. 17 . FIG. 17 is a block diagram schematically illustrating the overall configuration of the imaging device 100D according to this embodiment. The imaging device 100D according to this embodiment can switch between the configuration described in the first embodiment and the configuration described in the fifth embodiment. That is, the imaging device 100D according to this embodiment can switch between a configuration in which each of the multiple signal processing circuits 140 is electrically connected to a corresponding one of the multiple output lines 113, and a configuration in which the multiple output lines 113 share one signal processing circuit 140. In this embodiment, descriptions of elements common to the first or fifth embodiment may be omitted or simplified.

[0125] The imaging device 100D has a switch group 116 and a switch group 117. Each of the switch group 116 and the switch group 117 includes a plurality of switches and functions as a state switching unit. The plurality of switches are controlled by a control signal supplied from a timing control unit 190. The switch group 116 switches between a configuration in which each of the plurality of signal processing circuits 140 is connected to a corresponding one of the plurality of output lines 113 (first state) and a configuration in which the plurality of output lines 113 share one signal processing circuit 140 (second state). In the second state, similar to the fifth embodiment, the output line 113 connected to the shared signal processing circuit 140 is sequentially switched. The switch group 117 switches between a configuration in which each of the output terminals of the plurality of signal processing circuits 140 is connected to a corresponding one of the plurality of memory groups 180 and a configuration in which the output terminal of the shared signal processing circuit 140 is connected to one memory of the plurality of memory groups 180. In this way, the switch group 116 and the switch group 117 have the function of switching between a configuration state similar to that of the first embodiment and a configuration state similar to that of the fifth embodiment.

[0126] According to this embodiment, similarly to the first embodiment, an imaging device capable of high-speed operation and a method for driving an imaging device are provided. Also, it is possible to switch between a configuration in which each of a plurality of signal processing circuits 140 is electrically connected to a corresponding one of a plurality of output lines 113 as in the first embodiment, and a configuration in which a plurality of output lines 113 share one signal processing circuit 140 as in the fifth embodiment. In the latter configuration, it is possible to stop the power supply and operation of unused signal processing circuits 140, thereby reducing power consumption.

[0127] FIG. 17 illustrates a configuration in which four output lines 113 form one group, and in the second state, the four output lines 113 included in the group share one signal processing circuit 140, but the number of output lines 113 included in a group is not limited to four.

[0128] In this embodiment, the AD conversion unit may be configured as a pipeline AD conversion circuit as explained in the fourth embodiment, and in that case, the same effects as those of the fourth embodiment can be obtained.

[0129] [Seventh embodiment] A device according to a seventh embodiment of the present invention will be described with reference to Fig. 18. Fig. 18 is a block diagram showing a schematic configuration of the device according to this embodiment.

[0130] FIG. 18 is a schematic diagram showing equipment EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the imaging devices of the first to sixth embodiments. All or part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometry sensor, a distance measurement sensor, etc. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including photoelectric conversion units are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0131] The photoelectric conversion device APR may have a structure (chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may also be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected by through-silicon vias (TSVs), inter-chip wiring formed by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

[0132] The photoelectric conversion device APR may include, in addition to the semiconductor device IC, a package PKG that houses the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connecting members such as bonding wires and bumps that connect terminals provided on the base to terminals provided on the semiconductor device IC.

[0133] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes signals output from the photoelectric conversion device APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is, for example, an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is, for example, a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is, for example, a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. The device EQP displays the signal output from the photoelectric conversion device APR on a display device DSPL and transmits the signal to the outside using a communication device (not shown) provided in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and arithmetic circuit unit provided in the photoelectric conversion device APR.

[0134] The device EQP shown in FIG. 17 may be an electronic device such as an information terminal with a photographing function (e.g., a smartphone or a wearable device), a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP may also be a transportation device (mobile object) such as a vehicle, a ship, or an aircraft. The device EQP may also be a medical device such as an endoscope or a CT scanner.

[0135] The mechanical device MCHN in the transportation equipment can be used as a moving device. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device APR, assisting and / or automating driving (piloting) using a photographing function, etc. The processing device PRCS for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

[0136] The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser, and / or user. Therefore, if the photoelectric conversion device APR is installed in a device EQP, the value of the device EQP can also be increased. Therefore, when manufacturing and selling the device EQP, deciding to install the photoelectric conversion device APR according to this embodiment in the device EQP is advantageous in increasing the value of the device EQP.

[0137] [Eighth embodiment] 19(a) and 19(b) are block diagrams of devices related to an in-vehicle camera according to this embodiment. FIGS. 19(a) and 19(b) show an example in which the above-described imaging device is applied to a moving body such as a vehicle. Device 80 includes an imaging device 800 and a signal processing device (processing device) that processes signals from the imaging device 800. Device 80 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the imaging device 800, and a parallax calculation unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by device 80. Device 80 also includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, parallax calculation unit 802 and distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to an object. In other words, the distance information includes information on parallax, defocus amount, distance to the object, etc. The collision determination unit 804 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0138] The device 80 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The device 80 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The device 80 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high collision possibility, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel. The device 80 functions as a control means for controlling the operation of controlling the vehicle as described above.

[0139] In this embodiment, the device 80 captures images of the surroundings of the vehicle, for example, the front or rear. Fig. 19(b) shows the device when capturing an image of the area in front of the vehicle (image capturing range 850). A vehicle information acquisition device 810, which serves as an image capturing control means, sends an instruction to the device 80 or the image capturing device 800 to perform an image capturing operation. This configuration can further improve the accuracy of distance measurement.

[0140] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the present invention is not limited to vehicles such as automobiles, but can be applied to moving objects (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present invention can be applied to a wide range of devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, without being limited to moving objects.

[0141] [Modified embodiment] The present invention is not limited to the above-described embodiments and can be modified in various ways. For example, an example in which part of the configuration of one embodiment is added to another embodiment, or an example in which part of the configuration of one embodiment is replaced with part of the configuration of another embodiment, is also an embodiment of the present invention.

[0142] The structure of the imaging device described above is not limited to a specific form. For example, the element structure of the imaging device may be either a front-illuminated type or a back-illuminated type. Furthermore, the imaging device may be a stacked type in which a semiconductor chip including a pixel array and a semiconductor chip including a signal processing circuit are stacked.

[0143] The disclosure of this specification includes the complement of the concepts described in this specification. In other words, if this specification states, for example, that "A is B" (A=B), then this specification is deemed to disclose or suggest that "A is not B" even if the statement that "A is not B" (A≠B) is omitted. This is because when "A is B," it is assumed that the case where "A is not B" is taken into consideration.

[0144] The disclosure of this specification includes the following configurations or methods. (Configuration 1) a plurality of pixels each outputting a pixel signal; a first output line and a second output line each connected to a corresponding pixel; an analog-to-digital conversion unit that converts the pixel signal into analog-to-digital data; a first memory and a second memory each for holding the pixel data; a scanning circuit that performs scanning to output the pixel data from the first memory and the second memory; and In the first mode, the analog-to-digital converter performs analog-to-digital conversion on the pixel signal from the first output line to generate first pixel data, and performs analog-to-digital conversion on the pixel signal from the second output line to generate second pixel data; the first memory stores the first pixel data; the second memory stores the second pixel data; the scanning circuit causes the first pixel data to be output from the first memory and the second pixel data to be output from the second memory; In the second mode, the analog-to-digital converter performs analog-to-digital conversion on the pixel signal from the first output line to generate third pixel data, and performs analog-to-digital conversion on the pixel signal from the second output line to generate fourth pixel data; the first memory stores the third pixel data and the fourth pixel data; The scanning circuit outputs the third pixel data and the fourth pixel data from the first memory. An imaging device characterized by: (Configuration 2) the first memory has a storage capacity of k bits (k is an integer of 2 or more), the first pixel data and the second pixel data are m-bit digital data (m is an integer of 2 or more and k or less), The third pixel data and the fourth pixel data are n-bit digital data (n is an integer of 1 or more and m / 2 or less). 2. The imaging device according to claim 1, (Configuration 3) the first memory has a first memory area having a storage capacity of i bits (i is an integer of 2 or more) and a second memory area having a storage capacity of j bits (j is an integer of 2 or more); the first pixel data includes first optical data generated based on charges generated by photoelectric conversion and first noise data generated based on signals output from pixels in a reset state; the third pixel data includes third optical data generated based on charges generated by photoelectric conversion, the fourth pixel data includes fourth optical data generated based on charges generated by photoelectric conversion, In the first mode, the first memory area stores p bits (p is an integer between 2 and i) of the first optical data, and the second memory area stores q bits (q is an integer between 1 and j) of the first noise data; In the second mode, the first memory area and the second memory area store r bits of the third optical data and the fourth optical data (r is an integer of 1 to p / 2 and q). 2. The imaging device according to claim 1, (Configuration 4) In the second mode, the second memory stores dummy data of a fixed value. 4. The imaging device according to any one of configurations 1 to 3. (Configuration 5) Each of the third pixel data and the fourth pixel data is 1-bit digital data. 5. The imaging device according to any one of configurations 1 to 4. (Configuration 6) the analog-to-digital conversion unit includes a comparator and a counter; the comparator compares the potential of the first output line or the second output line with the potential of a reference signal; The counter outputs a signal corresponding to the time at which the output signal of the comparator changes to the first memory or the second memory. 6. The imaging device according to any one of configurations 1 to 5. (Configuration 7) The analog-to-digital conversion unit includes a pipelined analog-to-digital conversion circuit. 6. The imaging device according to any one of configurations 1 to 5. (Configuration 8) The plurality of pixels are arranged in a plurality of columns, the first output line is connected to pixels in one column of the plurality of columns; The second output line is connected to pixels in another column of the plurality of columns. 8. The imaging device according to any one of configurations 1 to 7, wherein: (Configuration 9) the analog-to-digital conversion unit has a plurality of processing circuits each having an analog-to-digital conversion function, The plurality of processing circuits are arranged to correspond to the plurality of columns, respectively. 9. The imaging device according to configuration 8, (Configuration 10) the analog-to-digital conversion unit has a plurality of processing circuits each having an analog-to-digital conversion function, One of the plurality of processing circuits is arranged to correspond to two or more of the plurality of columns. 9. The imaging device according to configuration 8, (Configuration 11) the analog-to-digital conversion unit has a plurality of processing circuits each having an analog-to-digital conversion function, The display device further includes a state switching unit that switches between a first state in which the plurality of processing circuits are arranged to correspond to the plurality of columns, respectively, and a second state in which one of the plurality of processing circuits is arranged to correspond to two or more of the plurality of columns. 9. The imaging device according to configuration 8. (Configuration 12) Each of the plurality of pixels is sensitive to radiation. 12. The imaging device according to any one of configurations 1 to 11. (Configuration 13) In the second mode, the scanning circuit simultaneously outputs the third pixel data and the fourth pixel data from the first memory. 13. The imaging device according to any one of configurations 1 to 12. (Configuration 14) In the second mode, the scanning circuit does not output a signal from the second memory. 14. The imaging device according to any one of configurations 1 to 13. (Configuration 15) The plurality of pixels are arranged in a plurality of rows and a plurality of columns, The time required to output pixel data corresponding to a plurality of pixels in one row in the second mode is shorter than the time required to output pixel data corresponding to a plurality of pixels in one row in the first mode. 15. The imaging device according to any one of configurations 1 to 14. (Configuration 16) a mode switching unit that switches between the first mode and the second mode by switching an output destination of a signal from the analog-to-digital conversion unit to either a first memory or a second memory; 16. The imaging device according to any one of configurations 1 to 15. (Configuration 17) a plurality of pixels each outputting a pixel signal; a first output line and a second output line each connected to a corresponding pixel; an analog-to-digital conversion unit that converts the pixel signal into analog-to-digital data; a first memory and a second memory each for holding the pixel data; a scanning circuit that performs scanning to output the pixel data from the first memory and the second memory; a mode switching unit that switches an output destination of a signal from the analog-to-digital conversion unit to either a first memory or a second memory; An imaging device comprising: (Configuration 18) an imaging device according to any one of configurations 1 to 17; an optical device corresponding to the imaging device; a control device that controls the imaging device; a processing device that processes a signal output from the imaging device; a display device that displays information obtained by the imaging device; a storage device that stores information obtained by the imaging device; and and a mechanical device that operates based on information obtained by the imaging device. (Configuration 19) 19. The device according to claim 18, wherein the processing device acquires distance information from the imaging device to an object. (Method 20) a plurality of pixels each outputting a pixel signal; a first output line and a second output line each connected to a corresponding pixel; a first memory and a second memory, each of which stores pixel data generated by analog-to-digital conversion of the pixel signal; A method for driving an imaging device having In the first mode, performing analog-to-digital conversion on the pixel signal from the first output line to generate first pixel data and store the first pixel data in the first memory, and performing analog-to-digital conversion on the pixel signal from the second output line to generate second pixel data and store the second pixel data in the second memory; outputting the first pixel data from the first memory and the second pixel data from the second memory; In the second mode, performing analog-to-digital conversion on the pixel signal from the first output line to generate third pixel data and store the third pixel data in the first memory, and performing analog-to-digital conversion on the pixel signal from the second output line to generate fourth pixel data and store the fourth pixel data in the first memory; and outputting the third pixel data and the fourth pixel data from the first memory. 10. A method for driving an imaging device comprising:

[0145] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0146] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0147] 100 Imaging device 111 pixels 113 Output line 130 horizontal scanning circuit 140 Signal Processing Circuit 160 counters 170 Reference signal generation circuit 180 Memory Group

Claims

1. a plurality of pixels each outputting a pixel signal; a first output line and a second output line each connected to a corresponding pixel; an analog-to-digital conversion unit that converts the pixel signal into analog-to-digital data; a first memory and a second memory each for holding the pixel data; a scanning circuit that performs scanning to output the pixel data from the first memory and the second memory; and In the first mode, the analog-to-digital converter performs analog-to-digital conversion on the pixel signal from the first output line to generate first pixel data, and performs analog-to-digital conversion on the pixel signal from the second output line to generate second pixel data; the first memory stores the first pixel data; the second memory stores the second pixel data; the scanning circuit causes the first pixel data to be output from the first memory and the second pixel data to be output from the second memory; In the second mode, the analog-to-digital converter performs analog-to-digital conversion on the pixel signal from the first output line to generate third pixel data, and performs analog-to-digital conversion on the pixel signal from the second output line to generate fourth pixel data; the first memory stores the third pixel data and the fourth pixel data; the scanning circuit outputs the third pixel data and the fourth pixel data from the first memory; An imaging device characterized by:

2. the first memory has a storage capacity of k bits (k is an integer of 2 or more); the first pixel data and the second pixel data are m-bit digital data (m is an integer of 2 or more and k or less), The third pixel data and the fourth pixel data are n-bit digital data (n is an integer of 1 or more and m / 2 or less).

2. The imaging device according to claim 1.

3. the first memory has a first memory area having a storage capacity of i bits (i is an integer of 2 or more) and a second memory area having a storage capacity of j bits (j is an integer of 2 or more); the first pixel data includes first optical data generated based on charges generated by photoelectric conversion and first noise data generated based on signals output from pixels in a reset state; the third pixel data includes third optical data generated based on charges generated by photoelectric conversion, the fourth pixel data includes fourth optical data generated based on charges generated by photoelectric conversion, In the first mode, the first memory area stores p bits of the first optical data (p is an integer of 2 or more and i or less), and the second memory area stores q bits of the first noise data (q is an integer of 1 or more and j or less); In the second mode, the first memory area and the second memory area store the third optical data and the fourth optical data of r bits (r is an integer of 1 to p / 2 and q).

2. The imaging device according to claim 1.

4. In the second mode, the second memory stores dummy data of a fixed value.

2. The imaging device according to claim 1.

5. Each of the third pixel data and the fourth pixel data is 1-bit digital data.

2. The imaging device according to claim 1.

6. the analog-to-digital conversion unit includes a comparator and a counter; the comparator compares the potential of the first output line or the second output line with the potential of a reference signal; The counter outputs a signal corresponding to the time at which the output signal of the comparator changes to the first memory or the second memory.

2. The imaging device according to claim 1.

7. The analog-to-digital conversion unit includes a pipelined analog-to-digital conversion circuit.

2. The imaging device according to claim 1.

8. The plurality of pixels are arranged in a plurality of columns, the first output line is connected to pixels in one column of the plurality of columns; The second output line is connected to pixels in another column of the plurality of columns.

2. The imaging device according to claim 1.

9. the analog-to-digital conversion unit has a plurality of processing circuits each having an analog-to-digital conversion function, The plurality of processing circuits are arranged to correspond to the plurality of columns, respectively.

9. The imaging device according to claim 8.

10. the analog-to-digital conversion unit has a plurality of processing circuits each having an analog-to-digital conversion function, One of the plurality of processing circuits is arranged to correspond to two or more of the plurality of columns.

9. The imaging device according to claim 8.

11. the analog-to-digital conversion unit has a plurality of processing circuits each having an analog-to-digital conversion function, The image sensor further includes a state switching unit that switches between a first state in which the plurality of processing circuits are arranged to correspond to the plurality of columns, respectively, and a second state in which one of the plurality of processing circuits is arranged to correspond to two or more of the plurality of columns.

9. The imaging device according to claim 8.

12. Each of the plurality of pixels is sensitive to radiation.

2. The imaging device according to claim 1.

13. In the second mode, the scanning circuit simultaneously outputs the third pixel data and the fourth pixel data from the first memory.

2. The imaging device according to claim 1.

14. In the second mode, the scanning circuit does not output a signal from the second memory.

2. The imaging device according to claim 1.

15. The plurality of pixels are arranged in a plurality of rows and a plurality of columns, The time required to output pixel data corresponding to a plurality of pixels in one row in the second mode is shorter than the time required to output pixel data corresponding to a plurality of pixels in one row in the first mode.

2. The imaging device according to claim 1.

16. a mode switching unit that switches between the first mode and the second mode by switching an output destination of a signal from the analog-to-digital conversion unit to either a first memory or a second memory; 2. The imaging device according to claim 1.

17. a plurality of pixels each outputting a pixel signal; a first output line and a second output line each connected to a corresponding pixel; an analog-to-digital conversion unit that converts the pixel signal into analog-to-digital data; a first memory and a second memory each for holding the pixel data; a scanning circuit that performs scanning to output the pixel data from the first memory and the second memory; a mode switching unit that switches an output destination of a signal from the analog-to-digital conversion unit to either a first memory or a second memory; An imaging device comprising:

18. An imaging device according to any one of claims 1 to 17; an optical device corresponding to the imaging device; a control device that controls the imaging device; a processing device that processes a signal output from the imaging device; a display device that displays information obtained by the imaging device; a storage device that stores information obtained by the imaging device; and and a mechanical device that operates based on information obtained by the imaging device.

19. The device of claim 18 , wherein the processing device acquires distance information from the imaging device to an object.

20. a plurality of pixels each outputting a pixel signal; a first output line and a second output line each connected to a corresponding pixel; a first memory and a second memory, each of which stores pixel data generated by analog-to-digital conversion of the pixel signal; A method for driving an imaging device having In the first mode, performing analog-to-digital conversion on the pixel signal from the first output line to generate first pixel data and store the first pixel data in the first memory, and performing analog-to-digital conversion on the pixel signal from the second output line to generate second pixel data and store the second pixel data in the second memory; outputting the first pixel data from the first memory and the second pixel data from the second memory; In the second mode, performing analog-to-digital conversion on the pixel signal from the first output line to generate third pixel data and store the third pixel data in the first memory, and performing analog-to-digital conversion on the pixel signal from the second output line to generate fourth pixel data and store the fourth pixel data in the first memory; and outputting the third pixel data and the fourth pixel data from the first memory.

10. A method for driving an imaging device comprising:

Images