LED color and brightness control apparatus and method

Abstract

To provide a control apparatus and method to effectively control the color and brightness level of an RGB based LED system.SOLUTION: An apparatus includes: a plurality of MOSFET device groups connected in parallel, where a first common node of the plurality of MOSFET device groups is coupled to a cathode of a light emitting diode channel of a plurality of light emitting diode channels and a second common node of the plurality of MOSFET device groups is connected to ground; and a control circuit configured to generate gate drive signals for the plurality of MOSFET device groups. The gate drive signals are configured to adjust a current flowing through the light emitting diode channel based on a predetermined color and a predetermined brightness level of the light emitting diode channel, and under different duty cycles, the control circuit controls the current flowing through the light emitting diode channel to be proportional to a corresponding duty cycle.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001]

[0001] Priority claims and cross-references This application is a continuation-in-part of U.S. Patent Application No. 17 / 663,707, filed May 17, 2022, which is incorporated herein by reference.

[0002] FIELD OF THE INVENTION

[0002] Embodiments of the present invention relate to light emitting diode color and brightness control devices and methods, and more particularly to RGB-based LED systems. [Background technology]

[0003]

[0003] A light-emitting diode (LED) is a semiconductor light source. When a voltage is applied to an LED, a current flows through it. In response to the current flowing through the LED, electrons and holes recombine at the PN junction of the diode. In the recombination process, energy is released in the form of photons. Photons with different wavelengths and / or frequencies produce light of different colors. The primary LED colors are red, green, and blue (RGB). By mixing these colors in different proportions, almost any color of visible light can be created.

[0004]

[0004] To produce different colors, three RGB colors of different intensities are combined. The intensity of light produced by an LED is proportional to the current flowing through it. The current flowing through the LED can be adjusted to change the intensity of the LED, thereby achieving different colors by changing the intensity of the RGB colors.

[0005]

[0005] RGB-based LED systems play an important role in lighting technology, which is widely used in fields such as automotive / industrial / architectural lighting, smart home appliances, wearable and handheld devices, etc. An RGB-based LED system can include multiple RGB modules (e.g., 12 RGB modules). Each RGB module includes three light-emitting diodes: a red LED, a green LED, and a blue LED. In most lighting applications, the three light-emitting diodes in one RGB module are close to each other, so that the light emitted from one RGB module is perceived by the human eye as a single point light source.

[0006]

[0006] The three RGB colors in one RGB module are mixed to form a single color and a single brightness level. The color and brightness level of the RGB module can be changed by adjusting the current flowing through the three light-emitting diodes in the RGB module. Various colors can be created by mixing the three RGB colors with different ratios of red, green, and blue light emission intensity. The brightness level of the RGB module is the total light emission intensity from the three light-emitting diodes combined. The brightness level of a channel (light-emitting diode) is proportional to the average current flowing through the LED channel.

[0007] The process of controlling the LED average current or luminous intensity is often referred to as dimming. Dimming processes can be divided into two categories: analog dimming and PWM (pulse-width modulation) dimming. Conventional RGB control methods employ two complex control methods to control the color and brightness level of an RGB-based LED system. In the first RGB control method, a brightness PWM control method is applied to all RGB modules. In other words, the brightness and color of each RGB module are controlled separately. This is known as the partition control method. In the second RGB control method, a single function control bit is used to control the color and brightness level of the corresponding RGB module. This is known as the bundling control method. Either the partition control method or the bundling control method results in a complex and expensive system. Such complex and expensive systems have many drawbacks, such as a lack of design flexibility and low reliability. It is desirable to have a simple control device and method for effectively controlling the color and brightness level of an RGB-based LED system. Summary of the Invention

[0008] These and other problems are generally solved and avoided, and technical advantages generally obtained, by preferred embodiments of the present disclosure, which provide light emitting diode (LED) color and brightness control devices and methods.

[0009]

[0009] According to one embodiment, an apparatus includes a bandgap voltage reference configured to generate a current reference for controlling a plurality of light emitting diode channels; a plurality of MOSFET devices connected in parallel and coupled between cathodes of the light emitting diode channels and ground, the MOSFET devices configured to control current through the light emitting diode channels; and a control circuit configured to generate gate drive signals for the plurality of MOSFET devices, the gate drive signals configured to adjust the current through the light emitting diode channels based on a predetermined color and a predetermined brightness level of the light emitting diode channels.

[0010]

[0010] According to another embodiment, a method for controlling the brightness and color of a group of red, green, and blue light-emitting diode channels in a lighting module having a red light-emitting diode channel, a green light-emitting diode channel, and a blue light-emitting diode channel includes steps of determining three color digital values ​​based on a predetermined color, storing the three color digital values ​​in three corresponding color registers, determining a brightness digital value based on a predetermined brightness level, storing the brightness digital value in the brightness register, and multiplying the three color digital values ​​by the brightness digital value to obtain three PWM signals for controlling currents flowing through the red light-emitting diode channel, the green light-emitting diode channel, and the blue light-emitting diode channel.

[0011]

[0011] According to yet another embodiment, a system includes a plurality of lighting modules, each having a red light emitting diode channel, a green light emitting diode channel, and a blue light emitting diode channel; and a light emitting diode control device, wherein the light emitting diode control device includes a bandgap voltage reference configured to generate a current reference for controlling the plurality of lighting modules; a plurality of MOSFET devices connected in parallel and coupled between a cathode of one light emitting diode channel and ground, the MOSFET devices configured to control a current through the light emitting diode channel; and a control circuit configured to generate gate drive signals for the plurality of MOSFET devices, the gate drive signals configured to adjust the current through the light emitting diode channel based on a predetermined color and a predetermined brightness level of the light emitting diode channel.

[0012] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the present disclosure that form the subject of the claims of the present disclosure will be described hereinafter. Those skilled in the art will appreciate that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure as set forth in the appended claims.

[0013] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 illustrates a block diagram of a controller for a light emitting diode system according to various embodiments of the present disclosure. [Figure 2] 2 illustrates multiple PWM generators for controlling the light emitting diodes shown in FIG. 1 according to various embodiments of the present disclosure. [Figure 3] 2 shows a schematic diagram of the control device shown in FIG. 1 according to various embodiments of the present disclosure. [Figure 4] 2 shows a block diagram of the light emitting diode system shown in FIG. 1 according to various embodiments of the present disclosure. [Figure 5] 2 shows a flowchart for controlling the light-emitting diode system shown in FIG. 1 according to various embodiments of the present disclosure. [Figure 6] 1 illustrates the linear relationship between duty cycle and current through a light emitting diode according to various embodiments of the present disclosure. [Figure 7] 1 shows a schematic diagram of a current-mode digital-to-analog converter according to various embodiments of the present disclosure. [Figure 8] 1 illustrates an example of applying a dithering control scheme to a PWM signal according to various embodiments of the present disclosure. [Figure 9]10 illustrates another example of applying a dithering control scheme to a PWM signal according to various embodiments of the present disclosure. [Figure 10] 1 illustrates a flow chart for controlling current through a light emitting diode according to various embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0024] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate relevant aspects of the various embodiments and are not necessarily drawn to scale.

[0016]

[0025] The making and use of presently preferred embodiments are described in detail below. It should be understood, however, that this disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments described are merely illustrative of specific ways to make and use the disclosure and do not limit the scope of the disclosure.

[0017]

[0026] The present disclosure will be described with respect to preferred embodiments in a particular context, namely, an RGB-based LED system. However, the present disclosure may be applied to a variety of LED systems. Various embodiments are described in detail below with reference to the accompanying drawings.

[0018]

[0027] 1 shows a block diagram of a control device for a light-emitting diode system according to various embodiments of the present disclosure. The light-emitting diode system includes multiple lighting modules (e.g., lighting modules 101 and 112). Each lighting module includes a red light-emitting diode channel, a green light-emitting diode channel, and a blue light-emitting diode channel. In some embodiments, there may be 12 lighting modules in the light-emitting diode system.

[0019]

[0028] As shown in FIG. 1 , the first lighting module 101 has three channels. Each channel comprises a light emitting diode. In some embodiments, D0 is a red light emitting diode. D1 is a green light emitting diode. D2 is a blue light emitting diode. The first lighting module 101 is a first RGB module. The second lighting module 112 has three channels. Each channel comprises a light emitting diode. In some embodiments, D33 is a red light emitting diode. D34 is a green light emitting diode. D35 is a blue light emitting diode. The second lighting module 112 is a second RGB module.

[0020]

[0029] 1 shows only two lighting modules of a light emitting diode system that can include hundreds of such lighting modules. The number of lighting modules shown herein is limited solely for purposes of clearly illustrating the inventive aspects of various embodiments. The present disclosure is not limited to any particular number of lighting modules.

[0021]

[0030] The control device 100 is a mixed-signal RGB controller that combines analog dimming and PWM dimming for controlling an array of RGB modules (e.g., lighting modules 101 and 112). The color of a lighting module is generated by setting a color control register for each channel of the lighting module. The brightness of a lighting module is generated by setting a brightness control register for the lighting module. The output of the control device 100 is configured to generate a PWM signal for each channel. In some embodiments, the PWM signal has 12-bit PWM resolution and operates at an ultrasonic frequency of 30 kHz. A high PWM resolution, such as 12-bit PWM resolution, helps the RGB controller achieve a smooth dimming effect. Selecting an ultrasonic operating frequency prevents the RGB controller from generating audible noise.

[0022]

[0031] In operation, the controller 100 is configured to control the current through each of the light emitting diodes shown in Figure 1. By controlling the current through the three channels within the lighting module, the color and brightness of the lighting module can be adjusted accordingly.

[0023]

[0032] As shown in Fig. 1, the control device 100 includes a number of output terminals Out0, Out1, and Out2 to Out33, Out34, and Out35. Each output terminal (e.g., Out0) is connected between a corresponding light-emitting diode (e.g., D0) and ground (not shown, but shown in Fig. 3). Inside the control device 100, a number of functional units are connected to the output terminals (e.g., Out0). The functional units are configured such that the current flowing through a channel (light-emitting diode) of a lighting module (e.g., lighting module 101) is determined based on the color setting and brightness setting for the lighting module.

[0024]

[0033] In some embodiments, the plurality of functional units connected to the output terminal include a bandgap voltage reference, a plurality of MOSFET devices, and a control circuit. The bandgap voltage reference is configured to generate a current reference for controlling a plurality of channels of the light-emitting diode system. The plurality of MOSFET devices are connected in parallel and coupled between the cathodes of the light-emitting diodes and ground via M1 in FIG. 3. The plurality of MOSFET devices are configured to control the current through the light-emitting diodes. The control circuit is configured to generate gate drive signals for the plurality of MOSFET devices. The gate drive signals are configured to achieve a predetermined color and a predetermined brightness level. A detailed schematic diagram of the plurality of functional units is described below in connection with FIG. 3.

[0025]

[0034] Figure 1 shows the I REF Set resistor R connected between the terminal and ground SET The set register R SETis used to set the maximum current through the light emitting diode shown in Figure 1. Capacitor C VCC is connected between the VCC pin and ground. Capacitor C VCC is used to keep the voltage at the VCC terminal constant and stable.

[0026]

[0035] In operation, a lighting module (e.g., lighting module 101) includes a red light-emitting diode channel (e.g., D0), a green light-emitting diode channel (e.g., D1), and a blue light-emitting diode channel (e.g., D2). Based on a predetermined color, the controller 100 determines three digital values ​​for setting the color of the lighting module. The three digital values ​​are stored in three corresponding color registers. In this case, the controller 100 determines a brightness digital value based on a predetermined brightness level and saves the brightness digital value in the brightness register. The controller 100 also multiplies the three digital values ​​for setting the color by the brightness digital value to obtain three PWM signals. These three PWM signals are used to control the currents flowing through the red light-emitting diode channel, the green light-emitting diode channel, and the blue light-emitting diode channel, respectively.

[0027]

[0036] 2 illustrates multiple PWM generators for controlling the light emitting diodes shown in FIG. 1 according to various embodiments of the present disclosure. The current through each light emitting diode is controlled by a PWM signal. In some embodiments, the PWM signal is a typical 12-bit resolution PWM signal generated by the PWM generator.

[0028]

[0037] 2, the color mixing unit is configured to generate a plurality of color control signals according to the color settings of the respective light emitting diodes. In some embodiments, each color control signal is an 8-bit color control signal. The 8-bit color control signal is stored in a corresponding color register.

[0029]

[0038] As shown in FIG. 2, an 8-bit color control signal R0 is used to determine the current through the red light-emitting diode in the first lighting module. An 8-bit color control signal G0 is used to determine the current through the green light-emitting diode in the first lighting module. An 8-bit color control signal B0 is used to determine the current through the blue light-emitting diode in the first lighting module. By configuring these three color control signals, the color of the first lighting module can be determined accordingly. Similarly, an 8-bit color control signal R11 is used to determine the current through the red light-emitting diode in the twelfth lighting module. An 8-bit color control signal G11 is used to determine the current through the green light-emitting diode in the twelfth lighting module. An 8-bit color control signal B11 is used to determine the current through the blue light-emitting diode in the twelfth lighting module. By configuring these three color control signals, the color of the twelfth lighting module can be determined accordingly.

[0030]

[0039] The brightness control unit is configured to generate a plurality of brightness control signals according to brightness settings of the respective lighting modules. In some embodiments, each brightness control signal is an 8-bit brightness control signal. The 8-bit brightness control signal is stored in a corresponding brightness register.

[0031]

[0040] As shown in FIG. 2, the color control signals of the lighting modules are multiplied with the corresponding brightness control signals to generate PWM signals for the lighting modules. For example, the 8-bit color control signal R0 is multiplied with the 8-bit brightness control signal of the first lighting module. The product of this multiplication is a 16-bit signal. The four least significant bits of this product may be omitted depending on design needs. As a result, a 12-bit PWM signal is generated for the red light-emitting diode of the first lighting module. In the embodiment shown in FIG. 3, MG3 may include six typical MOSFET devices controlled by a 6-bit global analog dimming control signal. The gate of each MOSFET device is configured to receive a 12-bit resolution PWM signal from the PWM generator 304 shown in FIG. 3.

[0032]

[0041] 3 shows a schematic diagram of the control device shown in FIG. 1 according to various embodiments of the present disclosure. As shown in FIG. 3, the anode of the light-emitting diode D1 is connected to a power supply Vs. The cathode of the light-emitting diode D1 is connected to an OUT node. The light-emitting diode D1 may be any of the light-emitting diodes shown in FIG. 1. The OUT node is connected to a corresponding output terminal shown in FIG. 1.

[0033]

[0042] The control unit includes a bandgap voltage reference VG, a first amplifier A1, a current mirror formed by MP1 and MP2, and a set resistor R SET a sample and hold circuit 302 formed by switches S1, S2, S3 and capacitor C0; a control circuit 300; a second amplifier A2; a transistor M1; and a plurality of MOSFET device groups MG1, MG2, MG3 and MG4.

[0034]

[0043] In operation, the bandgap voltage reference VG is configured to generate a current reference for controlling multiple light emitting diode channels (e.g., D1 shown in FIG. 3). In some embodiments, the bandgap voltage reference is equal to 700 mV. The bandgap voltage reference is shared by all channels shown in FIG. 3. One advantageous feature of having a single bandgap voltage reference for all light emitting diode channels is that the single bandgap voltage reference helps improve channel-to-channel accuracy. In some embodiments, the channel-to-channel accuracy can be controlled to within 2%. It should be noted that this high channel-to-channel accuracy is achieved without using common trimming options such as fuse trimming.

[0035]

[0044] The plurality of MOSFET device groups MG1, MG2, MG3, and MG4 are connected in parallel and coupled between the cathode of the light-emitting diode D1 and ground via M1 in FIG. 3. The plurality of MOSFET device groups MG1, MG2, MG3, and MG4 are configured to control the current through the light-emitting diode D1. The control circuit 300 is configured to generate gate drive signals for the plurality of MOSFET device groups MG1, MG2, MG3, and MG4. The gate drive signals are configured to adjust the current through the light-emitting diode D1 based on a predetermined color and a predetermined brightness level of the light-emitting diode D1.

[0036]

[0045] As shown in Figure 3, the input of the current mirror MP1 / MP2 is coupled to a bandgap voltage reference VG through a first operational amplifier A1. SET are coupled to a current mirror. As shown in Figure 3, the current mirror comprises a first current mirror transistor MP1 and a second current mirror transistor MP2. The gates of MP1 and MP2 are connected together and to the output of a first operational amplifier A1. The inverting input of the first operational amplifier A1 is connected to a bandgap voltage reference VG. The non-inverting input of the first operational amplifier A1 is connected to a set resistor R SETand the first current mirror transistor MP1.

[0037]

[0046] As shown in FIG. 3, the first current mirror transistor MP1 and the set resistor R SET are connected in series between a bias voltage Vb and ground. A current-to-voltage conversion device is coupled to the output of the current mirror. In some embodiments, the current-to-voltage conversion device is implemented as an auxiliary transistor M2 operating in the triode region. That is, the auxiliary transistor M2 functions as a resistor. As shown in FIG. 3, the auxiliary transistor M2 is connected in series with the second current mirror transistor MP2 between the bias voltage Vb and ground. The gate of the auxiliary transistor M2 is connected to the bias voltage Vb, where Vb is a logic high voltage. Vb is also connected to the gates of the devices in MG1, MG2, MG3, and MG4.

[0038]

[0047] As shown in Figure 3, the second operational amplifier A2 is coupled between the output of the current mirror (the drain of MP2) and the gate of transistor M1. The non-inverting input of the second operational amplifier A2 is connected to the common node of the auxiliary transistor M2 and the second current mirror transistor MP2 via a sample-and-hold circuit 302. The inverting input of the second operational amplifier A2 is connected to the source of transistor M1. The output of the second operational amplifier A2 is connected to the gate of transistor M1.

[0039]

[0048] The plurality of MOSFET device groups includes a first MOSFET device group MG1, a second MOSFET device group MG2, a third MOSFET device group MG3, and a fourth MOSFET device group MG4 connected in parallel between the source of the transistor M1 and ground.

[0040]

[0049] The sample-and-hold circuit 302 includes a first switch S1, a second switch S2, a third switch S3, and a capacitor C0. The first switch S1 is connected between the common node of the auxiliary transistor M2 and the second current mirror transistor MP2 and the non-inverting input of the second operational amplifier A2. The second switch S2 and the third switch S3 are connected in series between the common node of the auxiliary transistor M2 and the second current mirror transistor MP2 and the inverting input of the second operational amplifier A2. The capacitor C0 is connected between the non-inverting input of the second operational amplifier A2 and the common node of the second switch S2 and the third switch S3. The sample-and-hold circuit 302 and the second operational amplifier A2 form an auto-zero amplifier.

[0041]

[0050] In some embodiments, if the PWM signal has a 100% duty cycle, the auto-zero function can be achieved by a duty cycle compensation method. For example, the desired duty cycle is 100%. The PWM signal may have a 97% duty cycle, with the remainder (3%) being used to achieve the auto-zero function provided by the sample-and-hold circuit 302. To compensate for losses caused by duty cycle mismatch (3% duty cycle), a duty cycle compensation current can be used. This duty cycle compensation current can be implemented as a bleed current. This duty cycle compensation current can cover the losses caused by the duty cycle mismatch.

[0042]

[0051] In FIG. 3 , MG3 is a primary channel current regulator that controls approximately 97% of the channel current. MG1, MG2, and MG4 are auxiliary channel current regulators that control approximately 3% of the channel current. MG1 is configured to provide a bleed current. MG1 includes 24 exemplary devices (e.g., MOSFET devices) for 24-bit programming. The gates of each device are configured to receive a DC voltage equal to either 0 V or Vb. MG2 is configured to provide a delay compensation current. MG2 includes six exemplary devices (e.g., MOSFET devices) for 6-bit programming. The gates of each device are configured to receive a DC voltage equal to either 0 V or Vb. MG3 is configured to simultaneously provide 12-bit exemplary PWM dimming and 6-bit exemplary analog dimming. MG3 includes six exemplary devices (e.g., MOSFET devices) for 6-bit analog dimming, and the gates of each device are configured to receive a 12-bit exemplary PWM signal from PWM generator 304. MG4 is configured to provide current precision trimming. MG4 includes four typical devices (eg, MOSFET devices) for 4-bit trimming, with the gate of each device configured to receive a DC voltage equal to either 0V or Vb.

[0043]

[0052] It should be noted that the gates of the MOSFET devices in MG1, MG2, MG3, and MG4 are coupled to Vb when a logic high signal is applied to these gates. In addition, the drains of the MOSFET devices in MG1, MG2, MG3, and MG4 are maintained at a voltage level equal to Vref2. The above gate and drain voltage settings allow for precise control of the current through M1.

[0044]

[0053] In operation, during a PWM OFF phase in which the PWM signal applied to the gate of MG3 has a logic low state, the first switch S1 and the third switch S3 are turned on, and the second switch S2 is turned off. This causes an offset voltage to accumulate on the capacitor C0. During a PWM ON phase in which the PWM signal applied to the gate of MG3 has a logic high state (Vg equals Vb), the first switch S1 and the third switch S3 are turned off, and the second switch S2 is turned on. This causes the voltage stored on the capacitor C0 to be added to the non-inverting input of the second operational amplifier A2, canceling the offset voltage.

[0045]

[0054] In operation, the maximum current through transistor M1 is set by resistor R SET is determined by.

[0046]

[0055] The current flowing through MP1 can be expressed by the following equation: I=VG / R SET (1)

[0047]

[0056] The ratio of the current mirror MP1 / MP2 is 1:m. That is, the current through MP2 is m times greater than the current through MP1. M2 is configured to operate in the triode region, so it acts as a resistor. Let's denote the resistance of M2 as Ron_M2.

[0048]

[0057] The current flowing through MP2 can be expressed by the following equation: Iref=m×VG / R SET (2)

[0049]

[0058] The voltage at the common node between MP2 and M2 is denoted as Vref1. Considering equation (2), Vref1 can be expressed by the following equation:

number

[0050]

[0059] According to the operating principle of the second amplifier A2, Vref2 is equal to Vref1. As shown in Figure 3, there are four MOSFET device groups connected in parallel between Vref2 and ground. The on-resistance of each MOSFET device in the four MOSFET device groups is inversely proportional to the channel width W. Therefore, the maximum current flowing through M1 can be expressed as follows: Imax=Vref2 / Ron_total(4)

[0051]

[0060] In equation (4), Ron_total is the total resistance of the group of four MOSFET devices connected in parallel. In some embodiments, Ron_total is inversely proportional to the equivalent width W_total. The resistance of M2 (Ron_M2) is inversely proportional to the width of M2 (W_2).

[0052]

[0061] Note that W_total is an equivalent width that takes into account the widths of the devices in MG1, MG2, MG3, and MG4. The duty cycle of the devices in MG3 may also be taken into account when calculating W_total. For example, the width of the devices in MG3 is W_MG3. If the duty cycle of the devices in MG3 is 50%, the corresponding width of the devices in MG3 is equal to 0.5 x W_MG3. Additionally, there is a 6-bit analog dimming register that selects the equivalent width W_total from the six devices in MG3.

[0053]

[0062] Considering equation (3), equation (4) can be expressed as follows:

number

[0054]

[0063] In equation (5), m, W_total and W_2 can be replaced by a general parameter K. The maximum current Imax can be simplified as follows:

number

[0055]

[0064] Equation (6) shows that the maximum current flowing through M1 is R SET and the 6-bit analog dimming register that controls the equivalent width W_total of MG3. SET By selecting a different value of Imax, the maximum current through M1 can be varied accordingly. In some embodiments, Imax is equal to 70 mA.

[0056]

[0065] Thus, LED luminance (current) control can be classified as a control method that combines both analog dimming and PWM dimming to control multiple LED channels. Setting Imax according to equation (6) is essentially an analog dimming process, which is achieved by setting the global dimming control signals / registers for MOSFET device groups MG1, MG2, MG3, and MG4. In the analog dimming process, certain MOSFET devices (e.g., the MOSFET devices in MG3) are enabled, while the remaining devices are disabled. When calculating W_total according to equation (5), only those enabled MOSFET devices can contribute to W_total. In the PWM dimming process, only MG3 is controlled by the PWM dimming signal generated by PWM generator 304. Note that in the PWM dimming process, only those enabled MOSFET devices in MG3 are subject to PWM dimming control. As a result, applying PWM dimming to Imax adjusts the current through M1.

[0057]

[0066] In operation, when the signal applied to the gate of M1 instantaneously changes from a low voltage (e.g., 0 V) ​​to a high voltage potential (e.g., the power supply voltage), the time required for the second amplifier A2 to charge the gate of M1 above the turn-on threshold voltage of M1 is finite. This transition introduces a significant amount of error. To avoid this error, a bleed current provided by MG1 is used to keep M1 always on to compensate for this error. In some embodiments, this bleed current is adjustable.

[0058]

[0067] 3, the first MOSFET device group MG1 is controlled by a first global dimming control signal having 24 control bits. Under the first global dimming control signal, the first MOSFET device group MG1 is configured to provide a bleed current to compensate for the finite amount of time used to charge the gate of transistor M1 from a low voltage potential (e.g., 0 V) ​​to a high voltage potential (e.g., a power supply voltage).

[0059]

[0068] In operation, when the PWM signal changes from a low voltage (e.g., 0 V) ​​to a high voltage potential (e.g., the supply voltage) with the bleed current applied, the gate voltage of M1 must change to support the increased current. The increase in current means that the current is the sum of the bleed current and the maximum current set by Equation (6). Also, when a MOSFET device group such as MG3 is turned on, the voltage at node VMG decreases. To maintain Vref2 equal to Vref1, the second operational amplifier A2 must increase the voltage at the gate of M1, thereby increasing the current through M1. The increased current through M1 charges VMG to a level equal to Vref1. Due to various parasitic capacitors coupled to VMG, a delay error may exist. To avoid this delay error, a small current is supplied by MG2 to compensate for this delay error. In particular, the second MOSFET device group MG2 is controlled by a second global dimming control signal having six typical control bits. Under the second global dimming control signal, the second MOSFET device group MG2 is configured to provide a delay compensation current to compensate for the delay error.

[0060]

[0069] In operation, the third MOSFET device group MG3 is controlled by a third global dimming control signal having six control bits. Under the third global dimming control signal, the third MOSFET device group MG3 is configured to provide a PWM current through transistor M1. More specifically, the MOSFET devices in the third MOSFET device group MG3 are selectively enabled by the third global dimming control signal having six control bits. Under the third global dimming control signal, the enabled MOSFET devices in the third MOSFET device group MG3 are configured to provide a PWM current through transistor M1. The PWM current is generated based on a PWM signal generated by PWM generator 304.

[0061]

[0070] During operation, systematic errors due to factors such as layout mismatch between different channels can cause channel-to-channel inaccuracies. These channel-to-channel inaccuracies can be corrected by using trimming options, which allow current to be added to or removed from M1 to minimize channel-to-channel inaccuracies. As shown in FIG. 3 , the fourth MOSFET device group MG4 is controlled by a trimming control signal having six control bits. Under the trimming control signal, the fourth MOSFET device group MG4 is configured to adjust the current through transistor M1 to balance the currents through different channels. In some embodiments, the trimming control signal is input via a suitable digital interface, such as I2C, a universal asynchronous receiver / transmitter (UART), or the like, to adjust the current through transistor M1.

[0062]

[0071] One advantageous feature of having the control device shown in FIG. 3 is the ability to reduce the voltage at the drain of M1. In some embodiments, the voltage at the drain of M1 is as low as 350 mV. Such a low voltage helps reduce power dissipation in the control device. This benefit of reduced power dissipation is achieved by the A2 op amp loop, which regulates the VMG voltage to a precise low value, such as about 200 mV.

[0063]

[0072] It should be noted that Figure 3 is simplified so that only one of many LED channels is shown. In a light-emitting diode system, the first amplifier A1, MP1, and set resistor R SET is unique and shared by all LED channels. Circuit 350 within the dashed rectangle is used to control the current through one of the channels. A detailed implementation of the light emitting diode system is described below with respect to FIG. 4.

[0064]

[0073] It should further be noted that the method for generating Vref1 is very flexible. In some embodiments, the controller can generate a single Vref1 for all channels. Alternatively, the controller may generate a dedicated Vref1 for each channel (e.g., the system configuration shown in FIG. 4). This is a trade-off between design simplicity and matching accuracy. Furthermore, in some embodiments, three reference signals can be used to control all channels. In particular, the controller is configured to generate a first Vref1 shared by all red LED channels. The controller is configured to generate a second Vref1 shared by all green LED channels. The controller is configured to generate a third Vref1 shared by all blue LED channels.

[0065]

[0074] FIG. 4 shows a block diagram of the light emitting diode system shown in FIG. 1 according to various embodiments of the present disclosure. The light emitting diode system includes 36 channels (D0-D35). Each circuit 350 shown in FIG. 4 is used to drive one channel. Each circuit 350 has three inputs connected to Vb, Vg, and Vb, respectively. As shown in FIG. 4, first amplifiers A1, MP1, and R SET is shared by all 36 channels. Vb is the bias voltage. Vg is tapped from the gate of MP1.

[0066]

[0075] It should be noted that Figure 4 shows only 36 channels of a light emitting diode system that can include hundreds of such channels. The number of channels shown herein is limited solely for purposes of clearly illustrating the inventive aspects of various embodiments. The present disclosure is not limited to any particular number of channels.

[0067]

[0076] 5 illustrates a flowchart for controlling the light-emitting diode system shown in FIG. 1 according to various embodiments of the present disclosure. The flowchart illustrated in FIG. 5 is merely an example and should not unduly limit the scope of the claims. Those skilled in the art may recognize many variations, substitutions, and modifications. For example, various steps illustrated in FIG. 5 may be added, deleted, substituted, rearranged, and repeated.

[0068]

[0077] Referring back to FIGS. 1 and 3, the light emitting diode system includes multiple lighting modules (e.g., lighting modules 101 and 112 shown in FIG. 1). Each lighting module includes a red light emitting diode channel, a green light emitting diode channel, and a blue light emitting diode channel. In some embodiments, there may be 12 lighting modules. Each module has three channels. The light emitting diode system includes 36 typical channels.

[0069]

[0078] A light emitting diode controller (e.g., the controller 100 shown in FIG. 1) is used to control the color and brightness of a light emitting diode system. The light emitting diode controller includes a bandgap voltage reference (e.g., VG shown in FIG. 3), a plurality of MOSFET devices (e.g., MG1, MG2, MG3, and MG4 devices shown in FIG. 3), a control circuit (e.g., the controller 100 shown in FIG. 3), and a PWM generator.

[0070]

[0079] The bandgap voltage reference is configured to generate a current reference for controlling multiple light-emitting diode channels in the light-emitting diode system. For each channel, multiple MOSFET devices (e.g., devices MG1, MG2, MG3, and MG4 shown in FIG. 3) are connected in parallel and coupled between the cathode of the light-emitting diode in that channel and ground via M1 in FIG. 3. The multiple MOSFET devices are configured to control the current through the light-emitting diode in that channel. The control circuit is configured to generate gate drive signals for the multiple MOSFET devices. The gate drive signals are configured to adjust the current through the light-emitting diode based on a predetermined color and a predetermined brightness level for the channel.

[0071]

[0080] The following method is used to control brightness and color from a group of red, green, and blue light emitting diode channels in a light emitting diode system.

[0072]

[0081] In step 502, in a lighting module having a red light emitting diode channel, a green light emitting diode channel, and a blue light emitting diode channel, three color digital values ​​are determined based on a predetermined color and stored in three corresponding color registers.

[0073]

[0082] In step 504, based on a predetermined brightness level, a brightness digital value is determined and stored in a brightness register.

[0074]

[0083] In step 506, the three color digital values ​​are multiplied with the brightness digital value to obtain three PWM signals for controlling the currents through the red light emitting diode channel, the green light emitting diode channel, and the blue light emitting diode channel, respectively.

[0075]

[0084] The method further includes determining a maximum current through a red light emitting diode channel, a green light emitting diode channel, and a blue light emitting diode channel by selecting values ​​of a set register; adjusting the maximum current through the red light emitting diode channel, the green light emitting diode channel, and the blue light emitting diode channel by selecting a predetermined set of MOSFET devices; and adjusting the current through one of the red light emitting diode channel, the green light emitting diode channel, and the blue light emitting diode channel with a PWM signal, wherein the PWM signal is configured to modulate the maximum current.

[0076]

[0085] The method further includes applying a bandgap voltage to a set resistor via a first operational amplifier to generate a first reference current; converting the first reference current to a second reference current via a current mirror; converting the second reference current to a first reference voltage by passing the second reference current through an auxiliary transistor operating in the triode region; generating a second reference voltage equal to the first reference voltage via a second operational amplifier; and applying the second reference voltage to a plurality of MOSFET devices connected in parallel and coupled between a cathode of one of the red light emitting diode channel, the green light emitting diode channel, and the blue light emitting diode channel and ground.

[0077]

[0086] A transistor (e.g., M1 in FIG. 3) is connected in series with one of the red, green, and blue light-emitting diode channels (e.g., D1 in FIG. 3). The current mirror includes a first current mirror transistor (e.g., MP1 in FIG. 3) and a second current mirror transistor (e.g., MP2 in FIG. 3) having gates connected to each other and further connected to the output of a first operational amplifier (e.g., A1 in FIG. 3). The first current mirror transistor and a set resistor (e.g., R SET ) are connected in series between a bias voltage (e.g., Vb in Figure 3) and ground. The inverting input of the first operational amplifier is connected to a bandgap voltage (e.g., VG in Figure 3). The non-inverting input of the first operational amplifier is connected to the common node of the set resistor and the first current mirror transistor. An auxiliary transistor (e.g., M2 in Figure 3) operating in the triode region is connected in series with the second current mirror transistor between the bias voltage and ground. The gate of the auxiliary transistor operating in the triode region is connected to the bias voltage. The non-inverting input of the second operational amplifier (e.g., A2 in Figure 3) is connected to the common node of the auxiliary transistor operating in the triode region and the second current mirror transistor via a sample-and-hold circuit (e.g., S1, S2, S3, and C0 in Figure 3). The inverting input of the second operational amplifier is connected to the source of the transistor. The output of the second operational amplifier is connected to the gate of the transistor. The multiple MOSFET devices are from a first MOSFET device group (e.g., MG1 in FIG. 3), a second MOSFET device group (e.g., MG2 in FIG. 3), a third MOSFET device group (e.g., MG3 in FIG. 3), and a fourth MOSFET device group (e.g., MG4 in FIG. 3) connected in parallel between the source of the transistor and ground.

[0078]

[0087] The method further includes applying a first global dimming control signal having 24 control bits to gates of MOSFET devices in the first MOSFET device group to provide bleed current to compensate for a finite amount of time used to charge the gates of the transistors from a low voltage potential to a high voltage potential.

[0079]

[0088] The method further includes applying a second global dimming control signal having six control bits to the gates of the MOSFET devices in the second MOSFET device group to supply a delay compensation current to compensate for delays caused by voltage changes on the gates of the transistors.

[0080]

[0089] The method further includes modulating the maximum current to generate a PWM current through the transistor by applying a PWM signal to a gate of the MOSFET device enabled by a third global dimming control signal having 6 control bits.

[0081]

[0090] The method further includes adjusting the current through the transistors to balance the current through the different channels by applying a trimming control signal having six control bits to the gates of the MOSFET devices in the fourth MOSFET device group.

[0082]

[0091] The sample-and-hold circuit (e.g., sample-and-hold circuit 302 in FIG. 3) includes a first switch (e.g., S1 in FIG. 3), a second switch (e.g., S2 in FIG. 3), a third switch (e.g., S3 in FIG. 3), and a capacitor (e.g., C0 in FIG. 3). The first switch is connected between a common node between the auxiliary transistor (e.g., M2 in FIG. 3) and the second current mirror transistor (e.g., MP2 in FIG. 3) and a non-inverting input of a second operational amplifier (e.g., A2 in FIG. 3). The second and third switches are connected in series between the common node between the auxiliary transistor and the second current mirror transistor and the inverting input of the second operational amplifier. The capacitor is connected between the non-inverting input of the second operational amplifier and the common node between the second switch and the third switch.

[0083]

[0092] The method further includes the steps of: during a PWM off phase, turning on the first switch and the third switch and turning off the second switch to store an offset voltage in a capacitor; and during a PWM on phase, turning off the first switch and the third switch and turning on the second switch to cancel the offset voltage.

[0084]

[0093] 3, multiple MOSFET device groups (e.g., MG1, MG2, MG3, and MG4) are connected in parallel. A first common node (e.g., VMG) of the multiple MOSFET device groups is coupled to the cathode of one light-emitting diode channel (e.g., D1) of multiple light-emitting diode channels (e.g., D0-D2 and D33-D35 shown in FIG. 1). A second common node of the multiple MOSFET device groups is connected to ground.

[0085]

[0094] A control circuit (e.g., control circuit 300) is configured to generate gate drive signals for the plurality of MOSFET device groups. The gate drive signals are configured to adjust the current through the light emitting diode channels based on a predetermined color and a predetermined brightness level of the light emitting diode channels. In particular, an external resistor (e.g., RSET ) is used to set the maximum current (IMAX) flowing through a light-emitting diode channel (e.g., D1). Current control for dimming is achieved by controlling the current flowing through the light-emitting diode channel to be equal to IMAX multiplied by the PWM duty cycle based on a predetermined color and a predetermined brightness level. Based on different current dimming requirements, the PWM duty cycle ranges from 0% to 100%. Under different duty cycles (0% to 100%), the control circuit is configured to control the current flowing through the light-emitting diode channel to be proportional to the corresponding duty cycle.

[0086]

[0095] In some embodiments, the plurality of MOSFET device groups comprises a first MOSFET device group (e.g., MG1), a second MOSFET device group (e.g., MG2), a third MOSFET device group (e.g., MG3), and a fourth MOSFET device group (e.g., MG4) connected in parallel. A first common node VMG of the first MOSFET device group, the second MOSFET device group, the third MOSFET device group, and the fourth MOSFET device group is coupled to the cathode of the light-emitting diode channel D1 via the transistor M1. A second common node of the first MOSFET device group, the second MOSFET device group, the third MOSFET device group, and the fourth MOSFET device group is connected to ground.

[0087]

[0096] In some embodiments, the first MOSFET device group MG1 is configured to provide a bleed current to compensate for duty cycle loss caused by a sample-and-hold circuit (e.g., sample-and-hold circuit 302 shown in FIG. 3). The second MOSFET device group MG2 is configured to provide a delay compensation current to compensate for delays caused by gate voltage changes (e.g., gate voltage changes of M1). The fourth MOSFET device group MG4 is configured to balance currents through different light-emitting diode channels (e.g., different light-emitting diode channels shown in FIG. 1). The MOSFET devices in the third MOSFET device group MG3 are configured to provide PWM currents through the light-emitting diode channels. The PWM currents are generated based on PWM signals generated by a PWM generator (e.g., PWM generator 304).

[0088]

[0097] In operation, the control circuit shown in Figure 3 can maintain a linear relationship between the duty cycle and the current through the light-emitting diode D1. The detailed operating principles of how the control circuit 300 maintains the linear relationship are described below with respect to Figures 6-7.

[0089]

[0098] FIG. 6 illustrates a linear relationship between duty cycle and current through a light-emitting diode according to various embodiments of the present disclosure. The horizontal axis of FIG. 6 represents the PWM duty cycle. The vertical axis of FIG. 6 represents the current through the light-emitting diode. The PWM duty cycle is used to control the current through the light-emitting diode. The current through the light-emitting diode is equal to IMAX multiplied by the PWM duty cycle. In operation, a user can control the current through the light-emitting diode by adjusting the PWM duty cycle.

[0090]

[0099] As shown in Figure 6, the duty cycle ranges from 0% to 100%. To maintain a linear relationship between the duty cycle and the current through the light-emitting diode (e.g., D1 shown in Figure 3), the duty cycle range is divided into two parts: a first duty cycle range and a second duty cycle range. In some embodiments, the first duty cycle range is from 0% to 3%, and the second duty cycle range is from 3% to 100%.

[0091]

[0100] It should be noted that the upper limit (3%) of the first duty cycle range used herein is merely an example and should not unduly limit the scope of the claims. Those skilled in the art may recognize many variations, alternatives, and modifications. Depending on different applications and design needs, the upper limit of the first duty cycle range may vary accordingly.

[0092]

[0101] In a first duty cycle range, the current through the light emitting diode channel is controlled by a linear dimming control scheme. In a second duty cycle range, the current through the light emitting diode channel is controlled by a switching dimming control scheme.

[0093]

[0102] In the switching dimming control scheme, the current flowing through the light-emitting diode channel is a combination of the PWM current flowing through the third MOSFET device group (MG3 in Figure 3) and the bleed current flowing through the first MOSFET device group (MG1 in Figure 3).

[0094]

[0103] At a 100% duty cycle, a portion of the 100% duty cycle is used by the sample and hold circuit 302 to achieve the auto-zero function. To achieve the current corresponding to the 100% duty cycle, a duty cycle compensation method is used to compensate for the current loss during the portion of the 100% duty cycle used by the sample and hold circuit 302. In particular, at a 100% duty cycle, the PWM current flowing through the third MOSFET device group contributes a first predetermined duty cycle (e.g., 97%) of the 100% duty cycle. The duty cycle gap (e.g., 3%) between the first predetermined duty cycle (97%) and the 100% duty cycle is used to achieve the auto-zero function provided by the sample and hold circuit (e.g., the sample and hold circuit 302 shown in FIG. 3). The current mismatch due to the duty cycle gap is compensated for by the bleed current flowing through the first MOSFET device group (MG1 in FIG. 3).

[0095]

[0104] Under the linear dimming control scheme, the current through the LED channel is digitally programmed by a plurality of resistor values. The resistor values ​​are converted to a current through the LED channel via a current-mode digital-to-analog converter. The current-mode digital-to-analog converter may be implemented as the first MOSFET device group MG1 shown in FIG. 3. The detailed structure and operating principle of the current-mode digital-to-analog converter are described below with reference to FIG. 7.

[0096]

[0105] Table 1 shows the control scheme status of the control circuit under different duty cycles. [Table 1]

[0097]

[0106] As shown in Table 1, when the target duty cycle is 3% or less, the duty cycle is contributed by bleed current (e.g., bleed current from the first MOSFET device group MG1 shown in FIG. 3). The duty cycle contributed by the PWM current is equal to 0. In other words, the switches in the third MOSFET device group MG3 are not switching. Because the switches in the third MOSFET device group MG3 are not switching, no switching noise is generated, and therefore the control circuit can maintain a linear relationship between the duty cycle and the current through the light-emitting diodes in the first duty cycle range (0% to 3%). Throughout the description, the first duty cycle range may alternatively be referred to as the low duty cycle range.

[0098]

[0107] The low duty cycle range (0%-3%) shown in Table 1 is merely an example and should not unduly limit the scope of the claims. Those skilled in the art may recognize many variations, alternatives, and modifications. Depending on different applications and design needs, the upper limit of the low duty cycle range may vary accordingly.

[0099]

[0108] Under the linear dimming control scheme, the current flowing through the light-emitting diode channel is supplied by the first MOSFET device group MG1. In other words, the first MOSFET device group MG1 and the associated digital control circuit function as a current-mode digital-to-analog converter. The structure of the current-mode digital-to-analog converter is described below in connection with FIG. 7.

[0100]

[0109] As shown in Table 1, if the target duty cycle is greater than 3%, the target duty cycle is within the second duty cycle range. The target duty cycle includes a fixed duty cycle (3%) contributed by the bleed current (e.g., the bleed current from the first MOSFET device group MG1 shown in FIG. 3) and a PWM duty cycle contributed by the PWM current flowing through the third MOSFET device group MG3 shown in FIG. 3. The duty cycle contributed by the PWM current is equal to the target duty cycle minus 3%. Throughout the description, the second duty cycle range may alternatively be referred to as the high duty cycle range.

[0101]

[0110] FIG. 7 illustrates a schematic diagram of a current-mode digital-to-analog converter according to various embodiments of the present disclosure. In some embodiments, a first MOSFET device group MG1 functions as a current-mode digital-to-analog converter. As shown in FIG. 7, the first MOSFET device group MG1 includes switches M10, M11, M12, M13, M14, and M15 connected in parallel between VMG and ground. In some embodiments, the standard switches have a 1X size. The switches M10, M11, M12, M13, M14, and M15 have 32X, 16X, 8X, 4X, 2X, and 1X sizes, respectively.

[0102]

[0111] As shown in FIG. 7, digital control circuit 700 is used to generate control signals D1, D2, D3, D4, D5, and D6. These control signals are used to control switches M10, M11, M12, M13, M14, and M15, respectively, as shown in FIG. 7. Referring again to FIG. 3, digital control circuit 700 is part of control circuit 300. As indicated by control signals D1-D6, 64 different currents can exist by changing the combination of D1-D6. These 64 different currents can satisfy the resolution step (e.g., 0.2%) shown in Table 1.

[0103]

[0112] Under the switching dimming control method, dithering control technology is used to improve the resolution of PWM control. As mentioned above, the resolution step of the duty cycle is about 0.2%. By using dithering control technology, the resolution step of the duty cycle can be improved to about 1 / 10 of 0.2%. The detailed control method of dithering control technology is shown below with reference to Table 2.

[0104]

[0113] In operation, a control circuit (e.g., the control circuit 300 shown in FIG. 3) is configured to multiply an N-bit color digital value (e.g., an 8-bit color digital value) by an N-bit luminance value (e.g., an 8-bit luminance value) to obtain a 2N-bit control signal (e.g., a 16-bit control signal). M predetermined least significant bits (e.g., four least significant bits) are omitted to obtain a (2N-M)-bit control signal (e.g., a 12-bit control signal). The PWM control signal is determined based on P bits (e.g., nine most significant bits) of the (2N-M)-bit control signal (e.g., the 12-bit control signal). The dithering control signal is determined based on Q bits (e.g., three least significant bits of the 12-bit control signal) of the (2N-M)-bit control signal. The P bits are the P most significant bits of the 2N-bit control signal. The Q bits are bits between the P most significant bits and the M predetermined least significant bits.

[0105]

[0114] Table 2 shows that by using the dithering control technique, the resolution step of the duty cycle can be improved to about 1 / 10 of 0.2%. [Table 2]

[0106]

[0115] It should be noted that in Table 2 above, there is a slight discrepancy between the set value and the actual value of the duty cycle. For example, a 100% duty cycle corresponds to the product of the 8-bit color digital value of FF and the 8-bit luminance digital value of FF. As shown in Table 2, according to the algorithm of the present disclosure, the first 9 bits of the product of the 8-bit color digital value of FF and the 8-bit luminance digital value of FF is 111111100. As shown in Table 2, the decimal value of 111111100 is 508. As is well known for 9-bit digital systems, a decimal value of 512 represents a 100% duty cycle. The decimal value 508 represents a duty cycle of 99.22% (i.e., 99.22% = 508 / 512). In other words, in response to a set duty cycle value of 100%, the actual duty cycle generated by the algorithm of the present disclosure is 99.22%. This small duty cycle discrepancy is due to algorithmic limitations in this 12-bit digital system.

[0107]

[0116] As shown in Table 2, the 8-bit color digital values ​​are in the second column. The 8-bit luminance digital values ​​are in the third column. The products of the 8-bit color digital values ​​multiplied by their respective 8-bit luminance digital values ​​are in the fourth column. The P bits (e.g., the nine most significant bits) of the values ​​are in the fifth column. The Q bits (e.g., the three least significant bits adjacent to the P bit) are in the sixth column. The duty cycle after the dithering control technique is enabled is in the seventh column. Meanwhile, the duty cycle after the dithering control technique is disabled is in the eighth column.

[0108]

[0117] The fifth row of Table 2 is used as an example to explain how the dithering control technique can improve resolution. As shown in Table 2, the 8-bit color digital value is 5B. The 8-bit brightness digital value is B3. The product of the 8-bit color digital value and the 8-bit brightness digital value is 3FA1. The binary representation of 3FA1 is 0011111110100001. The 9 most significant bits are 001111111. As shown in Table 2, the decimal value of 001111111 is 127. The 4 least significant bits are 0001. These 4 least significant bits are omitted. The 3 bits between the 9 most significant bits and the 4 least significant bits are 010. As shown in Table 2, the decimal value of 010 is 2. In other words, the dithering value is equal to 2.

[0109]

[0118] In operation, the 9 most significant bits (001111111) are used for PWM dimming. The equivalent decimal value of 001111111 is 127. With 9 bits, there are 512 cycles. The 9 most significant bits (001111111) indicate that 127 cycles are used as PWM on-time. The remaining 385 cycles are used as PWM off-time. The duty cycle is approximately 25%.

[0110]

[0119] Three bits (e.g., 000-111 shown in Table 2) are used for dithering control. The decimal value range of the three bits is 0 to 7. Therefore, eight PWM pulses are considered as one group.

[0111]

[0120] For the smallest decimal value change of the 9 most significant bits (e.g., 1), the corresponding duty cycle change is 0.19% (i.e., 1 / 512). When dithering control is used and the dithering value is equal to 1, one PWM pulse out of every eight PWM pulses is made one least significant bit longer. Because this variation is applied to one out of every eight consecutive PWM pulses, the finest resolution is equal to 0.024% (i.e., 1 / (512 x 8)).

[0112]

[0121] In the above example (row 5 of Table 2), the dithering value (010) is equal to 2. For eight PWM pulses, the first six PWM pulses have 127 on-time cycles and 385 off-time cycles. The last two PWM pulses of the eight PWM pulses have 128 on-time cycles and 384 off-time cycles. Therefore, the average duty cycle is approximately 25.05%, as shown in Table 2.

[0113]

[0122] 8 illustrates an example of applying a dithering control scheme to a PWM signal according to various embodiments of the present disclosure. In this example, the 8-bit color digital value is 3F. The 8-bit luminance digital value is 1F. The product of the 8-bit color digital value and the 8-bit luminance digital value is 07A1. The binary representation of 07A1 is 0000011110100001. The 9 most significant bits are 000001111. The decimal value of 000001111 is 15. The 4 least significant bits are 0001. These 4 least significant bits are omitted. The 3 bits between the 9 most significant bits and the 4 least significant bits are 010. The decimal value of 010 is 2. In other words, the dithering value is equal to 2.

[0114]

[0123] In operation, the 9 most significant bits (000001111) are used for PWM dimming. The equivalent decimal value is 15. With 9 bits, there are 512 cycles. The 9 most significant bits (000001111) indicate that 15 cycles are used as PWM on time. The remaining 497 cycles are used as PWM off time. The duty cycle is approximately 3%.

[0115]

[0124] Three bits are used for dithering control. The decimal value range of the three bits is 0 to 7. Therefore, eight PWM pulses are considered as one group.

[0116]

[0125] For the smallest decimal value change (e.g., 1) of the 9 most significant bits, the corresponding duty cycle change is 0.19% (i.e., 1 / 512). When dithering control is used and the dithering value is equal to 2, two PWM pulses out of eight PWM pulses are lengthened by one least significant bit. The average duty cycle of these PWM pulses is approximately 3.05%.

[0117]

[0126] 8, the PWM pulse within dashed rectangle 802 has 15 on-time cycles and 497 off-time cycles. The PWM pulse within dashed rectangle 802 is generated based on the most significant bits (000001111) of the 9 bits. Throughout the description, the PWM pulse within dashed rectangle 802 may alternatively be referred to as PWM pulse 802.

[0118]

[0127] The PWM pulse within dashed rectangle 804 has 16 on-time cycles and 496 off-time cycles. Throughout the description, the PWM pulse within dashed rectangle 804 may alternatively be referred to as PWM pulse 804.

[0119]

[0128] The PWM pulses within the dashed rectangle 804 are generated based on a combination of the 9 most significant bits (000001111) and the dithering control. When the dithering value is equal to 2, two PWM pulses out of eight PWM pulses are made longer than one least significant bit. As shown in FIG. 8, there are six consecutive PWM pulses 802 and two PWM pulses 804. These eight PWM pulses constitute a PWM pulse group. The average duty cycle of these PWM pulse groups is approximately 3.05%.

[0120]

[0129] 9 illustrates another example of applying a dithering control scheme to a PWM signal according to various embodiments of the present disclosure. The example illustrated in FIG. 9 is similar to the example illustrated in FIG. 8, except that the dithering value is equal to 1. As illustrated in FIG. 9, there are seven consecutive PWM pulses 802 and one PWM pulse 804. These eight PWM pulses constitute a PWM pulse group. The finest resolution of the duty cycle is equal to 0.024% (i.e., 1 / (512×8)). The average duty cycle of these PWM pulse groups is approximately 3.02%.

[0121]

[0130] 10 illustrates a flowchart for controlling current through a light-emitting diode according to various embodiments of the present disclosure. The flowchart illustrated in FIG. 10 is merely an example and should not unduly limit the scope of the claims. Those skilled in the art may recognize numerous variations, substitutions, and modifications. For example, various steps illustrated in FIG. 10 may be added, deleted, substituted, rearranged, and repeated.

[0122]

[0131] Referring back to FIGS. 1 and 3, the light emitting diode system includes multiple lighting modules (e.g., lighting modules 101 and 112 shown in FIG. 1). Each lighting module includes a red light emitting diode channel, a green light emitting diode channel, and a blue light emitting diode channel. In some embodiments, there may be 12 lighting modules. Each module has three channels. The light emitting diode system includes 36 typical channels.

[0123]

[0132] A light emitting diode controller (e.g., controller 100 shown in FIG. 1) is used to control the color and brightness of a light emitting diode system. The light emitting diode controller includes a bandgap voltage reference (e.g., VG shown in FIG. 3), a plurality of MOSFET devices (e.g., MG1, MG2, MG3, and MG4 devices shown in FIG. 3), a control circuit (e.g., control circuit 300 shown in FIG. 3), and a PWM generator.

[0124]

[0133] For each channel, multiple MOSFET devices (e.g., devices MG1, MG2, MG3, and MG4 shown in FIG. 3) are connected in parallel and coupled between the cathode of the light-emitting diode for that channel and ground via M1 in FIG. 3. The multiple MOSFET devices are configured to control the current through the light-emitting diode for that channel. A control circuit is configured to generate gate drive signals for the multiple MOSFET devices. The gate drive signals are configured to adjust the current through the light-emitting diode based on the predetermined color and predetermined brightness level of the channel.

[0125]

[0134] The following method is used to control brightness and color from a group of red, green, and blue light emitting diode channels in a light emitting diode system.

[0126]

[0135] In step 1002 (FIG. 10), in the low duty cycle range, the current through the light emitting diode channel is controlled to be proportional to the corresponding duty cycle by applying a linear dimming control scheme.

[0127]

[0136] In step 1004 (FIG. 10), in the high duty cycle range, the current through the light emitting diode channel is controlled to be proportional to the corresponding duty cycle by applying a combination of a switching dimming control scheme and a bleed current compensation scheme.

[0128]

[0137] The method further includes multiplying the N-bit color digital value by the N-bit brightness digital value to obtain a 2N-bit control signal; determining a PWM control signal based on a P bit of the 2N-bit control signal under a switching dimming control scheme; and determining a dithering control signal based on a Q bit of the 2N-bit control signal.

[0129]

[0138] The method further includes omitting M least significant bits of the 2N-bit control signal, wherein the sum of P, Q, and M equals 2N, the P bits are the P most significant bits of the 2N-bit control signal, and the Q bits are the bits between the P most significant bits and the M least significant bits.

[0130]

[0139] The method further includes achieving an auto-zero function at 100% duty cycle by a duty cycle compensation method, wherein a first portion of the current corresponding to the 100% duty cycle is provided by a PWM current flowing through the light-emitting diode channel, and a second portion of the current corresponding to the 100% duty cycle is provided by a bleed current flowing through the light-emitting diode channel.

[0131]

[0140] The method further includes configuring a current-mode digital-to-analog converter to convert the plurality of register values ​​into currents through the light-emitting diode channels under a linear dimming control scheme.

[0132]

[0141] According to one embodiment, an apparatus includes: a plurality of MOSFET device groups connected in parallel, a first common node of the plurality of MOSFET device groups coupled to a cathode of one light emitting diode channel among the plurality of light emitting diode channels, and a second common node of the plurality of MOSFET device groups connected to ground; and a control circuit configured to generate gate drive signals for the plurality of MOSFET device groups, the gate drive signals configured to adjust current through the light emitting diode channels based on a predetermined color and a predetermined brightness level of the light emitting diode channels, and under different duty cycles, the control circuit configured to control the current through the light emitting diode channels in proportion to the corresponding duty cycles.

[0133]

[0142] According to another embodiment, a method includes controlling, in a low duty cycle range, a current through a light emitting diode channel in proportion to a corresponding duty cycle by applying a linear dimming control scheme, and controlling, in a high duty cycle range, a current through a light emitting diode channel in proportion to a corresponding duty cycle by applying a combination of a switching dimming control scheme and a bleed current compensation scheme.

[0134]

[0143] According to yet another embodiment, a system includes a plurality of lighting modules, each including a red light emitting diode channel, a green light emitting diode channel, and a blue light emitting diode channel; and a light emitting diode controller, the light emitting diode controller including a plurality of MOSFET device groups connected in parallel, wherein a first common node of the plurality of MOSFET device groups is coupled to the cathodes of the light emitting diode channels of the plurality of lighting modules and a second common node of the plurality of MOSFET device groups is connected to ground; and a control circuit configured to generate gate drive signals for the plurality of MOSFET device groups, the gate drive signals being configured to adjust current through the light emitting diode channels based on a predetermined color and a predetermined brightness level of the light emitting diode channels, and under different duty cycles, the control circuit being configured to control the current through the light emitting diode channels in proportion to the corresponding duty cycles.

[0135]

[0144] Although the embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0136]

[0145] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. As will be readily apparent to those skilled in the art from the present disclosure, any now-existing or later-developed processes, machines, manufacture, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein can be utilized in accordance with the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. The steps include: applying a linear dimming control method in a low duty cycle range to control the current flowing through the light-emitting diode channel in proportion to the corresponding duty cycle; In a high duty cycle range, the current flowing through the light-emitting diode channel is controlled in proportion to the corresponding duty cycle by applying a combination of a switching dimming control method and a bleed current compensation method; The steps include: multiplying an N-bit color digital value by an N-bit luminance digital value to obtain a 2N-bit control signal; Under the switching dimming control method, the steps include determining a PWM control signal based on the P bit of the 2N bit control signal, The steps include determining a dithering control signal based on the Q bit of the 2N-bit control signal, Methods that include...

2. The step further includes omitting the M least significant bits of the 2N-bit control signal, The sum of P, Q, and M is equal to 2N. The P bits are the P most significant bits of the 2N-bit control signal. The Q bit is a bit between the P most significant bits and the M least significant bits. The method according to claim 1.

3. The step of omitting the M least significant bits is The step of omitting the four least significant bits when the N-bit color digital value and the N-bit luminance digital value are each 8 bits, thereby obtaining a 12-bit control signal used for PWM control, is included. The method according to claim 2.

4. The Q bit used for dithering control is a set of three bits immediately adjacent to the P most significant bits of the 12-bit control signal. The method according to claim 3.

5. The process further includes the step of achieving an auto-zero function through a duty cycle compensation method in a 100% duty cycle, The first portion of the current corresponding to the 100% duty cycle is provided by the PWM current flowing through the light-emitting diode channel. The second portion of the current corresponding to the 100% duty cycle is provided by the bleed current flowing through the light-emitting diode channel. The method according to claim 1.

6. The duty cycle compensation method described above is The steps include allocating a portion of the duty cycle for the auto-zero function provided by the sample-and-hold circuit, The steps include compensating for the resulting current mismatch using the bleed current, The method according to claim 5, including the method described in claim 5.

7. The bleed current is provided by the first MOSFET device group. The PWM current is provided by a third MOSFET device group. The first MOSFET device group and the third MOSFET device group are connected in parallel between the cathode and ground of the light-emitting diode channel. The method according to claim 5.

8. Under the linear dimming control method, the step of configuring a current-mode digital-to-analog converter to convert a plurality of register values ​​into the current flowing through the light-emitting diode channel is The method according to claim 1, further comprising:

9. The low duty cycle range includes duty cycles from 0% to 3%. The aforementioned high duty cycle range includes duty cycles exceeding 3%, The method according to claim 1.

10. The linear dimming control method is This includes digitally programming a current-mode digital-to-analog converter to generate a current flowing through the light-emitting diode channel based on multiple register values, The method according to claim 1.

11. A step to generate a predetermined color by determining three color digital values ​​for each red, green, and blue light-emitting diode channel and storing each color digital value in the corresponding color register. The method according to claim 1, further comprising:

12. A step of determining a digital luminance value based on a predetermined luminance level, The steps include storing the aforementioned digital luminance value in a luminance register, The method according to claim 1, further comprising:

13. The step of providing a delay-compensating current using a second group of MOSFET devices to compensate for the delay caused by gate voltage changes in the transistor that controls the current flowing through the light-emitting diode channel. The method according to claim 1, further comprising:

14. In a multi-channel system, a step of trimming the current flowing through the light-emitting diode channel using a fourth MOSFET device group in order to balance the current between multiple channels. The method according to claim 1, further comprising:

15. The step of setting the maximum current of the light-emitting diode channel by selecting the value of a set register coupled to the current mirror. The method according to claim 1, further comprising:

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