Image pickup device

Abstract

To improve an image quality of an image pickup device.SOLUTION: An image pickup device comprises: a first substrate that has a first pixel including a first photoelectric conversion part and a second pixel including a second photoelectric conversion part; a wiring layer having a first signal line connected to the first pixel and outputting a first signal based on an electric charge converted by the first photoelectric conversion part, and a second signal line connected to the second pixel and outputting a second signal based on the electric charge converted by the second photoelectric conversion part; and a second substrate laminated together with the first substrate and including a readout part including a first processing part that performs signal processing on the first signal output to the first signal line and a second processing part that performs signal processing on the second signal output to the second signal line, the second substrate including a first supply part that controls a voltage of the first signal line and a second supply part that controls a voltage of the second signal line. The wiring layer is disposed between the first substrate and the second substrate in a lamination direction, and the readout part is disposed at a position facing one of the first pixel and the second pixel in the lamination direction.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an imaging device. [Background technology]

[0002] There is known an imaging element in which a transistor for clamping a signal output from a pixel to a predetermined voltage level is provided for each column (Patent Document 1). Improvements in image quality have been desired for some time. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2004-222273 Summary of the Invention

[0004] According to a first aspect, an imaging element includes a first substrate having first pixels including first photoelectric conversion units that convert light into electric charges and second pixels including second photoelectric conversion units that convert light into electric charges; a wiring layer having first signal lines electrically connected to the first pixels and outputting first signals based on the electric charges converted by the first photoelectric conversion units, and second signal lines electrically connected to the second pixels and outputting second signals based on the electric charges converted by the second photoelectric conversion units; and a substrate laminated together with the first substrate, which receives a signal from the first signal output to the first signal lines. the wiring layer is disposed between the first substrate and the second substrate in a stacking direction in which the first substrate and the second substrate are stacked, and the readout unit is disposed at a position facing at least one of the first pixel and the second pixel in the stacking direction. [Brief explanation of the drawings]

[0005] [Figure 1] 1 is a diagram illustrating an example of the configuration of an imaging device according to a first embodiment. [Figure 2] 1 is a block diagram showing an example of the configuration of an imaging element according to a first embodiment. [Figure 3] 1 is a diagram showing an example of a cross-sectional structure of a part of an imaging element according to a first embodiment. [Figure 4] 1 is a diagram illustrating an example of the configuration of a portion of an imaging element according to a first embodiment. [Figure 5] 4 is a timing chart showing an example of the operation of the imaging element according to the first embodiment. [Figure 6] 4 is a timing chart showing an example of the operation of the imaging element according to the first embodiment. [Figure 7] FIG. 2 is a diagram showing an example of a layout of a part of an imaging element according to the first embodiment. [Figure 8] FIG. 10 is a block diagram showing an example of the configuration of an imaging element according to a modified example. [Figure 9] FIG. 10 is a block diagram showing another example of the configuration of an imaging element according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0006] (First embodiment) 1 is a diagram showing an example of the configuration of a camera 1, which is an example of an imaging device according to a first embodiment. The camera 1 includes a photographing optical system (imaging optical system) 2, an image sensor 3, a control unit 4, a memory 5, a display unit 6, and an operation unit 7. The photographing optical system 2 has multiple lenses, including a focus adjustment lens (focus lens), and an aperture stop, and forms a subject image on the image sensor 3. The photographing optical system 2 may be detachable from the camera 1.

[0007] The imaging element 3 is an imaging element such as a CMOS image sensor or a CCD image sensor. The imaging element 3 receives a light beam that has passed through the photographing optical system 2 and captures an image of a subject formed by the photographing optical system 2. The imaging element 3 has a plurality of pixels, each having a photoelectric conversion unit, arranged two-dimensionally (in the row and column directions). The photoelectric conversion unit is composed of a photodiode (PD). The imaging element 3 photoelectrically converts the received light to generate a signal and outputs the generated signal to the control unit 4.

[0008] The memory 5 is a recording medium such as a memory card. Image data, control programs, etc. are recorded in the memory 5. Writing data to the memory 5 and reading data from the memory 5 are controlled by the control unit 4. The display unit 6 displays an image based on the image data, information related to shooting such as the shutter speed and aperture value, and a menu screen, etc. The operation unit 7 includes various setting switches such as a release button, a power switch, and switches for switching between various modes, and outputs signals to the control unit 4 based on the respective operations.

[0009] The control unit 4 is configured with a processor such as a CPU, FPGA, or ASIC, and memories such as a ROM or RAM, and controls each unit of the camera 1 based on a control program. The control unit 4 supplies a signal that controls the image sensor 3 to the image sensor 3, thereby controlling the operation of the image sensor 3. When taking a still image, taking a video, or displaying a through image (live view image) of the subject on the display unit 6, the control unit 4 causes the image sensor 3 to capture an image of the subject and output a signal.

[0010] The control unit 4 generates image data by performing various types of image processing on the signal output from the imaging element 3. The control unit 4 also functions as a generation unit 4 that generates image data, and generates still image data and moving image data based on the signal output from the imaging element 3. The image processing includes image processing such as tone conversion processing and color interpolation processing.

[0011] 2 is a block diagram showing an example of the configuration of an image sensor according to the first embodiment. The image sensor 3 is configured by stacking a first substrate 111 on which a plurality of pixels 10 are provided and a second substrate 112 on which a supply unit 30 and a readout unit 60 are provided. The first substrate 111 and the second substrate 112 are each configured using a semiconductor substrate. The circuit provided on the first substrate 111 and the circuit provided on the second substrate 112 are electrically connected by connecting units such as electrodes and bumps.

[0012] The first substrate 111 has a plurality of regions 20 in which a plurality of pixels 10 are respectively arranged. In the example shown in FIG. 2, four regions 20 are illustrated. Each of these four regions 20 represents one region when the region in which the pixels 10 of the first substrate 111 are arranged is divided into regions each including a predetermined number of pixels. Note that the regions 20 may or may not partially overlap. The number of pixels in each region 20 may be four pixels (2 pixels x 2 pixels), or may be 16 pixels (4 pixels x 4 pixels), or may be any number. Hereinafter, the regions 20 are referred to as pixel blocks 20.

[0013] The imaging element 3 is provided with a signal line 22 and a supply unit 30 (described later) for each pixel block 20. As will be described later, the imaging element 3 is also provided with a pixel control unit and a supply control unit for each pixel block 20. The signal line 22 is a signal line that connects the pixel block 20 with the readout unit 60, and outputs a signal from the pixel 10. The signal line 22 is a signal line that uses a connection unit such as an electrode or a bump.

[0014] The readout unit 60 has a processing unit 50 including an analog-to-digital conversion unit (AD conversion unit) 40. A processing unit 50 is provided for each pixel block 20. In the image sensor 3 according to this embodiment, pixel signals are read out in parallel from a plurality of pixel blocks 20 using signal lines 22 provided for each pixel block 20. The readout unit 60 outputs the pixel signals of each pixel block 20 simultaneously (in parallel) to the processing unit 50 provided for each pixel block 20, so that the pixel signals can be simultaneously processed in each processing unit 50. Since each processing unit 50 simultaneously processes the signals output from each pixel block 20, the readout unit 60 can perform high-speed signal processing.

[0015] The AD conversion unit 40 of the processing unit 50 converts the pixel signals, which are analog signals input from each pixel 10 in the pixel block 20 via the signal line 22, into digital signals. The processing unit 50 may also have an amplifier unit that amplifies the pixel signals input via the signal line 22 by a predetermined gain (amplification factor). In this case, the AD conversion unit 40 converts the pixel signals amplified by the amplifier unit into digital signals.

[0016] The pixel signals converted into digital signals are subjected to signal processing such as correlated double sampling (CDS) and signal amount correction in the processing unit 50, and then output to the control unit 4 of the camera 1. Note that signal processing such as correlated double sampling on the pixel signals may be performed in a signal processing unit (not shown). In this case, the processing unit 50 outputs the pixel signals converted into digital signals by the AD conversion unit 40 to the signal processing unit. The signal processing unit performs signal processing such as correlated double sampling on the input pixel signals, and then outputs the processed pixel signals to the control unit 4.

[0017] A plurality of electrodes (pads) 200 to which a power supply voltage VDD is supplied (applied) are provided around the area in which each pixel 10 is arranged on the first substrate 111. The electrodes 200 are connected to the plurality of pixels 10 arranged on the first substrate 111 via wiring 121. The power supply voltage VDD is supplied to the pixels 10 via the wiring 121. As shown in FIG. 2 , the image sensor 3 is also provided with wiring 125 and wiring 126. The wiring 125 penetrates the first substrate 111. The wiring 126 connects the wiring 121 of the first substrate 111 to the wiring 122 of the second substrate 112. The wiring 125 and wiring 126 are each formed using an electrode, a bump, or the like. The electrode 200 is connected to a plurality of supply units 30 disposed on the second substrate 112 via the wiring 125 and wiring 122. The electrode 200 is also connected to a plurality of supply units 30 via the wiring 121, wiring 126, and wiring 122. The supply unit 30 is supplied with a power supply voltage VDD via the wiring 125 and wiring 122, and is also supplied with a power supply voltage VDD via the wiring 121 and wiring 126. The electrode 200 is an electrode common to a plurality of pixels 10 and the supply units 30, and is disposed on one surface of the first substrate 111 as shown in FIG. 2 . The configuration of the imaging element 3 according to this embodiment will be further described below with reference to the drawings.

[0018] Fig. 3 is a diagram showing an example of a cross-sectional structure of a portion of the image sensor according to the first embodiment. Fig. 4 is a diagram showing an example of the configuration of a portion of the image sensor according to the first embodiment. The image sensor 3 shown in Fig. 3 is a back-illuminated image sensor. The image sensor 3 includes a first substrate 111, a wiring layer 101 provided by being stacked on the first substrate 111, a second substrate 112, and a wiring layer 102 provided by being stacked on the second substrate 112. The wiring layer 101 and the wiring layer 102 are each a wiring layer including a conductor film (metal film) and an insulating film, and a plurality of wires, vias, interlayer insulating films, etc. are arranged therein.

[0019] Light from a subject is incident in the positive direction of the Z axis in FIG. 3 . Also, as shown by the coordinate axes in FIG. 3 , the rightward direction of the paper, perpendicular to the Z axis, is the positive X axis, and the forward direction of the paper, perpendicular to the Z axis and the X axis, is the positive Y axis. In the following figures, coordinate axes may be displayed based on the coordinate axes in FIG. 3 to clarify the orientation of each figure. On the first substrate 111 and the wiring layer 101, a plurality of pixel blocks 20, each including a plurality of pixels 10, are arranged in the X-axis and Y-axis directions. On the second substrate 112 and the wiring layer 102, a plurality of supply units 30 and a plurality of processing units 50 are arranged in the X-axis and Y-axis directions. In the image sensor 3, the wiring 126 is provided between the pixel 10 and the supply unit 30. It can also be said that the wiring 126 is provided between the photoelectric conversion unit 11 and the supply unit 30. In the example shown in FIG. 3 , the wiring 126 is arranged parallel to the signal line 22.

[0020] 4 shows some of the pixels 10 provided in the image sensor 3, some of the current sources 25 and supply units 30, some of the pixel control units 35 and supply control units 36, and a readout control unit 70. The current sources 25 and supply units 30 are provided for the signal lines 22. The pixel control units 35 and supply control units 36 are each arranged for each pixel block 20. Note that, to simplify the drawing, only one pixel 10 per pixel block 20 is shown in FIG. 4.

[0021] The pixel 10 includes a photoelectric conversion unit 11, a transfer unit 12, a floating diffusion (FD) 13, a reset unit 14, an amplifier unit 15, and a selection unit 16. The photoelectric conversion unit 11 is a photodiode PD, which converts incident light into electric charges and accumulates the photoelectrically converted electric charges.

[0022] The transfer unit 12 is composed of a transistor M1 controlled by a signal TX, and transfers the charges photoelectrically converted by the photoelectric conversion unit 11 to the FD13. The transistor M1 is a transfer transistor. The FD13 accumulates (holds) the charges transferred to the FD13 and converts them into a voltage divided by a capacitance value. The FD13 is an accumulation unit 13, and accumulates the charges generated by the photoelectric conversion unit 11.

[0023] The amplifier unit 15 is composed of a transistor M3 whose gate (terminal) is connected to the FD13, and amplifies and outputs a signal based on the charge accumulated in the FD13. The drain (terminal) of the transistor M3 is connected to the electrode 200 (see FIG. 2) via a wiring (power supply line) 121, and is supplied with a power supply voltage VDD. The source (terminal) of the transistor M3 is connected to a signal line 22 via a selection unit 16. The amplifier unit 15 functions as part of a source follower circuit, with a current source 25 as a load current source. The transistor M3 is an amplifying transistor. The amplifier unit 15 and the selection unit 16 constitute an output unit that generates and outputs a signal based on the charge generated by the photoelectric conversion unit 11.

[0024] The reset unit 14 is composed of a transistor M2 controlled by a signal RST, and electrically connects or disconnects the FD13 and the power supply line 121. The reset unit 14 resets the charge accumulated in the FD13. The reset unit 14 discharges the charge accumulated in the FD13 and resets the voltage of the FD13. The transistor M2 is a reset transistor. The selection unit 16 is composed of a transistor M4 controlled by a signal SEL, and electrically connects or disconnects the amplifier unit 15 and the signal line 22. When the transistor M4 of the selection unit 16 is in the on state, it outputs a signal from the amplifier unit 15 to the signal line 22. The transistor M4 is a selection transistor.

[0025] The current source 25 includes a transistor M5 to whose gate a signal VB is input. The current source 25 is connected to each pixel 10 of the pixel block 20 and the supply unit 30 via a signal line 22. The current source 25 generates a current based on the signal level of the signal VB and supplies the generated current to the signal line 22, the pixel 10, and the supply unit 30. The current source 25 may be configured with two cascode-connected transistors. The signal VB is generated by a signal generation unit (not shown). The signal generation unit is commonly connected to the current sources 25 provided for each signal line 22 and supplies the signal VB to each current source 25. The gates of the transistors M5 of each current source 25 are electrically connected to each other and receive the signal VB from the signal generation unit.

[0026] A signal (dark signal) obtained when the voltage of the FD 13 is reset and a signal (photoelectric conversion signal) based on the charges transferred from the photoelectric conversion unit 11 to the FD 13 by the transfer unit 12 are sequentially output to the signal line 22. The dark signal is used to remove noise contained in the photoelectric conversion signal. The dark signal can also be considered an analog signal indicating a reference level for the photoelectric conversion signal, and is used to correct the photoelectric conversion signal. The photoelectric conversion signal is an analog signal generated based on the charges photoelectrically converted by the photoelectric conversion unit 11. The dark signal and the photoelectric conversion signal are input to a processing unit 50 (see FIG. 2 ) of the readout unit 60 via the signal line 22. In this embodiment, the processing unit 50 has a calculation unit that performs subtraction between the photoelectric conversion signal and the dark signal, and performs CDS by subtracting the photoelectric conversion signal from the dark signal to remove noise components from the photoelectric conversion signal.

[0027] As shown in Fig. 4, the supply unit 30 has a signal output unit 31 and a switch unit 32, and has the function of supplying a voltage to the signal line 22. The signal output unit 31 is composed of a transistor M11 to whose gate a signal CLIP is input, and generates and outputs a signal of a voltage level based on the signal CLIP. The drain of the transistor M11 is connected to the electrode 200 (see Fig. 2) via a power supply line 122, and is supplied with a power supply voltage VDD. The source of the transistor M11 is connected to the signal line 22 via the switch unit 32.

[0028] The switch unit 32 is composed of a transistor M12 controlled by a signal CLIP_SW, and electrically connects or disconnects the signal output unit 31 and the signal line 22. When the transistor M12 of the switch unit 32 is in an on state, it can output a signal from the signal output unit 31 to the signal line 22. In this embodiment, when the switch unit 32 is in an on state, the signal output unit 31 limits the voltage (potential) of the signal line 22 to a value within a range with a voltage based on the signal CLIP as the lower limit. The supply unit 30 supplies a voltage to the signal line 22 so that the voltage of the signal line 22 does not fall below a predetermined voltage. The supply unit 30 can also be said to be a limiting unit 30 that limits the voltage of the signal line 22. The supply unit 30 supplies a voltage to the signal line 22 so that the voltage of the signal line 22 falls within a range from the power supply voltage VDD to the voltage based on the signal CLIP, and can also be said to control (adjust) the voltage of the signal line 22.

[0029] The pixel control unit 35 includes a switch and a buffer, and is controlled by the readout control unit 70. The pixel control unit 35 supplies signals such as the above-mentioned signal TX, signal RST, and signal SEL to the pixels 10 in the pixel block 20 to control the operation of each pixel 10. The pixel control unit 35 supplies signals to the gates of each transistor in the pixels 10 to turn the transistor on (connected, conductive, short-circuited) or off (disconnected, non-conductive, open, blocked).

[0030] The readout control unit 70 and pixel control unit 35 control the period during which charge is accumulated in the pixel blocks 20 and the timing for reading out pixel signals by controlling signals such as signals TX and SEL input to the pixels 10. The pixel control unit 35 provided for each pixel block 20 can control the pixels 10 so that the charge accumulation time varies for each pixel block 20, or can control the pixels 10 so that the charge accumulation time is the same for all pixel blocks 20. Each pixel control unit 35 can also control the pixels 10 so that the timing for reading out pixel signals varies for each pixel block 20, or can control the pixels 10 so that the timing for reading out pixel signals is the same for all pixel blocks 20. By controlling the pixels 10 so that the charge accumulation time varies for each pixel block 20, even if there are multiple subjects, it is possible to capture images tailored to the brightness of each subject. By controlling the pixels 10 so that the timing for reading out pixel signals varies for each pixel block 20, it is possible to capture images tailored to the moving speed of each subject, even if there are multiple subjects.

[0031] The supply control unit 36 ​​includes a switch and a buffer and is controlled by the readout control unit 70. As described above, the pixel control unit 35 can control the pixels 10 so that the charge accumulation time differs for each pixel block 20 and so that the timing of reading out the pixel signals differs for each pixel block 20. In this case, the timing at which a signal is output to the signal line 22 differs for each block 20, so the supply control unit 36 ​​must control the operation of each switch unit 32 for each pixel block 20. The supply control unit 36 ​​supplies the above-mentioned signal CLIP_SW to the switch unit 32 of each pixel block 20 to control the operation of each switch unit 32. The supply control unit 36 ​​controls the on / off of the switch unit 32 to start and stop supplying voltage from the signal output unit 31 to the signal line 22. In this embodiment, the supply control unit 36 ​​provided for each pixel block 20 adjusts the timing at which voltage is supplied from the signal output unit 31 to the signal line 22 based on the timing at which the dark signal and photoelectric conversion signal are read out in the pixel block 20. For example, the supply control unit 36 ​​provided for each pixel block 20 controls the switch unit 32 so that voltages can be supplied at different timings to the signal lines 22 provided for a certain pixel block 20 and the signal lines 22 provided for other pixel blocks 20. Note that each supply control unit 36 ​​may also control each switch unit 32 so that voltages can be supplied at the same timing to all pixel blocks 20.

[0032] The read control unit 70 is provided in common to multiple pixel blocks 20. The read control unit 70 is configured with multiple circuits including a timing generator, and is disposed on the second substrate 112. The read control unit 70 is controlled by the control unit 4 of the camera 1. The read control unit 70 controls the operation of the pixels 10 by controlling signals such as the signal TX, the signal RST, and the signal SEL that are input to the pixels 10 via the pixel control unit 35. The read control unit 70 also controls the operation of the supply unit 30 by controlling the signal CLIP_SW that is input to the supply unit 30 via the supply control unit 36.

[0033] The supply control unit 36 ​​described above is disposed on the second substrate 112. The pixel control unit 35 may be disposed on either the first substrate 111 or the second substrate 112, or may be divided between the first substrate 111 and the second substrate 112. The pixel control unit 35 may be disposed on a substrate different from the first substrate 111 and the second substrate 112. The readout control unit 70 may be divided between the first substrate 111 and the second substrate 112, or may be disposed on the first substrate 111. The readout control unit 70 may be disposed on a substrate different from the first substrate 111 and the second substrate 112.

[0034] When the selection unit 16 of the pixel 10 and the switch unit 32 of the supply unit 30 are both turned on, the source of the amplifier unit 15 and the source of the signal output unit 31 are electrically connected to the signal line 22. In this case, the path through which the current from the current source 25 connected to the signal line 22 flows changes based on the magnitude relationship between the voltage at the gate of the amplifier unit 15 (i.e., the voltage of FD13) and the voltage at the gate of the supply unit 30 (i.e., the voltage of the signal CLIP).

[0035] When the voltage of FD13 is higher than the voltage of signal CLIP, the current of current source 25 flows mainly via signal line 22 and selector 16 to amplifier 15. Amplifier 15 outputs a signal based on the voltage of FD13 to signal line 22. As a result, the voltage of signal line 22 becomes a voltage corresponding to the voltage of FD13. When the voltage of FD13 is lower than the voltage of signal CLIP, the current of current source 25 flows mainly via signal line 22 and switch 32 to signal output unit 31. At this time, signal output unit 31 outputs a signal based on the voltage of signal CLIP to signal line 22, thereby limiting the voltage of signal line 22 to a voltage based on the voltage of signal CLIP. The voltage of signal line 22 becomes a voltage corresponding to the voltage of signal CLIP.

[0036] In this way, when the switch unit 32 is in the ON state, the supply unit (limiting unit) 30 limits the voltage of the signal line 22 according to the voltage of the FD 13 and the voltage of the signal CLIP. The transistor M11 of the supply unit 30 is a transistor that limits (clips) the voltage of the signal line 22, and is sometimes referred to as a clipping transistor or a clamping transistor. When the voltage of the FD 13 is relatively low, the voltage of the signal line 22 is limited to a voltage based on the signal CLIP. This makes it possible to prevent the voltage of the signal line 22 from dropping and causing the current source 25 to malfunction. As a result, it is possible to prevent the current source 25 from failing to supply current. It is also possible to prevent the voltage of the signal line 22 from exceeding the expected range and being input to the readout unit 60.

[0037] Furthermore, in the image sensor 3 according to the present embodiment, the signal CLIP having a different signal level when reading out a dark signal and when reading out a photoelectric conversion signal is input to the supply unit 30. This allows the supply unit 30 to supply different voltages to the signal line 22 when reading out a dark signal and when reading out a photoelectric conversion signal.

[0038] When reading out a dark signal, a first voltage V1 is supplied to the gate of the transistor M11 of the signal output unit 31. In this case, the voltage of the signal line 22 is limited so that a voltage based on the first voltage V1 is its lower limit. This limits the voltage of the signal output to the readout unit 60 as a dark signal. When reading out a photoelectric conversion signal, a second voltage V2 lower than the first voltage V1 is supplied to the gate of the transistor M11. In this case, the voltage of the signal line 22 is limited so that a voltage based on the second voltage V2 is its lower limit. This limits the voltage of the signal output to the readout unit 60 as a photoelectric conversion signal.

[0039] Charge may accumulate in the FD13 due to pixel defects, resulting in a decrease in the voltage of the dark signal. When photographing a highly luminous subject, charge may accumulate in the FD13, resulting in a decrease in the voltage of the dark signal. In such cases, the difference between the dark signal and the photoelectric conversion signal may become small, which may result in a decrease in the quality of the image generated using the signal after CDS processing. In this embodiment, the voltage of the dark signal is limited as described above, thereby ensuring a difference between the signal level of the dark signal and the signal level of the photoelectric conversion signal. This makes it possible to prevent a decrease in image quality due to a decrease in the difference between the dark signal and the photoelectric conversion signal.

[0040] The second voltage V2 is determined so that the voltage of the signal line 22 does not drop below the voltage required for the operation of the transistor M5 of the current source 25 and can be as low as possible. This makes it possible to prevent the voltage of the signal line 22 from changing when the charge generated in the photoelectric conversion unit 11 is transferred to the FD 13. Furthermore, it is possible to prevent fluctuations in the current of the current source 25 and prevent noise from being mixed into the photoelectric conversion signal output to the signal line 22.

[0041] 5 and 6 are timing charts each showing an example of the operation of the image sensor 3 according to the first embodiment. In the timing charts shown in FIGS. 5 and 6, the vertical axis indicates the voltage level of the signal, and the horizontal axis indicates time. FD indicates the signal (voltage signal) of the FD 13, and VOUT indicates the signal output to the signal line 22. In the example shown in FIGS. 5 and 6, the signal CLIP_SW is set to a high level, and the switch unit 32 of the supply unit 30 is turned on. In FIGS. 5 and 6, transistors receiving a high-level (e.g., power supply voltage VDD) control signal (signal SEL, signal RST, signal TX) are turned on, and transistors receiving a low-level (e.g., ground voltage) control signal are turned off.

[0042] At time t1 shown in FIG. 5, signal RST goes high, turning on transistor M2 of the reset unit 14 of pixel 10 and electrically connecting FD13 to the power supply line 121. This resets the charge in FD13 and the voltage of FD13 becomes the reset voltage. Also at time t1, signal SEL goes high, turning on transistor M4 of the selection unit 16. This enables the amplifier unit 15 and selection unit 16 to output a signal based on the reset voltage of pixel 10, i.e., a signal after the charge in FD13 of pixel 10 has been reset, to signal line 22. At time t2, signal RST goes low, turning off transistor M2 of the reset unit 14.

[0043] The signal CLIP of the first voltage V1 is input to the signal output unit 31 of the supply unit 30, and the signal output unit 31 is in a state where it can supply a voltage based on the first voltage V1 (a clip voltage Vc1 indicated by a dashed line in FIG. 5) to the signal line 22. In the example shown in FIG. 5, during the period from time t2 to time t3, the voltage of the FD13 (the voltage of the FD shown in FIG. 5) is higher than the first voltage V1, which is the voltage of the signal CLIP. Therefore, the voltage of the signal VOUT output to the signal line 22 is a voltage based on the voltage of the FD13, i.e., a voltage based on the reset voltage after the charge accumulated in the FD13 is reset.

[0044] At time t3, the processing unit 50 of the readout unit 60 samples the signal VOUT, which has a voltage based on the reset voltage, as a dark signal. It can be said that the voltage of the dark signal is determined at time t3. The AD conversion unit 40 of the processing unit 50 converts the dark signal into a digital signal. At time t4, the signal CLIP, which has a second voltage V2 lower than the first voltage V1, is input to the signal output unit 31. The voltage of the signal CLIP changes from the first voltage V1 to the second voltage V2, and the signal output unit 31 is ready to supply a voltage based on the second voltage V2 (the clip voltage Vc2 indicated by the dashed line in FIG. 5) to the signal line 22.

[0045] At time t5, signal TX goes high, turning on transistor M1 of transfer unit 12 and transferring the charges photoelectrically converted by photoelectric conversion unit 11 to FD 13. As a result, the voltage of FD 13 becomes a voltage based on the charges transferred from photoelectric conversion unit 11. Also, because signal SEL is high, amplifier 15 and selector 16 are able to output a signal based on the charges generated by photoelectric conversion unit 11 to signal line 22. At time t6, signal TX goes low, turning off transistor M1 of transfer unit 12.

[0046] 5, during the period from time t6 to time t7, the voltage of FD13 is higher than the second voltage V2, which is the voltage of signal CLIP. Therefore, the voltage of signal VOUT output to signal line 22 is a voltage based on the voltage of FD13, i.e., a voltage based on the charge photoelectrically converted by photoelectric conversion unit 11.

[0047] At time t7, the processing unit 50 samples the signal VOUT, which is a voltage based on the charges photoelectrically converted by the photoelectric conversion unit 11, as a photoelectric conversion signal. It can also be said that the voltage of the photoelectric conversion signal is determined at time t7. The AD conversion unit 40 of the processing unit 50 converts the photoelectric conversion signal into a digital signal. The processing unit 50 performs CDS, which is a differential process between the dark signal and the photoelectric conversion signal, on the dark signal and the photoelectric conversion signal that have been converted into digital signals. After performing signal processing such as CDS processing, the processing unit 50 outputs the processed signal to the control unit 4.

[0048] Next, another example of the operation of the image sensor 3 will be described with reference to FIG. 6. At time t11 shown in FIG. 6, the signal RST goes high, turning on the transistor M2 of the reset unit 14 of the pixel 10. This resets the charge in the FD13, and the voltage of the FD13 becomes the reset voltage. Also at time t11, the signal SEL goes high, turning on the transistor M4 of the selection unit 16. This enables the amplifier unit 15 and the selection unit 16 to output a signal based on the reset voltage of the pixel 10 to the signal line 22. At time t12, the signal RST goes low, turning off the transistor M2 of the reset unit 14.

[0049] The signal output unit 31 of the supply unit 30 receives the signal CLIP of the first voltage V1 and is in a state where it can supply a voltage based on the first voltage V1 (clip voltage Vc1) to the signal line 22. In the example shown in Fig. 6, during the period from time t12 to time t13, the voltage of FD13 is higher than the first voltage V1, which is the voltage of the signal CLIP. Therefore, the voltage of the signal VOUT output to the signal line 22 is a voltage based on the reset voltage of FD13.

[0050] At time t13, the processing unit 50 of the readout unit 60 samples the signal VOUT, which is a voltage based on the reset voltage, as a dark signal. The processing unit 50 converts the dark signal into a digital signal. At time t14, the signal output unit 31 receives the signal CLIP of the second voltage V2, which is lower than the first voltage V1, and is ready to supply a voltage based on the second voltage V2 (clip voltage Vc2) to the signal line 22.

[0051] At time t15, signal TX goes high, turning on transistor M1 of transfer unit 12 and transferring the charges photoelectrically converted by photoelectric conversion unit 11 to FD 13. As a result, the voltage of FD 13 becomes a voltage based on the charges transferred from photoelectric conversion unit 11. Also, because signal SEL is high, amplifier 15 and selector 16 are able to output a signal based on the charges generated by photoelectric conversion unit 11 to signal line 22. At time t16, signal TX goes low, turning off transistor M1 of transfer unit 12.

[0052] 6, during the period from time t16 to time t17, the voltage of FD13 is lower than the second voltage V2, which is the voltage of signal CLIP. Therefore, the voltage of signal VOUT output to signal line 22 is limited to a voltage based on the second voltage V2, i.e., clip voltage Vc2.

[0053] At time t17, the processing unit 50 samples the signal VOUT, which becomes the clip voltage Vc2, as a photoelectric conversion signal. The processing unit 50 converts the photoelectric conversion signal into a digital signal. The processing unit 50 performs signal processing such as CDS processing using the digitally converted dark signal and the photoelectric conversion signal, and then outputs the processed signal to the control unit 4. As described above, in this embodiment, the supplying unit 30 receives the signal CLIP having different signal levels when reading out the dark signal and when reading out the photoelectric conversion signal. The supplying unit 30 can limit the voltage of the signal line 22 by supplying a voltage to the signal line 22 in accordance with the voltage of the signal CLIP and the voltage of the FD13.

[0054] As shown in FIG. 4 , the gate of the transistor M5 of each current source 25 provided for each signal line 22 is commonly connected to a signal line to which the signal VB is input. Furthermore, parasitic capacitance (load capacitance) may be present between the signal line 22 from which a pixel signal is output and the gate of the transistor M5 connected to that signal line 22. Due to the influence of this parasitic capacitance, fluctuations in the voltage of the signal line 22 may cause fluctuations in the voltage of the signal VB, resulting in fluctuations in the magnitude of the current flowing through each current source 25. If the image sensor 3 does not include a supply unit 30, a significant drop in the voltage of the signal line 22 and a significant drop in the voltage of the signal VB may occur, resulting in a decrease in the current supplied from the current source 25 or even no current being supplied from the current source 25. If the voltage of the signal line 22 provided for a certain pixel block 20 fluctuates, the voltage of the signal VB commonly supplied to each current source 25 may fluctuate, causing fluctuations in the voltage of the signal lines 22 provided for other pixel blocks 20.

[0055] On the other hand, the image sensor 3 according to this embodiment is provided with a supply unit 30 for each pixel block 20. When the switch unit 32 is in the on state, the supply unit 30 can supply a voltage based on the signal CLIP to the signal line 22, and can limit the voltage of the signal line 22. Therefore, the image sensor 3 can suppress fluctuations in the voltage of the signal VB by limiting the voltage of the signal line 22. This can prevent noise caused by fluctuations in the voltage of the signal VB from being mixed into the signal (photoelectric conversion signal, dark signal) output to the signal line 22.

[0056] In the present embodiment, when the voltage of the FD 13 is relatively low, an operation (clipping operation) is performed to limit the voltage of the signal line 22, and when the voltage of the FD 13 is relatively high, the clipping operation is not performed. As described above, the path through which the current flows from the current source 25 changes depending on whether the clipping operation is performed or not. When the clipping operation is performed, the current from the current source 25 flows between the power supply line 122 and the wiring (ground line) 131 shown in FIG. 4 via the signal output unit 31 of the supply unit 30. When the clipping operation is not performed, the current from the current source 25 flows between the power supply line 121 and the ground wiring (ground wiring) 131 via the amplifier unit 15 of the pixel 10. Since wiring resistance is added to the power supply line 121, the power supply line 122, and the ground line 131 as schematically shown in FIG. 4, a voltage drop (IR drop) due to the wiring resistance occurs.

[0057] The above-described change in current path can cause voltage drops in the power supply line 121, the power supply line 122, and the ground line 131 to differ depending on whether clipping is performed or not, potentially resulting in a difference in the value of the power supply voltage VDD applied to each pixel 10 via the power supply line 121. When signals are simultaneously read from multiple pixel blocks 20, fluctuations in the power supply voltage VDD can cause pixel signal differences between pixel blocks 20 in which clipping is performed during signal readout and pixel blocks 20 in which clipping is not performed during signal readout. Furthermore, fluctuations in the power supply voltage VDD during photoelectric conversion signal readout can cause fluctuations in the signal level of the reset voltage of the FD 13, i.e., the signal level that serves as the reference for voltage changes occurring in response to charge transferred from the photoelectric conversion unit 11. If a difference in the signal level of the reset voltage occurs between the dark signal readout period and the photoelectric conversion signal readout period, CDS processing is performed using a dark signal with a signal level different from the reference signal level for the photoelectric conversion signal, resulting in, for example, black sunshine or streaking in the image generated using the CDS-processed signal. In particular, when the pixel 10 and the supply unit 30 are supplied with power supply voltages from separate electrodes via separate power supply lines, it is believed that the difference in the value of the power supply voltage supplied to the pixel 10 between when the clipping operation is performed and when the clipping operation is not performed will be large.

[0058] In this embodiment, the pixel 10 and the supply unit 30 are connected to a common electrode 200. Furthermore, the power supply line 121 and the power supply line 122 are connected to each other by a plurality of wirings 126, so that the resistance value of the path from the electrode 200 to the pixel 10 and the supply unit 30 can be reduced. This reduces the difference in the power supply voltage VDD applied to the pixel 10 when a clipping operation is performed and when a clipping operation is not performed. This makes it possible to suppress the occurrence of differences in the signals of each pixel due to fluctuations in the power supply voltage. As a result, it is possible to prevent black spots and streaking from occurring in images generated using the pixel signals.

[0059] In the imaging element 3 according to this embodiment, the supply unit 30 is disposed on the second substrate 112. This allows the light receiving area of ​​the photoelectric conversion unit 11 to be larger than when the supply unit 30 is disposed within the first substrate 111. This prevents a decrease in the aperture ratio of the pixel. Furthermore, clipping can be performed without increasing the chip area, and a decrease in the quality of the image generated using the pixel signals can be suppressed. Furthermore, in this embodiment, the supply control unit 36 ​​is disposed on the second substrate 112. Since the supply unit 30 and the supply control unit 36 ​​are disposed on the same substrate, it becomes easier to control the supply unit 30.

[0060] FIG. 7 is a diagram showing an example of a layout of a portion of the image sensor according to the first embodiment. In each of a plurality of pixel blocks 20 of the image sensor 3, a plurality of pixels 10, each including a photoelectric conversion unit 11, are arranged in a row direction (X direction), which is a first direction, and a column direction (Y direction), which is a second direction intersecting the first direction. In the example shown in FIG. 7, four pixels 10 are provided in the pixel block 20. On the first substrate 111 of the image sensor 3, a plurality of pixel blocks 20, each including four pixels 10, are arranged in the row direction (horizontal direction) and the column direction (vertical direction). Note that FIG. 7 schematically shows a portion of the wiring provided in the image sensor 3.

[0061] The signal lines 22 provided for each pixel block 20 are connected to each of the four pixels 10 in the pixel block 20 and transmit pixel signals to the processing unit 50. The wiring 126 is provided between adjacent signal lines 22. As described above, the power supply voltage VDD is applied to the wiring 126, and the wiring 126 is provided so as to sandwich the signal line 22, thereby functioning as a shield. This can suppress coupling between the signal lines 22 and prevent noise from being mixed into the pixel signals output to the signal lines 22.

[0062] 7 schematically represents the plurality of wirings (control lines) that transmit the above-described signals TX, RST, and SEL. When the pixel control unit 35 that supplies the signals TX and the like is disposed on the second substrate 112, the control lines 38 may be disposed at the corners (diagonal corners) of the pixel blocks 20, as shown in FIG. 7. In this case, the control lines 38 are disposed away from the signal lines 22, and therefore noise due to the signals (signals TX, RST, SEL, and the like) of the control lines 38 can be prevented from affecting the signal lines 22.

[0063] According to the above-described embodiment, the following effects can be obtained. (1) The image sensor 3 includes a first substrate 111 on which a photoelectric conversion unit 11 that generates electric charges through photoelectric conversion and a signal line 22 that outputs a signal based on the electric charges generated by the photoelectric conversion unit 11 are provided, and a second substrate 112 on which a supply unit 30 that supplies a voltage to the signal line 22 and a processing unit 50 that processes the signal output to the signal line 22 are provided and which is stacked on the first substrate 111. In this embodiment, pixels 10 each having a photoelectric conversion unit 11 are disposed on the first substrate 111, and the supply unit 30 is disposed on the second substrate 112. This allows clipping without increasing the chip area, preventing degradation of pixel signal quality. This suppresses degradation of the image quality generated using the pixel signals. Compared to a case in which the supply unit 30 is provided within the first substrate 111, the light-receiving area of ​​the photoelectric conversion unit 11 can be increased, suppressing degradation of the pixel aperture ratio. (2) In this embodiment, the readout unit 60 having multiple processing units 50 is disposed on the second substrate 112. This allows multiple circuits for processing pixel signals to be disposed without increasing the chip area. In addition, a decrease in the aperture ratio of the pixel can be suppressed.

[0064] The following modifications are also within the scope of the present invention, and one or more of the modifications may be combined with the above-described embodiment.

[0065] (Variation 1) In the above-described embodiment, an example has been described in which the supply unit 30 includes the signal output unit 31 and the switch unit 32, but the configuration of the supply unit 30 is not limited to this. The supply unit 30 may also be configured without the switch unit 32. The signal output unit 31 is electrically connected to the signal line 22 without the switch unit 32, and is able to supply voltage to the signal line 22 both when reading out a dark signal and when reading out a photoelectric conversion signal. In this modification, the switch unit 32 can be eliminated, thereby reducing the chip area.

[0066] (Variation 2) A signal output unit 31 may be provided for each pixel 10. For example, if a pixel block 20 is made up of four pixels 10, four signal output units 31 and four switch units 32 may be provided for each pixel block 20. Of the signal output units 31 and switch units 32, only the signal output units 31 may be provided for each pixel 10, and no switch units 32 may be provided.

[0067] The signal CLIP may be supplied using a separate wiring for each signal output unit 31 or for each of a plurality of signal output units 31. In this case, the number of signal output units 31 connected to one wiring can be reduced, and the signal level of the signal CLIP can be switched at high speed.

[0068] (Variation 3) In the above-described embodiment, an example has been described in which a signal line 22 and a supply unit 30 are provided for each pixel block 20. However, a signal line 22 may be provided for each pixel 10, and a supply unit 30 may be provided for each signal line 22. In this case, a pixel control unit 35 may be provided for each pixel 10, and a supply control unit 36 ​​may be provided for each supply unit 30. Each supply control unit 36 ​​may control the supply unit 30 provided for each signal line 22 so that voltages can be supplied to each signal line 22 at different timings.

[0069] (Variation 4) FIG. 8 is a block diagram showing an example configuration of an image sensor according to Modification 4. As shown in FIG. 8, power supply voltages may be supplied to the pixel 10 and the supply unit 30 from separate electrodes. In the example shown in FIG. 8, the pixel 10 is supplied with a power supply voltage VDD1 from the electrode 201 via a power supply line 121, and the supply unit 30 is supplied with a power supply voltage VDD2 from the electrode 202 via a power supply line 122. The power supply lines 121 and 122 may be formed so that the resistance value of the path from the electrode 201 to each pixel 10 is the same as the resistance value of the path from the electrode 202 to each supply unit 30. Note that the power supply voltages VDD1 and VDD2 may have different values; for example, the power supply voltage VDD2 may be lower than the voltage VDD1. In this case, the supply unit 30 can be operated by the power supply voltage VDD2, which is lower than the power supply voltage VDD1 supplied to the pixel 10. This reduces the power consumption of the image sensor 3.

[0070] (Variation 5) Fig. 9 is a block diagram showing an example of the configuration of an imaging element according to Modification 5. As shown in Fig. 9, the first substrate 111 may not be provided with the power supply lines 121 connecting the electrodes 200 and each pixel 10. In this case, the power supply voltage VDD is supplied to each pixel 10 from the electrodes 200 via the power supply lines 122 and wiring 126. In this modification, the number of wirings arranged on the first substrate 111 can be reduced.

[0071] (Variation 6) The pixel 10 and the supply unit 30 may be configured using NMOS transistors or PMOS transistors. The pixel 10 and the supply unit 30 may be configured using both NMOS transistors and PMOS transistors. When the amplifier unit 15 and the signal output unit 31 are configured using NMOS transistors, as described above, a signal CLIP having a lower voltage than that used when reading out a dark signal may be supplied to the signal output unit 31 when reading out a photoelectric conversion signal. When the amplifier unit 15 and the signal output unit 31 are configured using PMOS transistors, a signal CLIP having a higher voltage than that used when reading out a dark signal may be supplied to the signal output unit 31 when reading out a photoelectric conversion signal. The supply unit 30 supplies a voltage to the signal line 22 so that the voltage of the signal line 22 ranges from the power supply voltage (or ground voltage) to a voltage based on the signal CLIP. The supply unit 30 limits the voltage of the signal line 22 to a value within a range with the voltage based on the signal CLIP as the upper or lower limit.

[0072] (Variation 7) In the above-described embodiment, an example has been described in which the imaging element 3 is configured by stacking the first substrate 111 and the second substrate 112. However, the first substrate 111 and the second substrate 112 do not have to be stacked.

[0073] (Variation 8) In the above-described embodiment, the imaging element 3 has been described as a back-illuminated type. However, the imaging element 3 may have a front-illuminated type in which the wiring layer 101 is provided on the light incident surface side.

[0074] (Variation 9) In the above-described embodiment and modified examples, a photodiode is used as the photoelectric conversion unit, but a photoelectric conversion film (organic photoelectric film) may be used as the photoelectric conversion unit.

[0075] (Variation 10) The imaging elements and imaging devices described in the above-mentioned embodiments and variations may be applied to cameras, smartphones, tablets, cameras built into PCs, in-vehicle cameras, cameras mounted on unmanned aerial vehicles (drones, radio-controlled aircraft, etc.), etc.

[0076] Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments that are conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention.

[0077] The disclosures of the following priority applications are incorporated herein by reference: Japanese Patent Application No. 2019-180781 (filed September 30, 2019) [Explanation of symbols]

[0078] 1...imaging device, 3...imaging element, 4...control unit, 10...pixel, 11...photoelectric conversion unit, 20...pixel block, 30...supply unit, 35...pixel control unit, 36...supply control unit, 40...AD conversion unit, 50...processing unit, 60...readout unit, 70...readout control unit, 111...first substrate, 112...second substrate

Claims

[Claim 1] a first substrate having first pixels including first photoelectric conversion units that convert light into electric charges and second pixels including second photoelectric conversion units that convert light into electric charges; a wiring layer including a first signal line electrically connected to the first pixel and outputting a first signal based on the charge converted by the first photoelectric conversion unit, and a second signal line electrically connected to the second pixel and outputting a second signal based on the charge converted by the second photoelectric conversion unit; a second substrate that is laminated together with the first substrate and has a readout section including a first processing section that performs signal processing on the first signal output to the first signal line and a second processing section that performs signal processing on the second signal output to the second signal line, a first supply section that controls a voltage of the first signal line, and a second supply section that controls a voltage of the second signal line; Equipped with the wiring layer is disposed between the first substrate and the second substrate in a stacking direction in which the first substrate and the second substrate are stacked, the readout unit is disposed at a position facing at least one of the first pixel and the second pixel in the stacking direction; Image sensor.

Images