Multiprocessor core system

Abstract

To disperse tasks to multiple processor cores while suppressing task redispersion in a multiprocessor core system.SOLUTION: A multiprocessor core system 100 includes multiple processor cores 11-13 that execute predetermined specific processing and a load balancing unit 20 that allocates input tasks to at least some of the multiple processor cores in a load-dispersed manner. The load balancing unit allocates input tasks to the multiple processor cores in a load-dispersed manner so as to suppress at least one of the following: variations in load magnitude among the multiple processor cores and variations in the load on each processor core over time.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to multi-processor core systems. [Background technology]

[0002] In recent years, systems that calculate DNN (Deep Neural Network) models for machine learning have been widely used. In such systems, how to process many processes and tasks, such as multiply-and-accumulate operations, becomes an issue. In the system disclosed in Patent Document 1, a priority is set for each process, and when a high-priority process occurs while a low-priority process is running, the low-priority process is evacuated to a process queue and the high-priority process is allowed to interrupt.

[0003] Furthermore, systems have been proposed that are equipped with multiple processor cores and are capable of executing multiple processes and tasks in parallel. In systems equipped with multiple processor cores, the problem is how to allocate many processes and tasks to the multiple processor cores. The system disclosed in Patent Document 2 monitors the loads on the multiple processors, and when the difference in load exceeds a certain level, it divides (fragments) the process into multiple threads (tasks) and moves the thread from the processor with the highest load to the processor with the lowest load. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2023-153160 [Patent Document 2] International Publication No. 2012 / 124077 Summary of the Invention [Problem to be solved by the invention]

[0005] The system of Patent Document 1 has only a single NPU (Neural Processing Unit) as a processor core, which delays the execution of low-priority processes and makes it impossible to simultaneously perform calculations on multiple DNN models. The system of Patent Document 2 is merely a system equipped with multiple general-purpose processors (CPUs), and does not consider load balancing in a system equipped with multiple processors that execute specific processes such as DNN model calculations. Furthermore, the system of Patent Document 2 assigns threads (tasks) based on the load at a given time, rather than taking into account future load conditions. As a result, if the load on the processor core to which a thread is moved becomes excessive in the future, the thread will be redistributed to another processor core, resulting in a problem of reduced task allocation efficiency.

[0006] The above problem is not limited to processor cores specialized for DNN model calculations, but is common to multi-processor core systems equipped with multiple processor cores that execute any type of specific processing, such as DSPs (Digital Signal Processors) and ISPs (Image Signal Processors).For this reason, in a multi-processor core system equipped with multiple processor cores that execute predetermined specific processing, there is a demand for technology that can distribute tasks to multiple processor cores while suppressing task redistribution. [Means for solving the problem]

[0007] One aspect of the present disclosure provides a multiprocessor core system (100) that includes a plurality of processor cores (11-13) that execute predetermined specific processes, and a load distribution unit (20) that allocates input tasks to at least some of the plurality of processor cores in a load-distributed manner, the load distribution unit distributing the input tasks to the plurality of processor cores in a load-distributed manner so as to reduce at least one of variations in load magnitude among the plurality of processor cores and variations in load over time on each of the processor cores.

[0008] In this form of multi-processor core system, the load distribution unit distributes and assigns input tasks to multiple processor cores so as to reduce at least one of the variations in load magnitude among the multiple processor cores and the variations in load over time on each processor core.Therefore, in a multi-processor core system having multiple processor cores that execute predetermined specific processes, tasks can be distributed to multiple processor cores while reducing the need to redistribute tasks. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram illustrating a schematic configuration of a multiprocessor core system according to an embodiment of the present disclosure. [Figure 2] FIG. 10 is an explanatory diagram showing an example of the setting contents of a time load table. [Figure 3] 10 is a flowchart showing a procedure for task allocation processing. [Figure 4] 10 is a flowchart showing the detailed processing procedure of S110. [Figure 5] FIG. 2 is an explanatory diagram showing an example of a load state of each processor core; [Figure 6] FIG. 2 is an explanatory diagram showing an example of a load state of each processor core; [Figure 7] 10 is a flowchart showing the detailed processing procedure of S110 in the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] A. First embodiment: A1.Device configuration: The multiprocessor core system 100 shown in FIG. 1 is a system for processing and outputting an input task. In this embodiment, the multiprocessor core system 100 is mounted on and used in a vehicle having sensors for detecting the surrounding environment, such as an imaging device or millimeter-wave radar (hereinafter referred to as "surrounding environment sensors"). In this embodiment, the "input task" is a task for extracting feature points for estimating the vehicle's own position using the detection results of the surrounding environment sensors. Therefore, for example, a captured image, which is the detection result of the surrounding environment sensor, is input to the multiprocessor core system 100 as the input task.

[0011] In this embodiment, the multiprocessor core system 100 is configured as an SoC (System on Chip). The multiprocessor core system 100 includes a first processor core 11, a second processor core 12, a third processor core 13, a load balancer 20, a map storage unit 30, a DRAM (Dynamic Random Access Memory) 40, and a bus 50.

[0012] In this embodiment, each of the three processor cores 11 to 13 functions as an NPU (Neural Processing Unit), and each executes at least a portion of the DNN processing. The DNN processing (computation) includes a layer that performs so-called convolution operations, which include multiple multiply-and-accumulate operations, a layer that performs pooling operations, a layer that performs predetermined matrix operations, and a layer that performs predetermined vector operations. These operations do not depend on the input image. Therefore, the compiler 21 and scheduler 22, which will be described later, can estimate in advance the time required for the operations in each layer and the load (usage rate) of the processor cores.

[0013] The load distribution unit 20 distributes the load of input tasks among at least some of the three processor cores 11 to 13 and assigns them to the processor cores. In this embodiment, the load distribution unit 20 is configured by a CPU (Central Processing Unit) as a general-purpose processor core. The load distribution unit 20 includes a compiler 21 and a scheduler 22. The compiler 21 and the scheduler 22 are functional units that are realized when the CPU constituting the load distribution unit 20 executes a program stored in a memory (not shown).

[0014] The compiler 21 divides the input task into a plurality of divided tasks (hereinafter referred to as "subdivision tasks"). The scheduler 22 determines which of the three processor cores 11 to 13 should execute the subdivision tasks obtained by the division by the compiler 21 and when. Details of the processes executed by the compiler 21 and the scheduler 22 will be described later.

[0015] The map storage unit 30 is configured with a nonvolatile rewritable storage device, such as an EEPROM (Electrically Erasable Programmable Read-Only Memory). The map storage unit 30 stores a time load map 31. The time load map 31 is a map that indicates the current load and future planned load of each of the processor cores 11 to 13 at each time. In the example of FIG. 2, the first processor core 11 has no load at present or in the future. Therefore, the time average value Av1 of the load of the first processor core 11 (hereinafter also referred to as the "load average value") is zero. In contrast, the second processor core 12 and the third processor core 13 each have a load at present and a load planned for the future. Note that in the example of FIG. 2, the load average value Av2 of the second processor core 12 is greater than the load average value Av3 of the third processor core 13. As will be described later, the time load map 31 is rewritten as needed. In FIG. 2 and later-described FIGS. 5 and 6, the processor cores 11 and 12 are abbreviated to "core."

[0016] 1 temporarily stores input tasks input from the outside. The processor cores 11 to 13, the load distribution unit 20, the map storage unit 30, and the DRAM 40 are configured to be able to exchange data with one another via a bus 50.

[0017] A2. Task assignment process: 3 means a process of dividing an input task into a plurality of subtasks as needed, and determining to which of the core processors 11 to 13 the task should be assigned. The task allocation process starts when a new input task occurs in the DRAM 40.

[0018] In step S105, the scheduler 22 reads out the time load map 31 stored in the map storage unit 30. Note that hereinafter, "step S" will be simply written as "S", and the word "step" will be omitted.

[0019] In S110, the scheduler 22 determines a processor core to which a newly generated input task is temporarily assigned (hereinafter referred to as a "temporarily assigned processor core"). Specifically, S205 and S210 shown in FIG. 4 are executed. In S205, the scheduler 22 calculates the average load value of each processor core before the input task is assigned, based on the time load map 31 read in S105. In the example of FIG. 2, the scheduler 22 calculates a load average value Av1 of the first processor core 11, a load average value Av2 of the second processor core 12, and a load average value Av3 of the third processor core 13. In S210, the scheduler 22 determines the processor core with the smallest average load value as the temporarily assigned processor core. In the example of FIG. 2, the first processor core 11 is determined as the temporarily assigned processor core.

[0020] As shown in FIG. 3, in S115, the scheduler 22 calculates the average load value of each of the processor cores 11 to 13 when all input tasks are assigned to the tentatively assigned processor cores determined in S110.

[0021] 5 shows an example of the load state of each processor core when S110 is executed. In FIG. 5 and the following figures, the load due to a newly generated input task and subtasks generated from the input task are indicated by hatching. As described above, when the first processor core 11 is determined as the assigned processor core, the scheduler 22 determines the load per unit time of the input task by determining the load per unit time. The scheduler 22 then calculates a new load average value Av1a for the first processor core 11. Note that, since no new tasks have been assigned to the second processor core 12 and the third processor core 13, their load average values ​​are the same as the load average values ​​Av2 and Av3 shown in FIG. 2.

[0022] As shown in FIG. 3, the scheduler 22 determines whether the difference between the load average values ​​of the processor cores calculated in S115 is equal to or greater than the difference threshold (S120). The "difference between the load average values" refers to the difference between any two pairs of the three processor cores 11 to 13. That is, there are a total of three pairs of load average value differences. Then, in S120, it is determined whether the difference between at least one of these three pairs is equal to or greater than the difference threshold. If it is determined that the difference between the load average values ​​is not equal to or greater than the difference threshold, that is, if the differences between all three pairs are smaller than the difference threshold (S120: NO), the scheduler 22 sets the tentative allocation of the input task as a formal allocation (S125).

[0023] On the other hand, if it is determined that the difference in the load average values ​​is greater than or equal to the difference threshold, i.e., if it is determined that at least one of the differences between the three sets is greater than or equal to the difference threshold (S120: YES), the compiler 21 divides the input task into subtasks, and the scheduler 22 executes a process of assigning the divided subtasks to processor cores other than the assigned processor core so as to suppress the difference in the load average values ​​(S130).

[0024] In the example of FIG. 6, a task at time t2 and a task at time t3 of the first processor core 11 are divided into sub-tasks. A sub-task Td1 included in the task at time t2 is assigned to the second processor core 12 at time t3. A sub-task Td2 included in the task at time t3 is assigned to the third processor core 13 at time t2. As a result of the assignment of the sub-tasks Td1 and Td2, the load average value Av1b of the first processor core 11 decreases compared to before the assignment of the sub-tasks Td1 and Td2. In contrast, the load average value Av2b of the second processor core 12 and the load average value Av3b of the third processor core 13 increase compared to before the assignment of the sub-tasks Td1 and Td2. Therefore, the difference between any two pairs of load average values ​​Av1b to Av3b of the three processor cores 11 and 12 decreases compared to the state of FIG. 5.

[0025] Specifically, in this embodiment, the allocation process of the subdivision tasks Td1 and Td2 shown in Figure 6 is realized by trying various combinations and finding the combination that minimizes the difference in the load average values. For example, among the loads on the first processor core 11, a task corresponding to the load at time t1 is divided into subdivision tasks, and the first subdivision task obtained is added to the other two processor cores 12 and 13 at times t1 to t4, and the load average values ​​for each of the processor cores 11 to 13 are calculated. Next, among the subdivision tasks obtained by dividing the load on the first processor core 11 corresponding to the load at time t1, a second subdivision task is added to the other two processor cores 12 and 13 at times t1 to t4, and the load average values ​​for each of the processor cores 11 to 13 are calculated. After the division, allocation, and calculation of the load average value of the task corresponding to the load at time t1 of the load on the first processor core 11 are completed in this way, the division, allocation, and calculation of the load average value of the task corresponding to the load at time t2 to t4 are then performed in the same manner as for the task corresponding to the load at time t1. In this way, all tasks at all times t1 to t4 of the first processor core 11 are divided, distributed, and the average load values ​​are calculated, and then the combination that minimizes the difference in the average load values ​​of the processor cores 11 to 13 is found.

[0026] After completing S125 or S130 described above, the scheduler 22 determines the execution times of the subdivision tasks so as to suppress the variation in the magnitude of the load at each time in each of the processor cores 11 to 13 (S135). For example, in the example of FIG. 6, the load at time t4 on the third processor core 13 is excessively small compared to the load at the other times t1 to t3. Therefore, in this case, the scheduler 22 determines that the subdivision task scheduled to be executed at one of the other times t1 to t3 on the third processor core 13 is to be executed at time t4. The specific determination method at this time is the same as the subdivision task allocation process in S130 described above. That is, the scheduler 22 calculates the variation in the load at each time when each of the subdivision tasks assigned to the third processor core 13 at times t1 to t3 is assigned to time t3. In this embodiment, the "load variation" is the difference (absolute value) between the load value at each time and the average load value. The scheduler 22 then identifies an allocation pattern that minimizes the calculated time average value of the load variation. Note that instead of the time average value of the load variation, the scheduler 22 may identify an allocation pattern that minimizes the difference between the maximum and minimum values ​​of the load variation.

[0027] As shown in FIG. 3, in S140, the time load map 31 is overwritten and updated with a time load map that reflects the execution times of the divided tasks in the processor cores 11 to 13 determined in S135 (S140).

[0028] According to the multi-processor core system 100 of the first embodiment described above, the load distribution unit 20 distributes and assigns input tasks to the multiple processor cores 11 to 13 so as to reduce the variation in load magnitude among the multiple processor cores 11 to 13 and the variation in load over time on each processor core 11 to 13.Therefore, in the multi-processor core system 100 having multiple processor cores 11 to 13 that execute DNN, which is a predetermined specific process, tasks can be distributed to the multiple processor cores 11 to 13 while reducing the need to redistribute tasks.

[0029] Furthermore, the load distribution unit 20 includes the compiler 21 and the scheduler 22, and is therefore able to divide the input task into a plurality of subtasks and determine which of the processor cores 11 to 13 should execute each subtask and when.

[0030] Furthermore, the scheduler 22 determines the provisionally assigned processor core and calculates the average load value of each processor core 11 to 13 when all of the input tasks are assigned to the provisionally assigned processor core. If the difference in the average load values ​​is equal to or greater than a predetermined difference threshold, the compiler 21 divides the input task into multiple subtasks. The scheduler 22 assigns subtasks corresponding to at least a portion of the input task assigned to the provisionally assigned processor core to other processor cores so as to suppress the difference in the average load values, thereby suppressing the difference in the time average load (average load value) between each processor core 11 to 13.

[0031] In addition, the scheduler 22 executes a process to determine the execution time of the subtasks in each of the processor cores 11 to 13 so as to suppress the variation in the load magnitude from time to time in each of the processor cores 11 to 13, thereby suppressing the variation in the load magnitude from time to time in each of the processor cores 11 to 13.

[0032] Furthermore, the scheduler 22 determines the processor core with the smallest time average load before the input task is provisionally assigned as the provisionally assigned processor core, thereby suppressing the occurrence of distribution (redistribution) of the divided tasks from the provisionally assigned processor core to another processor core.

[0033] B. Second embodiment: The device configuration of the multiprocessor core system 100 of the second embodiment is the same as that of the multiprocessor core system 100 of the first embodiment, so the same components are given the same reference numerals and detailed description thereof will be omitted.

[0034] The task allocation process of the second embodiment differs from the task allocation process of the first embodiment in the detailed procedure of S110. The other procedures in the task allocation process of the second embodiment are the same as those in the task allocation process of the first embodiment, so the same procedures are denoted by the same reference numerals and detailed descriptions thereof will be omitted.

[0035] As shown in Fig. 7, S110 of the second embodiment differs from S110 of the first embodiment shown in Fig. 4 in that S205a is executed instead of S205, and S210a is executed instead of S210. When S110 starts, the scheduler 22 identifies the scheduled task end time for each of the processor cores 11 to 13 based on the time load map 31 read in S105 (S205a). In S210a, the scheduler 22 determines the processor core with the earliest scheduled task end time as the tentatively assigned processor core. After S210a is completed, the above-mentioned S115 is executed.

[0036] The multiprocessor core system 100 of the second embodiment described above has the same effects as the multiprocessor core system 100 of the first embodiment. In addition, the processor core with the earliest scheduled task completion time before the input task is provisionally assigned is determined as the provisionally assigned processor core, which prevents a specific processor core from completing the task excessively late compared to the other processor cores.

[0037] C. Other Embodiments: (C1) In each embodiment, execution of S130 reduces the load variation among the three processor cores 11 to 13, and execution of S135 reduces the load variation over time among the processor cores 11 to 13, but the present disclosure is not limited to this. For example, S130 may be omitted. Even in this configuration, execution of S135 can reduce the load variation over time among the processor cores 11 to 13. Also, S135 may be omitted. Even in this configuration, execution of S130 can reduce the load variation over time among the three processor cores 11 to 13.

[0038] (C2) In each embodiment, the load distribution unit 20 includes the compiler 21 and the scheduler 22, but the present disclosure is not limited to this. For example, instead of the compiler 21 and the scheduler 22, the load distribution unit 20 may include a single functional unit that executes both the processes executed by the compiler 21 and the scheduler 22 described above.

[0039] (C3) In the first embodiment, the processor core with the smallest average load value was determined as the provisionally assigned processor core. In the second embodiment, the processor core with the earliest scheduled task completion time before the input task was provisionally assigned was determined as the provisionally assigned processor core. However, the present disclosure is not limited to these configurations. For example, one of the three processor cores 11 to 13 may be fixedly determined as the provisionally assigned processor core. Alternatively, the calculation of the load average value and the determination of whether the load average value is equal to or less than a predetermined threshold may be performed for the three processor cores 11 to 13 in order. If a processor core with a load average value equal to or less than the predetermined threshold is found, that processor core may be determined as the provisionally assigned processor core. For the subsequent processor cores, the calculation of the load average value and the determination of whether the load average value is equal to or less than the predetermined threshold may not be performed. This reduces the processing load involved in determining the provisionally assigned processor core.

[0040] (C4) In each embodiment, all three processor cores 11 to 13 function as NPUs, but the present disclosure is not limited to this. For example, they may be processor cores that perform any type of specific processing, such as a DSP (Digital Signal Processor) or an ISP (Image Signal Processor). Even if they are DSPs or ISPs, they can achieve the same effects and advantages as the respective embodiments, provided that similar images are input. That is, for example, when a task execution command is issued, such as "perform semantic segmentation," a processor core used to execute a specific process in which the processing to be executed is substantially fixed and the processing load on each processor core can be easily predicted may be applied to the multi-processor core system of the present disclosure.

[0041] (C5) The multiprocessor core system 100 of each embodiment is merely an example and can be modified in various ways. For example, the number of processor cores in the multiprocessor core system 100 is not limited to three and may be any number equal to or greater than two. Furthermore, the multiprocessor core system 100 does not have to be configured as an SoC. For example, the load distribution unit 20 and other functional units may be configured on different boards, with the boards electrically connected to each other.

[0042] The present disclosure is not limited to the above-described embodiments and can be realized in various configurations without departing from the spirit thereof. For example, the technical features in each embodiment corresponding to the technical features in the embodiments described in the Summary of the Invention section can be appropriately replaced or combined to solve some or all of the above-described problems or achieve some or all of the above-described effects. Furthermore, if a technical feature is not described as essential in this specification, it can be deleted as appropriate. The present disclosure may be realized, for example, in the following forms. [Explanation of symbols]

[0043] 11 to 13...processor core, 20...load distribution unit, 21...compiler, 22...scheduler, 30...map storage unit, 31...time load map, 100...multiprocessor core system

Claims

1. A multi-processor core system (100), a plurality of processor cores (11 to 13) that execute predetermined specific processes; a load distribution unit (20) that distributes the load of input tasks to at least some of the processor cores; Equipped with the load distribution unit distributes the load of the input tasks among the plurality of processor cores so as to reduce at least one of a variation in load magnitude among the plurality of processor cores and a variation in load over time on each of the processor cores; Multi-processor core system.

2. 2. The multiprocessor core system of claim 1, The load distribution unit a compiler (21) for dividing the input task into a plurality of subtasks; a scheduler (22) that determines when each of the subtasks is to be executed on which of the plurality of processor cores; A multi-processor core system having:

3. 3. The multiprocessor core system according to claim 2, The system further comprises a map storage unit (30) for storing a time load map (31) indicating the time and the magnitude of the load in each of the processor cores, The scheduler (i) reading the time load map from the map storage unit, and determining, based on the time load map, a provisionally assigned processor core to which the input task is provisionally assigned from among the plurality of processor cores; (ii) calculating a load average value, which is a time average value of a load on each of the processor cores when all of the input tasks are assigned to the provisionally assigned processor cores; Run The compiler (iii) when the difference between the load average values ​​among the processor cores is equal to or greater than a predetermined difference threshold, executing a process of dividing the input task into the plurality of subtasks; The scheduler (iv) A multi-processor core system that performs a process of assigning the subdivided tasks, which correspond to at least a portion of the input tasks assigned to the provisionally assigned processor core, to other processor cores so as to suppress the difference in each of the load average values.

4. 4. The multiprocessor core system according to claim 3, After the process of (iv), the scheduler (v) A multi-processor core system that executes a process for determining the execution time of the divided tasks in each of the processor cores so as to suppress variations in the magnitude of the load at each time.

5. 5. The multiprocessor core system according to claim 3, In the process (i), the scheduler determines the processor core with the smallest time average load before the input task is provisionally assigned as the provisionally assigned processor core.

6. 5. The multiprocessor core system according to claim 3, In the process (i), the scheduler determines the processor core having the earliest scheduled task completion time before the input task is provisionally assigned as the provisionally assigned processor core.

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