Semiconductor equipment

Abstract

To provide a storage device capable of increasing the storage capacity per unit area while securing the data holding period.SOLUTION: A plurality of bit lines are divided into some groups, and a plurality of word lines are also divided into some groups. In memory cells connected to the bit lines that belong to one group, the word lines that belong to the one group are connected. In addition, the driving of the bit lines is controlled for each group by a plurality of bit line driving circuits. In addition, a cell array is formed on driving circuits including the bit line driving circuits and a word line driving circuit. By forming a three-dimensional structure so that the driving circuits and the cell array are overlapped, the occupied area of the storage device can be reduced even if the plurality of bit line driving circuits are provided.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a memory device and a semiconductor device having the memory device. [Background technology]

[0002] In recent years, as a material for the active layer of transistors, a material that combines high mobility and uniform device characteristics has been developed. Metal oxides that exhibit semiconducting properties, known as oxide semiconductors, are attracting attention. For example, indium oxide is used to form the pixel electrodes in liquid crystal displays. Metal oxides that exhibit semiconducting properties are used as materials for the base electrodes. tungsten oxide, tin oxide, indium oxide, zinc oxide, etc., which have semiconductor properties A transistor using a metal oxide exhibiting the above-mentioned property in a channel formation region is already known (Patent Reference 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, semiconductor memory devices (hereinafter simply referred to as memory devices) are classified as volatile memories. DRAM, SRAM, and non-volatile memory such as mask ROM, EPROM, and EE There are PROM, flash memory, ferroelectric memory, etc., which use a single crystal semiconductor substrate. Many of these memories have already been put to practical use. RAM consists of memory cells made up of transistors and capacitors (hereinafter also called capacitive elements). It has a simple structure, and is easier to configure memory cells than other memory devices such as SRAM. Therefore, the memory capacity per unit area is higher than other memory devices. This allows for lower costs.

[0005] As mentioned above, DRAM is suitable for large storage capacity, but it is necessary to suppress the increase in chip size. In order to realize a more highly integrated circuit, it is necessary to increase the unit area, just like other memory devices. The memory capacity per unit area must be increased. To achieve this, each memory cell must have a capacity to hold a charge. Therefore, it is necessary to reduce the area of ​​the capacitance element provided in the memory cell and reduce the area of ​​each memory cell. Not obtained.

[0006] However, when the capacitance value of the capacitance element is reduced due to the area reduction, the difference between each digital value becomes Since the difference in the amount of charge is small, the accuracy of the data can be maintained if the off-state current of the transistor is high. Therefore, the frequency of refresh operations is This increases the power consumption.

[0007] Furthermore, when the number of memory cells is increased to achieve a larger storage capacity, the number of cells connected to one bit line increases. The number of memory cells increases, or the distance over which one bit line is routed increases. Therefore, the parasitic capacitance and parasitic resistance of the bit line increase, and the area of ​​the capacitance element is reduced. When the difference in the amount of charge between the digital values ​​becomes small, the difference in the amount of charge is transferred via the bit line. , it becomes difficult to read data accurately, and the error rate increases.

[0008] In addition, when the number of memory cells is increased, the number of memory cells connected to one word line is increased in the same manner as in the case of bit lines. The number of memory cells increases, or the distance over which one word line is routed becomes longer. Therefore, the parasitic capacitance and parasitic resistance of the word line increase, and the signal input to the word line The pulse is delayed or the potential drop of the word line becomes large. When a signal to control the switching of the transistor is supplied to the memory cell, the memory Depending on the cell, data may not be written or may not be able to hold the data properly and may be lost. , data is not read correctly because the read time is too long. Problems occur in the series of operations of writing, holding, and reading, increasing the error rate.

[0009] In view of the above-mentioned problems, one aspect of the present invention is to provide a method for reducing the storage capacity per unit area while ensuring a data retention period. Another object of the present invention is to propose a storage device that can increase the storage capacity. One aspect is a storage device that can increase storage capacity per unit area while suppressing the error rate. Another object of the present invention is to propose a storage device. It is an object of the present invention to realize a highly integrated semiconductor device. One embodiment aims to realize a highly reliable semiconductor device by using the memory device. It is one of the targets. [Means for solving the problem]

[0010] The inventors have reduced the number of memory cells connected to one bit line, and instead By increasing the number of lines, the parasitic capacitance and parasitic resistance of the bit lines can be reduced even if the number of memory cells increases. However, as the number of bit lines increases, The layout of the cell array, which consists of several memory cells, is elongated in one direction. The aspect ratio is far from 1.

[0011] If the aspect ratio of the cell array is far from 1, the versatility of the memory device will decrease. When designing an integrated circuit using a memory device, there are many layout restrictions. In a memory device according to one aspect of the present invention, a plurality of bit lines are divided into several groups, and The number of word lines is also divided into several groups. The connected memory cells are connected to word lines belonging to one group. Furthermore, the plurality of bit lines are driven by a plurality of bit line driving circuits for each group. to be controlled.

[0012] With the above configuration, the cell array layout can be designed so that the aspect ratio approaches 1. This makes it easier to do so.

[0013] Furthermore, in one aspect of the present invention, there is provided a semiconductor device including the plurality of bit line driver circuits and a word line driver circuit. The cell array is formed on the driving circuit. By integrating the bit line driver circuits, the area occupied by the memory device can be reduced even if a plurality of bit line driver circuits are provided. It is possible.

[0014] Specifically, one aspect of the present invention is a first bit line driver circuit that drives a plurality of first bit lines. a second bit line driving circuit for driving the plurality of second bit lines; a word line driving circuit for driving the second word line; and a first cell having a plurality of first memory cells. a second cell array having a plurality of second memory cells, The gate electrode of the transistor is electrically connected to one of the plurality of first word lines, and the source voltage one of the electrode and the drain electrode is electrically connected to any one of the plurality of first bit lines a first transistor, one electrode of which is a source electrode and a drain electrode of the first transistor; and a first capacitance element electrically connected to the other of the first and second memory cells. a source electrode and a drain electrode electrically connected to one of the plurality of second word lines; a second transistor, one of whose electrodes is electrically connected to any one of the plurality of second bit lines; and one electrode of the second transistor is electrically connected to the other of the source electrode and drain electrode of the second transistor. and a second capacitance element connected to the first bit line driving circuit. The second cell array is provided so as to overlap the second bit line driving circuit. The storage device is characterized by being provided with:

[0015] In addition, in one embodiment of the present invention, a semiconductor element such as a transistor used in a driver circuit is The semiconductors used are silicon and germanium. The transistor is an oxide semiconductor with a wider band gap than silicon or germanium. Semiconductors such as these are used.

[0016] Transistors that use semiconductors with a wide band gap, such as oxide semiconductors, in the active layer are The off-state current is significantly lower than that of transistors using semiconductors such as silicon or germanium. Therefore, by using the above-described transistor with extremely low off-state current in a memory cell, This prevents leakage of charge from the capacitor. Even if the child becomes smaller, the frequency of refresh operations can be prevented from increasing.

[0017] That is, the first transistor and the second transistor use an oxide semiconductor for an active layer. A memory device including a transistor having a capacitance of 0.1 to 0.2 μm is also one embodiment of the present invention.

[0018] On the other hand, semiconductors such as polycrystalline or single-crystalline silicon or germanium are used for the active layer. Compared to transistors that use the above-mentioned wide band gap semiconductors in the active layer, Therefore, by using the transistor with high mobility in a driver circuit, The storage device can be driven at high speed.

[0019] That is, the first bit line driving circuit, the second bit line driving circuit, and the word line The driving circuit is a transistor that uses polycrystalline or single-crystalline silicon or germanium as the active layer. A storage device having the above is also one aspect of the present invention. [Effects of the Invention]

[0020] A memory device according to one embodiment of the present invention can reduce the number of elements electrically connected to a bit line. That is, it is possible to reduce the parasitic capacitance of the bit line. The reduction in the number of elements electrically connected to the bit line is accompanied by the shortening of the bit line. In other words, the parasitic resistance of the bit line can be reduced. This reduces the capacitance value (size of the capacitance element) of the capacitance element provided in the memory cell. Therefore, even if the data is lost, the data can be retained in the memory cell. Alternatively, the storage device according to one embodiment of the present invention can have a higher storage capacity per unit area. With the above configuration, it is possible to increase the storage capacity per unit area while suppressing the error rate. Alternatively, a semiconductor device according to one embodiment of the present invention can achieve the following by using the above memory device: Alternatively, the semiconductor device according to one embodiment of the present invention can be configured as follows: By using the above storage device, reliability can be improved. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a conceptual diagram showing an example of the structure of a storage device. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a cell array. [Figure 3] FIG. 2 is a block diagram showing a configuration example of a drive circuit. [Figure 4] FIG. 2 is a circuit diagram showing a configuration example of a readout circuit. [Figure 5] FIG. 1 is a cross-sectional view showing an example of the structure of a memory device. [Figure 6] 1A and 1B are cross-sectional views showing modified examples of a transistor. [Figure 7] 10A to 10D are cross-sectional views showing modified examples of transistors. [Figure 8] 1A to 1D are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 9] FIG. 1 is a block diagram showing an example of the configuration of a microprocessor. [Figure 10] FIG. 1 is a block diagram showing an example of the configuration of an RF tag. [Figure 11] 1A to 1C are diagrams illustrating specific examples of semiconductor devices. [Figure 12] 1A to 1E are diagrams illustrating structures of oxide materials according to one embodiment of the present invention. [Figure 13] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Figure 14] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Figure 15] FIG. 10 is a graph illustrating the gate voltage dependence of mobility obtained by calculation. [Figure 16] (A) to (C) Graphs explaining the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 17] (A) to (C) Graphs explaining the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 18] (A) to (C) Graphs explaining the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 19] (A) and (B) are diagrams illustrating the cross-sectional structure of a transistor used in calculations. [Figure 20] Graphs of characteristics of transistors using oxide semiconductor films are shown in (A) to (C). [Figure 21] 10A and 10B are graphs showing the Vgs-Ids characteristics of the transistor of Sample 1 after a BT test. [Figure 22] 10A and 10B are graphs showing the Vgs-Ids characteristics of the transistor of Sample 2 after a BT test. [Figure 23] FIG. 1 shows the Vgs dependence of Ids and field-effect mobility. [Figure 24] (A) and (B) are graphs showing the relationship between substrate temperature and threshold voltage, and the relationship between substrate temperature and field-effect mobility. [Figure 25] FIG. 1 shows XRD spectra of sample A and sample B. [Figure 26] FIG. 10 is a graph showing the relationship between the off-state current of a transistor and the substrate temperature during measurement. [Figure 27] 1A to 1C illustrate a structure of a transistor according to one embodiment of the present invention. [Figure 28] 1A to 1C illustrate a structure of a transistor according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and methods thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the following description of the embodiments.

[0023] In addition, integrated circuits such as microprocessors and image processing circuits, RF tags, storage media, and semiconductors Any and all semiconductor devices that can use memory devices, such as display devices, can be used in the present invention. The semiconductor display devices include liquid crystal display devices and organic light emitting diode (OLED) devices. Light-emitting devices with light-emitting elements, such as those represented by l Micromirror Device), PDP (Plasma Display) Panel), FED (Field Emission Display), etc. A semiconductor display device having a circuit element using a semiconductor film in a pixel section or a driving circuit falls into this category. Included.

[0024] (Embodiment 1) First, a memory device of one embodiment of the present invention will be described with reference to FIGS.

[0025] <Example of storage device structure> FIG. 1 is a conceptual diagram illustrating a structural example of a storage device according to one embodiment of the present invention. A word line driving circuit 101 and a first bit line driving circuit 102 are provided using a semiconductor substrate 100. a second bit line driving circuit 102a, a second bit line driving circuit 102b, a third bit line driving circuit 102c, and a A first cell array 103a is provided on the bit line driver circuit 102a so as to overlap with the second cell array 103a. a second cell array 103b provided on the bit line driving circuit 102b in an overlapping manner; and a third cell array 103c provided on and overlapping with the line driving circuit 102c. In FIG. 1, a word line driver circuit 101 and first to third bit line driver circuits 102a to 102c are provided. The bit line driver circuit 102c and the first to third cell arrays 103a to 103c are connected to each other. Although they are shown spaced apart, they are overlapped in the storage device.

[0026] The semiconductor substrate 100 may be made of silicon, germanium, silicon germanium, carbon, or the like. Semiconductor substrates made of Group 14 elements such as silicon hydride, as well as gallium arsenide and indium phosphide Compound semiconductor substrates such as SOI substrates can be used. The term "substrate" refers to a substrate having a silicon layer provided on an insulating surface. The present invention also includes a substrate having a semiconductor layer made of a material other than silicon on an insulating surface. The SOI substrate is a semiconductor substrate formed on an insulating substrate such as a glass substrate via an insulating layer. The term "electrode" includes a configuration in which a conductor layer is provided.

[0027] In FIG. 1, the memory device has three types of bit line driving circuits and three types of cell arrays. The memory device has k types of bit lines (k is a natural number of 2 or more). The drive circuits and the k types of cell arrays each of which is provided superimposed on the corresponding bit line drive circuits. It is also possible to have a configuration with a ray.

[0028] <Example of cell array configuration> FIG. 2 shows an example of the configuration of the cell arrays (first cell array 103a to third cell array 103c). The first cell array 103a shown in FIG. , a plurality of first bit lines 105a, and a plurality of first memory cells 10 arranged in a matrix. Each of the plurality of first memory cells 106a has a plurality of gate electrodes. The source electrode and the drain electrode are electrically connected to one of the first word lines 104a. A transistor having one pole electrically connected to any one of the plurality of first bit lines 105a. 107a, one electrode of which is the source electrode and the drain electrode of the transistor 107a. a capacitor 108a having one electrode electrically connected to a capacitor line and the other electrode electrically connected to a capacitor line; Each of the first word lines 104a is connected to the word line driving circuit 101. That is, the word line driving circuit 101 controls the potential of the first memory cell 106. a) is a circuit for controlling the switching of the transistors included in the first bit Each of the lines 105a is controlled by the first bit line driving circuit 102a. Specifically, data is written to a specific first memory cell 106a. When this is done, the first bit line 106a electrically connected to the specific first memory cell 106a is The potential of the bit line driver 102a is changed to a potential corresponding to the data. When data is read from the specific first memory cell 106a, , the potential of the first bit line 105a electrically connected to the specific first memory cell 106a That is, the first bit line driving circuit 1 02a writes data to the first memory cell 106a and reads the data. It is a detour.

[0029] The second cell array 103b and the third cell array 103c shown in FIG. 2 are also the same as the first cell array shown in FIG. The second cell array 103b has a similar configuration to the first cell array 103a. A second word line 104b, a plurality of second bit lines 105b, and a plurality of second bit lines 105a arranged in a matrix form. The second memory cells 106b have a number of second memory cells 106a. Specifically, the plurality of second memory cells 106b have the same circuit configuration as the second memory cells 106a. Each of the gate electrodes is electrically connected to one of the plurality of second word lines 104b. One of the source electrode and the drain electrode is connected to one of the plurality of second bit lines 105b. A transistor 107b is electrically connected to the transistor 107b, and one electrode of the transistor 107b is connected to the The other electrode is electrically connected to the capacitance line. and a capacitor element 108b connected to the second word line 104b. The potential of each of the second bit lines 10 is controlled by the word line driving circuit 101. 5b are controlled and determined by the second bit line driving circuit 102b. It will be held.

[0030] Similarly, the third cell array 103c includes a plurality of third word lines 104c and a plurality of third bit lines 104d. The memory cell 106 includes a line 105c and a plurality of third memory cells 106c arranged in a matrix. The third memory cell 106c has the same structure as the first memory cell 106a and the second memory cell 106b. Specifically, each of the third memory cells 106c has a circuit configuration similar to that of the first memory cell 106a. The gate electrode is electrically connected to one of the plurality of third word lines 104c, and the source electrode and one of the drain electrodes is electrically connected to one of the plurality of third bit lines 105c. One electrode of the transistor 107c is the source electrode and the other electrode of the transistor 107c is the drain electrode. a capacitance element electrically connected to the other of the drain electrodes, the other electrode of which is electrically connected to the capacitance line; Each of the plurality of third word lines 104c has a word line driver 108c. The potential of each of the third bit lines 105c is controlled by the operation circuit 101. The third bit line driver circuit 102c controls and determines the potential of the bit line.

[0031] <Driver circuit configuration example> FIG. 3 shows the driving circuits (word line driving circuit 101 and first to third bit line driving circuits 102a to 102c). 3 is a block diagram showing an example of the configuration of the bit line driving circuit 102c, etc. Although the figure shows circuits classified by function as independent blocks, the actual circuit is It is difficult to completely separate the functions, and one circuit may be involved in multiple functions. do.

[0032] The memory device shown in FIG. 3 includes a first cell array 103a, a second cell array 103b, a third cell array 103c, and a The word line drive circuit 103c includes a drive circuit 120. 1 and a first bit line driver circuit 102a to a third bit line driver circuit 102c. Furthermore, the driving circuit 120 includes the word line driving circuit 101 and the first bit line driving circuit 102a. The control circuit 110 controls the operations of the first to third bit line driver circuits 102c.

[0033] In addition, the first bit line driver circuit 102a shown in FIG. 3 has the following configuration in the first cell array 103a: A write circuit 810 for writing data to a selected memory cell, and a first cell array A read circuit 811 generates a signal containing the data read from the I 103a as information. The write circuit 810 includes a decoder 812 and a level shifter 813. and a selector 814.

[0034] The second bit line driving circuit 102b and the third bit line driving circuit 102c have the same circuit configuration. The configuration of the second bit line driving circuit 102a is the same as that of the first bit line driving circuit 102a. The specific circuit configurations of the first bit line driving circuit 102b and the third bit line driving circuit 102c are the same as those of the first bit line driving circuit 102a and the third bit line driving circuit 102b. The circuit configuration of the output line driver circuit 102a can be referred to.

[0035] The word line driving circuit 101 shown in FIG. 3 includes a decoder 815, a level shifter 816, and , and a buffer 817.

[0036] Next, a specific example of the operation of the drive circuit shown in FIG. 3 will be described.

[0037] A signal AD including address (Ax, Ay) as information is input to the control circuit 110 shown in FIG. Then, the control circuit 110 determines that the memory cell at the address is in the first cell array 103a, It is determined whether the cell belongs to the second cell array 103b or the third cell array 103c. For example, if the memory cell belongs to the first cell array 103a, the address column direction The address Ax, which is information about the direction, is transmitted to the first bit line corresponding to the first cell array 103a. The control circuit 110 also sends a signal DAT containing data as information to the drive circuit 102a. A is sent to the first bit line driving circuit 102a. The address Ay, which is the information, is sent to the word line driving circuit 101 .

[0038] Data write and read operations in the first cell array 103a to the third cell array 103c The read operation is selected by a signal RE (Read enable) supplied to the control circuit 110. , signal WE (Write enable), etc.

[0039] For example, when a write operation is selected by a signal WE in the first cell array 103a, In accordance with an instruction from the control circuit 110, the decoder 815 of the word line driving circuit 101 In this case, a signal for selecting a memory cell corresponding to the address Ay is generated. The signal is adjusted in amplitude by a level shifter 816, and then the waveform is converted into a waveform by a buffer 817. The data is processed and input to the first cell array 103a via the first word line.

[0040] On the other hand, the first bit line driving circuit 102a performs decoding in accordance with an instruction from the control circuit 110. Among the memory cells selected in the data register 812, a memory cell corresponding to the address Ax is selected. The amplitude of the signal is adjusted by a level shifter 813. After being input, the signal is input to the selector 814. The selector 814 selects a signal according to the input signal. The signal data is sampled and stored in the memory cell corresponding to the address (Ax, Ay). Input the filtered signal.

[0041] When a read operation is selected by the signal RE, the control circuit 110 Then, the decoder 815 included in the word line driving circuit 101 receives the address Ay. A signal for selecting a memory cell is generated. The signal is shifted by a level shifter 816. After the amplitude is adjusted by the buffer 817, the waveform is processed and output to the first cell array 103. On the other hand, the read circuit 811 included in the first bit line driver circuit 102a is In accordance with an instruction from the control circuit 110, among the memory cells selected by the decoder 815, Then, the read circuit 811 selects a memory cell corresponding to the address Ax. The data stored in the memory cell corresponding to the address (Ax, Ay) is read out, and the data A signal containing the information is generated.

[0042] Note that the memory device according to one embodiment of the present invention may be a memory device that can be mounted on a printed wiring board or the like. The device was in a packaged state, with connection terminals provided and protected by resin or the like. That's fine.

[0043] The control circuit 110 also controls other circuits that configure the memory device (the word line driving circuit 101 and The first bit line driver circuit 102a to the third bit line driver circuit 102c and the first cell array 1 The first cell array 103a to the second cell array 103c may be formed on a single substrate. , may be formed using different substrates.

[0044] If a different substrate is used, FPC (Flexible Printed Circuit) In this case, the electrical connection can be ensured through the control circuit 110. A part of it may be connected to the FPC using a COF (Chip On Film) method. Alternatively, the COG (Chip On Glass) method can be used to ensure electrical connection. This can be done.

[0045] <Example of readout circuit configuration> Next, a specific example of the configuration of the readout circuit will be described.

[0046] The potential read from the cell array varies according to the data written in the memory cell. Therefore, ideally, data of the same digital value is stored in multiple memory cells. If so, the potentials read from multiple memory cells will all be at the same level. However, in reality, transistors that function as capacitance elements and switching elements The characteristics of the data may vary among memory cells. Even if all the data have the same digital value, there will be variations in the actual read potential. However, the read circuit can read the potentials from the cell array. Even if there is some variation, it contains more accurate data as information and still achieves the desired specifications. It is possible to form signals whose amplitude and waveform are processed in a variety of ways.

[0047] FIG. 4 is a circuit diagram showing an example of the configuration of a readout circuit. A switch for controlling the input of the potential Vdata read from the array to the readout circuit. The readout circuit shown in FIG. has an operational amplifier 262.

[0048] The transistor 260, which functions as a switching element, receives a signal at its gate electrode. According to the potential of the signal Sig, the potential Vdata to the non-inverting input terminal (+) of the operational amplifier 262 For example, when the transistor 260 is turned on, the potential Vdata is supplied to the The voltage is applied to the non-inverting input terminal (+) of the operational amplifier 262. The reference potential Vref is applied to the input terminal (-). The potential V of the output terminal depends on whether the potential applied to is higher or lower than the reference potential Vref. The level of out can be different, thereby indirectly including data as information. A signal can be obtained.

[0049] Even if the same data value is stored in memory cells, there may be variations in the characteristics between the memory cells. The variation in the voltage Vdata also causes variations in the level of the read potential Vdata, and the distribution of the voltage Vdata varies widely. Therefore, the level of the reference potential Vref is Therefore, the voltage Vdata is determined taking into consideration the variations in the potential Vdata.

[0050] Also, since Figure 4 shows an example of a readout circuit that handles binary digital values, The operational amplifiers used to read out the data are connected to the nodes to which the potential Vdata is applied. Although the number of operational amplifiers is not limited to this, the number of n-ary (n is a natural number greater than or equal to 2) When dealing with data, the number of operational amplifiers for the node to which the potential Vdata is given is n-1. Let's say.

[0051] <Example of cross-sectional structure of a storage device> FIG. 5 is a cross-sectional view showing an example of the structure of a storage device. The storage device shown in FIG. The device has a cell array 201 in which a plurality of rechargeable cells 670 are provided, and a drive circuit 210 at the bottom. The upper cell array 201 includes a transistor 662 using an oxide semiconductor, and the lower cell array 201 includes a transistor 662 using an oxide semiconductor. The driving circuit 210 uses a semiconductor such as polycrystalline or single crystal silicon or germanium. The transistor 660 is connected to the power supply 620.

[0052] The transistor 660 and the transistor 662 are n-channel transistors and p-channel transistors. In this example, transistor 660, transistor The following description will be given taking as an example a case where all the resistors 662 are n-channel type.

[0053] The transistor 660 is provided on a substrate 600 including a semiconductor such as silicon or germanium. A channel forming region 616 is formed by diffusing impurity atoms. A region 620, a metal compound region 624 in contact with the impurity region 620, and a channel forming region 6 A gate insulating film 608 is provided on the gate insulating film 608. The electrode 610 and the source or drain electrode 624 are electrically connected to the metal compound region 624. The insulating film 628 covers the transistor 660. The source and drain electrodes 630a and 630b are formed on the insulating film 628. The insulating layer 622 is electrically connected to the metal compound region 624 through an opening formed in the insulating layer 622. An electrode 636a is formed on the insulating film 628 in contact with the source or drain electrode 630a. An electrode 636b is formed in contact with the source or drain electrode 630b.

[0054] In addition, an element isolation insulating layer 606 is provided on the substrate 600 so as to surround the transistor 660. In order to achieve high integration, the transistor 660 is It is desirable to have a structure without a sidewall insulating film. When the characteristics of 0 are important, a sidewall insulating film is provided on the side of the gate electrode 610, Including the region with different impurity concentrations formed in the region overlapping with the sidewall insulating film. An impurity region 620 may be provided.

[0055] The transistor 662 is formed on an insulating film 640 that covers the electrodes 636a and 636b. The oxide semiconductor film 644 and the source The oxide semiconductor film 644 is connected to the source or drain electrodes 642a and 642b. The gate insulating film 646 covers the drain electrodes 642a and 642b. a gate electrode 648a provided over the oxide semiconductor film 644 so as to overlap with the oxide semiconductor film 644; .

[0056] The oxide semiconductor film 644 was analyzed by secondary ion mass spectrometry (SIMS). The hydrogen concentration measured by mass spectroscopy was 5×10 19 / cm 3 Less than or equal to 5 x 10 18 / cm 3 Less than or equal to 5 × 10 17 / cm 3 or less, more preferably 1 × 10 16 / cm 3 Furthermore, Hall effect measurements The measurable carrier density of the oxide semiconductor film is 1×10 14 / cm 3 Less than 1 x10 12 / cm 3 less than 1×10 11 / cm 3 In addition, oxidation The band gap of the compound semiconductor is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. Highly purified acid with sufficiently reduced impurity concentrations such as water and hydrogen. By using a nitride semiconductor film, the off-state current of the transistor 662 can be reduced. .

[0057] Here, the analysis of the hydrogen concentration in the oxide semiconductor film will be described. The hydrogen concentration in the conductive film was measured using secondary ion mass spectrometry (SIMS). SIMS analysis is performed using ion mass spectrometry (SIMS). It is difficult to obtain accurate data near the sample surface or near the interface between layers of different materials. Therefore, the distribution of hydrogen concentration in the film in the thickness direction was analyzed by SIMS. When analyzing, the value should be approximately constant without extreme fluctuations within the range where the target film exists. The average value in the area where the value is obtained is adopted as the hydrogen concentration. When the film thickness is small, the hydrogen concentration in the adjacent film affects the film thickness, and a nearly constant value is obtained. In this case, the hydrogen concentration in the area where the film exists may be The maximum or minimum value of the hydrogen concentration in the film is used as the hydrogen concentration in the film. In the region, when there are no mountain-shaped peaks with maximum values ​​or valley-shaped peaks with minimum values, In this case, the value at the inflection point is adopted as the hydrogen concentration.

[0058] Specifically, the off-state current of a transistor using a highly purified oxide semiconductor film as an active layer For example, when the channel width is 1×10 6 μm Even in a device with a channel length of 10 μm, the voltage between the source and drain electrodes (drain When the on-state voltage is in the range of 1V to 10V, the off-state current is Below the detection limit, i.e., 1×10 -13 In this case, the characteristic of A or less can be obtained. The off-current density, which corresponds to the value obtained by dividing the off-current by the channel width of the transistor, is 100 It can be seen that the capacitance is less than zA / μm. A circuit that controls the charge flowing into or out of a capacitor element using the transistor is used. The off-state current density was measured. A semiconductor film is used in the channel forming region, and the charge amount per unit time of the capacitance element is calculated. The off-state current density of the transistor was measured. As a result, the source electrode and drain electrode of the transistor When the voltage between the gate electrodes is 3 V, an even lower off-state current density of several tens of yA / μm is obtained. Therefore, in the semiconductor device according to one embodiment of the present invention, the highly purified oxide The off-state current density of a transistor using a compound semiconductor film as the active layer was measured by Depending on the voltage between the electrodes, it may be 100 yA / μm or less, preferably 10 yA / μm or less, and more preferably 10 yA / μm or less. Preferably, the current density can be reduced to 1 yA / μm or less. The transistor using the film as an active layer has an off-state current of crystalline silicon. This is significantly lower than that of transistors.

[0059] The transistor 662 has a gate insulating film to suppress leakage current between elements due to miniaturization. Although an oxide semiconductor film processed into an island shape is used, a structure that is not processed into an island shape is also adopted. When the oxide semiconductor film is not processed into an island shape, the number of masks can be reduced. This can be done.

[0060] The capacitor 664 includes a source electrode or a drain electrode 642 a, a gate insulating film 646 , and a That is, the source electrode or drain electrode 642a is made of a conductive film 648b. The conductive film 648b functions as one electrode of the capacitor 664, and the conductive film 648c functions as the other electrode of the capacitor 664. This structure ensures sufficient capacitance. It is possible.

[0061] In the transistor 662 and the capacitor 664, the source electrode or the drain electrode The ends of 642a and 642b are preferably tapered. The ends of the source or drain electrode 642a and the source or drain electrode 642b are tapered. This improves the coverage of the gate insulating film 646, and The taper angle is set to, for example, 30° or more. The taper angle is 60° or less. The electrode or drain electrode 642a is aligned in a direction perpendicular to its cross section (a plane perpendicular to the surface of the substrate). This indicates the inclination angle between the side and bottom surfaces of the film when observed from above.

[0062] An insulating film 650 and an insulating film 652 are provided over the transistor 662 and the capacitor 664. The insulating film 646, the insulating film 650, the insulating film 652, etc. Electrodes 654a and 654b are provided in the openings, and the electrodes 654a and 654b are provided on the insulating film 652. The wiring 656 is formed to connect one of the memory cells to another. The wiring 656 is a wiring that connects the electrodes 654b, 642c, and The electrode 626 is connected to the electrode 636c via the electrode 626. The circuit 210 can be connected to the upper cell array 201. Electrode 642c is shown as being electrically connected to electrode 636c via electrode 626. However, an opening is provided in the insulating film 640, and the electrode 642c and the electrode 636c are in direct contact with each other. That's fine.

[0063] 5 shows an example in which one layer of the cell array 201 is stacked on the driving circuit 210. However, one embodiment of the present invention is not limited to this. That is, the cell array 201 can be configured using multiple cell array layers. The second cell array layer is provided on top of the first cell array layer. The same applies to the second and subsequent cell array layers. The same configuration as the first cell array layer can be applied to the second and subsequent layers. For the cell array layer, a different configuration from the first cell array layer can be applied. By applying such a stacked structure, it is possible to further increase the integration of the memory device. do.

[0064] <Regarding the storage device disclosed in this specification> The memory device disclosed in this specification increases the number of memory cells by increasing the number of bit lines. Even if the number of memory cells connected to one bit line is small, the number of memory cells connected to one bit line can be kept small. Since the parasitic capacitance and parasitic resistance of the bit line can be reduced, the area of ​​the capacitance element can be reduced. Even if the difference in the amount of charge between each digital value becomes smaller due to miniaturization, This increases the accuracy of the data being read and reduces the error rate.

[0065] The memory device disclosed in this specification further comprises: dividing a plurality of bit lines into several groups; The bit line driving circuits control the driving of the bit lines for each of the groups. With the above configuration, even if the number of bit lines increases, the aspect ratio of the cell array can be kept from 1 to 100%. This can prevent the device from moving too far to the edge, thereby increasing the versatility of the storage device. In addition, when designing an integrated circuit using a memory device, it is possible to reduce layout constraints. This can be done.

[0066] In addition, the memory device disclosed in this specification divides a plurality of word lines into several groups, The memory cells connected to the bit lines belonging to one group are connected to the word lines belonging to one group. With the above configuration, even if the number of memory cells increases, Therefore, the number of memory cells connected to the word line can be reduced. This reduces the parasitic capacitance and resistance of the signal input to the word line. This prevents the delay of the data transfer or the potential drop of the word line from increasing, and ultimately improves the The error rate can be kept low.

[0067] Furthermore, the memory device disclosed in this specification includes a transistor with extremely low off-state current as a capacitor. By using it as a switching element to hold the charge stored in the capacitor, This prevents leakage of charge from the memory cells, making it possible to retain data for a long period of time. Even if the capacitance value of the capacitive element is reduced by miniaturizing the memory cell, the refresh operation This can prevent the frequency of

[0068] In addition, in the memory device disclosed in this specification, the drive circuit and the cell array are three-dimensionally arranged so as to overlap each other. By integrating the bit line driver circuits, the area occupied by the memory device can be reduced even if a plurality of bit line driver circuits are provided. It is possible.

[0069] <Modification of Transistor> 6 and 7 show examples of the configuration of a transistor different from the transistor 662 shown in FIG. vinegar.

[0070] The transistor 312 illustrated in FIG. 6A includes an oxide semiconductor film 644 and a source electrode or a drain electrode. Between the drain electrodes 642a and 642b, an oxide film is formed, which functions as a source region or a drain region. The oxide semiconductor film 644 and the source electrode 643b are provided. Alternatively, a region functioning as a source region or a drain region may be formed between the drain electrodes 642a and 642b. By providing the oxide conductive films 643a and 643b, the source and drain regions This allows the resistance in the low-resistance region to be reduced, and the transistor 312 can be operated at high speed. In addition, the oxide semiconductor film 644, the oxide conductive films 643a and 643b, and the source electrode or the drain electrode By stacking the drain electrodes 642a and 642b, the breakdown voltage of the transistor 312 is improved. The capacitor 314 includes an oxide conductive film 643b and a source electrode Alternatively, the drain electrode 642b, the gate insulating film 646, and the conductive film 648b may be included. are.

[0071] The transistor 322 illustrated in FIG. 6B includes an oxide semiconductor film 644 and a source electrode or a drain electrode. Between the drain electrodes 642a and 642b, an oxide film is formed, which functions as a source region or a drain region. The structure is the same as that shown in FIG. 6(A) in that the semiconductor layer 640 has the nitride conductive films 643a and 643b. In the transistor 312 shown in FIG. 1A, oxide conductive films 643a and 643b are made of an oxide semiconductor. The upper and side surfaces of the film 644 are in contact with each other, whereas the transistor 322 shown in FIG. In this case, the oxide conductive films 643a and 643b are in contact with each other on the top surface of the oxide semiconductor film 644. Even in such a configuration, it is possible to reduce the resistance of the source region and the drain region. As a result, the transistor 322 can operate at high speed. , oxide conductive films 643a and 643b, and source or drain electrodes 642a and 64 2b, the breakdown voltage of the transistor 322 can be improved. In addition, the description of FIG. 5 can be referred to for the configuration of the capacitor 324.

[0072] The transistor 332 shown in FIG. 7A has a source electrode or a drain electrode over an insulating film 640. Electrodes 642a and 642b, an oxide semiconductor film 644, a gate insulating film 646, and a gate electrode 64 7A. The transistor 662 shown in FIG. 5 has the same structure as the transistor 662 shown in FIG. 5 in that it includes the transistor 8a. The transistor 332 differs from the transistor 662 illustrated in FIG. 5 in that the oxide semiconductor film 644 is , the position where the source electrode or drain electrode 642a, 642b is connected. After the oxide semiconductor film 644 is formed, the transistor 662 is By forming the electrodes 642a and 642b, at least one of the upper surfaces of the oxide semiconductor film 644 is The portion is in contact with the source electrode or drain electrode 642a, 642b. The transistor 332 has a portion of the top surface of the source or drain electrodes 642a, 642b. is in contact with the oxide semiconductor film 644. The structure of the capacitor 334 is similar to that shown in FIG. The following description can be taken into consideration.

[0073] Although the transistors shown in FIGS. 5, 6 and 7A have a top gate structure, the transistors shown in FIGS. 5, 6 and 7A may have a bottom gate structure. 7B and 7C show a bottom-gate transistor. Shows.

[0074] In the transistor 342 shown in FIG. 7B, a gate electrode 648a is provided over the insulating film 640. A gate insulating film 646 is provided on the gate electrode 648a. A source electrode or drain electrode 642a, 642b is provided, a gate insulating film 646, and and the source or drain electrodes 642a, 642b, and a gate electrode 648a is provided on the The oxide semiconductor film 644 is provided so as to cover the insulating film 64 0, a conductive film 648b provided on the gate insulating film 646, and a source electrode or a drain electrode. and electrode 642b.

[0075] In addition, insulating films 650 and 652 are provided over the transistor 342 and the capacitor 344. It may also be included.

[0076] The transistor 352 shown in FIG. 7C includes a gate electrode 648a, a gate the gate insulating film 646, the source or drain electrodes 642a and 642b, and the oxide semiconductor film 6 7B in that it includes a transistor 44. The difference between the transistor 352 shown in FIG. 7B and the transistor 342 shown in FIG. 7B is that the transistor 352 is an oxide semiconductor. The position where the body membrane 644 and the source electrode or drain electrode 642a, 642b contact each other. That is, the transistor 342 has a source electrode or a drain electrode 642a, 642b. b is formed, the oxide semiconductor film 644 is formed, and then at least the oxide semiconductor film 64 A part of the bottom surface of the transistor 4 is in contact with the source electrode or drain electrode 642a, 642b. In contrast, the transistor 352 has source and drain electrodes 642a and 642b. Part of the bottom surface of the capacitor 354 is in contact with the oxide semiconductor film 644. For details, please refer to the description in Figure 7(B).

[0077] The transistor structure is such that gate insulating films are placed above and below the channel formation region. A dual gate structure having two gate electrodes may be used. A transistor with a rugate structure is shown.

[0078] The transistor 362 shown in FIG. 7D includes a gate electrode 648a, a gate the gate insulating film 646, the source or drain electrodes 642a and 642b, and the oxide semiconductor film 6 7B in that it includes a transistor 44. , and further, source and drain electrodes 642a and 642b and an oxide semiconductor film 64 An insulating film 650 is provided to cover the oxide semiconductor film 64. A conductive film 659 is provided to overlap with the second gate insulating film 44. The conductive film 659 functions as a second gate electrode. By doing so, it is possible to carry out bias-thermal stress tests (hereafter referred to as In the BT test, the change in the threshold voltage of a transistor before and after the BT test is The conductive film 659 has the same potential as the gate electrode 648a. In addition, the potential of the conductive film 659 may be GND, 0V, or FLO. It may be in a charging state.

[0079] <An example of a transistor manufacturing method> Next, an example of a method for manufacturing the transistor 662 shown in FIGS. 5A and 5B will be described with reference to FIGS. do.

[0080] First, an oxide semiconductor film is formed over the insulating film 640, and the oxide semiconductor film is processed to form an oxide semiconductor film. Then, a compound semiconductor film 644 is formed (see FIG. 8(A)).

[0081] The insulating film 640 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, The insulating film 640 is formed using a material containing an inorganic insulating material such as aluminum oxide. By using low-k materials, the capacitance caused by overlapping of various electrodes and wiring is reduced. The insulating film 640 is preferably made of the above-mentioned material. Porous insulating layers may be used. Porous insulating layers are more cost-effective than dense insulating layers. This reduces the dielectric constant, making it possible to further reduce the capacitance caused by electrodes and wiring. The insulating film 640 may be formed using an organic insulating material such as polyimide or acrylic. The insulating film 640 can be formed to have a single layer structure or a stacked layer structure using the above-mentioned materials. Here, the case where silicon oxide is used as the insulating film 640 will be described. Reveal.

[0082] The oxide semiconductor used is at least indium (In) or zinc (Zn ) is preferably contained. In particular, it is preferably contained In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of transistors using In addition, it is preferable to have gallium (Ga). It is preferable to have hafnium (Hf) as a stabilizer. It is also preferable to have aluminum (Al) as a stabilizer. preferable.

[0083] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0084] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. You can be there.

[0085] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements other than a and Zn may be included.

[0086] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) It is also possible to use a material represented by the formula: where M is selected from Ga, Fe, Mn, and Co. It refers to one or more metal elements. In addition, as an oxide semiconductor, In3SnO5 (ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0087] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In-Sn-Zn oxide having an atomic ratio or an oxide having a composition close to that.

[0088] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In addition, in order to obtain the required semiconductor characteristics, Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the following appropriate.

[0089] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, even in In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0090] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ c=1), the atomic ratio of the oxide is In:Ga:Zn=A:B:C (A+B+C=1) The oxides of the oxides are close by r if a, b, and c are (a-A) 2 +(b-B) 2 +(c― C) 2 ≦r 2 This means that the following condition is satisfied. For example, r can be set to 0.05. The same is true for monsters.

[0091] The oxide semiconductor may be single-crystal or non-single-crystal. In the latter case, it may be amorphous or polycrystalline. In addition, it may be a structure containing a crystalline portion in an amorphous state or a non-amorphous state. That's fine too.

[0092] Amorphous oxide semiconductors can be easily flattened, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high efficiency. High mobility can be obtained.

[0093] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and the surface By improving the flatness of the oxide semiconductor, it is possible to obtain a mobility higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form it on the surface of 0.1 nm or less.

[0094] For Ra, the centerline average roughness defined in JIS B0601 can be applied to the surface. It is a three-dimensional extension of the method, which is based on the averaging of the absolute values ​​of the deviations from the reference surface to the specified surface. This can be expressed as the "value obtained" and is defined by the following formula:

[0095]

number

[0096] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y1 ) (the rectangular region bounded by the four points represented by (x2, y2)), and Z0 is It refers to the average height of the measurement surface. Ra is measured by an atomic force microscope (AFM). It can be evaluated using a microscope.

[0097] In addition, the oxide semiconductor film is preferably one in which impurities such as hydrogen, water, a hydroxyl group, or hydride are less likely to be mixed. The oxide semiconductor film is preferably formed by a sputtering method, for example. It can be made.

[0098] Here, the oxide semiconductor film is formed by sputtering using an In-Ga-Zn oxide target. It is formed by the ring method.

[0099] As an In-Ga-Zn oxide target, for example, the composition ratio is In2O3: An oxide target with a molar ratio of Ga2O3:ZnO = 1:1:1 can be used. The material and composition of the target do not have to be limited to those mentioned above. For example, In2O3 An oxide target with a composition ratio of Ga2O3:ZnO=1:1:2 [molar ratio] is used. It is also possible.

[0100] The filling rate of the oxide target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. % or less. By using a metal oxide target with a high filling rate, the oxide film This is because the semiconductor film can be made dense.

[0101] The film formation atmosphere is a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. The oxide semiconductor film may be heated under a mixed atmosphere of hydrogen, water, and hydroxyl groups. To prevent contamination with impurities such as hydrogen, water, hydroxyl groups, and hydrides, It is desirable to use an atmosphere using a high purity gas that has been removed.

[0102] For example, the oxide semiconductor film can be formed as follows.

[0103] First, the substrate is held in a film-forming chamber maintained under reduced pressure, and the substrate temperature is increased to 200°C for 5 minutes. 00°C or less, preferably more than 300°C and less than 500°C, more preferably more than 350°C and less than 400°C Heat to below 50°C.

[0104] Next, while removing the remaining moisture in the film-forming chamber, impurities such as hydrogen, water, hydroxyl groups, and hydrides are thoroughly removed. A high-purity gas removed by the removal of the target was introduced into the chamber, and an oxide semiconductor film was deposited on the substrate using the target. To remove residual moisture in the deposition chamber, a cryopump or Adsorption type vacuum pumps such as ion pumps and titanium sublimation pumps can be used. It is also desirable that the exhaust means be a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump contains, for example, hydrogen, water, hydroxyl groups, or hydrogen. Because impurities such as chlorine and fluorine (and more preferably compounds containing carbon atoms) are removed hydrogen, water, a hydroxyl group, hydride, or the like contained in the oxide semiconductor film formed in the film formation chamber The concentration of impurities can be reduced.

[0105] When the substrate temperature during film formation is low (for example, 100°C or less), the oxide semiconductor contains hydrogen atoms. It is preferable to heat the substrate at the above-mentioned temperature because there is a risk of contamination with substances containing fluorine. By heating the substrate at the above temperature to form the oxide semiconductor film, the substrate temperature becomes high. Therefore, the hydrogen bonds are broken by heat, and substances containing hydrogen atoms are incorporated into the oxide semiconductor film. Therefore, when the oxide semiconductor film is formed in a state where the substrate is heated to the above-mentioned temperature, By performing this, impurities such as hydrogen, water, a hydroxyl group, or hydride contained in the oxide semiconductor film can be removed. It is possible to sufficiently reduce the concentration of substances. It is also possible to reduce damage caused by sputtering. This can be done.

[0106] As an example of the film formation conditions, the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, The direct current (DC) power supply was 0.5 kW, the substrate temperature was 400°C, and the film formation atmosphere was oxygen (oxygen flow rate If a pulsed DC power supply is used, the powdery material generated during film formation will This is preferable because it can reduce particles (also called dust) and make the film thickness distribution uniform.

[0107] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced. The powder adhering to the surface on which the oxide semiconductor film is to be formed is removed by performing reverse sputtering to generate plasma. It is preferable to remove the particles or dust particles. This method involves applying a voltage to the plate, generating plasma near the substrate, and modifying the surface of the substrate. Instead of argon, gases such as nitrogen, helium, and oxygen may be used.

[0108] The oxide semiconductor film is processed to form the oxide semiconductor film 644. The oxide semiconductor film is processed by forming a mask of a desired shape on the oxide semiconductor film, and then This can be done by etching the semiconductor film. Alternatively, the ink jet method or the like may be used. The mask may be formed by a dry etching method. It is possible to use either etching or wet etching. Of course, these may be used in combination. .

[0109] After that, the oxide semiconductor film 644 may be subjected to heat treatment (first heat treatment). By performing the treatment, the substance including hydrogen atoms contained in the oxide semiconductor film 644 can be further The structure of the oxide semiconductor film 644 is adjusted to reduce defect levels in the energy gap. The heat treatment temperature is preferably 250°C or higher and 700°C or lower in an inert gas atmosphere. Preferably, the temperature is 450°C or higher and 600°C or lower, or lower than the distortion point of the substrate. Inert gas atmosphere As the main component, an atmosphere containing nitrogen or rare gases (helium, neon, argon, etc.) It is desirable to use an atmosphere that does not contain water, hydrogen, etc. The purity of nitrogen and rare gases such as helium, neon, and argon introduced into the equipment is 6N (99.9%). 999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration 1 ppm or less, preferably 0.1 ppm or less).

[0110] The heat treatment is carried out by, for example, placing the object to be treated in an electric furnace using a resistance heating element, and heating the object in a nitrogen atmosphere. The oxide semiconductor film 644 is not exposed to the air during this time. Do not allow leakage and prevent contamination with water or hydrogen.

[0111] By performing heat treatment, impurities are reduced and the semiconductor becomes i-type (intrinsic semiconductor) or as close to i-type as possible. By forming a thin oxide semiconductor film, a transistor with excellent characteristics can be realized. can.

[0112] The above-mentioned heat treatment has the effect of removing hydrogen and water. This heat treatment can also be called hydration treatment or dehydrogenation treatment. It can also be performed before processing the body film into islands or after forming the gate insulating film. In addition, such dehydration and dehydrogenation treatments can be carried out not only once but also multiple times. good.

[0113] Note that oxide semiconductors are insensitive to impurities, and the film contains a considerable amount of metal impurities. There is no problem even if it is used in a low-cost sodalite, which contains a large amount of alkali metals such as sodium. It has been pointed out that ash glass can also be used (Kamiya, Nomura, Hosono, "Amorphous Oxide Semiconductors" "Current Status of Physical Properties and Device Development," Solid State Physics, September 2009, Vol. 44, pp. 62 1-633.) However, this is not an appropriate indication. Alkali metals do not form oxide semiconductors. Alkaline earth metals are not constituent elements of oxide semiconductors, so they are considered impurities. In particular, Na, among alkali metals, is an impurity when it is not an element that is present in the alloy. When the insulating film in contact with the semiconductor film is an oxide, Na diffuses into the insulating film.+ It becomes. In addition, Na breaks the bond between the metal and oxygen that constitute the oxide semiconductor in the oxide semiconductor film. As a result, for example, the threshold voltage may change in the negative direction. This shift leads to deterioration of transistor characteristics, such as normally-on and reduced mobility. This impurity causes transistor characteristics to vary. The deterioration and variation of the characteristics occur when the hydrogen concentration in the oxide semiconductor film is sufficiently low. Therefore, when the hydrogen concentration in the oxide semiconductor film is 5×10 19 cm -3 Below Below, especially 5x10 18 cm -3 If the concentration of the impurities is less than or equal to Specifically, the measured value of the Na concentration by secondary ion mass spectrometry is 5 × 10 16 / cm 3 Less than 1 × 10 16 / cm 3 or less, more preferably 1 × 10 15 / cm 3 Similarly, the measured value of Li concentration should be 5×10 15 / cm 3 The following is preferred: 1×10 15 / cm 3 Similarly, the measured value of the K concentration should be 5 x 10 15 / cm 3 Less than 1 × 10 15 / cm 3 The following would be appropriate.

[0114] In addition, an impurity element that imparts p-type conductivity, such as tin (Sn), is added to the oxide semiconductor film 644. The oxide semiconductor film 644 may have weak p-type conductivity by using Sn. By including SnOx in the oxide semiconductor target, the oxide semiconductor film 644 As described above, the highly purified oxide semiconductor can be doped with p-type impurity elements. Since the film 644 is intrinsic or substantially intrinsic, impurity elements for valence electron control are not included. By adding a small amount of , it is possible to obtain an oxide semiconductor film that exhibits weak p-type conductivity. As a result, a transistor formed using the oxide semiconductor film 644 can be obtained. (a state in which drain current flows even when no voltage is applied to the gate electrode) In addition, to prevent the normally-on state, it is necessary to A second gate electrode is provided on the side opposite to the gate electrode across the body membrane 644, thereby The threshold voltage may be controlled.

[0115] Note that the oxide semiconductor film 644 may be amorphous. It is preferable to use a crystalline oxide semiconductor film as the region. By using a semiconductor film, the reliability of the transistor (gate bias stress resistance) can be improved. Because it can be increased.

[0116] A crystalline oxide semiconductor film is ideally single-crystal. Axis-aligned crystal (also called CAAC) It is preferable that the oxide contains SiO 2 .

[0117] Here, the c-axis is oriented and the ab plane, surface, or interface is viewed in a triangular or hexagonal shape. The atomic arrangement is such that the metal atoms are layered or the metal atoms and oxygen atoms are layered on the c-axis. The a-axis and b-axis are oriented differently on the ab plane (rotating around the c-axis). C-Axis Aligned Crystal (CAAC) We will explain about this.

[0118] In a broad sense, oxides containing CAAC are non-single crystals that are not single crystals and are not uniform in size when viewed from the direction perpendicular to the ab plane. The atomic arrangement is triangular, hexagonal, equilateral triangular or equilateral hexagonal, and perpendicular to the c-axis direction. When viewed from the direction, it is an acid containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. It refers to a monster.

[0119] CAAC is not a single crystal, but it is not made up of only amorphous material. AC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is not clearly defined. Sometimes it's impossible to tell for sure.

[0120] When the CAAC contains oxygen, a part of the oxygen may be replaced with nitrogen. The c-axis of each crystalline part that composes the CAAC is aligned in a certain direction (for example, the substrate surface supporting the CAAC, C Or, the individual CAACs may be aligned in a direction perpendicular to the surface of the CAAC. The normal to the ab plane of the crystal part of the CAAC is in a certain direction (for example, the substrate surface supporting the CAAC, It may be oriented in a direction perpendicular to the surface of the

[0121] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Depending on the composition, they may be transparent or opaque to visible light. Do it.

[0122] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface or the supporting substrate surface. When observed from the direction, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, When the metal atoms are mixed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Crystals may also be mentioned.

[0123] CAAC will be described in detail with reference to Figures 12 to 14. 12 to 14, the upward direction is the c-axis direction, and the plane perpendicular to the c-axis direction is the ab-plane. Oh, when we simply say the upper half and the lower half, we mean the upper and lower halves as viewed from the ab plane.

[0124] Figure 12(A) shows one hexacoordinated In atom and six tetracoordinated oxygen atoms (hereafter referred to as 4) adjacent to the In atom. The structure shown has a metal atom and a nearby oxygen atom. The structure shown in Figure 12(A) is an octahedral structure, but it can be easily For simplicity, the structure is shown in a plan view. There are three O atoms in each group, each with four coordinates. The small group shown in Figure 12(A) has a zero charge.

[0125] Figure 12(B) shows one pentacoordinate Ga atom and three tricoordinate oxygen atoms (hereafter referred to as 3) adjacent to the Ga atom. The structure shown has a tetracoordinated O atom and two tetracoordinated O atoms adjacent to Ga. Both exist on the ab plane. There is one each in the upper and lower halves of Figure 12(B). In addition, since In also has five-coordination, it can take the structure shown in Figure 12(B). The small group shown in FIG. 12(B) has a charge of 0.

[0126] FIG. 12(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 12(C) has one tetracoordinate O atom, and the lower half has three tetracoordinate O atoms. Alternatively, in the upper half of Figure 12(C), there are three 4-coordinate O atoms, and in the lower half there is one There may be four-coordinated O atoms. The small group shown in Figure 12(C) has a zero charge.

[0127] FIG. 12(D) shows a structure having one hexacoordinated Sn atom and six tetracoordinated O atoms adjacent to the Sn atom. The upper half of Figure 12(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 12(D) has a charge of +1.

[0128] Figure 12(E) shows a small group containing two Zn atoms. The upper half of Figure 12(E) shows one Zn atom. The small group shown in Figure 12(E) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. has a charge of -1.

[0129] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a This is called a large group (also called a unit cell).

[0130] Here, we will explain the rules for combining these small groups. The three O atoms in the upper half of the hexacoordinated In atom have three neighboring In atoms in the downward direction, and the lower half Each of the three O atoms has three adjacent In atoms in the upward direction. An O has one neighboring Ga in the downward direction, and an O in the lower half has one neighboring Ga in the upward direction. One O atom in the upper half of the 4-coordinated Zn has one neighboring Zn atom in the downward direction, and Each of the three O atoms has three adjacent Zn atoms in the upward direction. The number of tetrahedral O atoms is equal to the number of adjacent metal atoms below the O atoms. The number of tetrahedral O atoms below the O is equal to the number of adjacent metal atoms above the O. Because of the coordination, the sum of the number of neighboring metal atoms below and the number of neighboring metal atoms above is 4 Therefore, the number of tetrahedral O atoms above a metal atom and the number of O atoms below another metal atom are When the sum of the number of tetracoordinated O atoms in the For example, a hexacoordinated metal atom (In or Sn) can be bonded to a tetracoordinated metal atom in the lower half. When bonding via O, there are three tetracoordinate O atoms, so the five-coordinate metal atom (Ga or In) or the tetracoordinated O in the top half of a tetracoordinated metal atom (Zn) becomes.

[0131] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinated oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0132] Figure 13(A) shows a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. Figure 13(B) shows a large group consisting of three medium groups. C) shows the atomic arrangement when the layer structure of FIG. 13(B) is observed from the c-axis direction.

[0133] In FIG. 13(A), for simplicity, the tricoordinate O atoms are omitted, and only the number of the tetracoordinate O atoms is shown. For example, the circle indicates that there are three tetrahedral O atoms in the upper and lower halves of Sn. Similarly, in FIG. 13(A), the upper and lower halves of In are Each has one tetracoordinate O atom, which is shown as a circled 1. Similarly, in Figure 13 In (A), there is one tetracoordinate O in the bottom half and three tetracoordinate O in the top half. Zn with one tetrahedral O atom in the top half and three tetrahedral O atoms in the bottom half. This shows that:

[0134] In Fig. 13(A), the middle group, which is composed of the In-Sn-Zn-O system layer structure, is Sn has three tetrahedral O atoms in the upper half and three in the lower half, and one tetrahedral O atom in the upper half. In is bonded to the In in the upper and lower halves, and the In is bonded to the Z n, and three tetracoordinate O atoms bond to the upper half of the Zn via one tetracoordinate O atom in the lower half of the Zn. and In in the lower half, which is bonded to Zn2 with one tetrahedral O in the upper half. It bonds to a small group consisting of 4, 4, and 4 through one 4-coordinate O in the lower half of this small group. Three O atoms are bonded to the Sn atoms in the upper and lower halves. Multiple loops are combined to form large groups.

[0135] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6 67, -0.5. For example, In (6-coordinate or 5-coordinate), Zn (4 The charges of Sn (5 or 6 coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, a layer structure containing Sn is formed. To do this, a charge of -1 is required to cancel out the charge of +1. 2(E), there is a small group containing two Zn atoms. For example, there are Sn-containing If there is one small group containing two Zn atoms for every small group, the charges are canceled out. Therefore, the total charge of the layer structure can be set to zero.

[0136] Specifically, the large group shown in Figure 13(B) is repeated to form In-Sn-Zn -O system crystal (In2SnZn3O8) can be obtained. -Zn-O system layer structure is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) It can be expressed by the composition formula:

[0137] In addition, there are oxides of quaternary metals such as In-Sn-Ga-Zn oxides and ternary In-Ga-Zn oxide (also written as IGZO), which is an oxide of the elemental metal, In- Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-A l-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-C e-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm -Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb- Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Z n-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn In-Zn oxides, Sn-Zn oxides, and Al oxides are binary metal oxides. -Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, and I The same applies when n-Ga-based oxides are used.

[0138] For example, Figure 14(A) shows a model of the middle group consisting of an In-Ga-Zn-O system layer structure. A diagram is shown.

[0139] In FIG. 14(A), the middle group, which is composed of an In-Ga-Zn-O-based layer structure, is In the upper half and lower half, there are three tetracoordinate O atoms, and in the lower half, there is one tetracoordinate O atom. It bonds to the Zn in the center, and one tetracoordinate O is bonded to the Zn via the three tetracoordinate O atoms in the lower half of the Zn. It bonds to Ga atoms in the upper and lower halves, respectively, and is bonded to one tetracoordinate O atom in the lower half of the Ga atom. The structure is such that three tetracoordinate O atoms are bonded to three In atoms in the upper and lower halves. Multiple medium groups combine to form large groups.

[0140] Figure 14(B) shows a large group consisting of three medium groups. 14(B) shows the atomic arrangement when the layer structure of FIG. 14(B) is observed from the c-axis direction.

[0141] Here, the charges of In (6- or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are Since the valence numbers are +3, +2, and +3 respectively, the small group containing either In, Zn, or Ga is , the charge is 0. Therefore, if these small groups are combined, the combination of the medium groups The total charge is always 0.

[0142] The middle group, which is composed of an In-Ga-Zn-O layer structure, is shown in FIG. Not limited to the middle group, large-sized compounds with different arrangements of In, Ga, and Zn are also available. Groups can also be taken.

[0143] An oxide semiconductor film composed of CAAC can also be fabricated by a sputtering method. To obtain an oxide semiconductor film made of CAAC by sputtering, The hexagonal crystals are formed in the initial stage of deposition of the semiconductor film, and the crystals It is important to grow the crystal using the target as a seed. The distance between the substrates is kept large (for example, about 150 mm to 200 mm), and the substrate heating temperature is set to 100 °C to 500 °C, preferably 200 °C to 400 °C, and more preferably 250 °C to 300 °C. In addition, the deposited film is preferably heated at a temperature higher than the substrate heating temperature during film formation. By heat-treating the oxide semiconductor film, micro defects contained in the film and defects at the stacking interface can be repaired. It can be recovered.

[0144] The oxide semiconductor film made of CAAC is highly purified and has fewer defects due to oxygen vacancies. Moreover, the c-axis oriented crystal structure makes it structurally sensitive to impurity elements that control valence electrons. This makes it easier to control the valence electrons to a weak p-type.

[0145] Next, a source electrode and a drain electrode (which are formed in the same layer as the oxide semiconductor film 644) are formed on the oxide semiconductor film 644 and the like. A conductive layer for forming a semiconductor device (including wiring) is formed, and the conductive layer is processed to form a semiconductor device. Then, source or drain electrodes 642a and 642b are formed (see FIG. 8B).

[0146] The conductive layer can be formed by using a PVD method or a CVD method. These are made from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. The selected elements and alloys containing the above elements can be used. Magnesium, zirconium, beryllium, neodymium, scandium, or A combination of these materials may also be used.

[0147] The conductive layer may have a single layer structure or a laminated structure of two or more layers. single-layer structure of silicon film or titanium nitride film, single-layer structure of aluminum film containing silicon, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film Examples include a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated. In addition, when the conductive layer has a single layer structure of a titanium film or a titanium nitride film, a tapered shape is The advantage is that it is easy to process the source electrode or drain electrode 642a, 642b. There is a to.

[0148] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxide Indium-zinc oxide alloy (In2O3-ZnO), or these metal oxide materials It is possible to use a material containing silicon or silicon oxide.

[0149] The etching of the conductive layer is performed to form the source or drain electrodes 642a, 642b. It is preferable to perform the process so that the end portion has a tapered shape. Here, the taper angle is, for example, , preferably 30° or more and 60° or less. , the end of 642b is etched to have a tapered shape, This improves the coverage of the gate insulating film 646 and prevents discontinuities.

[0150] The channel length (L) of the upper transistor is determined by the source or drain electrode 642a and The distance between the bottom end of the source electrode or drain electrode 642b is determined by the distance between the bottom end of the source electrode or drain electrode 642a and the bottom end of the drain electrode 642b. Exposure for forming masks used to form transistors with a channel length (L) of less than 25 nm When carrying out this work, extreme ultraviolet rays with a wavelength of several nanometers to several tens of nanometers are used. It is desirable to use extreme ultraviolet light. Exposure to extreme ultraviolet light provides high resolution and a good depth of focus. Therefore, the channel length (L) of the transistor to be formed later should be set to 10 nm or more. It is possible to make it 00nm (1μm) or less, which makes it possible to increase the operating speed of the circuit. Furthermore, miniaturization can also reduce the power consumption of a memory device.

[0151] Next, an oxide semiconductor film is formed on the source electrode 642a or the drain electrode 642b. A gate insulating film 646 is formed so as to be in contact with a part of 644 (see FIG. 8C).

[0152] The gate insulating film 646 can be formed by a CVD method, a sputtering method, or the like. The gate insulating film 646 is made of silicon oxide, silicon nitride, silicon oxynitride, or gallium oxide. ammonium, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, hafnium Hafnium silicate (HfSixOy (x>0, y>0)), nitrogen-doped hafnium silicate Hafnium aluminate (HfSixOy(x>0, y>0)), nitrogen-doped hafnium aluminate It is preferable to form the layer so as to contain HfAlxOy (x>0, y>0), etc. The gate insulating film 646 may have a single layer structure or a stacked structure using a combination of the above materials. The thickness is not particularly limited, but when miniaturizing a memory device, It is desirable to make it thin to ensure the operation of the transistor. For example, In this case, the thickness is set to 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less. This can be done.

[0153] As described above, if the gate insulating film 646 is thinned, the gate resistance due to the tunnel effect or the like is reduced. To solve the gate leakage problem, the gate insulating film 646 is provided with an oxide film. Hf, tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy( x>0, y>0), nitrogen-doped hafnium silicate (HfSixOy(x>0 , y>0), nitrogen-doped hafnium aluminate (HfAlxOy(x>0, y It is recommended to use high-k materials such as By using it as the gate insulating film 646, it is possible to suppress gate leakage while ensuring electrical characteristics. It is possible to increase the film thickness. silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, etc. It may also have a laminated structure with a film containing either of them.

[0154] In addition, the insulating film in contact with the oxide semiconductor film 644 (the gate insulating film 64 in FIG. 8C) 6) may be an insulating material containing a Group 13 element and oxygen. Many of them contain elements from Group 13, and insulating materials containing these elements are compatible with oxide semiconductors. By using this for an insulating film in contact with an oxide semiconductor film, the state of the interface with the oxide semiconductor film can be improved. You can keep it good.

[0155] Here, the insulating material containing a Group 13 element refers to an insulating material containing one or more Group 13 elements. Examples of insulating materials containing Group 13 elements include gallium oxide, There are aluminum, aluminum gallium oxide, and aluminum gallium oxide. Aluminum gallium oxide is a material that has a higher aluminum content than gallium content (atomic %). Gallium aluminum oxide refers to the material with a high gallium content (atomic %). This indicates that the content (atomic %) of aluminum is equal to or greater than the content (atomic %) of aluminum.

[0156] For example, when a gate insulating film is formed in contact with an oxide semiconductor film containing gallium, By using a material containing gallium oxide for the gate insulating film, the interface between the oxide semiconductor film and the gate insulating film In addition, the oxide semiconductor film and the insulating film containing gallium oxide can be formed on the substrate. By providing the insulating film in contact with the oxide semiconductor film, hydrogen pile-up at the interface between the oxide semiconductor film and the insulating film can be prevented. Note that when an element in the same group as a component element of an oxide semiconductor is used for the insulating film, For example, a material containing aluminum oxide can provide the same effect. It is also effective to form an insulating film using aluminum oxide. Therefore, the use of this material can prevent water from entering the oxide semiconductor film. It is also preferable in terms of preventing intrusion.

[0157] The insulating film in contact with the oxide semiconductor film 644 is subjected to heat treatment in an oxygen atmosphere or oxygen doping. It is preferable to make the insulating material have more oxygen than the stoichiometric composition ratio by using a filter or the like. Oxygen doping refers to adding oxygen to the bulk. The term "acid" is used to clarify that the acid is added not only to the surface of the thin film but also to the inside of the thin film. The elemental doping includes oxygen plasma doping in which oxygen in plasma form is added to the bulk. The oxygen doping may be performed by ion implantation or ion doping.

[0158] For example, when gallium oxide is used as an insulating film in contact with the oxide semiconductor film 644, By performing heat treatment under atmospheric conditions and oxygen doping, the composition of gallium oxide is changed to GaO x (X=3+α, 0<α<1). When aluminum oxide is used as an insulating film, heat treatment in an oxygen atmosphere or oxygen doping By performing the above, the composition of aluminum oxide is changed to AlO X (X=3+α, 0<α<1) Alternatively, a gallium oxide insulating film can be used as an insulating film in contact with the oxide semiconductor film 644. When aluminum (aluminum gallium oxide) is used, heat treatment in an oxygen atmosphere, By doping with oxygen, gallium aluminum oxide (aluminum gallium oxide) The composition of Ga X Al 2-X O 3+α (0 <X<2、0<α<1)とすることができる。

[0159] By performing oxygen doping treatment, an insulating film having a region with more oxygen than the stoichiometric composition ratio can be obtained. When the insulating film having such a region is in contact with the oxide semiconductor film, As a result, excess oxygen in the insulating film is supplied to the oxide semiconductor film, and oxygen is The oxide semiconductor film is made into an i-type oxide semiconductor film by reducing oxygen deficiency defects at the interface between the oxide semiconductor film and the insulating film. The oxide semiconductor can be an oxide semiconductor that is almost i-type or i-type.

[0160] Note that the insulating film having a region with more oxygen than the stoichiometric composition ratio is used instead of the gate insulating film 646. In addition, the oxide semiconductor film 644 may be applied to a base film, such as the gate insulating film 646 and the base insulating film 648. It may be applied to both the velum and the velum.

[0161] After the gate insulating film 646 is formed, a second thermal treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 The temperature is between 0°C and 350°C. For example, heat treatment can be performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, the variation in the electrical characteristics of the transistors can be reduced. When the gate insulating film 646 contains oxygen, the oxide semiconductor film 644 Oxygen is supplied to the oxide semiconductor film 644 to compensate for oxygen vacancies in the oxide semiconductor film 644, thereby forming an i-type (intrinsic) semiconductor. Alternatively, an oxide semiconductor film that is as close to i-type as possible can be formed.

[0162] Here, the second heat treatment is performed after the gate insulating film 646 is formed. The timing of the treatment is not limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. The second heat treatment may be performed after the first heat treatment, or after the first heat treatment. The first heat treatment may be performed in combination with the second heat treatment, or the second heat treatment may be performed in combination with the first heat treatment. stomach.

[0163] As described above, by applying at least one of the first heat treatment and the second heat treatment, the oxide The semiconductor film 644 is highly purified so that it does not contain any substances containing hydrogen atoms as much as possible. can.

[0164] Next, a conductive layer is formed to form the gate electrode (including the wiring formed in the same layer). The conductive layer is processed to form a gate electrode 648a and a conductive film 648b (FIG. 8 (See (D)).

[0165] The gate electrode 648a and the conductive film 648b are made of molybdenum, titanium, tantalum, or tungsten. Metallic materials such as tin, aluminum, copper, neodymium, scandium, etc., or materials containing these as their main components The gate electrode 648a and the conductive film 648 can be formed using an alloy material. b may have a single layer structure or a laminated structure.

[0166] As described above, the transistor 662 including the purified oxide semiconductor film 644 and the capacitor The capacitor 664 is completed (see FIG. 8(D)).

[0167] When the transistor 332 and the capacitor 334 shown in FIG. 7A are formed, an insulating film A source electrode or a drain electrode 642a, 642b is formed on the insulating film 640. An oxide semiconductor film 644 is formed over the source and drain electrodes 642a and 642b. Next, the source and drain electrodes 642a and 642b and the oxide semiconductor film 64 A gate insulating film 646 is then formed on the gate insulating film 646. A gate electrode 648a is formed so as to overlap the film 644, and a source electrode or a drain electrode A conductive film 648b is formed to overlap with 642b.

[0168] When the transistor 342 and the capacitor 344 shown in FIG. 7B are formed, an insulating film A gate electrode 648a and a conductive film 648b are formed on the insulating film 640. A gate insulating film 646 is formed on the conductive film 648a and the conductive film 648b. 6, source and drain electrodes 642a and 642b are formed. An oxide semiconductor film 644 is formed over the insulating film 646 to overlap with the gate electrode 648a. By this, the transistor 342 and the capacitor 344 are completed. Insulating films 650 and 652 may be formed to cover the insulating film 650 and the capacitor 344. For example, the insulating film 650 is formed by oxidizing an insulating material through heat treatment in an oxygen atmosphere or oxygen doping. The insulating film 652 preferably has a higher oxygen content than the stoichiometric composition ratio. The insulating film 652 is preferably impermeable to water and hydrogen. This prevents water and hydrogen from entering the oxide semiconductor film 644. The oxygen vacancies in the oxide semiconductor film 644 are reduced by adjusting the oxygen content of the oxide semiconductor film 644 to a value higher than the stoichiometric ratio. By filling the gap, the i-type or nearly i-type oxide semiconductor film 644 can be formed. Because.

[0169] In addition, when the transistor 352 and the capacitor 354 shown in FIG. 7C are formed, an insulating film A gate electrode 648a and a conductive film 648b are formed on the insulating film 640. A gate insulating film 646 is formed on the conductive film 648a and the conductive film 648b. An oxide semiconductor film 644 is formed over the gate electrode 648a so as to overlap with the gate electrode 648a. The source and drain electrodes 642a and 642b are formed over the oxide semiconductor film 644. By this, the transistor 352 and the capacitor 354 are completed. For the insulating film 652, the description of FIG. 7B can be referred to.

[0170] In addition, when the transistor 362 and the capacitor 364 shown in FIG. 7D are formed, an insulating film A gate electrode 648a and a conductive film 648b are formed on the insulating film 640. A gate insulating film is formed on 48a (the first gate electrode in FIG. 7D) and the conductive film 648b. 646 (the first gate insulating film in FIG. 7(D)). Next, the gate insulating film 6 An oxide semiconductor film 644 is formed over the gate electrode 648a so as to overlap with the oxide semiconductor film 644. Source and drain electrodes 642a and 642b are formed on the semiconductor film 644. Then, an insulating film is formed on the oxide semiconductor film 644 and the source and drain electrodes 642a and 642b. An insulating film 650 (a second gate insulating film in FIG. 7D) is formed, and an oxide semiconductor film 64 A conductive film 659 (a second gate electrode in FIG. 7D) is formed so as to overlap with the gate electrode 4. In this way, the transistor 362 and the capacitor 364 are completed. The description of the port electrode 648a can be taken into consideration.

[0171] Next, a manufacturing method of the transistor and the capacitor shown in FIGS. 6A and 6B will be described. Reveal.

[0172] A method for manufacturing the transistor 312 and the capacitor 314 shown in FIG. 6A will be described.

[0173] First, an oxide semiconductor film 644 is formed over the insulating film 640. Over the film 644, a stack of an oxide conductive film and a conductive layer is formed.

[0174] The oxide conductive film is formed by sputtering, vacuum deposition (electron beam deposition, etc.), The arc discharge ion plating method and the spray method are used. zinc oxide, zinc aluminum oxide, zinc aluminum oxide nitride, zinc gallium oxide In addition, silicon oxide can be added to the above materials. The method and material for forming the conductive layer are the same as those for forming the source electrode or the drain electrode. The description of the conductive layer for forming the electrodes 642a and 642b can be referred to.

[0175] Next, a mask is formed on the conductive layer, and the conductive layer and the oxide conductive film are selectively etched. As a result, the source and drain electrodes 642a and 642b and the oxide conductive film 64 3a, forming 643b.

[0176] Note that when the conductive layer and the oxide conductive film are etched, the oxide semiconductor film is etched excessively. To prevent this, the etching conditions (type of etching material, concentration, etching time, etc.) Adjust as appropriate.

[0177] Next, the source and drain electrodes 642a and 642b and the oxide semiconductor film 644 A gate insulating film 646 is then formed on the oxide semiconductor film 6 A gate electrode 648a is formed so as to overlap with the source electrode or drain electrode 64 A conductive film 648b is formed to overlap with 2b.

[0178] Through the above steps, the transistor 312 and the capacitor 314 are completed (see FIG. 6A).

[0179] When the transistor 322 and the capacitor 324 illustrated in FIG. 6B are manufactured, an oxide semiconductor The oxide semiconductor film and the oxide conductive film are stacked on the same photoresist. The shape is processed by a lithography process to form an island-shaped oxide semiconductor film and an oxide conductive film. Next, source and drain electrodes 642a and 642b are formed on the island-shaped oxide conductive film. After forming b, the source electrode or drain electrode 642a or 642b is used as a mask to form an island. By etching the oxide conductive film, the oxide conductive film that becomes the source region or the drain region is formed. Conductive films 643a and 643b are formed.

[0180] Next, the source and drain electrodes 642a and 642b and the oxide semiconductor film 644 A gate insulating film 646 is then formed on the oxide semiconductor film 6 A gate electrode 648a is formed so as to overlap with the source electrode or drain electrode 64 A conductive film 648b is formed to overlap with 2b.

[0181] Through the above steps, the transistor 322 and the capacitor 324 are completed (see FIG. 6B).

[0182] In the above-described transistor, the oxide semiconductor film 644 is highly purified. The concentration is 5 x 10 19 / cm 3 Below 5×10 18 / cm 3 The following is more desirable: Kuha 5 x 10 17 / cm 3 The carrier density of the oxide semiconductor film 644 is as follows: The carrier density in a typical silicon wafer (1×10 14 / cm 3 (compared to the degree) , a sufficiently small value (e.g., 1×10 12 / cm 3 Less than 1.45 x 1 0 10 / cm 3 The off-state current of the transistor is also sufficiently small. For example, the off-state current (here, unit channel width) of the transistor at room temperature (25°C) (value per 1 μm) is 100 zA (1 zeptoampere is 1 × 10 -21 A) Below that, it is preferably 10zA or less.

[0183] In addition, the oxide semiconductor film 644 has a sufficiently low concentration of alkali metal and alkaline earth metal. The concentration of alkali metals or alkaline earth metals is reduced, for example, by 5x Na. 10 16 cm -3 Less than 1 × 10 16 cm -3 Below, more preferably 1 × 1 0 15 cm -3 In the case of Li, 5×10 15 cm -3 Less than 1 × 10 15 cm -3 In the case of K, 5×10 15 cm -3 Less than 1 × 10 15 cm -3 The following is the result.

[0184] By using the oxide semiconductor film 644 that has been highly purified and made intrinsic, It is easy to sufficiently reduce the off-state current of such a transistor. By using this, it is possible to obtain a storage device that can retain stored content for an extremely long period of time. can be.

[0185] <Examples of storage device usage> An example of using the above-mentioned storage device will be described below with reference to FIGS.

[0186] FIG. 9 is a block diagram showing an example of the configuration of a microprocessor. The processor includes a CPU 401, a main memory 402, a clock controller 403, a cache controller 404, serial interface 405, I / O port 406, terminal 4 407, an interface 408, a cache memory 409, etc. are formed. The microprocessor shown in Figure 9 is merely an example of a simplified configuration, and may differ from an actual microprocessor. The processor has a wide variety of configurations depending on its application.

[0187] To make the CPU 401 operate at a higher speed, a correspondingly high-speed memory is required. However, it is necessary to use a high-speed, large-capacity memory with an access time that matches the operating speed of the CPU 401. Therefore, the use of large-capacity main memory is generally costly. In addition to the main memory 402, there is also a memory such as an SRAM, which is a memory with a smaller capacity but higher speed than the main memory 402. The cache memory 409 is interposed between the CPU 401 and the main memory 402 . When the CPU 401 accesses the cache memory 409, the main memory 402 This allows high-speed operation regardless of the speed of the

[0188] In the microprocessor shown in FIG. 9, the above-mentioned storage device is used for the main memory 402. The above configuration allows for a highly integrated microprocessor and a highly reliable microprocessor. A processor can be implemented.

[0189] The main memory 402 stores a program executed by the CPU 401. For example, at the beginning of execution, the program stored in the main memory 402 is The downloaded program is downloaded to the cache memory 409. The data is not limited to those stored in the internal memory 402, but may be downloaded from other external memories. The cache memory 409 stores the program executed by the CPU 401. It not only stores data but also functions as a work area, temporarily storing the calculation results of the CPU 401. Store.

[0190] The number of CPUs is not limited to one, but multiple CPUs may be provided. By doing so, the operating speed can be improved. In this case, the processing speed between CPUs If it is done bit by bit, it may cause problems when looking at the overall process, so each slave CP The processing speed of U may be balanced by the master CPU.

[0191] Although a microprocessor is used as an example here, the above-mentioned storage device may be a microprocessor. Its use is not limited to the main memory of a computer. For example, it can be used in the drive circuit of a display device. It is also suitable for use as a video RAM that can be used in a variety of applications, such as the large-capacity memory required for image processing circuits. In addition, it is also used as a large-capacity or small-sized memory in various system LSIs. You can be there.

[0192] 10 is a block diagram showing an example of the configuration of an RF tag. The antenna circuit 551 and the integrated circuit 552 are connected to a power supply circuit. 553, demodulation circuit 554, modulation circuit 555, regulator 556, arithmetic circuit 557, memory The storage device 558 has a boost circuit 559. is.

[0193] Next, an example of the operation of the RF tag 550 will be described. The radio wave is converted into an AC voltage in the antenna circuit 551. The AC voltage from the antenna circuit 551 is rectified to generate a power supply voltage. The power supply voltage generated in is supplied to the arithmetic circuit 557 and the regulator 556. The regulator 556 stabilizes the voltage for the power supply from the power supply circuit 553 or After adjusting the height, the demodulation circuit 554, modulation circuit 555, and arithmetic circuit 556 in the integrated circuit 552 are 57, and supplies it to various circuits such as a memory device 558 or a booster circuit 559.

[0194] The demodulation circuit 554 demodulates the AC signal received by the antenna circuit 551 and outputs it to the subsequent calculation circuit The calculation circuit 557 performs calculation processing according to the signal input from the demodulation circuit 554. When the above-mentioned calculation process is performed, the storage device 558 stores the primary cache. The arithmetic circuit 557 can be used as a flash memory or a secondary cache memory. The signal input from the demodulation circuit 554 is analyzed, and the signal is output in accordance with the command sent from the interrogator. Thus, the output of information in the memory device 558 or the execution of the contents of the instructions in the memory device 558 The signal output from the arithmetic circuit 557 is coded and sent to the modulation circuit 555. The modulation circuit 555 modulates the radio wave received by the antenna circuit 551 in accordance with the signal. The radio waves modulated by the antenna circuit 551 are received by the interrogator.

[0195] In this way, the communication between the RF tag 550 and the interrogator uses radio waves as a carrier. This is done by modulating the carrier. The modulation method also varies depending on the standard, and can be amplitude modulation, frequency modulation, phase modulation, etc. There are various modulation methods, such as modulation with a standard, but any modulation method can be used as long as it conforms to the standard. .

[0196] The signal transmission method is classified into electromagnetic coupling method, electromagnetic induction method, and microwave method depending on the carrier wavelength. They can be classified into various types, such as:

[0197] The boost circuit 559 boosts the voltage output from the regulator 556 and outputs it to the storage device 558. We are supplying it.

[0198] In the RF tag 550 shown in FIG. 10, the above-mentioned storage device is used as the storage device 558. This makes it possible to achieve high integration and high reliability.

[0199] Here, the configuration of the RF tag 550 having the antenna circuit 551 is explained. However, the RF tag shown in Figure 10 does not necessarily have to include an antenna circuit as a component. Furthermore, an oscillator circuit or a secondary battery may be provided in the RF tag shown in FIG.

[0200] (Embodiment 2) The field-effect mobility of insulated gate transistors, not limited to oxide semiconductors, is actually measured as However, the mobility is lower than the original mobility due to various reasons. There are defects inside the semiconductor and defects at the interface between the semiconductor and the insulating film. Using this, we can theoretically derive the field effect mobility assuming that there are no defects inside the semiconductor. Therefore, in this embodiment, an electric field of an ideal oxide semiconductor having no defects inside the semiconductor is The effective mobility is theoretically derived, and fine transistors are fabricated using such oxide semiconductors. The calculation results of the characteristics when a transistor is fabricated are shown below.

[0201] The intrinsic mobility of the semiconductor is μ0, and the measured field-effect mobility is μ. Assuming the existence of potential barriers (grain boundaries, etc.), this can be expressed by the following equation:

[0202]

number

[0203] where E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. Also, if we assume that the potential barrier originates from defects, the Levinson model gives , which can be expressed by the following formula:

[0204]

number

[0205] where e is the elementary charge, N is the average defect density per unit area in the channel, and ε is the The dielectric constant, n is the number of carriers contained in the channel per unit area, C ox is per unit area capacitance, V g is the gate voltage, and t is the channel thickness. In the case of a semiconductor layer, the thickness of the channel can be considered to be the same as the thickness of the semiconductor layer. Drain current I d can be expressed by the following formula:

[0206]

number

[0207] Here, L is the channel length and W is the channel width, where L=W=10 μm. Also, V d is the drain voltage. g Dividing by and taking the logarithm of both sides, we get It looks like this:

[0208]

number

[0209] The right side of number 5 is V g As can be seen from this equation, the vertical axis is a function of ln(I d / Vg ), The horizontal axis is 1 / V g The defect density N can be calculated from the slope of the line I d -V g The defect density can be evaluated from the characteristics. In the case where the ratio of In, tin (Sn), and zinc (Zn) is In:Sn:Zn=1:1:1, The defect density N is 1×10 12 / cm 2 That's about it.

[0210] Based on the defect density thus obtained, equations 2 and 3 are used to calculate μ0 = 120 cm 2 / Vs The mobility measured in defective In-Sn-Zn oxide is 35 cm 2 / V However, the oxide semiconductor without defects inside the semiconductor and at the interface between the semiconductor and the insulating film The mobility of the conductor μ0 is 120 cm 2 It can be expected that / Vs.

[0211] However, even if there are no defects inside the semiconductor, scattering at the interface between the channel and the gate insulating film can cause electrons to be scattered. The transport characteristics of the transistor are affected by the distance x from the gate insulating film interface. The mobility μ1 at the location can be expressed by the following formula:

[0212]

number

[0213] Here, D is the electric field in the gate direction, and B and G are constants. B and G are determined by actual measurements. From the above measurement results, B = 4.75 × 10 7 cm / s, G=10 nm (depth of interface scattering). D increases (i.e., gate voltage increases). Since the second term on the right side of Equation 6 increases, it can be seen that the mobility μ1 decreases.

[0214] Mobility of a transistor using an ideal oxide semiconductor channel with no internal defects The calculation results for μ2 are shown in Figure 15. The calculation was performed using a Synopsys device simulator. Sentaurus Device, a software company, is used to measure the bandgap of oxide semiconductors. The top, electron affinity, relative permittivity, and thickness are set to 2.8 eV, 4.7 eV, and These values ​​were measured for thin films formed by sputtering. This was obtained by

[0215] Furthermore, the work functions of the gate, source, and drain are set to 5.5 eV and 4.6 eV, respectively. The gate insulating film thickness was 100 nm and the relative dielectric constant was 4.6 electron volts. The channel length and width were both 10 μm, and the drain voltage V d is 0 .1V.

[0216] As shown in Figure 15, the mobility is 100 cm at a gate voltage of just over 1 V. 2 / Vs or higher peak However, if the gate voltage is further increased, the interface scattering increases and the mobility decreases. In order to reduce interface scattering, the semiconductor layer surface must be flattened at the atomic level (At Omic Layer Flatness is desirable.

[0217] The characteristics of a miniaturized transistor fabricated using an oxide semiconductor with such mobility are as follows: The results of the calculation of the performance are shown in Figs. 16 to 18. The cross-sectional structure of the transistor used in the calculation The structure of the transistor shown in FIG. + Conductivity type of The semiconductor region 8103a and the semiconductor region 8103c are included. The resistivity of the semiconductor region 8103c is 2×10 -3 Let it be Ωcm.

[0218] The transistor shown in FIG. 19A has a base insulating layer 8101 and a A buried insulating layer 8102 made of aluminum oxide is formed on the buried insulating layer 8102. The transistor is made up of a semiconductor region 8103a, a semiconductor region 8103c, and a semiconductor region sandwiched between them. It has an intrinsic semiconductor region 8103 b which becomes a channel forming region, and a gate 8105 .

[0219] Between the gate 8105 and the semiconductor region 8103b, there is a gate insulating film 8104. The gate 8105 is provided on both sides with sidewall insulators 8106a and 8106b. On top of 8105, there is an insulator 810 to prevent short circuits between the gate 8105 and other wiring. The width of the sidewall insulator is set to 5 nm. A source 8108a and a drain 8108b are provided in contact with the region 8103c. The channel width in this transistor is set to 40 nm.

[0220] The transistor shown in FIG. 19B has a base insulating layer 8101 and a A semiconductor region 8103a and a semiconductor region 8103c are formed on the buried insulating layer 8102. and an intrinsic semiconductor region 8103b sandwiched between them, a gate 8105 with a width of 33 nm, and The gate insulating film 8104 and the sidewall insulator 8106a, and the sidewall insulator 8106b and the insulator 810 19(A) in that it has a source 8108a and a drain 8108b. It is the same as Zista.

[0221] The transistor shown in FIG. 19(A) differs from the transistor shown in FIG. 19(B) in that the sidewall insulation The conductivity type of the semiconductor region under the insulating layer 8106a and the sidewall insulating layer 8106b is shown in FIG. In the transistor shown in A), the sidewall insulators 8106a and 8106b are The semiconductor region is n + In the semiconductor region 8103a and the semiconductor region 8103c, However, in the transistor shown in FIG. 19B, it is an intrinsic semiconductor region 8103b. That is, the semiconductor region 8103a (semiconductor region 8103c) and the gate 8105 are Loff. This area is called the offset area, and its width Loff is the offset area. As is clear from the figure, the offset length is the length of the sidewall insulator 8106a (side It is the same width as the wall insulator 8106b).

[0222] The other parameters used in the calculation are as described above. We used the Sentaurus Device simulation software. The drain current (I d , solid line) and mobility (μ, dotted line) gate voltage (V g The drain voltage (gate-source potential difference) dependence is shown. Flow I d The drain voltage (potential difference between the drain and source) is set to +1V, and the mobility μ is The calculation was made assuming a voltage of +0.1V.

[0223] FIG. 16(A) shows the case where the thickness of the gate insulating film is 15 nm, and FIG. 16(B) shows the case where the thickness of the gate insulating film is 10 nm. In Figure 16(C), the thickness is set to 5 nm. The drain current I d On the other hand, the mobility The peak value of μ and the drain current I in the on-state d There is no noticeable change in the on-state current. At a gate voltage of around 1V, the drain current exceeds 10μA, which is required for memory cells, etc. was shown.

[0224] FIG. 17 shows a transistor having the structure shown in FIG. 19(B), in which the offset length Loff is set to 5n m, the drain current I d (solid line) and mobility μ (dotted line) at gate voltage V g dependence The drain current I d The drain voltage is +1V, and the mobility μ is The calculation was performed with a voltage of +0.1V. FIG. 17(B) shows the result when the thickness is 10 nm, and FIG. 17(C) shows the result when the thickness is 5 nm. This is what happened.

[0225] FIG. 18 shows the offset length Loff of the transistor having the structure shown in FIG. 19(B). The drain current I d (solid line) and mobility μ (dotted line) The drain current I d The drain voltage is +1V, and the mobility μ is The calculation was performed with a voltage of +0.1V. 18(B) is 10 nm, and FIG. 18(C) is 5 nm This is what we have decided.

[0226] In both cases, the thinner the gate insulating film, the more significantly the off-state current decreases, while the peak of the mobility μ decreases. There is no noticeable change in the on-state current or the on-state voltage.

[0227] The peak of the mobility μ is 80 cm in FIG. 2 / Vs, but in Figure 17, cm 2 / Vs, 40cm in Figure 18 2 When the offset length Loff increases, The off-current also shows a similar trend. On the other hand, the on-current It decreases with increasing Loff, but the decrease is much slower than the decrease in off-state current. In both cases, the gate voltage is around 1V, and the drain current is the voltage required for memory cells, etc. It was shown to be greater than 10 μA.

[0228] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0229] (Embodiment 3) A transistor with a channel formation region made of an oxide semiconductor containing In, Sn, and Zn as its main components is The oxide semiconductor film is formed by heating the substrate. By performing heat treatment after formation, good characteristics can be obtained. In this embodiment, oxide semiconductors are elements that are contained in an amount of 5 atomic % or more. By intentionally heating the substrate after the deposition of the semiconductor film, the field-effect mobility of the transistor can be improved. The case where the above is done will be described with reference to FIGS.

[0230] Intentionally heating the substrate after forming an oxide semiconductor film containing In, Sn, and Zn as its main components Therefore, it is possible to improve the field effect mobility of the transistor. This makes it possible to shift the threshold voltage in the positive direction and make the device normally off.

[0231] For example, FIGS. 20(A) to 20(C) show a semiconductor device with a channel length L of 3 μm and containing In, Sn, and Zn as the main components. The oxide semiconductor film has a channel width W of 10 μm and a gate insulating film with a thickness of 100 nm. These are the characteristics of the transistors used. d was set to 10V.

[0232] Figure 20(A) shows the deposition of In, Sn, and Zn as the main components by sputtering without intentionally heating the substrate. The figure shows the transistor characteristics when an oxide semiconductor film having the above structure is formed. The degree is 18.8cm 2 On the other hand, by intentionally heating the substrate, In, S When an oxide semiconductor film containing n or Zn as a main component is formed, the field-effect mobility can be improved. Fig. 20(B) shows the formation of a thin film of In, Sn, and Zn by heating the substrate to 200°C. The transistor characteristics when an oxide semiconductor film is formed are shown. The field-effect mobility is 32.2 cm 2 / Vsec is obtained.

[0233] The field effect mobility was measured by forming an oxide semiconductor film mainly composed of In, Sn, and Zn and then performing a heat treatment. Fig. 20(C) shows the results of the ion implantation of In, Sn, and Zn. After sputtering at 200°C, an oxide semiconductor film containing SiO2 as the main component was heat-treated at 650°C. The transistor characteristics are shown below. In this case, the field effect mobility is 34.5 cm 2 / V sec is obtained.

[0234] By intentionally heating the substrate, moisture is absorbed into the oxide semiconductor film during sputtering. In addition, by performing heat treatment after film formation, the effect of reducing the amount of oxidation can be expected. Hydrogen, hydroxyl groups, or moisture can be released and removed from the oxide semiconductor film. This improvement in field-effect mobility can be achieved by dehydration. Not only do impurities get removed by hydrogenation and dehydrogenation, but the interatomic distance gets shorter due to the increased density. It is also estimated that crystallization can be promoted by removing impurities from an oxide semiconductor and purifying it. Such a highly purified non-single-crystal oxide semiconductor can be ideally 0cm 2 It is estimated that it will be possible to achieve a field-effect mobility of more than 1 / Vsec.

[0235] Oxygen ions are implanted into an oxide semiconductor whose main components are In, Sn, and Zn, and the oxide is then converted into a The hydrogen, hydroxyl groups, or moisture contained in the compound semiconductor is released, and the heat treatment is performed simultaneously or in addition to the heat treatment. The oxide semiconductor may be crystallized by subsequent heat treatment. By the crystallization treatment, a non-single-crystal oxide semiconductor with good crystallinity can be obtained.

[0236] The effect of intentionally heating the substrate during film formation and / or heat treatment after film formation is This not only improves the effective mobility but also contributes to making the transistor normally off. The oxide semiconductor, which is mainly composed of In, Sn, and Zn, was formed without intentionally heating the substrate. The threshold voltage of a transistor with a conductive film as the channel formation region is shifted negatively. However, when an oxide semiconductor film formed by intentionally heating a substrate is used, In this case, the negative shift of the threshold voltage is eliminated. This tendency is shown in Figure 20(A) and Figure 20(B). ) can also be confirmed by comparing

[0237] The threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn. It is possible to achieve a transistor noise by using a composition ratio of In:Sn:Zn=2:1:3. Furthermore, the target composition ratio is In:Sn:Zn By adjusting the ratio of SiO 2 to ... =2:1:3, an oxide semiconductor film with high crystallinity can be obtained.

[0238] The intentional substrate heating temperature or heat treatment temperature is 150°C or higher, preferably 200°C or higher. The temperature is more preferably 400°C or higher, and film formation or heat treatment at higher temperatures can improve the transistor performance. This makes it possible to make the starter normally off.

[0239] In addition, by intentionally heating the substrate during film formation and / or by performing heat treatment after film formation, it is possible to It can improve the stability against as stress. For example, 2MV / cm, 150℃ , and 1 hour application conditions, the drift is less than ±1.5V, preferably 1.0V You can get less than that.

[0240] In fact, Sample 1 was not subjected to heat treatment after the oxide semiconductor film was formed, and Sample 2 was subjected to heat treatment at 650° C. The BT test was carried out on the transistor of sample 2 that had undergone the above.

[0241] First, the substrate temperature is set to 25°C, and V ds is set to 10V, and the V of the transistor gs -I ds Characteristics Next, the substrate temperature was set to 150°C, and V ds was set to 0.1V. Next, the gate V so that the electric field strength applied to the insulating film 608 becomes 2MV / cm gs Apply 20V to Then, V gsNext, the substrate temperature was set to 25°C, and V ds is set to 10V, and the V of the transistor gs -I ds Measurement was carried out. This is a plus BT test It is called.

[0242] Similarly, first set the substrate temperature to 25°C, and then V ds is set to 10V, and the V of the transistor gs -I d s Next, the substrate temperature was set to 150°C, and V ds was set to 0.1V. , V so that the electric field strength applied to the gate insulating film 608 becomes −2 MV / cm. gs Ni-2 0 V was applied and held for 1 hour. gs Next, the substrate temperature was set to 2 5℃, V ds is set to 10V, and the V of the transistor gs -I ds Measurements were carried out. It is called the Inas BT test.

[0243] The results of the positive BT test for sample 1 are shown in Figure 21(A), and the results of the negative BT test are shown in Figure 21(B). The results of the positive BT test for sample 2 are shown in Figure 22(A), and the results of the negative BT test for sample 2 are shown in Figure 22(B). The results are shown in Figure 22(B).

[0244] The threshold voltage fluctuations of sample 1 due to the positive BT test and the negative BT test are as follows: The positive and negative BT tests for sample 2 were 1.80V and -0.42V. The threshold voltage variations due to the BT test were 0.79 V and 0.76 V, respectively. In both Sample 1 and Sample 2, the change in threshold voltage before and after the BT test was small, and the signal It is known to be highly reliable.

[0245] The heat treatment can be carried out in an oxygen atmosphere, but it is first necessary to use a nitrogen or inert gas atmosphere, or a reduced pressure atmosphere. It is also possible to first perform heat treatment under an oxygen-containing atmosphere and then perform heat treatment in an oxygen-containing atmosphere. Adding oxygen to the oxide semiconductor after hydrogenation can further enhance the effect of heat treatment. To add oxygen later, oxygen ions are accelerated by an electric field to form an oxide semiconductor film. Alternatively, a method of injecting the material into the solution may be applied.

[0246] Oxygen vacancies are likely to cause defects in the oxide semiconductor and at the interface with the stacked film. By such heat treatment, excess oxygen is contained in the oxide semiconductor, and thus the oxide semiconductor is steadily generated. The excess oxygen mainly exists in the interstitial The oxygen concentration is 1×10 16 / cm 3 Over 2×10 20 / cm 3 If the following conditions are met, the compound can be contained in the oxide semiconductor without causing distortion or the like to the crystal. .

[0247] Furthermore, by making the oxide semiconductor contain crystals at least in part by heat treatment, For example, when the composition ratio of In:Sn:Zn=1, a more stable oxide semiconductor film can be obtained. Oxide film sputtered using a 1:1 ratio target without intentionally heating the substrate. The semiconductor film was analyzed by X-ray diffraction (XRD) to find a halo pattern. The oxide semiconductor film thus formed is crystallized by heat treatment. The heat treatment temperature can be any temperature, but for example, by performing heat treatment at 650°C, X-ray A clear diffraction peak can be observed by diffraction.

[0248] In fact, XRD analysis of the In-Sn-Zn-O film was carried out. Using the AXS D8 ADVANCE X-ray diffractometer, the out-of-plane method was used. Measured.

[0249] Samples A and B were prepared for XRD analysis. The method for preparing material B will be explained.

[0250] An In-Sn-Zn-O film was formed to a thickness of 100 nm on a dehydrogenated quartz substrate. .

[0251] The In-Sn-Zn-O film was prepared by sputtering in an oxygen atmosphere at a power of 100 W ( The target was In:Sn:Zn=1:1:1 [atomic ratio]. An n-Sn-Zn-O target was used. The substrate heating temperature during film formation was 200°C. The sample prepared in this manner was designated as Sample A.

[0252] Next, a sample prepared in the same manner as sample A was subjected to heat treatment at a temperature of 650°C. The heat treatment is first performed in a nitrogen atmosphere for 1 hour, and then in an oxygen atmosphere without lowering the temperature. The sample was then subjected to a further heat treatment for 1 hour. The sample thus prepared was designated as sample B.

[0253] Figure 25 shows the XRD spectra of sample A and sample B. In sample A, peaks derived from crystals However, in sample B, 2θ was observed around 35 deg and 37 deg to 38 deg. A peak derived from crystals was observed in g.

[0254] In this way, oxide semiconductors containing In, Sn, and Zn as their main components are intentionally heated during film formation. and / or by performing heat treatment after film formation, the characteristics of the transistor can be improved. Cut.

[0255] This substrate heating and heat treatment removes hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors, from the film. In other words, it has the effect of preventing oxide semiconductors from being included in the film or removing them from the film. High purity can be achieved by removing hydrogen, which acts as a donor impurity in the conductor. This allows the transistor to be normally off, and the oxide semiconductor is highly purified. By doing so, the off-current can be reduced to 1 aA / μm or less. The unit indicates the current value per 1 μm of channel width.

[0256] Figure 26 shows the relationship between the off-state current of a transistor and the reciprocal of the substrate temperature (absolute temperature) at the time of measurement. For simplicity, we use the value obtained by multiplying the reciprocal of the substrate temperature at the time of measurement by 1000 (1000 / T) is the horizontal axis.

[0257] Specifically, as shown in FIG. 26, when the substrate temperature is 125° C., the current is 1 aA / μm (1×1 0 -18 A / μm) or less, and at 85°C it is 100zA / μm (1×10 -19 A / μm ) or less, and at room temperature (27°C), it is 1zA / μm (1×10 -21 A / μm or less Preferably, the current is 0.1 aA / μm (1×10 -19 A / μ m) or less at 85°C, -20 A / μm) at room temperature 0.1zA / μm (1×10 -22 A / μm or less.

[0258] However, in order to prevent hydrogen and moisture from being mixed into the oxide semiconductor film during the film formation, Leaks from the chamber and outgassing from the inner walls of the deposition chamber are sufficiently suppressed, resulting in high purity sputtering gas. For example, it is preferable that the sputtering gas has a dew point of -70°C or lower so that moisture is not contained in the film. It is preferable to use a gas that is below the target limit. It is preferable to use a target that has been highly purified so that it does not contain any impurities. Oxide semiconductors whose main components are In, Sn, and Zn can be thermally treated to remove moisture from the film. However, the temperature at which moisture is released is higher than that of oxide semiconductors whose main components are In, Ga, and Zn. Therefore, it is preferable to form a film that does not contain moisture from the beginning.

[0259] In addition, in the sample transistor that was subjected to heat treatment at 650° C. after the oxide semiconductor film was formed, The relationship between the substrate temperature and the electrical characteristics was evaluated.

[0260] The transistor used for the measurement has a channel length L of 3 μm, a channel width W of 10 μm, and Lov is 0 μm, and dW is 0 μm. ds The voltage was set to 10 V. The substrate temperature was -40 The test was carried out at temperatures of 25°C, -25°C, 25°C, 75°C, 125°C and 150°C. In the case of a gate electrode, the overlap width between the gate electrode and a pair of electrodes is called Lov, and the The protrusion of the pair of electrodes is called dW.

[0261] In Figure 23, I ds (solid line) and field-effect mobility (dotted line) gs It also indicates dependency. Figure 24(A) shows the relationship between the substrate temperature and the threshold voltage, and Figure 24(B) shows the relationship between the substrate temperature and the field effect transition. The relationship between the mobility is shown.

[0262] From FIG. 24(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. The range was 1.09V to -0.23V from -40℃ to 150℃.

[0263] Furthermore, it can be seen from FIG. 24(B) that the higher the substrate temperature, the lower the field effect mobility. The temperature range is -40℃ to 150℃ and is 36cm 2 / Vs~32cm 2 / Vs. Therefore, it can be seen that the fluctuations in the electrical characteristics are small within the above temperature range.

[0264] The above-mentioned oxide semiconductor containing In, Sn, and Zn as its main components is used for the channel formation region. According to the transistor, the field effect mobility is 30c while keeping the off current below 1aA / μm. m 2 / Vsec or more, preferably 40cm 2 / Vsec or more, preferably 60cm 2 / Vsec or more, and the on-current value required by the LSI can be satisfied. For example, A FET with L / W=33nm / 40nm, gate voltage 2.7V, drain voltage 1.0V When the on-state current is 12 μA or more, the on-state current required for transistor operation can be Even in a wide temperature range, sufficient electrical characteristics can be ensured. For example, a transistor made of oxide semiconductor is embedded in an integrated circuit made of silicon semiconductor. Even if the chip size is small, it is possible to realize an integrated circuit with new functions without sacrificing operating speed. Cut.

[0265] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes. [Example]

[0266] In this example, an example of a transistor using an In-Sn-Zn-O film as an oxide semiconductor film is described. This will be explained using FIG. 27 etc.

[0267] Figure 27 shows the top of a coplanar top-gate / top-contact transistor. FIG. 27(A) shows a top view of a transistor. 27B) shows a cross section A1-A2 corresponding to the dashed line A1-A2 in FIG. 27A.

[0268] The transistor shown in FIG. 27B is a transistor including a substrate 1101 and a base film provided over the substrate 1101. An insulating layer 1102, a protective insulating film 1104 provided around the base insulating layer 1102, and a base insulating film A high resistance region 1106a and a low resistance region 1106b are provided on the insulating layer 1102 and the protective insulating film 1104. The oxide semiconductor film 1106 has a resistor region 1106b. The gate insulating film 1108 is formed on the oxide semiconductor film 110. A gate electrode 1110 is provided so as to overlap with the gate electrode 6, and a gate electrode 1110 is provided so as to contact with the side surface of the gate electrode 1110. and a pair of sidewall insulating films 1112 provided in contact with at least the low resistance region 1106b. The electrode 1114, at least the oxide semiconductor film 1106, the gate electrode 1110, and a pair of An interlayer insulating film 1116 is provided to cover the electrode 1114, and a layer is provided on the interlayer insulating film 1116. The wiring 11 is connected to at least one of the pair of electrodes 1114 through the opening. 18 and has.

[0269] Although not shown, a protective film is provided to cover the interlayer insulating film 1116 and the wiring 1118. By providing the protective film, the surface conduction of the interlayer insulating film 1116 can be prevented. This can reduce the minute leakage current that occurs due to the gate insulating film, thereby reducing the off-state current of the transistor. It is possible.

[0270] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Example]

[0271] In this example, a transistor using an In-Sn-Zn-O film as an oxide semiconductor film, which is different from the above, was used. Another example of a register is shown below.

[0272] FIG. 28 is a top view and a cross-sectional view showing the structure of the transistor fabricated in this example. 28(A) is a top view of the transistor. Also, FIG. 28(B) is a chain diagram of FIG. 28(A). A cross section B1-B2 corresponding to the line B1-B2 is shown.

[0273] The transistor shown in FIG. 28B is a transistor including a substrate 1600 and a base film provided over the substrate 1600. The insulating layer 1602, the oxide semiconductor film 1606 provided over the base insulating layer 1602, and the oxide semiconductor film 1606 A pair of electrodes 1614 in contact with the oxide semiconductor film 1606, and a pair of electrodes 1614 in contact with the oxide semiconductor film 1606 a gate insulating film 1608 provided on the electrode 1614, and A gate electrode 1610 overlapping with the oxide semiconductor film 1606 and a gate insulating film 16 16. An interlayer insulating film 1616 is provided to cover the gate electrode 1610 and the insulating film 1616. Wiring 1618 is connected to a pair of electrodes 1614 through an opening provided in 616, and and a protective film 1620 provided to cover the insulating film 1616 and the wiring 1618.

[0274] The substrate 1600 is a glass substrate, the base insulating layer 1602 is a silicon oxide film, and the base insulating layer 1602 is an acid film. The compound semiconductor film 1606 is an In—Sn—Zn—O film, and the pair of electrodes 1614 is A tungsten film is used as the gate insulating film 1608, a silicon oxide film is used as the gate electrode 161 0 is a laminated structure of a tantalum nitride film and a tungsten film, and The layer structure is a silicon oxynitride film and a polyimide film, and the wiring 1618 is a titanium film. The protective film 1620 is a laminated structure in which an aluminum film and a titanium film are formed in this order. A polyethyleneimide film can be used.

[0275] In the transistor having the structure shown in FIG. 28A, the gate electrode 1610 and the pair of electrodes The overlapping width with the electrode 1614 is called Lov. The protrusion of the paired electrode 1614 is called dW.

[0276] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Example]

[0277] In this embodiment, an example of a semiconductor device having the above-described memory device will be described. By using a memory device according to one embodiment of the present invention, the device can be made more reliable and smaller. In particular, in the case of a portable semiconductor device, a memory device according to one embodiment of the present invention can be used. If miniaturization can be achieved by using this, the advantage will be improved usability for users. can be.

[0278] The storage device according to one aspect of the present invention is a device for use in a display device, a notebook personal computer, a recording medium, Image playback devices equipped with a DVD (Digital Versatile Digital Used in devices that have a display that can play back recording media such as ISC and display the images In addition, a semiconductor in which the memory device according to one embodiment of the present invention can be used As devices, mobile phones, portable game consoles, personal digital assistants, e-books, video cameras, digital cameras, still camera, goggle-type display (head-mounted display), navigation audio systems, audio playback devices (car audio, digital audio players, etc.), Copiers, fax machines, printers, multi-function printers, automated teller machines (AT) M), vending machines, etc. Specific examples of these semiconductor devices are shown in FIG.

[0279] FIG. 11A shows a portable game machine, which includes a housing 7031, a housing 7032, a display portion 7033, Display unit 7034, microphone 7035, speaker 7036, operation keys 7037, The storage device according to one embodiment of the present invention is a portable game console. It can be used in an integrated circuit for controlling the operation of a portable game machine. A highly reliable portable game console can be achieved by using a memory device according to one embodiment of the present invention in an integrated circuit. In this way, a compact portable game machine can be provided. The handheld game machine has two display units 7033 and 7034. The number of display units that the computer has is not limited to this.

[0280] FIG. 11B shows a mobile phone, which includes a housing 7041, a display portion 7042, an audio input portion 7043, It has an audio output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received in the sensor into an electrical signal, an external image can be captured. The memory device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. The memory device according to one embodiment of the present invention can be included in an integrated circuit for controlling the operation of a mobile phone. By using this, it is possible to provide a highly reliable and compact mobile phone.

[0281] FIG. 11C shows a portable information terminal, which includes a housing 7051, a display portion 7052, and operation keys 7053. The portable information terminal shown in FIG. 11C has a modem built in a housing 7051. The memory device according to one embodiment of the present invention may be an integrated circuit for controlling the operation of a mobile information terminal. The present invention can be applied to an integrated circuit for controlling the operation of a portable information terminal. By using the storage device according to the embodiment, a highly reliable portable information terminal and a compact portable information terminal can be provided. A terminal can be provided. [Explanation of symbols]

[0282] 100 Semiconductor substrate 101 Word line driving circuit 102a First bit line driving circuit 102b Second bit line driving circuit 102c Third bit line driving circuit 103a First cell array 103b Second cell array 103c Third cell array 104a First word line 104b Second word line 104c 3rd word line 105a 1st bit line 105b Second bit line 105c 3rd bit line 106a First memory cell 106b Second memory cell 106c Third memory cell 107a Transistor 107b Transistor 107c transistor 108a Capacitor element 108b Capacitive element 108c Capacitive element 110 control circuit 120 Drive Circuit 201 Cell Array 210 Drive circuit 260 transistors 262 Operational Amplifier 312 Transistor 314 Capacitor 322 transistor 324 Capacitor 332 transistors 334 Capacitor 342 transistors 344 Capacitive element 352 transistors 354 Capacitor 362 transistors 364 Capacitor 401 CPU 402 main memory 403 Clock Controller 404 Cache Controller 405 serial interface 406 I / O ports 407 terminal 408 Interface 409 Cache Memory 550 RF tags 551 Antenna Circuit 552 Integrated Circuits 553 Power supply circuit 554 Demodulation Circuit 555 Modulation Circuit 556 Regulator 557 Arithmetic circuit 558 Storage device 559 Boost Circuit 600 boards 606 Element isolation insulating layer 608 Gate insulating film 610 Gate electrode 616 Channel formation region 620 Impurity region 624 Metal compound area 626 Electrode 628 Insulating film 630a Source electrode or drain electrode 630b Source electrode or drain electrode 636a electrode 636b Electrode 636c electrode 640 insulating film 642a Source or drain electrode 642b Source or drain electrode 642c electrode 643a Oxide conductive film 643b Oxide conductive film 644 Oxide Semiconductor Film 646 Gate insulating film 648a Gate electrode 648b Conductive film 650 insulating film 652 insulating film 654a electrode 654b electrode 656 Wiring 659 Conductive Film 660 transistors 662 Transistor 664 Capacitor 670 memory cells 810 Write circuit 811 Readout circuit 812 decoder 813 Level Shifter 814 Selector 815 decoder 816 Level Shifter 817 buffers 1101 Circuit Board 1102 Undercoat insulation layer 1104 Protective insulating film 1106a High resistance area 1106b Low resistance region 1106 Oxide semiconductor film 1108 Gate insulating film 1110 gate electrode 1112 Sidewall insulating film 1114 Pair of electrodes 1116 Interlayer insulating film 1118 Wiring 1600 board 1602 Undercoat insulation layer 1606 Oxide semiconductor film 1608 Gate insulating film 1610 Gate electrode 1614 Pair of electrodes 1616 Interlayer insulating film 1618 Wiring 1620 Protective film 7031 Housing 7032 chassis 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Housing 7042 Display section 7043 Audio Input Unit 7044 Audio output section 7045 Operation Key 7046 Light receiving section 7051 Housing 7052 Display section 7053 Operation Key 8101 Base insulation layer 8102 buried insulating layer 8103a Semiconductor area 8103b Semiconductor field 8103c Semiconductor field 8104 Gate insulating film 8105 Gate 8106a Sidewall Insulator 8106b Sidewall insulator 8107 Insulators 8108a Source 8108b Drain

Claims

1. A first transistor having a first channel formation region containing silicon, A semiconductor device comprising: a second transistor provided above the first transistor and having a second channel-forming region containing an oxide semiconductor, A first conductive layer located above the first channel formation region and functioning as the gate electrode of the first transistor, A first insulating film having a region in contact with the upper surface of the first conductive layer, A second conductive layer having a region in contact with the upper surface of the first insulating film, A second insulating film having a region in contact with the upper surface of the second conductive layer, A third insulating film having a region in contact with the upper surface of the second insulating film, An oxide semiconductor film located above the third insulating film and having the second channel-forming region, A third conductive layer located above the third insulating film and functioning as one of the source and drain electrodes of the second transistor, A fourth conductive layer located above the third insulating film and functioning as the other of the source electrode and drain electrode of the second transistor, A fifth conductive layer is located above the third insulating film and is electrically connected to the second conductive layer, A sixth conductive layer having overlap with the third conductive layer and located above the second channel forming region, and having the same material as the gate electrode of the second transistor, A fourth insulating film above the third conductive layer, above the fourth conductive layer, above the fifth conductive layer and above the sixth conductive layer, It has a seventh conductive layer located above the fourth insulating film and electrically connected to the fifth conductive layer, The oxide semiconductor film overlaps with the first conductive layer, The seventh conductive layer overlaps with each of the first to sixth conductive layers. Semiconductor equipment.

2. A first transistor having a first channel formation region containing silicon, A semiconductor device comprising: a second transistor provided above the first transistor and having a second channel-forming region containing an oxide semiconductor, A first conductive layer located above the first channel formation region and functioning as the gate electrode of the first transistor, A first insulating film having a region in contact with the upper surface of the first conductive layer, A second conductive layer having a region in contact with the upper surface of the first insulating film, A second insulating film having a region in contact with the upper surface of the second conductive layer, A third insulating film having a region in contact with the upper surface of the second insulating film, An oxide semiconductor film located above the third insulating film and having the second channel-forming region, A third conductive layer located above the third insulating film and functioning as one of the source and drain electrodes of the second transistor, A fourth conductive layer located above the third insulating film and functioning as the other of the source electrode and drain electrode of the second transistor, A fifth conductive layer is located above the third insulating film and is electrically connected to the second conductive layer, A sixth conductive layer having overlap with the third conductive layer and located above the second channel forming region, and having the same material as the gate electrode of the second transistor, A fourth insulating film above the third conductive layer, above the fourth conductive layer, above the fifth conductive layer and above the sixth conductive layer, It has a seventh conductive layer located above the fourth insulating film and electrically connected to the fifth conductive layer, The oxide semiconductor film overlaps with the first conductive layer, The third conductive layer overlaps with the first conductive layer. The seventh conductive layer overlaps with each of the first to sixth conductive layers. Semiconductor equipment.

3. A first transistor having a first channel formation region containing silicon, A semiconductor device comprising: a second transistor provided above the first transistor and having a second channel-forming region containing an oxide semiconductor, A first conductive layer located above the first channel formation region and functioning as the gate electrode of the first transistor, A first insulating film having a region in contact with the upper surface of the first conductive layer, A second conductive layer having a region in contact with the upper surface of the first insulating film, A second insulating film having a region in contact with the upper surface of the second conductive layer, A third insulating film having a region in contact with the upper surface of the second insulating film, An oxide semiconductor film located above the third insulating film and having the second channel-forming region, A third conductive layer located above the third insulating film and functioning as one of the source and drain electrodes of the second transistor, A fourth conductive layer located above the third insulating film and functioning as the other of the source electrode and drain electrode of the second transistor, A fifth conductive layer is located above the third insulating film and is electrically connected to the second conductive layer, A sixth conductive layer having overlap with the third conductive layer and located above the second channel forming region, and having the same material as the gate electrode of the second transistor, A fourth insulating film above the third conductive layer, above the fourth conductive layer, above the fifth conductive layer and above the sixth conductive layer, It has a seventh conductive layer located above the fourth insulating film and electrically connected to the fifth conductive layer, The oxide semiconductor film overlaps with the first conductive layer, The seventh conductive layer overlaps with each of the first to sixth conductive layers. The channel length direction of the second transistor is the same as the channel length direction of the first transistor. Semiconductor equipment.

4. A first transistor having a first channel formation region containing silicon, A semiconductor device comprising: a second transistor provided above the first transistor and having a second channel-forming region containing an oxide semiconductor, A first conductive layer located above the first channel formation region and functioning as the gate electrode of the first transistor, A first insulating film having a region in contact with the upper surface of the first conductive layer, A second conductive layer having a region in contact with the upper surface of the first insulating film, A second insulating film having a region in contact with the upper surface of the second conductive layer, A third insulating film having a region in contact with the upper surface of the second insulating film, An oxide semiconductor film located above the third insulating film and having the second channel-forming region, A third conductive layer located above the third insulating film and functioning as one of the source and drain electrodes of the second transistor, A fourth conductive layer located above the third insulating film and functioning as the other of the source electrode and drain electrode of the second transistor, A fifth conductive layer is located above the third insulating film and is electrically connected to the second conductive layer, A sixth conductive layer having overlap with the third conductive layer and located above the second channel forming region, and having the same material as the gate electrode of the second transistor, A fourth insulating film above the third conductive layer, above the fourth conductive layer, above the fifth conductive layer and above the sixth conductive layer, It has a seventh conductive layer located above the fourth insulating film and electrically connected to the fifth conductive layer, The oxide semiconductor film overlaps with the first conductive layer, The third conductive layer overlaps with the first conductive layer. The seventh conductive layer overlaps with each of the first to sixth conductive layers. The channel length direction of the second transistor is the same as the channel length direction of the first transistor. Semiconductor equipment.

5. In any one of Claims 1 to 4, The oxide semiconductor film has In, Ga, and Zn. Semiconductor equipment.

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