Integrated circuit chip

Abstract

To address deficiencies associated with fabricating MEMS devices in various implementations.SOLUTION: Disclosed is a MEMS device formed using the materials of the BEOL of a CMOS process where post-processing of vHF and post baking were applied to form the MEMS device and where a total size of the MEMS device is between 50 μm and 150 μm. The MEMS device may be implemented as an inertial sensor among other applications.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This application relates generally to MEMS devices, and more particularly to techniques for manufacturing MEMS devices. [Background technology]

[0002] An integrated circuit is a semiconductor device that has a substrate of semiconductor material onto which a series of layers are deposited using photolithographic techniques. The layers are doped and polarized to create electrical elements (e.g., resistors, capacitors, or impedances) or electronic devices (e.g., diodes or transistors). Other layers are then deposited, which form the structure of interconnect layers required for electrical connections.

[0003] Microelectromechanical systems (MEMS) are miniature electromechanical devices fabricated using layer deposition techniques based on photolithography. MEMS can provide cavities or hollow spaces within them, which can be filled with liquids or gases. Conventional integrated circuits are completely solid devices, i.e., they do not have any kind of cavities. Cavities can be defined as cavities larger than the atomic or subatomic scale. MEMS can have moving elements within them. The moving elements can be connected by one of their ends to the rest of the MEMS structure, or they can be completely loose (i.e., not physically attached to its surroundings) within an at least partially closed housing (to prevent loose parts from "escaping" the MEMS). A chip can include a MEMS device and an integrated circuit (IC), where the IC can control the MEMS.

[0004] A major issue with today's MEMS devices is the need for custom manufacturing processes, which did not occur with solid-state electronics, which have converged towards a manufacturing standard called complementary metal-oxide-semiconductor (CMOS), with many variants, categorized primarily in terms of node, which is the smallest feature size that the process can resolve at the front-end-of-line (FEOL).

[0005] In practice, most MEMS ICs found on the market today consist of a package with two dice inside. One of these dice comes from a CMOS wafer, and the other comes from a MEMS wafer that is manufactured using a custom process. The dice inside the package are typically wire-bonded and packaged using a plastic package. For combo ICs that require several MEMS devices, the package may require more than two dice inside: one CMOS with control electronics and several MEMS dice, each built with a different manufacturing process.

[0006] This requirement for proprietary manufacturing processes for each MEMS manufacturer and each type of MEMS device poses several challenges: cost, size, time to market, performance, and mass production capabilities.Since 90% of the semiconductor industry consists of solid-state ICs, which do not involve MEMS and most of them are built with CMOS processing, most semiconductor companies use the so-called fabless model, whereby they outsource all production to large-scale CMOS foundries, which are companies that focus their business solely on manufacturing CMOS wafers.

[0007] This creates economies of scale, typically 100x or more globally compared to the largest MEMS foundries. Therefore, the cost of MEMS processing is significantly greater than the cost of CMOS wafers. However, the cost of MEMS wafers can be lower than the cost of CMOS wafers, especially when we consider lower nodes, due to the incremental complexity of the CMOS process compared to the MEMS process. However, for the same level of complexity, CMOS is much lower cost than any MEMS process. If MEMS could be built using the same CMOS process, the overall cost of the IC would be significantly reduced. This is because only one die is needed in the package, rather than two initially. Therefore, we eliminate the MEMS die, simplifying the packaging.

[0008] There is interest in reducing the size of ICs, especially in applications like smartphones, and even in wearables, especially earphones, where space is very constrained. The best packaging technology used today to minimize the overall size of ICs is wafer-level chip-scale packaging (WLCSP). This essentially involves depositing a sealing layer on the wafer to protect it, bumping the pads, and dicing the wafer with a prior selective backgrind. While there may be additional steps in the process, such as a redistribution layer (RDL), they are not essential or necessary for all implementations. However, if more than one die needs to be packaged, WLCSP cannot be used. If MEMS can be built within the same CMOS die, we can apply WLCSP to package it, which significantly reduces the overall package die and, if possible, allows various MEMS devices to be implemented in the same CMOS process. This allows manufacturers to build combo chips packaged with WLCSP, which will result in even greater shrinkage compared to the multi-die plastic packaging counterparts used today.

[0009] When a new type of MEMS device is developed, a new manufacturing process must be developed to build the new MEMS device. This is a complex project that typically takes several years and is expensive, because the volumes that this process must handle are very high because the MEMS market is generally consumer-oriented and high yields are expected from it to minimize costs. If the MEMS could be built using the same CMOS process, which already exists and is ready to be mass-produced at low cost, time to market would be minimized because only the device needs to be developed; there is no need to spend the time (and money) to develop a custom manufacturing process.

[0010] Due to the different economies of scale that exist in CMOS versus MEMS processes, the equipment used in CMOS processes is state-of-the-art, while in MEMS processes, it is usually legacy equipment, reducing the cost of setting up a MEMS process. This means that the minimum feature size, also known as the critical dimension, is usually smaller with CMOS processes than with MEMS processes. Therefore, if MEMS can be built using CMOS manufacturing processes, they will be able to produce MEMS devices with smaller feature sizes. This helps improve the performance of the device because it is possible to build softer springs / membranes and smaller gaps.

[0011] Additionally, building MEMS using CMOS processes minimizes the parasitic capacitance that appears when connecting the MEMS to the electronic interface (usually sense / drive) circuitry in the CMOS die. This is typically done via wire bonds inside the plastic package, which typically adds capacitance on the order of 1 pF to 10 pF. With MEMS built within the same CMOS process, this parasitic capacitance resulting from connecting the MEMS to the electronics is typically reduced to 1 fF to 10 fF—a reduction of 100x to 1000x. Because parasitic capacitance masks the capacitance of the MEMS device and therefore reduces its performance, reducing it can improve the performance of the MEMS IC. Improved performance can mean increasing the sensor's sensitivity, reducing its power consumption, or a combination of the two.

[0012] Furthermore, as already mentioned, mainstream CMOS foundries have mass production capabilities that are over 100 times greater than the major MEMS foundries. Therefore, if we can build MEMS devices using CMOS processing, we will benefit from this mass production capability. This will enable us to address new markets, such as the Internet of Things (IoT), which would otherwise be impossible. Today, it is difficult for MEMS providers to serve existing MEMS markets due to their limited mass production capabilities. The IoT is predicted to expand the current MEMS market volume by over 100 times. This is achievable today only if MEMS devices are built using CMOS mainstream foundries.

[0013] Some companies use a monolithic solution to build MEMS together with CMOS, which leaves a single die containing both CMOS and MEMS at the end of the manufacturing process. Two options for building this are to bond the MEMS and CMOS wafers together after they are separately manufactured, or to build the MEMS wafer on a finished CMOS wafer instead of starting with a blanket silicon wafer. In both cases, a custom MEMS manufacturing process is required. These monolithic solutions reduce the IC dimensions because they eliminate the need for wire bonding and allow the use of WLCSP with them. They also slightly increase performance due to the lower parasitic interconnect capacitance between the MEMS and CMOS, which typically drops to 100 fF to 1 pF.

[0014] However, the previous approach still requires a fully custom MEMS process, which still presents challenges with cost, time to market, and mass production capabilities. Also, while dimensions are shrinking and performance is increasing, it would still be much better if we could build MEMS using a CMOS process. From a dimension perspective, the profile is always larger because we are essentially stacking two dies one on top of the other. But with CMOS, it's one die, which can be back-ground. In terms of performance, this reduces parasitic capacitance by 10x compared to a conventional two-die packaging solution, but by building MEMS devices using a CMOS process, we would get a 100x reduction.

[0015] And ultimately, these monolithic solutions only work if we have a single MEMS device or sensor. If we need a combo chip that combines different types of sensors, it's no longer applicable. But by building all these MEMS devices using a CMOS process, we continue to have a single die solution that can be back-ground. So, as we move to combo chips, building MEMS with a CMOS process offers significant cost and size advantages.

[0016] The cost and size reduction is due in part to the elimination of many bond pads, which are no longer necessary, even more so when we move to combo chips. Given the known benefits if we could build MEMS devices using CMOS fabrication processes, several solutions have been proposed. The first solution proposes modifications to the CMOS process that add several steps to build the MEMS device. Depending on whether these are performed at the beginning, middle, or end of the CMOS process, the solutions have been called pre-processing, mid-processing, or post-processing.

[0017] Modifications to the CMOS process were required because, when MEMS devices need to perform mechanical movement, they require some free space inside the IC to perform this movement, and these free spaces are something that CMOS cannot create. Another reason for the modification was to add layers of different materials or layers with different mechanical properties not found in the CMOS process.

[0018] Given the prohibitive cost of implementing modern CMOS processes in mainstream foundries and the cost of keeping them stable, in order to continue producing very high volumes while maintaining very high yields, front-end and mid-end process modifications have been abandoned, and the only option remaining is post-CMOS processing to implement MEMS.

[0019] Post-CMOS processing means that after the fabrication of the CMOS wafers is completed, they undergo several additional fabrication steps in which the MEMS are implemented. However, unlike the monolithic approach described above, this involves wafer bonding or building the MEMS onto the CMOS wafer; in this case, we simply create the free space necessary to allow for the mechanical movement of the MEMS. The MEMS are then built using materials present inside the CMOS wafer.

[0020] One possibility would be to implement the MEMS using polysilicon, but this requires a deep etch to get there, either from the top of the wafer, thus etching through all the back end of the line (BEOL) first, or from the back, requiring a deep etch through the silicon substrate, which requires a complex process that is not cost-effective.

[0021] The only solution then remains to package the MEMS using materials present at the back-end of the CMOS, which is on top of the CMOS die and therefore requires minimal post-processing and therefore minimal cost.

[0022] Different solutions have been proposed, for example using plasma and / or wet etching in combination with HF and other chemicals, but these processes, especially those involving wet etching, are difficult to implement in mass production with high yields.

[0023] A previously proposed simple post-processing approach is to use a single vapor HF (vHF) maskless post-processing step. vHF etches away silicon oxide present between metal layers in the back-end of the electrode, leaving all metal behind. This was proposed by Baolab. Due to its simplicity, it is the lowest-cost CMOS post-processing approach. Furthermore, it can be implemented in the same CMOS foundry or packaging or assembly house.

[0024] In this approach, MEMS devices are constructed using metal layers, typically Al or AlCu and W, but other layers such as Cu are also possible. With proper design, it is possible to confine oxides inside the metal casing. Other materials can be used, but they must reside in the CMOS BEOL. Most previous approaches use special packages, such as laminate packages, e.g., LGAs, to protect the MEMS. This increases cost and size, thereby minimizing or eliminating the size and cost advantages we would otherwise gain when building MEMS using CMOS processes.

[0025] Baolab proposed using a top metal layer to protect the MEMS while having a small hole that would allow vHF to enter inside the MEMS cavity. A second set of post-processing steps is then applied, consisting of Al sputtering and patterning, to properly seal the MEMS device. This typically adds 10% cost to the CMOS process. This simplifies the packaging requirements; it is no longer necessary to use laminates or other special packages. Instead, standard packaging technologies such as QFN can be used. This reduces the cost and size of the final IC.

[0026] In addition to the top metal layer, a bottom metal layer was used to complete the metal cavity where the MEMS device will be placed. This was done to limit vHF etching to the bottom, given that most CMOS processes have doped silicon oxide under the bottom metal layer, M1. Doped silicon oxide reacts very aggressively to vHF, rapidly increasing the etch rate and leaving a very troublesome residue that is difficult to remove. This makes the design portable to most CMOS processes; otherwise, it would only be applicable to specialized processes that do not have doped silicon oxide under the bottom metal layer in the back-end of the electrode.

[0027] Baolab's solution, like other solutions that use back-end materials to package MEMS devices, surrounds the MEMS device with metal walls that define the MEMS cavity within the ASIC die. The electronics are then placed around it. The implementation of these metal walls is made with a stack of metal layers (usually made of aluminum) and vias (usually made of tungsten). However, as we move down the CMOS node to 0.18 μm processes and below, the materials can be different, primarily copper. As a rule, these are not straight vertical walls, because DRC rules require that the metal layers extend beyond the edges of the vias. However, some exceptions can be made to this if we are interested in increasing the lateral area exposed to the walls, for example in the case of in-plane capacitive sensors. This then becomes a DRV that the foundry must accept.

[0028] Using Baolab's solution, the vertical metal wall essentially connects the top and bottom metal planes, thereby electrically shorting all MEMS cavities. Normally, we wouldn't be interested in this, or at least not everywhere in all cavities. To solve this problem, Baolab uses vertical interleaved anchor structures. These structures allow the vHF to move up and down through the silicon oxide layer until it is depleted, leaving the silicon oxide unetched. In this way, we can obtain mechanically consistent walls without electrically shorting the top and bottom metal plates.

[0029] One reason this is particularly effective is that silicon oxide layers typically deposited between metal layers in the back-end of a CMOS process exist on two distinct sublayers, each with a different oxide density. Therefore, one of these layers is etched away more slowly by vHF than the other. Etching silicon oxide vertically with vHF is thus more difficult (i.e., it takes longer) than etching horizontally because the etch propagates faster along one of the silicon oxide sublayers. With these anchor structures, we force the vHF to etch all of the slower-etching sublayers without rapidly propagating through the faster sublayers. These interleaved anchors can also be used to add columns or pillars at various locations on the MEMS to provide greater consistency to the top metal surface. This is particularly important in terms of supporting subsequent sealing, typically with Al sputtering. This prevents the top metal surface from bending, which could ultimately destroy or render the MEMS device unusable.

[0030] The main problem with these anchor walls is that although they provide mechanical robustness while keeping the top and bottom metal surfaces electrically disconnected, the capacitance between them is very large because large surfaces are placed close together inside the interleaved anchor structure, one connected to the top plate and the other to the bottom plate, and to make matters worse, this critical area is filled with silicon oxide.

[0031] Another problem related to the previous one is that there is a significant tradeoff between this parasitic capacitance between the top and bottom metal plates and production yield and reliability. To minimize this parasitic capacitance, we can minimize the length of the anchor structure, reduce the number of fingers and / or their height, and / or increase the etching time. Thus, if we minimize this parasitic capacitance, we have a small anchor structure with a minimal amount of silicon oxide remaining inside it after vHF etching. However, this is a very weak structure and is prone to mechanical failure due to mechanical shock, vibration, or simply when sealing or packaging the device. It also results in low yield. Even a slight overetch can completely remove the silicon oxide inside the anchor structure, resulting in the collapse of the top and bottom portions and making the device completely unusable. In manufacturing, we need to avoid this requirement for a critical vHF etch, as it always leads to low yield. This is because the etch rate and silicon oxide etched inside the MEMS cavity depend not only on the vHF machine and recipe applied, but also on the CMOS process. While we can have tight control over the vHF machine and its recipe, we cannot control the CMOS process, which typically has tolerances on the order of 30%.

[0032] In addition to potentially requiring all the metal layers to implement the MEMS device, it requires a special packaging process, requires a specific CMOS process that does not have doped silicon oxide under the bottom metal layer, and introduces significant parasitic capacitance. Two key issues with any solution that uses CMOS back-end of line (BEOL) materials to implement MEMS are yield and reliability. These issues become even more critical when using the Baolab approach for top and bottom metal layers. However, if we do not use them, the process becomes more complex and expensive, eliminating the cost benefits, as well as the benefits in volume production, time to market, and even performance.

[0033] One major issue we see when using back-of-the-line metals in CMOS processes to implement MEMS devices is vertical stress gradients, which are typically minimized in custom MEMS fabrication processes. However, in CMOS, these metal lines are not intended to implement mechanical structures but are simply electrical connections surrounded by silicon oxide in solid-state ICs, so residual stress is less of a concern and generally has high values. In addition to high residual stress, we generally see high vertical stress gradients. This generally results in upward metal bending or curling, but depending on the layer, it can also be downward, especially on the upper layers. This bending is a major concern when we use top and bottom metal planes. Therefore, the available vertical gap spacing above and below the device is minimal, allowing easy contact. If a MEMS device makes contact with the top or bottom metal planes, it becomes unusable. This leads to very poor yield and reliability.

[0034] One possibility to alleviate this problem somewhat would be to increase the vertical gap spacing and reduce the number of metal layers used in the MEMS device itself. However, this reduces performance in the out-of-plane direction due to the larger gap, which reduces the relative capacitance variation of a given sensor point for the same displacement. Also, in the case of inertial sensors, we are forced to use smaller proof masses and cannot use all available metal layers, further reducing performance. Furthermore, reducing the number of metal layers used to construct the moving parts of a device, such as the proof mass in the case of inertial sensors, further increases their curvature, as discussed below. Therefore, it is necessary to minimize the curvature height of the MEMS device. This is defined as the maximum vertical displacement of any metal layer along the entire MEMS device or its specific element, and therefore the maximum vertical displacement in the out-of-plane direction.

[0035] One known solution to this problem is to stack two or more metal layers. In this way, we increase the radius of curvature of the resulting metal structure, thereby reducing the total curvature height. However, while this is a good solution for designing certain parts of MEMS devices, such as the proof mass of an inertial sensor, we want it to be as large as possible to improve the sensor's sensitivity. On the other hand, for other components, such as springs, this leads to very high stiffness, which significantly reduces sensitivity. In fact, stiffness is inversely proportional to the cube of the length versus thickness, so increasing the thickness quickly leads to very stiff springs. This means that the sensor has very low sensitivity and the drive voltage for the actuator is high. Furthermore, stacking multiple layers is limited by the number of metal layers in the process, and if it is necessary to modify or use a CMOS process with a higher number of metal layers in the back-end assembly, this quickly increases the cost.

[0036] In summary, there is a need to find a suitable design to implement MEMS devices by reusing the BEOL materials present in standard CMOS processes and using vHF to etch away some of the silicon oxide in the MEMS cavities, which can then be packaged by WLCSP, and these devices have very high yield, reliability, and performance.

[0037] Yet another problem with using a post-CMOS vHF etch post-processing step is that the SiN passivation layer that is deposited and patterned on top of the CMOS wafer is partially etched away by vHF. This means that in practice, unless a very short vHF etch step is performed, the SiN passivation layer is largely or completely etched away. This leaves troublesome residue on the wafer and also exposes all the wafer with ASIC areas whose silicon oxide should not be etched away.

[0038] A known solution to prevent this is to increase the silicon content of the passivation, which is commonly measured by the refractive index, or RI, of the layer. While this is not technically complicated to implement, it requires process tweaks that are very challenging to accommodate in large mainstream foundries. Ultimately, this requirement means that we can no longer use full standard CMOS processes, and therefore we lose some of the benefits of low cost, fast time to market, and high-volume manufacturing capabilities. Summary of the Invention [Problem to be solved by the invention]

[0039] This application addresses deficiencies associated with the manufacture of MEMS devices in various implementations. [Means for solving the problem]

[0040] In various aspects, systems, devices, and methods result from or use vHF etching to etch away portions of silicon oxide in the back-end of a CMOS process, thereby freeing up material present in the back-end of the process that constitutes the MEMS device. The inventive approach uses bottom and top metal surfaces with arrays of small holes that allow vHF to enter the interior of the MEMS cavity. A key inventive concept is to limit the overall MEMS size in the layout to 50 μm to 150 μm, preferably less than 100 μm. For a given radius of curvature of a MEMS device or element, the total radius of curvature depends on the horizontal dimension. Therefore, if the device is small enough, the curvature height is limited despite the large vertical stress gradient.

[0041] The second original concept is the spring design. To have good performance in such a small device, we need small and soft springs while also maintaining a small curvature height. These seem like contradictory requirements. Short springs mean that they are very stiff, which reduces the sensitivity (performance) of the MEMS sensor. To have soft springs, we need to minimize their thickness, which means using minimal or no metal stack at all. However, this increases the normal stress gradient, which rapidly increases the total curvature height.

[0042] The preferred inventive solution to the spring design problem is to use a set of at least three springs rather than a single one, evenly distributed around the device and rotating about the central axis of the device, so that symmetry prevents the MEMS device from tilting after being released by vHF etching.

[0043] In the case of an inertial sensor, a MEMS device may include a central proof mass made of several metal stacks, making it very flat compared to the springs surrounding it. This proof mass may be larger than the springs to provide sufficient sensitivity. If one or more springs holding it are bent, the proof mass tilts, resulting in a large curvature height, even though the proof mass itself is relatively flat. However, if there are at least three evenly spaced springs around it, the proof mass will experience a small vertical displacement due to the curvature of the springs, but it will be flat and therefore not contribute to the total vertical height due to its large size.

[0044] In a specific implementation, the central mass is circular, and the springs around it have a spiral shape and are made of a single metal layer or a stackup of only two metal layers. When using a stackup of two metal layers, we connect them with a via layer between them. In a preferred implementation, this via layer has the same linear or spiral shape as the metal layers above and below, but is generally slightly tapered laterally to satisfy DRC rules in at least one horizontal direction at each point. Throughout this application, when we say we use a stackup of a particular set of metal layers, it is understood that we use a via layer between them to maintain their connection. The use of circular and rounded shapes for the proof mass, springs, and generally for all or as many components of the MEMS device as possible avoids high mechanical stresses that would otherwise accumulate at the linear angles of the device geometry. These rounded shapes help balance the spring stresses and provide the horizontal tilt required for the central mass when we use an array of at least three evenly distributed springs around it.

[0045] One embodiment includes a MEMS device formed using back-end of line (BEOL) materials in a CMOS process, where vHF post-processing and post-backing are applied to form the MEMS device. The total dimension of the MEMS device is between 50 μm and 150 μm. The total dimension of the MEMS device can be less than 100 μm. In some implementations, the total dimension of the MEMS device is 50 μm or less. The MEMS device can include a set of at least three springs evenly distributed around the MEMS device and rotated around a central axis of the MEMS device or its movable part. The device can be circular in shape, and the springs can have a helical shape. The springs can be composed of a single metal layer or a stackup of at least two metal layers. The MEMS device can include an inertial sensor.

[0046] The MEMS device can include a proof mass. The proof mass can be formed or fabricated by a stackup of four metal layers and a spring, where the spring is either connected to the top metal layer of the proof mass that forms the stackup or to the top two metal layers of the stackup. The spring can be connected to an outer ring such that a portion of the spring remains embedded in the silicon oxide on its outer edge after vHF etching.

[0047] In some implementations, the MEMS device has a top metal surface and a bottom metal surface that is smaller than the top metal surface. The outer ring width of the bottom metal surface can be equal to or less than 10% to 50% of the outer ring width of the top metal surface. The outer ring width of the bottom metal surface can be approximately 30% of the outer ring width of the top metal surface. The MEMS device can include at least one pad. The at least one pad includes a top metal layer disposed such that it extends laterally 15 μm to 25 μm in all directions beyond the vertically aligned passivation openings. The at least one pad can extend laterally 20 μm in all directions beyond the vertically aligned passivation openings. The MEMS device can be formed in a MEMS cavity that does not include a metal fill structure. In some implementations, the MEMS device is configured with more capacitance, for example, to enable measurement of MEMS capacitance using more conventional sensing circuitry. The MEMS device can be constructed with an array of MEMS devices electrically connected in parallel. Each of these MEMS devices has its own passivation opening, which is completely cut apart except for the lines / tracks that make the electrical connections.

[0048] In another aspect, the MEMS device includes a set of at least three springs evenly distributed around the MEMS device and rotated around a central axis of the MEMS device. The device shape can be circular and the springs can be helical. The springs can be made from a single metal layer or a stackup of at least two metal layers. The MEMS device can include an inertial sensor. The MEMS device can include a proof mass. The proof mass is made from a stackup of four metal layers and the springs. The springs are connected to the top metal layer of the proof mass forming the stackup, or to the two top metal layers of the stackup.

[0049] In a further aspect, the MEMS device includes a spring having a ratio of maximum displacement to spring length of at least 1%. The MEMS device can include a proof mass. The proof mass is made of a stackup of four metal layers and a spring. The spring is connected to the top metal layer of the proof mass forming the stackup, or to the two top metal layers of the stackup. The spring can be connected to an outer ring such that a portion of the spring remains embedded in the silicon oxide on its outer edge after vHF etching. The MEMS device can include top and bottom metal surfaces, where the outer ring width of the bottom metal surface is equal to or less than 10% to 50% of the outer ring width of the top metal surface.

[0050] Yet another aspect is a method for fabricating a MEMS device using back-end of line (BEOL) materials in a CMOS process, including applying a vHF post-treatment and post-backing to form a MEMS device, wherein the MEMS device has a total dimension of 50 μm to 150 μm. The total dimension of the MEMS device can be less than 100 μm. The method can further include forming a set of at least three springs evenly distributed around the MEMS device and rotated about a central axis of the MEMS device.

[0051] The method can include forming a device shape that is circular and forming the spring in a helical shape. The method can include forming the spring from a single metal layer or a stackup of at least two metal layers. The method can form a MEMS device that includes an inertial sensor.

[0052] The method can include forming a proof mass, where the proof mass is made of a stackup of four metal layers and a spring, where the spring is connected to the top metal layer of the proof mass forming the stackup or to the top two metal layers of the stackup. The method can include connecting the spring to an outer ring such that a portion of the spring remains embedded in silicon oxide on its outer edge after vHF etching.

[0053] The method may include forming a MEMS device having a top metal surface and a bottom metal surface that is smaller than the top metal surface. The method may include forming an outer ring width of the bottom metal surface that is equal to or less than 10% to 50% of the outer ring width of the top metal surface. The method may include forming the outer ring width of the bottom metal surface to be approximately 30% of the outer ring width of the top metal surface. The method may include forming the MEMS device in a MEMS cavity that does not include a metal fill structure.

[0054] In a further aspect, a method for fabricating a MEMS device includes forming a set of at least three springs evenly distributed around the MEMS device or a movable portion thereof and rotated about a central axis of the MEMS device or a movable portion thereof. The method may include forming a shape of the MEMS device that is circular and forming the springs to have a helical shape. The method may include forming the springs from a single metal layer or a stackup of at least two metal layers. The method may include forming the MEMS device to include an inertial sensor. The method may include forming a proof mass, where the proof mass is made from a stack of four metal layers and springs, and the springs are connected to the top metal layer of the proof mass forming the stackup or to the two top metal layers of the stackup.

[0055] In yet another aspect, a method for fabricating a MEMS device includes forming a spring having a ratio of maximum displacement to spring length of at least 1%. The method may include forming a proof mass having a four-metal layer stackup and a spring, where the spring is connected to the top metal layer of the proof mass forming the stackup or to the top two metal layers of the stackup. The method may include connecting the spring to an outer ring such that a portion of the spring remains embedded in silicon oxide on its outer edge after vHF etching. The method may include forming a width of the outer ring of the bottom metal surface that is equal to or less than 10% to 50% of the width of the outer ring of the top metal surface.

[0056] In a further aspect, a smartphone, a wearable, an earphone, or an Internet of Things (IoT) device includes a MEMS device according to the above-described aspect.

[0057] All of the inventive concepts described in this section and throughout this application apply primarily to CMOS, but may also be applicable to the BEOL of any other solid-state semiconductor process, such as BiCMOS, GaAs, SiGe, GaN, SOI, etc.

[0058] Any two or more of the features described in this specification, including in this Summary section, may be combined to form implementations not specifically described in this specification.

[0059] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0060] [Figure 1] FIG. 1 shows a proof mass of a MEMS device having three springs connected to and equally spaced around its periphery. [Figure 2] FIG. 2 is an exploded view of the metal and via layers of a MEMS device without showing the SiO2, passivation, and substrate. [Figure 3] FIG. 3 is an enlarged view of the M4 layer of the MEMS device of FIG. [Figure 4] FIG. 4 is an enlarged view of the M5 layer of the MEMS device of FIG. [Figure 5] FIG. 5 is an enlarged view of the V4 layer of the MEMS device of FIG. [Figure 6] FIG. 6 is a three-dimensional view of the MEMS device of FIG. [Figure 7] FIG. 7 shows a side view of the metal layer of the MEMS device of FIG. [Figure 8] FIG. 8 is a cross-sectional schematic view of the MEMS device of FIGS. [Figure 9] FIG. 9 is an exploded view of the metal and via layers of a MEMS device including side electrodes. DETAILED DESCRIPTION OF THE INVENTION

[0061] Like reference numbers in different figures indicate like elements.

[0062] This application addresses, in various aspects, deficiencies associated with the manufacture and / or construction of MEMS devices.

[0063] In various aspects, systems, devices, and methods rely on or utilize vHF etching to etch away portions of silicon oxide in the back-end of an interconnect (BEOL) CMOS process, thereby freeing up material present in the back-end that constitutes a MEMS device. The inventive approach utilizes bottom and top metal surfaces with arrays of small holes to allow vHF to penetrate the interior of the MEMS cavity. A key inventive concept is to limit the overall MEMS size on the layout to between 50 μm and 150 μm, preferably less than 100 μm. For a given radius of curvature of a MEMS device or element, the total height of the curvature depends on the horizontal size. Therefore, if the device is small enough, the height of the curvature is limited despite a large vertical stress gradient.

[0064] The second original concept is the spring design. For such a small device to have good performance, it needs small and soft springs while maintaining a small curvature height. These seem like contradictory requirements: a short spring means the spring is very stiff, which reduces the sensitivity (performance) of the MEMS sensor. To have a soft spring, its thickness needs to be minimized, which means minimizing the metal stack or using no metal stack at all. However, this increases the normal stress gradient, which rapidly increases the total curvature height.

[0065] The preferred inventive solution to the spring design problem is to use a set of at least three springs, rather than just one, evenly distributed around the device and rotating about the central axis of the device, so that symmetry prevents the MEMS device from tilting after being released by vHF etching.

[0066] In the case of an inertial sensor, the MEMS device includes a central proof mass made of several metal stacks, making it very flat compared to the surrounding springs. This proof mass may also be larger than the springs to provide sufficient sensitivity. If one or more springs holding it bend, when the proof mass is tilted, it will have a large curvature height, even though the proof mass itself is relatively flat. However, if the springs are evenly distributed around its periphery, and there are at least three springs, the proof mass will undergo a small vertical displacement due to the curvature of the springs, but because it is flat, it will not contribute to the total vertical height due to its large size.

[0067] FIG. 1 shows a central and / or proof mass 100 of a MEMS device having three evenly spaced springs 102, 104, and 106 fabricated and / or connected around its circumference. The proof mass 100 also includes an array of etched holes 108. In some implementations, the central mass 100 is circular, and the surrounding springs 102, 104, and 106 are spiral-shaped and fabricated from only one metal layer, or only two stackups, or more than two layers. The use of circular and rounded shapes for the proof mass 100, the springs 102, 104, and 106, and generally for all or as many components of the MEMS device as possible, avoids high mechanical stresses that would otherwise accumulate at the straight corners of the device geometry. These rounded shapes, in turn, help balance the stresses on the springs 102, 104, and 106, which leads to horizontal tilt. As we use an array of at least three springs 102, 104 and 106 evenly distributed around the central mass 100, we require a horizontal tilt in the central mass 100.

[0068] The number of springs can be increased, so we could use four or more, which would further assist in achieving horizontal tilt of the central proof mass 100, but in this particular implementation there are only three springs because otherwise the overall stiffness of the MEMS device would increase in proportion to the number of springs, thereby reducing its sensitivity.

[0069] Throughout this application, we use the term "inertial sensor" to refer to a variety of devices that sense acceleration. This may include, at least, accelerometers, motion detectors, and bone conduction sensors. While the physical principles of their operation are the same, their differences lie in the frequencies they detect; hence, their bandwidth, whether they need to detect direct current (DC), and their resolution and / or sensitivity requirements.

[0070] Another implementation could use linear pairs of springs located on either side of the proof mass 100, with each pair of springs collinear. This solution works because the residual stress in metal lines is known to be tensile in most CMOS processes, although the top metal layer may be omitted. In this way, the curvature height is minimized. However, this solution results in a relatively high stiffness, which is also highly dependent on the device temperature. Therefore, this is a solution that may be applicable to some MEMS devices, especially when a high mechanical resonant frequency is required and when the temperature dependence of the spring stiffness is not important.

[0071] If the proof mass (such as in the case of an inertial sensor) or the central portion of the MEMS device attached to the spring is thicker than the spring and therefore made from a larger stackup of metal layers, a preferred practice is for the spring to be made using the upper metal layer when we connect the central portion of the MEMS or proof mass to the upper metal surface. This minimizes the parasitic capacitance of the spring and the supporting outer ring to the lower metal plate.

[0072] Figure 2 shows an exploded view of the metal and via layers of MEMS device 200, without showing the SiO2, passivation, and substrate. Figure 2 illustrates an out-of-plane inertial sensor. It is constructed using a six-metal BEOL CMOS process. The metal layers are numbered M1 (bottom) through M6 (top). There are five via layers numbered V1 (between M1 and M2) through V5 (between M5 and M6), with V1 not used in this particular design. The proof mass has a circular structure with three helical springs evenly spaced around it. The diameter of the proof mass and springs is 50 μm. The proof mass consists of a stack of metal layers M2 through M5, with the springs stacking metal layers M4 and M5. The proof mass has concentric rings, terminated by etched holes that run vertically across it, and consists of via layers V2 through V4.

[0073] The top metal surface has the same diameter and a 20 μm wide outer ring around it, which corresponds to a 90 μm diameter circle. There is an array of 0.8 μm holes with a spacing of about 5 μm between the centers of every two holes in both the X and Y directions. The springs have a 20 μm wide peripheral ring around them, which is constructed on the same layers M4 and M5. There is an array of concentric vias connecting these rings to the top metal surface above them; i.e., they are implemented on layers V4 and V5.

[0074] There is a circular bottom metal surface made of M1, which also has a 50 μm diameter and a 6 μm wide outer ring. It is therefore smaller than the top metal surface and the outer ring on the top layer for spring support. The inner and outer circles together correspond to a circle with a diameter of 62 μm. The difference between the inner and outer rings arises from the fact that after vHF etching, the outer ring is only partially etched away, leaving its edges buried (and exposed) in the silicon oxide. The top passivation is opened by a 50 μm circular feature above the MEMS device.

[0075] The MEMS device 200 includes an M6 layer 202, a V5 layer 204, an M5 layer 206, a V4 layer 208, an M4 layer 210, a V3 layer 212, an M3 layer 214, a V2 layer 216, an M2 layer 218, and an M1 layer 220. The M6 ​​layer 202 includes a top plate 222 having an array of etched holes and connections to an ASIC. The V5 layer 204 includes an array of concentric via rings 224 extending onto the outer metal. The M5 layer 206 includes a proof mass top lid 226 having an array of etched holes. The layer 206 also includes a portion of a helical spring 228 and an outer metal ring 230. The V4 layer 208 includes an array 232 of concentric via rings extending over the outer metal, a portion of the spiral spring 228 extending over the V4 layer 208, and an array 236 of concentric via rings extending over the proof mass, stopping at the etched hole locations, surrounding the etched hole locations with square rings. The M4 layer 210 includes a proof mass plane 238 with an etched hole array, a portion of the spiral spring 228, and a portion of the outer metal ring 230. The V3 layer 212 includes an array of concentric via rings 244 extending over the proof mass, stopping at the etched hole locations, surrounding the etched hole locations with square rings. The M3 layer 214 includes a proof mass metal plane 246 with an etched hole array. The V2 layer 216 includes an array 248 of concentric via rings extending over the proof mass, stopping at the etched hole locations, surrounding the etched hole locations with square rings. The M2 layer 218 includes a proof mass metal bottom cap 250 that contains an array of etched holes. The M1 layer 220 includes a bottom metal surface 252 that contains connections to the ASIC.

[0076] A preferred implementation for an accelerometer using a six metal layer process with the M1 layer 220 being the bottom layer and the M6 ​​layer 202 being the top layer is as follows: The M1 layer 220 is used to implement the bottom surface, and the M6 ​​layer 202 is used to implement the top metal surface, which is shorted to the proof mass and springs. The proof mass is implemented using the stackup from the M2 layer 218 through the M5 layer 206. Also, the springs 228 are implemented using either the M5 layer 206 alone or the stackup of the M4 layer 210 and the M5 layer 206.

[0077] When we set the total diameter of the proof mass and spring, there is an optimum for the length or maximum angle that the spring will rotate. Longer springs (longer total angle) mean they will be softer, but the proof mass will be smaller. Shorter springs allow for a larger proof mass, but the springs will be stiffer. Thus, there is always an optimum, which depends on the specific design and process characteristics. However, in general, it is difficult to build reliable devices with high yields with springs that have angles greater than 360°. That is, it is preferable that each individual spring not complete a rotation around the circular proof mass.

[0078] Another parameter that affects the yield, performance, and reliability of a design is the spacing around the spring. That is, the horizontal spacing or gap that exists at each point on the spring without any other spring, proof mass, anchor, or part of the device (except at the spring's edges, where these start and eventually merge with the outer ring or anchor / wall and proof mass or other MEMS components). This obviously needs to be at least equal to the minimum spacing set by the process design rule check (DRC). However, in practice, we set it to a higher value, between 2x and 10x this minimum spacing set by the process DRC. A preferred value is 5x. For example, in an 180 nm process with a minimum metal-to-metal gap DRC of 300 nm, we preferably set this horizontal spacing for the springs to 1.5 μm. The tradeoff here is that with a very large spacing, we degrade sensitivity and / or performance because we reduce the proof mass area and therefore the mass for the same spring length (thus achieving a given softness / stiffness in the spring). However, this narrow horizontal spacing between the springs results in poor yield and reliability.

[0079] Another important aspect of springs, which is especially important when they are soft, such as when using a set of three or more helical springs evenly distributed around a central proof mass, is to make them short enough compared to the displacement (both vertically, hence out-of-plane, and horizontally, hence in-plane). Because we have small proof masses and need very soft springs to achieve sufficient sensitivity, this is in principle prone to stiction problems, which leads to poor reliability of MEMS devices.

[0080] Figure 3 is a close-up view 300 of the M4 layer 210 of the MEMS device of Figure 2. The M4 layer 210 includes a 50 μm circular metal surface 302 inside the proof mass, a helical spring 306, an outer 20 μm wide ring 304 that is partially embedded in silicon oxide at its outer portion after vHF etching to support the spring and therefore the proof mass, and an array of etched holes 308 through the proof mass.

[0081] Figure 4 is a close-up view 400 of the M5 layer 206 of the MEMS device of Figure 2. The M5 layer 400 includes a proof mass top lid 402 with an array of etched holes, a helical spring 404, and an outer metal ring 406.

[0082] Figure 5 is a close-up view 500 of the V4 layer 208 of the MEMS device of Figure 2. The V4 layer 500 includes an array of concentric via rings 502 that extend over the proof mass, stopping at each etch hole 504 and surrounding each hole 504 with a square ring. The layer 500 also includes an array of concentric via rings 508 that extend over the outer metal.

[0083] Figure 6 is an unexploded 3D view 600 of a metal layer (thus not showing the remaining silicon oxide, passivation, and substrate) such as M6 layer 202 including etch holes of the MEMS device of Figure 2. Layer 202 includes an array of etch holes 602, an outer ring 604, and connections 606 to the ASIC (upper electrode and proof mass). M1 layer 220 includes bottom electrode connections 608 to the ASIC.

[0084] Figure 7 shows a side view 700 of metal layers M1-M6 and via layers V2-V5 (since V1 is empty) of the MEMS device of Figure 2. Side view 700 includes connections 702 to the ASIC (upper electrode and proof mass), a top metal plane 704, an outer ring 706, a proof mass 708, a bottom metal plane 710, and a lower electrode connection 712 to the ASIC.

[0085] Figure 8 is a cross-sectional schematic diagram 800 of the MEMS device of Figures 2, 6, and 7. Diagram 800 shows a passivation layer 802, passivation openings 804, springs 806, an etch hole array 808, an outer metal ring 810, an M6 layer 812, a V5 layer 814, an M5 layer 816, a V4 layer 818, an M4 layer 820, a SiO2 deposit 822, an M1 layer 824, a V3 layer 826, an M3 layer 828, a V2 layer 830, an M2 layer 832, a bottom metal surface 834, a proof mass 836, an array 838 of concentric via rings within the proof mass 836, and an array 840 of concentric via rings along the outer metal ring 810.

[0086] MEMS devices are designed to operate in the linear region. This is because they have large dimensions and large springs that make them soft enough despite their thickness, and the maximum displacement they can have is very small to cover any gaps they may have above, below, in front of, or on the sides. In this way, MEMS springs obey Hooke's law and have a constant stiffness, which generates a mechanical restoring force proportional to the displacement.

[0087] In some instances, if the displacement is large compared to the length of the spring, the mechanical restoring force begins to be proportional to the displacement, but after a certain initial displacement it is no longer linear and grows faster. Thus, while the spring is soft at small displacements around the equilibrium point, which is where the sensor operates with great sensitivity, if the proof mass experiences a larger displacement, for example, if it is subjected to an impact or strong vibration and comes into contact with a surrounding wall, roof, or floor, the mechanical restoring force will become much larger at this point. In this way, the MEMS device returns to its equilibrium position and is decoupled from the stiction force by this grown mechanical restoring force at the point of contact.

[0088] A more detailed view of this phenomenon is that all springs are nonlinear. However, while other MEMS devices only experience small displacements, the devices described herein can experience large displacements that enter the nonlinear region of mechanical restoring force to displacement before contacting the surrounding walls, roof, or floor.

[0089] We can count the length of a spring in two ways. One is the linear distance from one end to the other. The second measurement is the total distance along the entire length of the spring, following its meandering and curvature. We consider the longest of these measurements to be the “length” of the spring. In the implementations described herein, the minimum ratio between the length of any spring and the minimum displacement at which the spring can contact the surrounding wall, roof, or floor is at least 1%, but in some designs it can be 5% or even 10%. This principle also works with lower ratios, but they may not be as robust. However, depending on the specific process and overall implementation, 0.5% or even 0.1% may provide sufficient results. Such short ratios are a factor in the MEMS devices described herein that are not found in other MEMS designs, allowing for the implementation of soft springs and short gaps, while simultaneously achieving high-performance devices that can be packaged with all packaging technologies, including WLCSP, with high yield and reliability.

[0090] Another inventive concept involves the design of vertical walls, or more precisely, the definition of the MEMS area, or the restriction of the lateral etching of the silicon oxide, and the mechanical anchors or support of the MEMS. As mentioned previously, other designs use vertical metal walls or anchors.

[0091] In the first case, using vertical metal walls, we cannot seal the device from the top and / or bottom using top and / or bottom metal layers. This means we need special CMOS processes without doped silicon below the bottom metal layer of the BEOL, and / or special, more expensive packaging techniques, such as laminate substrates, to adequately protect the MEMS cavity from the top, and usually also more expensive post-processing etching sequences. This can be totally or partially avoided if the MEMS device allows the top and bottom metal surfaces to be electrically shorted to the surrounding walls, which is usually not possible.

[0092] The second option, using anchors, electrically separates the top and bottom metal layers, but this creates a large parasitic capacitance between them, which degrades device performance. Furthermore, any attempt to improve performance by reducing this parasitic capacitance by reducing the anchor structure or increasing the vHF etch time reduces device yield and reliability.

[0093] The devices of the present invention do not have vertical metal walls or capacitive anchors connecting the top and bottom metal surfaces. Instead, these devices use two different solutions. One solution is to extend the components of the MEMS device, such as springs, located between the top and bottom metal surfaces or electrodes, but it could also be other electrodes, so that they are embedded in silicon oxide with sufficient horizontal spacing so that the vHF does not reach them. In practice, we have found that long distances are not necessary. For example, at the 180 nm CMOS node, 20 μm of metal around the MEMS device is sufficient. Thus, there is metal located around the MEMS device to be released, which holds it in place because its outer edge has silicon oxide around and / or adjacent to it to prevent it from being etched. Preferably, this perimeter metal has a circular outer edge, but other shapes may be implemented.

[0094] In the above solution, we have at least three electrically disconnected components, where the top metal surface, the bottom metal surface, and the components of the MEMS device between them are electrically decoupled, and more components can be electrically disconnected. Alternative implementations can be applied where, instead of having three or more electrically disconnected components, there are only two components. In this example, a portion of the MEMS device may be attached between the top and bottom metal surfaces using a vertical metal wall on one of them but not the other. In some implementations, the MEMS device is connected to the top one. This is because the top metal layer is typically less flat and more curved than the bottom metal layer. This is because the bottom metal layer is not separated from the underlying silicon oxide. To increase the mechanical integrity of these outer rings, we can connect them using an array of vias. To make them even more robust, we can use an array of concentric via rings, like those used inside the proof mass, instead of the usual square via array. In this case, however, there are no holes through the outer rings, as occurs in the proof mass, so the rings do not need to be broken; they can be continuous.

[0095] Another implementation aspect that can be applied to these last two options is that because we do not use vertical metal walls shorting the top and bottom metal planes or connecting them with capacitive anchors, we can reduce the dimensions of the bottom metal plane compared to the larger dimensions of the top metal plane. This is because the lateral overetch is larger for the top metal than for the bottom metal layer because the vHF must etch and reach the bottom metal layer first in order to etch it. The lateral overetch is the distance from the outermost edge of the passivation opening window on the MEMS device that we need to release to the outermost location where there is silicon oxide that will be etched after the vHF post-processing step. That is, we do not use metal vertical walls shorting from top to bottom, nor do we use capacitive anchors, but instead surround the MEMS device with a metal region that extends into the surrounding silicon oxide, so that part of this metal region has its surrounding silicon oxide etched during the vHF step, but beyond a certain point it no longer etchs.

[0096] With this approach, we reduce the parasitic capacitance between the top and bottom metal planes, which is also the parasitic capacitance between the top or bottom metal planes and the moving parts of the MEMS device when using the second approach above, i.e., when we shorten the section between the top and bottom metal planes using one of these vertical planes or connections. This reduction in parasitic capacitance improves the sensitivity or performance of the device.

[0097] The size of the reduction in the width of the outer ring on the lower metal plate compared to the top metal plate depends on the CMOS process and overall design, but in some implementations it is 10% to 50%, with 30% being a preferred value. In some implementations, the width for the outer ring on the top metal plate is 20 μm, which means the outer ring width on the bottom metal plate may have a preferred dimension of 6 μm. If the central disk (proof mass and spring) has a diameter of 50 μm, the total dimension of the top plate may be 90 μm, and the diameter for the entire bottom plate may be 62 μm.

[0098] We anchor a portion between the top and bottom metal surfaces with a metal region around which extends a metal region that will be embedded in the unetched silicon oxide. We can then create them with dimensions smaller than the top metal surface but larger than the bottom metal surface. In this case, due to their overetching, it is somewhat between the top and bottom metal surfaces. In some implementations, the outer ring width for this intermediate plate or plates is 30% to 70% of the ring width for the top metal surface. In one implementation, the value may be 50%. However, this ultimately depends on the specific CMOS process and overall design. If the top metal surface has a circular shape, it may include an inner disk adjacent to the outer ring that surrounds it. The inner disk may have an array of holes therein that allow vHF to enter the MEMS cavity, while the outer ring is solid (with a possible exception, described below, for constructing a trench to electrically isolate most of this outer ring).

[0099] The inner disk expansion is, in principle, the expansion of the MEMS we want to release with vHF. However, another ingenious concept is to reduce the expansion of the inner disk, so we don't place release holes around the outer portions of the MEMS that need to be released. Because the vHF can travel a relatively long distance, all of the MEMS are released, and we minimize overetching the outer rings in all metal layers, thereby reducing their dimensions. This reduces the parasitic capacitance between the top and bottom metal plates and therefore improves the performance of the MEMS. When using this reduced expansion for the release holes, the passivation opening can also be reduced, because we only need to open it over the area with the hole array.

[0100] The reduction in the internal disk we can implement depends on the CMOS process, but in some implementations, it ranges from 2 μm to 20 μm on each side, with a preferred value of 6 μm. That is, the disk diameter is reduced between 4 μm and 40 μm, with a preferred diameter reduction of 12 μm. By implementing this reduction in the internal disk, we can reduce the external ring to the same value in all metal layers that have such an external ring. For clarity, we discuss an internal disk and an external ring, but in reality, the layout of the top metal layer is a single disk. An etched hole array is then placed in the center and covers the area defined by the dimensions of the internal disk. Therefore, the surrounding solid area without etched holes can be referred to as the external ring. Also for clarity, when we say we are reducing the internal disk, this does not affect the dimensions for the proof mass, spring, or other components of the MEMS device that need to be released. The internal disk here only defines the area on the MEMS device or component that needs to be released and has an etched hole array.

[0101] The above explanation is also valid when there are several electrically disconnected components between the top and bottom metal layers, each with its own metal extension buried in silicon oxide, which are electrically disconnected between them, but there is always some electrical parasitic capacitance.

[0102] The preferred approach is to have this external metal area between the top and bottom metal surfaces to support the MEMS components, surrounding all internally released MEMS and providing better mechanical consistency, although this is not strictly necessary. This can be particularly beneficial in the above case where there are two or more electrically disconnected MEMS components between the top and bottom metal layers. One example of this is for an in-plane inertial sensor, where there are several side electrodes arranged to sense acceleration in different directions.

[0103] Another variation to reduce the parasitic capacitance between the top metal surface (and the middle portion of the MEMS device, for example, if it is electrically shorted to it using a vertical metal connection to it) and the bottom metal surface is to add a very short trench around all top metal surfaces at a certain distance from the MEMS that need to be released. In some implementations, this trench is placed at half the overetch distance. In one configuration, this is about 10 μm, since the total length of this metal area around the MEMS is about 20 μm. However, the distance can be as short as 5 μm or even zero. Preferably, it is placed at a distance of 5 μm to 15 μm. Also, the extension of the top metal plate can be a distance of about 20 μm. However, it can be 5 μm to 30 μm, depending on the specific CMOS process characteristics, the overall MEMS design, and the required vHF characteristics and recipe.

[0104] The trench width should be as small as the process allows. This width can be 0.8 μm, but in some implementations it ranges from 0.5 μm to 2 μm, depending on the process and, in particular, the thickness of the top metal layer. To maintain passivation, a metal ring can be implemented beyond the trench. This trench splits the outer ring into two parts, one inside the other, electrically and mechanically decoupling them. There is some parasitic capacitance between them, and they ultimately connect to the silicon oxide, so they do not move relative to each other.

[0105] Therefore, one may wonder why we need to retain the outer portion of this split outer ring. The reason is that there is over-etching during the vHF post-processing step, which etches away the silicon oxide located between the passivation and this top metal layer, making the passivation very brittle. For this reason, it is preferable to retain the outermost metal ring, so that it can be supported in case the passivation is broken. However, depending on the process characteristics and overall design, it may be possible to simply remove this outer portion of the outer ring and, instead of building a trench for it, simply reduce its diameter. This would further reduce the parasitic capacitance.

[0106] A preferred implementation has a short vertical metal wall surrounding the MEMS device and connected to the top metal surface. This vertical metal wall may or may not be connected to a moving part of the MEMS, such as a spring anchor, located between the top and bottom metal surfaces. The purpose of this short wall (i.e., not down to the bottom metal surface) is to prevent the vHF from etching horizontally under the top metal surface toward its outer edge, forcing the vHF to first descend the vertical wall and then return upward so that it can etch under the top metal surface toward its outer edge. Depending on the implementation, this short vertical metal wall may also provide mechanical integrity and / or electrical connections to other parts of the MEMS device (e.g., spring anchors, etc.).

[0107] Another implementation that achieves a mechanical connection between two MEMS components without electrically shorting them without using capacitive anchors is to use a MIM layer in the MEMS process. This layer typically does not etch away with vHF, or at least etches slowly, depending on the specific CMOS process. This provides a more compact solution than capacitive anchors. However, the capacitance tends to be larger and the mechanical robustness may not be sufficient. However, in some implementations, it may still be beneficial depending on the MEMS device, process, and overall design. In some implementations, it may also be beneficial to use horizontal capacitive anchors instead of vertical capacitive anchors. In some configurations, mixed designs can be implemented using the same design principles as capacitive anchors of any type or combination of types, implementing feedthroughs that route connections to MEMS metal walls or surfaces.

[0108] The array of holes in the top metal plane 222 is made as small as possible. They may be smaller than allowed by the process's DRC, but are sufficient to ensure openness through the entire top metal thickness. This minimum dimension depends on the specific CMOS process, particularly the top metal thickness. In some implementations, the dimension is 0.8 μm wide. Below this, it is usually difficult for them to open completely, which would result in low production yields. As discussed below, larger values ​​may not be properly filled when we apply a sealing layer. Therefore, there is a trade-off: when patterning the top metal layer during the CMOS process, we cannot have holes that are too small to open, nor holes that are too large that would not seal properly during subsequent packaging. Therefore, in some implementations, the hole dimension is between 0.5 μm and 1.5 μm, with 0.8 μm being the preferred value. However, depending on the CMOS process, top metal thickness, sealing material, thickness, and process being used, the etch hole dimension may vary. In some implementations, if the holes are very small, they are depicted as square holes. This is because, in fact, any other shapes make no difference as we push the process solution, and they are partially rounded anyway during device fabrication.

[0109] The separation between holes on a top metal surface, e.g., top plate 222, can be similar to the vertical length of the vertical distance from the top to the bottom metal layers M1 through M6. In some configurations, the etch holes are spaced horizontally on top metal layer 222 a distance at least twice this vertical distance between M1 and M6. In some implementations, the distance can be greater, given that vHF etches more slowly in the vertical direction compared to the horizontal direction due to multiple oxide sublayers with different densities and etch rates. The goal is to ensure that the holes are spaced close enough together so that we properly etch all the volume inside the MEMS cavity, while at the same time avoiding the formation of a weak top metal surface with so many holes and so little metal remaining that it may not be able to withstand sealing on top of it when the device is packaged, as described later in this specification.

[0110] We have experimentally found that a sufficient value is to space the etch holes at a distance between 50% and 200% of the height of the metal stack. This height is measured from the lowest point of the bottom metal layer M1 to the highest point of the top metal layer, e.g., M6. A preferred value is to separate the holes by a distance equal to this height (e.g., 100%). The hole distance is measured from the center of one hole to the center of another hole in both the horizontal (X) and vertical (Y) directions.

[0111] To allow the vHF to descend to the lowest level of silicon oxide so that all the silicon oxide that needs to be removed is properly etched in all cavities, an identical array of holes is implemented through all the MEMS devices inside the cavities. This can be shifted laterally relative to the holes in the top metal surface, but the preferred implementation is to simply place them in the same location. If these holes pass through structures with trapped silicon oxide inside them, such as proof masses, these holes can be surrounded by via walls to prevent the vHF from passing inside these holes and etching the silicon oxide that we want to remain unetched. Given the small dimensions of these holes, which can be preferably made square, these via barriers can be implemented as square rings.

[0112] The fourth inventive concept is the use of a sealing layer present in the WLCSP process, also known as repassivation. This is typically made of polyimide (PI), but can also use benzocyclobutene (BCB) or other coatings to seal the MEMS cavity. This avoids the need for specialized aluminum sputtering and patterning processes, reducing post-processing complexity and cost, which is further reduced by only vHF etching and post-backing. Additionally, the use of PI or BCB was found to provide a better seal and better cover the array of holes in the top metal layer. In contrast, aluminum sputtering requires a very thick deposition, and even then, due to the conformality of the deposition, some holes may not be properly sealed. This does not occur with PI, which seals all holes very well. Even in cases involving other types of packages other than WLCSP, the process can apply PI, BCB, or other coatings and patterning (even aluminum sputtering; while not ideal, it can be done with sufficient thickness and the right set of parameters) and then continue the packaging process.

[0113] Another key inventive concept involves not using metal fill structures within the MEMS cavity. To compensate for metal residual stress, CMOS designs must have a consistent metal density across all areas of the ASIC. To achieve this, once the ASIC design is finalized, an automated process called "metal fill" is performed, which fills all empty areas with random small metal shapes to achieve the required target metal density. This metal fill must not be performed within the MEMS cavity. Otherwise, after applying vHF, all these small metal fill structures will release and adhere to the MEMS device due to stiction, preventing it from functioning properly or at all.

[0114] All descriptions provided in this application may apply to different CMOS nodes, different metal stacks, and even different solid-state semiconductor processes. Also, when we describe top and bottom metal layers, these typically refer to the top and bottom metal layers in the process layer stack. However, it may also apply to other metal layers. When building an inertial sensor in a six-metal-layer process, we typically require all available metal layers to maximize the thickness and therefore mass of the sensor proof mass. However, if the process has more available metal layers, or if we are building another type of MEMS device, or even for an inertial sensor, and we manage to obtain the required specifications, we may not need to use all available metal layers in the metal stack. In this case, we prefer to use the top-located ones, thus leaving the bottom-located metal layers to be used by the ASIC to make electrical connections to it. In this case, there is no dedicated area for mounting the MEMS; instead, the MEMS is mounted on the ASIC.

[0115] In all cases, the active area (FEOL) under the MEMS can be used to implement the ASIC. However, if there are no available metal layers to use for connections, they will all be used to implement the MEMS, making it difficult to implement useful portions of the ASIC under the MEMS. However, depending on the process and the specific ASIC design, it may be beneficial to implement large transistors or other circuits that require little wiring, and / or polysilicon lines, if available, can be used for this wiring. In cases where not all metal layers in the process stack are used to implement the MEMS, all descriptions in this application should be understood as follows: "Top" and "bottom" metal layers are the top and bottom metal layers used to implement the MEMS device, not the top and bottom of the metal stack. While preferred embodiments include using circular and rounded shapes, the disclosed invention can be applied to other types of shapes.

[0116] Yet another important inventive concept involves sensing electronics interfacing with MEMS, whether they are capacitive MEMS sensors, such as, but not limited to, accelerometers, bone conduction sensors, motion detectors, ultrasonic sensors, or any other capacitive sensor. In one implementation, the MEMS capacitive sensors herein have a uniquely small capacitance. This is due in part to their small size and unique features, resulting from several of the concepts discussed above, and to minimal parasitic capacitance. Also, due to the proximity of the ASIC attached to the MEMS edge, there is no need to wire the MEMS to a separate die on which the ASIC is located, and in the case of wafer bonding methods or building the MEMS on an ASIC CMOS wafer, there is no need even to connect the MEMS to the top of the wafer on which the ASIC is located.

[0117] In some implementations, current MEMS sensors have capacitances on the order of 10 fF to 100 fF, or about 50 fF. This is about 100 times smaller than commercially available MEMS devices for consumer electronics. This allows for the implementation of completely different sensing schemes that are not possible with other MEMS devices because they imply too much power consumption.

[0118] In some configurations, MEMS capacitance sensing is accomplished by building a ring oscillator, where at least one of the capacitances in the loop is a MEMS device as described herein. This ring oscillator feeds a counter that is read and reset every sample period. The output of the counter is already digital and outputs the capacitance value. This approach has many technical advantages. First, it simplifies the analog design, which is all digital with the sole exception of the ring oscillator. This means that there are many analog blocks that we would otherwise need but avoid here, such as transconductance amplifiers, programmable gain amplifiers, A / D converters, analog filters, choppers, and capacitance mismatch compensation, among others. This simplification has many technical advantages: smaller ASIC area, very low manufacturing costs, reduced design time, very fast time to market, reduced development costs, easy portability to other CMOS nodes and processes, and lower power.

[0119] The lower power consumption comes from avoiding numerous analog blocks that consume large amounts of power. However, the tradeoff for these blocks is that the process involves continuously charging and discharging the MEMS sensor capacitance at a very high frequency. This high frequency can be between 10 MHz and 100 MHz, depending on the MEMS design, the CMOS process, and the target specifications for the sensor. This would consume excessive power for a typical capacitance on the order of a few picofarads. However, for current MEMS sensors with capacitances on the order of 100 times lower or less, this represents more, but not actually lower, power consumption, making the inventive sensor very power-efficient, in addition to the other advantages mentioned above for this sensing scheme.

[0120] A ring oscillator can change its frequency depending on many factors, such as the supply voltage and its noise, temperature, and even process variations. To compensate for this, a second ring oscillator can be implemented, using another MEMS device built very close to the first ring oscillator, so that it sees roughly the same process, voltage, and temperature variations. This second MEMS device (or devices, if multiple MEMS are included in the ring oscillator loop) is slightly different and has stiffer springs. Preferably, it is made using wider and / or thicker springs (i.e., using more metal stackup). In this way, the capacitance reading from the counter connected to this second sensor will move very little due to the magnitude the sensor measures (e.g., acceleration in the case of an accelerometer), but it will vary in the same way as the first sensor due to all other factors, such as supply voltage, process, and temperature variations.

[0121] In one implementation, two ring oscillators each run a different counter until the second ring oscillator reaches a predetermined value. In this case, we read the first counter, which gives us the value of the sensed magnitude. We then reset the two counters and start counting again. This predetermined value can be programmable, allowing us to define different sampling frequencies. If the sampling frequency is low, the ring oscillators and / or counters are disabled between samples, thus minimizing power consumption. Some implementations include a third digital counter with a very slow digital clock to wake the device each time a new sample needs to be taken.

[0122] In some implementations, to increase the proof mass without increasing its dimensions, metal walls are constructed and / or formed around the entire perimeter of the MEMS device. In this way, the silicon oxide is confined inside the proof mass and is not etched away by vHF. Furthermore, the proof mass with many vias is made of tungsten, which is denser than the silicon oxide and aluminum used in the metal layers. To further increase the effective density and total mass of the proof mass, larger and more closely spaced via arrays can be implemented than permitted by the process DRC. For circular proof masses, we can also use concentric via rings spaced a distance equal to the ring thickness, preferably with this distance and ring width equal to the via dimensions and via spacing defined by the CMOS process DRC. While vias in CMOS processes generally require a fixed square size, in practice, we can expand these vias in one dimension while maintaining at least the specified via dimensions in the other dimension. Otherwise, the wafer will not be properly fabricated. Because we need to make holes all the way through the proof mass, these circular rings may need to be interrupted around the holes. Other shapes can be implemented for both the proof mass and rings, or the via filing structures therein.

[0123] Another important inventive concept involves modifying the pads. This is because there are passivation openings not only over the MEMS device but also over each pad, i.e., vertically aligned with the pad. This is why CMOS processes have passivation openings. This means that when vHF is applied in post-processing, the oxide under the passivation (i.e., between the passivation and the top metal layer) is etched away. If the top metal layer at the pad is not large enough, the silicon etch will go beyond it and etch under the passivation without the metal underneath. When this happens, much of the silicon oxide around the pad is etched away, and the top passivation will eventually have no oxide underneath. This results in a broken passivation and also an etch away of much silicon oxide, potentially destroying part of the ASIC electronics. An implementation to solve this technical problem is to extend at least the top metal layer beyond the conventional pad design (and if we extend more or all other metal layers further to provide better consistency). This extension depends on the specific process and the details of the vHF etch applied. In some implementations, the metal has a lateral extension of 15 μm to 25 μm beyond the passivation opening in all directions. In one implementation, this extension is 20 μm. It is not necessary to use rounded shapes, so in various implementations, the pad maintains a square design for the passivation opening and therefore for the metal that defines it. However, other shapes are also implemented.

[0124] Most of the inventive concepts disclosed herein can be applied to many different devices, including, but not limited to, inertial sensors, gyroscopes, pressure sensors, ultrasonic sensors, transducers such as CMUTs, loudspeakers, magnetometers and compasses, microphones, RF switches, tunable capacitors, RF inductors, temperature sensors, and many others. To avoid the need for CMOS foundries to increase the silicon content of the passivation, we can use special recipes and / or equipment developed, for example, by Memsstar (Scotland). After the vHF etching step, we bake the wafer to sublimate the fluorine residue.

[0125] Due to the smaller size and cost and higher performance of the MEMS devices disclosed herein, as well as their mass production capabilities and fast time to market, the inventive concepts enable the construction of smaller, more powerful smartphones, wearables, and earphones with more functionality and longer lifespans and autonomy due to having more space for larger batteries. These sensors are also enablers of many Internet of Things (IoT) applications, where there is a requirement for very low-cost, small sensors that are produced in very high volumes while still having very low power consumption (high performance). Another application is RFID with embedded sensors.

[0126] FIG. 9 is an exploded view of the metal and via layers of a MEMS device 900 including side electrodes. FIG. 9 shows a variation of the implementation of FIG. 2, which senses planar acceleration by including side electrodes around the bottom of the proof mass without springs. That is, the proof mass is constructed from four metal layers, M2 through M5. The springs are made from metal layers M4 and M5 and have an outer metal ring supporting them. Therefore, the proof mass does not use metal around it in layers M2 and M3. In this way, we use layers M2 and M3 to construct the side electrodes for the proof mass. The shape of these side electrodes is essentially similar to the outer ring of metal layers (M4 and M5) described above, but instead of a whole ring, there are two half rings. Each of these half rings is made from two available metal layers (M2 and M3) stacked together, which means there are many vias inside to connect them. These vias are shaped as an array of concentric half rings.

[0127] The outer diameter of these side electrodes is shorter than the outer ring of the top metal layer, and in this design it is shorter than the bottom metal surface, but it would be an improvement to make the diameter of the bottom metal surface smaller than the outer diameter of these side electrodes.

[0128] Because we maintain the bottom metal surface, we can still sense out-of-plane acceleration as well. Therefore, the MEMS device has several electrodes, and it is possible to fully sense one, two, or even three axes with the same device. This is possible if instead of dividing these side electrodes into half rings, they are divided into quarter rings. Furthermore, differential capacitance can be implemented in the X and Y axes (i.e., in-plane acceleration). Although this design is for an inertial sensor, the same design principles (electrodes, spring supports, etc.) can be used to implement other types of capacitive sensors and actuators.

[0129] The MEMS device 900 includes an M6 layer 902, a V5 layer 904, an M5 layer 906, a V4 layer 908, an M4 layer 910, a V3 layer 912, an M3 layer 914, a V2 layer 916, an M2 layer 918, and an M1 layer 920. The M6 ​​layer 902 includes a top plate 922 with an array of etched holes and connections to the ASIC. The V5 layer 904 includes an array of concentric via rings 924 extending onto the outer metal. The M5 layer 906 includes a proof mass top lid 926 with an array of etched holes. Layer 906 also includes a portion of a helical spring 928 and an outer metal ring 930. The V4 layer 908 includes an array 932 of concentric via rings extending onto the outer metal, a portion of a spiral spring 928 extending onto the V4 layer 908, and an array of concentric via rings 936 extending onto the proof mass, stopping at the etch holes and surrounding them with square rings. The M4 layer 910 includes a proof mass plane 938, a portion of the spiral spring 928, and a portion of the outer metal ring 930. The V3 layer 912 includes an array of concentric via rings 944 extending onto the proof mass, stopping at the etch holes and surrounding them with square rings. The M3 layer 914 includes a proof mass metal plane 946 with an array of etch holes and a side electrode 954 with connections to the ASIC. The V2 layer 916 includes an array 948 of concentric via half rings extending onto the proof mass, stopping at the etch holes and surrounding them with square rings. The V2 layer 916 also includes an array of concentric via half-rings 956 that extend over the side electrodes. The M2 layer 918 includes a proof mass metal bottom lid 950 with an etched hole array. The M2 layer 918 also includes a side electrode 958. The M1 layer 920 includes a bottom metal plane 952 that includes connections to the ASIC.

[0130] Elements or steps of different described implementations may be combined to form other implementations not specifically described above. Elements or steps may generally be omitted from the described systems or processes without adversely affecting their operation or the operation of the system. Furthermore, various separate elements or steps may be combined with one or more individual elements or steps to perform the functions described herein.

[0131] Other implementations not specifically described herein are also within the scope of the following claims.

Claims

1. 1. A MEMS device formed using materials from the BEOL of a CMOS process, comprising: applying a vHF post-processing and post-backing to form the MEMS device; A MEMS device, wherein the total dimension of the MEMS device is between 50 μm and 150 μm.

2. The MEMS device of claim 1 , wherein the total dimension of the MEMS device is less than 100 μm.

3. 3. A MEMS device according to claim 1 or 2, further comprising a set of at least three springs evenly distributed around the MEMS device and rotated about a central axis of the MEMS device.

4. 4. The MEMS device according to claim 1, wherein the MEMS device has a circular shape, and the spring has a spiral shape.

5. The MEMS device according to any one of claims 1 to 4, wherein the spring is made from one of a single metal layer and a stack-up of at least two metal layers.

6. The MEMS device according to any one of claims 1 to 5, wherein the MEMS device is an inertial sensor.

7. 7. A MEMS device according to any one of claims 1 to 6, comprising a proof mass, the proof mass being made from a stackup of four metal layers and the spring, the spring being made from the top metal layer of the proof mass forming the stackup and connected to the top metal layer, or connected to two top metal layers of the stackup.

8. A MEMS device according to any preceding claim, wherein the spring is connected to the outer ring such that a portion of the spring remains embedded in silicon oxide on its outer edge after vHF etching.

9. The MEMS device of any one of claims 1 to 8, wherein the MEMS device has a top metal surface and a bottom metal surface that is smaller than the top metal surface.

10. 10. The MEMS device of claim 9, wherein the width of the outer ring of the bottom metal surface is less than or equal to 10% to 50% of the width of the outer ring of the top metal surface.

11. 11. A MEMS device according to any preceding claim, comprising a pad, said pad comprising a top metal layer arranged to extend laterally beyond vertically aligned passivation openings by 15 μm to 25 μm in all directions.

12. A MEMS device according to any preceding claim, wherein the MEMS device is formed in a MEMS cavity that does not include a metal filling structure.

13. A MEMS device comprising a set of at least three springs evenly distributed around the MEMS device and rotated about a central axis of the MEMS device.

14. The MEMS device of claim 13 , wherein the MEMS device is circular in shape and the spring has a helical shape.

15. 15. The MEMS device according to claim 13 or 14, wherein the spring is made from one of a single metal layer and a stack-up of at least two metal layers.

16. The MEMS device according to any one of claims 13 to 15, wherein the MEMS device is an inertial sensor.

17. 17. A MEMS device according to any one of claims 13 to 16, comprising a proof mass made from a stackup of four metal layers and the spring, the spring being connected to the top metal layer of the proof mass forming the stackup or to the two top metal layers of the stackup.

18. A MEMS device comprising a spring, the ratio of maximum displacement to length of said spring being at least 1%.

19. 20. The MEMS device of claim 18, wherein the proof mass is made of a stackup of four metal layers and the spring, and the spring is connected to the top metal layer of the proof mass that forms the stackup or to the two top metal layers of the stackup.

20. the spring is connected to the outer ring such that a portion of the spring remains embedded in silicon oxide on its outer edge after vHF etching; 20. The MEMS device according to claim 18 or 19, wherein the width of the outer ring of the bottom metal surface is less than or equal to 10% to 50% of the width of the outer ring of the top metal surface.

21. 1. A method for fabricating a MEMS device using materials from the BEOL of a CMOS process, comprising: applying a vHF post-treatment and post-backing to form the MEMS device; and The method includes the MEMS device having a total dimension of between 50 μm and 150 μm.

22. 22. The method of claim 21, wherein the total dimension of the MEMS device is less than 100 μm.

23. 23. The method of claim 21 or 22, further comprising forming a set of at least three springs evenly distributed around the MEMS device and rotated about a central axis of the MEMS device.

24. 24. The method of any one of claims 21 to 23, comprising forming the device shape as a circle, and the spring having a helical shape.

25. The method of any one of claims 21 to 24, comprising forming the spring from one of a single metal layer and a stack-up of at least two metal layers.

26. The method of any one of claims 21 to 25, wherein the MEMS device is an inertial sensor.

27. 27. The method of any one of claims 21 to 26, comprising forming a proof mass, the proof mass being made from a stackup of four metal layers and the spring, the spring being connected to the top metal layer of the proof mass forming the stackup or to the two top metal layers of the stackup.

28. A method according to any one of claims 21 to 27, comprising connecting the spring to an outer ring such that a portion of the spring remains embedded in silicon oxide on its outer edge after vHF etching.

29. The method of any one of claims 21 to 28, comprising forming the MEMS device having a top metal surface and a bottom metal surface that is smaller than the top metal surface.

30. 30. The method of claim 29, including forming the width of the outer ring of the bottom metal surface to be less than or equal to 10% to 50% of the width of the outer ring of the top metal surface.

31. 31. The method of any one of claims 21 to 30, comprising forming pads, said pads comprising a top metal layer arranged to extend laterally beyond the vertically aligned passivation openings by 15 μm to 25 μm in all directions.

32. A method according to any one of claims 21 to 31, comprising forming the MEMS device in a MEMS cavity that does not contain a metal filling structure.

33. A method for manufacturing a MEMS device comprising forming a set of at least three springs evenly distributed around a MEMS device and rotated about a central axis of said MEMS device.

34. 34. The method of claim 33, comprising forming the MEMS device in a circular shape and forming the spring in a helical shape.

35. 35. The method of claim 33 or 34, comprising forming the spring from one of a single metal layer and a stack-up of at least two metal layers.

36. The method of any one of claims 33 to 35, wherein the MEMS device is an inertial sensor.

37. 37. The method of any one of claims 33 to 36, comprising forming a proof mass, the proof mass being made from a stackup of four metal layers and the springs, the springs being connected to the top metal layer of the proof mass forming the stackup or to the two top metal layers of the stackup.

38. A method for fabricating a MEMS device comprising forming a spring having a ratio of maximum displacement to length of the spring of at least 1%.

39. 39. The method of claim 38, comprising forming a proof mass, the proof mass being made from a stackup of four metal layers and the springs, the springs being connected to the top metal layer of the proof mass forming the stackup or to the top two metal layers of the stackup.

40. connecting said spring to an outer ring such that a portion of said spring remains embedded in silicon oxide on its outer edge after vHF etching; and 40. The method of claim 38 or 39, comprising forming the width of the outer ring of the bottom metal surface to be less than or equal to 10% to 50% of the width of the outer ring of the top metal surface.

41. A smartphone, wearable, earphone or Internet of Things (IoT) device comprising a MEMS device according to any one of claims 1 to 20.

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