Display panel and display device

Abstract

To provide a display panel and a display device.SOLUTION: A display panel and a display device are disclosed. The display panel includes: a substrate including a display region, a peripheral region, and a pad region existing on one side of the peripheral region apart from the display region; at least one barrier existing in the peripheral region, surrounding the display region, and including a one-side barrier structure existing between the display region and the pad region; an organic insulating structure including a plurality of sub-insulating structures that are stacked, in which a part of the sub-insulating structures exists in the display region; each sub-insulating structure includes a first border existing between the display region and the one-side barrier structure, the first border of the sub-insulating structures on the side apart from the substrate with respect to the two arbitrary adjacent sub-insulating structures is closer to the display region than the first border of the sub-insulating structures on the side closer to the substrate; and the distance between the first borders of the two arbitrary adjacent sub-insulating structures is 20 μm or more; a touch electrode pattern; and a touch signal line.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, and more particularly to display panels and display devices. [Background technology]

[0002] OLED display devices have been widely used with the development of organic light emitting diode (OLED) display technology. To meet user needs for product thickness and touch experience, a touch function layer is fabricated on the encapsulation layer of the OLED display panel during the production process. Summary of the Invention [Means for solving the problem]

[0003] An embodiment of the present disclosure provides a display panel and a display device.

[0004] According to a first aspect of the present disclosure, there is provided a display device including: a substrate including a display area, a peripheral area surrounding the display area, and a pad area located on one side of the peripheral area away from the display area; At least one barrier disposed on the substrate, located in the peripheral region and surrounding the display region, the barrier including a one-sided barrier structure located between the display region and the pad region; an organic insulating structure disposed on the substrate, the organic insulating structure including a plurality of sub-insulating structures arranged in a stack, a portion of each of the plurality of sub-insulating structures being located in the display area, each of the plurality of sub-insulating structures having a first boundary located between the display area and the one-sided barrier structure, wherein for any two adjacent sub-insulating structures, the first boundary of the sub-insulating structure farther from the substrate is closer to the display area than the first boundary of the sub-insulating structure closer to the substrate, and the distance between the first boundaries of any two adjacent sub-insulating structures is 20 μm or more; a touch electrode pattern disposed on one side of the organic insulating structure away from the substrate; a touch signal line disposed on one side of the organic insulating structure away from the substrate, one end electrically connected to the touch electrode pattern and the other end connected to the pad area, wherein an orthogonal projection of a portion of the touch signal line in the peripheral area on the substrate intersects with a first boundary of each of the sub-insulating structures.

[0005] In some embodiments, the distance between the first boundaries of any two adjacent sub-insulating structures is between 25 μm and 60 μm.

[0006] In some embodiments, the plurality of sub-insulating structures of the organic insulating structure are a first planarization layer disposed on the substrate; a second planarization layer positioned on one side of the first planarization layer away from the substrate; a pixel-defining layer located on one side of the second planarization layer away from the substrate.

[0007] In some embodiments, there is a space between the first boundary of the sub-insulating structure and the one-sided barrier structure.

[0008] In some embodiments, the display panel further includes an encapsulation layer located on one side of the organic insulating structure away from the substrate, and the touch electrode pattern and the touch signal line are both located on one side of the encapsulation layer away from the substrate.

[0009] In some embodiments, the sealing layer comprises: a first inorganic sealing layer; a second inorganic sealing layer located on one side of the first inorganic sealing layer away from the substrate; an organic sealing layer located between the first inorganic sealing layer and the second inorganic sealing layer.

[0010] In some embodiments, a groove is formed between the organic insulating structure and the one-sided barrier structure, and the orthogonal projection of the encapsulation layer on the substrate simultaneously covers the orthogonal projection of the organic insulating structure on the substrate, the orthogonal projection of the groove on the substrate, and the orthogonal projection of the one-sided barrier structure on the substrate, and the one-sided barrier structure is located between the substrate and the encapsulation layer.

[0011] In some embodiments, the display panel further includes a touch insulating layer disposed on one side of the encapsulation layer away from the substrate; The touch electrode pattern includes a plurality of touch driving electrodes and a plurality of touch sensing electrodes, the touch driving electrodes and the touch sensing electrodes are arranged to intersect with each other, the intersections of the touch driving electrodes and the touch sensing electrodes are insulated and separated by the touch insulating layer, and each of the touch driving electrodes and each of the touch sensing electrodes is connected to one of the touch signal lines.

[0012] In some embodiments, the touch drive electrode includes a plurality of drive electrode units arranged along a first direction and a connection portion connected between each two adjacent drive electrode units; The touch sensing electrode includes a plurality of sensing electrode units arranged along a second direction and a bridge connecting each two adjacent sensing electrode units; The first direction and the second direction intersect, the driving electrode unit, the connection part and the sensing electrode unit are all located on one side of the touch insulating layer away from the substrate and are located in the same layer, and the bridge is located between the touch insulating layer and the encapsulation layer.

[0013] In some embodiments, the touch signal line includes a first transmission part located between the touch insulating layer and the encapsulation layer, and a second transmission part located on one side of the touch insulating layer away from the encapsulation layer, and the second transmission part is electrically connected to the first transmission part through a via hole penetrating the touch insulating layer.

[0014] In some embodiments, the display panel has a plurality of pixel units, each pixel unit having a light-emitting element, and further includes a power supply line electrically connected to the light-emitting element, wherein the power supply line is located between the organic insulating structure and the substrate, and an orthogonal projection of the power supply line on the substrate overlaps with an orthogonal projection of the first boundary on the substrate.

[0015] In some embodiments, the barrier comprises: a first barrier located in the peripheral region and surrounding the display region; a second barrier located in the peripheral region and surrounding the first barrier; The one-sided barrier structure is formed by a portion of the first barrier located between the display area and the pad area, and a portion of the second barrier located between the display area and the pad area.

[0016] In some embodiments, the substrate is a flexible substrate and further includes a flex region located between the peripheral region and the pad region.

[0017] In some embodiments, the display panel comprises: a first buffer layer disposed on the substrate; a semiconductor layer disposed between the first buffer layer and the first planarization layer; a first gate insulating layer disposed between the semiconductor layer and the first planarization layer; a first gate electrode layer disposed between the first gate insulating layer and the first planarization layer; a second gate insulating layer disposed between the first gate electrode layer and the first planarization layer; a second gate electrode layer disposed between the second gate insulating layer and the first planarization layer; an interlayer insulating layer disposed between the second gate electrode layer and the first planarization layer; a first source / drain conductive layer disposed between the interlayer insulating layer and the first planarization layer; a passivation layer disposed between the first source / drain conductive layer and the first planarization layer; a second source / drain conductive layer disposed between the first planarization layer and the second planarization layer; a first electrode layer disposed between the second planarization layer and the pixel definition layer, the first electrode layer including a plurality of first electrodes, the pixel definition layer including pixel openings corresponding one-to-one to the first electrodes; a light-emitting layer disposed within the pixel opening; a second electrode layer disposed on one side of the light emitting layer away from the substrate; a sealing layer disposed on one side of the light-emitting layer away from the substrate; a second buffer layer disposed on one side of the encapsulation layer away from the substrate.

[0018] According to a second aspect of the present disclosure, a substrate including a display area, a peripheral area surrounding the display area, and a pad area located on one side of the peripheral area away from the display area; At least one barrier disposed on the substrate, located in the peripheral region and surrounding the display region, the barrier including a one-sided barrier structure located between the display region and the pad region; an organic insulating structure disposed on the substrate, a portion of which is located in the display region and another portion of which is located in the peripheral region, the organic insulating structure having a bottom surface facing the substrate, a top surface opposite to the bottom surface, and a first side surface connecting the bottom surface and the top surface and facing the one-sided barrier structure, the first side surface being an inclined surface with an inclination angle of 0 to 40°; a touch electrode pattern disposed on one side of the organic insulating structure away from the substrate; a touch signal line disposed on one side of the organic insulating structure away from the substrate, one end electrically connected to the touch electrode pattern and the other end connected to the pad area, wherein an orthogonal projection of a portion of the peripheral area on the substrate passes through an orthogonal projection of the inclined surface on the substrate.

[0019] In some embodiments, the inclination angle of the inclined surface is 25 to 35°.

[0020] In some embodiments, the plurality of sub-insulating structures of the organic insulating structure are a first planarization layer disposed on the substrate; a second planarization layer positioned on one side of the first planarization layer away from the substrate; a pixel-defining layer located on one side of the second planarization layer away from the substrate.

[0021] In some embodiments, there is a space between the first side and the one-sided barrier structure.

[0022] In some embodiments, the display panel further comprises an encapsulation layer located on one side of the organic insulating structure away from the substrate; The touch electrode pattern and the touch signal line are both located on one side of the encapsulation layer away from the substrate.

[0023] In some embodiments, the sealing layer comprises: a first inorganic sealing layer; a second inorganic sealing layer located on one side of the first inorganic sealing layer away from the substrate; an organic sealing layer located between the first inorganic sealing layer and the second inorganic sealing layer.

[0024] In some embodiments, a groove is formed between the organic insulating structure and the one-sided barrier structure, and the orthogonal projection of the encapsulation layer on the substrate simultaneously covers the orthogonal projection of the organic insulating structure on the substrate, the orthogonal projection of the groove on the substrate, and the orthogonal projection of the one-sided barrier structure on the substrate, and the one-sided barrier structure is located between the substrate and the encapsulation layer.

[0025] In some embodiments, the display panel further includes a touch insulating layer located on one side of the encapsulation layer away from the substrate; The touch electrode pattern includes a plurality of touch driving electrodes and a plurality of touch sensing electrodes, the touch driving electrodes and the touch sensing electrodes are arranged to intersect with each other, the intersections of the touch driving electrodes and the touch sensing electrodes are insulated and separated by the touch insulating layer, and each of the touch driving electrodes and each of the touch sensing electrodes is connected to one of the touch signal lines.

[0026] In some embodiments, the touch drive electrode includes a plurality of drive electrode units arranged along a first direction and a connection portion connected between each two adjacent drive electrode units; The touch sensing electrode includes a plurality of sensing electrode units arranged along a second direction and a bridge connecting each two adjacent sensing electrode units; The first direction and the second direction intersect, the driving electrode unit, the connection part and the sensing electrode unit are all located on one side of the touch insulating layer away from the substrate and are located in the same layer, and the bridge is located between the touch insulating layer and the encapsulation layer.

[0027] In some embodiments, the touch signal line includes a first transmission part located between the touch insulating layer and the encapsulation layer, and a second transmission part located on one side of the touch insulating layer away from the encapsulation layer, and the second transmission part is electrically connected to the first transmission part through a via hole penetrating the touch insulating layer.

[0028] In some embodiments, the display panel has a plurality of pixel units, each pixel unit having a light-emitting element, and further includes a power supply line electrically connected to the light-emitting element, wherein the power supply line is located between the organic insulating structure and the substrate, and an orthogonal projection of the power supply line on the substrate overlaps with an orthogonal projection of the first boundary on the substrate.

[0029] In some embodiments, the barrier comprises: a first barrier located in the peripheral region and surrounding the display region; a second barrier located in the peripheral region and surrounding the first barrier; The one-sided barrier structure is formed by a portion of the first barrier located between the display area and the pad area, and a portion of the second barrier located between the display area and the pad area.

[0030] In some embodiments, the substrate is a flexible substrate and further includes a flex region located between the peripheral region and the pad region.

[0031] In some embodiments, the display panel comprises: a first buffer layer disposed on the substrate; a semiconductor layer disposed between the first buffer layer and the first planarization layer; a first gate insulating layer disposed between the semiconductor layer and the first planarization layer; a first gate electrode layer disposed between the first gate insulating layer and the first planarization layer; a second gate insulating layer disposed between the first gate electrode layer and the first planarization layer; a second gate electrode layer disposed between the second gate insulating layer and the first planarization layer; an interlayer insulating layer disposed between the second gate electrode layer and the first planarization layer; a first source / drain conductive layer disposed between the interlayer insulating layer and the first planarization layer; a passivation layer disposed between the first source / drain conductive layer and the first planarization layer; a second source / drain conductive layer disposed between the first planarization layer and the second planarization layer; a first electrode layer disposed between the second planarization layer and the pixel definition layer, the first electrode layer including a plurality of first electrodes, the pixel definition layer including pixel openings corresponding one-to-one to the first electrodes; a light-emitting layer disposed within the pixel opening; a second electrode layer disposed on one side of the light emitting layer away from the substrate; a sealing layer disposed on one side of the light-emitting layer away from the substrate; The semiconductor device further includes a second buffer layer disposed on one side of the encapsulation layer away from the substrate.

[0032] According to a third aspect of the present disclosure, there is provided a substrate including a display area, a peripheral area surrounding the display area, and a pad area located on one side of the peripheral area away from the display area; At least one barrier disposed on the substrate, located in the peripheral region and surrounding the display region, the barrier including a one-sided barrier structure located between the display region and the pad region; an organic insulating structure disposed on the substrate, the organic insulating structure including a plurality of sub-insulating structures arranged in a stack, a portion of each of the sub-insulating structures being located in the display area, each of the sub-insulating structures having a first boundary located between the display area and the one-sided barrier structure, and each of the sub-insulating structures except for the sub-insulating structure farthest from the substrate includes an extension portion, and for any two adjacent sub-insulating structures, the extension portion of the sub-insulating structure closer to the substrate is located between the first boundary of the sub-insulating structure farther from the substrate and the one-sided barrier structure; a touch electrode pattern disposed on one side of the organic insulating structure away from the substrate; a touch signal line disposed on one side of the organic insulating structure away from the substrate, one end electrically connected to the touch electrode pattern and the other end connected to the pad area, wherein an orthogonal projection of a portion of the touch signal line in the peripheral area on the substrate overlaps with an orthogonal projection of an extension portion of each of the sub-insulating structures on the substrate; The sub-insulating structure having the extension portion is formed by performing a patterning process on the organic material layer using a dual-tone mask plate, and when performing the patterning process, the area where the extension portion is formed provides a display panel corresponding to the semi-transparent area of ​​the dual-tone mask plate.

[0033] In some embodiments, the plurality of sub-insulating structures of the organic insulating structure are a first planarization layer disposed on the substrate; a second planarization layer positioned on one side of the first planarization layer away from the substrate; a pixel-defining layer located on one side of the second planarization layer away from the substrate.

[0034] According to a fourth aspect of the present disclosure, there is provided a display device including the above-described display panel. [Brief explanation of the drawings]

[0035] The drawings are intended to provide a further understanding of the present disclosure, constitute a part of the description, and are intended to explain, but not limit, the present disclosure in conjunction with the following specific embodiments.

[0036] [Figure 1] FIG. 2 is a conceptual diagram of the area division of a substrate of a display panel provided by some embodiments of the present disclosure. [Figure 2] FIG. 1 is a conceptual plan view of a display panel provided by some embodiments of the present disclosure. [Figure 3] FIG. 3 is an enlarged view of the Q1 region in FIG. 2. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA' in FIG. [Figure 5] FIG. 1 is a conceptual diagram of a trench between an organic insulating structure and a one-sided barrier structure in some embodiments of the present disclosure. [Figure 6] FIG. 2 is an equivalent conceptual diagram of a pixel circuit according to some embodiments of the present disclosure. [Figure 7] FIG. 3 is a cross-sectional view taken along the line BB′ in FIG. [Figure 8] FIG. 3 is a cross-sectional view taken along the line DD′ in FIG. 2. [Figure 9] 4 is a cross-sectional view taken along line AA' in FIG. 3 of some other embodiments of the present disclosure. [Figure 10] FIG. 10 is a diagram showing the first structure of the organic insulating structure in FIG. [Figure 11] FIG. 10 is a second structural diagram of the organic insulating structure in FIG. 9. [Figure 12]10A-10C are schematic diagrams illustrating a manufacturing process of a sub-insulation structure having an extension provided by some embodiments of the present disclosure. [Figure 13] 10A-10C are schematic diagrams illustrating a manufacturing process of a sub-insulation structure having an extension provided by some embodiments of the present disclosure. [Figure 14] 10A-10C are schematic diagrams illustrating a manufacturing process of a sub-insulation structure having an extension provided by some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0037] In order to clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure in combination with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all of the embodiments. Based on the described embodiments of the present disclosure, a person skilled in the art can obtain all other embodiments without exerting his or her imagination, and all of them fall within the protection scope of the present disclosure.

[0038] The technical terms used herein to describe the embodiments of the present disclosure are not intended to limit and / or restrict the scope of the present disclosure. For example, unless otherwise defined, technical or scientific terms used in this disclosure have the meaning commonly understood by one of ordinary skill in the art to which the present invention belongs. It should be understood that the terms "first," "second," and similar terms used in this disclosure do not denote any order, number, or importance, but are merely used to distinguish between different components. Similar terms such as the singular forms "one," "one," or "the" also mean the presence of at least one, but do not denote a numerical limitation unless the context clearly indicates otherwise. Similar terms such as "comprise" or "containing" mean that the element or entity preceding "comprise" or "containing" encompasses the elements or entities listed after "comprise" or "containing" and equivalents thereof, and do not exclude other elements or entities. Similar terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "up," "down," "left," and "right" merely indicate relative positional relationships, and if the absolute position of the object being described changes, the relative positional relationships may also change accordingly.

[0039] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or intermediate elements or layers may be present. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, intermediate elements or layers are not present. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] Embodiments of the present disclosure provide a display panel including a substrate. FIG. 1 is a conceptual diagram of the division of a substrate of a display panel provided by some embodiments of the present disclosure. As shown in FIG. 1, the substrate SUB includes a display area DA, a peripheral area PA, and a pad area WA. The peripheral area PA surrounds the display area DA, and the pad area WA is located on one side of the peripheral area PA away from the display area DA. The display area DA may include elements for displaying images, such as pixel circuits, scan lines GL, data lines DL, and light-emitting elements. The display area DA may also include a touch electrode pattern for implementing a touch function. The pad area WA is located on one side of the peripheral area PA away from the display area DA. The pad area WA includes a plurality of contact pads PAD (also referred to as pads), each of which is arranged to electrically connect a signal line extending from the display area DA or the peripheral area PA. For example, the data line DL may be connected to the contact pad via a data connection line. The contact pads PAD may be exposed on the surface of the pad area WA, i.e., not covered by any layer, for electrical connection to a flexible printed circuit board (FPCB). The flexible printed circuit board FPCB is electrically connected to an external controller and arranged to transmit signals from the external controller. The electrical connection between the contact pads PAD and each signal line realizes mutual communication between the signal line and the flexible printed circuit board FPCB. It should be understood that the number and arrangement of the contact pads PAD in FIG. 1 are merely a schematic illustration and do not constitute limitations on the contact pads PAD.

[0041] FIG. 2 is a conceptual plan view of a display panel provided by some embodiments of the present disclosure, FIG. 3 is an enlarged view of region Q1 in FIG. 2, and FIG. 4 is a cross-sectional view along line A-A' in FIG. 3. Referring to FIGS. 1 to 4, the display panel 100 further includes at least one barrier 10, an organic insulating structure 20, a touch electrode pattern and a touch signal line TL.

[0042] The barrier 10 is disposed on the substrate SUB, is located in the peripheral area PA, and surrounds the display area DA. The barrier 10 prevents external moisture and oxygen from entering the display area DA, thereby preventing the display effect from being affected. The barrier 10 includes a one-sided barrier structure located between the display area DA and the peripheral area PA. As a specific example, as shown in FIG. 2 , the barrier 10 includes a first barrier 11 and a second barrier 12 surrounding the first barrier 11. The first barrier 11 includes a first barrier portion 111 located between the display area DA and the peripheral area PA. The second barrier 12 includes a fourth barrier portion 121 located between the display area DA and the peripheral area PA. In this case, the first barrier portion 111 and the third barrier portion 121 form the one-sided barrier structure.

[0043] The organic insulating structure 20 is disposed on a substrate SUB and includes a plurality of sub-insulating structures 21 arranged in a stack, with a portion of each sub-insulating structure 21 located in the display area DA and another portion located in the peripheral area PA. For example, the orthogonal projection of the sub-insulating structure 21 on the substrate SUB extends from the display area DA to between the display area DA and the barrier 10. Each sub-insulating structure 21 has a first boundary E1, and for any two adjacent sub-insulating structures 21, the first boundary E1 of the sub-insulating structure 21 farther from the substrate SUB is closer to the display area DA than the first boundary E1 of the sub-insulating structure 21 closer to the substrate SUB, thereby forming a staircase shape (see FIG. 4). The distance d between the first boundaries E1 of two adjacent sub-insulating structures 21 is 20 μm or more. 3 shows only the Q1 region in FIG. 2 in an enlarged scale to make it easier to understand the positional relationship between the first boundaries E1 of each sub-insulating structure 21, but each first boundary E1 is not located only in the Q1 region in FIG. 2 but corresponds to the entire lower edge of the display area DA in FIG. 2, that is, the first boundary E1 extends from the left end to the right end of the Q region in FIG. 2. Accordingly, the organic insulating structure 20 not only forms the stepped shape in FIG. 4 in the Q1 region, but also forms a stepped shape throughout the Q region.

[0044] The touch electrode pattern is disposed on one side of the organic insulating structure 20 away from the substrate SUB. The touch electrode pattern is configured to detect the occurrence of a touch in the display area DA. For example, the touch electrode pattern includes touch drive electrodes TX and touch sensing electrodes TX shown in FIG. 2 .

[0045] The touch signal lines TL are disposed on one side of the organic insulating structure 20 away from the substrate SUB, one end of each touch signal line TL is electrically connected to the touch electrode pattern, and the other end of each touch signal line TL is connected to the pad area WA, and is electrically connected to the contact pads PAD in the pad area WA. The orthogonal projection of the touch signal lines TL in the peripheral area PA on the substrate SUB intersects with the first boundary E1 of each sub-insulating structure 21.

[0046] If the distance d between the first boundaries E1 of two adjacent sub-insulating structures 21 is relatively small (e.g., d is 5 μm or less), the touch signal lines TL will be located on a relatively steep slope, and in this situation, when the touch signal lines TL are formed using an etching process, residual conductive material is likely to remain between the touch signal lines TL, resulting in short circuits between the touch signal lines TL. In the embodiment of the present disclosure, in each sub-insulating structure 21 of the organic insulating structure 20, the distance d between the first boundaries E1 of two adjacent sub-insulating structures 21 is large, so that the touch signal lines TL are located on a relatively gentle slope, which is advantageous for reducing residual conductive material and reducing or preventing short circuits between the touch signal lines TL.

[0047] In some embodiments, the distance d between the first boundaries E1 of two adjacent sub-insulating structures 21 is 25 μm to 60 μm, thereby minimizing the amount of residual conductive material and simultaneously reducing the outer frame of the display panel 100. For example, d is 30 μm, 35 μm, 40 μm, 45 μm, or 50 μm.

[0048] A display panel according to an embodiment of the present disclosure will be specifically described below with reference to FIGS.

[0049] 2 , the barrier 10 includes a first barrier 11 and a second barrier 12. The first barrier 11 is located in the peripheral area PA and surrounds the display area DA. The second barrier 12 is located in the peripheral area PA and surrounds the first barrier 11, thereby further preventing external moisture or oxygen from entering the display area DA and providing dual protection for the display area DA. In some embodiments, the vertical distance from one end of the first barrier 11 away from the substrate SUB to the substrate SUB is smaller than the vertical distance from one end of the second barrier 12 away from the substrate SUB to the substrate SUB, thereby lengthening the path for external water vapor and oxygen to enter the display area DA and improving the barrier properties of the barrier 10. The first barrier 11 includes a first barrier section 111 located on one side of the display area DA near the curved region (i.e., in FIG. 2, the portion of the first barrier 11 located below the display area DA and extending in the horizontal direction), and a second barrier section 112 which is the remaining portion of the first barrier 11 excluding the first barrier section 111. The second barrier 12 includes a third barrier section 121 located on one side of the display area DA near the curved region (i.e., in FIG. 2, the portion of the second barrier 12 located below the display area DA and extending in the horizontal direction), and a fourth barrier section 122 which is the remaining portion of the second barrier 12 excluding the third barrier section 121. The first barrier section 111 and the third barrier section 113 form the one-sided barrier structure.

[0050] In some embodiments, the substrate SUB is a flexible substrate made of a flexible organic material. For example, the organic material may be a resin-based material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, or polyethylene naphthalate. The substrate SUB further includes a bending region BA located between the peripheral region PA and the pad region WA. The bending region BA is configured to bend along a bending axis BX. By bending the bending region BA, the pad region WA can be positioned behind the display panel 100 (wherein the display side of the display panel 100 is the front side and the side opposite the display side is the rear side or back side), thereby improving space utilization and reducing the outer frame width of the display product.

[0051] In some embodiments, the display area DA includes a plurality of pixel units P, each defined by a scan line GL and a data line DL. The scan line GL is connected to a gate driving circuit in the peripheral area PA, and the data line DL is connected to a contact pad PAD in the pad area WA by a data connection line. Each pixel unit P includes a light-emitting element 50 and a pixel circuit. The light-emitting element 50 may be an organic light-emitting diode (OLED), which can emit, for example, red, green, blue, or white light. FIG. 6 is an equivalent conceptual diagram of a pixel circuit in some embodiments of the present disclosure. As shown in FIG. 6, the pixel circuit includes a driving transistor Td, a switching transistor Ts, and a storage capacitor Cs. The gate of the switching transistor Ts is connected to the scan line GL, a first pole is connected to the data line DL, and a second pole is connected to the gate of the driving transistor Td. Both ends of the storage capacitor Cs are connected to a first power supply line VDD and the gate of the driving transistor Td, respectively. The first electrode of the driving transistor Td is connected to the first power supply line VDD, the second electrode is connected to the first electrode of the light emitting element 50, and the second electrode of the light emitting element 50 is connected to the second power supply line VSS. Each transistor may be a thin film transistor, a field effect transistor, or other device with the same characteristics. The source and drain of the transistors used are symmetrical, so there is no distinction between the source and drain. To distinguish between the source and drain of the transistor, one of the electrodes is referred to as the first electrode and the other as the second electrode.

[0052] The first power supply line VDD is connected from the pad area WA to the display area DA and transmits voltage signals to each pixel unit. The second power supply line VSS is located in the peripheral area PA and includes a first portion surrounding the display area DA in an open loop manner and a second portion. The second portion of the second power supply line VSS is connected between the first portion and the contact pad PAD in the pad area WA. As shown in Figures 2 and 4, the orthogonal projection of the first boundary E1 of each sub-insulation structure 21 on the substrate SUB and the orthogonal projection of the second power supply line VSS on the substrate SUB overlap.

[0053] In some embodiments, the touch electrode pattern may have a mutual capacitance structure or a self-capacitance structure. The embodiments of the present disclosure will be described taking the mutual capacitance structure as an example. As shown in FIG. 2 , the touch electrode pattern includes a plurality of touch drive electrodes TX and a plurality of touch sense electrodes RX. The touch drive electrodes TX and the touch sense electrodes RX are arranged crosswise. The intersections between the touch drive electrodes TX and the touch sense electrodes RX are insulated and separated by a touch insulating layer TLD. FIG. 7 is a cross-sectional view taken along line B-B′ in FIG. 2 . Combining the contents of FIGS. 2 and 7 , the touch drive electrodes TX include a plurality of drive electrode units TX1 arranged along a first direction and a connection portion TX2 connected between the drive electrode units TX1. The touch sense electrodes RX include a plurality of sensing electrode units RX1 and a bridge RX2 connected between the sensing electrode units. The first direction intersects with a second direction. For example, the first direction is the up-down direction in FIG. 2 , and the second direction is the left-right direction in FIG. 2 . The driving electrode unit TX1, the connection portion TX2, and the sensing electrode unit RX1 are respectively located on one side of the touch insulating layer TLD away from the substrate SUB. The driving electrode unit TX1, the connection portion TX2, and the sensing electrode unit RX1 can be arranged on the same layer, and the bridge RX2 is located on one side of the touch insulating layer TLD away from the substrate SUB. The bridge RX2 is arranged across the connection portion TX2 and is separated by the touch insulating layer TLD. The sensing electrode unit RX1 is connected to the bridge RX2 through a via hole on the touch insulating layer TLD. Note that the touch driving electrodes TX and touch sensing electrodes RX shown in FIGS. 2 and 7 are exemplary and do not limit the present invention. For example, the bridge RX2 can be located on one side of the touch insulating layer TLD away from the substrate SUB, and the connection portion can be located on one side of the touch insulating layer TLD closer to the substrate SUB. Further, for example, adjacent driving electrode units TX1 can be connected by a bridge located on a different layer, and adjacent sensing electrode units RX1 can be connected by a connection portion on the same layer.

[0054] Wherein, each touch driving electrode TX and each touch sensing electrode RX may be correspondingly connected to one touch driving line TL. When the touch signal line TL passes through the peripheral area PA, the orthogonal projection of the part of the touch signal line TL in the peripheral area PA on the substrate SUB intersects with the first boundary E1 of each sub-insulation structure 21. In one example, the touch insulation layer TLD also covers at least the peripheral area PA between the display area DA and the pad area WA, and the touch signal line TL in the peripheral area PA between the display area DA and the pad area WA is located on the touch insulation layer TLD. In one example, the thickness of the touch insulation layer TLD is 0.2 μm to 0.5 μm, for example, 0.3 μm, 0.33 μm, or 0.35 μm.

[0055] In some embodiments, as shown in FIG. 4 , the touch signal line TL has a two-layer structure and includes a first transmission part TL1 located on one side of the touch insulating layer TLD close to the substrate SUB and a second transmission part TL2 located on one side of the touch insulating layer TLD away from the substrate SUB. The second transmission part TL2 is electrically connected to the first transmission part TL1 through a via hole penetrating the touch insulating layer TLD. Note that, for the sake of schematic illustration of the connection between the second transmission part TL2 and the first transmission part TL1, only one via hole is shown in FIG. 4 . However, in practice, multiple via holes may be provided at other positions, and the second transmission part TL2 may be connected in parallel to the first transmission part TL1 through the multiple via holes. The first transmission part TL1 may be disposed on the same layer as the bridge RX2, and the second transmission part TL2 may be disposed on the same layer as the driving electrode unit TX1, the connection part TX2, and the sensing electrode unit RX1.

[0056] 7, the first buffer layer BFL1 is disposed on the substrate SUB to prevent or reduce diffusion of metal atoms and / or impurities from the substrate SUB into the active layer of the transistor. In the embodiment of the present disclosure, the first buffer layer BFL1 exposes a portion of the top surface of the substrate SUB located in the bending region BA to facilitate bending of the substrate SUB. For example, the first buffer layer BFL1 may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), and / or silicon oxynitride (SiON), and may be formed as a multilayer or single layer.

[0057] The semiconductor layer is disposed on the first buffer layer BFL1. The semiconductor layer may be made of, for example, an inorganic semiconductor material (e.g., polycrystalline silicon, amorphous silicon, etc.), an organic semiconductor material, or an oxide semiconductor material. The semiconductor layer includes an active layer 31 of each transistor 30. The active layer 31 includes a channel portion, a source connection portion and a drain connection portion located on both sides of the channel portion. The source connection portion is connected to the source 33 of the transistor 30, and the drain connection portion is connected to the drain 34 of the transistor 30. The source connection portion and the drain connection portion may be doped with impurities (e.g., N-type impurities or P-type impurities) at a higher concentration than the channel portion. The channel portion faces the gate 32 of the transistor 30. When a voltage signal applied to the gate 32 reaches a certain value, a carrier path is formed in the channel portion, establishing electrical continuity between the source 33 and the drain 34 of the transistor 30.

[0058] The first gate insulating layer GI1 is disposed on the semiconductor layer, and the first gate insulating layer GI1 exposes a portion of the top surface of the substrate SUB located in the bending region BA, facilitating bending of the substrate SUB. The first gate insulating layer GI1 may be made of a silicon compound or a metal oxide. For example, the first gate insulating layer GI1 may be made of silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon oxycarbide (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The first gate insulating layer GI1 may be a single layer or a multilayer.

[0059] The first gate electrode layer G1 is disposed on the first gate insulating layer GI1, and includes the gate 32 of each transistor 30 and the first electrode plate 41 of the capacitor 40. The material of the first gate electrode layer G1 may include, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the first gate electrode layer G1 may include gold (Au), gold alloy, silver (Ag), silver alloy, aluminum (Al), aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SR0), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The first gate electrode layer G1 may have a single layer or multiple layers.

[0060] 7, the second gate insulating layer GI2 is disposed on the first gate electrode layer G1, and the second gate insulating layer GI2 can expose a portion of the top surface of the substrate SUB located in the bending region BA. The material of the second gate insulating layer GI2 may include silicon compounds, metal oxides, etc. For example, the material of the second gate insulating layer GI2 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon oxycarbide (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The second gate insulating layer GI2 may be formed as a single layer or multiple layers.

[0061] 7, the second gate electrode layer G2 is disposed on the second gate insulating layer GI2. The second gate electrode layer G2 may include the second electrode plate 42 of the capacitor 40. The material of the second gate electrode layer G2 may include, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the gate electrode may include gold (Au), gold alloy, silver (Ag), silver alloy, aluminum (Al), aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SR0), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The second gate electrode layer G2 may have a single layer or multiple layers.

[0062] 7, the interlayer insulating layer ILD is disposed on the second gate electrode layer G2, and the interlayer insulating layer ILD can expose a portion of the upper surface of the substrate SUB located in the bending region BA. The interlayer insulating layer ILD may be made of a material such as a silicon compound or a metal oxide. Specific examples of the silicon compound and metal oxide mentioned above are not described here.

[0063] The first source / drain conductive layer SD1 is disposed on the interlayer insulating layer ILD. The first source / drain conductive layer SD1 includes a source 33 and a drain 34 of each transistor included in the display area DA, with the source 33 electrically connected to the source connection portion and the drain 34 electrically connected to the drain connection portion. The first source / drain conductive layer SD1 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The first source / drain conductive layer SD1 may be a single layer or a multilayer made of a metal such as Mo / Al / Mo or Ti / Al / Ti. The transistor 30 shown in FIG. 7 includes a gate 32, a source 33, a drain 34, and an active layer 31. The transistor 30 shown in FIG. 7 may be the driving transistor Td of the pixel circuit shown in FIG. 6. However, if the pixel circuit uses a different circuit structure, the driving transistor Td does not necessarily have to be directly connected to the light-emitting element 50. In this case, the transistor shown in FIG. 7 does not necessarily have to correspond to the driving transistor Td. In addition, the first source / drain conductive layer SD1 may further include a first power supply line VDD and a second power supply line VSS.

[0064] The passivation layer PVX is disposed on the first source / drain conductive layer SD1, and the passivation layer PVX can expose a portion of the upper surface of the substrate SUB located at the bent portion BA. The material of the passivation layer PVX may include a silicon compound such as silicon oxide, silicon nitride, or silicon oxynitride.

[0065] 4, the organic insulating structure 20 includes a plurality of sub-insulating structures 21, each of which includes a first planarization layer PLN1, a second planarization layer PLN2, and a pixel-defining layer PDL. The first planarization layer PLN1, the second planarization layer PLN2, and the pixel-defining layer PDL each include a portion located in the display area DA and a portion located between the display area DA and the barrier 10. The second planarization layer PLN2 is located on one side of the first planarization layer PLN1 away from the substrate SUB. The pixel-defining layer PDL is located on one side of the second planarization layer PLN2 away from the substrate SUB. The first buffer layer BFL1, the semiconductor layer, the first gate insulating layer GI1, the first gate electrode layer G1, the second gate insulating layer GI2, the second gate electrode layer G2, the interlayer insulating layer ILD, the first source / drain conductive layer SD1, and the passivation layer PVX are all located between the first planarization layer PLN1 and the substrate SUB. The surface of the first planarization layer PLN1 away from the substrate SUB is essentially flat. The first planarization layer PLN1 is made of an organic insulating material, such as a resin-based material such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, or siloxane. The organic insulating material may also include an elastic material such as urethane or thermoplastic polyurethane (TPU).

[0066] For example, the thickness of each of the first planarization layer PLN1 and the second planarization layer PLN2 is 1 μm to 2 μm, for example, 1.6 μm. The thickness of the pixel definition layer PDL is 1.5 μm to 3 μm, for example, 2 μm.

[0067] As shown in FIG. 7 , the second source / drain conductive layer SD2 is disposed on the first planarization layer PLN1. The second source / drain conductive layer SD2 may be located on the relay electrode 60 in the display area DA. The relay electrode 60 is electrically connected to the drain 34 through a via hole penetrating the first planarization layer PLN1 and the passivation layer PVX. The relay electrode 60 is also electrically connected to the first electrode 51 of the light-emitting element 50 through a via hole penetrating the second planarization layer PLN2. The relay electrode 60 can improve the quality of the electrical connection by preventing via holes with relatively large diameters from being directly formed in the first planarization layer PLN1 and the second planarization layer PLN2. The second source / drain conductive layer SD2 may be made of a metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc., and may be a single layer or multilayer structure made of metals such as Mo / Al / Mo or Ti / Al / Ti. The material of the second source / drain conductive layer SD2 may be the same as or different from the material of the first source / drain conductive layer SD1.

[0068] As shown in FIG. 7, the second planarization layer PLN2 is disposed on the second source / drain conductive layer SD2. The second planarization layer PLN2 covers the relay electrodes. The surface of the second planarization layer PLN2 is essentially flat. It may have an essentially flat upper surface. The second planarization layer PLN2 is made of an organic insulating material, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, or other resin-based materials. The organic insulating material may also include an elastic material, such as urethane or thermoplastic polyurethane (TPU). The material of the second planarization layer PLN2 may be the same as or different from the material of the first planarization layer PLN1.

[0069] The first electrode layer is disposed on the second planarization layer PLN2, and the first electrode layer includes a plurality of first electrodes, which may be the anode of the light-emitting element 50. As shown in FIG. 7 , the light-emitting element 50 includes a first electrode 51, a light-emitting layer 53, and a second electrode 52, and the first electrode 51 is disposed on the second planarization layer PLN2. The first electrode 51 is electrically connected to the relay electrode 60 through a via hole that penetrates the second planarization layer PLN2 and is further electrically connected to the drain 34 of the transistor 30. The first electrode 51 is made of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. The first electrode 51 may be formed as a single layer or multiple layers.

[0070] The pixel-defining layer PDL is disposed on the second planarization layer PLN2. The pixel-defining layer PDL includes pixel openings that correspond to the pixel units, exposing portions of the corresponding first electrodes 51. The light-emitting layers 54 are disposed in the pixel openings, and include small-molecule organic materials or polymer organic materials. These may be fluorescent or phosphorescent materials, and may emit red, green, blue, or white light. The material of the pixel-defining layer PDL may include an organic insulating material such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin. A partition (not shown in FIG. 7) may be disposed on the pixel-defining layer PDL, and the material of the partition may be the same as that of the pixel-defining layer PDL.

[0071] The second electrode 52 is located on one side of the light-emitting layer 53 away from the substrate SUB. The second electrode 52 may be made of a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. In the embodiments of the present disclosure, the light-emitting element 50 may adopt a top-emitting structure or a bottom-emitting structure. When using a top-emitting structure, the first electrode 51 includes a conductive material with a light-reflecting function or includes a light-reflecting film, and the second electrode 52 includes a transparent or semi-transparent conductive material. When using a bottom-emitting structure, the second electrode 52 is made of a conductive material with a light-reflecting function or includes a light-reflecting film, and the first electrode 51 includes a transparent or semi-transparent conductive material. The second electrodes 52 of the light-emitting elements 50 of each pixel unit are connected together to form a second electrode layer.

[0072] In addition, the light-emitting element 50 may further include other film layers, for example, a hole injection layer and a hole transport layer located between the first electrode 51 and the light-emitting layer 53, and an electron transport layer and an electron injection layer located between the light-emitting layer 53 and the second electrode 52.

[0073] 4 and 7 , the display panel 100 further includes an encapsulation layer EPL disposed on the pixel-defining layer PDL. The encapsulation layer EPL covers the pixel-defining layer PDL and the light-emitting element 50 and is used to seal the light-emitting element 50, preventing water vapor and / or oxygen in the external environment from corroding the light-emitting element 50. In some embodiments, the encapsulation layer EPL includes a first inorganic encapsulation layer CVD1, a second inorganic encapsulation layer CVD2, and an organic encapsulation layer IJP. The second inorganic encapsulation layer CVD2 is located on one side of the first inorganic encapsulation layer CVD1 away from the substrate SUB, and the organic encapsulation layer IJP is located between the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2. Optionally, the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 extend to the peripheral region PA and cover the barrier 10. The organic encapsulation layer IJP extends to the peripheral region PA and is located within the area surrounded by the barrier 10. The first inorganic sealing layer CVD1 and the second inorganic sealing layer CVD2 can be made of dense inorganic materials such as silicon oxynitride (SiON), silicon oxide (SiOx), or silicon nitride (SiNx). The organic sealing layer IJP can be made of a polymer material containing a desiccant or a polymer material that blocks water vapor. For example, using a polymer resin can relieve stress in the first inorganic sealing layer CVD1 and the second inorganic sealing layer CVD2, and a water-absorbing material such as a desiccant can be included to absorb substances such as water and oxygen that have penetrated inside.

[0074] In one example, the thicknesses of the first inorganic sealing layer CVD1 and the second inorganic sealing layer CVD2 are each 0.5 μm to 1.5 μm. For example, the thickness of the first inorganic sealing layer CVD1 is 1.0 μm, and the thickness of the second inorganic sealing layer CVD2 is 0.6 μm. The thickness of the organic sealing layer IJP in the display area DA is 5 μm to 10 μm, for example, 8 μm, 7 μm, or 9 μm.

[0075] The second buffer layer BFL2 is disposed on the encapsulation layer EPL, located in the display area DA, and extends to the peripheral area PA to cover the encapsulation layer EPL. The second buffer layer BFL2 may be made of the same material as the first buffer layer BFL1, and its description will be omitted here. The touch electrode pattern is located on one side of the encapsulation layer EPL away from the substrate SUB. The bridge RX2 of the touch electrode pattern is disposed on the encapsulation layer EPL. The touch insulation layer TLD is located on one side of the encapsulation layer EPL away from the substrate SUB and covers the bridge RX2. The sensing electrode unit RX1 of the touch driving electrode TX and the touch sensing electrode RX is disposed on the touch insulation layer TLD. The driving electrode unit TX1 and the sensing electrode unit RX1 are both configured with good light transmittance to avoid affecting the display. For example, they may be made of a transparent conductive material (e.g., indium tin oxide) or a metal mesh structure.

[0076] The touch electrode pattern and the touch insulating layer TLD are both located on one side of the encapsulation layer EPL away from the substrate SUB, and the bridge RX2 of the touch electrode pattern is located between the touch insulating layer TLD and the encapsulation layer EPL, whereby the bridge RX2 and the first transmission part TL1 are located between the touch insulating layer TLD and the second buffer layer BFL2.

[0077] As shown in FIG. 4 , there is a gap between the first boundary of each sub-insulating structure 21 and the one-sided barrier structure, i.e., there is no contact between each sub-insulating structure 21 and the one-sided barrier structure. At this time, a groove is formed between the organic insulating structure 20 and the one-sided barrier structure. FIG. 5 is a conceptual diagram of a groove between the organic insulating structure and the one-sided barrier structure in some embodiments of the present disclosure. FIG. 5 is a cross-sectional view taken along line A-A' in FIG. 3 after the organic insulating structure 20 and the barrier 10 are formed but before the encapsulation layer EPL is formed. Combining the contents of FIGS. 4 and 5 , the orthogonal projection of the encapsulation layer EPL on the substrate SUB simultaneously covers the orthogonal projection of the organic insulating structure 20 on the substrate SUB, the orthogonal projection of the groove V1 on the substrate SUB, and the orthogonal projection of the one-sided barrier structure on the substrate SUB.

[0078] The overcoat layer OC is disposed on one side of the touch electrode pattern away from the substrate SUB. The overcoat layer OC extends from the display area DA to the peripheral area PA to protect the touch signal lines TL in the peripheral area PA. The material of the overcoat layer OC may include an inorganic insulating material or an organic insulating material.

[0079] In the embodiments of the present disclosure, a first gate insulating layer GI1, a second gate insulating layer GI2, a first buffer layer BFL1, and a second buffer layer BFL2 are disposed on the flexible substrate SUB, but in some examples, these layers may be deleted or added as needed, and the present invention is not specifically limited in this regard.

[0080] FIG. 8 is a cross-sectional view taken along line D-D' in FIG. 2. For the sake of clarity and conciseness, FIG. 8 only shows the cross-sectional structure of barrier 10 and the first and second inorganic encapsulating layers on barrier 10. Combining the contents of FIGS. 2, 4, and 8, the first barrier portion 111, the second barrier portion 112, the third barrier portion 113, and the fourth barrier portion 114 each include a first barrier layer 11a and a second barrier layer 11b located on the first barrier layer 11a. The first barrier layer 11a is located in the same layer as the second planarization layer PLN2 and is made of the same material. The second barrier layer 11b is located in the same layer as the pixel definition layer PDL and is made of the same material. As shown in FIG. 4, the third barrier portion 121 further includes a third barrier layer 11C located in the same layer as the first planarization layer PLN1 and is made of the same material. 8, the second barrier portion 112 includes a first barrier layer 11a, a second barrier layer 11b, and a fourth barrier layer 11d that is disposed in the same layer as the partition on the pixel defining layer PDL and is made of the same material. The fourth barrier portion 122 includes a first barrier layer 11a, a second barrier layer 11b, a third barrier layer 11c, and a fourth barrier layer 11d.

[0081] In the embodiments of the present disclosure, "disposed in the same layer" refers to the two structures being formed from the same material layer through a patterning process, and therefore being in the same layer in terms of stacking relationship. However, this does not necessarily mean that the distance between the two structures and the substrate SUB is the same. Also, as shown in Figures 5 and 8, the first inorganic sealing layer CVD1 and the second inorganic sealing layer CVD2 in the sealing layer EPL extend over the first barrier 11 and the second barrier 12, respectively.

[0082] In some embodiments, the peripheral area PA of the substrate SUB includes a first fanout area FA1 located between the display area DA and the bending area BA. Data connection lines are connected to the data lines DL and then extend through the first fanout area FA1 and the bending area BA to the pad area WA. The substrate SUB further includes a second fanout area FA2 located between the bending area BA and the pad area WA and adjacent to the bending area BA. That is, the second fanout area FA2 is adjacent to the bending area BA and directly connected to each other, with no other areas between the two areas. A test area DTA, a control circuit area CCA, a third fanout area FA3, and an integrated circuit area IC are further disposed between the second fanout area and the pad area WA of the substrate SUB. In at least one example, the test area DTA is configured to be connected to an external test device to detect breaks in the screen, the bending area BA, etc. In at least one example, the control circuit area CCA includes a selector MUX for switching between input circuits and output circuits.

[0083] Another embodiment of the present disclosure further provides a display panel including a substrate, a barrier, an organic insulating structure, a touch electrode pattern, and a touch signal line. The substrate includes a display area, a peripheral area surrounding the display area, and a pad area located on one side of the peripheral area away from the display area. The barrier is disposed on the substrate, located in the peripheral area, and surrounding the display area, and includes a one-sided barrier structure located between the display area and the pad area. The organic insulating structure is disposed on the substrate, with a portion located in the display area and another portion located in the peripheral area.

[0084] Fig. 9 is a cross-sectional view of some other embodiments of the present disclosure taken along line A-A' in Fig. 3, Fig. 10 is a first structural diagram of the organic insulating structure in Fig. 9, and Fig. 11 is a second structural diagram of the organic insulating structure in Fig. 9. Combining the contents of Fig. 2 and Figs. 9 to 11, the organic insulating structure 20 has a bottom surface BS facing the substrate SUB, a top surface TS opposite to the bottom surface BS, and a first side surface LS connected between the bottom surface BS and the top surface TS and facing the one-sided barrier structure, and the first side surface LS is an inclined surface with an inclination angle of 0 to 40°C.

[0085] Note that the "inclined surface" here refers to a surface that gradually approaches the surface of the display area DA in a direction away from the substrate SUB. The inclined surface may be an inclined plane (e.g., as shown in FIG. 10) or an inclined arc (e.g., as shown in FIG. 11). When the inclined surface is a plane, the inclination angle refers to the angle θ1 between the inclined surface and the bottom surface BS of the organic insulating structure 20. When the inclined surface is an arc, the inclination angle refers to the maximum angle θ2 between the tangent to the arc and the bottom surface BS of the organic insulating structure 20. Note that the inclined surface is not only located in the Q1 region, but also extends from the left end to the right end of the Q region.

[0086] 2 and 9 , the touch electrode patterns (i.e., FIG. 2 includes patterns of the touch driving electrodes TX and the touch sensing electrodes RX) are disposed on one side of the organic insulating structure 20 away from the substrate. The touch signal lines TL are disposed on one side of the organic insulating structure 20 away from the substrate, with one end electrically connected to the touch electrode patterns and the other end connected to the pad area WA. The orthogonal projection of the part of the touch signal line TL in the peripheral area PA on the substrate SUB passes through the orthogonal projection of the inclined surface on the substrate SUB.

[0087] In some embodiments, the inclination angle of the inclined surface is 25 to 35°C, which reduces the amount of conductive material remaining and prevents the outer frame of the display product from being too wide, for example, 28°C, 29°C, 30°C, 31°C, or 32°C.

[0088] 9, the organic insulating structure 20 includes a plurality of sub-insulating structures 21 arranged in a stack, each of which includes a first planarization layer PLN1, a second planarization layer PLN2, and a pixel-defining layer PDL. The first planarization layer PLN1 is disposed on a substrate SUB. The second planarization layer PLN2 is located on one side of the first planarization layer PLN1 away from the substrate SUB. The pixel-defining layer PDL is located on one side of the second planarization layer PLN2 away from the substrate SUB.

[0089] An encapsulation layer EPL, a second buffer layer BFL2, and a touch insulating layer TLD are further disposed on the organic insulating structure 20. The encapsulation layer EPL includes a first inorganic encapsulation layer CVD1, a second inorganic encapsulation layer CVD2, and an organic encapsulation layer IJP. The second inorganic encapsulation layer CVD2 is located on one side of the first inorganic encapsulation layer CVD1 away from the substrate SUB, and the organic encapsulation layer IJP is located between the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2.

[0090] In this embodiment, the arrangement of the touch insulating layer TLD and the touch signal line TL can refer to the description of the above embodiment. As shown in FIGS. 2 and 7 , the touch electrode pattern includes touch driving electrodes TX and touch sensing electrodes RX, and the touch driving electrodes TX and the touch sensing electrodes RX are arranged to cross each other. The intersections of the touch driving electrodes TX and the touch sensing electrodes RX are insulated and separated by the touch insulating layer TLD. The touch driving electrodes TX and the touch sensing electrodes RX are both electrically connected to one touch signal line TL. The touch signal line TL includes a first transmission part TL1 located between the touch insulating layer TLD and the encapsulation layer EPL and a second transmission part TL2 located on one side of the touch insulating layer TLD away from the substrate SUB. The second transmission part TL2 is electrically connected to the first transmission part TL1 through a via hole penetrating the touch insulating layer TLD. The touch electrode pattern and the touch signal line TL are located on one side of the encapsulation layer EPL away from the substrate SUB.

[0091] There is a gap between the first side surface LS and the one-sided barrier structure, for example, there is a gap between one end of the first side surface LS close to the substrate SUB and one end remote from the substrate SUB and the one-sided barrier structure. A groove is formed between the organic insulating structure 20 and the one-sided barrier structure, and the orthogonal projection of the encapsulation layer EPL on the substrate SUB simultaneously covers the orthogonal projection of the organic insulating structure 20 on the substrate SUB, the orthogonal projection of the groove on the substrate SUB, and the orthogonal projection of the one-sided barrier structure on the substrate SUB, and the one-sided barrier structure is located between the substrate SUB and the encapsulation layer EPL.

[0092] The display area DA includes a plurality of pixel units, each of which has a light-emitting element 50 disposed therein. The display panel 100 further includes a second power line VSS electrically connected to the light-emitting element 50, wherein the second power line VSS is located between the organic insulating structure 20 and the substrate SUB, and the orthogonal projection of the first side LS on the substrate SUB overlaps with the orthogonal projection of the second power line VSS on the substrate SUB.

[0093] The barrier 10 includes a first barrier 11 located in the peripheral area PA and surrounding the display area DA, and a second barrier 12 located in the peripheral area PA and surrounding the first barrier 11. The specific structures of the first barrier 11 and the second barrier 12 can be referred to in the above embodiment, and therefore, a description thereof will be omitted here. On the substrate SUB, there are disposed structures such as a first buffer layer BFL1, a semiconductor layer, a first gate insulating layer GI1, a first gate electrode layer G1, a second gate insulating layer GI2, an interlayer insulating layer ILD, a first source / drain conductive layer SD1, a passivation layer PVX, and a second source / drain conductive layer SD2. The structure and position of each film layer can be referred to in the above embodiment, and therefore, a description thereof will be omitted here. The substrate SUB in this embodiment is a flexible substrate, and further includes a bending area BA located between the peripheral area PA and the pad area WA, as well as other areas such as a test area DTA and a control circuit area CCA. The positional relationship between each area can be determined by referring to the explanation in the above embodiment, and the explanation will be omitted here.

[0094] In the display panel of this embodiment, the first side of the organic insulating structure 20 is an inclined surface with a small inclination, which can reduce the amount of conductive material remaining when the touch signal lines are subsequently manufactured through an etching process, thereby reducing or preventing the occurrence of short circuits between the touch signal lines TL.

[0095] An embodiment of the present disclosure provides a display panel including a substrate, a barrier, an organic insulating structure, a touch electrode pattern, and a touch signal line. The substrate includes a display area, a peripheral area surrounding the display area, and a pad area located on one side of the peripheral area away from the display area. The barrier is disposed on the substrate, located in the peripheral area, and surrounding the display area, and includes a one-sided barrier structure located between the display area and the pad area. The organic insulating structure is disposed on the substrate and includes a plurality of stacked sub-insulating structures, with a portion of each sub-insulating structure located in the display area and another portion located in the peripheral area. Each of the sub-insulating structures has a first boundary located between the display area and the one-sided barrier structure. Except for the sub-insulating structure farthest from a substrate SUB, each of the remaining sub-insulating structures includes an extension portion, and for any two adjacent sub-insulating structures, the extension portion of the sub-insulating structure closest to the substrate SUB is located between the first boundary of the sub-insulating structure farther from the substrate SUB and the one-sided barrier structure. a touch electrode pattern disposed on one side of the organic insulating structure away from the substrate and located in the display area, a touch signal line disposed on one side of the organic insulating structure away from the substrate, one end electrically connected to the touch electrode pattern and the other end connected to the pad area, and an orthogonal projection of a portion of the touch signal line in the peripheral area on the substrate overlaps with an orthogonal projection of an extension portion of each of the sub-insulation structures on the substrate.

[0096] The sub-insulating structure having the extension portion is formed by performing a patterning process on the organic material layer using a dual-tone mask plate, and when performing the patterning process, the area where the extension portion is formed corresponds to the semi-transparent area of ​​the dual-tone mask plate.

[0097] In some embodiments, the plurality of sub-insulating structures of the organic insulating structure include a first planarization layer, a second planarization layer, and a pixel-defining layer, wherein the first planarization layer is disposed on the substrate, the second planarization layer is located on one side of the first planarization layer away from the substrate, and the pixel-defining layer is located on one side of the second planarization layer away from the substrate.

[0098] 12 to 14 are schematic diagrams illustrating a manufacturing process of a sub-insulating structure having an extension portion according to some embodiments of the present disclosure. The manufacturing process will be described below using a sub-insulating structure having an extension portion as an example. The sub-insulating structure may be a first planarization layer or a second planarization layer.

[0099] As shown in FIG. 12, an organic insulating material layer 210 is formed, where the organic insulating material layer 210 is a light-sensitive organic material layer, for example, a positive photoresist.

[0100] As shown in FIG. 13, a dual-tone mask plate M is used to expose a photoresist layer. The dual-tone mask plate M can be a gray-tone mask or a half-tone mask. The dual-tone mask plate M includes a light-transmitting region M1, a light-opaque region M3, and a semi-transmitting region M2, with the semi-transmitting region M2 having a lower light transmittance than the light-transmitting region M1. For example, assuming that the organic insulating material layer 210 is a positive photoresist, during exposure, the semi-transmitting region M2 of the dual-tone mask plate M corresponds to the region where the extension portion is to be formed, the light-transmitting region M1 of the dual-tone mask plate M corresponds to the region where the organic insulating material layer 210 is to be completely removed, and the light-opaque region M3 of the dual-tone mask plate M corresponds to the remaining region. After exposure, the portions of the organic insulating material layer 210 corresponding to the light-opaque regions are unexposed, the portions of the organic insulating material layer 210 corresponding to the light-transmitting regions are fully exposed, and the portions of the organic insulating material layer 210 corresponding to the semi-transmitting regions are partially exposed.

[0101] 14, the organic insulating material layer 210 is developed, whereby the portions of the organic insulating material layer 210 corresponding to the light-transmitting regions M1 are entirely removed, the portions corresponding to the partially light-transmitting regions M2 are partially removed, and the portions corresponding to the light-opaque regions M3 are completely left, thereby forming a pattern that is the sub-insulating structure 21. The portion of the sub-insulating structure 21 that corresponds to the partially light-transmitting region M2 is the extension 21a, and the surface of the extension 21a is a gently inclined surface.

[0102] In the patterning step, a negative photoresist can also be used, and in this case, the pattern of the mask plate used is complementary to the dual-tone mask plate M.

[0103] In the embodiment of the present disclosure, the sub-insulating structure 21 having the extension portion 21a is fabricated by performing a patterning process on the organic material layer 210 using a dual-tone mask plate. During exposure, the region where the extension portion 21a is formed corresponds to the semi-transparent region M2 of the dual-tone mask plate M. As a result, the formed extension portion 21a can have an inclined surface, and the entire side surface of the organic insulating structure 20 can be gentle. This can reduce the amount of conductive residue when forming touch signal lines through a subsequent etching process, and reduce or prevent the occurrence of short circuits between touch signal lines.

[0104] In this embodiment, the structure of the barrier 20, the structure and material of the pixel definition layer PDL, the structure and material of the first planarization layer PLN1, and the structure and material of the second planarization layer PLN2 can all be referred to in the above embodiments, and the description thereof will be omitted here.

[0105] In this embodiment, a sealing layer and a touch insulating layer are further disposed on the organic insulating structure. A light-emitting element may be further disposed in the display area of ​​the substrate, and the light-emitting element is connected to a second power line. The specific structure and material of the sealing layer, the arrangement method and material of the touch insulating layer, the structure and material of the light-emitting element, and the arrangement method of the second power line and the touch signal line can all be referred to in the descriptions of the above embodiments, and further description thereof will be omitted.

[0106] An embodiment of the present disclosure provides a display device including the display panel according to any one of the above embodiments, which may be any product or component having a display function, such as an OLED panel, a mobile phone, a tablet, a television, a display, a laptop computer, a digital photo frame, or a navigation system.

[0107] The above embodiments are merely exemplary implementations used to explain the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art can make various modifications and improvements without departing from the spirit and essential circumstances of the present disclosure, and the claims of the present disclosure also include such modifications and improvements. [Explanation of symbols]

[0108] 10 Barrier 11 First Barrier 11a First barrier layer 11b Second barrier layer 11c Third barrier layer 11d Fourth barrier layer 12 Second Barrier 20 Organic insulating structure 21 Sub-insulation structure 21a Extension part 30 transistors 31 Active layer Gate 32 33 Source 34 Drain 40 Capacitor 41 1st electrode plate 42 Second electrode plate 50 Light-emitting element 51 1st electrode 52 2nd electrode 53 Light-emitting layer 100 Display Panel 111 First Barrier Section 112 Second Barrier Section 121 Third Barrier Section 122 4th Barrier Section 210 Organic insulating material layer

Claims

1. a substrate including a display area, a peripheral area surrounding the display area, and a pad area located on one side of the peripheral area away from the display area; At least one barrier disposed on the substrate, located in the peripheral region and surrounding the display region, the barrier including a one-sided barrier structure located between the display region and the pad region; an organic insulating structure disposed on the substrate, the organic insulating structure including a plurality of sub-insulating structures arranged in a stack, each sub-insulating structure having a first boundary located between the display area and the one-sided barrier structure, and for at least two adjacent sub-insulating structures, the first boundary of the sub-insulating structure located away from the substrate is closer to the display area than the first boundary of the sub-insulating structure located closer to the substrate; a touch electrode pattern disposed on one side of the organic insulating structure away from the substrate; a touch signal line disposed on one side of the organic insulating structure away from the substrate, one end electrically connected to the touch electrode pattern and the other end connected to the pad area, wherein an orthogonal projection of a portion of the touch signal line in the peripheral area on the substrate intersects with a first boundary of each of the sub-insulating structures; a space between the first boundary of the sub-insulation structure and the one-sided barrier structure; Display panel.

2. The distance between the first boundaries of at least two adjacent sub-insulation structures is 20 μm or more. The display panel according to claim 1 .

3. The distance between the first boundaries of any two adjacent sub-insulation structures is between 25 μm and 60 μm. The display panel according to claim 2 .

4. The plurality of sub-insulating structures of the organic insulating structure include: a first planarization layer disposed on the substrate; a second planarization layer positioned on one side of the first planarization layer away from the substrate; At least two of the pixel-defining layers are located on one side of the second planarization layer away from the substrate. The display panel according to claim 1 .

5. further comprising an encapsulation layer located on one side of the organic insulating structure away from the substrate; The touch electrode pattern and the touch signal line are both located on one side of the encapsulation layer away from the substrate. The display panel according to claim 1 .

6. a groove is formed between the organic insulating structure and the one-sided barrier structure, and an orthogonal projection of the sealing layer on the substrate simultaneously covers an orthogonal projection of the organic insulating structure on the substrate, an orthogonal projection of the groove on the substrate, and an orthogonal projection of the one-sided barrier structure on the substrate, and the one-sided barrier structure is located between the substrate and the sealing layer; The display panel according to claim 5 .

7. a touch insulating layer disposed on one side of the encapsulation layer away from the substrate; the touch electrode pattern includes a plurality of touch driving electrodes and a plurality of touch sensing electrodes, the touch driving electrodes and the touch sensing electrodes are arranged to cross each other, the intersections of the touch driving electrodes and the touch sensing electrodes are insulated and separated by the touch insulating layer, and each of the touch driving electrodes and each of the touch sensing electrodes is connected to one of the touch signal lines, the touch drive electrode includes a plurality of drive electrode units arranged along a first direction and a connection portion connected between each two adjacent drive electrode units; The touch sensing electrode includes a plurality of sensing electrode units arranged along a second direction and a bridge connected between each two adjacent sensing electrode units; the first direction and the second direction intersect, the driving electrode unit, the connection part and the sensing electrode unit are all located on one side of the touch insulating layer away from the substrate and are located in the same layer, and the bridge is located between the touch insulating layer and the encapsulation layer; The touch signal line includes a first transmission part located between the touch insulating layer and the encapsulation layer and a second transmission part located on one side of the touch insulating layer away from the encapsulation layer, and the second transmission part is electrically connected to the first transmission part through a via hole penetrating the touch insulating layer. The display panel according to claim 5 .

8. the display panel, wherein the display area has a plurality of pixel units, each pixel unit having a light-emitting element disposed therein, and further includes a power supply line electrically connected to the light-emitting element, the power supply line being located between the organic insulating structure and the substrate, and an orthogonal projection of the power supply line on the substrate overlaps with an orthogonal projection of the first boundary on the substrate; The display panel according to claim 1 .

9. a first buffer layer disposed on the substrate; a semiconductor layer disposed between the first buffer layer and the first planarization layer; a first gate insulating layer disposed between the semiconductor layer and the first planarization layer; a first gate electrode layer disposed between the first gate insulating layer and the first planarization layer; a second gate insulating layer disposed between the first gate electrode layer and the first planarization layer; a second gate electrode layer disposed between the second gate insulating layer and the first planarization layer; an interlayer insulating layer disposed between the second gate electrode layer and the first planarization layer; a first source / drain conductive layer disposed between the interlayer insulating layer and the first planarization layer; a second source / drain conductive layer disposed between the first planarization layer and the second planarization layer; a first electrode layer disposed between the second planarization layer and the pixel definition layer, the first electrode layer including a plurality of first electrodes, the pixel definition layer including pixel openings corresponding one-to-one to the first electrodes; a light-emitting layer disposed within the pixel opening; a second electrode layer disposed on one side of the light emitting layer away from the substrate; a sealing layer disposed on one side of the light-emitting layer away from the substrate; a second buffer layer disposed on one side of the encapsulation layer away from the substrate; The touch electrode pattern and the touch signal line are disposed on one side of the second buffer layer away from the substrate. The display panel according to claim 4 .

10. a substrate including a display area, a peripheral area surrounding the display area, and a pad area located on one side of the peripheral area away from the display area; At least one barrier disposed on the substrate, located in the peripheral region and surrounding the display region, the barrier including a one-sided barrier structure located between the display region and the pad region; an organic insulating structure disposed on the substrate, a portion of which is located in the display region and another portion of which is located in the peripheral region, the organic insulating structure having a bottom surface facing the substrate, a top surface opposite to the bottom surface, and a first side surface located between the bottom surface and the top surface and facing the one-sided barrier structure, wherein an orthogonal projection of the top surface on the substrate is within a range of an orthogonal projection of the bottom surface on the substrate, and an angle between the bottom surface and the first side surface is 0 to 40 degrees; a touch electrode pattern disposed on one side of the organic insulating structure away from the substrate; a touch signal line disposed on one side of the organic insulating structure away from the substrate, one end electrically connected to the touch electrode pattern and the other end connected to the pad area, wherein an orthogonal projection of a portion of the peripheral area on the substrate passes through an orthogonal projection of the first side surface on the substrate; Including, a space between the first side and the one-sided barrier structure; Display panel.

11. The angle between the first side surface and the bottom surface is 25 to 35 degrees. The display panel according to claim 10.

12. The plurality of sub-insulating structures of the organic insulating structure include: a first planarization layer disposed on the substrate; a second planarization layer positioned on one side of the first planarization layer away from the substrate; At least two of the pixel-defining layers are located on one side of the second planarization layer away from the substrate. The display panel according to claim 10.

13. further comprising an encapsulation layer disposed on one side of the organic insulating structure away from the substrate; the touch electrode pattern and the touch signal line are both located on one side of the encapsulation layer away from the substrate; a groove is formed between the organic insulating structure and the one-sided barrier structure, and an orthogonal projection of the sealing layer on the substrate simultaneously covers an orthogonal projection of the organic insulating structure on the substrate, an orthogonal projection of the groove on the substrate, and an orthogonal projection of the one-sided barrier structure on the substrate, and the one-sided barrier structure is located between the substrate and the sealing layer; The display panel according to claim 10.

14. a touch insulating layer disposed on one side of the encapsulation layer away from the substrate; the touch electrode pattern includes a plurality of touch driving electrodes and a plurality of touch sensing electrodes, the touch driving electrodes and the touch sensing electrodes are arranged to cross each other, the intersections of the touch driving electrodes and the touch sensing electrodes are insulated and separated by the touch insulating layer, and each of the touch driving electrodes and each of the touch sensing electrodes is connected to one of the touch signal lines, the touch drive electrode includes a plurality of drive electrode units arranged along a first direction and a connection portion connected between each two adjacent drive electrode units; The touch sensing electrode includes a plurality of sensing electrode units arranged along a second direction and a bridge connected between each two adjacent sensing electrode units; the first direction and the second direction intersect, the driving electrode unit, the connection part and the sensing electrode unit are all located on one side of the touch insulating layer away from the substrate and are located in the same layer, and the bridge is located between the touch insulating layer and the encapsulation layer; The touch signal line includes a first transmission part located between the touch insulating layer and the encapsulation layer and a second transmission part located on one side of the touch insulating layer away from the encapsulation layer, and the second transmission part is electrically connected to the first transmission part through a via hole penetrating the touch insulating layer. The display panel according to claim 13.

15. the display panel, wherein the display area has a plurality of pixel units, each pixel unit having a light-emitting element disposed therein, and further includes a power supply line electrically connected to the light-emitting element, the power supply line being located between the organic insulating structure and the substrate, and an orthogonal projection of the power supply line on the substrate overlaps with an orthogonal projection of the first side surface on the substrate; The display panel according to claim 10.

16. a first buffer layer disposed on the substrate; a semiconductor layer disposed between the first buffer layer and the first planarization layer; a first gate insulating layer disposed between the semiconductor layer and the first planarization layer; a first gate electrode layer disposed between the first gate insulating layer and the first planarization layer; a second gate insulating layer disposed between the first gate electrode layer and the first planarization layer; a second gate electrode layer disposed between the second gate insulating layer and the first planarization layer; an interlayer insulating layer disposed between the second gate electrode layer and the first planarization layer; a first source / drain conductive layer disposed between the interlayer insulating layer and the first planarization layer; a second source / drain conductive layer disposed between the first planarization layer and the second planarization layer; a first electrode layer disposed between the second planarization layer and the pixel definition layer, the first electrode layer including a plurality of first electrodes, the pixel definition layer including pixel openings corresponding one-to-one to the first electrodes; a light-emitting layer disposed within the pixel opening; a second electrode layer disposed on one side of the light emitting layer away from the substrate; a sealing layer disposed on one side of the light-emitting layer away from the substrate; a second buffer layer disposed on one side of the encapsulation layer away from the substrate. The display panel according to claim 12.

17. a substrate including a display area, a peripheral area surrounding the display area, and a pad area located on one side of the peripheral area away from the display area; At least one barrier disposed on the substrate, located in the peripheral region and surrounding the display region, the barrier including a one-sided barrier structure located between the display region and the pad region; an organic insulating structure disposed on the substrate, a portion of which is located in the display region and another portion of which is located in the peripheral region, the organic insulating structure having a step structure on a side close to the one-sided barrier structure, the step structure including at least two steps, the height of the at least two steps gradually decreasing in a direction from the display region toward the peripheral region; a touch electrode pattern disposed on one side of the organic insulating structure away from the substrate; a touch signal line disposed on one side of the organic insulating structure away from the substrate, one end electrically connected to the touch electrode pattern and the other end connected to the pad area, wherein an orthogonal projection of a portion of the touch signal line in the peripheral area on the substrate overlaps with an orthogonal projection of the step structure of each of the organic insulating structures on the substrate. Display panel.

18. The distance between the boundaries of at least two adjacent steps is 20 μm or more. The display panel according to claim 17.

19. The plurality of sub-insulating structures of the organic insulating structure include: a first planarization layer disposed on the substrate; a second planarization layer positioned on one side of the first planarization layer away from the substrate; At least two of the pixel-defining layers are located on one side of the second planarization layer away from the substrate. The display panel according to claim 17.

20. A display device comprising the display panel according to any one of claims 1 to 19.

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