Display device

Abstract

To provide a display device capable of realizing an improvement in a yield or improvement in reliability.SOLUTION: A display device according to an embodiment includes: a plurality of sub-pixels each including a wiring that supplies a signal or a voltage, a display element including an organic layer that emits light in response to application of a voltage, and a pixel circuit that drives the display element; and a dummy sub-pixel including the display element and a dummy pixel circuit. The pixel circuit and the dummy pixel circuit of the plurality of sub-pixels constitute a circuit column arranged along the wiring. The dummy pixel circuit is located at an end of the circuit column. In each of the plurality of sub-pixels, an electrical path from the wiring to the display element via the pixel circuit is formed. In each of the dummy sub-pixels, at least a part of an electrical path from the wiring to the display element via the dummy pixel circuit is cut off.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have come into practical use. For these types of display devices, technology that can improve yield and reliability is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device that can achieve an improvement in yield or reliability. [Means for solving the problem]

[0005] A display device according to one embodiment includes a plurality of sub-pixels, each of which includes a wiring for supplying a signal or voltage, a display element including an organic layer that emits light in response to the application of a voltage, and a pixel circuit for driving the display element; and a dummy sub-pixel including the display element and a dummy pixel circuit. The pixel circuits and the dummy pixel circuits of the plurality of sub-pixels form a circuit row aligned along the wiring. The dummy pixel circuit is located at an end of the circuit row. In each of the plurality of sub-pixels, an electrical path is formed from the wiring to the display element via the pixel circuit. In the dummy sub-pixel, at least a portion of the electrical path from the wiring to the display element via the dummy pixel circuit is cut off. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of a configuration applicable to a pixel circuit. [Figure 3] FIG. 3 is a schematic plan view showing an example of an arrangement of three pixel circuits arranged for one pixel. [Figure 4] FIG. 4 is a schematic plan view showing an example of the layout of display elements of three sub-pixels included in one pixel. [Figure 5] FIG. 5 is a schematic cross-sectional view of the display device taken along line VV in FIG. [Figure 6] FIG. 6 is a schematic plan view showing the vicinity of the boundary between the display region and the peripheral region. [Figure 7] FIG. 7 is a schematic plan view showing a configuration applicable to the dummy pixel. [Figure 8] FIG. 8 is a schematic plan view showing an example of an arrangement of three dummy pixel circuits arranged for one dummy pixel. [Figure 9] FIG. 9 is a circuit diagram showing an example of a configuration applicable to a dummy pixel circuit. [Figure 10]FIG. 10 is a schematic plan view showing an example of a configuration applicable to pixel circuits and dummy pixel circuits arranged near the boundary between the display region and the peripheral region. [Figure 11] FIG. 11 is an enlarged plan view of the pixel circuit shown in FIG. [Figure 12] FIG. 12 is an enlarged plan view of the dummy pixel circuit shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0008] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0009] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0010] 1 is a diagram showing an example of the configuration of a display device DSP according to one embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0011] In this embodiment, the shape of the substrate 10 and the display area DA in a plan view is circular (perfect circle). However, the shape of the substrate 10 and the display area DA in a plan view is not limited to this example and may be other shapes such as rectangular, square, or elliptical.

[0012] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a green subpixel SP1, a red subpixel SP2, and a blue subpixel SP3. However, the pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0013] The display device DSP further includes a terminal section T arranged in the peripheral area SA. To the terminal section T, for example, a flexible circuit board is connected that supplies voltages and signals for driving the display device DSP.

[0014] 2 is a circuit diagram showing an example of a configuration applicable to the pixel circuit PC included in each of the subpixels SP (SP1, SP2, SP3). The pixel circuit PC shown in this diagram includes three thin-film transistors TR1, TR2, TR3 and one storage capacitor Cst. The display device DSP also includes a signal line SL, a power supply line PL, a reset line RST, and scan lines GL1 and GL2 as examples of wiring for supplying signals or voltages to the pixel circuit PC.

[0015] In the following description, one of the source-drain electrodes of each of the thin-film transistors TR1, TR2, and TR3 is referred to as the first electrode, and the other as the second electrode. Similarly, one of the electrodes of the storage capacitor Cst is referred to as the first electrode, and the other as the second electrode.

[0016] The gate electrode of the thin film transistor TR1 is connected to a scanning line GL1 that supplies a scanning signal SG, and the gate electrode of the thin film transistor TR2 is connected to a scanning line GL2 that supplies a reset signal RG.

[0017] A first electrode of the thin-film transistor TR1 is connected to a signal line SL that supplies a video signal Sdata. The video signal Sdata is a signal that is written to the sub-pixel SP to display an image. A first electrode of the thin-film transistor TR2 is connected to a power line PL that supplies a drive voltage VDDEL. A first electrode of the thin-film transistor TR3 is connected to a reset line RST that supplies a reset voltage Vrst.

[0018] The second electrode of the thin-film transistor TR1 is connected to the gate electrode of the thin-film transistor TR2 and the first electrode of the storage capacitor Cst. The second electrode of the thin-film transistor TR2 is connected to the anode of the display element DE included in the subpixel SP and the second electrode of the storage capacitor Cst. Similarly, the second electrode of the thin-film transistor TR3 is connected to the anode of the display element DE and the second electrode of the storage capacitor Cst. A voltage VSSEL is supplied to the cathode of the display element DE.

[0019] The configuration of the pixel circuit PC is not limited to the example shown in Fig. 2. For example, the pixel circuit PC may include four or more transistors. The pixel circuit PC may also include a plurality of storage capacitors Cst.

[0020] 3 is a schematic plan view showing an example of the arrangement of pixel circuits PC arranged for one pixel PX. In the example of Fig. 3, pixel circuits PC (PC1, PC2, PC3) of subpixels SP1, SP2, SP3 are aligned in the X direction.

[0021] The pixel circuits PC1, PC2, and PC3 are connected to the display elements DE of the subpixels SP1, SP2, and SP3 via contact holes CH1, CH2, and CH3, respectively, provided in the organic insulating layer 12 (described later). In the example of Fig. 3, the contact holes CH1, CH2, and CH3 are aligned in the X direction. However, the arrangement of the contact holes CH1, CH2, and CH3 is not limited to this example.

[0022] 4 is a schematic plan view showing an example of the layout of the display elements DE (DE1, DE2, DE3) of the subpixels SP1, SP2, SP3. In the example of FIG. 4, the display elements DE1 and DE2 are aligned with the display element DE3 in the X direction. Furthermore, the display elements DE1 and DE2 are aligned with each other in the Y direction.

[0023] When the display elements DE1, DE2, and DE3 are laid out in this manner, the display area DA is formed with a column in which the display elements DE1 and DE2 are alternately arranged in the Y direction and a column in which multiple display elements DE3 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the display elements DE1, DE2, and DE3 is not limited to the example in FIG. 4.

[0024] A rib layer 5 is disposed in the display area DA. The rib layer 5 has a pixel aperture AP1 surrounding the display element DE1, a pixel aperture AP2 surrounding the display element DE2, and a pixel aperture AP3 surrounding the display element DE3.

[0025] 4, pixel aperture AP2 is smaller than pixel aperture AP1, and pixel aperture AP3 is larger than pixel aperture AP1. That is, among subpixels SP1, SP2, and SP3, subpixel SP3 has the largest aperture ratio and subpixel SP2 has the smallest aperture ratio. However, the relationship between the aperture ratios of subpixels SP1, SP2, and SP3 is not limited to this example.

[0026] Display element DE1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Display element DE2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Display element DE3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0027] A lattice-shaped partition wall 6 is disposed on the rib layer 5. The partition wall 6 entirely overlaps the rib layer 5 and has the same planar shape as the rib layer 5. That is, the partition wall 6 has openings surrounding the display elements DE1, DE2, and DE3. The partition wall 6 serves as wiring for supplying a cathode voltage to the upper electrodes UE1, UE2, and UE3. The contact holes CH1, CH2, and CH3 described above overlap the rib layer 5 and the partition wall 6, respectively.

[0028] 5 is a schematic cross-sectional view of the display device DSP taken along line VV in FIG. 4. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits PC (PC1, PC2, PC3), signal lines SL, reset lines RST, power supply lines PL, and scanning lines GL1 and GL2 shown in FIG. 2. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0029] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. Ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. The lower electrodes LE1, LE2, and LE3 are connected to pixel circuits PC1, PC2, and PC3 of the circuit layer 11 through contact holes CH1, CH2, and CH3 (see FIGS. 3 and 4) provided in the organic insulating layer 12, respectively.

[0030] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhanging shape.

[0031] In the example of FIG. 5, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Also, in the example of FIG. 5, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0032] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3.

[0033] The upper electrodes UE1, UE2, UE3 are in contact with the lower portion 61 of the partition wall 6. Specifically, the upper electrodes UE1, UE2, UE3 cover the bottom layer 63 protruding from the side surface of the shaft layer 64. The upper electrodes UE1, UE2, UE3 may further cover at least a portion of the side surface of the shaft layer 64.

[0034] Display element DE1 includes a cap layer CP1 disposed on an upper electrode UE1. Display element DE2 includes a cap layer CP2 disposed on an upper electrode UE2. Display element DE3 includes a cap layer CP3 disposed on an upper electrode UE3. The cap layers CP1, CP2, and CP3 function as optical adjustment layers that improve the extraction efficiency of light emitted from organic layers OR1, OR2, and OR3, respectively.

[0035] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0036] A portion of the laminated film FL1 is located on the upper portion 62. This portion is separated from a portion of the laminated film FL1 that is located around the partition wall 6 (a portion that constitutes the display element DE1). Similarly, a portion of the laminated film FL2 is located on the upper portion 62, and this portion is separated from a portion of the laminated film FL2 that is located around the partition wall 6 (a portion that constitutes the display element DE2). Furthermore, a portion of the laminated film FL3 is located on the upper portion 62, and this portion is separated from a portion of the laminated film FL3 that is located around the partition wall 6 (a portion that constitutes the display element DE3). Note that at least one of the laminated films FL1, FL2, and FL3 does not necessarily have to be disposed on the partition wall 6.

[0037] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3.

[0038] 5, the stacked film FL1 and the sealing layer SE11 on the partition wall 6 between the display elements DE1 and DE3 are spaced apart from the stacked film FL3 and the sealing layer SE13 on the partition wall 6. In addition, the stacked film FL2 and the sealing layer SE12 on the partition wall 6 between the display elements DE2 and DE3 are spaced apart from the stacked film FL3 and the sealing layer SE13 on the partition wall 6.

[0039] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0040] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0041] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0042] The lower electrodes LE1, LE2, and LE3 each include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0043] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). In this embodiment, the lower electrodes LE1, LE2, and LE3 correspond to anodes, and the upper electrodes UE1, UE2, and UE3 correspond to cathodes.

[0044] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0045] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0046] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0047] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. Examples of the metal material that can be used to form the lower layer include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the upper layer include ITO and IZO. The upper portion 62 may also have a single-layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0048] A cathode voltage is supplied to the partition wall 6. This cathode voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A voltage corresponding to the video signal Sdata of the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits PC (PC1, PC2, and PC3) of the subpixels SP1, SP2, and SP3, respectively.

[0049] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the red wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the blue wavelength range.

[0050] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0051] 6 is a schematic plan view showing the boundary between the display area DA and the peripheral area SA. In this embodiment, the outer shape of the display area DA has a curved rounded portion RP. Specifically, when the display area DA is circular as shown in FIG. 1, the entire outer shape corresponds to the rounded portion RP. As another example, the outer shape of the display area DA may include the rounded portion RP and a linear portion.

[0052] As described above, a plurality of pixels PX are arranged in the display area DA. In the rounded portion RP, the pixels PX are arranged in a stepped pattern, for example, as shown in FIG.

[0053] A plurality of dummy pixels DPX that do not display an image (do not light up) are arranged in the peripheral area SA. The dummy pixels DPX are adjacent to the pixels PX arranged at the outermost periphery of the display area DA in the X direction or Y direction. In one example, the dummy pixels DPX are arranged so as to surround the display area DA. In this case, all of the pixels PX arranged at the outermost periphery of the display area DA are adjacent to the dummy pixels DPX. However, it is not necessary for at least one of the pixels PX arranged at the outermost periphery of the display area DA to be adjacent to the dummy pixel DPX.

[0054] 7 is a schematic plan view showing a configuration applicable to the dummy pixel DPX. The dummy pixel DPX includes dummy subpixels DSP1, DSP2, and DSP3. The dummy subpixel DSP1 includes a display element DE1, just like the subpixel SP1. The dummy subpixel DSP2 includes a display element DE2, just like the subpixel SP2. The dummy subpixel DSP3 includes a display element DE3, just like the subpixel SP3.

[0055] The layout of the display elements DE1, DE2, DE3 in the dummy pixel DPX is similar to the layout of the display elements DE1, DE2, DE3 in the pixel PX shown in Fig. 4. In the example of Fig. 7, pixel openings AP1, AP2, AP3 that overlap with the display elements DE1, DE2, DE3 of the dummy pixel DPX are provided in the rib layer 5. Furthermore, the display elements DE1, DE2, DE3 of the dummy pixel DPX are each surrounded by a partition wall 6.

[0056] 8 is a schematic plan view showing an example of the arrangement of dummy pixel circuits DPC arranged for one dummy pixel DPX. The dummy subpixels DSP1, DSP2, and DSP3 each include a dummy pixel circuit DPC (DPC1, DPC2, and DPC3). The dummy pixel circuits DPC1, DPC2, and DPC3 are arranged in the X direction, similar to the pixel circuits PC1, PC2, and PC3 shown in FIG.

[0057] 7 and 8, the contact holes CH1, CH2, and CH3 shown in Fig. 4 are not provided. In this case, the display elements DE1, DE2, and DE3 of the dummy pixel DPX are not connected to the dummy pixel circuits DPC1, DPC2, and DPC3. As another example, contact holes CH1, CH2, and CH3 may also be provided in the dummy pixel DPX, and the display elements DE1, DE2, and DE3 may be connected to the dummy pixel circuits DPC1, DPC2, and DPC3 through these contact holes.

[0058] 9 is a circuit diagram showing an example of a configuration applicable to the dummy pixel circuits DPC (DPC1, DPC2, DPC3). Like the pixel circuit PC shown in FIG. 2, the dummy pixel circuit DPC includes thin-film transistors TR1, TR2, TR3 and a storage capacitor Cst.

[0059] In the subpixels SP1, SP2, and SP3, an electrical path is formed from the wiring (signal line SL, power line PL, and reset wiring RST) that supplies signals or voltages related to driving the display element DE via the pixel circuit PC to the display element DE. On the other hand, in the dummy subpixel DSP, at least a part of this electrical path is cut off. As a result, the display element DE of the dummy subpixel DSP does not light up.

[0060] 9, cut portions C1, C2, C3, and C4 indicated by chain-line circles are provided. At cut portion C1, the electrical path between the dummy pixel circuit DPC and the signal line SL, specifically the path between the thin-film transistor TR1 and the signal line SL, is cut. At cut portion C2, the electrical path between the dummy pixel circuit DPC and the power line PL, specifically the path between the thin-film transistor TR2 and the power line PL, is cut. At cut portion C3, the electrical path between the dummy pixel circuit DPC and the reset line RST, specifically the path between the thin-film transistor TR3 and the reset line RST, is cut. Furthermore, at cut portion C4, the path between the dummy pixel circuit DPC and the display element DE, specifically the paths between the thin-film transistors TR2 and TR3 and the display element DE, is cut.

[0061] 10 is a schematic plan view showing an example of a configuration applicable to pixel circuits PC and dummy pixel circuits DPC arranged near the boundary between the display area DA and the peripheral area SA. In this example, one dummy pixel DPX is arranged outside the pixels PX arranged at the outermost periphery of the display area DA.

[0062] The signal lines SL and power lines PL extend in the Y direction. The scanning lines GL1, GL2 and reset lines RST extend in the X direction. The signal lines SL and power lines PL are made of, for example, a first metal layer included in the circuit layer 11 shown in FIG. 5. The scanning lines GL1, GL2 and reset lines RST are made of, for example, a second metal layer included in the circuit layer 11.

[0063] The pixel circuits PC1, PC2, PC3 and dummy pixel circuits DPC1, DPC2, DPC3 aligned in the X direction constitute a circuit column Rx, while the pixel circuits PC1, PC2, PC3 and dummy pixel circuits DPC1, DPC2, DPC3 aligned in the Y direction constitute a circuit column Ry.

[0064] The scanning lines GL1, GL2 and the reset wiring RST extend across the pixel circuits PC1, PC2, PC3 and dummy pixel circuits DPC1, DPC2, DPC3 that make up the circuit column Rx. From another perspective, the pixel circuits PC1, PC2, PC3 and dummy pixel circuits DPC1, DPC2, DPC3 that make up the circuit column Rx are aligned along one scanning line GL1, GL2 and one reset wiring RST, respectively.

[0065] The signal line SL and the power supply line PL extend across the pixel circuits PC1, PC2, PC3 and dummy pixel circuits DPC1, DPC2, DPC3 that make up the circuit column Ry. From another perspective, the pixel circuits PC1, PC2, PC3 and dummy pixel circuits DPC1, DPC2, DPC3 that make up the circuit column Ry are each aligned along one signal line SL and one power supply line PL.

[0066] 10, the dummy pixel circuit DPC1 is located at one end of the circuit column Rx. Note that, for example, the dummy pixel circuit DPC3 is located at the opposite end of the circuit column Rx.

[0067] 10, dummy pixel circuits DPC1, DPC2, and DPC3 are located at the ends of circuit column Ry. A similar configuration can be applied to the opposite end of circuit column Ry.

[0068] FIG. 11 is an enlarged plan view of the pixel circuit PC (PC1, PC2, PC3) shown in FIG. 10. In the example of FIG. 11, the pixel circuit PC includes semiconductor layers SC1 and SC2, a gate electrode GE, and an output electrode OE. All of these elements are included in the circuit layer 11 shown in FIG. 5. For example, the output electrode OE is formed from the same first metal layer as the signal line SL and the power supply line PL. Furthermore, the gate electrode GE is formed from the same second metal layer as the scanning lines GL1 and GL2 and the reset line RST.

[0069] The semiconductor layer SC1 is connected to the signal line SL at a contact portion P1 and to the gate electrode GE at a contact portion P2. The semiconductor layer SC1 intersects with the scanning line GL1 between the contact portions P1 and P2. This forms the thin-film transistor TR1 shown in FIG. 2.

[0070] The semiconductor layer SC2 is connected to the power line PL at a contact P3, to the reset line RST at a contact P4, and to the output electrode OE at a contact P5. The contact P5 is located between the contacts P3 and P4. The output electrode OE is connected to the lower electrodes (LE1, LE2, LE3) of the subpixel SP that includes the pixel circuit PC through contact holes (CH1, CH2, CH3) in the organic insulating layer 12.

[0071] The semiconductor layer SC2 intersects with the gate electrode GE between the contact portions P3 and P5, thereby forming the thin-film transistor TR2 shown in Figure 2. The semiconductor layer SC2 also intersects with the scanning line GL2 between the contact portions P4 and P5, thereby forming the thin-film transistor TR3 shown in Figure 2.

[0072] Fig. 12 is an enlarged plan view of the dummy pixel circuits DPC (DPC1, DPC2, DPC3) shown in Fig. 10. Like the pixel circuits PC, the dummy pixel circuits DPC include semiconductor layers SC1 and SC2, a gate electrode GE, and an output electrode OE. However, the circuit is cut at cut portions C1, C2, C3, and C4, which are also shown in Fig. 9.

[0073] Specifically, the contact portion P1 shown in FIG. 11 is not provided in the cut portion C1. This separates the semiconductor layer SC1 from the signal line SL. Furthermore, the contact portion P3 shown in FIG. 11 is not provided in the cut portion C2. This separates the semiconductor layer SC2 from the power line PL. Furthermore, the contact portion P4 shown in FIG. 11 is not provided in the cut portion C3. This separates the semiconductor layer SC2 from the reset line RST. Furthermore, the contact portion P5 shown in FIG. 11 is not provided in the cut portion C4. This separates the semiconductor layer SC2 from the output electrode OE.

[0074] It should be noted that the dummy pixel circuit DPC does not necessarily have to have all of the disconnection portions C1, C2, C3, and C4. Furthermore, in the dummy pixel circuit DPC, the electrical path between the display element DE and the dummy pixel circuit DPC may be disconnected in a manner different from the disconnection portions C1, C2, C3, and C4. For example, the electrical path between the display element DE and the dummy pixel circuit DPC can also be disconnected by not providing contact holes (CH1, CH2, CH3) in the dummy subpixel DSP as described above.

[0075] As described above, the display device DSP according to this embodiment includes dummy pixels DPX outside the outermost pixels PX arranged in the display area DA. This configuration can improve the yield and reliability of the display device DSP compared to a case where the dummy pixels DPX are not included.

[0076] Specifically, in a configuration without dummy pixels DPX, the thin-film transistors of the pixel circuits PC at the outermost periphery of the display area DA may be destroyed by static electricity, resulting in abnormal characteristics. In this case, the pixel circuits PC may not function properly, and a defect point may occur in which the sub-pixels SP connected to those pixel circuits PC are always off or always on.

[0077] In contrast, in the display device DSP according to this embodiment, dummy pixel circuits DPC (DPC1, DPC2, DPC3) are arranged outside the outermost pixel circuits PC. In this case, even if breakdown due to static electricity occurs, the damage will be mainly suffered by the dummy pixel circuits DPC. Therefore, the influence on the pixel circuits PC in the display area DA is reduced, and it is possible to suppress the occurrence of the above-mentioned defects.

[0078] Furthermore, when the display area DA has a rounded portion, static electricity damage is likely to occur at the rounded portion. Therefore, when the display area DA is circular as in this embodiment, the effect of providing the dummy pixels DPX becomes more pronounced.

[0079] All display devices and manufacturing methods that can be implemented by a person skilled in the art by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0080] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of each of the above-described embodiments, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0081] Furthermore, with regard to other effects brought about by the aspects described in each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0082] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, DE1, DE2, DE3...display element, PC1, PC2, PC3...pixel circuit, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, DPX...dummy pixel, DSP1, DSP2, DSP3...dummy subpixel, DPC1, DPC2, DPC3...dummy pixel circuit, 5...rib layer, 6...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer.

Claims

1. Wiring that supplies a signal or voltage; a plurality of sub-pixels each including a display element including an organic layer that emits light in response to application of a voltage, and a pixel circuit that drives the display element; a dummy sub-pixel including the display element and a dummy pixel circuit; Equipped with the pixel circuits and the dummy pixel circuits of the plurality of sub-pixels form a circuit row aligned along the wiring, the dummy pixel circuit is located at an end of the circuit row, In each of the plurality of sub-pixels, an electrical path is formed from the wiring to the display element via the pixel circuit, In the dummy sub-pixel, at least a part of an electrical path from the wiring to the display element via the dummy pixel circuit is cut off. Display device.

2. In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the display element is cut off. The display device according to claim 1 .

3. In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the wiring is cut off. The display device according to claim 1 .

4. the wiring includes a signal line that supplies video signals to the plurality of sub-pixels, In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the signal line is cut off. The display device according to claim 3 .

5. the wiring includes a power supply line to which a drive voltage is applied to be supplied to the display elements of the plurality of sub-pixels, In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the power supply line is cut off. The display device according to claim 3 .

6. the wiring includes a reset wiring that supplies a reset voltage to the display elements of the plurality of sub-pixels; In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the reset line is cut off. The display device according to claim 3 .

7. the plurality of sub-pixels are arranged in a display area for displaying an image, The outer shape of the display area includes a non-linear rounded portion. The display device according to any one of claims 1 to 6.

8. The outer shape of the display area is circular. The display device according to claim 7 .

9. Wiring that supplies a signal or voltage; a plurality of sub-pixels each including a display element including an organic layer that emits light in response to application of a voltage, and a pixel circuit that drives the display element; a dummy sub-pixel including the display element and a dummy pixel circuit; a partition wall surrounding the display element of each of the plurality of sub-pixels; Equipped with the pixel circuits and the dummy pixel circuits of the plurality of sub-pixels form a circuit row aligned along the wiring, the dummy pixel circuit is located at an end of the circuit row, In each of the plurality of sub-pixels, an electrical path is formed from the wiring to the display element via the pixel circuit, In the dummy sub-pixel, at least a part of an electrical path from the wiring to the display element via the dummy pixel circuit is cut off. Display device.

10. the partition wall further surrounds the display element of the dummy sub-pixel. The display device according to claim 9 .

11. The partition wall is a conductive lower portion; an upper portion disposed on the lower portion and having an end portion protruding from a side surface of the lower portion; Including, The display device according to claim 9 .

12. The lower part is the conductive bottom layer; a shaft layer disposed on the bottom layer; Including, The bottom layer protrudes from the side surface of the shaft layer. The display device according to claim 11.

13. The display element of each of the plurality of sub-pixels includes: a lower electrode connected to the pixel circuit; an upper electrode facing the lower electrode and in contact with the lower portion of the partition wall; the organic layer located between the lower electrode and the upper electrode; Including, The display device according to claim 11.

14. In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the display element is cut off. The display device according to claim 9 .

15. In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the wiring is cut off. The display device according to claim 9 .

16. the wiring includes a signal line that supplies video signals to the plurality of sub-pixels, In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the signal line is cut off. The display device according to claim 15.

17. the wiring includes a power supply line to which a drive voltage is applied to be supplied to the display elements of the plurality of sub-pixels, In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the power supply line is cut off. The display device according to claim 15.

18. the wiring includes a reset wiring that supplies a reset voltage to the display elements of the plurality of sub-pixels; In the dummy sub-pixel, an electrical path between the dummy pixel circuit and the reset line is cut off. The display device according to claim 15.

19. the plurality of sub-pixels are arranged in a display area for displaying an image, The outer shape of the display area includes a non-linear rounded portion.

19. A display device according to any one of claims 9 to 18.

20. The outer shape of the display area is circular.

20. The display device according to claim 19.

Images