Display device and electronic apparatus

Abstract

To provide a display device capable of driving data lines at high speed.SOLUTION: A display device includes: a plurality of first light-emitting elements; a plurality of second light-emitting elements; a data transfer line; a first data line extending in a first direction; a second data line extending in the first direction and adjacent to the first data line along the first direction; a plurality of first pixel circuits connected to the first data line and respectively connected to the plurality of first light-emitting elements; a plurality of second pixel circuits coupled to the second data line and respectively connected to the plurality of second light-emitting elements; a first switching circuit that controls the electrical connection between the first data line and the data transfer line; and a second switching circuit that controls the electrical connection between the second data line and the data transfer line. In a plan view, the first switching circuit overlaps at least one of the plurality of first light-emitting elements.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present invention relates to a display device and an electronic device. [Background technology]

[0002] Display devices that have light-emitting elements such as organic EL (Electro Luminescence) elements are known. In these display devices, a large number of pixel circuits, each having multiple transistors used to drive the light-emitting elements and control the timing of light emission, are connected to a single data line.

[0003] For example, Patent Document 1 discloses a display device in which the threshold voltage of a driving transistor of a light-emitting element is held at one end of a coupling capacitance provided between a data line and a pixel circuit, and then data is written to the pixel circuit from the other end of the coupling capacitance by changing the voltage according to gradation data. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-96418 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the display device described in Patent Document 1, when the load capacitance of the data lines increases due to an increase in the number of pixels and an increase in screen size as a result of higher resolution displayed images, it becomes difficult to drive the data lines at high speed, and the time required to initialize the voltage on the data lines and to write data becomes longer. [Means for solving the problem]

[0006] One aspect of the display device according to the present invention is A plurality of first light-emitting elements; A plurality of second light-emitting elements; A data transfer line; a first data line extending in a first direction; a second data line extending in the first direction and adjacent to the first data line along the first direction; a plurality of first pixel circuits connected to the first data lines and connected to the plurality of first light-emitting elements, respectively; a plurality of second pixel circuits connected to the second data lines and connected to the plurality of second light-emitting elements, respectively; a first switch circuit that controls an electrical connection between the first data line and the data transfer line; a second switch circuit that controls an electrical connection between the second data line and the data transfer line; a signal for causing each of the plurality of first light-emitting elements to emit light is supplied to the first data line from the data transfer line via the first switch circuit; a signal for causing each of the plurality of second light-emitting elements to emit light is supplied to the second data line from the data transfer line via the second switch circuit; In a plan view, the first switch circuit overlaps with at least one of the plurality of first light-emitting elements.

[0007] One aspect of the electronic device according to the present invention is The display device has one aspect of the above. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view schematically showing a display device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a plan view schematically showing a display panel of the display device. [Figure 3] FIG. 1 is a block diagram showing the electrical configuration of a display device according to a first embodiment. [Figure 4] FIG. 2 is a diagram showing the configuration of a pixel circuit and a data potential generating circuit. [Figure 5] FIG. 2 is a timing chart showing an example of waveforms of various signals in the display device. [Figure 6] 1A and 1B are diagrams illustrating the operation of a display device. [Figure 7]1A and 1B are diagrams illustrating the operation of a display device. [Figure 8] 1A and 1B are diagrams illustrating the operation of a display device. [Figure 9] 1A and 1B are diagrams illustrating the operation of a display device. [Figure 10] FIG. 2 is a cross-sectional view schematically showing a part of a display panel. [Figure 11] FIG. 2 is a plan view showing an example of the layout of part of pixel circuit blocks BLK-1 and BLK-2 in the first embodiment. [Figure 12] FIG. 3 is a plan view showing in more detail the layout of part of each pixel circuit block in the first embodiment. [Figure 13] FIG. 10 is a block diagram showing the electrical configuration of a display device according to a second embodiment. [Figure 14] FIG. 10 is a plan view showing an example of the layout of part of pixel circuit blocks BLK-1 and BLK-2 according to a second embodiment. [Figure 15] FIG. 10 is a plan view showing in more detail the layout of part of each pixel circuit block according to the second embodiment. [Figure 16] FIG. 1 is a perspective view schematically showing a head-mounted display according to an embodiment of the present invention. [Figure 17] FIG. 2 is a diagram schematically illustrating an image forming device and a light guiding device of the head-mounted display according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0010] 1.Display device 1-1. First embodiment 1-1-1. Overall configuration of the display device Fig. 1 is a perspective view schematically showing a display device 1 of this embodiment. Fig. 2 is a plan view schematically showing a display panel 2 of the display device 1 of this embodiment. Note that Figs. 1 and 2 show an X-axis, a Y-axis, and a Z-axis as three mutually orthogonal axes.

[0011] The display device 1 is, for example, a micro display that displays color images in an HMD, etc. HMD is an abbreviation for Head Mount Display.

[0012] 1, the display device 1 includes a display panel 2, an FPC board 120, and a case 130. FPC is an abbreviation for Flexible Printed Circuits.

[0013] The display panel 2 includes a plurality of light-emitting elements, a plurality of pixel circuits connected to the plurality of light-emitting elements, and a drive circuit for driving the pixel circuits. In this embodiment, the plurality of light-emitting elements, the plurality of pixel circuits, and the drive circuit included in the display panel 2 are formed on a silicon substrate, and the light-emitting elements are OLEDs. OLED is an abbreviation for Organic Light Emitting Diode.

[0014] As shown in FIG. 2, the display panel 2 has a display area 112. In the illustrated example, the display area 112 is a rectangle with long sides parallel to the X axis. In the display area 112, a plurality of pixels P as display units are displayed in a matrix at a predetermined arrangement pitch. In the illustrated example, the plurality of pixels P are displayed in a matrix in the X-axis direction and the Y-axis direction. In the following description, it is assumed that m×n pixels P are displayed in m rows in the Y-axis direction and n columns in the X-axis direction. Note that m and n are integers of 2 or greater. Note that the pitch refers to the distance along a predetermined direction from one end of one element in the predetermined direction to one end of an adjacent element in the predetermined direction when a plurality of elements are arranged along the predetermined direction.

[0015] Pixel P has luminance information and may also have color information. When pixel P has luminance information but no color information, a black and white image is displayed in display area 112. On the other hand, when pixel P has luminance information and color information, a color image is displayed in display area 112. In the following description, it is assumed that pixel P has luminance information and color information.

[0016] Each of the m×n pixels P is made up of three sub-pixels SP of red, green and blue.

[0017] As shown in FIG. 1, the display panel 2 is housed and fixed in a frame-shaped case 130 that opens in the display area 112, and one end of an FPC board 120 is connected to the case. The other end of the FPC board 120 is provided with a plurality of external connection terminals 124, which are connected to an external circuit (not shown). A control circuit 3, which is a semiconductor chip, is mounted on the FPC board 120 using COF technology, and image data synchronized with a synchronization signal is supplied from the external circuit via the plurality of external connection terminals 124. COF is an abbreviation for Chip On Film. The synchronization signal includes a vertical synchronization signal that instructs the start of vertical scanning of image data, a horizontal synchronization signal that instructs the start of horizontal scanning of image data, and a dot clock signal that indicates the timing of one pixel of image data.

[0018] The control circuit 3 supplies various control signals and various potentials generated in accordance with the synchronization signal to the display panel 2, and also supplies data corresponding to each pixel P included in the image data to the display panel 2 in a time-division manner.

[0019] 1-1-2. Functional configuration of the display device Fig. 3 is a block diagram showing the electrical configuration of the display device 1 of the first embodiment. As shown in Fig. 3, the display device 1 includes a control circuit 3, a plurality of pixel circuits 20, a scanning line driving circuit 21, a plurality of switch circuits 22, a plurality of data potential generating circuits 23, and a plurality of P-channel MOSFETs 24. The plurality of pixel circuits 20, the scanning line driving circuit 21, the plurality of switch circuits 22, the plurality of data potential generating circuits 23, and the plurality of MOSFETs 24 are provided in the display panel 2. As described above, the control circuit 3 is mounted on the FPC board 120, but may also be provided in the display panel 2.

[0020] The display panel 2 is provided with m scanning lines 11 arranged in the horizontal direction in the figure, and 3n data transfer lines 17 arranged in the vertical direction in the figure. In Figure 3, the horizontal direction corresponds to the X-axis direction in Figures 1 and 2, and the vertical direction corresponds to the Y-axis direction in Figures 1 and 2. Then, m x 3n pixel circuits 20 are provided corresponding to the m scanning lines 11 and the 3n data transfer lines 17. That is, one pixel circuit 20 is provided corresponding to one scanning line 11 and one data transfer line 17, and the m x 3n pixel circuits 20 are arranged in a matrix of m rows in the vertical direction and 3n columns in the horizontal direction.

[0021] The m×3n pixel circuits 20 are divided into q pixel circuit blocks BLK-1 to BLK-2, each of which has p×3n pixel circuits 20 connected to any one of p scanning lines 11. 3, the pixel circuit block BLK-1 includes p×3n pixel circuits 20 connected to any of p scanning lines 11 in rows 1 to p. The second pixel circuit block BLK-2 includes p×3n pixel circuits 20 connected to any of p scanning lines 11 in rows p+1 to 2p. In general, the kth pixel circuit block BLK-k includes p×3n pixel circuits 20 connected to any of p scanning lines 11 in rows (k−1)×p+1 to k×p. k is an integer between 1 and q.

[0022] Each pixel circuit block BLK-k is provided with 3n data lines 12 arranged in the vertical direction, and p pixel circuits 20 are connected to each data line 12. The 3n data lines 12 are divided into n groups, each consisting of three data lines. Of these n groups, the j-th group from the left includes the data line 12 in the 3j-2 column, the data line 12 in the 3j-1 column, and the data line 12 in the 3j-2 column. Here, j is an integer between 1 and n. The n pixel circuits 20 that respectively cause n red subpixels SP to emit light are connected to the data line 12 in the 3j-2 column. The n pixel circuits 20 that respectively cause n blue subpixels SP to emit light are connected to the data line 12 in the 3j-1 column. The n pixel circuits 20 that respectively cause n green subpixels SP to emit light are connected to the data line 12 in the 3j-2 column. In FIG. 3, the pixel circuits 20 that cause the red subpixels SP to emit light are marked with "R," the pixel circuits 20 that cause the blue subpixels SP to emit light are marked with "B," and the pixel circuits 20 that cause the green subpixels SP to emit light are marked with "G."

[0023] Each pixel circuit block BLK-k also includes 3n switch circuits 22, and each of the 3n switch circuits 22 controls the electrical connection between each of the 3n data lines 12 and each of the 3n data transfer lines 17 under the control of the control circuit 3. That is, when each switch circuit 22 is turned on, each data line 12 is electrically connected to each data transfer line 17, and when each switch circuit 22 is turned off, each data line 12 is electrically disconnected from each data transfer line 17. Specifically, when the switch circuit 22 connected to the data line 12 in the 3j-2 column is turned on, the data line 12 in the 3j-2 column is electrically connected to the data transfer line 17 in the 3j-2 column; when the switch circuit 22 connected to the data line 12 in the 3j-1 column is turned on, the data line 12 in the 3j-1 column is electrically connected to the data transfer line 17 in the 3j-1 column; when the switch circuit 22 connected to the data line 12 in the 3j column is turned on, the data line 12 in the 3j column is electrically connected to the data transfer line 17 in the 3j column.

[0024] The drains of the 3n MOSFETs 24 are connected to the 3n data transfer lines 17. A potential VINI is commonly supplied from the control circuit 3 to the sources of the 3n MOSFETs 24, and a control signal XGINI is commonly supplied from the control circuit 3 to the gates of the 3n MOSFETs 24.

[0025] The display panel 2 is also provided with 3n power supply lines 15 arranged along the vertical direction. The 3j-2th power supply line 15 is connected to m pixel circuits 20 corresponding to the red subpixels SP of the m pixels P in the jth column. The 3j-1th power supply line 15 is connected to m pixel circuits 20 corresponding to the blue subpixels SP of the m pixels P in the jth column. The 3j-1th power supply line 15 is connected to m pixel circuits 20 corresponding to the green subpixels SP of the m pixels P in the jth column. A potential V0 is commonly supplied to the 3n power supply lines 15 from the control circuit 3. The potential V0 is, for example, a ground potential VSS, which is a reference for zero potential, or a potential close to the ground potential VSS. Specifically, the potential V0 is a potential such that, when applied to a light-emitting element, no current flows through the light-emitting element.

[0026] The control circuit 3 controls each component based on image data VID, a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, and a dot clock signal DCLK supplied from an external circuit. The image data VID is data that specifies the gradation level of each pixel P of an image to be displayed in the display area 112, for example, by 8 bits for each RGB. In other words, the image data VID is data that switches between 24-bit RGB data corresponding to the luminance information and color information of each pixel P for each cycle of the dot clock signal DCLK.

[0027] Here, because the brightness characteristics indicated by the gradation levels do not match the luminance characteristics of the light-emitting elements, the control circuit 3 converts the image data VID that specifies the gradation levels of the pixels P into image data VIDX that specifies the luminance corresponding to the gradation levels. That is, the control circuit 3 up-converts each of the 8 bits of R data, G data, and B data of each pixel P included in the image data VID into, for example, 10-bit R data, G data, and B data that specify the luminance of the corresponding light-emitting element, thereby generating the image data VIDX. For such up-conversion, a look-up table that pre-stores the correspondence between each of the 8-bit R data, G data, and B data and each of the 10-bit R data, G data, and B data is used.

[0028] The scanning line driving circuit 21 is a circuit for driving the pixel circuits 20 arranged in m rows and 3n columns, row by row, under the control of the control circuit 3, and outputs various signals. For example, the scanning line driving circuit 21 supplies scanning signals XGWR[1] to XGWR[m] to the 1st to mth scanning lines 11 in order. That is, the scanning signal XGWR[i] is supplied to the i-th scanning line 11.

[0029] One data potential generating circuit 23 is provided for one data transfer line 17. That is, the display panel 2 includes 3n data potential generating circuits 23.

[0030] The 3j-2-th data potential generating circuit 23 from the left generates a data potential VDATA[3j-2] to be supplied to the data transfer line 17 in the 3j-2-th column based on image data VIDX supplied from the control circuit 3, in accordance with control by the control circuit 3. Similarly, the 3j-1-th data potential generating circuit 23 from the left generates a data potential VDATA[3j-1] to be supplied to the data transfer line 17 in the 3j-1-th column based on image data VIDX supplied from the control circuit 3, in accordance with control by the control circuit 3. Similarly, the 3j-th data potential generating circuit 23 from the left generates a data potential VDATA[3j] to be supplied to the data transfer line 17 in the 3j-1-th column based on image data VIDX supplied from the control circuit 3, in accordance with control by the control circuit 3. Specifically, the 3j-2-th data potential generating circuit 23 includes a capacitive DAC, which acquires and D / A converts R data of the pixel P in the ith row and jth column included in the image data VIDX at a timing specified by the control circuit 3, and outputs a data potential VDATA[3j-2] to the 3j-2-th data transfer line 17. The 3j-1-th data potential generating circuit 23 also includes a capacitive DAC, which acquires and D / A converts B data of the pixel P in the ith row and jth column included in the image data VIDX at a timing specified by the control circuit 3, and outputs a data potential VDATA[3j-1] to the 3j-1-th data transfer line 17. The 3j-th data potential generating circuit 23 also includes a capacitive DAC, which acquires and D / A converts G data of the pixel P in the ith row and jth column included in the image data VIDX at a timing specified by the control circuit 3, and outputs a data potential VDATA[3j-1] to the 3j-1-th data transfer line 17.

[0031] The control circuit 3 supplies various control signals and various potentials to the display panel 2, but only some of them are shown in FIG.

[0032] 1-1-3. Configuration of pixel circuit and data potential generating circuit 4 is a diagram showing the configuration of three pixel circuits 20 and three data potential generating circuits 23 corresponding to the pixel P on the i-th row and j-th column. These three pixel circuits 20 are included in the k-th pixel circuit block BLK-k. For ease of explanation, in FIG. 4, the three pixel circuits 20 corresponding to the pixel P on the i-th row and j-th column are distinguished as pixel circuits 20-1, 20-2, and 20-3, respectively. However, the three pixel circuits 20 have the same configuration, and the same components are assigned the same reference numerals. The pixel circuit 20-1 is the pixel circuit 20 corresponding to the red subpixel SP of the pixel P, the pixel circuit 20-2 is the pixel circuit 20 corresponding to the blue subpixel SP of the pixel P, and the pixel circuit 20-3 is the pixel circuit 20 corresponding to the green subpixel SP of the pixel P.

[0033] 4, the three light-emitting elements 27 connected to the pixel circuits 20-1, 20-2, and 20-3 are distinguished as light-emitting elements 27-1, 27-2, and 27-3, respectively, but the four light-emitting elements 27 have the same configuration. Also, in FIG. 4, the three data potential generating circuits 23 are distinguished as data potential generating circuits 23-1, 23-2, and 23-3, respectively, but the three data potential generating circuits 23 have the same configuration, and only the configuration of the data potential generating circuit 23-1 is shown. The data potential generating circuits 23-1, 23-2, and 23-3 are the 3j-2th, 3j-1st, and 3jth data potential generating circuits 23, respectively. Also, in FIG. 4, the three data transfer lines 17 connected to the data potential generating circuits 23-1, 23-2, and 23-3, respectively, are distinguished as data transfer lines 17-1, 17-2, and 17-3, respectively. The three switch circuits 22 connected to the data transfer lines 17-1, 17-2, and 17-3 are respectively designated as switch circuits 22-1, 22-2, and 22-3, but the configurations of the three switch circuits 22 are the same. The three MOSFETs 24 connected to the data transfer lines 17-1, 17-2, and 17-3 are respectively designated as MOSFETs 24-1, 24-2, and 24-3, but the configurations of the three MOSFETs 24 are the same.

[0034] 4, the pixel circuit 20 includes a capacitive element 201 and P-channel MOSFETs 202 to 206, and is connected to a light-emitting element 27. MOS is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0035] The light-emitting element 27 is an OLED having a structure in which a light-emitting functional layer is sandwiched between a pixel electrode and a common electrode (not shown). The pixel electrode functions as an anode, and the common electrode, which is optically transparent, functions as a cathode. When a current flows from the anode to the cathode in the light-emitting element 27, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer to generate excitons, thereby generating white light. The generated white light then resonates in an optical resonator composed of a reflective layer and a semi-reflective / semi-transmissive layer (not shown) and is emitted at a resonant wavelength set corresponding to one of red, green, or blue. A color filter corresponding to the corresponding color is provided on the light exit side of the optical resonator. Therefore, the light emitted from the light-emitting element 27 is visually recognized by the viewer after being colored by the optical resonator and color filter. Note that the color filter is omitted when displaying a black-and-white image in the display area 112.

[0036] A potential VEL is supplied to one end of the capacitance element 201 from the control circuit 3, and the other end of the capacitance element 201 is connected to the gate of the MOSFET 202 and the drain of the MOSFET 203. A potential VEL is supplied to the source of the MOSFET 202, and the drain of the MOSFET 202 is connected to the drain of the MOSFET 204 and the source of the MOSFET 205. The drain of the MOSFET 205 is connected to the drain of the MOSFET 206 and the anode of the light-emitting element 27. A potential VCT is supplied to the cathode of the light-emitting element 27 from the control circuit 3.

[0037] The source of the MOSFET 203 and the source of the MOSFET 204 are connected to the data line 12. The source of the MOSFET 206 is connected to the power supply line 15. A potential V0 is supplied from

[0038] The gate of the MOSFET 203 receives a scanning signal XGWR[i] from the scanning line driving circuit 21. The gate of the MOSFET 204 receives a control signal XGCMP[i] from the scanning line driving circuit 21. The gate of the MOSFET 205 receives a control signal XGEL[i] from the scanning line driving circuit 21. The gate of the MOSFET 206 receives a control signal XGOR[i] from the scanning line driving circuit 21.

[0039] The MOSFET 202 supplies a current according to the voltage between the gate and source to the light emitting element 27. Specifically, the higher the voltage between the gate and source of the MOSFET 202, the larger the current flowing through the light emitting element 27, and the greater the amount of light emitted by the light emitting element 27.

[0040] The MOSFET 203 controls the electrical connection between the data line 12 and the gate of the MOSFET 202 according to the potential of the scanning line 11. Specifically, when the scanning signal XGWR[i] supplied to the scanning line 11 is at L level, the MOSFET 203 is turned on, electrically connecting the data line 12 and the gate of the MOSFET 202, and when the scanning signal XGWR[i] is at H level, the MOSFET 203 is turned off, electrically disconnecting the data line 12 and the gate of the MOSFET 202.

[0041] The MOSFET 204 controls the electrical connection between the data line 12 and the drain of the MOSFET 202. Specifically, when the control signal XGCMP[i] is at an L level, the MOSFET 204 is turned on, electrically connecting the data line 12 and the drain of the MOSFET 202, and when the control signal XGCMP[i] is at an H level, the MOSFET 204 is turned off, electrically disconnecting the data line 12 and the drain of the MOSFET 202.

[0042] The MOSFET 205 controls the electrical connection between the light-emitting element 27 and the drain of the MOSFET 202. Specifically, when the control signal XGEL[i] is at an L level, the MOSFET 205 is turned on, electrically connecting the anode of the light-emitting element 27 and the drain of the MOSFET 202, and when the control signal XGEL[i] is at an H level, the MOSFET 205 is turned off, electrically disconnecting the anode of the light-emitting element 27 and the drain of the MOSFET 202.

[0043] The MOSFET 206 controls the electrical connection between the power supply line 15 and the light-emitting element 27. Specifically, when the control signal XGOR[i] is at an L level, the MOSFET 206 is turned on, electrically connecting the power supply line 15 and the anode of the light-emitting element 27, and when the control signal XGOR[i] is at an H level, the MOSFET 206 is turned off, electrically disconnecting the power supply line 15 and the anode of the light-emitting element 27.

[0044] 4, a capacitance 25 is provided between the data line 12 connected to the pixel circuit 20 and the power supply line 15. The capacitance 25 may be a parasitic capacitance between the data line 12 and the power supply line 15, or may be a capacitance formed by sandwiching an insulating layer between different conductive layers on a silicon substrate.

[0045] 4, the switch circuit 22 is a transmission gate in which the sources and drains of an N-channel MOSFET and a P-channel MOSFET are connected to each other. Hereinafter, in the switch circuit 22, the gate of the N-channel MOSFET will be referred to as the "first control terminal," the gate of the P-channel MOSFET will be referred to as the "second control terminal," the connection node between the source of the N-channel MOSFET and the source of the P-channel MOSFET will be referred to as the "input terminal," and the connection node between the drain of the N-channel MOSFET and the drain of the P-channel MOSFET will be referred to as the "output terminal."

[0046] A potential VINI is supplied to the source of MOSFET 24-1 from control circuit 3, and the drain of MOSFET 24-1 is connected to data line 12 connected to pixel circuit 20-1. An input terminal of switch circuit 22-1 is connected to data transfer line 17-1, and an output terminal of switch circuit 22-1 is connected to data line 12 connected to pixel circuit 20-1.

[0047] Similarly, the potential VINI is supplied to the source of MOSFET 24-2 from control circuit 3, and the drain of MOSFET 24-2 is connected to data line 12 connected to pixel circuit 20-2. The input terminal of switch circuit 22-2 is connected to data transfer line 17-2, and the output terminal of switch circuit 22-2 is connected to data line 12 connected to pixel circuit 20-2.

[0048] Similarly, the potential VINI is supplied to the source of MOSFET 24-3 from control circuit 3, and the drain of MOSFET 24-3 is connected to data line 12 connected to pixel circuit 20-3. The input terminal of switch circuit 22-3 is connected to data transfer line 17-3, and the output terminal of switch circuit 22-3 is connected to data line 12 connected to pixel circuit 20-3.

[0049] A control signal XGINI is input to each gate of MOSFETs 24-1, 24-2, and 24-3 from the control circuit 3. A control signal SEL[k] is commonly input to a first control terminal of each of switch circuits 22-1, 22-2, and 22-3 from the control circuit 3, and a control signal XSEL[k] is commonly input to a second control terminal of each of switch circuits 22-1, 22-2, and 22-3 from the control circuit 3. The control signal SEL[k] and the control signal XSEL[k] are digital signals whose logical levels are inverted from each other.

[0050] The MOSFET 24-1 controls the supply of the potential VINI to the data transfer line 17-1. The MOSFET 24-2 controls the supply of the potential VINI to the data transfer line 17-2. The MOSFET 24-3 controls the supply of the potential VINI to the data transfer line 17-3. Specifically, when the control signal XGINI is at an L level, the MOSFET 24-1 turns on and the potential VINI is supplied to the data transfer line 17-1, the MOSFET 24-2 turns on and the potential VINI is supplied to the data transfer line 17-2, and the MOSFET 24-3 turns on and the potential VINI is supplied to the data transfer line 17-3. On the other hand, when the control signal XGINI is at an H level, the MOSFET 24-1 turns off and the potential VINI is not supplied to the data transfer line 17-1, the MOSFET 24-2 turns off and the potential VINI is not supplied to the data transfer line 17-2, and the MOSFET 24-3 turns off and the potential VINI is not supplied to the data transfer line 17-3.

[0051] Switch circuit 22-1 controls the electrical connection between the data line 12 connected to pixel circuit 20-1 and data transfer line 17-1. Switch circuit 22-2 controls the electrical connection between the data line 12 connected to pixel circuit 20-2 and data transfer line 17-2. Switch circuit 22-3 controls the electrical connection between the data line 12 connected to pixel circuit 20-3 and data transfer line 17-3. Specifically, when control signals SEL[k] and XSEL[k] are H level and L level, respectively, switch circuit 22-1 turns on, electrically connecting the data line 12 connected to pixel circuit 20-1 and data transfer line 17-1, switch circuit 22-2 turns on, electrically connecting the data line 12 connected to pixel circuit 20-2 and data transfer line 17-2, and switch circuit 22-3 turns on, electrically connecting the data line 12 connected to pixel circuit 20-3 and data transfer line 17-3. When the control signals SEL[k] and XSEL[k] are at the L level and the H level, respectively, the switch circuit 22-1 is turned off, and the data line 12 connected to the pixel circuit 20-1 is electrically disconnected from the data transfer line 17-1, the switch circuit 22-2 is turned off, and the data line 12 connected to the pixel circuit 20-2 is electrically disconnected from the data transfer line 17-2, and the switch circuit 22-3 is turned off, and the pixel circuit 20- The data line 12 connected to the data transfer line 17-3 is electrically disconnected from the data transfer line 17-3.

[0052] When the data line 12 connected to the pixel circuit 20-1 is electrically connected to the data transfer line 17-1 by the switch circuit 22-1, the data potential VDATA[3j-2] is transferred from the data transfer line 17-1 to the data line 12. Similarly, when the data line 12 connected to the pixel circuit 20-2 is electrically connected to the data transfer line 17-2 by the switch circuit 22-2, the data potential VDATA[3j-1] is transferred from the data transfer line 17-2 to the data line 12. Similarly, when the data line 12 connected to the pixel circuit 20-3 is electrically connected to the data transfer line 17-3 by the switch circuit 22-3, the data potential VDATA[3j] is transferred from the data transfer line 17-3 to the data line 12.

[0053] The control signal XGINI is input in common to 3n MOSFETs 24, and the control signals SEL[k], XSEL[k] are input in common to 3n switch circuits 22 included in the k-th pixel circuit block BLK-k.

[0054] 4, 10-bit image data VIDX that is switched in a time-division manner to R data, B data, and G data of pixels P in column j is input to data potential generating circuits 23-1, 23-2, and 23-3 from the control circuit 3. In FIG. 4, the most significant bits of the image data VIDX are denoted as D9, D8, D7, D6, D5, D4, D3, D2, D1, and D0, in that order.

[0055] The data potential generating circuit 23-1 includes a capacitive DAC having capacitive elements 231-0 to 231-9 and 232, and switch circuits 233-0 to 233-9 and 234.

[0056] One end of each of the capacitive elements 231-0 to 231-4 and the output terminal of the switch circuit 234 are connected to one end of the capacitive element 232. One end of each of the capacitive elements 231-5 to 231-9 is connected to the other end of the capacitive element 232 and the data transfer line 17-1. The other end of each of the capacitive elements 231-0 to 231-9 is connected to the output terminal of each of the switch circuits 233-0 to 233-9. A potential VL is supplied from the control circuit 3 to a first input terminal of each of the switch circuits 233-0 to 233-9, and a potential VH higher than the potential VL is supplied from the control circuit 3 to a second input terminal of each of the switch circuits 233-0 to 233-9. Bits D0 to D9 of the image data VIDX are input from the control circuit 3 to the control terminal of each of the switch circuits 233-0 to 233-9, respectively. When bit Dr is at L level, switch circuit 233-r establishes electrical continuity between its first input terminal and output terminal, and when bit Dr is at H level, it establishes electrical continuity between its second input terminal and output terminal. That is, switch circuit 233-r outputs potential VL when bit Dr is at L level, and outputs potential VH when bit Dr is at H level. r is an integer between 0 and 9.

[0057] If the capacitance value of the capacitive element 231-r is Cr, then, for example, C0:C1:C2:C3:C4:C5:C6:C7:C8:C9=1:2:4:8:16:1:2:4:8:16. The capacitance value Cser of the capacitive element 232 may be the same as C0 and C5. Note that a certain degree of error is allowed for the capacitance values ​​C0 to C9 and Cser as long as linearity is maintained between the value of the input 10-bit image data VIDX and the output data potential VDATA[3j-2].

[0058] An input terminal of the switch circuit 234 is supplied with a potential VRST from the control circuit 3, and a control signal XRST is input from the control circuit 3 to a control terminal of the switch circuit 234. When the control signal XRST is at L level, the input terminal and output terminal of the switch circuit 234 are electrically connected, and when the control signal XRST is at H level, the input terminal and output terminal are not electrically connected. Therefore, when the control signal XRST is at L level, one end and A potential VRST is supplied to one end of the capacitive element 232. Note that, since one end of the capacitive elements 231-5 to 231-9 and the other end of the capacitive element 232 are connected to the data transfer line 17-1, a potential VINI is supplied thereto when the control signal XGINI is at L level. Therefore, when the control signal XRST and the control signal XGINI are both at L level, the charges accumulated in the capacitive elements 231-0 to 231-9 and 232 are initialized.

[0059] On the other hand, when the control signal XRST and the control signal XGINI are both at H level, charges corresponding to the logic levels of the bits D0 to D9 are accumulated in each of the capacitive elements 231-0 to 231-9. Since one end of each of the capacitive elements 231-0 to 231-4 is connected to one end of the capacitive element 232, one end of the capacitive element 232 has a potential corresponding to the logic levels of the bits D0 to D4. Furthermore, since one end of each of the capacitive elements 231-5 to 231-9 is connected to the other end of the capacitive element 232, the other end of the capacitive element 232 has a potential that is a potential corresponding to the logic levels of the bits D5 to D9, shifted in accordance with the potential at one end of the capacitive element 232. Therefore, the potential at the other end of the capacitive element 232 changes linearly with the bits D9 to D0 and is supplied to the data transfer line 17-1 as the data potential VDATA[3j-2].

[0060] The configuration of the data potential generating circuits 23-2 and 23-3 is the same as that of the data potential generating circuit 23-1, and the data potential generating circuit 23-2 generates a data potential VDATA[3j-1] and supplies it to the data transfer line 17-2, while the data potential generating circuit 23-3 generates a data potential VDATA[3j] and supplies it to the data transfer line 17-3.

[0061] In this way, the 3j-2-th data potential generating circuit 23, under the control of the control circuit 3, acquires and D / A converts the R data of m pixels P in the j-th column included in the image data VIDX output from the control circuit 3 at the timing specified by the control circuit 3, and generates a data potential VDATA[3j-2] to be supplied to the 3j-2-th data transfer line 17. Also, the 3j-1-th data potential generating circuit 23, under the control of the control circuit 3, acquires and D / A converts the B data of m pixels P in the j-th column included in the image data VIDX output from the control circuit 3 at the timing specified by the control circuit 3, and generates a data potential VDATA[3j-1] to be supplied to the 3j-1-th data transfer line 17. Also, the 3j-th data potential generating circuit 23, under the control of the control circuit 3, acquires and D / A converts the G data of m pixels P in the j-th column included in the image data VIDX output from the control circuit 3 at the timing specified by the control circuit 3, and generates a data potential VDATA[3j] to be supplied to the 3j-1-th data transfer line 17. Therefore, the data potentials VDATA[3j-2], VDATA[3j-1], and VDATA[3j] are switched in a time-division manner at the timing when R data, B data, or G data is written to 3m pixel circuits 20 corresponding to m pixels P in the jth column.

[0062] 1-1-4. Display device operation The operation of the display device 1 will be described with reference to Fig. 5 to Fig. 9. Fig. 5 is a timing chart showing an example of waveforms of various signals in the display device 1. Fig. 6 to Fig. 9 are diagrams in which the on / off states of the MOSFET and switch circuit and the supply paths of various potentials in each period are added to Fig. 4.

[0063] As shown in Fig. 5, a horizontal scanning period 1H corresponds to one cycle period from the timing when the horizontal synchronization signal HSYNC input from an external circuit of the display device 1 transitions from H level to L level to the timing when the horizontal synchronization signal HSYNC next transitions from H level to L level. During each horizontal scanning period 1H, data is written to 3n pixel circuits 20 corresponding to n pixels P in each row. During each horizontal scanning period 1H, the scanning line driving circuit 21 commonly outputs control signals XGEL[i], XGOR[i], XGCMP[i] and scanning signal XGWR[i] to the 3n pixel circuits 20 corresponding to n pixels P in the i-th row. In addition, the control circuit 3 , the control circuit 3 outputs a control signal XGINI in common to the n MOSFETs 24. The control circuit 3 also outputs control signals SEL[k], XSEL[k] in common to the n switch circuits 22 included in the k-th pixel circuit block BLK-k. Note that FIG. 5 is a timing chart focusing on the horizontal scanning period 1H of the i-th row after the horizontal scanning periods 1H of the 1st to (i-1)th rows have ended. Note that the 3n pixel circuits 20 connected to the scanning line 11 of the i-th row are assumed to be included in the k-th pixel circuit block BLK-k.

[0064] As shown in Figure 5, the horizontal scanning period 1H for the i-th row includes an initialization period a, a compensation period b following the initialization period a, and a writing period c following the compensation period b. After the writing period c, there is a light-emitting period d, and after one frame period, the horizontal scanning period 1H for the i-th row begins again. Note that one frame period corresponds to one cycle of the vertical synchronization signal VSYNC, and is the period required to display one frame of the image specified by the image data VID. For example, if the frequency of the vertical synchronization signal VSYNC is 60 Hz, the period of one frame is approximately 16.7 milliseconds.

[0065] As shown in FIG. 5, in the horizontal scanning period 1H of the i-th row, during the initialization period a, the scanning signal XGWR[i] is at the L level. Also, the control signal XGOR[i] is at the L level, and the control signals XGEL[i] and XGCMP[i] are at the H level. Also, the control signals XGINI and XRST are at the L level. Also, the control signal SEL[k] is at the H level, and the control signal XSEL[k] is at the L level. Therefore, as shown in FIG. 6, during the initialization period a, in the pixel circuits 20-1, 20-2, and 20-3, the MOSFETs 203 and 206 are turned on, and the MOSFETs 204 and 205 are turned off. Also, the MOSFETs 24-1, 24-2, and 24-3 are turned on, and the switch circuits 22-1, 22-2, and 22-3 are turned on. Therefore, a potential VINI is supplied from the control circuit 3 to the data transfer lines 17-1, 17-2, and 17-3 via the MOSFETs 24-1, 24-2, and 24-3, and a predetermined potential VINI is supplied from the data transfer lines 17-1, 17-2, and 17-3 to the data lines 12 connected to each of the pixel circuits 20-1, 20-2, and 20-3 via the switch circuits 22-1, 22-2, and 22-3, respectively. Then, in the pixel circuits 20-1, 20-2, and 20-3, the potential VINI is supplied to the gate of the MOSFET 202 and the other end of the capacitance element 201 via the data line 12. Also, a potential V0 is supplied to the anode of the light-emitting element 27 via the power supply line 15. That is, the potentials of the data line 12, the gate of the MOSFET 202, and the other end of the capacitance element 201 are initialized to the potential VINI, and the potential of the anode of the light-emitting element 27 is initialized to the potential V0. Furthermore, a predetermined potential VINI is supplied to one end of each of the capacitive elements 231-5 to 231-9 of the capacitive DAC and the other end of the capacitive element 232, and a potential VRST is supplied to one end of each of the capacitive elements 231-0 to 231-4 and one end of the capacitive element 232, and the charges accumulated in the capacitive elements 231-0 to 231-9 and 232 are initialized.

[0066] As shown in FIG. 5, in the horizontal scanning period 1H of the i-th row, during the compensation period b, the scanning signal XGWR[i] is at the L level. Furthermore, the control signals XGOR[i] and XGCMP[i] are at the L level, and the control signal XGEL[i] is at the H level. Furthermore, the control signals XGINI and XRST are at the H level. Furthermore, the control signal SEL[k] is at the L level, and the control signal XSEL[k] is at the H level. Therefore, as shown in FIG. 7, during the compensation period b, in the pixel circuits 20-1, 20-2, and 20-3, the MOSFETs 203, 204, and 206 are turned on, and the MOSFET 205 is turned off. Furthermore, the MOSFETs 24-1, 24-2, and 24-3 are turned off, and the switch circuits 22-1, 22-2, and 22-3 are turned off. Therefore, in the pixel circuits 20-1, 20-2, and 20-3, a current flows from the power supply line of the potential VEL to the gate of the MOSFET 202 via the MOSFETs 202, 204, and 203, and the potentials of the data line 12, the gate of the MOSFET 202, and the other end of the capacitance element 201 rise from the potential VINI. At this time, the MOSFET 202 is in a state where the gate and the drain are connected, i.e., in a diode-connected state, and therefore, a voltage between the gate and the source of the MOSFET 202 is The voltage at the data line 12 converges to the threshold voltage Vth of the MOSFET 202. Since the MOSFET 202 is a P-channel type, the threshold voltage Vth is a negative voltage. Since the potential VEL is supplied to the source of the MOSFET 202, the potentials at the data line 12, the gate of the MOSFET 202, and the other end of the capacitive element 201 converge to the potential (VEL-|Vth|). In addition, the potential at the anode of the light-emitting element 27 maintains the potential V0.

[0067] As shown in FIG. 5, in the horizontal scanning period 1H of the i-th row, during the writing period c, the scanning signal XGWR[i] is at the L level. Furthermore, the control signal XGOR[i] is at the L level, and the control signals XGCMP[i] and XGEL[i] are at the H level. Furthermore, the control signals XGINI and XRST are at the H level. Furthermore, the control signal SEL[k] is at the H level, and the control signal XSEL[k] is at the L level. Therefore, as shown in FIG. 8, during the writing period c, in the pixel circuits 20-1, 20-2, and 20-3, the MOSFETs 203 and 206 are turned on, and the MOSFETs 204 and 205 are turned off. Furthermore, the data potential generating circuits 23-1, 23-2, and 23-3 generate data potentials VDATA[3j-2], VDATA[3j-1], and VDATA[3j], respectively, and output them to the data transfer lines 17-1, 17-2, and 17-3, respectively. Then, the data potential VDATA[3j-2] is transferred from the data transfer line 17-1 to the data line 12 connected to the pixel circuit 20-1 via the switch circuit 22-1, and in the pixel circuit 20-1, is supplied to the other end of the capacitive element 201 and the gate of the MOSFET 202 via the MOSFET 203. Also, the data potential VDATA[3j-1] is transferred from the data transfer line 17-2 to the data line 12 connected to the pixel circuit 20-2 via the switch circuit 22-2, and in the pixel circuit 20-2, is supplied to the other end of the capacitive element 201 and the gate of the MOSFET 202 via the MOSFET 203. Also, the data potential VDATA[3j] is transferred from the data transfer line 17-3 to the data line 12 connected to the pixel circuit 20-3 via the switch circuit 22-3, and in the pixel circuit 20-3, is supplied to the other end of the capacitive element 201 and the gate of the MOSFET 202 via the MOSFET 203.

[0068] Here, just before the MOSFET 203 and switch circuit 22-1 of the pixel circuit 20-1 are both turned on, the potential of the data line 12 is potential (VEL-|Vth|), and when the MOSFET 203 and switch circuit 22-1 are both turned on, the potential of the data transfer line 17-1 becomes the data potential VDATA[3j-2]. Therefore, due to capacitive coupling between the capacitor 25 and the capacitive elements 231-0 to 231-9, 232 of the data potential generating circuit 23-1, the potential of the data line 12 becomes potential ((Cd·(VEL-|Vth|)+Cst·VDATA[3j-2]) / (Cd+Cst)). Here, Cd is the capacitance value of the capacitor 25, and Cst is the combined capacitance value of the capacitor 25 and the capacitive elements 231-0 to 231-9, 232. Similarly, the potential of the data line 12 connected to the pixel circuit 20-2 becomes the potential ((Cd·(VEL-|Vth|)+Cst·VDATA[3j-1]) / (Cd+Cst)), and the potential of the data line 12 connected to the pixel circuit 20-3 becomes the potential ((Cd·(VEL-|Vth|)+Cst·VDATA[3j]) / (Cd+Cst)). After that, when the scanning signal XGWR[j] becomes the L level, in the pixel circuits 20-1, 20-2, and 20-3, the MOSFETs 203 are turned off, and the potentials of the gates of the MOSFETs 202 are fixed at the above potentials.

[0069] As shown in FIG. 5, in the horizontal scanning period 1H of the i-th row, the scanning signal XGWR[i] is at the H level during the light emission period d. Furthermore, the control signal XGEL[i] is at the L level, and the control signals XGCMP[i] and XGOR[i] are at the H level. Therefore, as shown in FIG. 9, in the light emission period d, in the pixel circuits 20-1, 20-2, and 20-3, the MOSFET 205 is turned on, and the MOSFETs 203, 204, and 206 are turned off. Therefore, a current flowing from the source to the drain of the MOSFET 202 is supplied to the light emitting element 27 via the MOSFET 205, causing the light emitting element 27 to emit light. In the pixel circuit 20-1, the potential of the source of the MOSFET 202 is the potential VEL, and the potential of the gate of the MOSFET 202 is the potential ((C Since the potential of the gate of MOSFET 202 in pixel circuit 20-2 is ((Cd·(VEL−|Vth|)+Cst·VDATA[3j-2]) / (Cd+Cst)), a current according to the data potential VDATA[3j-2] is supplied to light-emitting element 27 while compensating for the threshold voltage Vth of MOSFET 202. Similarly, since the potential of the gate of MOSFET 202 in pixel circuit 20-2 is ((Cd·(VEL−|Vth|)+Cst·VDATA[3j-1]) / (Cd+Cst)), a current according to the data potential VDATA[3j-1] is supplied to light-emitting element 27 while compensating for the threshold voltage Vth of MOSFET 202. Similarly, in pixel circuit 20-3, the potential of the gate of MOSFET 202 is potential ((Cd·(VEL-|Vth|)+Cst·VDATA[3j]) / (Cd+Cst)), so that a current corresponding to the data potential VDATA[3j] is supplied to light-emitting element 27 while compensating for the threshold voltage Vth of MOSFET 202.

[0070] As shown in Figure 5, in the horizontal scanning period 1H of the i+1th row following the horizontal scanning period 1H of the i-th row, the control signals XGEL[i+1], XGOR[i+1], XGCMP[i+1] and the scanning signal XGWR[i+1] have waveforms that are shifted by a time equivalent to the cycle of the horizontal scanning period 1H from the control signals XGEL[i], XGOR[i], XGCMP[i] and the scanning signal XGWR[i].

[0071] 1-1-5. Display panel structure Fig. 10 is a cross-sectional view schematically showing a portion of the display panel 2. As shown in Fig. 10, the display panel 2 includes, for example, a substrate 50, interlayer insulating layers 54, 55, 56, and 57, a wiring layer 58, a reflective layer 59, an insulating layer 30, an organic EL element 40, an insulating layer 60, a sealing layer 70, a colored layer 80, and a counter substrate 90.

[0072] The substrate 50 is, for example, a silicon substrate. The substrate 50 is provided with impurity regions 51 into which impurities are ion-implanted. The impurity regions 51 function as the sources or drains of the above-mentioned MOSFETs 202 to 206. A gate insulating layer 52 is provided on the substrate 50. The gate insulating layer 52 is made of, for example, silicon oxide. A gate electrode 53 is provided on the gate insulating layer 52. The gate electrode 53 is made of, for example, metal or polysilicon. The gate electrode 53 functions as the gate of the above-mentioned MOSFETs 202 to 206.

[0073] The interlayer insulating layer 54 covers the gate insulating layer 52 and the gate electrode 53. The interlayer insulating layers 54, 55, 56, and 57 are stacked in this order from the substrate 50 side. The interlayer insulating layers 54, 55, 56, and 57 are, for example, silicon oxide layers.

[0074] The wiring layer 58 is provided on the interlayer insulating layer 54, the interlayer insulating layer 55, and the interlayer insulating layer 56. The material of the wiring layer 58 is, for example, a metal such as aluminum or copper.

[0075] The reflective layer 59 is provided on the interlayer insulating layer 57. The reflective layer 59 is provided for each of the sub-pixels SP. Two sub-pixels SP are shown in FIG. 10. The reflective layer 59 is made of a metal such as aluminum. The reflective layer 59 reflects light generated by the organic EL element 40 and directed toward the substrate 50, toward the colored layer 80.

[0076] The insulating layer 30 is provided on the reflective layer 59. The insulating layer 30 has different thicknesses for the red subpixel SP, the green subpixel SP, and the blue subpixel SP. The insulating layer 30 has, for example, a stacked structure in which multiple layers are stacked. The insulating layer 30 has different numbers of stacked layers for the red subpixel SP, the green subpixel SP, and the blue subpixel SP. The insulating layer 30 is, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like.

[0077] The organic EL element 40 is provided on the insulating layer 30. The organic EL element 40 is, for example, an OLED, and functions as the above-mentioned light-emitting element 27. The organic EL element 40 has a pixel electrode 41, a light-emitting functional layer 42, and a common electrode 43.

[0078] The pixel electrode 41 is provided on the insulating layer 30. The pixel electrode 41 is provided for each of the plurality of sub-pixels SP. The pixel electrode 41 transmits light generated in the light-emitting functional layer 42. The pixel electrode 41 is a transparent electrode made of, for example, ITO. The pixel electrode 41 is one of the electrodes for injecting current into the light-emitting functional layer 42. ITO is an abbreviation for Indium Tin Oxide.

[0079] The light-emitting functional layer 42 is provided on the pixel electrode 41. The light-emitting functional layer 42 is provided continuously in a plurality of sub-pixels SP. The light-emitting functional layer 42 is configured, for example, by stacking a plurality of light-emitting layers. The light-emitting functional layer 42 emits, for example, white light.

[0080] The common electrode 43 is provided on the light-emitting functional layer 42. The common electrode 43 is a common electrode provided continuously in the plurality of sub-pixels SP. The material of the common electrode 43 is, for example, an alloy of magnesium and silver. The common electrode 43 is the other electrode for injecting a current into the light-emitting functional layer 42.

[0081] The common electrode 43, the insulating layer 30, and the reflective layer 59 form an optical resonance structure. The thickness of the insulating layer 30 is adjusted so as to form a standing wave of a predetermined wavelength between the reflective layer 59 and the common electrode 43. This allows light of a predetermined wavelength to be emitted from the organic EL element 40 for each of the multiple sub-pixels SP.

[0082] The insulating layer 60 is provided on the pixel electrode 41. The insulating layer 60 is, for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0083] An opening 62 is formed in the insulating layer 60. The opening 62 penetrates the insulating layer 60. The insulating layer 60 defines the light-emitting region 44 of the organic EL element 40. The light-emitting region 44 is a region that overlaps with the opening 62 of the organic EL element 40 in a plan view.

[0084] The sealing layer 70 is provided on the common electrode 43. The sealing layer 70 is continuous in the plurality of sub-pixels SP. The sealing layer 70 is configured by stacking, for example, an inorganic layer and an organic layer. The sealing layer 70 may have a structure in which an organic layer is sandwiched between a pair of inorganic layers. The inorganic layer is, for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The inorganic layer protects the light-emitting functional layer 42 from moisture, oxygen, and the like. The organic layer is, for example, an acrylic or other resin layer. The organic layer improves the flatness of the upper surface of the sealing layer 70.

[0085] The colored layer 80 is provided on the sealing layer 70. The colored layer 80 is a color filter configured to transmit light of a predetermined wavelength in each of the red sub-pixels SP, the green sub-pixels SP, and the blue sub-pixels SP. The material of the colored layer 80 is, for example, a color resist.

[0086] The counter substrate 90 is provided on the colored layer 80. In the illustrated example, the counter substrate 90 is adhered to the colored layer 80 by an adhesive layer 92. The counter substrate 90 and the adhesive layer 92 transmit light emitted from the colored layer 80. The counter substrate 90 functions as a protective substrate that protects the organic EL elements 40 and the colored layer 80.

[0087] The display panel 2 is manufactured using, for example, a known semiconductor manufacturing process.

[0088] In this embodiment, as described above, the m×3n pixel circuits 20 included in the display panel 2 are divided into q pixel circuit blocks BLK-1 to BLK-q, and each pixel circuit block BLK-k includes p×n light-emitting elements 27, p×n pixel circuits 20, and n switch circuits 22 corresponding to the p×n red sub-pixels SP. Each pixel circuit block BLK-k also includes p×n light-emitting elements 27, p×n pixel circuits 20, and n switch circuits 22 corresponding to the p×n blue sub-pixels SP. Each pixel circuit block BLK-k also includes p×n light-emitting elements 27, p×n pixel circuits 20, and n switch circuits 22 corresponding to the p×n green sub-pixels SP. Therefore, each pixel circuit block BLK-k includes p×3n light-emitting elements 27, p×3n pixel circuits 20, and 3n switch circuits 22.

[0089] Meanwhile, in the display region 112 of the display panel 2, m×n pixels P are arranged in m rows and n columns, so that n pixels P are arranged at equal intervals in each row in the X-axis direction and m pixels P are arranged at equal intervals in each column in the Y-axis direction. Each pixel P is composed of three light-emitting elements 27 corresponding to red, blue, and green subpixels SP. Therefore, by matching the size of the arrangement area of ​​p×3n pixel circuits 20 and 3n switch circuits 22 included in each pixel circuit block BLK-k with the arrangement area of ​​p×3n light-emitting elements 27 included in that pixel circuit block BLK-k, the layout area of ​​the display panel 2 is reduced.

[0090] 11 is a plan view showing a layout configuration example of a portion of pixel circuit blocks BLK-1 and BLK-2. FIG. 11 illustrates only a portion of the layout of pixel circuit blocks BLK-1 and BLK-2 corresponding to one column of pixels P. In FIG. 11, the light-emitting elements 27 corresponding to the red, blue, and green sub-pixels SP are identified as light-emitting elements 27R, 27B, and 27G, respectively. The pixel circuits 20 are identified as pixel circuits 20R, 20B, and 20G, respectively. The switch circuits 22 connected to the pixel circuits 20R, 20B, and 20G, respectively, are identified as switch circuits 22R, 22B, and 22G, respectively. The data lines 12 connected to the switch circuits 22R, 22B, and 22G, respectively, are identified as data lines 12R, 12B, and 12G, respectively.

[0091] 11, as shown in L1, pixel circuit block BLK-1 includes p pixel arrangement areas PA. The p pixel arrangement areas PA are provided adjacent to each other in the Y-axis direction. For convenience, in Fig. 11, the p pixel arrangement areas PA are distinguished as PA-1 to PA-p, but the layout of the p pixel arrangement areas PA is the same, and light emitting elements 27R, 27B, and 27G are arranged in the pixel arrangement areas PA.

[0092] Furthermore, as shown in L2, pixel circuit block BLK-1 includes p pixel circuit arrangement areas CA. The p pixel circuit arrangement areas CA are provided adjacent to each other in the Y-axis direction in a layer lower than the p pixel circuit arrangement areas PA. In Fig. 11, for convenience, the p pixel circuit arrangement areas CA are distinguished as CA-1 to CA-p, but the layout of the p pixel circuit arrangement areas CA is the same, and in each pixel circuit arrangement area CA, three pixel circuits 20R, 20B, and 20G are arranged adjacent to each other in the X-axis direction.

[0093] 11, the pixel circuit block BLK-1 includes one switch circuit arrangement region SA. The switch circuit arrangement region SA is provided adjacent to the pixel circuit arrangement region CA-p in the Y-axis direction in a layer lower than the p pixel circuit arrangement regions PA, and three switch circuits 22R, 22B, and 22G are arranged in the switch circuit arrangement region SA adjacent to each other in the X-axis direction and adjacent to the three pixel circuits 20R, 20B, and 20G of the pixel circuit arrangement region CA-p in the Y-axis direction.

[0094] 11 , in pixel circuit block BLK-1, data line 12R, which is the data line 12 in the 3j-2th column extending in the Y-axis direction, data line 12B, which is the data line 12 in the 3j-1th column extending in the Y-axis direction, and data line 12R, which is the data line 12 in the 3j-1th column extending in the Y-axis direction, are arranged. Data line 12R is supplied with a data potential VDATA[3j-2], which is a signal for causing each of p light-emitting elements 27R to emit light, via switch circuit 22R; data line 12B is supplied with a data potential VDATA[3j-1], which is a signal for causing each of p light-emitting elements 27B to emit light, via switch circuit 22B; and data line 12G is supplied with a data potential VDATA[3j], which is a signal for causing each of p light-emitting elements 27G to emit light, via switch circuit 22G. The data line 12R is arranged to overlap p pixel circuits 20R and switch circuits 22R, and the p pixel circuits 20R and switch circuits 22R are connected to the data line 12R. The data line 12B is arranged to overlap p pixel circuits 20B and switch circuits 22B, and the p pixel circuits 20B and switch circuits 22B are connected to the data line 12B. The data line 12G is arranged to overlap p pixel circuits 20G and switch circuits 22G, and the p pixel circuits 20G and switch circuits 22G are connected to the data line 12.

[0095] 11, pixel circuit block BLK-2 is disposed adjacent to pixel circuit block BLK-1 in the Y-axis direction. The layout of pixel circuit block BLK-1 and the layout of pixel circuit block BLK-2 are exactly the same.

[0096] 11, as shown in L1, the pixel circuit block BLK-2 includes p pixel arrangement areas PA-1 to PA-p, and as shown in L2, the pixel circuit block BLK-2 includes p pixel circuit arrangement areas CA-1 to CA-p and a switch circuit arrangement area SA. Also, as shown in L2 in FIG. 11, in the pixel circuit block BLK-2, a data line 12R that is the data line 12 in the 3j-2th column extending in the Y-axis direction is arranged, a data line 12B that is the data line 12 in the 3j-1th column extending in the Y-axis direction is arranged, and a data line 12R that is the data line 12 in the 3j-1th column extending in the Y-axis direction is arranged. The data line 12R included in the pixel circuit block BLK-2 is adjacent to the data line 12R included in the pixel circuit block BLK-1 along the Y-axis direction. Similarly, the data line 12B included in the pixel circuit block BLK-2 is adjacent to the data line 12B included in the pixel circuit block BLK-1 along the Y-axis direction. Similarly, the data line 12G included in the pixel circuit block BLK-2 is adjacent to the data line 12G included in the pixel circuit block BLK-1 along the Y-axis direction.

[0097] The data line 12R is supplied with a data potential VDATA[3j-2], which is a signal for causing each of the p light-emitting elements 27R to emit light, via a switch circuit 22R. The data line 12B is supplied with a data potential VDATA[3j-1], which is a signal for causing each of the p light-emitting elements 27B to emit light, via a switch circuit 22B. The data line 12G is supplied with a data potential VDATA[3j], which is a signal for causing each of the p light-emitting elements 27G to emit light, via a switch circuit 22G. The data line 12R is arranged to overlap with the p pixel circuits 20R and the switch circuit 22R, and the p pixel circuits 20R and the switch circuit 22R are connected to the data line 12R. The data line 12B is arranged to overlap with the p pixel circuits 20B and the switch circuit 22B, and the p pixel circuits 20B and the switch circuit 22B are connected to the data line 12B. The data line 12G is arranged so as to overlap with p pixel circuits 20G and switch circuits 22G, and the p pixel circuits 20G and switch circuits 22G are connected to the data line 12.

[0098] Although not shown in the figure, each of the pixel circuit blocks BLK-1 and BLK-2 has In the pixel circuit arrangement region, p pixel arrangement regions PA-1 to PA-p are arranged in n columns adjacent to each other in the X-axis direction, and p pixel circuit arrangement regions CA-1 to CA-p and switch circuit arrangement region SA are arranged in n columns adjacent to each other in the X-axis direction. Furthermore, pixel circuit blocks BLK-3 to BLK-q are arranged adjacent to pixel circuit block BLK-2 in the Y-axis direction in this order. The layout of pixel circuit blocks BLK-3 to BLK-q is also exactly the same as the layout of pixel circuit blocks BLK-1 and BLK-2.

[0099] 11, in pixel circuit block BLK-1, p light-emitting elements 27R are arranged at a first pitch w1 in the Y-axis direction, and p pixel circuits 20R are arranged at a second pitch w2 in the Y-axis direction. Similarly, p light-emitting elements 27B are arranged at a first pitch w1 in the Y-axis direction, and p pixel circuits 20B are arranged at a second pitch w2 in the Y-axis direction. Similarly, p light-emitting elements 27G are arranged at a first pitch w1 in the Y-axis direction, and p pixel circuits 20G are arranged at a second pitch w2 in the Y-axis direction. The first pitch w1 matches the width of one pixel arrangement area PA in the Y-axis direction, and the second pitch w2 matches the width of one pixel circuit arrangement area CA in the Y-axis direction.

[0100] Here, because the second pitch w2 is smaller than the first pitch w1, the width w2×p in the Y-axis direction of p pixel circuit arrangement areas CA is smaller than the width w1×p in the Y-axis direction of p pixel circuit arrangement areas PA. The difference between these two widths is equal to the product (w1-w2)×p of the difference (w1-w2) between the first pitch w1 and the second pitch w2 and the number p of light-emitting elements 27R, and therefore, by matching the width w3 in the Y-axis direction of the switch circuit arrangement area SA to (w1-w2)×p, the width in the Y-axis direction of the area consisting of p pixel circuit arrangement areas PA and the width in the Y-axis direction of the area consisting of p pixel circuit arrangement areas CA and switch circuit arrangement area SA will match.

[0101] In addition, in a plan view, the switch circuit 22R overlaps with at least one of the p light-emitting elements 27R, the switch circuit 22B overlaps with at least one of the p light-emitting elements 27B, and the switch circuit 22G overlaps with at least one of the p light-emitting elements 27G. Specifically, in a plan view, the switch circuits 22R, 22B, and 22G overlap with the light-emitting elements 27R, 27B, and 27G arranged in the pixel arrangement area PA-p, respectively.

[0102] Furthermore, in a plan view, the switch circuit 22R is arranged in a region between the arrangement region of the p pixel circuits 20R included in the pixel circuit block BLK-1 and the arrangement region of the p pixel circuits 20R included in the pixel circuit block BLK-2. Similarly, in a plan view, the switch circuit 22B is arranged in a region between the arrangement region of the p pixel circuits 20B included in the pixel circuit block BLK-1 and the arrangement region of the p pixel circuits 20B included in the pixel circuit block BLK-2. Similarly, in a plan view, the switch circuit 22G is arranged in a region between the arrangement region of the p pixel circuits 20G included in the pixel circuit block BLK-1 and the arrangement region of the p pixel circuits 20G included in the pixel circuit block BLK-2.

[0103] Note that, since the first pitch w1 and the second pitch w2 are different, the larger the value of s, the greater the positional deviation in the Y-axis direction between the pixel arrangement area PA-s and the pixel circuit arrangement area CA-s, where s is an integer between 1 and p.

[0104] On the other hand, the pixel electrode 41, which is the anode of the light-emitting element 27R arranged in the pixel arrangement region PA-s, is connected to the drains of the MOSFETs 205 and 206 of the pixel circuit 20R arranged in the pixel circuit arrangement region CA-s. Similarly, the pixel electrode 41, which is the anode of the light-emitting element 27B arranged in the pixel arrangement region PA-s, is connected to the drains of the MOSFETs 205 and 206 of the pixel circuit 20B arranged in the pixel circuit arrangement region CA-s. Similarly, the pixel electrode 41, which is the anode of the light-emitting element 27G arranged in the pixel arrangement region PA-s, is connected to the drains of the MOSFETs 205 and 206 of the pixel circuit 20G arranged in the pixel circuit arrangement region CA-s. Therefore, in this embodiment, as shown in FIG. 12 , For each pixel circuit arrangement area CA-s, the positions of vias 208R, 208B, and 208G that connect the three anodes of light-emitting elements 27R, 27B, and 27G to the three wirings 209R, 209B, and 209G that are connected to the drains of MOSFETs 205 and 206 of pixel circuits 20R, 20B, and 20G, respectively, are shifted.

[0105] Fig. 12 is a plan view showing a detailed layout of a portion of each pixel circuit block BLK-k, with the same reference numerals assigned to the same components as in Fig. 11. In Fig. 12, as shown in L2, three wirings 209R, 209B, and 209G are provided in an upper wiring layer for each of p pixel circuit arrangement areas CA-1 to CA-p. That is, each pixel circuit block BLK-k is provided with p wirings 209R, 209B, and 209R extending in the Y-axis direction. The p wirings 209R have the same shape and are arranged at a second pitch w2 in the Y-axis direction. Similarly, the p wirings 209B have the same shape and are arranged at a second pitch w2 in the Y-axis direction. Similarly, the p wirings 209G have the same shape and are arranged at a second pitch w2 in the Y-axis direction.

[0106] 12, as shown in L1 and L2, each of the p light-emitting elements 27R overlaps with one of the p wirings 209R in the Z-axis direction, and a via 208R is disposed in the overlapping region. Similarly, each of the p light-emitting elements 27B overlaps with one of the p wirings 209B in the Z-axis direction, and a via 208B is disposed in the overlapping region. Similarly, each of the p light-emitting elements 27G overlaps with one of the p wirings 209G in the Z-axis direction, and a via 208G is disposed in the overlapping region. Therefore, the relative positions of the wirings 209R, 209B, 209G and the vias 208R, 208B, 208G differ between the pixel arrangement region PA and the pixel circuit arrangement region CA. In this way, by arranging p vias 208R, p vias 208B, and p vias 208G in a staggered manner in each pixel circuit block BLK-k, it is possible to arrange p wirings 209R, p wirings 209B, and p wirings 209G in the area consisting of pixel circuit arrangement areas CA-1 to CA-p and switch circuit arrangement area SA, thereby suppressing an increase in the layout area due to these wirings.

[0107] Furthermore, if the width w3 = (w1 - w2) × p of the switch circuit arrangement area SA is less than or equal to the first pitch w1, p pixel arrangement areas PA-1 to PA-p can have the same layout, p pixel circuit arrangement areas CA-1 to CA-p can have the same layout, and p vias 208R, p vias 208B, and p vias 208G can be arranged with their positions shifted.

[0108] 12, in each pixel circuit block BLK-k, wiring lines 222R, 222B, and 222G connected to the input terminals of switch circuits 22R, 22B, and 22G are provided in switch circuit arrangement region SA. Furthermore, as shown in L3, data transfer lines 17R, 17B, and 17G are arranged in a wiring layer between the pixel circuit arrangement regions CA-1 to CA-p and switch circuit arrangement region SA and the pixel arrangement regions PA-1 to PA-p, extending in the Y-axis direction. Furthermore, as shown in L2 and L3, in each pixel circuit block BLK-k, vias 221R, 221B, and 221G connecting the data transfer lines 17R, 17B, and 17G to wiring lines 222R, 222B, and 222G, respectively, are provided at positions overlapping with switch circuit arrangement region SA in the Z-axis direction. In this way, in each pixel circuit block BLK-k, the data transfer lines 17R, 17B, 17G are arranged so as to overlap, in a plan view, the area consisting of the pixel circuit arrangement areas CA-1 to CA-p and the switch circuit arrangement area SA, and the pixel arrangement areas PA-1 to PA-p, and by arranging the vias 221R, 221B, 221G in positions that overlap the switch circuit arrangement area SA, an increase in the layout area due to connection with the data transfer lines 17R, 17B, 17G is suppressed.

[0109] In the first embodiment, the p light-emitting elements 27R in the 3j-2 column included in the pixel circuit block BLK-1 are an example of the "plurality of first light-emitting elements," and the p light-emitting elements 27R in the 3j-2 column included in the pixel circuit block BLK-2 are an example of the "plurality of second light-emitting elements." Furthermore, the p pixel circuits 20R in the 3j-2 column included in the pixel circuit block BLK-1 are an example of the "plurality of first pixel circuits," and the p pixel circuits 20R in the 3j-2 column included in the pixel circuit block BLK-2 are an example of the "plurality of second pixel circuits." Furthermore, the switch circuit 22R in the 3j-2 column included in the pixel circuit block BLK-1 is an example of the "first switch circuit," and the switch circuit 22R in the 3j-2 column included in the pixel circuit block BLK-2 is an example of the "second switch circuit." Furthermore, the data line 12R in the 3j-2th column included in the pixel circuit block BLK-1 is an example of a “first data line,” and the data line 12R in the 3j-2th column included in the pixel circuit block BLK-2 is an example of a “second data line.” Furthermore, the Y-axis direction is an example of a “first direction.”

[0110] 1-1-6.Effects As described above, in the display device 1 of the first embodiment, m pixel circuits 20 in the same column are not commonly connected to the data transfer line 17, but p pixel circuits 20 included in each pixel circuit block BLK-k are connected to the data line 12 branching from the data transfer line 17 via the switch circuit 22. Therefore, the p pixel circuits 20 become loads connected to the data line 12, but the np pixel circuits 20 do not become loads connected to the data line 12, thereby reducing the load on the data line 12. Furthermore, while the switch circuit 22 included in each pixel circuit block BLK-k becomes loads connected to the data transfer line 17, the m pixel circuits 20 do not become loads connected to the data transfer line 17, thereby also reducing the load on the data transfer line 17. Therefore, according to the display device 1 of the first embodiment, each data transfer line 17 and each data line 12 can be driven at high speed, making it possible to display high-definition images, for example.

[0111] Furthermore, in the display device 1 of the first embodiment, in each pixel circuit block BLK-k, the switch circuit 22 overlaps with at least one of the p light-emitting elements 27 in a planar view. In particular, by making the second pitch w2 at which the p pixel circuits 20 are arranged in the Y-axis direction smaller than the first pitch w1 at which the p light-emitting elements 27 are arranged in the Y-axis direction, the switch circuit 22 can be arranged in a switch circuit arrangement area SA, which is the area consisting of the p pixel circuit arrangement areas PA excluding the area consisting of the p pixel circuit arrangement areas CA, in a planar view. Therefore, the display device 1 of the first embodiment prevents an increase in the layout area of ​​the display panel 2 due to the switch circuit 22. In this embodiment, when the switch circuit 22 overlaps with the light-emitting elements 27 in a planar view, for example, any of the source, gate, and drain of the N-channel MOSFET, the source, gate, and drain of the P-channel MOSFET, and wiring for electrically connecting them, which constitute the switch circuit 22, overlaps with the light-emitting region of the light-emitting element 27 in a planar view.

[0112] 1-2. Second embodiment Hereinafter, for the display device 1 of the second embodiment, the same symbols will be used for configurations similar to those of the first embodiment, and explanations similar to those of the first embodiment will be omitted or simplified, with the main focus being on the differences from the first embodiment.

[0113] The perspective view of the display device 1 of the second embodiment is the same as FIG. 1, and the plan view of the display panel 2 of the second embodiment is the same as FIG. 2, so illustration and description thereof will be omitted.

[0114] 13 is a block diagram showing the electrical configuration of the display device 1 of the second embodiment. The electrical connection relationship of the display device 1 of the second embodiment is similar to that of the display device 1 of the first embodiment shown in FIG. 3, but as shown in FIG. 13, the physical positions of 3n switch circuits 22 in each pixel circuit block BLK-k are different from those of the display device 1 of the first embodiment. k is 1 or more and q j is an integer between 1 and n. Specifically, in each pixel circuit block BLK-k, the switch circuit 22 that controls the electrical connection between the data line 12 connected to p pixel circuits 20 in the 3j-2 column and the data transfer line 17 in the 3j-2 column is disposed between two pixel circuits 20 included in the p pixel circuits 20. Similarly, the switch circuit 22 that controls the electrical connection between the data line 12 connected to p pixel circuits 20 in the 3j-1 column and the data transfer line 17 in the 3j-1 column is disposed between two pixel circuits 20 included in the p pixel circuits 20. Similarly, the switch circuit 22 that controls the electrical connection between the data line 12 connected to p pixel circuits 20 in the 3j-1 column and the data transfer line 17 in the 3j-1 column is disposed between two pixel circuits 20 included in the p pixel circuits 20. j is an integer between 1 and n, inclusive.

[0115] The pixel circuit 20 and the data potential generating circuit 23 are configured in the same manner as in FIG. 4, and therefore will not be illustrated or described again.

[0116] Fig. 14 is a plan view showing an example of the layout configuration of part of the pixel circuit blocks BLK-1 and BLK-2 in the second embodiment. In Fig. 14, only part of the layout corresponding to one column of pixels P in the pixel circuit blocks BLK-1 and BLK-2 is shown.

[0117] In FIG. 14, as shown by L1, p pixel arrangement areas PA-1 to PA-p are provided adjacent to each other in the Y-axis direction in the pixel circuit block BLK-1, similar to FIG.

[0118] 14, in the pixel circuit block BLK-1, in a layer lower than the pixel circuit arrangement areas PA-1 to PA-p, t pixel circuit arrangement areas CA-1 to CA-t are arranged adjacent to each other in the Y-axis direction, and pt pixel circuit arrangement areas CA-(t+1) to CA-p are arranged adjacent to each other in the Y-axis direction, with a switch circuit arrangement area SA being provided between the pixel circuit arrangement areas CA-t and CA-(t+1). t is a predetermined integer between 1 and p-1. As in FIG. 11, the layout of the p pixel circuit arrangement areas CA is the same, and three pixel circuits 20R, 20B, and 20G are arranged adjacent to each other in the X-axis direction in the pixel circuit arrangement area CA.

[0119] In the switch circuit arrangement area SA, three switch circuits 22R, 22B, and 22G are arranged adjacent to each other in the X-axis direction, adjacent to the three pixel circuits 20R, 20B, and 20G in the pixel circuit arrangement area CA-t in the Y-axis direction, and adjacent to the three pixel circuits 20R, 20B, and 20G in the pixel circuit arrangement area CA-(t+1) in the Y-axis direction. That is, in a planar view, the switch circuit 22R is arranged in a region between two pixel circuits 20R out of the p pixel circuits 20R. Similarly, in a planar view, the switch circuit 22B is arranged in a region between two pixel circuits 20B out of the p pixel circuits 20B. Similarly, in a planar view, the switch circuit 22G is arranged in a region between two pixel circuits 20G out of the p pixel circuits 20G.

[0120] In this way, by providing the switch circuit arrangement region SA between the pixel circuit arrangement region CA-t and the pixel circuit arrangement region CA-(t+1), the distance from the switch circuits 22R, 22B, and 22G to the pixel circuits 20R, 20B, and 20G at the ends in the Y-axis direction is shorter than in the first embodiment, which reduces the difference in time constant when writing data to each pixel P and reduces unevenness in the image displayed in the display region 112. Note that, in order to minimize the difference in time constant when writing data to each pixel P, it is preferable that t=p / 2, where p is an even number. In other words, it is preferable that the switch circuit arrangement region SA is provided so as to overlap with the center in the Y-axis direction of the region consisting of p pixel arrangement regions PA-1 to PA-p.

[0121] 14, in the pixel circuit block BLK-1, the data line 12R in the 3j-2th column extending in the Y-axis direction is connected to p pixel circuits 20R and switches 20R-2. In pixel circuit block BLK-1, a data line 12B in the 3j-1-th column extending in the Y-axis direction is arranged to overlap with p pixel circuits 20B and switch circuits 22B, and the p pixel circuits 20B and switch circuits 22B are connected to the data line 12B. In pixel circuit block BLK-1, a data line 12G in the 3j-1-th column extending in the Y-axis direction is arranged to overlap with p pixel circuits 20G and switch circuits 22G, and the p pixel circuits 20G and switch circuits 22G are connected to the data line 12G.

[0122] As shown in FIG. 14, pixel circuit block BLK-2 is arranged adjacent to pixel circuit block BLK-1 in the Y-axis direction. The layout of pixel circuit block BLK-1 and the layout of pixel circuit block BLK-2 are exactly the same. Although not shown, in each of pixel circuit blocks BLK-1 and BLK-2, p pixel arrangement regions PA-1 to PA-p are arranged in n columns adjacent to each other in the X-axis direction, and p pixel circuit arrangement regions CA-1 to CA-p and switch circuit arrangement region SA are arranged in n columns adjacent to each other in the X-axis direction. Furthermore, pixel circuit blocks BLK-3 to BLK-q are arranged adjacent to pixel circuit block BLK-2 in the Y-axis direction in this order. The layout of pixel circuit blocks BLK-3 to BLK-q is also exactly the same as the layout of pixel circuit blocks BLK-1 and BLK-2.

[0123] In the second embodiment, as in the first embodiment, in pixel circuit block BLK-1, the second pitch w2 at which p pixel circuits 20R are arranged in the Y-axis direction is smaller than the first pitch w1 at which p light-emitting elements 27R are arranged in the Y-axis direction. Therefore, by matching the width w3 in the Y-axis direction of the switch circuit arrangement area SA to (w1-w2)×p, the width in the Y-axis direction of the area consisting of p pixel circuit arrangement areas PA and the width in the Y-axis direction of the area consisting of p pixel circuit arrangement areas CA and switch circuit arrangement area SA match. s is an integer between 1 and p.

[0124] Furthermore, in a plan view, the switch circuit 22R overlaps with at least one of the p light-emitting elements 27R, the switch circuit 22B overlaps with at least one of the p light-emitting elements 27B, and the switch circuit 22G overlaps with at least one of the p light-emitting elements 27G. Specifically, in a plan view, the switch circuit 22B overlaps with the light-emitting element 27B arranged in the pixel arrangement region PA-t, and the switch circuits 22R and 22G overlap with the light-emitting elements 27R and 27G arranged in the pixel arrangement region PA-(t+1), respectively.

[0125] In the second embodiment, as in the first embodiment, as shown in FIG. 15, the positions of vias 208R, 208B, 208G that connect the three anodes of light-emitting elements 27R, 27B, 27G to the three wirings 209R, 209B, 209G that are connected to the drains of MOSFETs 205, 206 of pixel circuits 20R, 20B, 20G, respectively, are shifted for each pixel arrangement area PA-s and pixel circuit arrangement area CA-s.

[0126] FIG. 15 is a plan view showing a detailed layout of a portion of each pixel circuit block BLK-k, with the same reference numerals assigned to the same components as in FIG. 14. In FIG. 15, as shown in L2, three wirings 209R, 209B, and 209G are provided in an upper wiring layer for each of p pixel circuit arrangement areas CA-1 to CA-p. That is, each pixel circuit block BLK-k is provided with p wirings 209R, 209B, and 209R extending in the Y-axis direction. The p wirings 209R have the same shape and are arranged at a second pitch w2 in the Y-axis direction. Similarly, the p wirings 209B have the same shape and are arranged at a second pitch w2 in the Y-axis direction. Similarly, the p wirings 209G have the same shape and are arranged at a second pitch w2 in the Y-axis direction.

[0127] 15, as shown in L1 and L2, each of the p light-emitting elements 27R overlaps with one of the p wirings 209R in the Z-axis direction, and a via 208R is disposed in the overlapping region. Similarly, each of the p light-emitting elements 27B overlaps with one of the p wirings 209B in the Z-axis direction, and a via 208B is disposed in the overlapping region. Similarly, each of the p light-emitting elements 27G overlaps with one of the p wirings 209G in the Z-axis direction, and a via 208G is disposed in the overlapping region. Therefore, the relative positions of the wirings 209R, 209B, 209G and the vias 208R, 208B, 208G differ between the pixel arrangement region PA and the pixel circuit arrangement region CA. In this way, by arranging p vias 208R, p vias 208B, and p vias 208G in a staggered manner in each pixel circuit block BLK-k, it is possible to arrange p wirings 209R, p wirings 209B, and p wirings 209G in the area consisting of pixel circuit arrangement areas CA-1 to CA-p and switch circuit arrangement area SA, thereby suppressing an increase in the layout area due to these wirings.

[0128] Furthermore, if the width w3 = (w1 - w2) × p of the switch circuit arrangement area SA is less than or equal to the first pitch w1, p pixel arrangement areas PA-1 to PA-p can have the same layout, p pixel circuit arrangement areas CA-1 to CA-p can have the same layout, and p vias 208R, p vias 208B, and p vias 208G can be arranged with their positions shifted.

[0129] 15, in each pixel circuit block BLK-k, wiring lines 222R, 222B, and 222G connected to the input terminals of switch circuits 22R, 22B, and 22G are provided in switch circuit arrangement region SA. Furthermore, as shown in L3, data transfer lines 17R, 17B, and 17G are arranged in a wiring layer between the pixel circuit arrangement regions CA-1 to CA-p and switch circuit arrangement region SA and the pixel arrangement regions PA-1 to PA-p, extending in the Y-axis direction. Furthermore, as shown in L2 and L3, in each pixel circuit block BLK-k, vias 221R, 221B, and 221G connecting the data transfer lines 17R, 17B, and 17G to wiring lines 222R, 222B, and 222G, respectively, are provided at positions overlapping with switch circuit arrangement region SA in the Z-axis direction. In this way, in each pixel circuit block BLK-k, the data transfer lines 17R, 17B, 17G are arranged so as to overlap, in a plan view, the area consisting of the pixel circuit arrangement areas CA-1 to CA-p and the switch circuit arrangement area SA, and the pixel arrangement areas PA-1 to PA-p, and by arranging the vias 221R, 221B, 221G in positions that overlap the switch circuit arrangement area SA, an increase in the layout area due to connection with the data transfer lines 17R, 17B, 17G is suppressed.

[0130] In the second embodiment, the p light-emitting elements 27R in the 3j-2 column included in the pixel circuit block BLK-1 are an example of the "plurality of first light-emitting elements," and the p light-emitting elements 27R in the 3j-2 column included in the pixel circuit block BLK-2 are an example of the "plurality of second light-emitting elements." Furthermore, the p pixel circuits 20R in the 3j-2 column included in the pixel circuit block BLK-1 are an example of the "plurality of first pixel circuits," and the p pixel circuits 20R in the 3j-2 column included in the pixel circuit block BLK-2 are an example of the "plurality of second pixel circuits." Furthermore, the switch circuit 22R in the 3j-2 column included in the pixel circuit block BLK-1 is an example of the "first switch circuit," and the switch circuit 22R in the 3j-2 column included in the pixel circuit block BLK-2 is an example of the "second switch circuit." Furthermore, the data line 12R in the 3j-2th column included in the pixel circuit block BLK-1 is an example of a “first data line,” and the data line 12R in the 3j-2th column included in the pixel circuit block BLK-2 is an example of a “second data line.” Furthermore, the Y-axis direction is an example of a “first direction.”

[0131] According to the display device 1 of the second embodiment described above, the same effects as those of the display device 1 of the first embodiment can be obtained. Furthermore, in the display device 1 of the second embodiment, each pixel circuit block BLK In -k, by arranging the switch circuit arrangement area SA between two pixel circuit arrangement areas CA, the distance from each switch circuit 22 to each pixel circuit 20 at the end in the Y-axis direction is shortened, so that the difference in time constant when writing data to each pixel P is reduced, and unevenness in the image displayed in the display area 112 is reduced.

[0132] 2.Electronic equipment A head-mounted display will be described as an example of the electronic device of this embodiment. Fig. 16 is a perspective view that schematically shows a head-mounted display 900, which is an example of the electronic device of this embodiment.

[0133] As shown in Fig. 16, the head mounted display 900 is a head-mounted display that has an appearance similar to glasses. The head mounted display 900 is worn on the head of an observer. The observer is a user who uses the head mounted display 900. The head mounted display 900 allows the observer to view image light formed by a virtual image, and also allows the observer to view an external world image in a see-through manner.

[0134] The head mounted display 900 has, for example, a first display unit 910a, a second display unit 910b, a frame 920, a first temple 930a, and a second temple 930b.

[0135] The first display unit 910a and the second display unit 910b display images. Specifically, the first display unit 910a displays a virtual image for the observer's right eye. The second display unit 910b displays a virtual image for the observer's left eye. The display units 910a and 910b each include, for example, an image forming device 911 and a light guide device 915.

[0136] The image forming device 911 forms image light. The image forming device 911 has an optical system, such as a light source and a projection device, and an external member 912. The external member 912 houses the light source and the projection device.

[0137] The light guide device 915 covers the viewer's eyes. The light guide device 915 guides the image light formed by the image forming device 911, and allows the viewer to view the image light overlapping with external light.

[0138] The frame 920 supports the first display unit 910a and the second display unit 910b. The frame 920, for example, surrounds the display units 910a and 910b. In the illustrated example, the image forming device 911 of the first display unit 910a is attached to one end of the frame 920. The image forming device 911 of the second display unit 910b is attached to the other end of the frame 920.

[0139] A first temple 930a and a second temple 930b extend from the frame 920. In the illustrated example, the first temple 930a extends from one end of the frame 920. The second temple 930b extends from the other end of the frame 920.

[0140] The first temple 930a and the second temple 930b are suspended over the ears of the viewer when the viewer wears the head mounted display 900. The viewer's head is positioned between the temples 930a and 930b.

[0141] 17 is a diagram schematically illustrating an image forming device 911 and a light guide device 915 of a first display unit 910a of a head-mounted display 900. The first display unit 910a and the second display unit 910b basically have the same configuration. Therefore, the following description of the first display unit 910a can also be applied to the second display unit 910b.

[0142] As shown in FIG. 17, the image forming device 911 includes, for example, a display device 1 as a light source and a projection device 914 for forming an image.

[0143] The projection device 914 projects the image light emitted from the display device 1 toward the light guide device 915. The projection device 914 is, for example, a projection lens. The lens constituting the projection device 914 may have an axially symmetrical surface as its lens surface.

[0144] The light guiding device 915 is accurately positioned relative to the projection device 914, for example, by being screwed to the lens barrel of the projection device 914. The light guiding device 915 has, for example, an image light guiding member 916 that guides the image light, and a see-through member 918 for see-through.

[0145] The image light emitted from the projection device 914 is incident on the image light guide member 916. The image light guide member 916 is a prism that guides the image light toward the viewer's eyes. The image light that has entered the image light guide member 916 is repeatedly reflected on the inner surface of the image light guide member 916, and is then reflected by the reflective layer 917 and emitted from the image light guide member 916. The image light that has emitted from the image light guide member 916 reaches the viewer's eyes. The reflective layer 917 is made of, for example, a metal or a dielectric multilayer film. The reflective layer 917 may be a half mirror.

[0146] The transparent member 918 is adjacent to the image light guiding member 916. The transparent member 918 is fixed to the image light guiding member 916. For example, the outer surface of the transparent member 918 is continuous with the outer surface of the image light guiding member 916. The transparent member 918 allows the viewer to see outside light through it. The image light guiding member 916 also has a function of allowing the viewer to see outside light through it, in addition to the function of guiding image light. Note that the head mounted display 900 may be configured not to allow the viewer to see outside light through it.

[0147] According to the electronic device of this embodiment, since the display device 1 is capable of driving the data lines 12 at high speed, it is possible to make the display device 1 display high-definition images, for example.

[0148] The electronic device having the display device 1 is not limited to a head-mounted display, but may be, for example, an EVF, a projector, a wearable display such as a smartwatch, or an in-vehicle head-up display. EVF is an abbreviation for Electronic View Finder.

[0149] The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0150] For example, in each of the above embodiments, the data potential generating circuit 23 is configured to include a capacitive DAC, but other configurations are also possible. For example, the j-th data potential generating circuit 23 may include a D / A conversion circuit and an amplifier circuit, in which the D / A conversion circuit acquires the R data, B data, and G data of m pixels P in the j column included in the image data VIDX output from the control circuit 3 at timings specified by the control circuit 3 and performs D / A conversion on a time-division basis, and the amplifier circuit amplifies the potential after D / A conversion to output the data potential VDATA[j].

[0151] The above-described embodiments and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be combined as appropriate.

[0152] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations that have the same functions, methods, and results, or configurations that have the same purpose and effects. The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that have the same effects as the configurations described in the embodiments or that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0153] The following can be derived from the above-described embodiment and modifications.

[0154] One aspect of the display device is A plurality of first light-emitting elements; A plurality of second light-emitting elements; A data transfer line; a first data line extending in a first direction; a second data line extending in the first direction and adjacent to the first data line along the first direction; a plurality of first pixel circuits connected to the first data lines and connected to the plurality of first light-emitting elements, respectively; a plurality of second pixel circuits connected to the second data lines and connected to the plurality of second light-emitting elements, respectively; a first switch circuit that controls an electrical connection between the first data line and the data transfer line; a second switch circuit that controls an electrical connection between the second data line and the data transfer line; a signal for causing each of the plurality of first light-emitting elements to emit light is supplied to the first data line from the data transfer line via the first switch circuit; a signal for causing each of the plurality of second light-emitting elements to emit light is supplied to the second data line from the data transfer line via the second switch circuit; In a plan view, the first switch circuit overlaps with at least one of the plurality of first light-emitting elements.

[0155] In this display device, instead of a common connection between the data transfer line and the plurality of first pixel circuits, the plurality of first pixel circuits are connected to a first data line branching from the data transfer line via a first switch circuit, and the plurality of second pixel circuits are connected to a second data line branching from the data transfer line via a second switch circuit. Therefore, the plurality of first pixel circuits become loads connected to the first data line, but the plurality of second pixel circuits do not become loads connected to the first data line, thereby reducing the load on the first data line. Similarly, the plurality of second pixel circuits become loads connected to the second data line, but the plurality of first pixel circuits do not become loads connected to the second data line, thereby reducing the load on the second data line. Furthermore, while the first switch circuit and the second switch circuit become loads connected to the data transfer line, the plurality of first pixel circuits and the plurality of second pixel circuits do not become loads connected to the data transfer line, thereby also reducing the load on the data transfer line. Therefore, this display device allows high-speed driving of the data transfer line, the first data line, and the second data line, thereby enabling, for example, the display of high-resolution images.

[0156] Furthermore, in this display device, the first switch circuit overlaps with at least one of the plurality of first light-emitting elements in plan view, so that an increase in layout area due to the first switch circuit is suppressed.

[0157] In one aspect of the display device, the plurality of first light emitting elements are arranged at a first pitch in the first direction, the plurality of first pixel circuits are arranged at a second pitch in the first direction, The second pitch may be smaller than the first pitch.

[0158] In this display device, the second pitch at which the multiple first pixel circuits are arranged in the first direction is smaller than the first pitch at which the multiple first light-emitting elements are arranged in the first direction, so the layout area for the multiple first pixel circuits is smaller than the layout area for the multiple first light-emitting elements. Therefore, when the layout area for the multiple first light-emitting elements is stacked on a layer above the layout area for the multiple first pixel circuits, the first switch circuit can be arranged in the area remaining after the layout area for the multiple first light-emitting elements, excluding the layout area for the multiple first pixel circuits, in a planar view. Therefore, this display device prevents an increase in layout area due to the first switch circuit.

[0159] In one aspect of the display device, In a plan view, the first switch circuit may be disposed in a region between two of the first pixel circuits.

[0160] According to this display device, the distance from the first switch circuit to the pixel circuit at the end in the first direction is short, so the difference in time constant when writing data to each pixel is small, and unevenness in the displayed image is reduced.

[0161] In one aspect of the display device, In a plan view, the first switch circuit may be arranged in a region between an arrangement region of the plurality of first pixel circuits and an arrangement region of the plurality of second pixel circuits.

[0162] In one aspect of the display device, The product of the difference between the first pitch and the second pitch and the number of the first light-emitting elements may be equal to or less than the first pitch.

[0163] In this display device, when the layout area of ​​the plurality of first light-emitting elements is overlapped on an upper layer of the layout area of ​​the plurality of first pixel circuits, the plurality of wirings and the plurality of vias connecting the plurality of first light-emitting elements to the plurality of first pixel circuits can be arranged in the area where the layout area of ​​the plurality of first pixel circuits and the layout area of ​​the plurality of first light-emitting elements overlap, thereby suppressing an increase in layout area due to the plurality of wirings and the plurality of vias.

[0164] One aspect of the electronic device is The display device has one aspect of the above.

[0165] According to this electronic device, since the electronic device has a display device that can drive data lines at high speed, it is possible to display high-definition images on the display device, for example. [Explanation of symbols]

[0166] 1... display device, 2... display panel, 3... control circuit, 11... scanning line, 12, 12R, 12B, 12G... data line, 15... power supply line, 17, 17-1, 17-2, 17-3, 17R, 17B, 17G... data transfer line, 20, 20-1, 20-2, 20-3, 20R, 20B, 20G... pixel circuit, 21... scanning line drive circuit, 22, 22-1, 22-2, 22-3, 22R, 22B, 22G... switch circuit, 23, 23-1, 23-2, 23-3... data potential generation circuit, 24, 24-1, 24-2, 24-3... MOSFET, 25... capacitor, 27, 27 R, 27B, 27G...light-emitting element, 30...insulating layer, 40...organic EL element, 41...pixel electrode, 42...light-emitting functional layer, 43...common electrode, 44...light-emitting region, 50...substrate, 51...impurity region, 52...gate insulating layer, 53...gate electrode, 54, 55, 56, 57...interlayer insulating layer, 58...wiring layer, 59...reflective layer, 60...insulating layer, 62...opening, 70...sealing layer, 80...colored layer, 90...opposite substrate, 92...adhesive layer, 112...display region, 120...FPC, 124...external connection terminal, 130...case, 201...capacitor element, 202-206...MOSFET, 208R, 208B, 208G... vias, 209R, 209B, 209G... wiring, 221R, 221B, 221G... vias, 222R, 222B, 222G... wiring, 231-0 to 231-9... capacitance elements, 232... capacitance elements, 233-0 to 233-9, 234... switch circuits, 900... head mounted display, 910a... first display unit, 910b... second display unit, 911... image forming device, 912... external member, 914... projection device, 915... light guide device, 916... image light guide member, 917... reflective layer, 918... transparent member, 920... frame, 930a... first temple, 930b... second temple

Claims

1. A plurality of first light-emitting elements; A plurality of second light-emitting elements; A data transfer line; a first data line extending in a first direction; a second data line extending in the first direction and adjacent to the first data line along the first direction; a plurality of first pixel circuits connected to the first data lines and connected to the plurality of first light-emitting elements, respectively; a plurality of second pixel circuits connected to the second data lines and connected to the plurality of second light-emitting elements, respectively; a first switch circuit that controls an electrical connection between the first data line and the data transfer line; a second switch circuit that controls an electrical connection between the second data line and the data transfer line; a signal for causing each of the plurality of first light-emitting elements to emit light is supplied to the first data line from the data transfer line via the first switch circuit; a signal for causing each of the plurality of second light-emitting elements to emit light is supplied to the second data line from the data transfer line via the second switch circuit; The display device, wherein the first switch circuit overlaps with at least one of the plurality of first light-emitting elements in a plan view.

2. In claim 1, the plurality of first light-emitting elements are arranged at a first pitch in the first direction, the plurality of first pixel circuits are arranged at a second pitch in the first direction, The display device, wherein the second pitch is smaller than the first pitch.

3. In claim 1, a first switch circuit disposed in a region between two of the first pixel circuits in a plan view;

4. In claim 1, a first switch circuit disposed in a region between an arrangement region of the plurality of first pixel circuits and an arrangement region of the plurality of second pixel circuits in a plan view;

5. In claim 2, A display device, wherein a product of a difference between the first pitch and the second pitch and the number of the first light-emitting elements is equal to or less than the first pitch.

6. An electronic device comprising the display device according to claim 1 .

Images