Modulator capable of controlling phase of baseband signal and phase control method

Abstract

To provide a novel phase control method and a phase-controllable modulator that can achieve highly accurate phase control of a baseband signal using a relatively slow multiplier.SOLUTION: A modulator (10) that multiplies a baseband signal by a carrier signal includes a first converter (101) that converts serial carrier data into first parallel data, a plurality of multipliers (M1-MN) that sequentially multiply each of the first parallel data by the baseband signal, a second converter (103) that converts second parallel data output from each of the plurality of multipliers into serial transmission data, and a timing selector (104) that selects from the plurality of multipliers a multiplier that starts multiplication of the baseband signal in accordance with a phase control signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a phase control technique for a baseband signal that is multiplied by a carrier signal. [Background technology]

[0002] There is a transmitter that includes a modulator that multiplies multiple baseband signals by carrier waves of different frequencies, and a power amplifier that amplifies the power of each modulated carrier wave and transmits it. It is known that in such a transmitter, if there is a synchronization error between the multiple baseband signals, the distortion characteristics of the power amplifier deteriorate. To prevent such deterioration in distortion characteristics, a wireless transmission device has been proposed that includes a function for correcting the synchronization error between the multiple baseband signals (Patent Document 1). Specifically, a variable delay means, such as a digital filter, is provided for each baseband signal, ensuring synchronization between the multiple baseband signals.

[0003] Furthermore, in RF transmission systems, it is common to implement a modulator, a carrier frequency conversion device, and the like in an FPGA (Field Programmable Gate Array) (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. WO2014 / 136437 Pamphlet [Patent Document 2] Special Publication No. 2020-537847 Summary of the Invention [Problem to be solved by the invention]

[0005] It is known that the positioning accuracy of positioning signals transmitted by positioning satellites is reduced by phase errors. Therefore, the transmission system for positioning signals must align the phase in steps of, for example, 1 nanosecond (ns) or less. To achieve such high-precision phase alignment using an FPGA, the FPGA must operate at a high-speed clock of around 1 GHz. However, it is not easy to implement a modulator that operates at a clock frequency on the order of GHz, especially in an FPGA for satellite installation. Furthermore, using a fractional delay filter that delays only the fractional part of the clock cycle for phase alignment requires a large-scale circuit, both of which are difficult to implement in an FPGA for satellite installation.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a new phase control method and a phase-controllable modulator that can achieve highly accurate phase control of a baseband signal using a relatively slow multiplier. [Means for solving the problem]

[0007] The modulator in the present disclosure is a modulator that multiplies a baseband signal and a carrier signal, and includes: a first converter that converts serial carrier data into first parallel data; a plurality of multipliers that sequentially multiply each of the first parallel data by the baseband signal; a second converter that converts second parallel data output from each of the plurality of multipliers into serial transmission data; and a timing selector that selects from the plurality of multipliers a multiplier that starts multiplying the baseband signal in accordance with a phase control signal. The phase control method disclosed herein is a method for controlling the phase of multiplication of a baseband signal and a carrier signal, in which a first converter converts serial carrier data into first parallel data, a plurality of multipliers multiply each of the first parallel data by the baseband signal, a second converter converts second parallel data output from each of the plurality of multipliers into serial transmission data, and a timing selection unit selects from the plurality of multipliers a multiplier that starts multiplication of the baseband signal in accordance with a phase control signal. [Effects of the Invention]

[0008] As described above, according to the present invention, by selecting a multiplier that starts multiplication of a baseband signal from a plurality of multipliers in accordance with a phase control signal, highly accurate phase control of a baseband signal can be achieved using a relatively slow multiplier. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram illustrating a schematic configuration of a transmitter employing a modulator according to the present disclosure. [Figure 2] FIG. 2 is a schematic diagram showing an example of serial-to-parallel conversion of carrier waveform data in a modulator according to the present disclosure. [Figure 3] FIG. 3 is a schematic diagram showing an example of the multiplication timing adjustment operation of the modulator according to the present disclosure. [Figure 4] FIG. 4 is a schematic diagram illustrating an example of parallel-to-serial conversion of modulated parallel data in a modulator according to the present disclosure. [Figure 5] FIG. 5 is a block diagram illustrating another example of a transmitter employing a modulator according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] 1. Overview of the embodiment According to an embodiment of the present invention, one multiplier is selected as a starting point from among a plurality of multipliers arranged in parallel, and multiplication of parallel carrier data and a baseband signal is started from the selected multiplier. This allows the phase adjustment step of the timing for multiplying the baseband signal to be reduced according to the number of multipliers arranged in parallel. Therefore, highly accurate phase alignment can be achieved using a relatively slow multiplier.

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the components described in the following embodiments are merely examples and are not intended to limit the technical scope of the present invention.

[0012] 2. Embodiment <Configuration> As illustrated in FIG. 1, a transmitter 1 includes a phase-controllable modulator 10 according to the present disclosure and a digital-to-analog converter (hereinafter referred to as DAC) 20. The modulator 10 includes a serial-to-parallel (S / P) converter 101, a multiplier array 102, a parallel-to-serial (P / S) converter 103, and a start timing selector 104. Hereinafter, the frequency of the clock (CLK) signal will be referred to as f CLK Let's say.

[0013] The S / P converter 101 receives the carrier waveform data D CW are input sequentially in clock units (1CLK), and a predetermined number N of parallel data D CW1 , D CW2 , ···D CWN (Hereafter, D CW ) to the multiplier array 102. Therefore, the parallel data D CW is output to the multiplier array 102 with a period of N / f CLK This becomes:

[0014] The multiplier array 102 includes N multipliers M1-M N are connected in parallel between the S / P converter 101 and the P / S converter 103. N are the parallel data D input from the S / P converter 101. CW1 , D CW2 , ···D CWN and the baseband signal S input sequentially in clock units from the start timing selector 104. BB and are multiplied respectively. The multiplied parallel data D M CW1 , D M CW2 , ···D M CWN is output to the P / S converter 103. The P / S converter 103 receives the input parallel data D M CW1 , D M CW2 , ···D M CWN (Hereafter, D M CW ) are read out in sequence in accordance with the CLK signal, and the serial transmission data D TXis output to DAC20. DAC20 outputs the serial transmission data D TX is converted to analog and the RF transmission signal S TX Directly output.

[0015] The start timing selector 104 outputs a phase control signal C PH Multiplier M specified according to i (i is an integer between 1 and N) as the starting point, multipliers M1-M N Here, the cyclic selection is performed by selecting the multiplier M i Starting from M i , M i+1 , M1, M2, M N , M1, . . . are selected in a circularly repeated order. In this way, the start timing selector 104 selects the baseband signals S BB (B1, B2, B3, . . . ) are sequentially output to the selected multiplier at the corresponding timing. In this way, each multiplier in the multiplier array 102 outputs the corresponding parallel data D CW and the baseband signal S BB Multiply and the resulting parallel data D M CW is output to the P / S converter 103.

[0016] In FIG. 1, when the multiplier M1 is designated as the starting point, the start timing selector 104 generates the baseband signal S in accordance with the CLK signal. BB From the beginning, multipliers M1 to M N , and then multipliers M1 to M N In this case, the baseband signal S BB is multiplied to the carrier wave without any delay.

[0017] When the multiplier M2 is designated as the starting point, the start timing selector 104 generates the baseband signal S according to the CLK signal. BB are output sequentially from the beginning to multipliers M2 to M1, and then N The selection is repeated up to M1 through M2. In this case, the baseband signal S BBis Δt=1 / Nf CLK Hereinafter, if i is an integer between 1 and N, the multiplier M i is specified as the starting point, the baseband signal S BB is i×Δt=i / Nf CLK That is, the desired delay amount is set depending on which multiplier the start timing selector 104 selects as the starting point. At this time, the phase adjustment step Δt is 1 / Nf CLK Therefore, by setting the number N of parallel multipliers, fractional delay control of one clock period or less can be easily achieved.

[0018] Also, multipliers M1-M of multiplier array 102 N is the period N / f CLK Parallel data D CW Since the input is , it can be implemented using a relatively slow satellite-mounted FPGA.

[0019] <Example of operation> Next, the operation of the phase-controllable modulator 10 will be described using an example in which eight multipliers M1 to M8 are provided in the multiplier array 102. CW For the sake of convenience, the carrier waveform data D CW The data for one clock of the baseband signal S is distinguished by serial numbers 1, 2, 3, etc. (hereinafter referred to as (1), (2), etc.) from the beginning. BB The data for one clock is distinguished from the beginning by the codes B1, B2, B3, etc.

[0020] As shown in FIG. 2, the S / P converter 101 converts the carrier waveform data D CW are parallelized every 8 clocks in the order of serial numbers from the beginning, and the parallel data D CW1 , D CW2 , ···D CW8to the multiplier array 102. That is, the first 8 data (1) to (8) of the carrier waveform data are output in the first clock, and the next 8 data (9) to (16) are output in the next clock, and so on, so that data for every 8 clocks is parallelized and output.

[0021] As shown in FIG. 3, multipliers M1-M8 of the multiplier array 102 receive parallel data D from the S / P converter 101. CW1 , D CW2 , ···D CWN The start timing selector 104 receives the phase control signal C PH Select a multiplier according to the input signal, set the start timing of multiplication, and generate the baseband signal S BB The data B1, B2, B3, . . . are output to the selected multipliers in sequence.

[0022] Here, it is assumed that the multiplication starts from the multiplier M8. That is, the multiplier M8 receives the parallel data D CW8 The head data (8) is multiplied by the baseband signal B1, and the multiplied parallel data D M CW8 (In Figure 3, this is written as "8*B1"). At the next clock, multiplier M1 is selected and multiplier M1 outputs parallel data D CW1 The next data (9) is multiplied by the baseband signal B2, and the multiplied parallel data D M CW1 (In Figure 3, this is written as "9*B2") and then output the parallel data D CW8 The data (8) is converted into the baseband signal S BB The parallel data D that is multiplied with M CW1 ~D M CW8 is output to the P / S converter 103.

[0023] As shown in FIG. 4, the P / S converter 103 converts the multiplied parallel data D M CW1 , D M CW2 , ···D M CW8and serially read them out according to the CLK signal to generate serial transmission data D TX is output to the DAC 20. As described above, the parallel data D CW8 The data (8) is converted into the baseband signal S BB In Figure 4, the data parallel data D CW8 The serial numbers of the data (8) and onwards are denoted by adding a multiplication mark "*". Therefore, the serial transmission data D output from the P / S converter 103 TX is the baseband signal S from the timing delayed by 7Δt from the beginning. BB is multiplied.

[0024] By a similar process, multipliers M other than multiplier M8 are i When multiplication starts from the timing delayed by i × Δt, the baseband signal S BB Here, since N=8, the phase adjustment step Δt=1 / 8f CLK For example, if the clock frequency of the FPGA is 200MHz, it can be controlled in steps Δt of 625 picoseconds (ps), which corresponds to 1600MHz, eight times 200MHz. The phase-adjusted serial transmission data D TX is converted by DAC104 into RF transmit signal S TX is converted to

[0025] As described above, the desired delay amount can be set by selecting which multiplier the start timing selector 104 uses as the starting point, making it easy to achieve fractional delay control of less than one clock period. The multipliers in the multiplier array 102 can be implemented using a relatively slow satellite-mounted FPGA. Furthermore, even if the multipliers used by the modulator 100 are implemented in a DSP (Digital Signal Processor), only the number of DSPs required for parallelization is required, which requires significantly fewer resources than implementing a filter.

[0026] 3. Other Embodiments As shown in FIG. 5, the transmitter 2 has m transmission systems, and transmits separate carrier waveform data D1 CW ~DmCW and baseband signal S1 BB ~Sm BB and the serial transmission data D1 modulated as described above. TX ~Dm TX is converted to analog and the RF transmission signal S1 TX ~Sm TX and DACs 20(1) to 20(m) that output the respective signals.

[0027] Hereinafter, for the sake of simplicity, if j, which indicates the transmission system, is an integer between 1 and m, the phase-adjustable modulator 10(j) has the same configuration as the above-described modulator 10. That is, the phase-adjustable modulator 10(j) receives the phase control signal Cj as described above. PH According to the multiplier M i is specified as the starting point, the baseband signal Sj BB is i×Δt=i / Nf CLK That is, the phase control signal Cj PH According to this, the start timing selector 104 can control the fractional delay depending on which multiplier it selects as the start point.

[0028] RF transmission signal Sj output by transmission system j of transmitter 2 TX is transmitted through an output stage consisting of a bandpass filter BPFj and a power amplifier AMPj. TX The phase characteristic of the phase-adjustable modulator 10(j) inevitably changes due to temperature and time variations, but the amount of change is not necessarily constant at all output stages. Therefore, the change in the phase characteristic at the output stage of each transmission system j is measured in advance, and the phase adjustment signal Cj of the phase-adjustable modulator 10(j) is adjusted to compensate for the change in the phase characteristic. PH That is, according to this embodiment, it is possible to adjust the number of RF transmission signals S1 TX ~Sm TXThe phase adjustment in the above can be performed by each of the phase-adjustable modulators 10(1) to 10(m). In particular, if the phase-adjustable modulators 10(1) to 10(m) are realized using FPGAs, phase adjustment can be achieved simply by setting the FPGA, eliminating the need for hardware replacement or adjustment.

[0029] 4. Application Examples The above-described embodiment can be applied to a transmitter of a positioning satellite. For example, if the carrier wave is set to a GHz level, and the baseband signal S BB is the GPS identification code, the RF transmission signal S TX Therefore, even when multiple positioning signals are to be transmitted, multiple phase-aligned RF outputs can be easily obtained by configuring as shown in FIG.

[0030] Furthermore, the phase-tunable modulator 10 or both the phase-tunable modulator 10 and the DAC 20 can be implemented using an FPGA. In particular, the multiple multipliers of the phase-tunable modulator 10 can operate at a relatively low speed, so they can be implemented using an FPGA for onboard use on a satellite.

[0031] Furthermore, the phase-controllable modulator 10 can also be implemented by executing a program stored in a memory (not shown) on a processor such as a CPU (Central Processing Unit) or a DSP.

[0032] Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate.

[0033] 5. Supplementary Notes Some or all of the above-described embodiments and examples can be described as follows, but are not limited to these. (Appendix 1) A modulator that multiplies a baseband signal and a carrier signal, comprising: a first converter for converting serial carrier data into first parallel data; a plurality of multipliers that sequentially multiply each of the first parallel data by the baseband signal; a second converter that converts second parallel data output from each of the plurality of multipliers into serial transmission data; a timing selector that selects a multiplier that starts multiplication of the baseband signal from the plurality of multipliers in accordance with a phase control signal; A phase-tunable modulator having: (Appendix 2) 2. The phase-adjustable modulator according to claim 1, wherein the timing selector cyclically selects the plurality of multipliers from the selected multipliers in a predetermined order, and outputs the baseband signal to the sequentially selected multipliers. (Appendix 3) The phase-adjustable modulator according to claim 2, wherein the plurality of first parallel data are read out every clock and multiplied by the baseband signal sequentially from selected multipliers of the plurality of multipliers. (Appendix 4) The number of the multiple multipliers is N, and the clock frequency is f CLK Then, the multiplication phase adjustment step of the baseband signal is 1 / N f CLK 2. The phase-adjustable modulator according to claim 1, (Appendix 5) 2. The phase-adjustable modulator according to claim 1, wherein each of the plurality of multipliers is implemented in an FPGA (Field Programmable Gate Array). (Appendix 6) The number of the multiple multipliers is N, and the clock frequency is f CLK Then, the operating frequency of the FPGA is f CLK 6. The phase-tunable modulator according to claim 5, wherein: (Appendix 7) A transmitter having a phase-adjustable modulator according to any one of appendices 1-6, further comprising a digital-to-analog (DA) converter for converting the serial transmission data into an analog high-frequency signal. (Appendix 8) The transmitter described in Appendix 7, characterized in that a plurality of pairs of the phase-adjustable modulator and the DA converter are provided in parallel, and the start timing of the baseband signal of the analog high-frequency signal output from each pair is adjusted by the phase control signal. (Appendix 9) 1. A method for controlling a phase for multiplying a baseband signal and a carrier signal, comprising: a first converter converting the serial carrier data into first parallel data; a plurality of multipliers multiply each of the first parallel data by the baseband signal; a second converter converts second parallel data output from the plurality of multipliers into serial transmission data; a timing selection unit selecting a multiplier that starts multiplication of the baseband signal from the plurality of multipliers in accordance with a phase control signal; Phase control method. (Appendix 10) the timing selector cyclically selects the plurality of multipliers in a predetermined order from the selected multipliers, and outputs the baseband signal to the sequentially selected multipliers; 10. The phase control method according to claim 9, (Appendix 11) A phase control method according to claim 10, characterized in that the plurality of first parallel data are read out every clock and multiplied by the baseband signal sequentially from selected multipliers of the plurality of multipliers. (Appendix 12) The number of the multiple multipliers is N, and the clock frequency is f CLK Then, the multiplication phase adjustment step of the baseband signal is 1 / N f CLK 10. The phase control method according to claim 9, wherein: (Appendix 13) 10. The phase control method according to claim 9, wherein each of the plurality of multipliers is implemented in an FPGA (Field Programmable Gate Array). (Appendix 14) The number of the multiple multipliers is N, and the clock frequency is f CLK Then, the operating frequency of the FPGA is f CLK 14. The phase control method according to claim 13, wherein: (Appendix 15) A program that causes a computer to function as a modulator that controls a phase for multiplying a baseband signal and a carrier signal, a first converter converting the serial carrier data into first parallel data; a function in which a plurality of multipliers multiply each of the first parallel data by the baseband signal; a second converter converting the second parallel data output from each of the plurality of multipliers into serial transmission data; a timing selection unit selecting a multiplier from the plurality of multipliers to start multiplication of the baseband signal in accordance with a phase control signal; A program for realizing the above on the computer. [Industrial Applicability]

[0034] The present invention is applicable to modulators in transmitters of positioning satellites. [Explanation of symbols]

[0035] 1, 2 Transmitter 10 Phase-controllable modulator 20 Digital-to-Analog Converter (DAC) 101 Serial-to-parallel converter (S / P converter) 102 Multiplier Array 103 Parallel-to-serial converter (P / S converter) 104 Start timing selector

Claims

1. A modulator that multiplies a baseband signal and a carrier signal, comprising: a first converter for converting serial carrier data into first parallel data; a plurality of multipliers that sequentially multiply each of the first parallel data by the baseband signal; a second converter that converts second parallel data output from each of the plurality of multipliers into serial transmission data; a timing selector that selects a multiplier that starts multiplication of the baseband signal from the plurality of multipliers in accordance with a phase control signal; A phase-tunable modulator having:

2. 2. The phase-adjustable modulator according to claim 1, wherein the timing selector cyclically selects the plurality of multipliers in a predetermined order from the selected multipliers, and outputs the baseband signal to the sequentially selected multipliers.

3. 3. The phase-adjustable modulator according to claim 2, wherein the plurality of first parallel data are read out every clock and multiplied by the baseband signal sequentially from selected multipliers of the plurality of multipliers.

4. The number of the multiple multipliers is N, and the clock frequency is f ＣＬＫ Then, the multiplication phase adjustment step of the baseband signal is 1 / N·f ＣＬＫ 2. The phase-tunable modulator of claim 1, wherein:

5. 2. The phase-tunable modulator of claim 1, wherein each of the plurality of multipliers is implemented in an FPGA (Field Programmable Gate Array).

6. The number of the multiple multipliers is N, and the clock frequency is f ＣＬＫ Then, the operating frequency of the FPGA is f ＣＬＫ 6. The phase-tunable modulator of claim 5, wherein:

7. A transmitter comprising a phase-adjustable modulator according to any one of claims 1 to 6, further comprising a digital-to-analog (DA) converter for converting the serial transmission data into an analog high-frequency signal.

8. The transmitter according to claim 7, characterized in that a plurality of pairs of the phase-adjustable modulator and the DA converter are provided in parallel, and the start timing of the baseband signal of the analog high-frequency signal output from each pair is adjusted by the phase control signal.

9. 1. A method for controlling a phase for multiplying a baseband signal and a carrier signal, comprising: a first converter converting the serial carrier data into first parallel data; a plurality of multipliers multiply each of the first parallel data by the baseband signal; a second converter converts the second parallel data output from each of the plurality of multipliers into serial transmission data; a timing selection unit selecting a multiplier that starts multiplication of the baseband signal from the plurality of multipliers in accordance with a phase control signal; Phase control method.

10. the timing selector cyclically selects the plurality of multipliers in a predetermined order from the selected multipliers, and outputs the baseband signal to the sequentially selected multipliers; 10. The phase control method according to claim 9.

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