Grayscale voltage generation circuit, source driver, and display device

Abstract

To provide a grayscale voltage generation circuit with which it is possible to accelerate the output operation of a source driver while suppressing an increase in current consumption.SOLUTION: Provided is a grayscale voltage generation circuit including: a plurality of gamma amplifiers for receiving input of a plurality of gamma reference voltages including a first reference voltage, a second reference voltage, and a voltage derived by dividing between both reference voltages, and individually amplifying the plurality of gamma reference voltages; a ladder resistor including a plurality of resistors each of which between the outputs of the gamma amplifiers are connected in series, and outputting a plurality of grayscale voltages generated by dividing the gamma reference voltages corresponding to the first reference voltage and the second reference voltage from the respective connection nodes of resistors of the plurality of resistors; a comparator for comparing the voltage of the first connection node among the plurality of connection nodes between the respective output terminals of the first and second gamma amplifiers with the reference voltage; and a switch for connecting one of connection nodes in a connection node group and the voltage supply line of the first voltage on the basis of the comparison result of the comparator.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a grayscale voltage generating circuit, a source driver, and a display device. [Background technology]

[0002] Active matrix driving is used as a driving method for display devices such as liquid crystal display devices and organic electroluminescence (EL) devices. In active matrix driving display devices, the display panel is composed of a semiconductor substrate on which pixel sections and pixel switches are arranged in a matrix. The pixel switches are controlled to be turned on and off by gate pulses, and when the pixel switches are turned on, a grayscale voltage signal corresponding to a video data signal is supplied to the pixel sections to control the brightness of each pixel section, thereby producing a display. The driving circuit of the display device includes, for example, a gate driver that outputs gate pulses to gate lines, a source driver that outputs grayscale voltage signals to data lines, and a timing controller that supplies video signals and timing signals to the source driver.

[0003] The source driver includes a DA conversion circuit that converts a digital video signal into a drive voltage having an analog voltage value, and a gradation voltage generation circuit that generates a plurality of gradation voltages, each having a different voltage value, corresponding to the entire luminance range that can be expressed by the video signal. The gradation voltage generation circuit is configured to generate a plurality of gradation voltages by dividing a reference voltage generated by a reference voltage source arranged in the display panel using a ladder resistor circuit. The DA conversion circuit selects a gradation voltage corresponding to the luminance level indicated by the video signal from the plurality of gradation voltages generated by the gradation voltage generation circuit and outputs it as a drive voltage.

[0004] In such a gradation voltage generating circuit, in order to supply a stable gradation voltage while suppressing power consumption, a configuration has been proposed in which a gamma correction circuit consisting of an operational amplifier and a gamma correction resistor formed on its input side is provided between the reference voltage source and the ladder resistor circuit (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-10276 Summary of the Invention [Problem to be solved by the invention]

[0006] In recent years, panel displays such as those found in smartphones and monitors have become faster. This increased speed necessitates a reduction in the voltage transition time of the source driver output. However, with conventional source driver configurations, it is difficult to speed up the output due to the rate-limiting effect of the gamma correction circuit output (gamma tap). Increasing the current capacity of the gamma amplifier to shorten the transition time of the tap voltage (gamma tap output voltage) results in an increase in the gamma amplifier circuit size and current consumption.

[0007] Furthermore, when the DA conversion circuit changes its selection state, the charging and discharging of the output amplifier provided downstream of the DA conversion circuit causes voltage changes such as voltage drops and overshoots in the grayscale voltage. This voltage change causes the grayscale voltage to take time to return to its original voltage value, resulting in a problem of slower output voltage transition times.

[0008] The present invention has been made in view of the above problems, and has as its object to provide a grayscale voltage generating circuit that can increase the speed of the output of a source driver while suppressing an increase in current consumption. [Means for solving the problem]

[0009] A grayscale voltage generation circuit according to the present invention is a grayscale voltage generation circuit that generates a plurality of grayscale voltages corresponding to each luminance level in a luminance range that can be expressed by a video signal, based on a first reference voltage and a second reference voltage having mutually different voltage levels, and includes a plurality of gamma reference voltages that receive inputs, including the first reference voltage, the second reference voltage, and a voltage obtained by dividing a voltage between the first reference voltage and the second reference voltage, and a plurality of gamma amplifiers that amplify the plurality of gamma reference voltages individually, and a plurality of resistors that are connected in series with each other between outputs of adjacent gamma amplifiers among the plurality of gamma amplifiers, and a connection that connects the resistors of the plurality of resistors together. The circuit includes a ladder resistor that outputs the plurality of gradation voltages generated by dividing a voltage between a gamma reference voltage corresponding to the first reference voltage and a gamma reference voltage corresponding to the second reference voltage from each of the plurality of gamma reference voltages, a comparator that compares the voltage of one of a plurality of connection nodes in a connection node group formed between output terminals of a first gamma amplifier and a second gamma amplifier that are arranged adjacent to each other among the plurality of gamma amplifiers, with a reference voltage, and a switch that connects any one of the connection nodes in the connection node group to a voltage supply line of a first voltage based on a comparison result of the comparator.

[0010] Furthermore, a source driver according to the present invention is connected to a display panel having a plurality of pixel units arranged in a matrix at each of intersections between a plurality of data lines and a plurality of gate lines, and generates grayscale voltage signals to be supplied to the plurality of pixel units based on image data, the source driver including a grayscale voltage generation circuit that generates a plurality of grayscale voltages corresponding to each luminance level in a luminance range that can be expressed by a video signal based on a first reference voltage and a second reference voltage having mutually different voltage levels, the grayscale voltage generation circuit receiving input of a plurality of gamma reference voltages including the first reference voltage, the second reference voltage, and a voltage obtained by dividing a voltage between the first reference voltage and the second reference voltage, and a plurality of gamma amplifiers that individually amplify the plurality of gamma reference voltages; the plurality of gamma amplifiers includes a ladder resistor that includes a plurality of resistors connected in series between the outputs of the gamma amplifiers adjacent to each other, and outputs the plurality of gradation voltages that are generated by dividing a voltage between a gamma reference voltage corresponding to the first reference voltage and a gamma reference voltage corresponding to the second reference voltage from each of connection nodes that connect the resistors of the plurality of resistors; a comparator that compares the voltage of one connection node of a connection node group that includes a plurality of connection nodes between the output terminals of a first gamma amplifier and a second gamma amplifier that are arranged adjacent to each other among the plurality of gamma amplifiers, with a reference voltage; and a switch that connects any one connection node of the connection node group to a voltage supply line of a first voltage based on a comparison result of the comparator.

[0011] Further, a display device according to the present invention includes a display panel having a plurality of data lines and a plurality of gate lines, and a plurality of pixel units arranged in a matrix at each intersection of the plurality of data lines and the plurality of gate lines; a display controller that outputs an image data signal indicating an image to be displayed on the display panel; and a source driver that receives the image data signal from the display controller and generates, based on the image data signal, grayscale voltage signals to be supplied to the plurality of pixel units, wherein the source driver has a grayscale voltage generation circuit that generates, based on a first reference voltage and a second reference voltage having mutually different voltage levels, a plurality of grayscale voltages corresponding to each luminance level in a luminance range that can be expressed by a video signal, and the grayscale voltage generation circuit has a plurality of gamma amplifiers that receive input of a plurality of gamma reference voltages including the first reference voltage, the second reference voltage, and a voltage obtained by dividing a voltage between the first reference voltage and the second reference voltage, and that individually amplify the plurality of gamma reference voltages; The circuit is characterized by including: a ladder resistor including a plurality of resistors connected in series between outputs of adjacent gamma amplifiers among the plurality of gamma amplifiers, and outputting the plurality of gradation voltages generated by dividing a voltage between a gamma reference voltage corresponding to the first reference voltage and a gamma reference voltage corresponding to the second reference voltage from each of connection nodes connecting resistors of the plurality of resistors; a comparator that compares the voltage of one connection node among a plurality of connection nodes between output terminals of a first gamma amplifier and a second gamma amplifier that are arranged adjacent to each other among the plurality of gamma amplifiers, with a reference voltage; and a switch that connects any one connection node among the connection node group to a voltage supply line of a first voltage based on a comparison result of the comparator. [Effects of the Invention]

[0012] The grayscale voltage generating circuit according to the present invention makes it possible to increase the speed of the output of the source driver while suppressing an increase in current consumption. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a block diagram showing a configuration of a display device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram showing an internal configuration of a source driver. [Figure 3] FIG. 2 is a circuit diagram showing the internal configuration of a grayscale voltage generating circuit. [Figure 4] 2 is a circuit diagram showing a part of the internal configuration of a grayscale voltage generating circuit in the first embodiment. FIG. [Figure 5] FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of a comparator. [Figure 6] 10A and 10B are diagrams illustrating a comparison of voltage drops between a case where a reference voltage generating circuit is provided and a case where a reference voltage generating circuit is not provided; [Figure 7] FIG. 10 is a circuit diagram illustrating an internal configuration of a grayscale voltage generating circuit according to a second embodiment. [Figure 8] FIG. 10 is a circuit diagram showing the internal configuration of a grayscale voltage generating circuit according to a third embodiment. [Figure 9] FIG. 10 is a circuit diagram illustrating an internal configuration of a grayscale voltage generating circuit according to a fourth embodiment. [Figure 10] FIG. 10 is a circuit diagram illustrating an internal configuration of a grayscale voltage generating circuit according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail. In the following description of each embodiment and in the accompanying drawings, the same reference numerals are used to designate substantially the same or equivalent parts. [Example]

[0015] 1 is a block diagram showing the configuration of a display device 100 according to a first embodiment of the present invention. The display device 100 is an active matrix liquid crystal display device. The display device 100 includes a display panel 11, a timing controller 12, a gate driver 13, source drivers 14-1 to 14-p, and a reference voltage source 15.

[0016] The display panel 11 is composed of a semiconductor substrate on which a plurality of pixel units P11 to Pnm and pixel switches M11 to Mnm (n is an integer of 2 or greater, and m is an integer of 2 or greater and a multiple of 3) are arranged in a matrix of n rows and m columns. The display panel 11 has n gate lines GL1 to GLn which are horizontal scanning lines, and m data lines DL1 to DLm which are arranged orthogonally to intersect the gate lines GL1 to GLn. The pixel units P11 to Pnm and pixel switches M11 to Mnm are provided at the intersections of the gate lines GL1 to GLn and the data lines DL1 to DLm, and are arranged in a matrix.

[0017] The pixel switches M11 to Mnm are controlled to be on or off in response to gate signals Vg1 to Vgn supplied from the gate driver 13. The pixel units P11 to Pnm are supplied with grayscale voltage signals Gv1 to Gvm corresponding to video data from the source drivers 14-1 to 14-p. When the pixel switches M11 to Mnm are respectively on, the grayscale voltage signals Gv1 to Gvm are applied to the pixel electrodes of the pixel units P11 to Pnm, and each pixel electrode is charged. The brightness of the pixel units P11 to Pnm is controlled in response to the grayscale voltage signals Gv1 to Gvm at each pixel electrode of the pixel units P11 to Pnm, and display is performed.

[0018] In other words, the gate driver 13 operates to select m pixel units arranged along the extension direction of the gate lines (i.e., in a horizontal row) as targets to which the gradation voltage signals Gv1 to Gvm are to be supplied. The source drivers 14-1 to 14-p apply the gradation voltage signals Gv1 to Gvm to the selected pixel units in the horizontal row, causing them to display a color corresponding to the voltage. One frame of screen display is performed by selectively switching the pixel units in the horizontal row selected as targets to which the gradation voltage signals Gv1 to Gvm are to be supplied, and repeating this process in the extension direction of the data lines (i.e., the vertical direction).

[0019] Each of the pixel units P11 to Pnm includes a transparent electrode connected to a data line via a pixel switch, and a liquid crystal sealed between the transparent electrode and a counter substrate that is disposed opposite the semiconductor substrate and has a single transparent electrode formed over the entire surface. Display is achieved by changing the transmittance of the liquid crystal in response to the voltage difference between the grayscale voltage signals Gv1 to Gvm supplied to the pixel units P11 to Pnm and the counter substrate voltage, relative to the backlight inside the display device.

[0020] Based on the video data VS, the timing controller 12 generates a series of pixel data pieces PD (serial signal) that represent the brightness level of each pixel using, for example, 256 8-bit brightness gradations. The timing controller 12 also generates a clock signal CLK of an embedded clock type having a fixed clock cycle based on the synchronization signal SS. The timing controller 12 generates a video data signal VDS, which is a serial signal that combines the series of pixel data pieces PD with the clock signal CLK, and supplies this to the source drivers 14-1 to 14-p to control the display of the video data. The video data signal VDS is configured as a video data signal serialized according to the number of transmission paths for each predetermined number of data lines.

[0021] In this embodiment, one frame of video data signal VDS is formed by serially connecting n pixel data fragment groups, each consisting of m pixel data fragments PD. Each of the n pixel data fragment groups is a pixel data fragment group made up of pixel data fragments corresponding to a grayscale voltage to be supplied to pixels on one horizontal scan line (i.e., each of gate lines GL1 to GLn). Through operation of source drivers 14-1 to 14-p, pixel drive voltage signals Vd1 to Vdm to be supplied to n×m pixel units (i.e., pixel units P11 to Pnm) are applied via data lines DL1 to DLm based on the m×n pixel data fragments PD.

[0022] Furthermore, the timing controller 12 generates a frame synchronization signal FS indicating the timing of each frame of the video data signal VDS based on the synchronization signal SS, and supplies the generated signal to the source driver 14. The timing controller 12 generates a gate control signal GS for controlling the operation of the gate driver 13, and supplies the gate driver 13 with the generated signal.

[0023] The gate driver 13 receives a gate control signal GS from the timing controller 12, and sequentially supplies gate signals Vg1 to Vgn to the gate lines GL1 to GLn based on the clock timing included in the gate control signal GS.

[0024] The source drivers 14-1 to 14-p are arranged adjacent to each other along the horizontal direction (i.e., the extension direction of the gate lines GL1 to GLn). The source drivers 14-1 to 14-p are formed on separate semiconductor integrated circuit (IC) chips. For example, if each source driver has 960 outputs and the display panel has one data line per pixel column, the data lines are driven by 12 source drivers for a 4K panel and 24 source drivers for an 8K panel. The source drivers 14-1 to 14-p receive serial signals, which are an integrated combination of a control signal CS, a clock signal CLK, and a video data signal VDS, from the timing controller 12 via separate transmission paths. When there are one pair (two transmission paths) between the timing controller 12 and each source driver, the video data signals VDS and control signals CS corresponding to the number of source driver outputs are supplied as serialized differential signals during one data period.

[0025] The reference voltage source 15 generates reference voltages VGH and VGL and supplies them to the source drivers 14-1 to 14-p. The reference voltages VGH and VGL have a magnitude relationship of VGH>VGL.

[0026] FIG. 2 is a block diagram showing a schematic internal configuration of the source driver 14-1 selected from the source drivers 14-1 to 14-p.

[0027] The source driver 14-1 includes a grayscale voltage generating circuit 21, a data acquisition unit 22, a DA conversion unit 23, and an output unit 24.

[0028] The gradation voltage generation circuit 21 is connected to the reference voltage source 15 and receives the reference voltages VGH and VGL from the reference voltage source 15. Based on the reference voltages VGH and VGL, the gradation voltage generation circuit 21 generates gradation voltages V0 to V1023 that indicate different voltage values ​​that represent the range of brightness levels that can be expressed by the video signal in, for example, 1024 stages, and supplies these to the DA conversion unit 23.

[0029] The data acquisition unit 22 sequentially acquires k pixel data fragments PD corresponding to the data lines DL1 to DLk from the series of pixel data fragments PD included in the video data signal VDS every horizontal scanning period, and supplies each of them to the DA conversion unit 23 as display data VD1 to VDk.

[0030] The DA conversion unit 23 converts the display data VD1 to VDk into gradation voltage signals Q1 to Qk having analog voltage values ​​using gradation voltages V0 to V1023. That is, for each of the display data VD1 to VDk, the DA conversion unit 23 selects, from the gradation voltages V0 to V1023, a gradation voltage having a voltage value corresponding to the luminance level indicated by that display data VD. Then, the DA conversion unit 23 obtains gradation voltage signals Q1 to Qk each having the gradation voltage selected for each of the display data VD1 to VDk. The DA conversion unit 23 supplies the gradation voltage signals Q1 to Qk to the output unit 24.

[0031] The output unit 24 outputs the signals obtained by individually amplifying the grayscale voltage signals Q1 to Qk as pixel drive signals Dv1 to Dvk. That is, the output unit 24 of the source driver 14-1 outputs the pixel drive signals Dv1 to Dvk and supplies them to the data lines DL1 to DLk of the display panel 11, respectively.

[0032] FIG. 3 is a circuit diagram showing the internal configuration of the grayscale voltage generating circuit 21 of the source driver 14-1.

[0033] The grayscale voltage generating circuit 21 includes amplifiers GA1 and GA2 as input gamma buffer amplifiers, a first ladder resistor circuit LD1, amplifiers AP0 to AP9 as output gamma buffers, and a second ladder resistor circuit LD2.

[0034] Each of the amplifiers GA1, GA2, and AP0 to AP9 is, for example, a voltage follower operational amplifier whose inverting input terminal and output terminal are connected to each other.

[0035] The amplifier GA1 receives a reference voltage VGH as an input, amplifies the reference voltage VGH, and outputs the amplified potential as a first potential VX. As described above, the amplifier GA1 is a voltage follower operational amplifier, and therefore the first potential VX has a voltage level equal to that of the reference voltage VGH.

[0036] The amplifier GA2 receives the reference voltage VGL as an input, amplifies the reference voltage VGL, and outputs the amplified potential as the second potential VY. As described above, the amplifier GA2 is a voltage follower operational amplifier, and therefore the second potential VY has a voltage level equal to that of the reference voltage VGL.

[0037] The first ladder resistor circuit LD1 is composed of resistors R11 to R19 connected in series. One end of the resistor R19, which forms one end of the first ladder resistor circuit LD1, is connected to the output terminal of the amplifier GA1. Furthermore, one end of the resistor R11, which forms the other end of the first ladder resistor circuit LD1, is connected to the output terminal of the amplifier GA2.

[0038] The first ladder resistor circuit LD1 divides the voltage between one end and the other end, and outputs a plurality of gamma reference voltages having different voltage values ​​from the connection points of the resistors R11 to R19, including one end of each of the resistors R11 and R19.

[0039] The amplifiers AP0 to AP9 individually amplify the gamma reference voltages input to their respective input terminals and output the amplified potentials from their respective output terminals. As described above, the amplifiers AP0 to AP9 are voltage follower operational amplifiers, so the output potentials from their respective output terminals have a voltage level equal to the gamma reference voltages input to their respective input terminals.

[0040] The second ladder resistor circuit LD2 is composed of resistors R21 to R29 connected in series. The second ladder resistor circuit LD2 divides the voltage between the potential of the output terminal of the amplifier AP0 and the potential of the output terminal of the amplifier AP9, and outputs 1024 voltages having different voltage values ​​as grayscale voltages V0 to V1023. The grayscale voltages V0 to V1023 are supplied to each of DACs 23-1 to 23-k that make up the DA conversion unit 23.

[0041] Each of the resistors R21 to R29 is made up of a plurality of resistor elements connected in series. Connection nodes connecting the resistor elements together serve as output terminals for the grayscale voltages V0 to V1023.

[0042] 4 is an enlarged view of the reference voltage generating circuit 25 (the portion enclosed by the dashed line in FIG. 3) which is a part of the circuit block that constitutes the grayscale voltage generating circuit 21. The reference voltage generating circuit 25 includes a switch 31 and a comparator 32.

[0043] Amplifiers AP8 and AP9 are gamma amplifiers arranged adjacent to each other, and are output gamma buffers whose output voltages have similar voltage values ​​(in other words, among AP0 to AP9, the voltage values ​​of their output voltages are adjacent to each other).

[0044] A plurality of resistors R281 to 284 connected in series are provided between the output terminals of the amplifiers AP8 and AP9. The connection nodes connecting the resistors R281 to 284 serve as output terminals for the grayscale voltages. In the following description, the connection node between the resistors R282 and R283 is referred to as node n1, and the connection node between the resistors R283 and R284 is referred to as node n2.

[0045] The switch 31 is a first switch that is turned on when a voltage of logic level 0 (L level) is applied and turned off when a voltage of logic level 1 (H level) is applied. The switch 31 is composed of a P-channel MOS transistor. A power supply voltage VDDH is applied to the source of the transistor that constitutes the switch 31. The drain of the transistor that constitutes the switch 31 is connected to a node n1, which is a connection node between the resistors R283 and R282. The gate of the transistor that constitutes the switch 31 is connected to the output terminal of the comparator 32.

[0046] The first input terminal T1 of the comparator 32 is connected to the input terminal of the amplifier AP8, and the second input terminal T2 is connected to a node n2 which is a connection node between the resistors R283 and R284. The grayscale voltage V895 which is the input voltage of the amplifier AP8 is input to the first input terminal T1 of the comparator 32 as a comparison reference voltage. The second input terminal T2 of the comparator 32 is input to a voltage VT2 which is the voltage of the node n2.

[0047] The comparator 32 compares the comparison reference voltage (grayscale voltage V895) input to the first input terminal T1 with the voltage VT2 input to the second input terminal T2, and outputs an output signal VC indicating the comparison result. For example, in this embodiment, the comparator 32 outputs an output signal VC of logic level 0 (L level) when the voltage VT2 at the node n2 falls below the grayscale voltage V895, which is the comparison reference voltage, by a predetermined voltage value or more. The switch 31 receives the L level output signal VC and turns on.

[0048] On the other hand, when the voltage difference between the voltage VT2 of the node n2 and the gradation voltage V895 is less than a predetermined voltage value, the comparator 32 outputs an output signal VC of logic level 1 (H level). The switch 31 receives the output signal VC of H level and turns off.

[0049] 5 is a circuit diagram showing an example of the circuit configuration of the comparator 32. The comparator 32 is made up of transistors PM1, PM2, NM1, NM2, and NM3.

[0050] The transistors PM1 and PM2 are P-channel MOSFETs of a first conductivity type. The sources of the transistors PM1 and PM2 are commonly connected to a supply line of the power supply voltage VDDH. The gates of the transistors PM1 and PM2 are connected to each other and to the drain of the transistor PM1.

[0051] The transistors NM1 and NM2 are configured by N-channel MOSFETs, which are transistors of a second conductivity type. The drain of the transistor NM1 is connected to the drain of the transistor PM1. The drain of the transistor NM2 is connected to the drain of the transistor PM2. The sources of the transistors NM1 and NM2 are connected to each other.

[0052] A tap voltage TV is supplied to the gate of transistor NM1. In this embodiment, a voltage VT2, which is the voltage of node n2, is supplied to the gate of transistor MN1 as the tap voltage TV. A comparison reference voltage RV is supplied to the gate of transistor NM2. In this embodiment, a grayscale voltage V895, which is the input voltage of amplifier AP8, is supplied to the gate of transistor NM2 as the comparison reference voltage RV.

[0053] The transistor NM3 is an N-channel MOSFET, which is a second conductivity type transistor. The source of the transistor NM3 is grounded, and the drain is connected to the sources of the transistors NM1 and NM2. A bias voltage VB is applied to the gate of the transistor NM3.

[0054] The transistor NM3 functions as a constant current source circuit, and the constant current output by the transistor NM3 as a constant current source circuit is controlled by a bias voltage VB applied to the gate.

[0055] As described above, the comparator 32 switches the signal level of the output signal VC depending on whether the tap voltage TV (voltage VT2) is lower than the comparison reference voltage RV (grayscale voltage V895) by a predetermined value or more. The predetermined value is set based on the size ratio between the transistors PM1 and NM1 and the transistors PM2 and NM2.

[0056] With this configuration, the comparator 32 outputs an output signal VC of logic level 0 (L level) when the tap voltage TV (voltage VT2) falls below the comparison reference voltage RV (grayscale voltage V895) by a predetermined value or more. In response, the switch 31 is turned on, and the node n1 is connected to the voltage supply line of the power supply voltage VDDH. As a result, current is supplied to the node n1 via the voltage supply line of the power supply voltage VDDH, thereby suppressing the influence of a voltage drop during a voltage transition of the output of the source driver 14-1.

[0057] 6 is a diagram comparing the voltage drop observed when the grayscale voltage generation circuit 21 has the reference voltage generation circuit 25 configured as in this embodiment and when it does not have such a circuit. Here, the change in voltage VT1 at node n1 in this embodiment is shown by a solid line, and the voltage change when the grayscale voltage generation circuit 21 does not have the reference voltage generation circuit 25 configured as in this embodiment is shown by a dashed line (voltage VT0).

[0058] According to the gradation voltage generating circuit 21 of this embodiment, the switch 31 turns on in response to a drop in the voltage VT2, and current is supplied to the node n3 from the voltage supply line of the power supply voltage VDDH, so that the voltage drop can be suppressed compared to a case where a configuration such as the reference voltage generating circuit 25 is not provided.

[0059] Furthermore, since the voltage drop is suppressed, the original voltage level is restored more quickly than when the gradation voltage generation circuit 21 does not have a configuration like the reference voltage generation circuit 25. Therefore, the gradation voltage generation circuit 21 of this embodiment makes it possible to achieve high-speed operation of the output of the source driver 14-1. [Example]

[0060] Next, a description will be given of a second embodiment of the present invention. The grayscale voltage generating circuit of this embodiment differs from the grayscale voltage generating circuit 21 of the first embodiment in the configuration of the reference voltage generating circuit.

[0061] 7 is a circuit diagram showing the configuration of a reference voltage generating circuit 25A of this embodiment. In the comparator 32 of this embodiment, a first input terminal T1 is connected to the output terminal of the amplifier AP8, and a second input terminal T2 is connected to a node n2.

[0062] With this configuration, the comparator 32 compares the output voltage of the amplifier AP8 input to the first input terminal T1 as a comparison reference voltage with the voltage VT2 input to the second input terminal T2, and outputs an output signal VC indicating the comparison result.

[0063] Unlike the first embodiment, the reference voltage generating circuit 25A of the present embodiment inputs the output voltage of the amplifier A8, rather than the input voltage, to the first input terminal T1 of the comparator 32. Therefore, the potential difference between the voltage input to the first input terminal T1 and the voltage (VT2) input to the second input terminal is smaller than that of the first embodiment.

[0064] Therefore, the grayscale voltage generating circuit of this embodiment makes it possible to realize high-speed operation of the output of the source driver. [Example]

[0065] Next, a description will be given of a third embodiment of the present invention. The grayscale voltage generating circuit of this embodiment differs from the grayscale voltage generating circuits of the first and second embodiments in the configuration of the reference voltage generating circuit.

[0066] 8 is a circuit diagram showing the configuration of a reference voltage generating circuit 25B of this embodiment. In this embodiment, a comparator 32 has a first input terminal T1 connected to the input terminal of an amplifier AP8, and a second input terminal T2 connected to a node n1, which is a connection node between resistors R282 and R283. That is, a voltage VT1, which is the voltage at node n1, is input to the second input terminal T2 of the comparator 32.

[0067] With this configuration, the comparator 32 compares the output voltage of the amplifier AP8, which is input to the first input terminal T1 as a comparison reference voltage, with the voltage VT1 of the node n1, which is input to the second input terminal T2, and outputs an output signal VC indicating the comparison result.

[0068] Unlike the first embodiment, the reference voltage generating circuit 25B of the present embodiment inputs the voltage VT1 of the node n1, rather than the voltage VT2 of the node n2, to the second input terminal T2 of the comparator 32. That is, the node n1 is connected to the drain of the transistor that configures the switch 31, and is also connected to the second input terminal T2 of the comparator 32.

[0069] In the reference voltage generating circuit 25B of this embodiment, a common node of the ladder resistor is connected to one end of each of the switch 31 and the comparator 32. Therefore, compared to the case where different nodes are connected as in the first embodiment, the circuit can be simplified. [Example]

[0070] Next, a fourth embodiment of the present invention will be described. The grayscale voltage generating circuit of this embodiment differs from the grayscale voltage generating circuits of the first to third embodiments in the configuration of the reference voltage generating circuit.

[0071] 9 is a circuit diagram showing the configuration of a reference voltage generating circuit 25C of this embodiment. The source of the transistor constituting the switch 31 of this embodiment is connected to the output terminal of the amplifier AP9. The second input terminal T2 of the comparator 32 is connected to the node n1, as in the third embodiment.

[0072] As described in the first embodiment, the amplifier AP9 is a voltage follower operational amplifier, and therefore the output voltage of the amplifier AP9 is equal to the reference voltage VGH. Therefore, when the switch 31 is turned on, the output terminal of the amplifier AP9 is connected to the node n1, and the reference voltage VGH, which is the gamma power supply voltage, is supplied to the node n1.

[0073] The source of the transistor that constitutes the switch 31 can be connected to the output terminal of the amplifier AP9, which is closer, rather than to the supply line of the power supply voltage VDDH, which is the power supply voltage of the system, making it possible to further simplify the circuit than in Example 3. [Example]

[0074] Next, a fifth embodiment of the present invention will be described. The grayscale voltage generating circuit of this embodiment differs from the grayscale voltage generating circuits of the first to fourth embodiments in the configuration of the reference voltage generating circuit.

[0075] 10 is a circuit diagram showing the configuration of a reference voltage generating circuit 25D of this embodiment. Unlike the switch 31 of embodiments 1 to 4, the switch 41 of this embodiment is composed of an N-channel MOS transistor.

[0076] The drain of the transistor that constitutes the switch 41 is connected to a voltage supply line of the power supply voltage VSSH. The power supply voltage VSSH is a power supply voltage having a voltage level lower than the voltage VT1 of the node n1, which is the tap voltage.

[0077] The source of the transistor that constitutes the switch 41 is connected to a node n1 that is a connection node between the resistors R283 and R282. The gate of the transistor that constitutes the switch 41 is connected to the output terminal of the comparator .

[0078] The comparator 42 has a first input terminal T1 connected to the input terminal of the amplifier AP9 and a second input terminal T2 connected to the node n1. The comparator 42 compares the comparison reference voltage (grayscale voltage V1023) input to the first input terminal T1 with the voltage VT1 input to the second input terminal T2, and outputs an output signal VC indicating the comparison result.

[0079] When the voltage VT1 at the node n1 exceeds the gradation voltage V1023, which is the comparison reference voltage, by a predetermined voltage value or more, the comparator 42 outputs an output signal VC of logic level 1 (H level). The switch 41 receives the output signal VC of H level and turns on.

[0080] On the other hand, when the voltage difference between the voltage VT1 at the node n1 and the gradation voltage V1023 is less than a predetermined voltage value, the comparator 42 outputs an output signal VC of logic level 0 (L level). The switch 41 receives the output signal VC of L level and turns off.

[0081] With this configuration, in this embodiment, when the voltage VT1 exceeds the gradation voltage V1023, which is the comparison reference voltage, by a predetermined value or more, the comparator 42 outputs an output signal VC of logic level 1 (H level), and in response, the switch 41 is turned on. When the switch 41 is turned on, the node n1 is connected to the voltage supply line of the power supply voltage VSSH.

[0082] Since the power supply voltage VSSH is a power supply voltage lower than the voltage VT1, when the switch 41 is on, a discharge current flows from the node n1 to the voltage supply line of the power supply voltage VSSH.

[0083] According to the grayscale voltage generating circuit having the reference voltage generating circuit 25D of this embodiment, the switch 41 turns on in response to a voltage rise in the voltage VT1, and a discharge current flows from the node n1 to the voltage supply line of the power supply voltage VSSH. This makes it possible to suppress a voltage change in the opposite direction to that of the first to fourth embodiments, i.e., a voltage rise. Furthermore, it is possible to speed up the return of the voltage rise state to the original voltage level.

[0084] It should be noted that the present invention is not limited to the above-described embodiments. For example, in the above-described embodiments 1 to 3, one end of the switch 31 is connected to a voltage supply line of the power supply voltage VDDH, and in the above-described embodiment 4, one end of the switch 31 is connected to the output terminal of the amplifier AP9. However, the connection destination of the one end of the switch 31 is not limited to these, and it may be connected to a voltage supply line that supplies a voltage (first voltage) that is higher than the voltage of the node n1. Similarly, in the above-described embodiment 5, the connection destination of the one end of the switch 41 is not limited to these, and it may be connected to a voltage supply line that supplies a voltage (first voltage) that is lower than VSSH.

[0085] Furthermore, in the above-described embodiments, an example has been described in which node n1, which is a connection node between resistors R282 and R283 among multiple resistors (R281 to 284) connected in series between the output terminal of amplifier AP8 and the output terminal of amplifier AP9, is connected to the other terminal of switch 31 or 41. However, the connection destination of the other terminal of switch 31 or 41 is not limited to this, and it may be connected to any one of multiple connection nodes (connection node group) connecting resistors R281 to 284. In other words, it is only necessary that any one connection node of the connection node group is connected to the voltage supply line of the first voltage when switch 31 or 41 is turned on.

[0086] Furthermore, in each of the above embodiments, the reference voltage generating circuit is provided between the amplifiers AP8 and AP9, but a similar configuration may be provided between the other amplifiers AP0 to AP8.

[0087] Furthermore, the configurations of the above-described embodiments can be used in appropriate combination. For example, in a configuration in which the switch 41 is configured by an N-channel MOS transistor and the first input terminal T1 of the comparator 42 is connected to the voltage supply line of the power supply voltage VSSH as in the fifth embodiment, the second input terminal T2 of the comparator 42 may be connected to the node n2 as in the first embodiment, instead of the node n1. [Explanation of symbols]

[0088] 100 display device 11 Display panel 12 Timing Controller 13 Gate Driver 14A Source Driver 14B Source Driver 15 Reference voltage source 21 Gradation voltage generation circuit 22 Data acquisition section 23 DA conversion section 24 Output section 25 Reference voltage generation circuit 31,41 Switch 32,42 Comparator

Claims

1. A grayscale voltage generating circuit that generates a plurality of grayscale voltages corresponding to each luminance level in a luminance range that can be expressed by a video signal, based on a first reference voltage and a second reference voltage having mutually different voltage levels, a plurality of gamma amplifiers that receive input of a plurality of gamma reference voltages including the first reference voltage, the second reference voltage, and a voltage obtained by dividing a voltage between the first reference voltage and the second reference voltage, and that individually amplify the plurality of gamma reference voltages; a ladder resistor including a plurality of resistors connected in series between the outputs of adjacent gamma amplifiers among the plurality of gamma amplifiers, and outputting the plurality of gradation voltages generated by dividing a voltage between a gamma reference voltage corresponding to the first reference voltage and a gamma reference voltage corresponding to the second reference voltage from each of connection nodes connecting the resistors of the plurality of resistors; a comparator that compares a voltage of one of a plurality of connection nodes between output terminals of a first gamma amplifier and a second gamma amplifier that are adjacent to each other among the plurality of gamma amplifiers, with a reference voltage; a switch that connects any one of the connection nodes to a voltage supply line of a first voltage based on a comparison result of the comparator; A grayscale voltage generating circuit comprising:

2. 2. The grayscale voltage generating circuit according to claim 1, wherein the switch connects the first connection node to a voltage supply line of the first voltage based on a comparison result of the comparator.

3. 2. The gradation voltage generating circuit according to claim 1, wherein the switch connects another connection node, among the plurality of connection nodes constituting the connection node group, that is positioned adjacent to the one connection node, to a voltage supply line of the first voltage, based on the comparison result of the comparator.

4. 2. The gradation voltage generating circuit according to claim 1, wherein the switch connects one of the connection nodes in the group of connection nodes to a voltage supply line of the first voltage when a voltage difference between the reference voltage and the voltage of the one connection node is a predetermined voltage difference or more.

5. 2. The grayscale voltage generating circuit according to claim 1, wherein the reference voltage is an input voltage of the second gamma amplifier.

6. 2. The grayscale voltage generating circuit according to claim 1, wherein the reference voltage is an output voltage of the second gamma amplifier.

7. 2. The grayscale voltage generating circuit according to claim 1, wherein the first voltage is an output voltage of the first gamma amplifier.

8. 2. The grayscale voltage generating circuit according to claim 1, wherein the first voltage is a power supply voltage.

9. A source driver is connected to a display panel having a plurality of pixel units arranged in a matrix at each of intersections of a plurality of data lines and a plurality of gate lines, and generates grayscale voltage signals to be supplied to the plurality of pixel units based on image data, a grayscale voltage generating circuit that generates a plurality of grayscale voltages corresponding to each luminance level in a luminance range that can be expressed by a video signal, based on a first reference voltage and a second reference voltage having mutually different voltage levels; The gradation voltage generating circuit a plurality of gamma amplifiers that receive input of a plurality of gamma reference voltages including the first reference voltage, the second reference voltage, and a voltage obtained by dividing a voltage between the first reference voltage and the second reference voltage, and that individually amplify the plurality of gamma reference voltages; a ladder resistor including a plurality of resistors connected in series between the outputs of adjacent gamma amplifiers among the plurality of gamma amplifiers, and outputting the plurality of gradation voltages generated by dividing a voltage between a gamma reference voltage corresponding to the first reference voltage and a gamma reference voltage corresponding to the second reference voltage from each of connection nodes connecting the resistors of the plurality of resistors; a comparator that compares a voltage of one of a plurality of connection nodes between output terminals of a first gamma amplifier and a second gamma amplifier that are adjacent to each other among the plurality of gamma amplifiers, with a reference voltage; a switch that connects any one of the connection nodes to a voltage supply line of a first voltage based on a comparison result of the comparator; A source driver comprising:

10. a display panel including a plurality of data lines and a plurality of gate lines, and a plurality of pixel units arranged in a matrix at each of the intersections of the plurality of data lines and the plurality of gate lines; a display controller that outputs image data signals representing an image to be displayed on the display panel; a source driver that receives the image data signal from the display controller and generates, based on the image data signal, a grayscale voltage signal to be supplied to the plurality of pixel units; A display device having: the source driver has a grayscale voltage generating circuit that generates a plurality of grayscale voltages corresponding to each luminance level in a luminance range that can be expressed by a video signal, based on a first reference voltage and a second reference voltage having mutually different voltage levels; The gradation voltage generating circuit a plurality of gamma amplifiers that receive input of a plurality of gamma reference voltages including the first reference voltage, the second reference voltage, and a voltage obtained by dividing a voltage between the first reference voltage and the second reference voltage, and that individually amplify the plurality of gamma reference voltages; a ladder resistor including a plurality of resistors connected in series between the outputs of adjacent gamma amplifiers among the plurality of gamma amplifiers, and outputting the plurality of gradation voltages generated by dividing a voltage between a gamma reference voltage corresponding to the first reference voltage and a gamma reference voltage corresponding to the second reference voltage from each of connection nodes connecting the resistors of the plurality of resistors; a comparator that compares a voltage of one of a plurality of connection nodes between output terminals of a first gamma amplifier and a second gamma amplifier that are adjacent to each other among the plurality of gamma amplifiers, with a reference voltage; a switch that connects any one of the connection nodes to a voltage supply line of a first voltage based on a comparison result of the comparator; A display device comprising:

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