Memory management device and memory management method

Abstract

To provide a memory management device that prevents a reduction in a TLB hit ratio of sporadic memory access in a driver or the like.SOLUTION: An information processing device 1 includes a memory management device 10 that performs conversion between a virtual address and a physical address in memory access. A control unit 103 included in the memory management device, upon registration of Translation Lookaside Buffer (TLB) 101, registers a length of a range of the virtual address to be converted in an entry of a tag 102, and when the entry of the TLB 101 is full, removes the entry having the maximum length from the tag 102 and the TLB 101.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a memory management device and a memory management method. [Background technology]

[0002] Generally, each process running on an Operating System (OS) has an independent virtual address space, and the process accesses main memory using virtual addresses. The Memory Management Unit (MMU) built into the processor converts these virtual addresses into physical addresses in main memory and performs memory access. To perform this conversion quickly, the MMU has an internal translation table that records the correspondence between virtual addresses and physical addresses. This translation table is called the Translation Lookaside Buffer (TLB).

[0003] The Least Recently Used (LRU) method is known as the method by which the MMU evicts entries from the TLB. LRU evicts the entry with the oldest reference time in the TLB. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2019-527900 [Patent Document 2] Japanese Patent Application Laid-Open No. 2005-108262 [Non-patent literature]

[0005] [Non-Patent Document 1] Nadav Amit et al. “IOMMU: Strategies for Mitigating the IOTLB Bottleneck” ISCA 2010 International Workshops: Computer Architecture pp 256-274, June 19-23, 2010 Summary of the Invention [Problem to be solved by the invention]

[0006] However, when flushing TLB entries using LRU, there is a risk that the TLB hit rate will decrease when sporadic memory accesses occur in drivers, etc.

[0007] One aspect of this is to prevent a decrease in the TLB hit rate due to sporadic memory accesses in drivers and the like. [Means for solving the problem]

[0008] In one aspect, a memory management device is a memory management device that converts between virtual addresses and physical addresses during memory access, and is equipped with a control unit that, when registering in a Translation Lookaside Buffer (TLB), registers the length of the range of virtual addresses to be converted in a tag entry, and when there is no more free space in the TLB entries, evicts the entry with the longest length from the tag and the TLB. [Effects of the Invention]

[0009] In one aspect, it is possible to prevent a decrease in the TLB hit rate due to sporadic memory accesses in drivers and the like. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 10 is a diagram illustrating the correspondence between a virtual address space and a physical address space in a related example. [Figure 2]10A and 10B are diagrams illustrating the configuration of a TLB and address translation processing in a related example. [Figure 3] FIG. 10 is a diagram illustrating a TLB entry eviction process in a related example. [Figure 4] FIG. 2 is a block diagram illustrating an example of the software configuration of an MMU according to an embodiment. [Figure 5] FIG. 5 is a diagram illustrating the configuration of the tag shown in FIG. 4. [Figure 6] 10A and 10B are diagrams illustrating a TLB entry eviction process according to an embodiment. [Figure 7] 10 is a flowchart illustrating a memory management process according to an embodiment. [Figure 8] FIG. 10 is a diagram illustrating an example of a tag configuration in a first modified example. [Figure 9] 10 is a flowchart illustrating a memory management process in a first modified example. [Figure 10] FIG. 10 is a diagram illustrating a configuration of a tag in a second modified example. [Figure 11] 10 is a flowchart illustrating a memory management process in a second modified example. [Figure 12] FIG. 1 is a block diagram illustrating an example of a hardware configuration of an information processing device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] [A] Related Examples FIG. 1 is a diagram for explaining the correspondence between a virtual address space 601 and a physical address space 602 in a related example.

[0012] 1, translation between a virtual address in a virtual address space 601 and a physical address in a physical address space 602 is performed in fixed units called pages. One entry in the TLB corresponds to one page.

[0013] FIG. 2 is a diagram for explaining the configuration of the TLB 61 and the address translation process in the related example.

[0014] When each process 603 accesses memory, the MMU 60 (described later with reference to FIG. 3) receives translation information such as a virtual address and an address space ID assigned to each process 603 .

[0015] The MMU 60 searches its internal tag 62 based on this translation information. The tag 62 links the translation information to the TLB 61, and each entry contains translation information. If the MMU 60 finds a tag 62 entry that matches the translation information from the process 603, it reads the corresponding TLB 61 and translates it into a physical address. If the MMU 60 does not find a matching tag 62 entry, it reads a table from the main memory that lists the correspondence between virtual addresses and physical addresses and performs address translation.

[0016] Furthermore, when a TLB miss occurs, the MMU 60 registers the translation information and physical address information in the respective entries of the tag 62 and TLB 61 described above.

[0017] Thereafter, when performing address translation for the same page range, the entry registered in tag 62 matches the translation information from process 603, so MMU 60 reads the entry registered in TLB 61 and performs address translation. A match between the tag and registered information is called a TLB hit, and a mismatch is called a TLB miss.

[0018] The tag 62 and the TLB 61 are physically stored in a flip-flop (FF) or random access memory (RAM) inside the MMU 60. When registering a new entry in the tag 62 and the TLB 61, if the FF or RAM is full of existing tag 62 and TLB 61 entries, the MMU 60 evicts the tag 62 and the TLB 61 entries from these and registers the new entry. The tag 62 and the TLB 61 entries to be evicted are selected from those predicted not to be used in subsequent address translations. The accuracy of this prediction is important to increase the TLB hit rate.

[0019] According to Non-Patent Document 1, Direct Memory Access mapping (DMA mapping) in an Input Output (IO) device 7 (described later with reference to FIG. 3) is classified as follows: DMA mapping is the correspondence between virtual addresses and physical addresses in data transfer between the IO device 7 and main memory.

[0020] Consistent DMA mappings: Used to control descriptor ring buffers, etc. Exists from driver initialization to termination.

[0021] Streaming DMA mappings: For DMA transfers. They are unmapped when the DMA transfer is complete.

[0022] The tag 62 and TLB 61 entries corresponding to Consistent DMA Mapping are assumed not to be evicted because they are used until the driver is terminated. On the other hand, Streaming DMA Mapping is not used after the data transfer is completed, so even if it is evicted, it is assumed that the TLB hit rate will not decrease.

[0023] However, since the MMU 60 cannot recognize the termination of the driver, it may evict the tag 62 and TLB 61 entries corresponding to outdated consistent DMA mappings, which may reduce the TLB hit rate for sporadic memory accesses by the driver, etc.

[0024] FIG. 3 is a diagram for explaining the entry eviction process of the TLB 61 in the related example.

[0025] 3, the MMU 60 receives an address translation request from the IO device 7. The IO device 7 operates as follows to perform a DMA transfer.

[0026] The IO device 7 reads the ring buffer in the main memory and acquires the DMA descriptor, which contains the address and length of the transfer target.

[0027] The IO device 7 performs DMA transfer by reading the main memory based on the contents of this DMA descriptor. The address of the ring buffer held by the IO device 7 and the address written in the DMA descriptor are virtual addresses.

[0028] FIG. 3 shows the address conversion process when the IO device 7 performs a DMA transfer.

[0029] The IO device 7 sends a conversion request for the address of the ring buffer (for example, virtual address A1) to the MMU 60 in order to obtain a DMA Descriptor (step S1).

[0030] The MMU 60 converts the virtual address and sends a conversion result response to the IO device 7. The MMU 60 also stores the conversion result in the tag 62 and the TLB 61 (step S2). At this point, the tag A is registered in the tag 62, and the physical address A is registered in the TLB 61. It is assumed that the DMA Descriptor instructs the transfer of virtual addresses B to E.

[0031] The IO device 7 sends a conversion request for the virtual addresses B to E to the MMU 60 (step S3).

[0032] The MMU 60 performs virtual address translation and returns the translation result to the IO device. The MMU 60 also saves the translation result in the tag 62 and the TLB 61. When the last virtual address E is to be stored, the entries in the tag 62 and the TLB 61 become full, and it is necessary to select an entry in the tag 62 and the TLB 61 to be evicted instead. The least recently referenced entries in the tag 62 and the TLB 61 are the tag A and the physical address A, which describe the translation result of the DMA Descriptor. Therefore, the MMU 60 uses the LRU to evict the tag A and the physical address A, and registers the tag E and the physical address E in each of the freed entries (step S4). At this point, the tags E, B, C, and D are registered in the tag 62, and the physical addresses E, B, C, and D are registered in the TLB 61.

[0033] After completing the transfer of virtual addresses B to E, the IO device 7 sends a translation request for virtual address A2 to the MMU 60 to read the next DMA Descriptor. As mentioned above, the DMA Descriptor contains only the data transfer instruction content, so its data size is small. Therefore, the virtual addresses A1 and A2 read in step S1 remain in a small range of virtual addresses and generally fit within the same page. The translation information for virtual address A2 is expected to match tag A. However, because the MMU 60 flushed tag A in step S4, a TLB miss occurs, and the translation process takes time (step S5).

[0034] [B] Embodiment An embodiment will be described below with reference to the drawings. However, the embodiment described below is merely an example, and is not intended to exclude various modifications or application of techniques not explicitly stated in the embodiment. In other words, this embodiment can be implemented with various modifications within the scope of its purpose. Furthermore, each figure does not intend to include only the components shown in the figure, but may include other components, etc.

[0035] [B-1] Software configuration example FIG. 4 is a block diagram illustrating an example of the software configuration of the MMU 10 according to the embodiment.

[0036] 4 is an example of a memory management device, and is provided in an information processing device 1, which will be described later with reference to FIG.

[0037] The control unit 103 performs memory read from a main memory (for example, a memory 12 described later with reference to FIG. 12). The control unit 103 receives a virtual address translation request from a processor (for example, corresponding to a CPU 11 described later with reference to FIG. 12) or an IO device 2 (described later with reference to FIG. 6), and after translation, performs DMA for the translated physical address using the tag 102 and the TLB 101.

[0038] For this reason, the processor or IO device 2 sends the virtual address, the address space ID, the type of DMA (Read / Write), and the size of the DMA used as a virtual address translation request to the MMU 10.

[0039] FIG. 5 is a diagram illustrating the configuration of the tag 102 shown in FIG.

[0040] The tag 102 shown in FIG. 5 includes conversion information and a usage size.

[0041] The translation information includes a virtual address, an address space ID, and a page size.

[0042] The used size indicates the length of the range of virtual addresses to be translated (in other words, the range of virtual addresses to be translated). The used size is transmitted in a virtual address translation request from the processor or the IO device 2, and is a unique field in this embodiment that indicates the size of the translation request related to the tag 102. The control unit 103 determines the entry of the TLB 101 to be evicted based on the used size of the tag 102.

[0043] In other words, when registering in TLB 101, control unit 103 registers the length of the range of virtual addresses to be translated in an entry of tag 102. When there are no more free entries in TLB 101, control unit 103 evicts the entry with the longest length from tag 102 and TLB 101.

[0044] FIG. 6 is a diagram illustrating the process of evicting entries from the TLB 101 in this embodiment.

[0045] The IO device 2 sends a conversion request for the address of the ring buffer (for example, virtual address A1) to the MMU 10 in order to obtain a DMA Descriptor (step S11).

[0046] The MMU 10 converts the virtual address and returns a conversion result response to the IO device 2. The MMU 10 also stores the conversion result in the tag 102 and an entry in the TLB 101. The MMU 10 also stores the size (n) of the address requested for conversion in the tag 102 (step S12). In other words, n is the size of the DMA descriptor, and corresponds to the length included in the tag 102 shown in FIG. 5. It is assumed that the DMA descriptor instructs the transfer of virtual addresses B to E.

[0047] The IO device 2 sends a conversion request for the virtual addresses B to E to the MMU 10 (step S13).

[0048] The MMU 10 performs virtual address translation and returns the translation result to the IO device. The MMU 10 also saves the translation result in the tag 102 and the entries in the TLB 101. When the last virtual address E is to be stored, the entries in the tag 102 and the TLB 101 will be full, and it will be necessary to select an entry in the tag 102 and the TLB 101 to be evicted instead. The MMU 10 evicts the entry with the largest size recorded in the tag 102. The size recorded in the tag A is n, and the sizes recorded in the tags B to E are m. n is the DMA Descriptor size, and is smaller than m because it describes only the data transfer instruction content. Therefore, the MMU 10 does not evict the tag A, but evicts the tag B (step S14).

[0049] After completing the transfer of virtual addresses B to E, IO device 2 sends a translation request for virtual address A2 to MMU 10 to read the next DMA Descriptor. As mentioned above, the DMA Descriptor contains only the data transfer instruction content, so its data size is small. Therefore, virtual addresses A1 and A2 read in step S1 remain in a small range of virtual addresses and generally fit within the same page. The translation information for virtual address A2 is expected to match tag A. Since tag A has not been flushed from TLB 101 of MMU 10, a TLB hit occurs (step S15).

[0050] The memory management process in this embodiment will be described with reference to the flowchart (steps S21 to S27) shown in FIG.

[0051] The control unit 103 of the MMU 10 receives the virtual address translation request and searches the TLB 101 to see if there is a corresponding entry (step S21).

[0052] The control unit 103 determines whether there is a TLB hit (step S22).

[0053] If a TLB hit occurs (see the Yes route in step S22), the control unit 103 issues a DMA using the converted physical address (step S23), and the memory management process in this embodiment ends.

[0054] On the other hand, if there is no TLB hit (see the No route in step S22), the control unit 103 reads the translation table from the main memory and obtains the physical address for the virtual address (step S24).

[0055] The control unit 103 determines whether there is free space in the tag 102 and the entry of the TLB 101 (step S25).

[0056] If there is free space in the entries of tag 102 and TLB 101 (see the Yes route in step S25), control unit 103 registers tag 102 and TLB 101 related to the physical address obtained from the translation table of the main memory in step S24 in the free entry. Control unit 103 also registers the usage size included in tag 102 searched in step S21 in the free entry (step S26). Then, the process proceeds to step S23.

[0057] On the other hand, if there is no free space in the tag 102 or the TLB 101 entries (see the No route in step S25), the control unit 103 evicts the tag 102 entry with the largest used size value (step S27). Then, the process proceeds to step S26.

[0058] [B-2] First Modified Example FIG. 8 is a diagram illustrating a configuration of a tag in the first modified example.

[0059] The first modification combines the LRU method with the above-described embodiment. If there are multiple entries with the largest tag size, the entry in tag 102 and TLB 101 with the oldest usage time is evicted. Because data references have temporal locality, the oldest entry is less likely to be used.

[0060] The tag 102a shown in FIG. 8 includes conversion information, a used size, and a used time.

[0061] The translation information includes a virtual address, an address space ID, and a page size, as in the above-described embodiment.

[0062] As in the above-described embodiment, the usage size indicates the length of the range of virtual addresses to be translated (in other words, the size of the translation request related to the tag 102a).

[0063] The use time indicates the time when the entry in the tag 102a was last used.

[0064] The control unit 103 determines the entry of the TLB 101 to be evicted based on the used size and used time of the entry in the tag 102a.

[0065] When registering an entry in TLB 101, control unit 103 also registers the last use time of the virtual address in the entry in tag 102a. When there are no more free entries in TLB 101 and there are multiple entries with the maximum length, control unit 103 evicts the entry with the oldest use time from tag 102a and TLB 101 among the multiple entries with the maximum length.

[0066] The memory management process in the first modified example will be described with reference to the flowchart (steps S31 to S40) shown in FIG.

[0067] The control unit 103 of the MMU 10 receives the virtual address translation request and searches the TLB 101 to see if there is a corresponding entry (step S31).

[0068] The control unit 103 determines whether there is a TLB hit (step S32).

[0069] If a TLB hit occurs (see the Yes route in step S32), the control unit 103 updates the use time of the entry of the tag 102 that has been hit (step S33).

[0070] The control unit 103 issues a DMA using the converted physical address (step S34), and the memory management process in the first modified example is then completed.

[0071] If there is no TLB hit (see the No route in step S32), the control unit 103 reads the translation table from the main memory and obtains the physical address for the virtual address (step S35).

[0072] The control unit 103 determines whether there is a free space in the tag 102a and the entry of the TLB 101 (step S36).

[0073] If there is a free entry in the tag 102a and the TLB 101 (see the Yes route in step S36), the control unit 103 registers the tag 102a and the TLB 101 related to the physical address obtained from the translation table of the main memory in step S34 in the free entry. The control unit 103 also registers the used size and used time included in the tag 102a searched in step S31 in the free entry (step S37). Then, the process proceeds to step S34.

[0074] On the other hand, if there is no free space in the tag 102a and the entries of the TLB 101 (see the No route in step S36), the control unit 103 determines whether there are multiple entries of the tag 102a with the largest used size value (step S38).

[0075] If there are multiple entries of tag 102a with the largest used size (see the Yes route in step S38), control unit 103 evicts the entry of tag 102a with the oldest used time from among the entries of tag 102a with the largest used size (step S39). Then, the process proceeds to step S37.

[0076] On the other hand, if there are not multiple entries of tag 102a with the largest used size value (see No route in step S38), control unit 103 evicts the entry of tag 102a with the largest used size value (step S40), and the process proceeds to step S37.

[0077] [B-3] Second Modified Example FIG. 10 is a diagram illustrating the configuration of a tag 102b in the second modified example.

[0078] The second modification corresponds to the case where the processor or the IO device 2 performs DMA to discontinuous (in other words, discrete) addresses.

[0079] When data is read / written to discontinuous addresses in a two-dimensional matrix data arrangement, the addresses are discontinuous and the MMU 10 issues multiple DMAs with small usage sizes.

[0080] For this reason, in the above-described embodiment and first modification based on the usage size, this discontinuous DMA is not recognized as a Streaming DMA mapping, and it is possible that it may remain in the TLB 101.

[0081] In the case of discontinuous DMA, the number of DMAs is large, and the number of conversion requests is also large. Therefore, in the second modified example, memory management is performed based on the number of conversion requests issued by the processor or the IO device 2, instead of the usage size.

[0082] When registering an entry in TLB 101, control unit 103 registers the number of translation requests issued for the same virtual address unit in the entry in tag 102b. When there are no more free entries in TLB 101, control unit 103 evicts from tag 102b and TLB 101 the entry with the largest number of requests that are assumed to be translation requests for discontinuous addresses.

[0083] The tag 102a shown in FIG. 10 includes conversion information and the number of conversion requests.

[0084] The translation information includes a virtual address, an address space ID, and a page size, as in the above-described embodiment and first modification.

[0085] The number of conversion requests indicates the number of requests to the MMU 10 to convert a virtual address issued by the processor or the IO device 2 into a physical address.

[0086] The control unit 103 determines the entry of the TLB 101 to be evicted based on the number of translation requests for the entry of the tag 102b.

[0087] The memory management process in the second modified example will be described with reference to the flowchart (S41 to S49) shown in FIG.

[0088] The control unit 103 of the MMU 10 receives the virtual address translation request and searches the TLB 101 to see if there is a corresponding entry (step S41).

[0089] The control unit 103 manages the number of conversion requests for each processor and IO device 2, and increments the number of conversion requests by 1 (step S42). Note that the control unit 103 receives conversion requests in parallel with the conversion process, and increments the number of conversion requests by 1 every time a conversion request is received.

[0090] The control unit 103 determines whether there is a TLB hit (step S43).

[0091] If a TLB hit occurs (see the Yes route in step S43), the control unit 103 decrements the number of conversion requests for each processor and IO device 2 by 1 when the conversion process is completed (step S44).

[0092] The control unit 103 issues a DMA using the converted physical address (step S45), and the memory management process in the second modified example ends.

[0093] If there is no TLB hit (see the No route in step S43), the control unit 103 reads the translation table from the main memory and obtains the physical address for the virtual address (step S46).

[0094] The control unit 103 determines whether there is a free space in the tag 102b and the entry in the TLB 101 (step S47).

[0095] If there is a vacant entry in tag 102b and TLB 101 (see the Yes route in step S47), control unit 103 registers tag 102b and TLB 101 related to the physical address obtained from the translation table in the main memory in step S46 in the vacant entry. Control unit 103 then registers the number of translation requests managed in the translation request number field of tag 102b in the vacant entry (step S48). Then, the process proceeds to step S44.

[0096] On the other hand, if there are no free entries in the tag 102b and the TLB 101 (see the No route in step S47), the control unit 103 evicts the entry in the tag 102b and the TLB 101 with the largest number of translation requests in order to register the translation result in the entry in the tag 102b and the TLB 101 (step S49). Then, the process proceeds to step S48.

[0097] [B-4] Hardware configuration example FIG. 12 is a block diagram schematically illustrating an example of the hardware configuration of the information processing device 1 according to the embodiment.

[0098] 12, the information processing device 1 includes an MMU 10 (described above with reference to FIG. 4), a CPU 11, a memory 12, a display control device 13, a storage device 14, an input interface (IF) 15, an external recording medium processing device 16, and a communication IF 17. The information processing device 1 may be a server, a supercomputer, or the like.

[0099] The memory 12 is an example of a storage unit, and is illustratively a read-only memory (ROM) and a RAM. A program such as a basic input / output system (BIOS) may be written to the ROM of the memory 12. The software program in the memory 12 may be read and executed by the CPU 11 as appropriate. The RAM of the memory 12 may be used as a temporary storage memory or a working memory.

[0100] The display control device 13 is connected to the display device 131 and controls the display device 131. The display device 131 is a liquid crystal display, an organic light-emitting diode (OLED) display, a cathode ray tube (CRT), an electronic paper display, or the like, and displays various information to the operator of the information processing device 1. The display device 131 may be combined with an input device, and may be, for example, a touch panel. The display device 131 displays various information to the operator of the information processing device 1.

[0101] The storage device 14 may be, for example, a solid state drive (SSD), a storage class memory (SCM), or a hard disk drive (HDD).

[0102] The input IF 15 may be connected to input devices such as a mouse 151 and a keyboard 152, and may control the input devices such as the mouse 151 and the keyboard 152. The mouse 151 and the keyboard 152 are examples of input devices, and an operator performs various input operations via these input devices.

[0103] The external recording medium processing device 16 is configured so that a recording medium 160 can be attached thereto. The external recording medium processing device 16 is configured so that, when the recording medium 160 is attached, the information recorded on the recording medium 160 can be read. In this example, the recording medium 160 is portable. For example, the recording medium 160 is a non-transitory recording medium such as a flexible disk, an optical disk, a magnetic disk, a magneto-optical disk, or a semiconductor memory.

[0104] The communication IF 17 is an interface that enables communication with an external device.

[0105] The CPU 11 is an example of a processor, and is a processing device that performs various controls and calculations. The CPU 11 realizes various functions by executing an OS and programs loaded into the memory 12. The CPU 11 may be a multiprocessor including multiple CPUs, a multi-core processor having multiple CPU cores, or a configuration having multiple multi-core processors.

[0106] The device for controlling the overall operation of the information processing device 1 is not limited to the CPU 11, and may be, for example, any one of an MPU, a DSP, an ASIC, a PLD, and an FPGA. The device for controlling the overall operation of the information processing device 1 may also be a combination of two or more of the CPU, MPU, DSP, ASIC, PLD, and FPGA. MPU is an abbreviation for Micro Processing Unit, DSP is an abbreviation for Digital Signal Processor, and ASIC is an abbreviation for Application Specific Integrated Circuit. PLD is an abbreviation for Programmable Logic Device, and FPGA is an abbreviation for Field Programmable Gate Array.

[0107] [C] Effect According to the memory management device and memory management method in the above-described embodiment, first modification, and second modification, the following advantageous effects can be achieved, for example.

[0108] When registering in TLB 101, control unit 103 registers the length of the range of virtual addresses to be translated in an entry of tag 102. When there are no more free entries in TLB 101, control unit 103 evicts the entry with the longest length from tag 102 and TLB 101.

[0109] This prevents a drop in the TLB hit rate due to sporadic memory accesses in drivers, etc.

[0110] The control unit 103 also registers the last use time of the virtual address in the entry of the tag 102a when registering in the TLB 101. When there are no more free entries in the TLB 101 and there are multiple entries with the maximum length, the control unit 103 evicts the entry with the oldest use time from the tag 102a and the TLB 101 among the multiple entries with the maximum length.

[0111] This allows for appropriate memory management that takes advantage of the temporal locality of data reference.

[0112] The control unit 103 registers the number of translation requests issued for the same virtual address unit in an entry of the tag 102b when registering in the TLB 101. When there are no more free entries in the TLB 101, the control unit 103 evicts the entry with the largest number of requests from the tag 102b and the TLB 101.

[0113] This allows appropriate memory management to be performed when performing DMA to discontinuous (in other words, discrete) addresses.

[0114] [D] Other The disclosed technology is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present embodiment. The configurations and processes of the present embodiment can be selected or combined as needed.

[0115] [E] Supplementary Note The following additional notes are disclosed regarding the above embodiment, first modified example, and second modified example.

[0116] (Appendix 1) A memory management device that performs conversion between virtual addresses and physical addresses in memory access, When registering the translation lookaside buffer (TLB), the length of the range of the virtual address to be translated is registered in a tag entry; When there is no free space in the TLB entries, the entry with the maximum length is evicted from the tag and the TLB. A memory management device comprising a control unit.

[0117] (Appendix 2) The control unit When registering the TLB, the last use time of the virtual address is further registered in the tag entry; When there is no free entry in the TLB and there are multiple entries with the maximum length, the entry with the oldest usage time among the multiple entries with the maximum length is evicted from the tag and the TLB. 2. The memory management apparatus of claim 1.

[0118] (Appendix 3) A memory management device that performs conversion between virtual addresses and physical addresses in memory access, When registering a Translation Lookaside Buffer (TLB), the number of translation requests issued for the same virtual address unit is registered in a tag entry; When there is no free space in the TLB entries, the entry with the largest number of requests is evicted from the tag and the TLB. A memory management device comprising a control unit.

[0119] (Appendix 4) A memory management method using a memory management device that converts between virtual addresses and physical addresses in memory access, comprising: When registering the translation lookaside buffer (TLB), the length of the range of the virtual address to be translated is registered in a tag entry; When there is no free space in the TLB entries, the entry with the maximum length is evicted from the tag and the TLB. A memory management method in which processing is executed by the memory management device.

[0120] (Appendix 5) When registering the TLB, the last use time of the virtual address is further registered in the tag entry; When there is no free entry in the TLB and there are multiple entries with the maximum length, the entry with the oldest usage time among the multiple entries with the maximum length is evicted from the tag and the TLB. 5. The memory management method according to claim 4, wherein processing is performed by the memory management device.

[0121] (Appendix 6) A memory management method using a memory management device that converts between virtual addresses and physical addresses in memory access, comprising: When registering a Translation Lookaside Buffer (TLB), the number of translation requests issued for the same virtual address unit is registered in a tag entry; When there is no free space in the TLB entries, the entry with the largest number of requests is evicted from the tag and the TLB. A memory management method in which processing is executed by the memory management device. [Explanation of symbols]

[0122] 1: Information processing equipment 10: MMU 101, 61:TLB 102, 102a, 102b, 62: Tags 103: Control unit 11: CPU 12: Memory 13: Display control device 131:Display device 14:Storage device 15: Input IF 151: Mouse 152: Keyboard 16: External recording medium processing device 160: Recording media 17: Communication IF 2, 7: IO devices 601: Virtual Address Space 602: Physical address space 603: Process

Claims

1. A memory management device that performs conversion between virtual addresses and physical addresses in memory access, When registering in a Translation Lookaside Buffer (TLB), a length of the range of the virtual address to be translated is registered in a tag entry; When there is no free space in the TLB entries, the entry with the maximum length is evicted from the tag and the TLB. A memory management device comprising a control unit.

2. The control unit When registering the TLB, the last use time of the virtual address is further registered in the tag entry; When there is no free entry in the TLB and there are multiple entries with the maximum length, the entry with the oldest usage time among the multiple entries with the maximum length is removed from the tag and the TLB. The memory management unit of claim 1 .

3. A memory management device that performs conversion between virtual addresses and physical addresses in memory access, When registering a Translation Lookaside Buffer (TLB), the number of translation requests issued for the same virtual address unit is registered in a tag entry; When there is no free space in the TLB entries, the entry with the largest number of requests is evicted from the tag and the TLB. A memory management device comprising a control unit.

4. A memory management method using a memory management device that performs conversion between virtual addresses and physical addresses in memory access, comprising: When registering in a Translation Lookaside Buffer (TLB), a length of the range of the virtual address to be translated is registered in a tag entry; When there is no free space in the TLB entries, the entry with the maximum length is evicted from the tag and the TLB. A memory management method in which processing is executed by the memory management device.

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