Display device and electronic apparatus including the same

Abstract

To provide a display device in which display quality is displayed by preventing a display failure in which a portion of a display surface of the display device is viewed as a dark color.SOLUTION: A display device comprises: a base layer divided into a display region and a non-display region surrounding at least a portion of the display region; a circuit element layer including a driver disposed on the base layer and overlapping the non-display region; and a display element layer disposed on the circuit element layer. The display element layer includes a pixel defining layer disposed on the circuit element layer, and a light emission element overlapping the display region and including a light emission layer. The pixel defining layer includes a light emission opening overlapping the display region and at least having the light emission layer disposed in the light emission opening, a driving opening overlapping the non-display region and overlapping the driver, and a dummy opening overlapping the non-display region and disposed between the light emission opening and the driving opening. The dummy opening has a planar shape substantially the same as that of the light emission opening or the driving opening.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a display device and an electronic device including the same. [Background technology]

[0002] Generally, electronic devices that provide images to users, such as smartphones, digital cameras, laptops, navigation systems, and smart televisions, include a display device for displaying the images. The display device generates images and provides the generated images to users via a display screen.

[0003] The display device includes a plurality of pixels for generating an image and a plurality of lines connected to the pixels, and the pixels are driven by receiving driving signals through the lines.

[0004] Recently, with the development of various types of display devices, there is a demand for the development of a technology that can ensure uniform visibility across the entire display surface of the display device and prevent defects such as excessively bright or dark images. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device that can display high quality images by preventing a display defect in which a part of the display surface of the display device, particularly a part of the non-display area adjacent to the tip of the display area, appears dark. [Means for solving the problem]

[0006] A display device according to an embodiment of the present invention includes a base layer divided into a display area and a non-display area surrounding at least a portion of the display area, a circuit element layer disposed on the base layer and including a driver overlapping the non-display area, and a display element layer disposed on the circuit element layer. The display element layer includes a pixel definition film disposed on the circuit element layer and a light emitting element overlapping the display area and including a light emitting layer. The pixel definition film includes a light emitting opening overlapping the display area and in which at least the light emitting layer is disposed, a driver opening overlapping the non-display area and overlapping the driver, and a dummy opening overlapping the non-display area and disposed between the light emitting opening and the driver opening. The dummy opening has substantially the same planar shape as the light emitting opening or the driver opening.

[0007] Each of the light emitting opening, the driving opening, and the dummy opening may include an inclined surface having an acute angle with respect to the top surface of the circuit element layer.

[0008] The light-emitting element may further include an anode disposed on the circuit element layer and a cathode facing the anode, and the light-emitting layer may be disposed between the anode and the cathode.

[0009] The cathode may be disposed on an inclined surface.

[0010] The circuit element layer may further include a plurality of insulating layers disposed on the base layer, and the anode may be disposed directly on the uppermost layer of the plurality of insulating layers.

[0011] The cathode may include a dummy portion disposed in the dummy opening, and the dummy portion may be disposed directly on the uppermost layer of the plurality of insulating layers.

[0012] The display element layer may further include a dummy electrode disposed on the circuit element layer, the cathode may include a dummy portion disposed in the dummy opening, and the dummy portion may be in contact with the dummy electrode.

[0013] The cathode may include a drive portion disposed within the drive opening, the display element layer may further include a voltage line disposed on the circuit element layer, and the drive portion may contact the voltage line.

[0014] The driven openings and the dummy openings may each have a circular, elliptical, rectangular, or chamfered rectangular shape in plan view.

[0015] The minimum spacing between the dummy opening and the light emitting opening may be smaller than or equal to the minimum spacing between the drive opening and the dummy opening.

[0016] The light emitting opening may include a first light emitting opening, a second light emitting opening spaced apart from the first light emitting opening, and a third light emitting opening spaced apart from the first light emitting opening and the second light emitting opening, and the dummy opening may have substantially the same planar shape as at least one of the first to third light emitting openings.

[0017] The display area may include a first side extending in a first direction, a second side adjacent to one end of the first side and extending in a second direction intersecting the first direction, and a first rounded corner connecting the one end of the first side to one end of the second side adjacent to the one end of the first side.

[0018] The dummy opening may be provided adjacent to at least one of the first side, the second side, and the first rounded corner.

[0019] The display device according to an embodiment of the present invention may further include a window disposed on the display element layer. The window may include a base member and a light-blocking pattern disposed under the base member and overlapping the non-display area. The driving openings and the dummy openings may be provided adjacent to the display area relative to the light-blocking pattern in a plan view.

[0020] The dummy region in which the dummy openings are provided may extend in a direction intersecting the spacing direction of the light emitting openings and the driving openings.

[0021] The width of the dummy region where the dummy opening is provided may be 40 μm or more and 80 μm or less.

[0022] The dummy opening may include a first dummy opening adjacent to the drive opening, and a second dummy opening provided between the first dummy opening and the light emitting opening on a plane.

[0023] The circuit element layer may further include at least one transistor electrically connected to the light emitting element.

[0024] A display device according to an embodiment of the present invention includes a base layer divided into a display area and a non-display area surrounding at least a portion of the display area, a circuit element layer disposed on the base layer and including a driver overlapping the non-display area, and a display element layer disposed on the circuit element layer. The display element layer includes a pixel defining layer disposed on the circuit element layer and a light emitting element overlapping the display area. The pixel defining layer includes a light emitting opening overlapping the display area, a driver opening overlapping the non-display area and overlapping the driver, and a dummy opening overlapping the non-display area and disposed between the light emitting opening and the driver opening. Each of the light emitting opening, the driver opening, and the dummy opening includes an inclined surface having an acute angle with respect to an upper surface of the circuit element layer.

[0025] The light-emitting element may include an anode disposed on the circuit element layer, a cathode facing the anode, and a light-emitting layer disposed between the anode and the cathode. The cathode may be disposed on an inclined surface.

[0026] According to an embodiment of the present invention, a display device includes a base layer divided into a display area and a non-display area surrounding at least a portion of the display area, a circuit element layer disposed on the base layer and including a driver overlapping the non-display area, and a display element layer disposed on the circuit element layer. The display element layer includes a pixel defining layer disposed on the circuit element layer and a light emitting element overlapping the display area. The pixel defining layer includes a light emitting opening overlapping the display area, a driver opening overlapping the non-display area and overlapping the driver, and a dummy opening disposed between the light emitting opening and the driver opening and not overlapping the driver. [Effects of the Invention]

[0027] According to an embodiment of the present invention, a dummy opening is provided overlapping a portion of a non-display area adjacent to a display area, so that the portion of the non-display area may have similar reflective properties to the display area and an area where an opening is formed to receive a data voltage, thereby preventing a display defect in which the portion of the non-display area adjacent to the display area appears dark, and improving display quality with the display layer. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a perspective view of a display device according to an embodiment of the present invention; [Figure 2] 1 is a cross-sectional view of a display device according to an embodiment of the present invention. [Figure 3] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention. [Figure 4] 1 is a block diagram of a display device according to an embodiment of the present invention; [Figure 5] FIG. 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. [Figure 6] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention. [Figure 7] 1 is a plan view of a display panel according to an embodiment of the present invention; [Figure 8] FIG. 2 is an enlarged plan view of a display area according to an embodiment of the present invention. [Figure 9] 1 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention. [Figure 10] 1 is an enlarged plan view of a partial configuration of a display panel according to an embodiment of the present invention. [Figure 11] 1 is an enlarged plan view of a partial configuration of a display panel according to an embodiment of the present invention. [Figure 12] 1 is an enlarged plan view of a partial configuration of a display panel according to an embodiment of the present invention. [Figure 13] 1 is an enlarged plan view of a partial configuration of a display panel according to an embodiment of the present invention. [Figure 14a] 1 is a cross-sectional view of a partial configuration of a display panel according to an embodiment of the present invention. [Figure 14b] 1 is a cross-sectional view of a partial configuration of a display panel according to an embodiment of the present invention. [Figure 15] 1 is a block diagram of an electronic device according to an embodiment of the present invention. [Figure 16] 1 is a schematic diagram of an electronic device according to various embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0029] As used herein, when a component (or region, layer, portion, etc.) is referred to as being "on" or "coupled" to another component, it means that it may be directly positioned, coupled, or connected to the other component, or that a third component may be disposed therebetween.

[0030] The same reference numerals refer to the same components, and in the drawings, thickness, proportions, and dimensions of the components are exaggerated for the purpose of effectively explaining the technical contents.

[0031] "And / or" includes all combinations of one or more of the associated constructs.

[0032] Terms such as "first" and "second" are used to describe various components, but the components are not limited to these terms. These terms are used only to distinguish one component from another. For example, a first component may be designated as a "second component" without departing from the scope of the present invention, and similarly, a second component may be designated as a "first component." A singular expression includes a plural expression unless the context clearly dictates otherwise.

[0033] Furthermore, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0034] It should be understood that the terms "comprise" or "have" and the like specify the presence of any feature, numeral, step, operation, component, part, or combination thereof set forth above in the specification, but do not preclude the possible presence or addition of one or more other features, numerals, steps, operations, components, parts, or combinations thereof.

[0035] As used herein, "directly disposed" can mean that there is no additional layer, film, region, plate, etc. between one layer, film, region, plate, etc. and another. For example, "directly disposed" can mean that two layers or two members are disposed without using an additional member such as an adhesive member between them.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted to have a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0037] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0038] FIG. 1 is a perspective view of a display device according to one embodiment of the present invention.

[0039] 1, a display device DD according to an embodiment of the present invention may have long sides extending parallel to a first direction DR1 and short sides extending parallel to a second direction DR2 intersecting the first direction DR1. Corners of the display device DD connecting the long sides and the short sides may be curved. Corners of the display device DD having a curved shape may be defined as rounded corners. The shape of such a display device DD may be defined as a rounded rectangle.

[0040] Hereinafter, a direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In addition, in this specification, the meaning of when viewed from a plane is defined as a state viewed from the third direction DR3.

[0041] The front surface of the display device DD may be defined as a display surface DS, which may have a plane defined by a first direction DR1 and a second direction DR2. An image IM generated by the display device DD may be presented to a user via the display surface DS.

[0042] The display surface DS includes a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image, while the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and define a frame for the display device DD that is printed in a predetermined color.

[0043] The display area DA may have a rectangular shape with rounded corners depending on the shape of the display device DD. For example, the display area DA may include rectangular sides extending in a first direction DR1 and a second direction DR2, and rounded corners connecting the sides. The four sides extending in the first direction DR1 may be defined as long sides, and the four sides extending in the second direction DR2 may be defined as short sides.

[0044] The display device DD can sense inputs applied from outside the display device DD. For example, the display device DD can sense a first input by a touch pen PEN and a second input by a touch TC. The touch pen PEN can be defined as an input device.

[0045] The touch pen PEN may be an active pen that outputs a signal. The second input by the touch TC may include various forms of external input such as a part of the user's body, light, heat, or pressure.

[0046] The display device DD and the touch pen PEN can communicate bidirectionally. The display device DD can provide an upward signal to the touch pen PEN. For example, the upward signal can include, but is not limited to, information such as panel information and protocol version.

[0047] The touch pen PEN may provide a downward signal to the display device DD. The downward signal may include a synchronization signal or status information of the touch pen PEN. For example, the downward signal may include, but is not limited to, coordinate information of the touch pen PEN, battery information of the touch pen PEN, gradient information of the touch pen PEN, and / or various information stored in the touch pen PEN.

[0048] The display device DD may be used in large electronic devices such as televisions, monitors, or external billboards. The display device DD may also be used in small to medium-sized devices such as personal computers, laptops, personal digital assistants, car navigation systems, game consoles, smartphones, tablets, or cameras. However, these are merely exemplary examples, and the display device DD may also be used in other electronic devices without departing from the concept of the present invention.

[0049] Figure 2 is a cross-sectional view of a display device according to an embodiment of the present invention. Figure 2 is a view exemplarily showing a cross-section of the display device shown in Figure 1. Exemplarily, Figure 2 shows a cross-section of the display device DD as viewed from a second direction DR2.

[0050] Referring to FIG. 2, the display device DD may include a display panel DP, an input sensing unit ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and first and second adhesive layers AL1 and AL2.

[0051] According to an embodiment of the present invention, the display panel DP may be an emissive display panel. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of an inorganic light-emitting display panel may include quantum dots, quantum rods, etc. Hereinafter, the display panel DP will be referred to as an organic light-emitting display panel.

[0052] The input sensing unit ISP may be disposed on the display panel DP. The input sensing unit ISP may include a plurality of sensing units (not shown) for sensing external inputs using a capacitive method. The input sensing unit ISP may be directly manufactured on the display panel DP when manufacturing the display device DD. However, the input sensing unit ISP is not limited thereto, and may be manufactured as a separate panel from the display panel DP and attached to the display panel DP by an adhesive layer.

[0053] The anti-reflection layer RPL may be disposed on the input sensing unit ISP. The anti-reflection layer RPL may be directly manufactured on the input sensing unit ISP when manufacturing the display device DD. However, the anti-reflection layer RPL is not limited thereto. The anti-reflection layer RPL may be manufactured as a separate display panel and attached to the input sensing unit ISP by an adhesive layer.

[0054] The anti-reflection layer RPL may be defined as an external light anti-reflection film. The anti-reflection layer RPL may reduce the reflectance of external light incident from above the display device DD toward the display panel DP. The anti-reflection layer RPL may prevent the external light from being perceived by the user.

[0055] If external light traveling toward the display panel DP is reflected by the display panel DP and provided to an external user, the user may view the external light as if it were a mirror. To prevent this phenomenon, for example, the anti-reflection layer RPL may include a plurality of color filters that display the same colors as the pixels of the display panel DP.

[0056] The color filter may filter external light to the same color as the pixel, so that the external light may not be visible to the user. However, the anti-reflection layer RPL may include a retarder and / or a polarizer to reduce the reflectance of external light.

[0057] The window WIN may be disposed on the anti-reflection layer RPL, and may protect the display panel DP, the input sensing unit ISP, and the anti-reflection layer RPL from external scratches and impacts.

[0058] As shown in FIG. 2, the window WIN may include a base member WM-BS and a light-shielding pattern WBM for defining a bezel area BZA (see FIG. 9). The light-shielding pattern WBM is a colored organic film and may be formed on one surface of the base member WM-BS by, for example, a coating method. The light-shielding pattern WBM may be disposed below the base member WM-BS.

[0059] The panel protection film PPF may be disposed below the display panel DP. The panel protection film PPF may protect the lower part of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate (PET).

[0060] The first adhesive layer AL1 is disposed between the display panel DP and the panel protective film PPF, and the first adhesive layer AL1 can bond the display panel DP and the panel protective film PPF to each other. The second adhesive layer AL2 is disposed between the window WIN and the anti-reflection layer RPL, and the second adhesive layer AL2 can bond the window WIN and the anti-reflection layer RPL to each other.

[0061] Figure 3 is a cross-sectional view of a display panel according to an embodiment of the present invention. Figure 3 is a view exemplarily showing a cross-section of the display panel shown in Figure 2. Exemplarily, Figure 3 shows a cross-section of the display panel DP as viewed from a second direction DR2.

[0062] Referring to Figure 3, the display panel DP may include a base layer SUB, a circuit element layer DP-CL arranged on the base layer SUB, a display element layer DP-OLED arranged on the circuit element layer DP-CL, and a thin-film encapsulation layer TFE arranged on the display element layer DP-OLED.

[0063] The base layer SUB may include a display area DA and a non-display area NDA surrounding the display area DA. The base layer SUB may be divided into the display area DA and the non-display area NDA surrounding the display area DA. The base layer SUB may include glass or a flexible plastic material such as polyimide (PI). The display element layer DP-OLED may be disposed on the display area DA.

[0064] A plurality of pixels may be disposed on the circuit element layer DP-CL and the display element layer DP-OLED, and each pixel may include a transistor disposed on the circuit element layer DP-CL and a light-emitting element disposed on the display element layer DP-OLED and connected to the transistor.

[0065] The thin film encapsulation layer TFE may be disposed on the circuit element layer DP-CL so as to cover the display element layer DP-OLED, and protects the pixels from moisture, oxygen, and external foreign substances.

[0066] 4 is a block diagram of a display device according to an embodiment of the present invention, showing the blocks of the display device shown in FIG.

[0067] Referring to FIG. 4, the display device DD may include a display panel DP, a timing controller (TC), a scan driver SDV, a data driver DDV, an emission driver EDV, and a voltage generator VG.

[0068] The display panel DP may include a plurality of scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm, a plurality of light emitting lines EL1 to ELm, a plurality of data lines DL1 to DLn, and a plurality of pixels PX, where m and n are natural numbers.

[0069] The pixels PX may be electrically connected to the scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm, the light emitting lines EL1 to ELm, and the data lines DL1 to DLn, respectively. Each pixel PX may be electrically connected to four corresponding scan lines, one corresponding data line, and one corresponding light emitting line.

[0070] The scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm may include a plurality of initialization scan lines GIL1 to GILm, a plurality of compensation scan lines GCL1 to GCLm, a plurality of write scan lines GWL1 to GWLm, and a plurality of bias scan lines GBL1 to GBLm.

[0071] Each pixel PX may be connected to a corresponding one of the initialization scan lines GIL1 to GILm, a corresponding one of the compensation scan lines GCL1 to GCLm, a corresponding one of the write scan lines GWL1 to GWLm, and a corresponding one of the bias scan lines GBL1 to GBLm.

[0072] The scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm are connected to the scan driver SDV, extended in a first direction DR1, and arranged in a second direction DR2. The light emitting lines EL1 to ELm are connected to the light emitting driver EDV, extended in the first direction DR1, and arranged in the second direction DR2. The data lines DL1 to DLn are connected to the data driver DDV, extended in the second direction DR2, and arranged in the first direction DR1.

[0073] The scan driver SDV, the emission driver EDV, and the data driver DDV may be substantially arranged on the display panel DP, and such a configuration is illustrated in FIG. 7 below.

[0074] The timing controller TC receives the video signal RGB and the control signal CTRL. The timing controller TC converts the data format of the video signal RGB to conform to the interface specification with the data driver DDV and generates a video data signal DAS. The timing controller TC outputs a scan control signal SCS, a data control signal DCS, and a light emission control signal ECS in response to the control signal CTRL.

[0075] The voltage generator VG generates voltages necessary for the operation of the display panel DP. The voltage generator VG generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage VAINT. The first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT, and the second initialization voltage VAINT can be applied to the pixels PX.

[0076] The scan driver SDV may receive a scan control signal SCS from the timing controller TC. In response to the scan control signal SCS, the scan driver SDV may output scan signals to the scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm. The scan signals may be applied to the pixels PX via the scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm.

[0077] The data driver DDV may receive a data control signal DCS and a video data signal DAS from the timing controller TC. The data driver DDV may convert the video data signal DAS into a data signal and output the converted data signal. The data signal may be defined as an analog voltage corresponding to the gray level of the video data signal DAS. The data signal may be applied to the pixels PX via the data lines DL1 to DLn.

[0078] The light emitting driver EDV may receive a light emitting control signal ECS from the timing controller TC. In response to the light emitting control signal ECS, the light emitting driver EDV may output a light emitting signal to the light emitting lines EL1 to ELm. The light emitting signal may be applied to the pixels PX via the light emitting lines EL1 to ELm.

[0079] The pixel PX can be provided with a data voltage in response to a scan signal, and can emit light of a brightness corresponding to the data voltage in response to a light emitting signal to display an image.

[0080] 5 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention, which illustrates one of the pixels shown in FIG.

[0081] 5 exemplarily shows a pixel PXij connected to the j-th data line DLj, the i-th scan lines GWLi, GCLi, GILi, and GBLi, and the i-th light-emitting line ELi, where i and j are natural numbers.

[0082] 5, the pixel PXij may include a pixel circuit PC and a light-emitting element OLEDC coupled to the pixel circuit PC. The pixel circuit light-emitting element PC may drive the light-emitting element OLED.

[0083] The pixel circuit PC may include a plurality of transistors T1 to T8 and a capacitor CST. The transistors T1 to T8 and the capacitor CST may control the amount of current flowing to the light emitting element OLED. The light emitting element OLED may generate light having a predetermined brightness according to the amount of current provided.

[0084] The i-th write scan line GWLi may receive the i-th write scan signal GWi, the i-th compensation scan line CGLi may receive the i-th compensation scan signal GCi, the i-th initialization scan line GILi may receive the i-th initialization scan signal GIi, the i-th bias scan line CBLi may receive the i-th bias scan signal GBi, and the i-th light-emitting line ELi may receive the i-th light-emitting signal EMi.

[0085] The pixel PXij may be connected to the jth data line DLj, the ith write scanning signal GWi, the ith compensation scanning signal GCi, the ith initialization scanning signal GIi, the ith bias scanning signal GBi, the ith light emitting signal EMi, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL, and the first and second power supply lines PL1 and PL2.

[0086] The first initialization line VIL1 may receive the first initialization voltage VINT, the second initialization line VIL2 may receive the second initialization voltage VAINT, the bias line VBL may receive the bias voltage VBIAS, the first power supply line PL1 may receive the first driving voltage ELVDD, and the second power supply line PL2 may receive the second driving voltage ELVSS.

[0087] Each of the transistors T1 to T8 may include a source electrode, a drain electrode, and a gate electrode. Hereinafter, in FIG. 5, for convenience, one of the source electrode and the drain electrode is defined as a first electrode, and the other is defined as a second electrode. Furthermore, the gate electrode is defined as a control electrode.

[0088] The transistors T1 to T8 may include first to eighth transistors T1 to T8. The first, second, fifth, and eighth transistors T1, T2, T5 to T8 may be PMOS transistors. The third and fourth transistors T3 and T4 may be NMOS transistors.

[0089] The first transistor T1 may be defined as a driving transistor, the second transistor T2 may be defined as a switching transistor, the third transistor T3 may be defined as a compensation transistor, the fourth transistor T4 and the seventh transistor T7 may be defined as initialization transistors, the fifth transistor T5 and the sixth transistor T6 may be defined as light-emitting control transistors, and the eighth transistor T8 may be defined as a bias transistor.

[0090] The light-emitting element OLED may be defined as an organic light-emitting element. The light-emitting element OLED may include an anode AE ​​and a cathode CE. The anode AE ​​may receive a first driving voltage ELVDD via the sixth, first, and fifth transistors T6, T1, and T5. The first driving voltage ELVDD may be applied to the pixel circuit PC via a first power line PL1.

[0091] The cathode CE may receive a second driving voltage ELVSS having a lower level than the first driving voltage ELVDD, and the second driving voltage ELVSS may be applied to the pixel circuit PC via a second power line PL2.

[0092] The first transistor T1 may be disposed between the fifth transistor T5 and the sixth transistor T6 and may be connected to the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may be connected to the first power line PL1 via the fifth transistor T5 and to the anode AE ​​via the sixth transistor T6.

[0093] The first transistor T1 may include a first electrode connected to the first power line PL1 via the fifth transistor T5, a second electrode connected to the anode AE ​​via the sixth transistor T6, and a control electrode connected to the first node N1.

[0094] A first electrode of the first transistor T1 may be connected to the fifth transistor T5, and a second electrode of the first transistor T1 may be connected to the sixth transistor T6. The first transistor T1 may control the amount of current flowing through the light emitting element OLED according to a voltage of a first node N1 applied to a control electrode of the first transistor T1.

[0095] The second transistor T2 may be disposed between the first transistor T1 and the j-th data line DLj and may be coupled to the first transistor T1 and the j-th data line DLj. The second transistor T2 may include a first electrode coupled to the j-th data line DLj, a second electrode coupled to the first electrode of the first transistor T1, and a control electrode coupled to the ith write scan line GWLi.

[0096] The second transistor T2 may be turned on by the i-th write scan signal GWi applied via the i-th write scan line GWLi to electrically connect the j-th data line DLj to the first electrode of the first transistor T1, and may perform a switching operation to provide the data voltage VD (corresponding to the data signal described above) applied via the j-th data line DLj to the first electrode of the first transistor T1.

[0097] The third transistor T3 may be connected to the second electrode of the first transistor T1 and the first node N1, and may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the i-th compensation scan line GCLi.

[0098] The third transistor T3 may be turned on by the i-th compensation scan signal GCi applied through the i-th compensation scan line GCLi to electrically connect the second electrode of the first transistor T1 to the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 and the third transistor T3 may be connected in the form of a diode.

[0099] The fourth transistor T4 may be coupled to the first node N1. The fourth transistor T4 may include a first electrode coupled to the first node N1, a second electrode coupled to the first initialization line VIL1, and a control electrode coupled to the i-th initialization scan line GILi. The fourth transistor T4 may be turned on by the i-th initialization scan signal GIi applied via the i-th initialization scan line GILi to provide the first initialization voltage VINT applied via the first initialization line VIL1 to the first node N1.

[0100] The fifth transistor T5 may include a first electrode coupled to the first power line PL1, a second electrode coupled to the first electrode of the first transistor T1, and a control electrode coupled to the i-th light-emitting line ELi.

[0101] The sixth transistor T6 may include a first electrode coupled to the second electrode of the first transistor T1, a second electrode coupled to the anode AE, and a control electrode coupled to the i-th light-emitting line ELi.

[0102] The fifth transistor T5 and the sixth transistor T6 may be turned on by the i-th light-emitting signal EMi applied through the i-th light-emitting line ELi. The turned-on fifth transistor T5 and the sixth transistor T6 may provide the first driving voltage ELVDD to the light-emitting element OLED, causing a driving current to flow through the light-emitting element OLED. As a result, the light-emitting element OLED may emit light.

[0103] The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line GBLi. The seventh transistor T7 may be turned on in response to the i-th bias scan signal GBi applied via the i-th bias scan line GBLi to provide the second initialization voltage VAINT received via the second initialization line VIL2 to the anode AE ​​of the light emitting element OLED.

[0104] In the embodiment of the present invention, the second initialization voltage VAINT may have a different level from the first initialization voltage VINT, but is not limited thereto, and may have the same level as the first initialization voltage VINT.

[0105] The seventh transistor T7 may improve the black display capability of the pixel PXij. When the seventh transistor T7 is turned on, a parasitic capacitor (not shown) of the light emitting element OLED may be discharged. Therefore, when black brightness is realized, the light emitting element OLED does not emit light due to the leakage current of the first transistor T1, thereby improving the black display capability.

[0106] The capacitor CST may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 may be determined by the voltage stored in the capacitor CST.

[0107] The eighth transistor T8 may include a first electrode coupled to the bias line VBL, a second electrode coupled to the first electrode of the first transistor T1, and a control electrode coupled to the i-th bias scan line GBLi.

[0108] The eighth transistor T8 may be turned on by the i-th bias scan signal GBi to provide the bias voltage VBIAS applied via the bias line VBL to the first electrode of the first transistor T1.

[0109] 6 is a cross-sectional view of a display panel according to an embodiment of the present invention, which exemplarily illustrates cross sections of a light emitting element, a first transistor, a fourth transistor, and a sixth transistor of the pixel shown in FIG.

[0110] Referring to Figure 6, the light-emitting element OLED may include an anode AE, a cathode CE, a hole control layer HCL, an electron control layer ECL, and an emitting layer EML. The anode AE ​​may correspond to the anode AE ​​shown in Figure 5, and the cathode CE may correspond to the cathode CE shown in Figure 5. The cathode CE may be disposed on the anode AE, and the hole control layer HCL, the electron control layer ECL, and the emitting layer EML may be disposed between the anode AE ​​and the cathode CE. Meanwhile, the anode AE ​​and the cathode CE may each include a metal material. The anode AE ​​and the cathode CE may each include a reflective metal.

[0111] The first, fourth, and sixth transistors T1, T4, and T6 and the light-emitting element OLED may be disposed on the base layer SUB. The display area DA may include a light-emitting area LEA corresponding to the pixel PXij and a non-light-emitting area NLEA adjacent to the light-emitting area LEA. The light-emitting element OLED may be disposed in the light-emitting area LEA.

[0112] A lower metal layer BML may be disposed on the base layer SUB. The lower metal layer BML may overlap the first transistor T1. Although not shown, a constant voltage may be applied to the lower metal layer BML. When the constant voltage is applied to the lower metal layer BML, the threshold voltage value of the first transistor T1 disposed on the lower metal layer BML remains unchanged.

[0113] The lower metal layer BML may block light incident on the first transistor T1 from below the lower metal layer BML. The lower metal layer BML may include a reflective metal. Meanwhile, in an embodiment of the display device, the lower metal layer BML may be omitted.

[0114] A buffer layer BFL may be disposed on the base layer SUB, and the buffer layer BFL may be an inorganic layer. The buffer layer BFL may cover the lower metal layer BML. The semiconductor layers S1, A1, and D1 of the first transistor T1 and the semiconductor layers S6, A6, and D6 of the sixth transistor T6 may be disposed on the buffer layer BFL. The semiconductor layers S1, A1, D1, S6, A6, and D6 may include polysilicon. However, the semiconductor layers S1, A1, D1, S6, A6, and D6 may include amorphous silicon.

[0115] The semiconductor layers S1, A1, D1, S6, A6, and D6 may be doped with an N-type dopant or a P-type dopant. The semiconductor layers S1, A1, D1, S6, A6, and D6 may include a highly doped region and a lightly doped region. The highly doped region has a higher conductivity than the lightly doped region and may substantially serve as the source and drain electrodes of the first and sixth transistors T1 and T6. The lightly doped region may substantially correspond to the active regions (or channels) of the first and sixth transistors T1 and T6.

[0116] The first source region S1, the first channel region A1, and the first drain region D1 of the first transistor T1 may be composed of semiconductor layers S1, A1, and D1. The sixth source region S6, the sixth channel region A6, and the sixth drain region D6 of the sixth transistor T6 may be composed of semiconductor layers S6, A6, and D6. The first channel region A1 may be disposed between the first source region S1 and the first drain region D1. The sixth channel region A6 may be disposed between the sixth source region S6 and the sixth drain region D6.

[0117] A first insulating layer INS1 may be disposed on the buffer layer BFL to cover the semiconductor layers S1, A1, D1, S6, A6, and D6. A first gate electrode G1 (or control electrode) of the first transistor T1 and a sixth gate electrode G6 (or control electrode) of the sixth transistor T6 may be disposed on the first insulating layer INS1. When viewed from above, the first gate electrode G1 may overlap the first channel region A1, and the sixth gate electrode G6 may overlap the sixth channel region A6.

[0118] Although not shown, the structures of the source region, channel region, drain region, and gate electrode of each of the second, fifth, and seventh transistors T2, T5, and T7 may be substantially the same as those of the first and sixth transistors T1, T6.

[0119] A second insulating layer INS2 may be disposed on the first insulating layer INS1 to cover the first and sixth gate electrodes G1 and G6. A dummy electrode DME may be disposed on the second insulating layer INS2. The dummy electrode DME may be disposed on the first gate electrode G1 and may overlap the first gate electrode G1 when viewed from above. The dummy electrode DME may form the above-mentioned capacitor CST together with the first gate electrode G1.

[0120] A third insulating layer INS3 may be disposed on the second insulating layer INS2 to cover the dummy electrode DME. Semiconductor layers S4, A4, and D4 of the fourth transistor T4 may be disposed on the third insulating layer INS3. The semiconductor layers S4, A4, and D4 may include an oxide semiconductor made of a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

[0121] The semiconductor layers S4, A4, and D4 may include multiple regions that are distinguished by whether the metal oxide is reduced or not. The regions where the metal oxide is reduced (hereinafter referred to as reduced regions) may have higher conductivity than regions where the metal oxide is not reduced (hereinafter referred to as non-reduced regions). The reduced regions may essentially function as the source or drain electrodes of the fourth transistor T4. The non-reduced regions essentially correspond to the active (or channel) of the fourth transistor T4.

[0122] The fourth source region S4, the fourth channel region A4, and the fourth drain region D4 of the fourth transistor T4 may be formed of semiconductor layers S4, A4, and D4, and the fourth channel region A4 may be disposed between the fourth source region S4 and the fourth drain region D4.

[0123] A fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to cover the semiconductor layers S4, A4, and D4. A fourth gate electrode G4 of the fourth transistor T4 may be disposed on the fourth insulating layer INS4. When viewed from above, the fourth gate electrode G4 may overlap the fourth channel region A4.

[0124] A fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 to cover the fourth gate electrode G4. Although not shown, the source region, channel region, drain region, and gate electrode of the third transistor T3 may have substantially the same structures as those of the fourth transistor T4.

[0125] The buffer layer BFL and the first to fifth insulating layers INS1 to INS5 may include inorganic layers. Exemplarily, the buffer layer BFL, the first insulating layer INS1, and the fourth insulating layer INS4 may include silicon oxide layers, and the second insulating layer INS2 may include a silicon nitride layer.

[0126] The third and fifth insulating layers INS3 and INS5 may comprise multiple inorganic insulating layers that are made of different materials and stacked on top of each other. For example, the third insulating layer INS3 may comprise a silicon nitride layer and a silicon oxide layer that are stacked sequentially, and the fifth insulating layer INS5 may comprise a silicon oxide layer and a silicon nitride layer that are stacked sequentially. The thicknesses of the third and fifth insulating layers INS3 and INS5 may be greater than the thicknesses of the buffer layer BFL and the first, second, and fourth insulating layers INS1, INS2, and INS4, respectively.

[0127] A connecting electrode CNE may be disposed between the sixth transistor T6 and the light emitting element OLED. The connecting electrode CNE may electrically connect the sixth transistor T6 and the light emitting element OLED. The connecting electrode CNE may include a first connecting electrode CNE1 and a second connecting electrode CNE2 disposed on the first connecting electrode CNE1.

[0128] The first connecting electrode CNE1 may be disposed on the fifth insulating layer INS5 and may be connected to the sixth drain region D6 through a first contact hole CH1 defined in the first to fifth insulating layers INS1 to INS5. A sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 to cover the first connecting electrode CNE1.

[0129] The second connecting electrode CNE1 may be disposed on the sixth insulating layer INS6. The second electrode CNE2 may be connected to the first connecting electrode CNE1 through a second contact hole CH2 defined in the sixth insulating layer INS6.

[0130] A seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 to cover the second connecting electrode CNE2. The sixth and seventh insulating layers INS6 and INS7 may include an inorganic layer or an organic layer.

[0131] An anode AE ​​may be disposed on the seventh insulating layer INS7 and may be electrically connected to the second connecting electrode CNE2 through a third contact hole CH3 defined in the seventh insulating layer INS7.

[0132] A pixel defining layer PDL exposing a predetermined portion of the anode AE ​​may be disposed on the anode AE ​​and the seventh insulating layer INS7. The pixel defining layer PDL may include a light emitting opening PX_OP exposing a predetermined portion of the anode AE. Meanwhile, the pixel defining layer PDL may be provided with an additional opening in the non-display area NDA (see FIG. 3) in addition to the light emitting opening PX_OP disposed in the display area DA. This will be described in detail later.

[0133] The hole control layer HCL may be disposed on the anode AE ​​and the pixel defining layer PDL. The hole control layer may be disposed in common in the light emitting area LEA and the non-light emitting area NLEA. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0134] The emitting layer EML may be disposed on the hole controlling layer HCL. The emitting layer EML may be disposed in a region corresponding to the light emitting opening PX_OP. The emitting layer EML may include an organic material and / or an inorganic material. The emitting layer EML may generate any one of red, green, and blue light.

[0135] The electron control layer ECL may be disposed on the light-emitting layer EML and the hole control layer HCL. The electron control layer ECL may be disposed in common in the light-emitting area LEA and the non-light-emitting area NLEA. The electron control layer ECL may include an electron transport layer and an electron injection layer.

[0136] The cathode CE may be disposed on the electronic control layer ECL. The cathode CE may be disposed in common with the pixels PX. That is, the cathode CE may be disposed in common with the emitting layer EML of the pixels PX.

[0137] The layers from the buffer layer BFL to the seventh insulating layer INS7 may be defined as a circuit element layer DP-CL, and the layer on which the light-emitting element OLED is disposed may be defined as a display element layer DP_OLED.

[0138] A thin-film encapsulation layer TFE may be disposed on the light-emitting element OLED. The thin-film encapsulation layer TFE may include an inorganic layer, an organic layer, and another inorganic layer that are stacked in sequence. The inorganic layer may include an inorganic material and may protect the pixel PX from moisture / oxygen. The organic layer may include an organic material and may protect the pixel PX from foreign matter such as dust particles.

[0139] A first driving voltage ELVDD may be applied to the anode AE, and a second driving voltage ELVSS may be applied to the cathode CE. Holes and electrons injected into the emitting layer EML combine to form excitons, and the excitons transition to a bottom state, causing the light emitting device OLED to emit light. The light emitting device OLED emits light, and an image may be displayed.

[0140] 7 is a plan view of a display panel according to an embodiment of the present invention, and is a plan view of the display panel shown in FIG.

[0141] FIG. 4 is a diagram mainly showing functional blocks of the display device DD, and FIG. 7 is a diagram mainly showing the planar structure of the display panel DP.

[0142] 7, the display device DD may include a display panel DP, a scan driver SDV, a plurality of data drivers DDV, a light emitting driver EDV, and a plurality of pads PD. The display panel DP may have a rectangular shape with rounded corners corresponding to the shape of the display device DD.

[0143] The frame of the display panel DP may have long sides extending parallel to the first direction DR1 and short sides extending parallel to the second direction DR2. The long and short sides of the display panel DP may correspond to the sides of a rectangle. The frame of the display panel DP may include rounded corners connecting the long and short sides of the display panel DP. Each of the rounded corners may connect adjacent long sides and individual pieces.

[0144] The display panel DP may include a display area DA and a non-display area NDA that is disposed around and surrounds the display area DA. The display area DA may have a rectangular shape with rounded corners corresponding to the shape of the display panel DP.

[0145] Because the display area DA has a rounded-corner rectangular shape, it may include first to fourth sides SI1 to SI4 and first to third rounded corners CR1 to CR3. The first to fourth sides SI1 to SI4 may define the four sides of the rectangle. The first to third rounded corners CR1 to CR3 may define the four rounded corners of the rectangle.

[0146] The first side SI1 and the fourth side SI4 may extend parallel to the first direction DR1 and face the second direction DR2. The second side SI2 and the third side SI3 may extend parallel to the second direction DR2 and face the first direction DR1. The first side SI1 and the fourth side SI4 may extend longer than the second side SI2 and the third side SI3. The first side SI1 and the fourth side SI4 may be defined as long sides, and the second side SI2 and the third side SI3 may be defined as short sides.

[0147] The second side SI2 and the third side SI3 may be adjacent to both ends of the first side SI1 and extend in the second direction DR2. The second side SI2 may be disposed adjacent to one end of the first side SI1 and extend in the second direction DR2. The third side SI3 may be disposed adjacent to the other end of the first side SI1 and extend in the second direction DR2. One end of the second side SI2 may be adjacent to one end of the first side SI1, and the other end of the third side SI3 may be adjacent to the other end of the first side SI1.

[0148] The fourth side SI4 may be adjacent to the other end of the second side SI2 and the other end of the third side SI3 and extend in the first direction DR1. One end of the fourth side SI4 may be adjacent to one end of the second side SI2, and the other end of the fourth side SI4 may be adjacent to the other end of the third side SI3.

[0149] One end and the other end of the first side SI1 may be defined as opposite ends of the first side SI1 in the first direction DR1. One end and the other end of the second side SI2 may be defined as opposite ends of the second side SI2 in the second direction DR2. One end and the other end of the third side SI3 may be defined as opposite ends of the third side SI3 in the second direction DR2. One end and the other end of the fourth side SI4 may be defined as opposite ends of the fourth side SI4 in the first direction DR1.

[0150] In the first direction DR1, the distance between the second side SI2 and the third side SI3 may be greater than the length of the first side SI1 and the length of the fourth side SI4. In the second direction DR2, the distance between the first side SI1 and the fourth side SI4 may be greater than the length of the second side SI2 and the length of the third side SI3.

[0151] When viewed from the second direction DR2, the first side SI1 and the fourth side SI4 may be disposed between the second side SI2 and the third side SI3. When viewed from the first direction DR1, the second side SI2 and the third side SI3 may be disposed between the first side SI1 and the fourth side SI4.

[0152] The first rounded corner CR1 may connect the first side SI1 and the second side SI2. For example, the first rounded corner CR1 may connect one end of the first side SI1 and one end of the second side SI2 that are adjacent to each other. The first rounded corner CR1 may have a curved shape that bulges toward the non-display area NDA.

[0153] The second rounded corner CF2 may connect the first side SI1 and the third side SI3. For example, the second rounded corner CR2 may connect the other end of the first side SI1 and one end of the third side SI3, which are adjacent to each other. The second rounded corner CR2 may have a curved shape that bulges toward the non-display area NDA.

[0154] Two third rounded corners CR3 may connect the other end of the fourth side SI4 to the other end of the second side SI2 and the other end of the third side SI3, respectively. One third rounded corner CR3 may connect the other end of the adjacent second side SI2 to one end of the fourth side SI4. Another third rounded corner CR3 may connect the other end of the adjacent third side SI3 to the other end of the fourth side SI4. The third rounded corners CR3 may have a curved shape that bulges toward the non-display area NDA.

[0155] The first rounded corner CR1 and the second rounded corner CR2 may be symmetrical to each other in the first direction DR1. The third rounded corner CR3 may be symmetrical to each other in the first direction DR1. The first and second rounded corners CR1 and CR2 and the third rounded corner CR3 may be symmetrical to each other in the second direction DR2.

[0156] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, and a plurality of light emitting lines EL1 to ELm. The pixels PX may be arranged in a display area DA. The pixels PX may be connected to the scan lines SL1 to SLm, the data lines DL1 to DLn, and the light emitting lines EL1 to ELm.

[0157] The scan lines SL1 to SLm may include the scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBL shown in Figure 4. For example, the i-th scan line among the scan lines SL1 to SLm may include the i-th write scan line GWLi, the i-th compensation scan line GCLi, the i-th initialization scan line GILi, and the i-th bias scan line GBLi. Therefore, the above-mentioned scan signals may be applied to the pixels PX via the scan lines SL1 to SLm.

[0158] The data lines DL1 to DLn and the light emitting lines EL1 to ELm may be the same as the data lines DL1 to DLn and the light emitting lines EL1 to ELm shown in FIG.

[0159] The scan driver SDV and the emission driver EDV may be disposed in adjacent non-display areas NDA on opposite sides of the display panel DP in the first direction DR1. The scan driver SDV may be adjacent to the second side SI2, the first rounded corner CR1, and the third rounded corner CR3 connected to the second side SI2. The emission driver EDV may be adjacent to the third side SI3, the second rounded corner CR2, and the third rounded corner CR3 connected to the third side SI3. In this specification, the scan driver SDV and the emission driver EDV may be referred to as "drivers."

[0160] A portion of the scan driver SDV adjacent to the first rounded corner CR1 and a portion of the scan driver SDV adjacent to the third rounded corner CR3 connected to the second side SI2 may have a curved shape. A portion of the light emitting driver EDV adjacent to the second rounded corner CR2 and a portion of the light emitting driver EDV adjacent to the third rounded corner CR3 connected to the third side SI3 may have a curved shape.

[0161] A plurality of data drivers DDV shown in FIG. 4 may be provided in the display panel DP as shown in FIG. 7. The data drivers DDV may be disposed in the non-display area NDA adjacent to one of both sides of the display panel DP that are opposite to each other in the second direction DR2. When viewed from above, the data drivers DDV may be adjacent to the bottom edge of the display panel DP. For example, the data drivers DDV may be adjacent to the first side SI1.

[0162] The scan lines SL1 to SLm extend in a first direction DR1 and may be connected to the pixels PX and the scan driver SDV. The data lines DL1 to DLn extend in a second direction DR2 and may be connected to the pixels PX and the data driver DDV. The light emitting lines EL1 to ELm extend in the first direction DR1 and may be connected to the pixels PX and the light emitting driver EDV.

[0163] The data drivers DDV may be spaced apart from each other in a first direction DR1. A predetermined number of data lines may be connected to each data driver DDV. Although two data drivers DDV are shown as an example, the number of data drivers DDV is not limited to this. For example, the number of data drivers DDV may increase as the left and right areas of the display panel DP increase.

[0164] The pads PD are disposed in the non-display area NDA adjacent to the lower end of the display panel DP and may be closer to the lower end of the display panel DP than the data driver DDV. The data driver DDV may be connected to the pads PD. The data lines DL1 to DLn may be connected to the data driver DDV, and the data driver DDV may be connected to the pads PD corresponding to the data lines DL1 to DLn.

[0165] Although not shown, the timing controller TC and voltage generator VG shown in FIG. 4 may be mounted on a printed circuit board and connected to the pads PD via the printed circuit board.

[0166] FIG. 8 is an enlarged plan view of a display area according to one embodiment of the present invention.

[0167] 8, the display area DA includes a plurality of light-emitting areas LEA1, LEA2, and LEA3, and may include a non-light-emitting area NLEA adjacent to the plurality of light-emitting areas LEA1, LEA2, and LEA3. The non-light-emitting area NLEA defines a boundary between the light-emitting areas LEA1, LEA2, and LEA3.

[0168] The light-emitting regions LEA1, LEA2, and LEA3 may be arranged in a one-to-one correspondence with the pixels PX in Fig. 7. Each pixel PX includes a light-emitting element, and the light-emitting regions LEA1, LEA2, and LEA3 may be areas from which light generated by the light-emitting element is emitted.

[0169] The light-emitting regions LEA1, LEA2, and LEA3 may include a first light-emitting region LEA1 (or first color light-emitting region) that generates a first color light, a second light-emitting region LEA2 (or second color light-emitting region) that generates a second color light, and a third light-emitting region LEA3 (or third color light-emitting region) that generates a third color light. In this embodiment, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. Meanwhile, the light-emitting elements OLED described above in FIG. 6 may be disposed in each of the light-emitting regions LEA1, LEA2, and LEA3. At least an emission layer EML may be disposed in each of the light-emitting regions LEA1, LEA2, and LEA3. Meanwhile, emission layers EML containing different materials may be disposed in each of the light-emitting regions LEA1, LEA2, and LEA3. That is, the light-emitting elements OLED corresponding to the first light-emitting region LEA1, the second light-emitting region LEA2, and the third light-emitting region LEA3 may include emission layers EML containing different materials.

[0170] The areas of the first light-emitting region LEA1, the second light-emitting region LEA2, and the third light-emitting region LEA3 may be different from each other, but are not necessarily limited to this. In this embodiment, the area of ​​the first light-emitting region LEA1 may be the smallest, and the area of ​​the third light-emitting region LEA3 may be the largest.

[0171] The first light-emitting region LEA1, the second light-emitting region LEA2, and the third light-emitting region LEA3 may define one unit light-emitting region UA. The unit light-emitting region UA ​​is a repeating arrangement unit of light-emitting regions arranged in the display area DA. In this embodiment, the unit light-emitting region UA ​​may include a first unit light-emitting region UA1 and a second unit light-emitting region UA2.

[0172] Referring to the first and second unit light-emitting regions UA1 and UA2, the first and second light-emitting regions LEA1 and LEA2 may be disposed on one side of the third light-emitting region LEA3 in the first direction (left side in FIG. 8). The second light-emitting region LEA2 of each of the first and second unit light-emitting regions UA1 and UA2 may be disposed on one side of the first light-emitting region LEA1 in the second direction (below in FIG. 8).

[0173] The positions of the third light-emitting region LEA3 relative to the first light-emitting region LEA1 and the second light-emitting region LEA2 may be different from each other in the second direction DR2. Regarding the first unit light-emitting region UA1, the position of the third light-emitting region LEA3 relative to the first light-emitting region LEA1 and the second light-emitting region LEA2 may be positioned lower relative to the first light-emitting region LEA1 and the second light-emitting region LEA2 in the second direction DR2. Regarding the second unit light-emitting region UA2, the position of the third light-emitting region LEA3 relative to the first light-emitting region LEA1 and the second light-emitting region LEA2 may be positioned higher relative to the first light-emitting region LEA1 and the second light-emitting region LEA2 in the second direction DR2. The first unit light-emitting region UA1 and the second unit light-emitting region UA2 may differ in the degree of shift of the third light-emitting region LEA3 relative to the first light-emitting region LEA1 and the second light-emitting region LEA2 in the second direction DR2. In this embodiment, the third light-emitting region LEA3 of the second unit light-emitting region UA2 may be shifted further relative to the third light-emitting region LEA3 of the first unit light-emitting region UA1. However, the present invention is not limited to this, and the first and second unit light-emitting regions UA1 and UA2 may be shifted in the second direction DR2 by the same amount as the shift of the third light-emitting region LEA3 relative to the first and second light-emitting regions LEA1 and LEA2.

[0174] The first and second unit light-emitting regions UA1 and UA2 may be alternately arranged along the first direction DR1 within the pixel row PXR. The first and second unit light-emitting regions UA1 and UA2 may be alternately arranged along the second direction DR2 within the pixel column PXC. This arrangement of the first and second unit light-emitting regions UA1 and UA2 may allow the third light-emitting region LEA3 of the first and second unit light-emitting regions UA1 and UA2 to be arranged in a predetermined pattern. The third light-emitting region LEA3 of the first and second unit light-emitting regions UA1 and UA2, which are adjacent to each other in the second direction DR2, may be spaced relatively close to each other by a first distance DT1. The third light-emitting region LEA3 of the first and second unit light-emitting regions UA1 and UA2, which are spaced apart by the first distance DT1, may define a pair of light-emitting regions UP. The pairs of light-emitting regions UP are spaced apart by a second distance DT2 within each pixel column PXC, which may be greater than the first distance DT1.

[0175] 9 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention, showing an enlarged plan view of a portion of the display panel DP adjacent to the first rounded corner CR1 of the display panel DP according to the embodiment of the present invention shown in FIG.

[0176] 9, a display area DA of a display panel according to an embodiment includes a plurality of unit light-emitting areas UA, each of which may include a first light-emitting area LEA1, a second light-emitting area LEA2, and a third light-emitting area LEA3. The unit light-emitting areas UA may be repeatedly arranged along a first direction DR1 and a second direction DR2.

[0177] The scan driver SDV may be disposed in the non-display area NDA and adjacent to the second side SI2 and the first rounded corner CR1. A portion of the scan driver SDV adjacent to the first rounded corner CR1 may have a curved shape that follows the first rounded corner CR1. In one embodiment, the area where the scan driver SDV is disposed may be referred to as a "drive area SDA." While the area where the scan driver SDV is disposed is shown as the drive area SDA in FIG. 9, the area where the light emitting driver EDV described above in FIG. 7 is disposed may also be referred to as a drive area. The scan driver SDV and the light emitting driver EDV may each include a plurality of transistors, and a voltage line VL (see FIG. 14a), which will be described later, may be disposed in the drive area SDA where the scan driver SDV and the light emitting driver EDV are disposed.

[0178] The non-display area NDA includes a dummy area DMA provided between the drive area SDA and the display area DA. The dummy area DMA may be an area where the scan driver SDV is not arranged. The dummy area DMA may be an area between an area where the scan driver SDV is arranged and an area where the pixels PX (see FIG. 7) are arranged.

[0179] The non-display area NDA may further include a bezel area BZA. The bezel area BZA may be an area overlapped by the above-mentioned light-blocking pattern WBM (see FIG. 2). The driver SDV and the dummy area DMA may be provided adjacent to the display area DA compared to the bezel area BZA.

[0180] 10 to 12 are enlarged plan views of a portion of a display panel according to an embodiment of the present invention. Each of FIGS. 10 to 12 shows the planar shapes of a plurality of openings provided in a pixel definition layer PDL included in a display panel according to an embodiment. FIG. 10 shows the planar shapes of the openings in the pixel definition layer PDL provided in the display area DA, drive area SDA, and dummy area DMA in a portion adjacent to the second side SI2 of the display area DA shown in FIG. 7. FIG. 11 shows the planar shapes of the openings in the pixel definition layer PDL provided in the display area DA, drive area SDA, and dummy area DMA in a portion adjacent to the first rounded corner CR1 of the display area DA shown in FIG. 7. FIG. 12 shows the planar shapes of the openings in the pixel definition layer PDL provided in the display area DA, drive area SDA, and dummy area DMA in a portion adjacent to the fourth side SI4 of the display area DA shown in FIG. 7.

[0181] 7, 9, and 10, the pixel definition layer PDL of one embodiment includes a plurality of light emitting openings PX_OP provided in the display area DA. The pixel definition layer PDL of one embodiment further includes a plurality of drive openings SD_OP provided in the drive area SDA and a plurality of dummy openings DM_OP provided in the dummy area DMA.

[0182] The plurality of light-emitting openings PX_OP are provided to correspond to the above-mentioned plurality of light-emitting openings LEA1, LEA2, and LEA3. The plurality of light-emitting openings PX_OP may have shapes corresponding to the shapes of the plurality of light-emitting openings LEA1, LEA2, and LEA3, respectively. The plurality of light-emitting openings PX_OP may include a first light-emitting opening PX_OP1 corresponding to the first light-emitting region LEA1, a second light-emitting opening PX_OP2 corresponding to the second light-emitting region LEA2, and a third light-emitting opening PX_OP3 corresponding to the third light-emitting region LEA3. The planar areas of the first light-emitting opening PX_OP1, the second light-emitting opening PX_OP2, and the third light-emitting opening PX_OP3 may be different from each other. In this embodiment, the area of ​​the first light-emitting opening PX_OP1 may be the smallest, and the area of ​​the third light-emitting opening PX_OP3 may be the largest.

[0183] The first light-emitting opening PX_OP1 and the second light-emitting opening PX_OP2 may each be provided in plurality and arranged alternately along the second direction DR2. The third light-emitting opening PX_OP3 may be provided spaced apart from the first light-emitting opening PX_OP1 and the second light-emitting opening PX_OP2 in the first direction DR1. The third light-emitting opening PX_OP3 may each be provided in plurality and arranged along the second direction DR2.

[0184] At least a part of the light-emitting element OLED described above in Fig. 6 may be disposed in each of the plurality of light-emitting openings PX_OP. At least an emission layer EML among components included in the light-emitting element OLED may be disposed in each of the plurality of light-emitting openings PX_OP.

[0185] A plurality of drive openings SD_OP are provided in the drive region SDA of the non-display area NDA. At least a portion of the plurality of drive openings SD_OP overlaps the above-mentioned scan driver SDV in a plane. The plurality of drive openings SD_OP are provided in the drive region SDA and are spaced apart in one direction from the plurality of light emitting openings PX_OP provided in the display area DA. In a portion adjacent to the second side SI2 of the display area DA, the plurality of drive openings SD_OP may be spaced apart from the plurality of light emitting openings PX_OP in a first direction DR1.

[0186] The plurality of drive openings SD_OP may have a shape in a plane that is different from the shape of each of the plurality of light emitting openings PX_OP. In one embodiment, the area of ​​each of the plurality of drive openings SD_OP in a plane may be smaller than the area of ​​each of the plurality of light emitting openings PX_OP in a plane. The plurality of drive openings SD_OP may have a rectangular shape in a plane. However, this is not limited thereto, and the plurality of drive openings SD_OP may have various shapes in a plane. For example, the plurality of drive openings SD_OP may have a circular shape, an elliptical shape, a rectangular shape, or a chamfered rectangular shape in a plane.

[0187] The plurality of dummy openings DM_OP are provided in a dummy area DMA of the non-display area NDA. The dummy area DMA may be defined as an area where the plurality of dummy openings DM_OP are provided. The plurality of dummy openings DM_OP do not overlap the above-mentioned scan driver SDV in a plan view. The plurality of dummy openings DM_OP are provided in the dummy area DMA and are arranged between the plurality of light emitting openings PX_OP provided in the display area DA and the plurality of drive openings SD_OP provided in the drive area SDA. In a portion adjacent to the second side SI2 of the display area DA, the plurality of dummy openings DM_OP may be arranged between the plurality of light emitting openings PX_OP and the plurality of drive openings SD_OP based on the first direction DR1.

[0188] The multiple dummy openings DM_OP may have substantially the same shape in a plane as the multiple light emitting openings PX_OP or the multiple drive openings SD_OP. For example, as shown in FIG. 10 , the multiple dummy openings DM_OP may have substantially the same shape in a plane as the multiple drive openings SD_OP. The multiple dummy openings DM_OP may have a circular, elliptical, rectangular, or chamfered rectangular shape in a plane. Meanwhile, in this specification, "substantially the same" not only refers to cases where the shapes are physically the same, but also includes cases where the same design exists but the only difference is a process error. The multiple dummy openings DM_OP may be formed by the same process as the multiple light emitting openings PX_OP or the multiple drive openings SD_OP, and may have substantially the same shape in a plane as the multiple light emitting openings PX_OP or the multiple drive openings SD_OP.

[0189] The minimum distance between any one of the dummy openings DM_OP and its nearest neighboring opening PX_OP based on the separation direction of the light emitting openings PX_OP and the drive openings SD_OP may be smaller than or equal to the minimum distance between any one of the dummy openings DM_OP and its nearest neighboring opening SD_OP. In one embodiment, in a portion adjacent to the second side SI2 of the display area DA, the separation direction of the light emitting openings PX_OP and the drive openings SD_OP is a first direction DR1, the minimum distance between any one of the dummy openings DM_OP and its nearest neighboring opening PX_OP based on the first direction DR1 is a first distance d1, and the minimum distance between any one of the dummy openings DM_OP and its nearest neighboring opening SD_OP based on the first direction DR1 is a second distance d2, and the first distance d1 may be smaller than or equal to the second distance d2. The first distance d1 may be 50% or more and 100% or less of the second distance d2.

[0190] The plurality of dummy openings DM_OP may be arranged in a direction intersecting the separation direction of the emission openings PX_OP and the drive openings SD_OP. A dummy region DMA in which the plurality of dummy openings DM_OP are arranged may extend in a direction intersecting the separation direction of the emission openings PX_OP and the drive openings SD_OP. In a portion adjacent to the second side SI2 of the display area DA, the plurality of dummy openings DM_OP may be arranged along a second direction DR2, and the dummy region DMA may extend along the second direction DR2.

[0191] The dummy region DMA may extend along the second direction DR2 and have a first width W1 in the first direction DR1, which may be between 40 μm and 80 μm.

[0192] Meanwhile, the dummy area DMA may be provided adjacent to at least some of the first to fourth sides SI1 to SI4 and the first to third rounded corners CR1 to CR3 of the display area DA. As shown in Fig. 10, the dummy area DMA may be provided adjacent to the second side SI2. Alternatively, as shown in Fig. 11, the dummy area DMA may be provided adjacent to the first rounded corner CR1, or as shown in Fig. 12, the dummy area DMA may be provided adjacent to the fourth side SI4. Although not shown, the dummy area DMA may also be provided adjacent to the third side SI3, the second rounded corner CR2, and the third rounded corner CR3.

[0193] 7, 9, and 11, the pixel definition layer PDL of one embodiment includes a plurality of light emitting openings PX_OP provided in the display area DA. The pixel definition layer PDL of one embodiment further includes a plurality of drive openings SD_OP provided in the drive area SDA and a plurality of dummy openings DM_OP provided in the dummy area DMA.

[0194] The plurality of drive openings SD_OP are provided in the drive region SDA and are spaced apart in one direction from the plurality of light emitting openings PX_OP provided in the display region DA. In a portion of the display region DA adjacent to the first rounded corner CR1, the plurality of drive openings SD_OP may be spaced apart from the plurality of light emitting openings PX_OP in a fourth direction DR4, which is a direction between the first direction DR1 and the second direction DR2.

[0195] The plurality of dummy openings DM_OP are provided in the dummy region DMA and are arranged between the plurality of light emitting openings PX_OP provided in the display region DA and the plurality of drive openings SD_OP provided in the drive region SDA. In a portion adjacent to the first rounded corner CR1 of the display region DA, the plurality of dummy openings DM_OP may be arranged between the plurality of light emitting openings PX_OP and the plurality of drive openings SD_OP with respect to the fourth direction DR4.

[0196] The plurality of dummy openings DM_OP may be arranged in a direction intersecting the separation direction of the emission openings PX_OP and the drive openings SD_OP. A dummy region DMA in which the plurality of dummy openings DM_OP are arranged may extend in a direction intersecting the separation direction of the emission openings PX_OP and the drive openings SD_OP. In a portion adjacent to the first rounded corner CR1 of the display region DA, the plurality of dummy openings DM_OP may be arranged along a fifth direction DR5 intersecting the fourth direction DR4, and the dummy region DMA may extend along the fifth direction DR5.

[0197] The plurality of dummy openings DM_OP may be provided in a plurality of rows in the separation direction of the light emitting opening PX_OP and the drive opening SD_OP. The plurality of dummy openings DM_OP may include a first dummy opening DM_OPa and a second dummy opening DM_OPb. The first dummy opening DM_OPa may be disposed adjacent to the drive opening SD_OP. The second dummy opening DM_OPb may be disposed adjacent to the light emitting opening PX_OP. The second dummy opening DM_OPb may be provided between the first dummy opening DM_OPa and the light emitting opening PX_OP. Each of the first dummy openings DM_OPa and the second dummy openings DM_OPb may be provided in plurality and arranged in a direction intersecting the separation direction. In a portion adjacent to the first rounded corner CR1 of the display area DA, the plurality of first dummy openings DM_OPa and the plurality of second dummy openings DM_OPb may be arranged along a fifth direction DR5.

[0198] 7, 9, and 11, the pixel definition layer PDL of one embodiment includes a plurality of light emitting openings PX_OP provided in the display area DA. The pixel definition layer PDL of one embodiment further includes a plurality of drive openings SD_OP provided in the drive area SDA and a plurality of dummy openings DM_OP provided in the dummy area DMA.

[0199] The plurality of drive openings SD_OP are provided in the drive region SDA and are spaced apart in one direction from the plurality of light emitting openings PX_OP provided in the display region DA. In a portion of the display region DA adjacent to the first rounded corner CR1, the plurality of drive openings SD_OP may be spaced apart from the plurality of light emitting openings PX_OP in a fourth direction DR4, which is a direction between the first direction DR1 and the second direction DR2.

[0200] The plurality of dummy openings DM_OP are provided in the dummy region DMA and are arranged between the plurality of light emitting openings PX_OP provided in the display region DA and the plurality of drive openings SD_OP provided in the drive region SDA. In a portion adjacent to the first rounded corner CR1 of the display region DA, the plurality of dummy openings DM_OP may be arranged between the plurality of light emitting openings PX_OP and the plurality of drive openings SD_OP with respect to the fourth direction DR4.

[0201] The plurality of dummy openings DM_OP may be arranged in a direction intersecting the separation direction of the emission openings PX_OP and the drive openings SD_OP. A dummy region DMA in which the plurality of dummy openings DM_OP are arranged may extend in a direction intersecting the separation direction of the emission openings PX_OP and the drive openings SD_OP. In a portion adjacent to the first rounded corner CR1 of the display region DA, the plurality of dummy openings DM_OP may be arranged along a fifth direction DR5 intersecting the fourth direction DR4, and the dummy region DMA may extend along the fifth direction DR5.

[0202] The plurality of dummy openings DM_OP may be provided in a plurality of rows in the separation direction of the light emitting opening PX_OP and the drive opening SD_OP. The plurality of dummy openings DM_OP may include a first dummy opening DM_OPa and a second dummy opening DM_OPb. The first dummy opening DM_OPa may be disposed adjacent to the drive opening SD_OP. The second dummy opening DM_OPb may be disposed adjacent to the light emitting opening PX_OP. The second dummy opening DM_OPb may be provided between the first dummy opening DM_OPa and the light emitting opening PX_OP. Each of the first dummy openings DM_OPa and the second dummy openings DM_OPb may be provided in plurality and arranged in a direction intersecting the separation direction. In a portion adjacent to the first rounded corner CR1 of the display area DA, the plurality of first dummy openings DM_OPa and the plurality of second dummy openings DM_OPb may be arranged along a fifth direction DR5.

[0203] 7, 9, 10, and 12, the pixel definition layer PDL of one embodiment includes a plurality of light emitting openings PX_OP provided in the display area DA. The pixel definition layer PDL of one embodiment further includes a plurality of drive openings SD_OP provided in the drive area SDA and a plurality of dummy openings DM_OP provided in the dummy area DMA.

[0204] A plurality of driving openings SD_OP are provided in the driving region SDA and are spaced apart in one direction from a plurality of light emitting openings PX_OP provided in the display region DA. In a portion adjacent to the fourth side SI4 of the display region DA, the plurality of driving openings SD_OP may be spaced apart from the plurality of light emitting openings PX_OP in a second direction DR2. Meanwhile, in a portion adjacent to the fourth side SI4, no separate driving unit is arranged in the driving region SDA, but a voltage line VL (see FIG. 14a), which will be described later, may be arranged therein.

[0205] The plurality of dummy openings DM_OP are provided in the dummy region DMA and are arranged between the plurality of light emitting openings PX_OP provided in the display region DA and the plurality of drive openings SD_OP provided in the drive region SDA. In a portion adjacent to the fourth side SI4 of the display region DA, the plurality of dummy openings DM_OP may be arranged between the plurality of light emitting openings PX_OP and the plurality of drive openings SD_OP with respect to the second direction DR2.

[0206] The plurality of dummy openings DM_OP may be arranged in a direction intersecting the separation direction of the emission openings PX_OP and the drive openings SD_OP. A dummy area DMA in which the plurality of dummy openings DM_OP are arranged may extend in a direction intersecting the separation direction of the emission openings PX_OP and the drive openings SD_OP. In a portion adjacent to the fourth side SI4 of the display area DA, the plurality of dummy openings DM_OP may be arranged along a first direction DR1, and the dummy area DMA may extend along the first direction DR1.

[0207] Fig. 13 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention. Fig. 13 shows the planar shapes of a plurality of openings provided in a pixel definition layer PDL included in a display panel according to the embodiment, and Fig. 13 shows the planar shapes of the openings in the pixel definition layer PDL provided in the display area DA, drive area SDA, and dummy area DMA in a portion adjacent to the second side SI2 of the display area DA shown in Fig. 7. Meanwhile, Fig. 13 shows a partial plan view of a display panel including dummy openings DM_OP in the dummy area DMA of another embodiment shown in Fig. 10.

[0208] 13, unlike the embodiment shown in FIG. 10, the plurality of dummy openings DM_OP' may have substantially the same shape as at least some of the plurality of light-emitting openings PX_OP' in a plan view. The plurality of dummy openings DM_OP' may have substantially the same shape as at least one of the first light-emitting opening PX_OP1, the second light-emitting opening PX_OP2, and the third light-emitting opening PX_OP3 included in the plurality of light-emitting openings PX_OP. For example, the plurality of dummy openings DM_OP' may include a first sub-dummy opening DM_OP1 having the same shape as the first light-emitting opening PX_OP1, a second sub-dummy opening DM_OP2 having the same shape as the second light-emitting opening PX_OP2, and a third sub-dummy opening DM_OP3 having the same shape as the third light-emitting opening PX_OP3. Meanwhile, unlike the embodiment shown in FIG. 13, the plurality of dummy openings DM_OP' may have openings that are the same as some of the first light-emitting opening PX_OP1, the second light-emitting opening PX_OP2, and the third light-emitting opening PX_OP3, but may not have openings corresponding to the remaining portions. For example, the multiple dummy openings DM_OP' may include only a third sub-dummy opening DM_OP3 having the same shape as the third light-emitting opening PX_OP3. Alternatively, the multiple dummy openings DM_OP' may include only a first sub-dummy opening DM_OP1 having the same shape as the first light-emitting opening PX_OP1 and a second sub-dummy opening DM_OP2 having the same shape as the second light-emitting opening PX_OP2.

[0209] 14a and 14b are cross-sectional views of a portion of a display panel according to an embodiment of the present invention, each showing cross-sectional shapes of openings in a pixel definition layer PDL provided in a display area DA, a dummy area DMA, and a drive area SDA, which are sequentially arranged along one direction, and cathodes CE disposed corresponding to the openings.

[0210] Referring to Figures 9, 10, and 14a, the pixel definition layer PDL of one embodiment includes an emission opening PX_OP provided in the display area DA, a drive opening SD_OP provided in the drive area SDA, and a dummy opening DM_OP provided in the dummy area DMA, and each of the emission opening PX_OP, the drive opening SD_OP, and the dummy area DM_OP may be formed by removing a portion of the pixel definition layer PDL so as to expose a structure disposed below the pixel definition layer PDL.

[0211] The light-emitting opening PX_OP may be provided in the display area DA to expose a portion of the anode AE. An emitting layer EML of the light-emitting element OLED may be disposed within the light-emitting opening PX_OP. The cathode CE may be provided as a common layer for each of the display area DA, the driving area SDA, and the dummy area DMA, and may include a light-emitting portion CE_1 disposed within the light-emitting opening PX_OP. The light-emitting layer EML may be interposed between the anode of the light-emitting element OLED and the light-emitting portion CE-1.

[0212] A drive opening SD_OP is provided in the drive region SDA, and a portion of the voltage line VL may be exposed through the drive opening SD_OP. The voltage line VL is disposed in the drive region SDA and may be disposed on the same layer as the anode AE ​​of the light-emitting element OLED. The voltage line VL may be disposed on, for example, the seventh insulating layer INS7.

[0213] The cathode CE is provided to overlap the drive region SDA and may include a drive portion CE_2 disposed within the drive opening SD_OP. The drive portion CE_2 may be disposed within the drive opening SD_OP and may contact an exposed upper surface of the voltage line VL. The drive portion CE_2 may be electrically coupled to the voltage line VL and receive a data voltage from the voltage line VL.

[0214] The dummy opening DM_OP may be provided in the dummy region DMA, and may expose a structure disposed below the pixel defining layer PDL through the dummy opening DM_OP. For example, the dummy opening DM_OP may expose an upper surface of the topmost insulating layer included in the circuit element layer DP-CL (see FIG. 6). As shown in FIG. 14a, the dummy opening DM_OP may expose an upper surface INS7_U of the seventh insulating layer INS7, which is the topmost insulating layer among the insulating layers. The cathode CE may be provided to overlap the dummy opening DMA and may include a dummy portion CE_D disposed within the dummy opening DM_OP. The dummy portion CE_D may be disposed within the dummy opening DM_OP and may contact the exposed upper surface INS7_U of the seventh insulating layer INS7.

[0215] The light-emitting opening PX_OP, the drive opening SD_OP, and the dummy opening DM_OP may each include inclined surfaces IS1, IS2, and IS3 having a predetermined taper angle. The inclined surfaces IS1, IS2, and IS3 of the light-emitting opening PX_OP, the drive opening SD_OP, and the dummy opening DM_OP may each be inclined surfaces having an acute angle with respect to the upper surface INS7_U of the seventh insulating layer INS7. The light-emitting opening PX_OP may include a first inclined surface IS1, the drive opening SD_OP may include a second inclined surface IS2, and the dummy opening DM_OP may include a third inclined surface IS3.

[0216] The slope of the third inclined surface IS3 may be substantially the same as one of the slopes of the first inclined surface IS1 and the second inclined surface IS2. For example, as shown in Fig. 14a, the slopes of the first inclined surface IS, the second inclined surface IS2, and the third inclined surface IS3 may all be the same. Alternatively, the slope of the third inclined surface IS3 may be substantially the same as the slope of the second inclined surface IS2, but different from the slope of the first inclined surface IS1.

[0217] Portions of the cathode CE disposed within each of the light-emitting opening PX_OP, the drive opening SD_OP, and the dummy opening DM_OP are disposed on the inclined surfaces IS1, IS2, and IS3. The cathode CE is disposed on top of each of the first inclined surface IS, the second inclined surface IS2, and the third inclined surface IS3, and may be in contact with each of the first inclined surface IS, the second inclined surface IS2, and the third inclined surface IS3. The light-emitting portion CE_1 of the cathode CE may be disposed directly on the first inclined surface IS1. The drive portion CE_2 of the cathode CE may be disposed directly on the second inclined surface IS2. The dummy portion CE_D of the cathode CE may be disposed directly on the third inclined surface IS3.

[0218] In one embodiment of the display device, a plurality of dummy openings DM_OP are provided in a dummy area DMA arranged on a plane between the display area DA and the drive area SDA, thereby preventing a display defect in which part of the non-display area NDA adjacent to the display area DA appears dark.

[0219] Unlike the display device of the embodiment, if a separate dummy opening DM_OP is not provided in the dummy region DMA, differences in reflectivity may occur between the dummy region DMA and the adjacent display region DA and drive region SDA. The display region DA and drive region SDA are each provided with an emission opening PX_OP and a drive opening SD_OP for electrical connection with the anode AE ​​and voltage line VL, respectively. A portion of the cathode CE is disposed along the inclined surfaces IS1 and IS2 of the emission opening PX_OP and the drive opening SD_OP, and the metal-containing cathode CE may be disposed along the inclined surfaces IS1 and IS2. Meanwhile, if a separate dummy opening DM_OP is not provided, no inclined surfaces are provided in the portion corresponding to the dummy region DMA, and the reflectivity of the display region DA and drive region SDA may differ from that of the dummy region DMA. This may result in differences in visibility between the display region DA and drive region SDA and the dummy region DMA when viewed from the outside.

[0220] In the display device according to an embodiment, a plurality of dummy openings DM_OP are provided in a dummy region DMA disposed between the display region DA and the drive region SDA, and a cathode CE is also disposed on a third inclined surface IS3 of the dummy opening DM_OP, so that the reflectance of the dummy region DMA can be adjusted to be similar to the reflectance of the display region DA and the drive region SDA, thereby preventing the dummy region DMA from appearing dark from the outside and improving the display quality of the display device.

[0221] 14b, unlike the embodiment shown in FIG. 14a, the display device according to the embodiment may further include a dummy electrode DME disposed in the dummy region DMA. The dummy electrode DME may be disposed in the dummy region DMA and on the same layer as the anode AE ​​of the light-emitting element OLED and the voltage line VL. The dummy electrode DME may be disposed on, for example, a seventh insulating layer INS7.

[0222] The dummy electrode DME may be provided in a floating state with no separate voltage applied thereto, so that even if a portion of the cathode CE contacts the dummy electrode DME, no separate signal may be provided to the portion of the cathode CE that contacts the dummy electrode DME.

[0223] The dummy opening DM_OP may be provided in the dummy region DMA, and a structure disposed below the pixel defining layer PDL may be exposed through the dummy opening DM_OP. For example, as shown in FIG. 14b, a portion of the upper surface of the dummy electrode DME may be exposed through the dummy opening DM_OP. The cathode CE may be provided to overlap the dummy opening DMA and may include a dummy portion CE_D disposed within the dummy opening DM_OP. The dummy portion CE_D may be disposed within the dummy opening DM_OP and may contact the exposed upper surface of the dummy electrode DME.

[0224] The display device according to the embodiment may be applied to various electronic devices. The electronic device according to the embodiment may include the display device described above, and may further include a module or device having additional functions other than the display device.

[0225] Fig. 15 is a block diagram of an electronic device according to one embodiment. Referring to Fig. 15, an electronic device 10_E according to one embodiment may include a display module 11, a processor 12, a memory 13, and a power supply module 14. The display module 11 may include the display panel DP previously described with reference to Figs. 3 to 14b.

[0226] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0227] The memory 13 may store data information necessary for the operation of the processor 12 and the display module 11. When the processor 12 executes an application stored in the memory 13, an image data signal and / or an input control signal is transmitted to the display module 11, and the display module 11 processes the provided signal and outputs image information via a display screen.

[0228] The power supply module 14 may include a power supply module such as a power adapter or a battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required to operate the electronic device 10_E.

[0229] At least one of the components of the electronic device 10_E described above may be included in the display device according to the above-described embodiment. Furthermore, some of the individual modules functionally included in one module may be included in the display device, and other modules may be provided separately from the display device. For example, the display device may include the display module 11, and the processor 12, memory 13, and power supply module 14 may be provided in the form of other devices within the electronic device 11 rather than the display device.

[0230] FIG. 16 is a schematic diagram of an electronic device according to various embodiments.

[0231] Referring to FIG. 16, various electronic devices to which the display device according to the embodiment can be applied include not only electronic devices for displaying images such as a smartphone 10_1a, a tablet PC 10_1b, a laptop 10_1c, a television 10_1d, and a desk monitor 10_1e, but also wearable electronic devices including a display module such as smart glasses 10_2a, a head-mounted display 10_2b, and a smart watch 10_2c, and vehicular electronic devices 10_3 including a display module such as a CID (Center Information Display) and a room mirror display arranged on an automobile's instrument panel, center fascia, or dashboard.

[0232] Although the present invention has been described with reference to the embodiments, it should be understood by those skilled in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as defined in the following claims. Furthermore, the disclosed embodiments of the present invention are not intended to limit the technical spirit of the present invention, and all technical spirits within the scope of the following claims and their equivalents should be interpreted as being included in the scope of the present invention. [Explanation of symbols]

[0233] DD: Display device DP: Display panel SUB: Base layer DP-CL: Circuit element layer DP-OLED: Display element layer PDL: Pixel definition layer OLED: Light emitting element PX_OP: Light emitting opening SD_OP: Drive opening DM_OP: Dummy opening

Claims

1. a base layer divided into a display area and a non-display area surrounding at least a portion of the display area; a circuit element layer including a driving unit disposed on the base layer and overlapping the non-display area; a display element layer disposed on the circuit element layer; The display element layer is a pixel defining film disposed on the circuit element layer; a light-emitting element that is superimposed on the display region and includes a light-emitting layer, The pixel defining film is a light-emitting opening portion overlapping the display area and in which at least the light-emitting layer is disposed; a driving opening portion overlapping the non-display area and the driving portion; a dummy opening portion overlapping the non-display area and disposed between the light emitting opening portion and the drive opening portion, The dummy opening is A display device having substantially the same planar shape as the light emitting aperture or the drive aperture.

2. The display device according to claim 1 , wherein each of the light-emitting openings, the drive openings, and the dummy openings includes an inclined surface that forms an acute angle with respect to an upper surface of the circuit element layer.

3. The light-emitting element is an anode disposed on the circuit element layer; a cathode facing the anode, 3. The display device according to claim 2, wherein the light-emitting layer is disposed between the anode and the cathode.

4. The display device according to claim 3 , wherein the cathode is disposed on the inclined surface.

5. The circuit element layer includes: further comprising a plurality of insulating layers disposed on the base layer; The display device according to claim 3 , wherein the anode is disposed directly on an uppermost insulating layer of the plurality of insulating layers.

6. the cathode includes a dummy portion disposed in the dummy opening; The display device according to claim 5 , wherein the dummy portion is disposed directly on the uppermost insulating layer of the plurality of insulating layers.

7. the display element layer further includes a dummy electrode disposed on the circuit element layer; the cathode includes a dummy portion disposed in the dummy opening; The display device according to claim 5 , wherein the dummy portion is in contact with the dummy electrode.

8. the cathode includes a driven portion disposed within the driven aperture; the display element layer further includes a voltage line disposed on the circuit element layer; The display device according to claim 3 , wherein the driving portion is in contact with the voltage line.

9. The display device according to claim 1 , wherein each of the drive openings and the dummy openings has a circular, elliptical, rectangular, or chamfered rectangular shape in plan view.

10. The minimum distance between the dummy opening and the light emitting opening is The display device of claim 1 , wherein the minimum spacing between the driven openings and the dummy openings is smaller than or equal to the minimum spacing between the driven openings and the dummy openings.

11. The light emitting opening is a first light-emitting opening; a second light emitting opening spaced apart from the first light emitting opening; a third light-emitting opening spaced apart from the first light-emitting opening and the second light-emitting opening, 2. The display device according to claim 1, wherein the dummy opening has substantially the same planar shape as at least one of the first to third light-emitting openings.

12. the display area includes a first side extending in a first direction, a second side adjacent to one end of the first side and extending in a second direction intersecting the first direction, and a first rounded corner connecting the one end of the first side to one end of the second side adjacent to the one end of the first side, The dummy opening is The display device of claim 1 , wherein the first edge is provided adjacent to at least one of the first edge, the second edge, and the first rounded corner.

13. further comprising a window disposed over the display element layer; The window is A base member; a light-blocking pattern disposed under the base member and overlapping the non-display area; The display device according to claim 1 , wherein the driving openings and the dummy openings are provided adjacent to the display area in a plane relative to the light-shielding pattern.

14. The display device of claim 1 , wherein the dummy region in which the dummy openings are provided extends in a direction intersecting a direction in which the light emitting openings and the driving openings are spaced apart from each other.

15. The display device according to claim 1 , wherein a width of the dummy region where the dummy opening is provided is 40 μm or more and 80 μm or less.

16. The dummy opening is a first dummy opening adjacent to the driven opening; The display device according to claim 1 , further comprising: a second dummy opening provided between the first dummy opening and the light emitting opening on a plane.

17. The display device of claim 1 , wherein the circuit element layer further comprises at least one transistor electrically connected to the light emitting element.

18. a base layer divided into a display area and a non-display area surrounding at least a portion of the display area; a circuit element layer including a driving unit disposed on the base layer and overlapping the non-display area; a display element layer disposed on the circuit element layer; The display element layer is a pixel defining film disposed on the circuit element layer; a light-emitting element overlapping the display area, The pixel defining film is a light-emitting opening portion overlapping the display area; a driving opening portion overlapping the non-display area and the driving portion; a dummy opening portion overlapping the non-display area and disposed between the light emitting opening portion and the drive opening portion, The display device, wherein the light emitting opening, the drive opening, and the dummy opening each include an inclined surface that forms an acute angle with respect to an upper surface of the circuit element layer.

19. The light-emitting element is an anode disposed over the circuit element; a cathode facing the anode; a light-emitting layer disposed between the anode and the cathode; 20. The display device of claim 18, wherein the cathode is disposed on the inclined surface.

20. a display module including a display panel; a processor including at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, and a controller; The display panel includes: a base layer divided into a display area and a non-display area surrounding at least a portion of the display area; a circuit element layer including a driving unit disposed on the base layer and overlapping the non-display area; a display element layer disposed on the circuit element layer; The display element layer is a pixel defining film disposed on the circuit element layer; a light-emitting element overlapping the display area, The pixel defining film is a light-emitting opening portion overlapping the display area; a driving opening portion overlapping the non-display area and the driving portion; a dummy opening that is arranged between the light emitting opening and the drive opening and does not overlap with the drive section.

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