Display device and electronic apparatus

Abstract

To provide a display device.SOLUTION: A display device comprises a first pixel circuit disposed on a substrate and a first light-emitting diode electrically connected to the first pixel circuit. The first pixel circuit includes a driving transistor having a driving semiconductor layer and a driving gate electrode, a first initialization transistor having a first initialization semiconductor layer A4 and a first initialization gate electrode and electrically connected to the driving transistor, and a first connection electrode 1630 electrically connecting the first initialization semiconductor layer A4 to the driving gate electrode. A semiconductor layer including a first initialization semiconductor layer A4 had a first extension area 1412 extending from a channel area C4 of the first initialization semiconductor layer A4 to the first connection electrode 1630. The first extension area 1412 overlaps a first shield layer disposed below the first initialization semiconductor layer A4 and a second shield layer disposed above the first initialization semiconductor layer A4.SELECTED DRAWING: Figure 19

Description

[Technical Field]

[0001] The present invention relates to a display device structure. [Background technology]

[0002] Recently, the applications of display devices have become more diverse. As the range of uses of display devices has become wider, the demand for high-resolution display devices has increased. To manufacture a high-resolution display device, it is necessary to arrange electronic elements with a diverse configuration in a small area. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Korean Patent Publication No. 10-2021-0029339 [Patent Document 2] Korean Patent Publication No. 10-2022-0004858 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a display device that displays high quality images, but this problem is merely an example and is not intended to limit the scope of the present invention. [Means for solving the problem]

[0005] One embodiment of the present invention provides a display device including: a first pixel circuit disposed on a substrate; and a first light emitting diode electrically connected to the first pixel circuit, wherein the first pixel circuit includes: a driving transistor including a driving semiconductor layer and a driving gate electrode; a first initialization transistor including a first initialization semiconductor layer and a first initialization gate electrode and electrically connected to the driving transistor; and a first connecting electrode electrically connecting the first initialization semiconductor layer and the driving gate electrode, wherein a semiconductor layer including the first initialization semiconductor layer includes a first extension region extending from a channel region of the first initialization semiconductor layer to the first connecting electrode, and the first extension region overlaps with a first shield layer disposed under the first initialization semiconductor layer and a second shield layer disposed over the first initialization semiconductor layer, respectively.

[0006] In one embodiment, the first shield layer may be interposed between the top surface of the substrate and the drive transistor.

[0007] In an embodiment, the first shield layer may be a lower metal layer arranged to overlap the channel region of the driving transistor and the first connecting electrode.

[0008] In an embodiment, the second shield layer may be interposed between the first connecting electrode and the first light emitting diode.

[0009] In one embodiment, the display device further includes a drive voltage line that transmits a drive voltage to the first pixel circuit and extends through the first pixel circuit, and the second shield layer may be the drive voltage line.

[0010] In one embodiment, the driving semiconductor layer and the first initialization semiconductor layer are disposed on different layers, and the driving semiconductor layer may be a silicon semiconductor layer, and the first initialization semiconductor layer may be an oxide semiconductor layer.

[0011] In one embodiment, the display device may further include a second pixel circuit adjacent to the first pixel circuit along a first direction, a third pixel circuit arranged on the opposite side of the first pixel circuit across the second pixel circuit, and a vertical voltage line arranged between the second pixel circuit and the third pixel circuit and extending along a second direction intersecting the first direction.

[0012] In one embodiment, the display device further includes a second light emitting diode electrically connected to the second pixel circuit and a third light emitting diode electrically connected to the third pixel circuit, wherein the first light emitting diode may emit red light, the second light emitting diode may emit green light, and the third light emitting diode may emit blue light.

[0013] In one embodiment, the vertical voltage line may be disposed on the same layer as the second shield layer.

[0014] In one embodiment, the display device may further include a horizontal voltage line electrically connected to the vertical voltage line and extending along the first direction, and a bridge pattern electrically connecting the vertical voltage line and the horizontal voltage line, wherein the bridge pattern may be disposed on substantially the same layer as the first connecting electrode.

[0015] In one embodiment, the third pixel circuit includes a silicon semiconductor layer and an oxide semiconductor layer, and when viewed in a direction perpendicular to the substrate, the oxide semiconductor layer of the third pixel circuit may be spaced apart from the bridge pattern.

[0016] In one embodiment, the third pixel circuit further includes a driving transistor, a compensation transistor including a compensation semiconductor layer and a compensation gate electrode, and electrically connected to the driving transistor, an emission control transistor including an emission control semiconductor layer and an emission control gate electrode, and electrically connected to the driving transistor, and a second connecting electrode electrically connecting the compensation transistor and the driving transistor and electrically connecting the compensation transistor and the emission control transistor, wherein the semiconductor layer including the compensation semiconductor layer includes a second extension region extending from a drain region of the compensation semiconductor layer to the second connecting electrode, and the bridge pattern and the second extension region may be disposed spaced apart from each other.

[0017] In one embodiment, the first pixel circuit further includes a compensation transistor including a compensation semiconductor layer and a compensation gate electrode, and electrically connected to the driving transistor, and the first initialization semiconductor layer and the compensation semiconductor layer may be integrally connected.

[0018] In one embodiment, the channel width:channel length ratio (W / L) of the first initialization transistor is also different from the channel width:channel length ratio (W / L) of the compensation transistor.

[0019] In one embodiment, the channel length of the compensation transistor is longer than the channel length of the first initialization transistor.

[0020] Another embodiment of the present invention provides a display device including: a first pixel circuit arranged on a substrate; a second pixel circuit adjacent to the first pixel circuit along a first direction; a third pixel circuit arranged on the opposite side of the first pixel circuit with the second pixel circuit interposed therebetween; a vertical voltage line arranged in a spaced-apart area between the second pixel circuit and the third pixel circuit and extending along a second direction intersecting the first direction; a horizontal voltage line electrically connected to the vertical voltage line and extending along the first direction; and a bridge pattern electrically connecting the vertical voltage line and the horizontal voltage line, wherein the third pixel circuit includes a silicon semiconductor layer and an oxide semiconductor layer, and when viewed from a direction perpendicular to the substrate, the oxide semiconductor layer and the bridge pattern are arranged spaced apart from each other.

[0021] In one embodiment, the display device further includes a first light emitting diode electrically connected to the first pixel circuit, a second light emitting diode electrically connected to the second pixel circuit, and a third light emitting diode electrically connected to the third pixel circuit, wherein the first light emitting diode may emit red light, the second light emitting diode may emit green light, and the third light emitting diode may emit blue light.

[0022] In one embodiment, the first pixel circuit, the second pixel circuit, and the third pixel circuit each include a driving transistor including a driving gate electrode and a driving semiconductor layer included in the silicon semiconductor layer, a first initialization transistor including a first initialization gate electrode and a first initialization semiconductor layer included in the oxide semiconductor layer and electrically connected to the driving transistor, and a first connecting electrode electrically connecting the first initialization semiconductor layer and the driving gate electrode, wherein the oxide semiconductor layer includes a first extension region extending from a channel region of the first initialization semiconductor layer to the first connecting electrode, and the first extension region may overlap with a first shielding layer disposed under the oxide semiconductor layer and a second shielding layer disposed over the oxide semiconductor layer, respectively.

[0023] In one embodiment, the first shield layer may be a lower metal layer interposed between the top surface of the substrate and the drive transistor.

[0024] In one embodiment, the display device further includes a driving voltage line arranged on the same layer as the vertical voltage line and spaced apart from the vertical voltage line, and the second shield layer may be the driving voltage line.

[0025] In one embodiment, the first pixel circuit, the second pixel circuit, and the third pixel circuit each include a compensation gate electrode and a compensation semiconductor layer included in the oxide semiconductor layer, and further include a compensation transistor electrically connected to the driving transistor, and the channel width:channel length ratio (W / L) of the first initialization transistor is different from the channel width:channel length ratio (W / L) of the compensation transistor. [Effects of the Invention]

[0026] A display device according to an embodiment of the present invention can prevent an increase in the resistance of a semiconductor layer and realize a high-quality image. The above-described advantages are merely examples, and the scope of the present invention is not limited to these advantages. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a plan view schematically illustrating a display device according to an embodiment of the present invention; [Figure 2] 1 is a block diagram illustrating a display device according to an embodiment of the present invention; [Figure 3] 1 is an equivalent circuit diagram of one pixel arranged in a display device according to an embodiment of the present invention. [Figure 4] 1 is an equivalent circuit diagram of a portion of pixels arranged in a display device according to an embodiment of the present invention; [Figure 5] 1 is a diagram illustrating a part of wirings arranged in a display area of ​​a display device according to an embodiment of the present invention; [Figure 6]1 is a cross-sectional view showing a part of a display area of ​​a display device according to an embodiment of the present invention. [Figure 7] 2 is a plan view illustrating first to third pixel circuits of a display device according to an embodiment of the present invention. FIG. [Figure 8] 8A to 8C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 7. [Figure 9] 8A to 8C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 7. [Figure 10] 8A to 8C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 7. [Figure 11] 8A to 8C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 7. [Figure 12] 8A to 8C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 7. [Figure 13] 8A to 8C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 7. [Figure 14] 8A to 8C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 7. [Figure 15] 8A to 8C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 7. [Figure 16] 8A to 8C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 7. [Figure 17] 8A to 8C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 7. [Figure 18] 8A to 8C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 7. [Figure 19] 1 is an enlarged plan view schematically illustrating a portion of a display device according to an embodiment of the present invention. [Figure 20] 1 is an enlarged plan view schematically illustrating a portion of a display device according to an embodiment of the present invention. [Figure 21] 1 is a cross-sectional view schematically illustrating a portion of a display device according to an embodiment of the present invention. [Figure 22]FIG. 10 is an enlarged plan view schematically illustrating a portion of a display device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0028] The present invention can be modified in various ways and can have various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. The advantages and features of the present invention, and methods for achieving them, will become clearer with reference to the embodiments described in detail below in conjunction with the drawings. However, the present invention is not limited to the embodiments described below, and can be embodied in various forms.

[0029] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, identical or corresponding components will be given the same drawing numbers and redundant description thereof will be omitted.

[0030] In the following embodiments, terms such as first and second are used to distinguish one component from another, without any limiting meaning.

[0031] In the following embodiments, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0032] In the following embodiments, terms such as "comprise" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0033] In the following embodiments, when a part such as a film, region, or component is said to be on or above another part, this does not only include the case where it is directly on top of the other part, but also the case where another film, region, component, etc. is interposed between them.

[0034] In the drawings, the size of components may be exaggerated or reduced for the sake of convenience. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for the sake of convenience, and the present invention is not necessarily limited to what is shown in the drawings.

[0035] If an embodiment can be implemented differently, the order of certain steps may be performed differently than that described. For example, two steps described in succession may be performed substantially simultaneously or may be performed in the reverse order of that described.

[0036] In the following embodiments, when a film, region, component, etc. is said to be connected, it includes not only the case where the film, region, component, etc. is directly connected, but also the case where the film, region, component, etc. is indirectly connected with another film, region, component, etc. interposed between them. For example, in this specification, when a film, region, component, etc. is said to be electrically connected, it includes not only the case where the film, region, component, etc. is directly electrically connected, but also the case where the film, region, component, etc. is indirectly electrically connected with another film, region, component, etc. interposed between them.

[0037] FIG. 1 is a plan view schematically showing a display device according to one embodiment of the present invention.

[0038] 1, a display device 1 may include a display area DA for displaying an image and an outer area PA outside the display area DA. The display area DA is entirely surrounded by the outer area PA.

[0039] The display area DA may have a substantially rectangular shape with rounded corners in a plan view. In other embodiments, the display area DA may have a polygonal shape such as a triangle, square, pentagon, or hexagon, or a circular, elliptical, or irregular shape.

[0040] The display device 1 of FIG. 1 is a device for displaying moving or still images and may be used in portable electronic devices such as mobile phones, laptops, tablet personal computers (PCs), smartphones, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs). The display device 1 may also be used in electronic devices for the Internet of Things (IoT), such as televisions, monitors, billboards, and wearable electronic devices such as smart watches, watch phones, eyeglass displays, and head-mounted displays (HMDs). The display device 1 according to an embodiment may also be used in automotive dashboards, center information displays (CIDs) located in the center fascia or dashboard of an automobile, room mirror displays replacing the side mirrors of an automobile, and display electronic devices located behind the front seats for rear-seat entertainment in an automobile.

[0041] FIG. 2 is a block diagram schematically illustrating a display device according to an embodiment of the present invention.

[0042] 1 and 2, a display device 1 according to an embodiment may include a pixel unit 11, a gate driving circuit 13, a data driving circuit 15, a power supply circuit 17, and a controller 19.

[0043] The pixel unit 11 may include a plurality of pixels arranged in a display area DA (FIG. 1). The plurality of pixels may be arranged in various patterns, such as a stripe array, a pentatile (diamond) array, or a mosaic array, to implement an image. Each pixel emits light through a light emitting diode (LED), and each light emitting diode (LED) may be electrically connected to a pixel circuit (PC). Each pixel circuit (PC) may be electrically connected to a gate line (GL) and a data line (DL), and may include a plurality of transistors and at least one capacitor.

[0044] The outer region PA (FIG. 1) may include various conductive lines transmitting electrical signals to the display region DA (FIG. 1), outer circuits electrically connected to the pixel circuits, and pads to which a printed circuit board or a driver IC chip is attached. For example, the outer region PA (FIG. 1) may include a gate driver circuit 13, a data driver circuit 15, a power supply circuit 17, and a controller 19.

[0045] The gate driving circuit 13 is electrically connected to the plurality of gate lines GL, and generates gate signals in response to a control signal GCS from the controller 19 and sequentially supplies the gate signals to the gate lines GL. The gate signals may be gate control signals that control the turn-on and turn-off of transistors electrically connected to the gate lines GL. The gate signals may be square wave signals including an on voltage at which the transistors are turned on and an off voltage at which the transistors are turned off. In one embodiment, the on voltage may be a high-level voltage (first-level voltage) or a low-level voltage (second-level voltage).

[0046] 2, one pixel circuit PC is illustrated as being connected to one gate line GL, but this is merely an example, and one pixel circuit PC may be connected to two or more gate lines, and the gate driving circuit 13 may supply two or more gate signals to the gate lines, each of which has a different timing at which an on-voltage is applied. For example, the pixel circuit PC may be electrically connected to a plurality of gate lines, and the gate driving circuit 13 may apply the scan signal GW, the first initialization control signal GI, the second initialization control signal GB, the compensation scan signal GC, and the emission control signal EM to the pixel circuit PC via the gate lines, respectively.

[0047] The data driving circuit 15 is connected to a plurality of data lines DL and may supply a data signal Dm to the data lines DL in response to a control signal DCS from the controller 19. The data signal Dm supplied to the data lines DL may be provided to the pixel circuits PC. The data driving circuit 15 may convert input image data having gray levels input from the controller 19 into the data signal Dm in the form of a voltage or current.

[0048] The power supply circuit 17 may generate voltages required to drive the pixel circuits PC and the light emitting diodes LED in response to a control signal PCS from the controller 19. The power supply circuit 17 may generate a driving voltage ELVDD and a common voltage ELVSS and supply them to the pixel circuits PC and the light emitting diodes LED, respectively. The driving voltage ELVDD may be a high-level voltage provided to a first electrode (or pixel electrode, anode) of the light emitting diode LED. The common voltage ELVSS may be a low-level voltage provided to a second electrode (or counter electrode, cathode) of the light emitting diode LED. The power supply circuit 17 may generate a bias voltage Vobs, a first initialization voltage Vint, and a second initialization voltage Vint and supply them to the pixel circuits PC.

[0049] The voltage level of the driving voltage ELVDD is higher than the voltage level of the common voltage ELVSS. The voltage levels of the first initialization voltage Vint and the second initialization voltage Vaint are higher than the voltage level of the common voltage ELVSS. The voltage level of the bias voltage Vobs is higher than the voltage level of the driving voltage ELVDD.

[0050] The controller 19 may generate control signals GCS, DCS, and PCS based on an externally input signal and supply them to the gate drive circuit 13, the data drive circuit 15, and the power supply circuit 17. The control signal GCS output to the gate drive circuit 13 may include a plurality of clock signals and a gate start signal. The control signal DCS output to the data drive circuit 15 may include a source start signal and a clock signal.

[0051] FIG. 3 is an equivalent circuit diagram of one pixel arranged in a display device according to one embodiment of the present invention.

[0052] FIG. 3 is an equivalent circuit diagram showing one of the light emitting diodes and a pixel circuit arranged in a display device according to an embodiment of the present invention.

[0053] 3, the pixel circuit PC is connected to gate lines, for example, a scan line GWL, a first initialization control line GIL, a second initialization control line GBL, a compensation scan line GCL, and an emission control line EML, and may receive a scan signal GW, a first initialization control signal GI, a second initialization control signal GB, a compensation scan signal GC, and an emission control signal EM. For example, the scan line GWL, the first initialization control line GIL, the second initialization control line GBL, the compensation scan line GCL, and the emission control line EML in FIG. 3 may be gate lines connected to a pixel circuit PC located in an i-th row (i is a natural number).

[0054] The pixel circuits PC may receive a data signal Dm via a data line DL. For example, the data line DL in FIG. 3 may be a signal line connected to the pixel circuits PC located in the j-th column (j is a natural number).

[0055] The pixel circuit PC of the display device according to this embodiment is electrically connected to a light emitting diode LED that emits light of a predetermined color, and the light emitting diode LED may include a first electrode (pixel electrode, anode), a second electrode (counter electrode, cathode), and an intermediate layer therebetween.

[0056] The pixel circuit PC may include a plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 and capacitors Cst and Ca. The plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 may include a drive transistor T1, a data write transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, a light-emitting control transistor T6, a second initialization transistor T7, and a bias transistor T8. The capacitors Cst and Ca may include a first capacitor Cst and a second capacitor Ca.

[0057] In one embodiment, some of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be PMOS (p-channel MOSFETs), and the remaining transistors may be NMOS (n-channel MOSFETs). For example, the driving transistor T1, the data writing transistor T2, the operation control transistor T5, the light-emitting control transistor T6, the second initialization transistor T7, and the bias transistor T8 of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be PMOS, and the compensation transistor T3 and the first initialization transistor T4 of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be PMOS, and the remaining transistors may be NMOS. Alternatively, all of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be NMOS or PMOS. The following description will focus on an embodiment in which the compensation transistor T3 and the first initialization transistor T4 are NMOS (n-channel MOSFETs) including an oxide semiconductor, and the rest are PMOS (p-channel MOSFETs).

[0058] At least one of the plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and at least one of the plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be a transistor having an oxide semiconductor layer.

[0059] The driving transistor T1, which directly affects the brightness of the display device, may be configured to include a semiconductor layer made of highly reliable polycrystalline silicon, thereby enabling a high-resolution display device. Meanwhile, oxide semiconductors have high carrier mobility and low leakage current, so they do not significantly drop voltage even over long drive periods. That is, low-frequency drive is possible because the image color does not change significantly due to voltage drop even during low-frequency drive. Because oxide semiconductors have the advantage of low leakage current, at least one of the compensation transistor T3 and the first initialization transistor T4, which are connected to the drive gate electrode of the driving transistor T1, may be made of an oxide semiconductor to prevent leakage current from flowing through the drive gate electrode and reduce power consumption. For example, the driving transistor T1, the data write transistor T2, the operation control transistor T5, the light-emitting control transistor T6, the second initialization transistor T7, and the bias transistor T8 may be transistors having low-temperature polysilicon semiconductor layers, and the compensation transistor T3 and the first initialization transistor T4 may be transistors having oxide semiconductor layers.

[0060] The driving transistor T1 may be connected between a driving voltage line (or vertical driving voltage line, PL) that provides a driving voltage ELVDD and the light emitting diode LED. A gate electrode of the driving transistor T1 may be connected to one end of a first capacitor Cst, which is a storage capacitor. A gate electrode of the driving transistor T1 may be connected to a first node N1. A source electrode of the driving transistor T1 may be connected to the driving voltage line PL via an operation control transistor T5. A drain electrode of the driving transistor T1 may be electrically connected to a pixel electrode (e.g., an anode) of the light emitting diode LED via an emission control transistor T6. The driving transistor T1 may receive a data signal Dm transmitted through a data line DL through a switching operation of the data write transistor T2 and supply a driving current to the light emitting diode LED.

[0061] A gate electrode of the data write transistor T2 may be connected to the scan line GWL. A first electrode of the data write transistor T2 may be connected to the data line DL, and a second electrode of the data write transistor T2 may be connected to the source electrode of the drive transistor T1. The data write transistor T2 is turned on by a scan signal GW transmitted through the scan line GWL to transmit a data signal Dm transmitted to the data line DL to the source electrode of the drive transistor T1. At the same time, the data signal Dm may be transmitted to the gate electrode of the drive transistor T1 by the compensation transistor T3, which is turned on.

[0062] The gate electrode of the compensation transistor T3 may be connected to the compensation scan line GCL. The first electrode of the compensation transistor T3 may be connected to the drain electrode of the driving transistor T1, and the second electrode of the compensation transistor T3 may be connected to the first node N1. The compensation transistor T3 may be turned on in response to a scan signal GW transmitted through the scan line GWL to connect the gate electrode and drain electrode of the driving transistor T1 to each other, thereby diode-connecting the driving transistor T1 and compensating for the threshold voltage Vth of the driving transistor T1.

[0063] The gate electrode of the first initialization transistor T4 may be connected to a first initialization control line GIL. The first electrode of the first initialization transistor T4 may be connected to a first initialization voltage line VIL, and the second electrode may be connected to a first node N1. The first initialization transistor T4 is turned on by a first initialization control signal GI applied from the first initialization control line GIL to transmit a first initialization voltage Vint to the gate electrode of the driving transistor T1, thereby initializing the potential of the gate electrode of the driving transistor T1 (i.e., the potential of the first node N1) to a predetermined voltage. The first initialization voltage Vint has a voltage level higher than or equal to the common voltage ELVSS.

[0064] The gate electrode of the operation control transistor T5 may be connected to the emission control line EML, the first electrode of the operation control transistor T5 may be connected to the driving voltage line PL, and the second electrode of the operation control transistor T5 may be connected to the source electrode of the driving transistor T1.

[0065] A gate electrode of the emission control transistor T6 may be connected to an emission control line EML. A first electrode of the emission control transistor T6 may be connected to a drain electrode of the driving transistor T1, and a second electrode of the emission control transistor T6 may be electrically connected to a pixel electrode of the light emitting diode LED. The operation control transistor T5 and the emission control transistor T6 may be simultaneously turned on by an emission control signal EM applied from the emission control line EML. The driving voltage ELVDD applied through the turned-on operation control transistor T5 may be compensated through the driving transistor T1 and then transmitted to the light emitting diode LED.

[0066] A gate electrode of the second initialization transistor T7 may be connected to a second initialization control line GBL. A first electrode of the second initialization transistor T7 may be connected to a pixel electrode of the light emitting diode LED, and a second electrode of the second initialization transistor T7 may be connected to a second initialization voltage line VAL. The second initialization transistor T7 may be turned on by a second initialization control signal GB applied from the second initialization control line GBL to initialize the pixel electrode of the light emitting diode LED. The second initialization control signal GB may be the same as or different from the first initialization control signal GI.

[0067] In a comparative example of the present invention, even if the minimum current of the driving transistor T1 for displaying a black image flows as a driving current, if the light emitting diode LED emits light, the black image is not properly displayed. However, according to the present invention, the second initialization transistor T7 can disperse a portion of the minimum current of the driving transistor T1 as a bypass current to a current path other than the current path toward the light emitting diode LED. Here, the minimum current of the driving transistor T1 may refer to a current under a condition where the gate-source voltage Vgs of the driving transistor T1 is lower than a threshold voltage (Vth) and the driving transistor T1 is turned off. In this way, a minimum driving current (e.g., a current of 10 pA or less) under the condition of turning off the driving transistor T1 is transmitted to the light emitting diode LED, thereby displaying a black image. When the minimum driving current for displaying a black image flows, the bypass current has a significant effect. On the other hand, when a large driving current for displaying an image such as a normal image or a white image flows, the bypass current has almost no effect. Therefore, when a driving current for displaying a black image flows, an accurate black luminance image can be realized from the driving current using the second initialization transistor T7, thereby improving the contrast ratio and providing a display device with improved display quality.

[0068] A gate electrode of the bias transistor T8 may be connected to the second initialization control line GBL, a first electrode of the bias transistor T8 may be connected to a bias voltage line VOL to which a bias voltage Vobs is provided, and a second electrode of the bias transistor T8 may be connected to the source electrode of the driving transistor T1.

[0069] One end of the first capacitor Cst may be connected to the gate electrode of the driving transistor T1, and the other end may be connected to the driving voltage line PL. The first capacitor Cst may be connected between the driving voltage line PL and a first node N1. The first capacitor Cst may store a voltage between the driving voltage ELVDD and the first node N1.

[0070] The second capacitor Ca may be an auxiliary electrode electrically connected to the light-emitting control transistor T6, the second initialization transistor T7, and the first electrode of the light-emitting diode LED. The second capacitor Ca stores and maintains a voltage corresponding to the voltage difference between the first electrode of the light-emitting diode LED and the common voltage line VSL while the second initialization transistor T7 is turned on, thereby preventing an increase in black brightness when the light-emitting control transistor T6 is turned off.

[0071] The pixel electrode of the light emitting diode LED receives a driving current from the driving transistor T1 to emit light, thereby displaying an image. The driving voltage ELVDD may be a predetermined high-level voltage, and the common voltage ELVSS may be a voltage lower than the driving voltage ELVDD.

[0072] The operation of the pixel circuit PC and the light emitting diode LED will now be described.

[0073] During the initialization period, a first initialization control signal GI of a low level may be supplied to the first initialization transistor T4 via the first initialization control line GIL, and a second initialization control signal GB of a low level may be supplied to the second initialization transistor T7 via the second initialization control line GBL. As a result, the first initialization transistor T4 and the second initialization transistor T7 may be turned on. A first initialization voltage Vint applied from the first initialization voltage line VIL may be transferred to the gate electrode of the driving transistor T1 via the first initialization transistor T4, and a second initialization voltage Vaint applied from the second initialization voltage line VAL may be transferred to the anode via the second initialization transistor T7. As a result, the voltages of the gate electrode and anode of the driving transistor T1 may be initialized.

[0074] Thereafter, during a data write period, a low-level scan signal GW is supplied through the scan line GWL, and a high-level compensation scan signal GC is supplied through the compensation scan line GCL, turning on the data write transistor T2 and the compensation transistor T3. The data write transistor T2 transfers a data signal Dm from the data line DL to the source electrode of the drive transistor T1, and the drive transistor T1 is diode-coupled by the compensation transistor T3. As a result, a compensation voltage, which is reduced by the threshold voltage of the drive transistor T1 in response to the data signal Dm, is applied to the gate electrode of the drive transistor T1.

[0075] The driving voltage ELVDD and the compensation voltage are applied to both ends of the first capacitor Cst, and a charge corresponding to the voltage difference between both ends of the first capacitor Cst can be stored in the first capacitor Cst.

[0076] Thereafter, during the light-emitting period, the light-emitting control signal EM supplied from the light-emitting control line EML changes from high to low, turning on the operation control transistor T5 and the light-emitting control transistor T6, thereby generating a driving current due to the voltage difference between the gate electrode voltage of the driving transistor T1 and the driving voltage ELVDD, and the driving current is supplied to the light-emitting diode LED via the light-emitting control transistor T6, causing it to emit light.

[0077] The characteristics of the light emitting diodes LED that emit different light and / or the characteristics of the driving transistors T1 of each pixel circuit PC may differ from one another. In particular, when driven at a high frequency, the color coordinates of the display device 1 may vary (e.g., reddish). However, according to the present invention, the voltage of the source electrode of the driving transistor T1 may be controlled by the bias voltage Vobs via the bias transistor T8. This may improve the brightness deviation (current deviation) and color coordinate variation between pixels by controlling the driving current. Therefore, a display device with improved display quality may be provided.

[0078] Figure 4 is an equivalent circuit diagram of some pixels arranged in a display device according to an embodiment of the present invention. The plurality of pixels P (Figure 3) may include a first pixel P1, a second pixel P2, and a third pixel P3 that emit light of different colors. Figure 4 is an equivalent circuit diagram showing the first pixel P1, the second pixel P2, and the third pixel P3 that emit light of different colors. In describing Figure 4, descriptions that overlap with the description of the components in Figure 3 will be omitted, and differences will be mainly described.

[0079] 4, a first pixel P1, a second pixel P2, and a third pixel P3 may share one of the gate lines GL (FIG. 1). The first pixel P1 may be electrically connected to a first data line DL1 of the data lines DL. The second pixel P2 may be electrically connected to a second data line DL2 of the data lines DL. The third pixel P3 may be electrically connected to a third data line DL3 of the data lines DL.

[0080] The first pixel P1 may include a first pixel circuit PC1 and a first light emitting diode LED1. The second initialization transistor T7 of the first pixel circuit PC1 may be connected between a second-first initialization voltage line VAL1 and the anode of the first light emitting diode LED1 and may receive a second initialization control signal GB. The first pixel P1 may emit light of a first color. For example, the first color light may be red light.

[0081] The second pixel P2 may include a second pixel circuit PC2 and a second light emitting diode LED2. A second initialization transistor T7 of the second pixel circuit PC2 may be connected between a second-second initialization voltage line VAL2 and the anode of the second light emitting diode LED2 and may receive a second initialization control signal GB. The second pixel P2 may emit light of a second color different from the first color. For example, the second color light may be green light.

[0082] The third pixel P3 may include a third pixel circuit PC3 and a third light emitting diode LED3. A second initialization transistor T7 of the third pixel circuit PC3 may be connected between a second-second initialization voltage line VAL2 and an anode of the third light emitting diode LED3 and may receive a second initialization control signal GB. The third pixel P3 may emit light of a third color different from the first color and the second color. For example, the third color light may be blue light.

[0083] A 2-1 initialization voltage Vaint1 may be applied to the 2-1 initialization voltage line VAL1. A 2-2 initialization voltage Vaint2 may be applied to the 2-2 initialization voltage line VAL2. The 2-1 initialization voltage Vaint1 may have a lower level than the 2-2 initialization voltage Vaint2. In some embodiments, the 2-1 initialization voltage Vaint1 may have a similar level to the 2-2 initialization voltage Vaint2.

[0084] A first pixel circuit PC1 of the first pixel P1 may be connected to a second-first initialization voltage line VAL1, which receives a second-first initialization voltage Vaint1. The first pixel circuit PC1 may be electrically connected to a first light emitting diode OLED1 that emits light of a first color. A second pixel circuit PC2 of the second pixel P2 may be connected to a second initialization voltage line VAL2, which receives a second-second initialization voltage Vaint2. The second pixel circuit PC2 may be electrically connected to a second light emitting diode LED2 that emits light of a second color. A third pixel circuit PC3 of the third pixel P3 may be connected to a second initialization voltage line VAL2, which receives a second-second initialization voltage Vaint2. The third pixel circuit PC3 may be electrically connected to a third light emitting diode LED3 that emits light of a third color. That is, the initialization voltages Vaint1 and Vaint2 may be provided differently depending on the type of pixel.

[0085] 4 exemplarily illustrates that the first pixel circuit PC1 is connected to the first initialization voltage line VAL1, and the second pixel circuit PC2 and the third pixel circuit PC3 are connected to the second initialization voltage line VAL2, but the initialization voltages provided to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 according to an embodiment of the present invention are not limited thereto. For example, the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may be respectively connected to different initialization voltage lines and provided with different initialization voltages.

[0086] 5 is a plan view schematically illustrating a portion of wiring arranged in a display area of ​​a display device according to an embodiment of the present invention. Pixel circuits PC may be arranged in a first direction (e.g., ±x direction) and a second direction (e.g., ±y direction) in the display area DA, and FIG. 5 illustrates pixel circuits PC arranged in the same row, e.g., the i-th row.

[0087] The pixel circuits PC may be electrically connected to the light emitting diodes, respectively. For convenience of explanation, the pixel circuits PC electrically connected to the first, second, and third light emitting diodes emitting light of different colors will be referred to as first, second, and third pixel circuits PC1, PC2, and PC3.

[0088] The first pixel circuit PC1 may be electrically connected to a first light emitting diode emitting light of a first color, the second pixel circuit PC2 may be electrically connected to a second light emitting diode emitting light of a second color, and the third pixel circuit PC3 may be electrically connected to a third light emitting diode emitting light of a third color. In some embodiments, the first color, the second color, and the third color may be lights of different colors and may be selected from red, green, and blue.

[0089] The first to third pixel circuits PC1, PC2, and PC3 may be repeatedly arranged along a first direction (e.g., ±x direction). The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 are arranged in this order along the first direction (e.g., ±x direction), but the separation distance between the second pixel circuit PC2 and the third pixel circuit PC3 is longer than the separation distance between the second pixel circuit PC2 and the first pixel circuit PC1.

[0090] In the display area DA, lines electrically connected to the pixel circuits PC, for example, first conductive lines (hereinafter referred to as horizontal conductive lines) extending along a first direction (e.g., ±x direction) and second conductive lines (hereinafter referred to as vertical conductive lines) extending along a second direction (e.g., ±y direction), may be arranged.

[0091] The horizontal conductive lines extending along the first direction (e.g., ±x direction) may include a first initialization horizontal voltage line HVIL, a first initialization control line GIL, a scan line GWL, a compensation scan line GCL, an emission control line EML, a repair line RL, a second initialization control line GBL, a bias voltage line VOL, and a second initialization horizontal voltage line HVAL. The second initialization horizontal voltage line HVAL may include a 2-1 initialization horizontal voltage line HVAL1 and a 2-2 initialization horizontal voltage line HVAL2.

[0092] The vertical conductive lines extending along the second direction (e.g., ±y direction) may include a first initialization vertical voltage line VVIL, a common voltage line VSL providing the second power supply voltage ELVSS (FIG. 3), and a second initialization vertical voltage line VVAL. The second initialization vertical voltage line VVAL may include a 2-1 initialization vertical voltage line VVAL1 and a 2-2 initialization vertical voltage line VVAL2.

[0093] The first initialization vertical voltage line VVIL and the first initialization horizontal voltage line HVIL, which provide the first initialization voltage Vint, may be electrically connected in the display area DA. The second-first initialization horizontal voltage line HVAL1 and the second-first initialization vertical voltage line VVAL1, which provide the second-first initialization voltage Vaint1 to the first pixel circuit PC1, may be electrically connected in the display area DA. The second-second initialization vertical voltage line VVAL2 and the second-second initialization horizontal voltage line HVAL2, which provide the second-second initialization voltage Vaint2 to the second pixel circuit PC2 and the third pixel circuit PC3, may be electrically connected in the display area DA.

[0094] 5 illustrates a state in which the second pixel circuit PC2 and the third pixel circuit PC3 are electrically connected to the same voltage line, for example, the 2-2 initialization vertical voltage line VVAL2 and / or the 2-2 initialization horizontal voltage line HVAL2, but the present invention is not limited thereto. In another embodiment, the horizontal and vertical voltage lines for applying the second initialization voltage to the second pixel circuit PC2 and the horizontal and vertical voltage lines for applying the second initialization voltage to the third pixel circuit PC2 may be independent of each other.

[0095] FIG. 6 is a cross-sectional view showing a part of a display area of ​​a display device according to an embodiment of the present invention.

[0096] Referring to FIG. 6, pixel circuits PC may be arranged on a substrate 100, and light emitting diodes LED may be arranged on the pixel circuits PC.

[0097] The substrate 100 may include glass, ceramic, metal, plastic, or any other flexible or bendable material. If the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate, and cellulose acetate propionate (CAP).

[0098] The substrate 100 may have a single-layer or multi-layer structure of the above materials, and in the case of a multi-layer structure, may further include an inorganic layer. For example, the substrate 100 may include a first organic base layer, a first inorganic barrier layer, a second organic base layer, and a second inorganic barrier layer. The first organic base layer and the second organic base layer may each include a polymer resin. The first inorganic barrier layer and the second inorganic barrier layer are barrier layers that prevent the penetration of external foreign substances and may be single-layer or multi-layer structures including inorganic insulators such as silicon nitride and / or silicon oxide.

[0099] A lower metal layer BML may be disposed on the substrate 100. The lower metal layer BML may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In some embodiments, the lower metal layer BML may be a single layer of molybdenum, a bilayer structure in which a molybdenum layer and a titanium layer are stacked, or a trilayer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0100] The lower metal layer BML may have a constant voltage level. For example, the lower metal layer BML may be electrically connected to the driving voltage line PL described with reference to FIG. 3 and have the same voltage level (e.g., driving voltage ELVDD, FIG. 3) as the driving voltage line PL. The lower metal layer BML may prevent negative charges from accumulating under the semiconductor layer (hereinafter referred to as the first semiconductor layer or driving semiconductor layer, A1) of the driving transistor T1, thereby preventing or minimizing the problem of image retention due to negative charges. When viewed perpendicularly to the top surface of the substrate 100, the lower metal layer BML may entirely overlap the channel region C1 of the driving semiconductor layer A1 of the driving transistor T1.

[0101] The buffer layer 111 may be disposed on the lower metal layer BML. The buffer layer 111 may be an inorganic insulating layer containing an inorganic insulating material such as silicon nitride and / or silicon oxide, and may have a single-layer or multi-layer structure containing the aforementioned materials.

[0102] A transistor including a silicon semiconductor layer may be disposed on the buffer layer 111. In this regard, Figure 6 illustrates a driving semiconductor layer A1 of the driving transistor T1, which corresponds to a part of the first silicon semiconductor pattern 1110. The driving semiconductor layer A1 includes a channel region C1 and impurity regions doped with impurities disposed on both sides of the channel region C1. In this regard, Figure 4 illustrates a first region B1, which is one of the impurity regions disposed on one side of the channel region C1.

[0103] The first gate insulating layer 112 may be disposed on the first silicon semiconductor pattern 1110, for example, the driving semiconductor layer A1. The first gate insulating layer 112 may be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0104] The first conductive pattern 1210 may be disposed on the first gate insulating layer 112. The first conductive pattern 1210 may include a driving gate electrode G1 and / or a lower electrode CE1 of the first capacitor Cst. The driving gate electrode G1 of the first conductive pattern 1210 may perform the function of the lower electrode CE1, or the lower electrode CE1 may perform the function of the driving gate electrode G1. In other words, the driving gate electrode G1 may be integrally formed with the lower electrode CE1.

[0105] The first conductive pattern 1210, e.g., the drive gate electrode G1 and / or the lower electrode CE1 of the first capacitor Cst, may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers including the above materials. In some embodiments, the drive gate electrode G1 and / or the lower electrode CE1 of the first capacitor Cst may include a single layer of molybdenum.

[0106] The second gate insulating layer 113 may be disposed on the driving gate electrode G1 and / or the bottom electrode CE1 of the first capacitor Cst. The second gate insulating layer 113 may be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0107] Another conductive pattern (hereinafter referred to as a third conductive pattern 1310) may be disposed on the second gate insulating layer 113. The third conductive pattern 1310 may include an upper electrode CE2 of the first capacitor Cst. The third conductive pattern 1310, for example, the upper electrode CE2 of the first capacitor Cst, may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers including the above-mentioned materials. In some embodiments, the upper electrode CE2 may include the same material as the lower electrode CE1 and / or the lower metal layer BML.

[0108] The upper electrode CE2 may overlap the drive gate electrode G1 and / or the lower electrode CE1. The upper electrode CE2 may include an opening 1310OP so that the first connecting electrode 1630, which electrically connects the drive gate electrode G1 of the drive transistor T1 and the compensation semiconductor layer A3 of the compensation transistor T3, is connected to the drive gate electrode G1. The opening 1310OP may overlap a portion of the drive gate electrode G1.

[0109] The first interlayer insulating layer 114 may be disposed on the upper electrode CE2. The first interlayer insulating layer 114 may be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0110] An oxide semiconductor pattern 1410 may be disposed on the first interlayer insulating layer 114. In this regard, Figure 6 illustrates a compensation semiconductor layer A3 of the compensation transistor T3, which corresponds to a part of the oxide semiconductor pattern 1410. The oxide semiconductor pattern 1410 may include ITZO (InSnZnO), IGZO (InGaZnO), or the like.

[0111] The compensation semiconductor layer A3 includes a channel region C3 and conductive regions disposed on both sides of the channel region C3, and FIG. 6 illustrates one region B3 of the conductive regions disposed on one side of the channel region C3. The compensation semiconductor layer A3 and the driving semiconductor layer A1 may be disposed on different layers. For example, the driving semiconductor layer A1 may be disposed on the buffer layer 111, and the compensation semiconductor layer A3 may be disposed on the first interlayer insulating layer 114. In other words, the vertical distance from the substrate 100 to the compensation semiconductor layer A3 is longer than the vertical distance from the substrate 100 to the driving semiconductor layer A1.

[0112] The third gate electrode G3 may be disposed below and / or above the compensation semiconductor layer A3. In one embodiment, FIG. 4 illustrates the third gate electrode G3 including a lower compensation gate electrode G3a disposed below the compensation semiconductor layer A3 and an upper compensation gate electrode G3b disposed on the compensation semiconductor layer A3. In other embodiments, either the lower compensation gate electrode G3a or the upper compensation gate electrode G3b may be omitted.

[0113] The lower compensation gate electrode G3a may include the same material as the upper electrode CE2 and may be located on the same layer (e.g., the second gate insulating layer 113). The upper compensation gate electrode G3b may be disposed on the compensation semiconductor layer A3 with the third gate insulating layer 115 sandwiched therebetween. The upper compensation gate electrode G3b may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers including the above-mentioned materials.

[0114] 6 illustrates the third gate insulating layer 115 being disposed only between the upper compensation gate electrode G3b and the compensation semiconductor layer A3, but the present invention is not limited thereto. In another embodiment, the third gate insulating layer 115 may be formed to entirely cover the substrate 100, similar to other insulating layers, for example, the first gate insulating layer 112. The third gate insulating layer 115 may be an inorganic insulating layer containing an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure containing the aforementioned materials.

[0115] The second interlayer insulating layer 116 may be disposed on the upper compensation gate electrode G3b. The second interlayer insulating layer 116 may be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0116] The first connecting electrode 1630 and the compensation scan line GCL may be disposed on the second interlayer insulating layer 116. The first connecting electrode 1630 and the compensation scan line GCL may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers including the above materials. In one embodiment, the first connecting electrode 1630 and the compensation scan line GCL may have a three-layer structure of aluminum layer / titanium layer / aluminum layer. The compensation scan line GCL may be electrically connected to the upper compensation gate electrode G3b through a contact hole penetrating the second interlayer insulating layer 116.

[0117] The first organic insulating layer 121 may be formed on the first connecting electrodes 1630 and the compensation scan lines GCL. The first organic insulating layer 121 may include an organic material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0118] The driving voltage line PL may be disposed on the first organic insulating layer 121. The driving voltage line PL may overlap the driving transistor T1 and the first capacitor Cst. In some embodiments, the driving voltage line PL may overlap the compensation transistor T3. The driving voltage line PL may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers including the above materials. In one embodiment, the driving voltage line PL may have a three-layer structure of aluminum layer / titanium layer / aluminum layer.

[0119] The second organic insulating layer 123 may be disposed on the driving voltage line PL. The second organic insulating layer 123 may include an organic material such as BCB (Benzocyclobutene), polyimide, or HMDSO (hexamethyldisiloxane).

[0120] The light emitting diode LED may be formed on the second organic insulating layer 123. The light emitting diode LED may include a pixel electrode 210, an intermediate layer 220, and a counter electrode 230 on the second organic insulating layer 123.

[0121] The edge of the pixel electrode 210 may be covered by the bank layer 130, and an inner portion of the pixel electrode 210 may overlap the intermediate layer 220 through an opening 130OP of the bank layer 130. The pixel electrode 210 may be formed for each light emitting diode LED, whereas the counter electrode 230 may be formed corresponding to a plurality of light emitting diodes LED. In other words, a plurality of light emitting diodes LED may share the counter electrode 230, and the stacked structure of the pixel electrode 210, the intermediate layer 220, and the counter electrode 230 may correspond to the light emitting diode LED.

[0122] The intermediate layer 220 may include an emissive layer. In some embodiments, the intermediate layer 220 may further include an emissive layer and a functional layer. The functional layer may include a hole injection layer (HIL), a hole injection layer (HIL), an electron transport layer (ETL), and / or an electron injection layer (EIL). In some other embodiments, the intermediate layer 220 may include a first stack including an emissive layer and a functional layer, a second stack including an emissive layer and a functional layer, and a charge generation layer between the first and second stacks. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. The negative charge generation layer and the positive charge generation layer may further increase the luminous efficiency of a tandem light emitting diode (LED) having multiple emissive layers.

[0123] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metal material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metal material.

[0124] An encapsulation layer 300 may be disposed on the light-emitting diode LED. The encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 6 illustrates that, in one embodiment, the encapsulation layer 300 includes a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include silicon oxide, silicon nitride, and / or silicon oxynitride, and the organic encapsulation layer 320 may include an organic insulator.

[0125] 7 is a plan view illustrating first to third pixel circuits of a display device according to an embodiment of the present invention, in which a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3 are arranged along the i-th row.

[0126] 7, the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may each include a plurality of transistors and capacitors. In some embodiments, FIG. 7 illustrates that the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 each include the eight transistors T1, T2, T3, T4, T5, T6, T7, and T8 described above with reference to 3 and a first capacitor Cst.

[0127] The driving transistor T1 may overlap the first capacitor Cst. The switching transistors (e.g., T2, T3, T4, T5, T6, T7, and T8) may be arranged above and / or below the driving transistor T1 and / or the first capacitor Cst in a planar view. In one embodiment, FIG. 7 illustrates that the data write transistor T2, the compensation transistor T3, and the first initialization transistor T4 are arranged above (e.g., in the +y direction) the driving transistor T1 and / or the first capacitor Cst in a planar view. The operation control transistor T5, the light-emitting control transistor T6, the second initialization transistor T7, and the bias transistor T8 may be arranged below (e.g., in the -y direction) the driving transistor T1 and / or the first capacitor Cst in a planar view.

[0128] The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 are arranged along a first direction, and a first separation distance between the second pixel circuit PC2 and the third pixel circuit PC3 is longer than a second separation distance between the first pixel circuit PC1 and the second pixel circuit PC2. A vertical voltage line VCL may be disposed in a space (hereinafter referred to as an isolation space, IVA) between the second pixel circuit PC2 and the third pixel circuit PC3, which has the first separation distance. The vertical voltage line VCL shown in FIG. 6 may be the first initialization vertical voltage line VVIL, the common voltage line VSL, the 2-1st initialization vertical voltage line VVAL1, and / or the 2-2nd initialization vertical voltage line VVAL2 described with reference to FIG. 5.

[0129] 8 to 18 are plan views showing processes for forming the first to third pixel circuits shown in FIG.

[0130] 8, a lower metal layer BML may be disposed on a substrate. The lower metal layer BML may include main portions BMLc corresponding to the first to third pixel circuits PC1, PC2, and PC3, respectively. The lower metal layer BML may include first branch portions BMLa connecting the main portions BMLc along a first direction (e.g., ±x direction) and second branch portions BMLb connecting the main portions BMLc arranged in pixel circuits arranged in different rows along a second direction (e.g., ±y direction). The main portions BMLc, the first branch portions BMLa, and the second branch portions BMLb may be integrally connected.

[0131] The lower metal layer BML is electrically connected to the driving voltage line PL (FIG. 3) and may have the same voltage level as the driving voltage line PL (FIG. 17) described below.

[0132] The lower metal layer BML may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In some embodiments, the lower metal layer BML may be a single layer of molybdenum, a bilayer structure in which a molybdenum layer and a titanium layer are stacked, or a trilayer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0133] 6 and 9, a buffer layer 111 (FIG. 4) may be disposed on the lower metal layer BML, and a silicon semiconductor layer 1100 may be disposed on the buffer layer 111 (FIG. 4). The silicon semiconductor layer 1100 may include a first silicon semiconductor pattern 1110 and a second silicon semiconductor pattern 1120.

[0134] The first silicon semiconductor patterns 1110 and the second silicon semiconductor patterns 1120 may be arranged corresponding to the first to third pixel circuits PC1, PC2, and PC3, respectively. The first silicon semiconductor patterns 1110 arranged in the first to third pixel circuits PC1, PC2, and PC3, respectively, may be separated and spaced apart from each other. The first silicon semiconductor patterns 1110 and the second silicon semiconductor patterns 1120 corresponding to the same pixel circuit may also be spaced apart from each other, but the present invention is not limited thereto. In another embodiment, the first silicon semiconductor patterns 1110 and the second silicon semiconductor patterns 1120 corresponding to the same pixel circuit may be integrally connected.

[0135] The first silicon semiconductor pattern 1110 may include a driving semiconductor layer A1 of the driving transistor T1 (FIG. 7), a semiconductor layer of the data write transistor T2 (FIG. 7) (hereinafter referred to as a data write semiconductor layer A2), a semiconductor layer of the operation control transistor T5 (FIG. 7) (hereinafter referred to as an operation control semiconductor layer A5), a semiconductor layer of the light-emitting control transistor T6 (FIG. 7) (hereinafter referred to as a light-emitting control semiconductor layer A6), and a semiconductor layer of the second initialization transistor T7 (FIG. 7) (hereinafter referred to as a second initialization semiconductor layer A7), all of which are described with reference to FIG. 7. The second silicon semiconductor pattern 1120 may include a semiconductor layer of the bias transistor T8 (FIG. 7) (hereinafter referred to as a bias semiconductor layer A8).

[0136] The first silicon semiconductor pattern 1110 and the second silicon semiconductor pattern 1120 may include amorphous silicon or polysilicon. For example, the first silicon semiconductor pattern 1110 and the second silicon semiconductor pattern 1120 may include polysilicon crystallized at a low temperature.

[0137] 6 and 10, a first gate insulating layer 112 (FIG. 6) may be disposed on a silicon semiconductor layer 1100 (FIG. 9), and a first conductive layer 1200 may be disposed on the first gate insulating layer 112 (FIG. 6). The first conductive layer 1200 may include a first conductive pattern 1210, a second conductive pattern 1220, an emission control line EML, a second initialization control line GBL, and a second-2nd initialization horizontal voltage line HVAL2.

[0138] The first conductive pattern 1210, the second conductive pattern 1220, the light emitting control line EML, the second initialization control line GBL, and the second-second horizontal initialization voltage line HVAL2 may include the same material. The first conductive pattern 1210, the second conductive pattern 1220, the light emitting control line EML, the second initialization control line GBL, and the second-second horizontal initialization voltage line HVAL2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers including the above-mentioned materials.

[0139] Referring to FIG. 11, the first conductive pattern 1210, the second conductive pattern 1220, the emission control line EML, and the second initialization control line GBL may each include a gate electrode overlapping the first silicon semiconductor pattern 1110 and / or the second silicon semiconductor pattern 1120.

[0140] The first conductive pattern 1210 may be disposed in each of the first to third pixel circuits PC1, PC2, and PC3 and may have an isolated shape. The first conductive pattern 1210 may include a driving gate electrode G1 of the driving transistor T1. The driving semiconductor layer A1 may include a channel region overlapping the first conductive pattern 1210, which is the driving gate electrode G1, and source and drain regions disposed on both sides of the channel region. Referring to FIGS. 8 and 11, the channel region of the driving semiconductor layer A1 may overlap a portion (e.g., the main portion BMLc) of the lower metal layer BML. The channel region of the driving semiconductor layer A1 of each of the first and second pixel circuits PC1 and PC2 may have a shape with multiple bends (e.g., an omega shape). Considering the efficiency of the third light emitting diode electrically connected to the third pixel circuit PC3, the channel region of the driving semiconductor layer A1 of the third pixel circuit PC3 may have a linear shape.

[0141] The fact that the separation distance between the second pixel circuit PC2 and the third pixel circuit PC3 is longer than the separation distance between the second pixel circuit PC2 and the first pixel circuit PC1 can be seen from the fact that the separation distance between the drive transistor T1 of the second pixel circuit PC2 and the drive transistor T1 of the third pixel circuit PC3 is longer than the separation distance between the drive transistor T1 of the second pixel circuit PC2 and the drive transistor T1 of the first pixel circuit PC1. For example, this can be seen from the fact that the first separation distance DS1 between the channel region of the drive transistor T1 of the second pixel circuit PC2 and the channel region of the drive transistor T1 of the third pixel circuit PC3, measured along a first direction (e.g., the ±x direction), is longer than the second separation distance DS2 between the channel region of the drive transistor T1 of the second pixel circuit PC2 and the channel region of the drive transistor T1 of the first pixel circuit PC1. In other words, it can be seen that the first separation distance DS1 between the drive gate electrode G1 of the drive transistor T1 of the second pixel circuit PC2 and the drive gate electrode G1 of the drive transistor T1 of the third pixel circuit PC3 measured along the first direction (e.g., the ±x direction) is longer than the second separation distance DS2 between the drive gate electrode G1 of the drive transistor T1 of the second pixel circuit PC2 and the drive gate electrode G1 of the drive transistor T1 of the first pixel circuit PC1.

[0142] In some embodiments, the first conductive pattern 1210 may include the bottom electrode CE1 of the first capacitor Cst (FIG. 3). The first conductive pattern 1210 may be the driving gate electrode G1 and / or the bottom electrode CE1 of the first capacitor Cst (FIG. 3).

[0143] The second conductive patterns 1220 may be arranged in the first, second, and third pixel circuits PC1, PC2, and CP3, respectively, and may have an isolated shape. The second conductive patterns 1220 may include the second gate electrode G2 of the data write transistor T2. The data write semiconductor layer a2 may include a channel region overlapping the second gate electrode G2 of the data write transistor T2, and source and drain regions arranged on both sides of the channel region.

[0144] The emission control line EML may extend along a first direction (e.g., ±x direction) to pass through the first to third pixel circuits PC1, PC2, and CP3. The emission control line EML may include an operation control gate electrode G5 of the operation control transistor T5 and an emission control gate electrode G6 of the emission control transistor T6. The operation control semiconductor layer A5 may include a channel region overlapping the operation control gate electrode G5, and source and drain regions disposed on both sides of the channel region. The emission control semiconductor layer A6 may include a channel region overlapping the emission control gate electrode G6, and source and drain regions disposed on both sides of the channel region.

[0145] The second initialization control line GBL may extend along a first direction (e.g., ±x direction) to pass through the first to third pixel circuits PC1, PC2, and CP3. The second initialization control line GBL may include a second initialization gate electrode G7 of the second initialization transistor T7 and a bias gate electrode G8 of the bias transistor T8. The second initialization semiconductor layer A7 may include a channel region overlapping the second initialization gate electrode G7, and source and drain regions disposed on both sides of the channel region. The bias semiconductor layer A8 may include a channel region overlapping the bias gate electrode G8, and source and drain regions disposed on both sides of the channel region.

[0146] 6, the second gate insulating layer 113 (FIG. 4) may be disposed on the first conductive layer 1200 described in FIG. 11. Then, the second conductive layer 1300 may be disposed on the second gate insulating layer 113 (FIG. 4) as shown in FIG. 12. The second conductive layer 1300 may include a third conductive pattern 1310, a fourth conductive pattern 1320, a fifth conductive pattern 1330, and a sub-bridge pattern 1340.

[0147] The third conductive pattern 1310, the fourth conductive pattern 1320, and the fifth conductive pattern 1330 may include the same material. The third conductive pattern 1310, the fourth conductive pattern 1320, the fifth conductive pattern 1330, and the sub-bridge pattern 1340 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers including the aforementioned materials.

[0148] 11 and 12, the third conductive pattern 1310 may be disposed to overlap the first conductive pattern 1210. The third conductive pattern 1310 may extend along a first direction (e.g., ±x direction) to pass through the first to third pixel circuits PC1, PC2, and CP3 as a horizontal driving voltage line having a driving voltage level.

[0149] In one embodiment, the third conductive pattern 1310 may include a first portion 1311 overlapping the first conductive pattern 1210 arranged in each of the first to third pixel circuits PC1, PC2, and PC3, and a second portion 1312 extending along a first direction (e.g., the x-direction) to connect the first portions 1311 arranged in each of the first to third pixel circuits PC1, PC2, and PC3.

[0150] The first conductive patterns 1210 disposed in the first, second, and third pixel circuits PC1, PC2, and PC3 may correspond to the lower electrodes CE1 of the first capacitors Cst, and the first portions 1311 of the third conductive patterns 1310 disposed in the first, second, and third pixel circuits PC1, PC2, and PC3 may correspond to the upper electrodes CE2 of the first capacitors Cst.

[0151] 8 and 12, the third conductive pattern 1310 may overlap the lower metal layer BML. A first portion 1311 of the third conductive pattern 1310 may overlap a main portion BMLc of the lower metal layer BML, and a second portion 1312 of the third conductive pattern 1310 may overlap a first branch portion BMLa of the lower metal layer BML.

[0152] By arranging the third conductive pattern 1310 and the lower metal layer BML, which have the same voltage level, to overlap each other, coupling between the driving transistor T1 and its surrounding components (wiring or electrodes) can be prevented, and the transistors, voltage lines, and signal lines of the first to third pixel circuits PC1, PC2, and PC3 can be efficiently arranged in a limited space, thereby improving space efficiency (e.g., improving integration). The third conductive pattern 1310 may have a closed opening 1310OP.

[0153] The fourth conductive pattern 1320 and the fifth conductive pattern 1330 may be disposed in the first to third pixel circuits PC1, PC2, and PC3, respectively. The fourth conductive pattern 1320 and the fifth conductive pattern 1330 may have an isolated shape.

[0154] The fourth conductive pattern 1320 may correspond to a lower compensation gate electrode G3a of a compensation transistor T3, which will be described later, and the fifth conductive pattern 1330 may correspond to a lower first initialization gate electrode G4a of a first initialization transistor T4, which will be described later.

[0155] The sub-bridge pattern 1340 may be disposed in the separation space IVA between the second pixel circuit PC2 and the third pixel circuit PC3. The sub-bridge pattern 1340 may electrically connect the vertical voltage line VCL (FIG. 7) to a horizontal voltage line (described later). However, the sub-bridge pattern 1340 is not necessarily disposed in all separation spaces IVA disposed in the display area DA (FIG. 1). If the vertical voltage line VCL (FIG. 7) is the first initialization vertical voltage line VVIL (FIG. 5), the sub-bridge pattern 1340 may be disposed in the separation space IVA as shown in FIG. 12. If the vertical voltage line VCL (FIG. 7) is the common voltage line VSL (FIG. 5) or the initialization vertical voltage line VVAL, the sub-bridge pattern 1340 is not disposed in the separation space IVA. In other words, whether the sub-bridge pattern 1340 is disposed in the separation space IVA may be determined depending on the layer in which the horizontal voltage line to which the corresponding vertical voltage line VCL (FIG. 7) is electrically connected is disposed.

[0156] 6 and 13, the first interlayer insulating layer 114 (FIG. 6) may be disposed on the second conductive layer 1300 described with reference to FIG. 12. Then, the oxide semiconductor layer 1400 may be disposed on the first interlayer insulating layer 114 (FIG. 6). The oxide semiconductor layer 1400 may include an oxide semiconductor pattern 1410.

[0157] 13, the oxide semiconductor pattern 1410 may have a folded shape. For example, the oxide semiconductor pattern 1410 may include a portion corresponding to the compensation semiconductor layer A3 extending along a first direction (e.g., ±x direction) to overlap with the fourth conductive pattern 1320, and a portion corresponding to the first initialization semiconductor layer A4 extending along a second direction (e.g., ±y direction) to overlap with the fifth conductive pattern 1330.

[0158] Specifically, the oxide semiconductor pattern 1410 may include a first portion 1411, a second portion 1412 (or a first extension region), a third portion 1413, and a fourth portion 1414 (or a second extension region). The first portion 1411, the second portion 1412, the third portion 1413, and the fourth portion 1414 may be integrally connected.

[0159] The oxide semiconductor pattern 1410 may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, etc. Oxide semiconductors have a wide band gap (approximately 3.1 eV), high carrier mobility, and low leakage current, so that voltage drop is not large even with long driving times, and brightness change due to voltage drop is not large even with low frequency driving.

[0160] 14, a third conductive layer 1500 may be disposed on the structure described with reference to FIG 13. The third conductive layer 1500 may include a sixth conductive pattern 1510, a seventh conductive pattern 1520, a repair line RL, and a 2-1 st initialization horizontal voltage line HVAL1.

[0161] The sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL1 may include the same material. The sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL1 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers including the above-mentioned materials. In one embodiment, the sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL1 may have a three-layer structure of aluminum layer / titanium layer / aluminum layer.

[0162] The sixth conductive pattern 1510 and the seventh conductive pattern 1520 may be disposed in the first to third pixel circuits PC1, PC2, and PC3, respectively. The sixth conductive pattern 1510 and the seventh conductive pattern 1520 may have an isolated shape.

[0163] 15, the sixth conductive pattern 1510 and the seventh conductive pattern 1520 may each include a gate electrode overlapping the oxide semiconductor pattern 1410. The sixth conductive pattern 1510 may include an upper compensation gate electrode G3b overlapping a portion of the oxide semiconductor pattern 1410, for example, the compensation semiconductor layer A3. The seventh conductive pattern 1520 may include an upper first initialization gate electrode G4b overlapping a portion of the oxide semiconductor pattern 1410, for example, the first initialization semiconductor layer A4.

[0164] The compensation semiconductor layer A3 disposed in each of the first to third pixel circuits PC1, PC2, and PC3 may include a channel region overlapping the fourth conductive pattern 1320 disposed below the compensation semiconductor layer A3 and the sixth conductive pattern 1510 disposed on the compensation semiconductor layer A3, and source and drain regions disposed on both sides of the channel region. The first initialization semiconductor layer A4 disposed in each of the first to third pixel circuits PC1, PC2, and PC3 may include a channel region overlapping the fifth conductive pattern 1330 disposed below the first initialization semiconductor layer A4 and the seventh conductive pattern 1520 disposed on the first initialization semiconductor layer A4, and source and drain regions disposed on both sides of the channel region.

[0165] The fourth conductive pattern 1320 and the sixth conductive pattern 1510 may correspond to the lower and upper compensation gate electrodes G3a and G3b of the compensation transistor T3, respectively. The fifth conductive pattern 1330 and the seventh conductive pattern 1520 may correspond to the lower and upper first initialization gate electrodes G4a and G4b of the first initialization transistor T4, respectively.

[0166] 15 illustrates that the compensation transistor T3 includes a dual gate electrode of a lower compensation gate electrode G3a and an upper compensation gate electrode G3b, and that the first initialization transistor T4 includes a dual gate electrode of a lower first initialization gate electrode G4a and an upper first initialization gate electrode G4b, but the present invention is not limited thereto. In another embodiment, the compensation transistor T3 may include one of the lower compensation gate electrode G3a and the upper compensation gate electrode G3b, and the first initialization transistor T4 may include one of the lower first initialization gate electrode G4a and the upper first initialization gate electrode G4b.

[0167] The 2-1st initialization horizontal voltage line HVAL1 may be arranged on the same layer as the sixth conductive pattern 1510 which is the gate electrode of the compensation transistor T3 (e.g., the upper compensation gate electrode G3b), the seventh conductive pattern 1520 which is the gate electrode of the first initialization transistor T4 (e.g., the upper first initialization gate electrode G4b), and the repair line RL. For example, the 2-1st initialization horizontal voltage line HVAL1, the sixth conductive pattern 1510, the seventh conductive pattern 1520, and the repair line RL may each be arranged on the third gate insulating layer 115 (FIG. 6).

[0168] 6, the third gate insulating layers 115 (FIG. 6) disposed below the sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL(R) may be separated from one another, but the present invention is not limited thereto. In another embodiment, the third gate insulating layers 115 (FIG. 6) disposed below the sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL(R) may be integrally connected.

[0169] The 2-1st initialization horizontal voltage line HVAL1 and the 2-2nd initialization horizontal voltage line HVAL2 (FIG. 11) may overlap each other. The 2-2nd initialization horizontal voltage line HVAL2 (FIG. 11) and the 2-1st initialization horizontal voltage line HVAL1 may have a constant voltage level. For example, the 2-2nd initialization horizontal voltage line HVAL2 (FIG. 11) and the 2-1st initialization horizontal voltage line HVAL1 may have the same or similar voltage levels. By overlapping the 2-2nd initialization horizontal voltage line HVAL2 (FIG. 11) and the 2-1st initialization horizontal voltage line HVAL1 having the same or similar voltage levels, the generation of parasitic capacitance between the electrodes, voltage lines, and / or signal lines of the transistors of the first to third pixel circuits PC1, PC2, and PC3 in a limited space can be minimized and the space can be efficiently utilized (e.g., integration density can be improved).

[0170] 6 and 16, the second interlayer insulating layer 116 (FIG. 6) may be disposed on the third conductive layer 1500 described with reference to FIG. 15. Then, the fourth conductive layer 1600 may be disposed on the second interlayer insulating layer 116. The fourth conductive layer 1600 may include a voltage transmission line 1610, a first pixel connecting electrode 1620, a first connecting electrode 1630, a second connecting electrode 1640, a third connecting electrode 1650, a fourth connecting electrode 1660, a fifth connecting electrode 1670, a bridge pattern 1680, a first initialization horizontal voltage line HVIL, a first initialization control line GIL, a scan line GWL, a compensation scan line GCL, and a bias voltage line VOL.

[0171] The voltage transmission line 1610, the first pixel connecting electrode 1620, the first connecting electrode 1630, the second connecting electrode 1640, the third connecting electrode 1650, the fourth connecting electrode 1660, the fifth connecting electrode 1670, the bridge pattern 1680, the first initialization horizontal voltage line HVIL, the first initialization control line GIL, the scan line GWL, the compensation scan line GCL, and the bias voltage line VOL may include the same material. The voltage transmission line 1610, the first pixel connecting electrode 1620, the first connecting electrode 1630, the second connecting electrode 1640, the third connecting electrode 1650, the fourth connecting electrode 1660, the fifth connecting electrode 1670, the bridge pattern 1680, the first initialization horizontal voltage line HVIL, the first initialization control line GIL, the scan line GWL, the compensation scan line GCL, and the bias voltage line VOL may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The voltage transmission line 1610 may extend in a first direction (e.g., ±x direction). The voltage transmission line 1610 passes through the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3. The voltage transmission line 1610 may overlap with the repair line RL (FIG. 14).

[0172] In one embodiment, the voltage transmission line 1610 may have a voltage level of the driving voltage ELVDD (FIG. 3). In another embodiment, the voltage transmission line 1610 may be electrically connected to a driving voltage line PL (FIG. 17) described below and may have a voltage level of the driving voltage ELVDD (FIG. 3).

[0173] The voltage transmission wiring 1610 may be electrically connected to the lower metal layer BML (FIG. 8) through the first-1 contact hole CNT1a. The voltage transmission wiring 1610 may be electrically connected to the third conductive pattern 1310 (FIG. 12) through the first-2 contact hole CNT1b. The voltage transmission wiring 1610 may be electrically connected to the first silicon semiconductor pattern 1110 (FIG. 9) through the first-3 contact hole CNT1c. The lower metal layer BML (FIG. 8) may have a voltage level of the driving voltage ELVDD through the connection structure between the voltage transmission wiring 1610 and the lower metal layer BML (FIG. 8) through the first-1 contact hole CNT1a. The voltage transmission wiring 1610 may provide the driving voltage ELVDD to the upper electrode CE2 (FIG. 12) of the first capacitor Cst and the fifth semiconductor layer A5 (FIG. 11) of the operation control transistor T5 through the first-2 contact hole CNT1b and the first-3 contact hole CNT1c.

[0174] The first pixel connecting electrode 1620 may be spaced apart from the voltage transmission line 1610. The first pixel connecting electrode 1620 may be electrically insulated from the voltage transmission line 1610.

[0175] The first pixel connecting electrode 1620 may be disposed on the same layer as the voltage transmission line 1610. The first pixel connecting electrode 1620 may include a 1-1 pixel connecting electrode 1620a, a 1-2 pixel connecting electrode 1620b, and a 1-3 pixel connecting electrode 1620c disposed in the first to third pixel circuits PC1, PC2, and PC3, respectively. The 1-1 pixel connecting electrode 1620a, the 1-2 pixel connecting electrode 1620b, and the 1-3 pixel connecting electrode 1620c may be disposed apart from the voltage transmission line 1610.

[0176] The first pixel connecting electrode 1620 may be electrically connected to the first silicon semiconductor pattern 1110 (FIG. 9) through the second contact hole CNT2. For example, the 1-1 pixel connecting electrode 1620a may be electrically connected to the first silicon semiconductor pattern 1110 (FIG. 9) corresponding to the first pixel circuit PC1 through the second contact hole CNT2. The first pixel connecting electrode 1620 may be electrically connected to the emission control semiconductor layer A6 (FIG. 9) of the emission control transistor T6 (FIG. 11) and / or the second initialization semiconductor layer A7 (FIG. 11) of the second initialization transistor T7, which are formed along the first silicon semiconductor pattern 1110 (FIG. 9).

[0177] The first linking electrode 1630, the second linking electrode 1640, the third linking electrode 1650, the fourth linking electrode 1660, and the fifth linking electrode 1670 may each have an isolated shape. The first linking electrode 1630, the second linking electrode 1640, the third linking electrode 1650, the fourth linking electrode 1660, and the fifth linking electrode 1670 may be disposed in the first to third pixel circuits PC1, PC2, and PC3, respectively.

[0178] The first connecting electrode 1630 may electrically connect the first conductive pattern 1210 (FIG. 10) and the oxide semiconductor pattern 1410 (FIG. 13). The first connecting electrode 1630 may be electrically connected to the first conductive pattern 1210 (FIG. 10) through the 3-1 contact hole CNT3a. The first connecting electrode 1630 may be electrically connected to the oxide semiconductor pattern 1410 (e.g., the compensation semiconductor layer A3 of the compensation transistor T3, FIG. 15) through the 3-2 contact hole CNT3b. The first connecting electrode 1630 may electrically connect the driving gate electrode G1 of the driving transistor T1 (FIG. 11) and the compensation semiconductor layer A3 of the compensation transistor T3 (FIG. 15). The first connecting electrode 1630 may electrically connect the first capacitor Cst (FIG. 11) and the compensation transistor T3 (FIG. 15).

[0179] The first connecting electrode 1630 may overlap a portion of the lower metal layer BML (FIG. 8), for example, the second branch portion BMLb.

[0180] The second connecting electrode 1640 may electrically connect the first silicon semiconductor pattern 1110 (FIG. 9) and the oxide semiconductor pattern 1410 (FIG. 13). The second connecting electrode 1640 may be electrically connected to the first silicon semiconductor pattern 1110 (FIG. 9) through the 4-1 contact hole CNT4a. The second connecting electrode 1640 may be electrically connected to the oxide semiconductor pattern 1410 (FIG. 13) through the 4-2 contact hole CNT4b. The second connecting electrode 1640 may electrically connect the driving semiconductor layer A1 of the driving transistor T1 (FIG. 11) and the compensation semiconductor layer A3 of the compensation transistor T3 (FIG. 15). The second connecting electrode 1640 may electrically connect the emission control semiconductor layer A6 of the emission control transistor T6 (FIG. 11) and the compensation semiconductor layer A3 of the compensation transistor T3 (FIG. 15).

[0181] The third connecting electrode 1650 may be electrically connected to the first silicon semiconductor pattern 1110 (FIG. 9) through the fifth contact hole CNT5. For example, the third connecting electrode 1650 corresponding to the first pixel circuit PC1 may be electrically connected to the first data line DL1 (FIG. 17), which will be described later. That is, the third connecting electrode 1650 corresponding to the first pixel circuit PC1 may transmit a data signal applied to the first data line DL1 (FIG. 17) to the second semiconductor layer A2 (FIG. 11) of the data write transistor T2.

[0182] The fourth connecting electrode 1660 may electrically connect the first silicon semiconductor pattern 1110 (FIG. 9) and the second silicon semiconductor pattern 1120 (FIG. 9). The fourth connecting electrode 1660 may be electrically connected to the first silicon semiconductor pattern 1110 (FIG. 9) through the 6-1 contact hole CNT6a. The fourth connecting electrode 1660 may be electrically connected to the second silicon semiconductor pattern 1120 (FIG. 9) through the 6-2 contact hole CNT6b. The fourth connecting electrode 1660 may electrically connect the operation control semiconductor layer A5 (FIG. 11) of the operation control transistor T5 formed along the first silicon semiconductor pattern 1110 (FIG. 9) and the bias semiconductor layer A8 (FIG. 11) of the bias transistor T8 formed along the second silicon semiconductor pattern 1120 (FIG. 9).

[0183] The fifth connecting electrode 1670 corresponding to the first pixel circuit PC1 may electrically connect the first silicon semiconductor pattern 1110 (FIG. 9) corresponding to the first pixel circuit PC1 to the 2-1st initialization horizontal voltage line HVAL1 (FIG. 15). The fifth connecting electrode 1670 corresponding to the first pixel circuit PC1 may electrically connect the second initialization semiconductor layer A7 (FIG. 11) of the second initialization transistor T7 formed along the first silicon semiconductor pattern 1110 (FIG. 9) to the 2-1st initialization horizontal voltage line HVAL1 (FIG. 15).

[0184] The fifth connecting electrode 1670 corresponding to the first pixel circuit PC1 may be electrically connected to the second initialization semiconductor layer A7 (FIG. 11) of the second initialization transistor T7 corresponding to the first pixel circuit PC1 through the 7-1 contact hole CNT7a and may be electrically connected to the 2-1 initialization horizontal voltage line HVAL1 (FIG. 15) through the 7-2 contact hole CNT7b. The 2-1 initialization horizontal voltage line HVAL1 (FIG. 15) may transmit the 2-1 initialization voltage to the second initialization transistor T7 (FIG. 11) of the first pixel circuit PC1 through the fifth connecting electrode 1670.

[0185] The fifth connecting electrode 1670 corresponding to the second pixel circuit PC2 and the third pixel circuit PC3 may electrically connect the first silicon semiconductor pattern 1110 (FIG. 9) and the 2-2 initialization horizontal voltage line HVAL2 (FIG. 11) corresponding to the second pixel circuit PC2 and the third pixel circuit PC3, respectively. The fifth connecting electrode 1670 corresponding to the second pixel circuit PC2 and the third pixel circuit PC3, respectively, may electrically connect the second initialization semiconductor layer A7 of the second initialization transistor T7 (FIG. 11) and the 2-2 initialization horizontal voltage line HVAL2 (FIG. 11) corresponding to the second pixel circuit PC2 and the third pixel circuit PC3, respectively.

[0186] The fifth connecting electrodes 1670 corresponding to the second pixel circuits PC2 and the third pixel circuits PC3 are electrically connected to the second initialization semiconductor layers A7 (FIG. 11) of the second initialization transistors T7 corresponding to the second pixel circuits PC2 and the third pixel circuits PC3 through the 7-1 contact holes CNT7a. The fifth connecting electrodes 1670 corresponding to the second pixel circuits PC2 and the third pixel circuits PC3 may be electrically connected to the 2-2 initialization horizontal voltage line HVAL2 (FIG. 11) through the 7-2 contact holes CNT7b. The 2-2 initialization horizontal voltage line HVAL2 (FIG. 11) may transmit the 2-2 initialization voltage to the second initialization transistors T7 (FIG. 11) corresponding to the second pixel circuits PC2 and the third pixel circuits PC3 through the fifth connecting electrodes 1670 disposed in the second pixel circuits PC2 and the third pixel circuits PC3. In some embodiments, the 2-1 initialization voltage and the 2-2 initialization voltage may have the same voltage level.

[0187] The bridge pattern 1680 may have an isolated shape. The bridge pattern 1680 may be disposed between the second pixel circuit PC2 and the third pixel circuit PC3. The bridge pattern 1680 may be disposed in the isolation space IVA. The bridge pattern 1680 may be disposed to overlap with a vertical voltage line VCL (FIG. 7) described below. The bridge pattern 1680 may be a connecting electrode that electrically connects the vertical voltage line VCL (FIG. 7) and a horizontal voltage line. For example, the bridge pattern 1680 electrically connected to the vertical voltage line VCL (FIG. 7) may be electrically connected to the first initialization horizontal voltage line HVIL. To this end, one end of the sub-bridge pattern 1340 (FIG. 12) may be connected to the bridge pattern 1680 through the 13-1 contact hole CNT13a, and the other end of the sub-bridge pattern 1340 (FIG. 12) may be connected to the first initialization horizontal voltage line HVIL through the 13-2 contact hole CNT13b.

[0188] The first initialization control line GIL, the scan line GWL, the compensation scan line GCL, the bias voltage line VOL, and the first initialization horizontal voltage line HVIL may extend in a first direction (eg, ±x direction).

[0189] The first initialization control line GIL may be electrically connected to the fifth conductive pattern 1330 (FIG. 15) and the seventh conductive pattern 1520 (FIG. 15) of each of the first to third pixel circuits PC1, PC2, and PC3. The first initialization control line GIL may be electrically connected to the fifth conductive pattern 1330 (FIG. 15) of each of the first to third pixel circuits PC1, PC2, and PC3 through the 8-1 contact hole CNT8a. The first initialization control line GIL may be electrically connected to the seventh conductive pattern 1520 (FIG. 15) of each of the first to third pixel circuits PC1, PC2, and PC3 through the 8-2 contact hole CNT8b. The first initialization control line GIL may provide a first initialization control signal GI (FIG. 3) to the fifth conductive pattern 1330 (FIG. 15), which is the lower first initialization gate electrode G4a of the first initialization transistor T4, and the seventh conductive pattern 1520 (FIG. 15), which is the upper first initialization gate electrode G4b.

[0190] The scan line GWL may be electrically connected to the second conductive pattern 1220 (FIG. 11) of each of the first through third pixel circuits PC1, PC2, and PC3 through the ninth contact hole CNT9. The scan line GWL may provide a scan signal GW (FIG. 3) to the second conductive pattern 1220 (FIG. 11), which is the data write gate electrode G2 (FIG. 11) of the data write transistor T2 (FIG. 11) of each of the first through third pixel circuits PC1, PC2, and PC3.

[0191] The compensation scan line GCL may be electrically connected to the fourth conductive pattern 1320 (FIG. 15) and the sixth conductive pattern 1510 (FIG. 15) of each of the first through third pixel circuits PC1, PC2, and PC3. The compensation scan line GCL may be electrically connected to the fourth conductive pattern 1320 (FIG. 15) of each of the first through third pixel circuits PC1, PC2, and PC3 through the 10-1 contact hole CNT10a. The compensation scan line GCL may be electrically connected to the sixth conductive pattern 1510 (FIG. 15) of each of the first through third pixel circuits PC1, PC2, and PC3 through the 10-2 contact hole CNT10b. The compensation scan line GCL may provide a compensation scan signal GC (FIG. 3) to the fourth conductive pattern 1320 (FIG. 15), which is the lower compensation gate electrode G3a of the compensation transistor T3, and the sixth conductive pattern 1510 (FIG. 15), which is the upper compensation gate electrode G3b.

[0192] The bias voltage line VOL may be electrically connected to the second silicon semiconductor pattern 1120 (FIG. 11) of each of the first through third pixel circuits PC1, PC2, and PC3 through the eleventh contact hole CNT11. The bias voltage line VOL may provide the bias voltage Vobs (FIG. 3) to the bias semiconductor layer A8 (FIG. 11) of the bias transistor T8 of each of the first through third pixel circuits PC1, PC2, and PC3.

[0193] The first initialization horizontal voltage line HVIL may be electrically connected to the oxide semiconductor patterns 1410 (FIG. 15) of the first to third pixel circuits PC1, PC2, and PC3 through the twelfth contact holes CNT12. That is, the first initialization horizontal voltage line HVIL may provide the first initialization voltage Vint (FIG. 3) to the first initialization transistor T4 (FIG. 15) formed along the oxide semiconductor patterns 1410 (FIG. 15).

[0194] 6 and 17, the first organic insulating layer 121 (FIG. 6) may be disposed on the fourth conductive layer 1600, and the fifth conductive layer 1700 may be disposed on the first organic insulating layer 121 (FIG. 6). The fifth conductive layer 1700 may include a second pixel connecting electrode 1710, a driving voltage line PL, a first data line DL1, a second data line DL2, a third data line DL3, and a vertical voltage line VCL.

[0195] 17, the driving voltage line PL, the first data line DL1, the second data line DL2, the third data line DL3, and the vertical voltage line VCL extend along a second direction (e.g., the ±y direction). The driving voltage line PL, the first data line DL1, the second data line DL2, the third data line DL3, the vertical voltage line VCL, and the second pixel connecting electrode 1710 may include the same material.

[0196] The driving voltage line PL, the first data line DL1, the second data line DL2, the third data line DL3, the vertical voltage line VCL, and the second pixel connecting electrode 1710 may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0197] The driving voltage lines PL may be disposed in the first, second, and third pixel circuits PC1, PC2, and PC3, respectively. The driving voltage lines PL corresponding to any one of the first, second, and third pixel circuits PC1, PC2, and PC3 may be electrically connected to the voltage transmission line 1610 (FIG. 16) through a fifteenth contact hole CNT15. ​​The shapes and areas of the driving voltage lines PL disposed in the first, second, and third pixel circuits PC1, PC2, and PC3 may be different from each other.

[0198] The driving voltage line PL disposed in each of the first through third pixel circuits PC1, PC2, and PC3 may overlap the gate electrodes of the compensation transistors T3 of the first through third pixel circuits PC1, PC2, and PC3, for example, the lower compensation gate electrode G3a and the upper compensation gate electrode G3b in FIG. 15, and may also overlap the first connecting electrodes 1630 (FIG. 16) corresponding to the first through third pixel circuits PC1, PC2, and PC3, respectively. This overlapping structure may prevent unwanted parasitic capacitance from affecting the compensation transistors T3 and the first connecting electrodes 1630. As shown in FIG. 17, in a plan view, the first connecting electrode 1630 (FIG. 16) overlaps the second branch portion BMLb of the lower metal layer BML (FIG. 8) and the driving voltage line PL, which have the same constant voltage level (e.g., the driving voltage ELVDD level), thereby more effectively preventing the occurrence of the parasitic capacitance.

[0199] The first, second, and third data lines DL1, DL2, and DL3 may be electrically connected to the data write transistors T2 (FIG. 11) of the first, second, and third pixel circuits PC1, PC2, and PC3, respectively. The first, second, and third data lines DL1, DL2, and DL3 may transmit a data signal Dm (FIG. 3) to the first, second, and third pixel circuits PC1, PC2, and PC3, respectively.

[0200] The first data line DL1 may be electrically connected to the third connecting electrode 1650 (FIG. 16) corresponding to the first pixel circuit PC1 through the sixteenth contact hole CNT16. Similarly, the second data line DL2 may be electrically connected to the third connecting electrode 1650 (FIG. 16) corresponding to the second pixel circuit PC2 through the sixteenth contact hole CNT16, and the third data line DL3 may be electrically connected to the third connecting electrode 1650 (FIG. 16) corresponding to the third pixel circuit PC3 through the sixteenth contact hole CNT16. The third connecting electrode 1650 (FIG. 16) corresponding to each of the first through third pixel circuits PC1, PC2, and PC3 is electrically connected to the first silicon semiconductor pattern 1110 (FIG. 11) of the corresponding pixel circuit, and may provide a data signal Dm (FIG. 3) to the data write transistor T2 (FIG. 11) formed along the first silicon semiconductor pattern 1110 (FIG. 11).

[0201] The shapes of the first data line DL1, the second data line DL2, and the third data line DL3 are different from each other in a plan view. For example, the first data line DL1 and the second data line DL2 pass through the area corresponding to the second pixel circuit PC2 while having different planar shapes from each other. For example, the first data line DL1 and the second data line DL2 may be asymmetric with respect to a virtual line extending in the second direction (e.g., the ±y direction) between the first data line DL1 and the second data line DL2. The planar shape of the third data line DL3 is also different from the planar shapes of the first data line DL1 and the second data line DL2.

[0202] The vertical voltage line VCL may be disposed in the separation space IVA between the second pixel circuit PC2 and the third pixel circuit PC3. For example, the vertical voltage line VCL may be disposed between the second data line DL2 and the driving voltage line PL of the third pixel circuit PC3.

[0203] The vertical voltage line VCL may be electrically connected to horizontal voltage lines extending in a first direction (e.g., ±x direction). In one embodiment, if the vertical voltage line VCL is the first initialization vertical voltage line VVIL (FIG. 5), the vertical voltage line VCL may be electrically connected to the first initialization horizontal voltage line HVIL (FIG. 16). Specifically, the vertical voltage line VCL may be connected to the bridge pattern 1680 (FIG. 16) through the 17th contact hole CNT17, the bridge pattern 1680 (FIG. 16) may be connected to the sub-bridge pattern 1340 (FIG. 12) through the 13-1st contact hole CNT13a (FIG. 16), and the sub-bridge pattern 1340 (FIG. 12) may be electrically connected to the first initialization horizontal voltage line HVIL through the 13-2nd contact hole CNT13b (FIG. 16).

[0204] The second pixel connecting electrode 1710 may be electrically connected to the first pixel connecting electrode 1620 (FIG. 16). For example, the 2-1 pixel connecting electrode 1710a may be electrically connected to the 1-1 pixel connecting electrode 1620a (FIG. 16) through the 14-1 contact hole CNT14a. For example, the 2-2 pixel connecting electrode 1710b may be electrically connected to the 1-2 pixel connecting electrode 1620b (FIG. 16) through the 14-2 contact hole CNT14b. For example, the 2-3 pixel connecting electrode 1710c may be electrically connected to the 2-3 pixel connecting electrode 1620c (see FIG. 13) through the 14-3 contact hole CNT14c.

[0205] A second organic insulating layer 123 (FIG. 6) may be disposed on the structure described with reference to FIG. 17. Then, a pixel electrode as shown in FIG. 18 may be disposed on the second organic insulating layer 123 (FIG. 6).

[0206] 18, a first pixel electrode 210a electrically connected to the first pixel circuit PC1, a second pixel electrode 210b electrically connected to the second pixel circuit PC2, and a third pixel electrode 210c electrically connected to the third pixel circuit PC3 may be spaced apart from one another. In one embodiment, the first pixel electrodes 210a and the second pixel electrodes 210b may be arranged in the same column along a second direction (e.g., the y direction) and may be alternately arranged. The third pixel electrode 210c may be arranged in a column adjacent to the column in which the first pixel electrodes 210a and the second pixel electrodes 210b are arranged.

[0207] The pixel electrodes may be electrically connected to the first through third pixel circuits PC1, PC2, and PC3, respectively, via the second pixel connecting electrode 1710 (FIG. 17) and the first pixel connecting electrode 1620 (FIG. 16). The first pixel electrode 210a may be connected to the 2-1 pixel connecting electrode 1710a (FIG. 17) via the 18th contact hole CNT18, and the 2-1 pixel connecting electrode 1710a (FIG. 17) may be electrically connected to the 1-1 pixel connecting electrode 1620a (FIG. 16) via the 14-1 contact hole CNT14a (FIG. 17). The second pixel electrode 210b may be electrically connected to the 2-2nd pixel connecting electrode 1710b (FIG. 17) through the 19th contact hole CNT19, and the 2-2nd pixel connecting electrode 1710b (FIG. 17) may be electrically connected to the 1-2nd pixel connecting electrode 1620b (FIG. 16) through the 14-2nd contact hole CNT14b (FIG. 17). The third pixel electrode 210c may be electrically connected to the 2-3rd pixel connecting electrode 1710c (FIG. 17) through the 20th contact hole CNT20, and the 2-3rd pixel connecting electrode 1710c may be electrically connected to the 1-3rd pixel connecting electrode 1620c (FIG. 16) through the 14-3rd contact hole CNT14c (FIG. 17).

[0208] 19 and 20 are enlarged plan views each schematically illustrating a portion of a display device according to an embodiment of the present invention. FIG. 21 is a cross-sectional view schematically illustrating a portion of a display device according to an embodiment of the present invention. FIG. 19 is an enlarged view of a region in which the first initialization vertical voltage line VVIL is disposed in the separation space IVA (FIG. 17), and FIG. 20 is an enlarged view of a region in which the 2-1st initialization vertical voltage line VVAL1 is disposed in the separation space IVA (FIG. 17). FIG. 21 is a cross-sectional view taken along line II' in FIG. 7. For convenience of explanation, FIGS. 19 and 20 illustrate only some of the components.

[0209] 19 and 20, an oxide semiconductor pattern 1410 may be disposed in the display area DA (FIG. 1). The oxide semiconductor pattern 1410 may have a folded shape. The oxide semiconductor pattern 1410 may include a first portion 1411, a second portion 1412 (or a first extended region), a third portion 1413, and a fourth portion 1414 (or a second extended region). The first portion 1411, the second portion 1412, the third portion 1413, and the fourth portion 1414 may be integrally connected.

[0210] The first portion 1411 may be a portion disposed at the uppermost end of the oxide semiconductor pattern 1410 based on the second direction (e.g., the y direction). The first portion 1411 may be disposed extending along the first direction (e.g., the ±x direction). The first portion 1411 may be connected to the first initialization horizontal voltage line HVIL to transfer a voltage to the first initialization transistor T4. For example, the first portion 1411 may include a portion corresponding to the source region S4 of the first initialization semiconductor layer A4.

[0211] The second portion 1412 (or the first extension region) may be connected to the first portion 1411 and may be disposed extending along a second direction (e.g., the ±y direction). The second portion 1412 may include a portion corresponding to the first initialization semiconductor layer A4. For example, the second portion 1412 may include portions corresponding to the channel region C4 and the drain region D4 of the first initialization semiconductor layer A4. The second portion 1412 may be a portion extending from the channel region C4 of the first initialization semiconductor layer A4 to the first connecting electrode 1630.

[0212] The third portion 1413 may be connected to the second portion 1412 and may be disposed to extend along a first direction (e.g., the ±x direction). The third portion 1413 may include a portion corresponding to the compensation semiconductor layer A3. For example, the third portion 1413 may include portions corresponding to the source region S3 and the channel region C3 of the compensation semiconductor layer A3. The third portion 1413 may extend from the first connecting electrode 1630 to the drain region D3 of the compensation semiconductor layer A3.

[0213] The fourth portion 1414 (or the second extension region) may be connected to the third portion 1413 and may extend along the second direction (e.g., the ±y direction). The fourth portion 1414 may include a portion corresponding to the drain region D3 of the compensation semiconductor layer A3. The fourth portion 1414 may extend from the drain region D3 of the compensation semiconductor layer A3 to the second connecting electrode 1640 (FIG. 16).

[0214] 19 to 21, the second portion 1412 of the oxide semiconductor pattern 1410 may overlap the first shielding layer disposed under the oxide semiconductor pattern 1410 and may overlap the second shielding layer disposed over the oxide semiconductor pattern 1410.

[0215] In one embodiment, the first shield layer may be the bottom metal layer BML. That is, the second portion 1412 of the oxide semiconductor pattern 1410 may overlap with the bottom metal layer BML. Specifically, the second portion 1412 of the oxide semiconductor pattern 1410 may overlap with the second branch portion BMLb of the bottom metal layer BML. In one embodiment, the second shield layer may be the fifth conductive layer 1700 ( FIG. 17 ). For example, the second portion 1412 of the oxide semiconductor pattern 1410 may overlap with the driving voltage line PL.

[0216] In other words, the upper surface of the second portion 1412 may be shielded from light by the driving voltage line PL, and the lower surface of the second portion 1412 may be shielded from light by the lower metal layer BML. The second portion 1412 of the oxide semiconductor pattern 1410 extends from the channel region C4 of the first initialization semiconductor layer A4 to the first connecting electrode 1630, and the second portion 1412 may transmit the first initialization voltage Vint (FIG. 3) to the gate electrode G1 (FIG. 11) of the driving transistor T1 (FIG. 11). If ultraviolet light penetrates the second portion 1412, the wiring resistance of the second portion 1412 made of an oxide semiconductor increases, which may initialize the potential of the gate electrode G1 (FIG. 11) of the driving transistor T1 (FIG. 11), thereby causing a degradation in image quality.

[0217] Therefore, in the display device according to an embodiment of the present invention, the lower metal layer BML and the driving voltage line PL are disposed to overlap the second portion 1412 of the oxide semiconductor pattern 1410, thereby protecting the second portion 1412 from ultraviolet light, etc. Furthermore, since the second portion 1412 overlaps the lower metal layer BML and the driving voltage line PL having the same constant voltage level, unnecessary parasitic capacitance can be prevented from affecting the second portion 1412. In conclusion, the display device according to an embodiment of the present invention can implement a high-quality image by preventing an increase in resistance of the oxide semiconductor pattern 1410 and unnecessary parasitic capacitance.

[0218] 19 and 20, vertical voltage lines VCL may be arranged in the separation space IVA (FIG. 17) of the display area DA (FIG. 1). As described above, the vertical voltage lines VCL may include the first initialization vertical voltage line VVIL, the second-first initialization vertical voltage line VVAL1, the second-second initialization vertical voltage line VVAL2 (FIG. 5), and the common voltage line VSL (FIG. 5).

[0219] The vertical voltage lines VCL may be electrically connected to corresponding horizontal voltage lines. For example, the first initialization vertical voltage line VVIL may be connected to the first initialization horizontal voltage line HVIL as shown in FIG. 19. Alternatively, the 2-1st initialization vertical voltage line VVAL1 may be electrically connected to the 2-1st initialization horizontal voltage line HVAL1 (FIG. 5) as shown in FIG. 20.

[0220] 19, the first initialization vertical voltage line VVIL may be connected to the bridge pattern 1680 through the seventeenth contact hole CNT17, and the bridge pattern 1680 may be connected to one end of the sub-bridge pattern 1340 through the thirteenth contact hole CNT13a, and the other end of the sub-bridge pattern 1340 may be connected to the first initialization horizontal voltage line HVIL through the thirteenth contact hole CNT13b. That is, the first initialization vertical voltage line VVIL may be connected to the first initialization horizontal voltage line HVIL through the bridge pattern 1680 and the sub-bridge pattern 1340.

[0221] 20, the 2-1st initialization vertical voltage line VVAL1 may be connected to the bridge pattern 1680 through the 17th contact hole CNT17. The bridge pattern 1680 may be connected to the 8th conductive pattern 1530 through the 13-1st contact hole CNT13a. The 8th conductive pattern 1530 may be included in the third conductive layer 1500 (FIG. 14) and may be integrally connected to the 2-1st initialization horizontal voltage line HVAL1. That is, the 2-1st initialization vertical voltage line VVAL1 may be connected to the 2-1st initialization horizontal voltage line HVAL1 through the bridge pattern 1680 and the 8th conductive pattern 1530.

[0222] 19 to 21 , the bridge pattern 1680 and the oxide semiconductor pattern 1410 having the above-described structure do not overlap each other. In an embodiment, the bridge pattern 1680 may be spaced apart from the oxide semiconductor pattern 1410 in a plan view. For example, the bridge pattern 1680 may be spaced apart from the fourth portion 1414 of the oxide semiconductor pattern 1410 by a small distance. In other words, a spaced apart region SA may exist between the bridge pattern 1680 and the oxide semiconductor pattern 1410.

[0223] Alternatively, in some embodiments, the bridge pattern 1680 may overlap slightly with the oxide semiconductor pattern 1410. However, even in such embodiments, only a portion of the fourth portion 1414 of the oxide semiconductor pattern 1410 overlaps with the bridge pattern 1680, and most of the top surface of the fourth portion 1414 does not overlap with the bridge pattern 1680.

[0224] A display device according to an exemplary embodiment of the present invention may improve display quality by arranging the bridge pattern 1680 and the oxide semiconductor pattern 1410 so that they do not overlap each other. Specifically, if the oxide semiconductor pattern 1410 and the bridge pattern 1680 overlap, the bridge pattern 1680 may receive a low-level voltage from the vertical voltage line VCL, which may prevent the adjacent compensation transistor T3 from operating normally. That is, if the bridge pattern 1680 is arranged to overlap the fourth portion 1414, the resistance of the oxide semiconductor pattern 1410 may increase, resulting in poor image quality. On the other hand, if the bridge pattern 1680 and the oxide semiconductor pattern 1410 are spaced apart as shown in FIGS. 19 to 21 , the bridge pattern 1680, which receives a low-level voltage, does not affect the oxide semiconductor pattern 1410. In conclusion, a display device according to an exemplary embodiment of the present invention may prevent an increase in the resistance of the oxide semiconductor pattern 1410 and prevent abnormal operation of the compensation transistor T3, thereby implementing a high-quality image.

[0225] Figure 22 is an enlarged plan view schematically illustrating a portion of a display device according to another embodiment of the present invention. Referring to Figure 22, the features of the display device, except for the features related to the compensation transistor T3, are the same as those described with reference to Figures 7 to 21. The same reference numerals as those used with reference to Figures 7 to 21 are used in Figures 22, and the following description will focus on the differences. For ease of explanation, Figure 22 illustrates only a portion of the components.

[0226] 22, the first, second, and third pixel circuits PC1, PC2, and PC3 (FIG. 7) may each include a compensation transistor T3 and a first initialization transistor T4. The compensation transistor T3 may include a compensation gate electrode and a compensation semiconductor layer A3, and the compensation gate electrode may include a lower compensation gate electrode G3a and an upper compensation gate electrode G3b. The first initialization transistor T4 may include a first initialization gate electrode and a first initialization semiconductor layer A4, and the first initialization gate electrode may include a lower first initialization gate electrode G4a and an upper first initialization gate electrode G4b.

[0227] The compensation semiconductor layer A3 and the first initialization semiconductor layer A4 may be oxide semiconductor layers and may be integrally connected. The compensation semiconductor layer A3 may include a channel region C3 and impurity regions disposed on both sides of the channel region C3 and doped with impurities. The first initialization semiconductor layer A4 may also include a channel region C4 and impurity regions disposed on both sides of the channel region C4.

[0228] In one embodiment, the channel width:length ratio (W / L) of the compensation transistor T3 is also different from the channel width:length ratio (W / L) of the first initialization transistor T4. For example, referring to FIG. 22, the channel length CL3 of the compensation transistor T3 may be longer than the channel length CL4 of the first initialization transistor T4. In this case, the width of the fourth conductive pattern 1320 forming the lower compensation gate electrode G3a of the compensation transistor T3 along the first direction (e.g., ±x direction) is longer than the width of the fifth conductive pattern 1330 forming the lower first initialization gate electrode G4a of the first initialization transistor T4 along the second direction (e.g., ±y direction). Similarly, the width along the first direction (e.g., ±x direction) of the sixth conductive pattern 1510 that forms the upper compensation gate electrode G3b of the compensation transistor T3 is longer than the width along the second direction (e.g., ±y direction) of the seventh conductive pattern 1520 that forms the first initialization gate electrode G4b above the first initialization transistor T4.

[0229] The compensating transistor T3 is turned on by the compensating signal to connect the gate electrode and second electrode of the driving transistor T1 (FIG. 11) to diode-connect the driving transistor T1. As a result, a threshold voltage difference of the driving transistor T1 occurs between the first electrode and gate electrode of the driving transistor T1, and the threshold voltage deviation of the driving transistor T1 can be compensated by supplying a threshold-voltage-compensated data signal to the gate electrode of the driving transistor T1.

[0230] The compensation transistor T3 must be completely turned off after compensating for the threshold voltage of the drive transistor T1 (FIG. 11). However, a parasitic capacitance is formed between the compensation gate electrode of the compensation transistor T3 and the source region of the compensation semiconductor layer A3. A change in the amount of charge due to the parasitic capacitance causes a voltage change in the drive gate electrode G1 (FIG. 11) of the drive transistor T1 (FIG. 11), resulting in a kickback phenomenon in the display device. The kickback phenomenon refers to a flickering phenomenon in which the display screen flickers or an afterimage, which can cause a degradation in the quality of the display device.

[0231] In this case, a display device according to another embodiment of the present invention may adjust the kickback voltage by differently designing the channel regions of the compensation transistor T3 and the first initialization transistor T4. The kickback voltage is the amount of voltage change at the gate electrode of the driving transistor T1 (FIG. 11) and may be proportional to the magnitude of the parasitic capacitance of the compensation transistor T3. For example, as shown in FIG. 22, if the channel length CL3 of the compensation transistor T3 is longer than the channel length CL4 of the first initialization transistor T4, the compensation transistor T3 has a larger W / L ratio than the first initialization transistor T4, and the parasitic capacitance and kickback voltage of the compensation transistor T3 may vary. That is, a display device according to another embodiment of the present invention may adjust the kickback voltage by differently designing the compensation transistor T3 and the first initialization transistor T4, thereby suppressing or preventing the kickback phenomenon and improving medium / long-term image sticking figure of merit (ISFOM).

[0232] Although the present invention has been described based on one embodiment shown in the drawings, this is merely an example, and those skilled in the art will understand that various modifications and variations of the embodiment are possible. Therefore, the true technical scope of protection of the present invention should be determined by the technical spirit of the claims. [Explanation of symbols]

[0233] 1 Display device DA display area PA Outer Area PC pixel circuit PC1, PC2, PC3: First to third pixel circuits LED Light Emitting Diode VVIL First initialization vertical voltage line HVIL First initialization horizontal voltage line VSL Common voltage line VVAL1 2nd-1st initialization vertical voltage line VVAL2 2nd-2nd initialization vertical voltage line HVAL1 2nd-1st initialization horizontal voltage line HVAL2 2nd-2nd initialization horizontal voltage line IVA isolated space VCL Vertical voltage line BML bottom metal layer 1100 Silicon semiconductor layer 1200 First conductive layer 1300 Second conductive layer 1400 Oxide semiconductor layer 1410 Oxide semiconductor pattern 1500 Third conductive layer 1600 4th conductive layer 1700 5th conductive layer PL drive voltage line 1680 Bridge Pattern 1340 Sub-Bridge Pattern

Claims

1. a first pixel circuit disposed on a substrate; a first light emitting diode electrically connected to the first pixel circuit; The first pixel circuit a driving transistor including a driving semiconductor layer and a driving gate electrode; a first initialization transistor including a first initialization semiconductor layer and a first initialization gate electrode, the first initialization transistor being electrically connected to the driving transistor; a first connection electrode electrically connecting the first initialization semiconductor layer and the driving gate electrode; the semiconductor layer including the first initialization semiconductor layer includes a first extension region extending from a channel region of the first initialization semiconductor layer to the first connecting electrode; A display device, wherein the first extension region overlaps with a first shield layer disposed below the first initialization semiconductor layer and a second shield layer disposed above the first initialization semiconductor layer.

2. The display device according to claim 1 , wherein the first shield layer is interposed between the upper surface of the substrate and the drive transistor.

3. The display device of claim 2 , wherein the first shield layer is a lower metal layer arranged to overlap the channel region of the driving transistor and the first connecting electrode.

4. The display device of claim 1 , wherein the second shield layer is interposed between the first connecting electrode and the first light emitting diode.

5. a driving voltage line that transmits a driving voltage to the first pixel circuit and extends through the first pixel circuit; The display device according to claim 4 , wherein the second shield layer is the driving voltage line.

6. the driving semiconductor layer and the first initialization semiconductor layer are disposed on different layers; the driving semiconductor layer is a silicon semiconductor layer, The display device according to claim 1 , wherein the first initialization semiconductor layer is an oxide semiconductor layer.

7. a second pixel circuit adjacent to the first pixel circuit along a first direction; a third pixel circuit disposed on the opposite side of the first pixel circuit with the second pixel circuit interposed therebetween; The display device of claim 1 , further comprising: a vertical voltage line disposed between the second pixel circuit and the third pixel circuit and extending along a second direction intersecting the first direction.

8. a second light emitting diode electrically connected to the second pixel circuit; a third light emitting diode electrically connected to the third pixel circuit, 8. The display device of claim 7, wherein the first light emitting diode emits red light, the second light emitting diode emits green light, and the third light emitting diode emits blue light.

9. The display device according to claim 7 , wherein the vertical voltage line is disposed on the same layer as the second shield layer.

10. a horizontal voltage line electrically connected to the vertical voltage line and extending along the first direction; a bridge pattern electrically connecting the vertical voltage line and the horizontal voltage line, The display device of claim 7 , wherein the bridge pattern is disposed on substantially the same layer as the first connecting electrode.

11. the third pixel circuit includes a silicon semiconductor layer and an oxide semiconductor layer; The display device of claim 10 , wherein the oxide semiconductor layer of the third pixel circuit is disposed apart from the bridge pattern when viewed from a direction perpendicular to the substrate.

12. The third pixel circuit is a drive transistor; a compensation transistor including a compensation semiconductor layer and a compensation gate electrode, electrically connected to the driving transistor; an emission control transistor including an emission control semiconductor layer and an emission control gate electrode, the emission control transistor being electrically connected to the driving transistor; a second connection electrode electrically connecting the compensation transistor and the driving transistor and electrically connecting the compensation transistor and the light-emitting control transistor, the semiconductor layer including the compensation semiconductor layer includes a second extension region extending from the drain region of the compensation semiconductor layer to the second connecting electrode; The display device of claim 10 , wherein the bridge pattern and the second extension region are spaced apart from each other.

13. The first pixel circuit a compensation transistor including a compensation semiconductor layer and a compensation gate electrode, the compensation transistor being electrically connected to the driving transistor; The display device of claim 1 , wherein the first initialization semiconductor layer and the compensation semiconductor layer are integrally connected.

14. The ratio (W / L) of the channel width (Width):channel length (Length) of the first initialization transistor is The display device according to claim 13 , wherein the channel width:channel length (W / L) ratios of the compensation transistors are different from each other.

15. The display device according to claim 13 , wherein the channel length of the compensation transistor is longer than the channel length of the first initialization transistor.

16. a first pixel circuit disposed on a substrate; a second pixel circuit adjacent to the first pixel circuit along a first direction; a third pixel circuit disposed on the opposite side of the first pixel circuit with the second pixel circuit interposed therebetween; a vertical voltage line disposed in a region separating the second pixel circuit and the third pixel circuit and extending along a second direction intersecting the first direction; a horizontal voltage line electrically connected to the vertical voltage line and extending along the first direction; a bridge pattern electrically connecting the vertical voltage line and the horizontal voltage line, each of the first pixel circuit, the second pixel circuit, and the third pixel circuit includes a silicon semiconductor layer and an oxide semiconductor layer; When the third pixel circuit is viewed from a direction perpendicular to the substrate, the oxide semiconductor layer and the bridge pattern are disposed to be spaced apart from each other.

17. a first light emitting diode electrically connected to the first pixel circuit; a second light emitting diode electrically connected to the second pixel circuit; a third light emitting diode electrically connected to the third pixel circuit, 17. The display device of claim 16, wherein the first light emitting diode emits red light, the second light emitting diode emits green light, and the third light emitting diode emits blue light.

18. The first pixel circuit, the second pixel circuit, and the third pixel circuit each include: a driving transistor including a driving gate electrode and a driving semiconductor layer included in the silicon semiconductor layer; a first initialization transistor including a first initialization gate electrode and a first initialization semiconductor layer included in the oxide semiconductor layer, the first initialization transistor being electrically connected to the driving transistor; a first connection electrode electrically connecting the first initialization semiconductor layer and the driving gate electrode, the oxide semiconductor layer includes a first extension region extending from a channel region of the first initialization semiconductor layer to the first connecting electrode; The display device of claim 16 , wherein the first extension region overlaps a first shield layer disposed under the oxide semiconductor layer and a second shield layer disposed over the oxide semiconductor layer.

19. The display device according to claim 18 , wherein the first shield layer is a lower metal layer interposed between the upper surface of the substrate and the driving transistor.

20. a driving voltage line disposed on the same layer as the vertical voltage line and spaced apart from the vertical voltage line; The display device according to claim 18 , wherein the second shield layer is the driving voltage line.

21. The first pixel circuit, the second pixel circuit, and the third pixel circuit each include: a compensation transistor including a compensation gate electrode and a compensation semiconductor layer included in the oxide semiconductor layer, the compensation transistor being electrically connected to the driving transistor; The display device of claim 18 , wherein a ratio of channel width to channel length (W / L) of the first initialization transistor is different from a ratio of channel width to channel length (W / L) of the compensation transistor.

22. a first pixel circuit disposed on a substrate; a first light emitting diode electrically connected to the first pixel circuit; The first pixel circuit a driving transistor including a driving semiconductor layer and a driving gate electrode; a first initialization transistor including a first initialization semiconductor layer and a first initialization gate electrode, the first initialization transistor being electrically connected to the driving transistor; a first connection electrode electrically connecting the first initialization semiconductor layer and the driving gate electrode; the semiconductor layer including the first initialization semiconductor layer includes a first extension region extending from a channel region of the first initialization semiconductor layer to the first connecting electrode; The electronic device, wherein the first extension region overlaps with a first shield layer disposed below the first initialization semiconductor layer and a second shield layer disposed above the first initialization semiconductor layer.

23. a second pixel circuit adjacent to the first pixel circuit along a first direction; a third pixel circuit disposed on the opposite side of the first pixel circuit with the second pixel circuit interposed therebetween; a vertical voltage line disposed between the second pixel circuit and the third pixel circuit and extending along a second direction intersecting the first direction; a horizontal voltage line electrically connected to the vertical voltage line and extending along the first direction; a bridge pattern electrically connecting the vertical voltage line and the horizontal voltage line, The electronic device of claim 22 , wherein the bridge pattern is disposed on substantially the same layer as the first connecting electrode.

24. the third pixel circuit includes a silicon semiconductor layer and an oxide semiconductor layer; The electronic device according to claim 23 , wherein the oxide semiconductor layer of the third pixel circuit is disposed apart from the bridge pattern when viewed from a direction perpendicular to the substrate.

Images