Display device and electronic apparatus including display device

Abstract

To provide a display device and an electronic apparatus including the display device.SOLUTION: A display device comprises: a substrate including an active area and a dummy area disposed outside the active area; a pixel circuit disposed in the active area; a light-emitting element electrically connected to the pixel circuit and including a pixel electrode; a dummy circuit disposed in the dummy area; a repair line extending in a first direction on the substrate, electrically connected to the dummy circuit, and disposed connectable to the light-emitting element; a pixel connection electrode disposed to overlap the repair line and electrically connected to the pixel electrode; and a voltage transfer line disposed to overlap the repair line, spaced apart from the pixel connection electrode, and transferring a voltage to the pixel circuit. An area of a portion of the voltage transfer line overlapping the repair line is greater than an area of a portion of the pixel connection electrode overlapping the repair line.SELECTED DRAWING: Figure 20B

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a display device to which a repair process can be applied via dummy pixels. [Background technology]

[0002] During the manufacturing process of a display device, defects can occur in the pixel circuit of a particular pixel. In such cases, the defective pixel may constantly emit light or display black regardless of scan signals and data signals. A pixel that constantly emits light is perceived by the viewer as a bright spot (or luminous spot), while a pixel that displays black is perceived by the viewer as a dark spot (or black spot). Furthermore, as the circuits within pixels become more complex, it has become difficult to repair the pixel circuit of such a defective pixel and overcome the bright spot or dark spot. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved by the present invention is to provide a display device that can operate normally by repairing defective pixels and can change a certain part of the circuit structure of dummy pixels used after the repair process, thereby improving display quality.

[0004] Another problem that the present invention aims to solve is to provide a display device with improved display quality by reducing the effect of coupling of a parasitic capacitor formed between a repair wiring used in a repair process and a pixel electrode, thereby reducing the difference in brightness due to voltage.

[0005] The technical problems that the present invention aims to solve are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art from the description of the present invention. [Means for solving the problem]

[0006] A display device according to one embodiment of the present invention includes a substrate including an active region and a dummy region arranged outside the active region; a pixel circuit arranged in the active region; a light-emitting element electrically connected to the pixel circuit and including a pixel electrode; a dummy circuit arranged in the dummy region; a repair line extending in a first direction on the substrate, electrically connected to the dummy circuit, and arranged so as to be connectable to the light-emitting element; a pixel connecting electrode arranged overlapping (overlapping) the repair line and electrically connected to the pixel electrode; and a voltage transmission wiring arranged overlapping (overlapping) the repair line, spaced from the pixel connecting electrode, and transmitting a voltage to the pixel circuit; wherein an area of ​​a portion of the voltage transmission wiring overlapping with the repair line is larger than an area of ​​a portion of the pixel connecting electrode overlapping with the repair line.

[0007] In one embodiment, the width of the voltage transmission line in the first direction at the portion overlapping with the repair line is wider than the width of the pixel connecting electrode in the first direction at the portion overlapping with the repair line.

[0008] In one embodiment, the width of the repair line along a second direction perpendicular to the first direction at the portion where the repair line overlaps with the voltage transmission wiring is wider than the width of the repair line along the second direction at the portion where the repair line overlaps with the pixel connecting electrode.

[0009] In one embodiment, the width of the voltage transmission line in the second direction at the portion overlapping the repair line is wider than the width of the pixel connecting electrode in the second direction at the portion overlapping the repair line.

[0010] In an embodiment, the display device may further include a voltage line disposed on the voltage transmission wiring and transmitting a voltage to the voltage transmission wiring.

[0011] In one embodiment, the voltage line may carry a DC voltage.

[0012] In one embodiment, the voltage line may carry a driving voltage ELVDD.

[0013] In one embodiment, the display device further includes a first transistor disposed on a substrate and including a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer; and a second transistor including a second semiconductor layer disposed on the first gate electrode and a second gate electrode overlapping the second semiconductor layer, and the repair line may be disposed on the same layer as the second gate electrode of the second transistor.

[0014] In one embodiment, the first semiconductor layer may include a silicon semiconductor material, and the second semiconductor layer may include an oxide semiconductor material.

[0015] In an embodiment, the pixel connecting electrodes and the voltage transmission lines may be disposed on the same layer.

[0016] In an embodiment, the pixel connecting electrode and the voltage transmission line may be disposed on different layers.

[0017] a second gate layer disposed on the first gate layer; a second semiconductor layer disposed on the second gate layer; a third gate layer disposed on the second semiconductor layer, connected to the dummy circuit, and configured to be connectable to a light-emitting element of a defective pixel among the plurality of pixels, the third gate layer including a repair line extending in a first direction; and a connecting electrode layer disposed on the third gate layer, the pixel connecting electrode overlapping the repair line and electrically connected to a pixel electrode of the light-emitting element, and the voltage transmission line overlapping the repair line and spaced apart from the pixel connecting electrode;

[0018] In one embodiment, the width of the portion of the voltage transmission wiring overlapping the repair line along the first direction is wider than the width of the portion of the pixel connecting electrode overlapping the repair line along the first direction.

[0019] In one embodiment, the width of the portion of the repair line that overlaps with the voltage transmission wiring along a second direction perpendicular to the first direction is wider than the width of the portion of the repair line that overlaps with the pixel connecting electrode along the second direction.

[0020] In one embodiment, the width of the voltage transmission line in the second direction at the portion overlapping with the repair line is wider than the width of the pixel connecting electrode in the second direction at the portion overlapping with the repair line.

[0021] In an embodiment, the display device may further include a voltage line disposed on the connection electrode layer and transmitting a voltage to the voltage transmission wiring.

[0022] In one embodiment, the voltage line may carry a DC voltage.

[0023] In one embodiment, the voltage line may carry a driving voltage ELVDD.

[0024] In an embodiment, the connecting electrode layer may further include a scan line extending in the first direction, spaced apart from the voltage transmission line, and transmitting a scan signal.

[0025] A display device according to an embodiment of the present invention includes a substrate including an active region and a dummy region disposed outside the active region; a first pixel disposed in the active region, the first pixel circuit and a first light-emitting element; a second pixel disposed in the active region, the second pixel circuit and a second light-emitting element; a dummy circuit disposed in the dummy region; a repair line extending in a first direction on the substrate, electrically connected to the dummy circuit, and arranged to be connectable to the first light-emitting element or the second light-emitting element; a first pixel connecting electrode disposed overlapping the repair line and electrically connected to a first pixel electrode of the first light-emitting element; and a second light-emitting element disposed overlapping the repair line, the second light-emitting element a second pixel connecting electrode electrically connected to the second pixel electrode of the first pixel circuit; and a voltage transmission wiring disposed overlapping the repair line, spaced apart from the first pixel connecting electrode and the second pixel connecting electrode, and electrically connected to each of the first pixel circuit and the second pixel circuit; wherein an area of ​​a portion of the voltage transmission wiring overlapping with the repair line may be larger than an area of ​​a portion of the first pixel connecting electrode overlapping with the repair line, and the portion of the voltage transmission wiring overlapping with the repair line may be located between a portion of the first pixel connecting electrode overlapping with the repair line and a portion of the second pixel connecting electrode overlapping with the repair line.

[0026] An electronic device according to an embodiment of the present invention includes a display device, the display device including: a substrate including an active region and a dummy region disposed outside the active region; a pixel circuit disposed in the active region; a light-emitting element electrically connected to the pixel circuit and including a pixel electrode; a dummy circuit disposed in the dummy region; a repair line extending in a first direction on the substrate, electrically connected to the dummy circuit, and arranged to be connectable to the light-emitting element; a pixel connecting electrode disposed overlapping the repair line and electrically connected to the pixel electrode; and a voltage transmission line disposed overlapping the repair line, spaced apart from the pixel connecting electrode, for transmitting a voltage to the pixel circuit, wherein an area of ​​a portion of the voltage transmission line overlapping with the repair line is larger than an area of ​​a portion of the pixel connecting electrode overlapping with the repair line.

[0027] In one embodiment, the electronic device further includes a display module, a processor, a power supply module, and a memory, and the display device may include at least one of the display module, the processor, the power supply module, or the memory. [Effects of the Invention]

[0028] According to an embodiment of the present invention, the effect of coupling of a parasitic capacitor formed between a repair line used in a repair process and a pixel electrode is reduced, thereby reducing brightness differences due to voltage of the display device, thereby improving display quality of the display device. It goes without saying that the scope of the present invention is not limited by such effects. [Brief explanation of the drawings]

[0029] [Figure 1] 1 is a diagram schematically illustrating a display device according to an embodiment of the present invention; [Figure 2] 2 is a diagram schematically illustrating an embodiment of the display unit illustrated in FIG. 1; [Figure 3] 3 is a diagram illustrating a method of repairing a defective pixel using a repair line in the display unit shown in FIG. 2; [Figure 4] 2 is a diagram schematically illustrating another embodiment of the display unit illustrated in FIG. 1; [Figure 5] FIG. 2 is an equivalent circuit diagram of one pixel according to an embodiment of the present invention. [Figure 6] FIG. 2 is an equivalent circuit diagram of a dummy pixel according to an embodiment of the present invention. [Figure 7] FIG. 2 is an equivalent circuit diagram of a portion of a pixel according to an embodiment of the present invention. [Figure 8] 2 is a layout diagram illustrating the positions of transistors and capacitors in a pixel included in a display device according to an embodiment of the present invention; [Figure 9] 9 is a layout diagram schematically illustrating components such as transistors and capacitors of the display device illustrated in FIG. 8 layer by layer. [Figure 10]9 is a layout diagram schematically illustrating components such as transistors and capacitors of the display device illustrated in FIG. 8 layer by layer. [Figure 11] 9 is a layout diagram schematically illustrating components such as transistors and capacitors of the display device illustrated in FIG. 8 layer by layer. [Figure 12] 9 is a layout diagram schematically illustrating components such as transistors and capacitors of the display device illustrated in FIG. 8 layer by layer. [Figure 13] 9 is a layout diagram schematically illustrating components such as transistors and capacitors of the display device illustrated in FIG. 8 layer by layer. [Figure 14] 9 is a layout diagram schematically illustrating components such as transistors and capacitors of the display device illustrated in FIG. 8 layer by layer. [Figure 15] 9 is a layout diagram schematically illustrating components such as transistors and capacitors of the display device illustrated in FIG. 8 layer by layer. [Figure 16] 9 is a layout diagram schematically illustrating components such as transistors and capacitors of the display device illustrated in FIG. 8 layer by layer. [Figure 17] 9 is a layout diagram schematically illustrating components such as transistors and capacitors of the display device illustrated in FIG. 8 layer by layer. [Figure 18] 9 is a layout diagram schematically illustrating components such as transistors and capacitors of the display device illustrated in FIG. 8 layer by layer. [Figure 19] 9 is a layout diagram schematically illustrating components such as transistors and capacitors of the display device illustrated in FIG. 8 layer by layer. [Figure 20A] 1 is a layout diagram illustrating some layers of a display device according to an embodiment of the present invention; [Figure 20B] FIG. 20B is an enlarged view of area "A" in FIG. 20A. [Figure 21A] 10 is a layout diagram illustrating some layers of a display device according to another embodiment of the present invention. [Figure 21B] FIG. 21B is an enlarged view of area "B" in FIG. 21A. [Figure 22] 1 is a cross-sectional view schematically illustrating a cross section of a display device according to an embodiment. [Figure 23] FIG. 10 is a cross-sectional view schematically illustrating a cross section of a display device according to another embodiment. [Figure 24] FIG. 1 is a block diagram of an electronic device according to one embodiment. [Figure 25] 1 is a schematic diagram of an electronic device according to various embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0030] The present invention can be modified in various ways and can have various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. The advantages and features of the present invention, and methods for achieving them, will become clearer with reference to the embodiments described in detail below in conjunction with the drawings. However, the present invention is not limited to the embodiments described below, and can be embodied in various forms.

[0031] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, identical or corresponding components will be denoted by the same reference numerals, and duplicate descriptions thereof will be omitted.

[0032] In the following embodiments, terms such as first and second are used to distinguish one component from another, without any limiting meaning.

[0033] In the following embodiments, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0034] In the following embodiments, terms such as "comprise" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0035] In the following embodiments, when a part such as a film, region, or component is said to be on or above another part, this does not only include the case where it is directly on top of the other part, but also the case where another film, region, component, etc. is interposed between them.

[0036] In the drawings, the size of components may be exaggerated or reduced for the sake of convenience. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for the sake of convenience, and the present invention is not necessarily limited to what is shown in the drawings.

[0037] If an embodiment can be implemented differently, the order of certain steps may be performed differently than described. For example, two steps described as successive steps may be performed substantially simultaneously or in the reverse order of that described.

[0038] In this specification, "A and / or B" refers to A, B, or A and B. And "at least one of A and B" refers to A, B, or A and B.

[0039] In the following embodiments, when a film, region, component, etc. is said to be connected, this includes cases where the film, region, component, etc. is directly connected, and / or cases where the film, region, component, etc. is indirectly connected by another film, region, component, etc. being interposed between them. For example, in this specification, when a film, region, component, etc. is said to be electrically connected, this includes cases where the film, region, component, etc. is directly electrically connected, and / or cases where the film, region, component, etc. is indirectly electrically connected by another film, region, component, etc. being interposed between them.

[0040] The x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system, but may be interpreted in a broader sense to include this. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, but may also refer to different directions that are not perpendicular to each other.

[0041] FIG. 1 is a block diagram illustrating an organic light emitting display device according to an embodiment of the present invention.

[0042] 1, the display device 1 may include a display unit 10, a gate driver 20, a source driver 30, a control unit 40, and a power supply unit 50. The gate driver 20, the source driver 30, the control unit 40, and the power supply unit 50 may be formed on separate semiconductor chips or integrated into a single semiconductor chip. The gate driver 20 and / or the source driver 30 may be formed on the same substrate as the display unit 10. The display device 1 may be a component for displaying images in an electronic device such as a smartphone, a tablet PC, a laptop PC, a monitor, or a TV.

[0043] An active area (display area) AA and a dummy area DA may be defined in the display unit 10. The dummy area DA may be disposed in the non-display area adjacent to the active area AA. The dummy area DA may be disposed on the left and / or right side of the active area AA. In yet another example, the dummy area DA may be disposed above and / or below the active area AA. Since the display unit 10 includes a substrate 100 as will be described with reference to FIG. 22, it can also be said that the substrate 100 has the active area AA and the dummy area DA.

[0044] The active area AA may include a plurality of pixels P connected to a plurality of control lines CL1 through CLn extending along a first direction (e.g., the x direction) and a plurality of data lines DL1 through DLm extending along a second direction (e.g., the y direction). The dummy area DA may include a plurality of dummy pixels DP connected to a dummy data line DDL and a corresponding control line (e.g., CLi) among the plurality of control lines CL1 through CLn. The dummy pixels DP may be arranged in the dummy area DA along the second direction.

[0045] 1, the control lines CL1 to CLn are illustrated as a single signal line for convenience, but each of the control lines CL1 to CLn may be composed of multiple signal lines. For example, the first control line CL1 may be composed of three lines that apply a scan signal GW, an initialization control signal GI, and an emission control signal EM.

[0046] The display unit 10 may include a plurality of repair lines RL1 to RLn extending parallel to the plurality of control lines CL1 to CLn. The repair lines RL1 to RLn may be connected to the dummy pixels DP and arranged to be connectable to the pixels P.

[0047] A unit pixel may include a plurality of sub-pixels each representing a plurality of hues to display various hues. In this specification, a pixel P mainly refers to one sub-pixel. That is, in this specification, when it is stated that one pixel P exists, it can be interpreted as meaning that one sub-pixel exists.

[0048] As used herein, the terms "connectable" or "connectably" refer to a state in which they can be connected using a laser or the like in a repair process. For example, when a first member and a second member are arranged to be connectable, it means that the first member and the second member are not actually connected, but are placed in a state in which they can be connected to each other in a repair process. From a structural perspective, the first member and the second member that are "connectable" to each other may be arranged to cross each other in an overlapping (overlapping) region, with an insulating film sandwiched between them. When a laser is irradiated onto the overlapping region in a repair process, the insulating film in the overlapping region is destroyed, and the first member and the second member may be electrically connected to each other.

[0049] Additionally, in this specification, the term "separable" or "separably" refers to a state in which the first and second members can be separated using a laser or the like during a repair process. For example, when a first member and a second member are detachably connected, the first and second members are actually connected but are placed in a state in which they can be separated during a repair process. From a structural perspective, the detachably connected first and second members may be arranged to be connected to each other through a conductive connecting member. When a laser is irradiated onto the conductive connecting member during the repair process, the conductive connecting member is cut by melting the irradiated portion of the laser, and the first and second members may be electrically insulated from each other. For example, the conductive connecting member may include a silicon layer that can be melted by a laser. In another example, the conductive connecting member may be melted and cut by Joule heat caused by an electric current.

[0050] The display unit 10 may include a connection line GL connected to the dummy data line DDL and arranged to be connectable to the plurality of data lines DL1 to DLm. The connection line GL may extend along a first direction. The connection line GL may be arranged in a dead space on the periphery of the active area AA and the dummy area DA. The dead space may refer to an area in the display unit 10 where the pixels P and dummy pixels DP are not arranged. Because the connection line GL is arranged in the dead space, the connection line GL may be formed with a large design margin. For example, the connection line GL may have a wider width and / or thickness to reduce resistance. A plurality of connection lines GL may be arranged in the display unit 10.

[0051] The gate driver 20 provides a plurality of control signals to the pixels P and the dummy pixels DP via control lines CL1 to CLn, and the source driver 30 provides data signals to the pixels P via data lines DL1 to DLm. As shown in FIG. 1, the source driver 30 is not directly connected to the dummy data lines DDL. According to another example, the source driver 30 may be directly connected to the dummy data lines DDL and provide data signals directly to the dummy pixels DP.

[0052] The controller 40 may control the gate driver 20, the source driver 30, and the power supply 50. The controller 40 may output control signals and image data to the gate driver 20, the source driver 30, and / or the power supply 50 based on a horizontal synchronization signal and a vertical synchronization signal to control the gate driver 20, the source driver 30, and / or the power supply 50. The power supply 50 may apply a driving voltage ELVDD, a common voltage ELVSS, a first initialization voltage Vint, a second initialization voltage Vaint, and a bias voltage Vobs to the pixel P and / or the dummy pixel DP.

[0053] The pixel P may include a light-emitting element and a pixel circuit detachably connected to the light-emitting element. The dummy pixel DP may include a dummy circuit. For example, if the pixel P shown in FIG. 1 is a defective pixel, the light-emitting element of the defective pixel may be separated from the pixel circuit of the defective pixel and connected to a corresponding dummy pixel DP via a corresponding repair line RLi among the repair lines RL1 to RLn. Furthermore, a data line DLj connected to the defective pixel among the data lines DL1 to DLm may be connected to a dummy data line DDL via a connecting line GL. A data signal to be applied to the defective pixel is applied to the dummy pixel DP via the data line DLj, the connecting line GL connected to the data line DLj, and the dummy data line DDL connected to the connecting line GL. The dummy pixel DP generates a driving current corresponding to the data signal and supplies the driving current to the light-emitting element of the defective pixel via the repair line RLi. The light-emitting element emits light of a brightness corresponding to the data signal. Therefore, the light-emitting element of the defective pixel operates normally thanks to the dummy pixel DP.

[0054] In this specification, the terms "corresponding" or "correspondingly" mean being arranged in the same column or row depending on the context. For example, when a first member is connected to a "corresponding" second member among a plurality of second members, it means that the first member is connected to the second member arranged in the same column or row as the first member.

[0055] FIG. 2 is a diagram schematically illustrating an example of the display unit illustrated in FIG.

[0056] Referring to FIG. 2, the display unit 10 may include an active area AA that displays an image by emitting light and a dummy area DA surrounding the active area AA.

[0057] Each pixel P arranged in the active area AA may include a pixel circuit PC and a light-emitting element E that emits light by receiving a driving current from the pixel circuit PC. The light-emitting element E and the pixel circuit PC may be detachably connected to each other. The pixel circuit PC may include one or more thin film transistors and a capacitive element. In this specification, a capacitive element may refer to a capacitor. The pixel P may emit light of one color, for example, red, blue, green, or white. However, the present invention is not limited thereto, and the pixel P may emit light of a color other than red, blue, green, or white.

[0058] The light emitting element E of the pixel P may be insulated from the repair line in the same row and may be electrically connected to the repair line in a later repair process. That is, the light emitting element E of the pixel P may be arranged so as to be connectable to the repair line in the same row. For example, the light emitting element E may be electrically connected to the first connection member 11, and the first connection member 11 may be formed to partially overlap the repair line with an insulating film sandwiched therebetween. The first connection member 11 may include one or more conductive layers made of a conductive material. In the repair process, when a laser is irradiated onto the overlapping area of ​​the first connection member 11 and the repair line, the insulating film is destroyed, and the first connection member 11 and the repair line may be shorted and electrically connected. As a result, the light emitting element E may be electrically connected to the repair line.

[0059] 2 illustrates an example in which a dummy area DA is disposed to the left of the active area AA, and one dummy pixel DP is disposed in each row. A dummy data line DDL connected to the dummy pixel DP may be disposed in the dummy area DA. The dummy data line DDL may be disposed parallel to the data lines DL1 through DLm. Repair lines RL1 through RLn and control lines CL1 through CLn may also extend into the dummy area DA.

[0060] The dummy pixel DP includes a dummy circuit DC and does not include a light-emitting element. The dummy circuit DC may be identical to the pixel circuit PC. In other examples, the dummy circuit DC may differ from the pixel circuit PC. For example, the dummy circuit DC may omit and / or add transistors and / or capacitive elements of the pixel circuit PC, or the sizes and characteristics of the transistors and capacitive elements may differ from those of the pixel circuit PC.

[0061] The connection lines GL may be disposed on the periphery of the active region AA and the dummy region DA. The connection lines GL and the data lines DL1 through DLm are insulated from each other, and during a repair process, the connection lines GL and one of the data lines DL1 through DLm may be electrically connected to each other. For example, the data lines DL1 through DLm may be disposed to partially overlap the connection lines GL with an insulating film sandwiched therebetween. During the repair process, when a laser is irradiated onto the overlapping area of ​​the data line connected to the defective pixel and the connection lines GL, the insulating film is destroyed, the data line and the connection lines GL are shorted, and the data line connected to the defective pixel and the connection lines GL may be electrically connected to each other.

[0062] FIG. 3 is a diagram illustrating a method of repairing a defective pixel using a repair line in the display unit shown in FIG.

[0063] Hereinafter, a case where a defect occurs in a pixel Pij connected to the ith control line CLi and the jth data line DLj among the pixels P formed in the active area AA, for example, a case where the pixel circuit PC of the pixel Pij is defective, will be described as an example. In this example, the pixel Pij is referred to as the defective pixel Pij. The pixel Pij may be located in the ith row and the jth column.

[0064] 3, the light emitting element E of the defective pixel Pij may be separated from the pixel circuit PC. For example, the light emitting element E of the defective pixel Pij may be separated from the pixel circuit PC by irradiating a laser to cut a connection region between the light emitting element E and the pixel circuit PC.

[0065] Next, the light-emitting element E of the defective pixel Pij and the dummy circuit DC of the dummy pixel DPi may be electrically connected to each other. To this end, the light-emitting element E of the defective pixel Pij may be connected to the repair line RLi in the same row. For example, the light-emitting element E may be electrically connected to the repair line RLi by irradiating a laser onto an overlapping region between the first connection member 11 connected to the light-emitting element E of the defective pixel Pij and the repair line RLi in the same row. Since the repair line RLi is connected to the dummy circuit DC, the light-emitting element E of the defective pixel Pij may be connected to the dummy circuit DC of the dummy pixel DPi.

[0066] Next, the data line DLj connected to the defective pixel Pij and the dummy data line DDL may be electrically connected to each other. To this end, the data line DLj may be connected to the connecting line GL. For example, the data line DLj and the connecting line GL may be electrically connected to each other by irradiating a laser onto an overlapping area of ​​the data line DLj and the connecting line GL. Since the connecting line GL is connected to the dummy data line DDL, the data line DLj and the dummy data line DDL may be connected to each other.

[0067] The pixel circuit PC of the defective pixel Pij and the dummy circuit DC of the dummy pixel DPi may simultaneously respond to a scan signal applied to the same scan line among the control lines CLi. The data line DLj connected to the pixel circuit PC of the defective pixel Pij is connected to the dummy data line DDL via the connecting line GL, so that the data signal Dj applied to the pixel circuit PC of the defective pixel Pij may also be applied to the dummy circuit DC of the dummy pixel DPi. The dummy circuit DC may generate a driving current Iij corresponding to the data signal Dj and provide the driving current Iij to the light-emitting element E of the defective pixel Pij via the repair line RLi. The light-emitting element E of the defective pixel Pij may emit light with a brightness corresponding to the data signal Dj in response to the driving current Iij. As a result, the defective pixel Pij may be repaired to a normal pixel.

[0068] In this example, the dummy data line DDL is connected to the data line DLj via the connecting line GL, so there is no need to separately drive the dummy data line DDL, and therefore there is no need to modify the source driver to drive the dummy data line DDL or to provide a separate timing, and the existing driver can be used as is.

[0069] FIG. 4 is a diagram schematically illustrating yet another example of the display unit 10a illustrated in FIG.

[0070] 4, the display unit 10a is substantially the same as the display unit 10 shown in FIG. 2, except for some differences. Hereinafter, redundant explanations will be omitted and the differences will be mainly described. For easy understanding of this embodiment, FIG. 4 does not show normal pixels P, but only shows defective pixels BPa and BPb, and control lines are also omitted.

[0071] The display unit 10a may include a first dummy area DA1 disposed to the left of the active area AA and a second dummy area DA2 disposed to the right of the active area AA. A first dummy data line DDL1 and a plurality of first dummy pixels (e.g., DPa) connected thereto may be disposed in the first dummy area DA1. A second dummy data line DDL2 and a plurality of second dummy pixels (e.g., DPb) connected thereto may be disposed in the second dummy area DA2. The first dummy area DA1 and the second dummy area DA2 may correspond to the dummy area DA in FIG. 1.

[0072] The active region AA may be divided into a first active region AA1 and a second active region AA2. A first connection line GL1 connected to the first dummy data line DDL1 may be arranged above the first active region AA1, and a second connection line GL2 connected to the second dummy data line DDL2 may be arranged above the second active region AA2. The first connection line GL1 and the second connection line GL2 may be insulated from each other. The first connection line GL1 and the second connection line GL2 may be arranged below the first active region AA1 and the second active region AA2. The data line DLa on the first active region AA1 may be arranged to be connectable to the first connection line GL1. The data line DLb on the second active region AA2 may be arranged to be connectable to the second connection line GLW2.

[0073] The display unit 10a may include a first repair line (e.g., RLa) extending from the first dummy pixel DPa in the first dummy area DA1 onto the first active area AA1, and a second repair line (e.g., RLb) extending from the second dummy pixel DPb in the second dummy area DA2 onto the second active area AA2. The first repair line RLa and the second repair line RLb may be insulated from each other.

[0074] At least one defective pixel BPa in the first active area AA1 may be repaired using the first repair line RLa, the first connecting line GL1, and the first dummy data line DDL1. Multiple defective pixels BPa located in the same column may be repaired together without additional connecting lines and dummy data lines. The light-emitting element E of the defective pixel BPa in the first active area AA1 may be isolated from the pixel circuit PC and connected to the dummy circuit DC of the first dummy pixel DPa in the same row via the first repair line RLa. The data line DLa connected to the defective pixel BPa is connected to the first connecting line GL1, and a data signal applied to the data line DLa may also be applied to the dummy circuit DC. The dummy circuit DC generates a driving current corresponding to the data signal and provides it to the light-emitting element E of the defective pixel BPa via the first repair line RLa, and the light-emitting element E may emit light by the driving current.

[0075] At least one defective pixel BPb in the second active region AA2 may be repaired using the second repair line RLb, the second connecting line GL2, and the second dummy data line DDL2. The light-emitting element E of the defective pixel BPb in the second active region AA2 may be isolated from the pixel circuit PC and connected to a dummy circuit DC of a second dummy pixel DP2 in the same row via the second repair line RLb. The data line DLb connected to the defective pixel BPb may be connected to the second connecting line GL2, and a data signal applied to the data line DLb may also be applied to the dummy circuit DC. The dummy circuit DC may generate a driving current corresponding to the data signal and provide it to the light-emitting element E of the defective pixel BPb via the second repair line RLb, and the light-emitting element E may emit light by the driving current.

[0076] According to this embodiment, at least one defective pixel BPa in the first active area AA1 and at least one defective pixel BPb in the second active area AA2 can be repaired, and even if two defective pixels occur in the same row, they can be repaired.

[0077] Although the above-described embodiment has been described as an example of repair in which a defective pixel and a dummy pixel DP in the same row are connected by a repair line in the same row, the present invention is not limited thereto and may be equally applied to a case in which a defective pixel is connected to a dummy pixel DP in another row and a repair line in the same row as the defective pixel.

[0078] 5 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. Fig. 5 exemplarily illustrates an equivalent circuit diagram of one pixel P among a plurality of pixels P. For example, the pixel P in Fig. 5 may be the pixel Pij (see Fig. 3) located in the ith row and jth column.

[0079] 5, a pixel P is connected to a scan line GWL, a first initialization control line GIL, a second initialization control line GBL, a compensation scan line GCL, and an emission control line EML, respectively, and may receive a scan signal GW, a first initialization control signal GI, a second initialization control signal GB, a compensation scan signal GC, and an emission control signal EM. For example, the scan line GWL, the first initialization control line GIL, the second initialization control line GBL, the compensation scan line GCL, and the emission control line EML in FIG. 5 may be signal lines corresponding to a pixel P located in the i-th row.

[0080] The pixel P may receive a data signal Dm through a data line DL. For example, the data line DL in FIG. 5 may be a data line corresponding to the pixel Pij (see FIG. 3) located in the j-th column.

[0081] A pixel P of the display device according to this embodiment may include a pixel circuit PC and an organic light emitting element OLED (see FIG. 2) connected to the pixel circuit PC to emit light as a light emitting element E. The organic light emitting element OLED may include a pixel electrode (anode), a counter electrode (cathode), and an emitting layer between the anode and the cathode.

[0082] Hereinafter, a display device 1 (see FIG. 1) according to an embodiment of the present invention will be described as an organic light-emitting display device including an organic light-emitting element (OLED), but the display device 1 of the present invention is not limited thereto. In other embodiments, the display device 1 of the present invention may be an inorganic light-emitting display device (or inorganic EL display device) or a quantum dot light-emitting display device. For example, the light-emitting layer of the light-emitting element E (see FIG. 2) included in the display device 1 may include an organic material or an inorganic material. In addition, the display device 1 may include a light-emitting layer and a quantum dot layer positioned on the path of light emitted from the light-emitting layer.

[0083] The pixel circuit PC may include a plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 and a storage capacitive element. The plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, an emission control transistor T6, a second initialization transistor T7, and a bias transistor T8. The storage capacitive element may also be a capacitor, and may be referred to herein as a first storage capacitor Cst1.

[0084] In one embodiment, some of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be p-channel MOSFETs (PMOSs), and the remaining transistors may be n-channel MOSFETs (NMOSs). For example, the driving transistor T1, the switching transistor T2, the operation control transistor T5, the light-emitting control transistor T6, the second initialization transistor T7, and the bias transistor T8 of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be PMOSs, and the compensation transistor T3 and the first initialization transistor T4 of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be PMOSs, and the remaining transistors may be NMOSs. Alternatively, all of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be NMOSs or all of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be PMOSs. For convenience, the following description will be given assuming that the compensation transistor T3 and the first initialization transistor T4 are NMOS (n-channel MOSFETs) including an oxide semiconductor, and the rest are PMOS (p-channel MOSFETs).

[0085] At least one of the plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and at least one of the plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be a transistor having an oxide semiconductor layer.

[0086] The driving transistor T1, which directly affects the brightness of the display device, may be configured to include a semiconductor layer made of highly reliable polycrystalline silicon, thereby enabling a high-resolution display device. Meanwhile, oxide semiconductors have high carrier mobility and low leakage current, so they do not significantly drop in voltage even over long drive periods. That is, low-frequency drive is possible because the image color does not change significantly due to voltage drop even during low-frequency drive. Because oxide semiconductors have the advantage of low leakage current, at least one of the compensation transistor T3 and the first initialization transistor T4, which are connected to the drive gate electrode of the driving transistor T1, may be made of an oxide semiconductor to prevent leakage current from flowing through the drive gate electrode and reduce power consumption. For example, the driving transistor T1, the switching transistor T2, the operation control transistor T5, the emission control transistor T6, the second initialization transistor T7, and the bias transistor T8 may be transistors having low-temperature polysilicon semiconductor layers, and the compensation transistor T3 and the first initialization transistor T4 may be transistors having oxide semiconductor layers.

[0087] The driving transistor T1 may be connected between a driving voltage line PL receiving a driving voltage ELVDD and the organic light emitting element OLED. A gate electrode of the driving transistor T1 may be connected to one end of a first storage capacitor Cst1. A gate electrode of the driving transistor T1 may be connected to a first node N1. A source electrode of the driving transistor T1 may be connected to the driving voltage line PL via an operation control transistor T5. A drain electrode of the driving transistor T1 may be electrically connected to an anode of the organic light emitting element OLED via an emission control transistor T6. The driving transistor T1 may receive a data signal Dm transmitted from a data line DL through a switching operation of the switching transistor T2 and supply a driving current to the organic light emitting element OLED.

[0088] The gate electrode of the switching transistor T2 may be connected to the scan line GWL. The first electrode of the switching transistor T2 may be connected to the data line DL, and the second electrode of the switching transistor T2 may be connected to the source electrode of the driving transistor T1. The switching transistor T2 is turned on by a scan signal GW transmitted through the scan line GWL to transmit a data signal Dm transmitted to the data line DL to the source electrode of the driving transistor T1. The data signal Dm may be transmitted to the gate electrode of the driving transistor T1 by the compensation transistor T3, which is turned on at the same time.

[0089] A gate electrode of the compensation transistor T3 may be connected to a compensation scan line GCL. A first electrode of the compensation transistor T3 may be connected to a drain electrode of the driving transistor T1, and a second electrode of the compensation transistor T3 may be connected to a first node N1. The compensation transistor T3 is turned on by a compensation scan signal GC transmitted through the compensation scan line GCL to connect the gate electrode and drain electrode of the driving transistor T1 to each other, thereby diode-connecting the driving transistor T1 and compensating for the threshold voltage Vth of the driving transistor T1.

[0090] The gate electrode of the first initialization transistor T4 may be connected to a first initialization control line GIL. The first electrode of the first initialization transistor T4 may be connected to a first initialization voltage line VL1, and the second electrode may be connected to a first node N1. The first initialization transistor T4 may be turned on by a first initialization control signal GI applied from the first initialization control line GIL and transmit a first initialization voltage Vint to the gate electrode of the driving transistor T1, thereby initializing the potential of the gate electrode of the driving transistor T1 (i.e., the potential of the first node N1) to a predetermined voltage. The first initialization voltage Vint may be set to a voltage higher than the common voltage ELVSS or to the common voltage ELVSS.

[0091] The gate electrode of the operation control transistor T5 may be connected to the emission control line EML, the first electrode of the operation control transistor T5 may be connected to the driving voltage line PL, and the second electrode of the operation control transistor T5 may be connected to the source electrode of the driving transistor T1.

[0092] A gate electrode of the emission control transistor T6 may be connected to an emission control line EML. A first electrode of the emission control transistor T6 may be connected to a drain electrode of the driving transistor T1, and a second electrode of the emission control transistor T6 may be electrically connected to an anode of the organic light emitting element OLED. The operation control transistor T5 and the emission control transistor T6 may be simultaneously turned on by an emission control signal EM applied from the emission control line EML. The driving voltage ELVDD applied through the turned-on operation control transistor T5 may be compensated through the driving transistor T1 and then transferred to the organic light emitting element OLED.

[0093] A gate electrode of the second initialization transistor T7 may be connected to a second initialization control line GBL. A first electrode of the second initialization transistor T7 may be connected to the anode of the organic light emitting element OLED, and a second electrode of the second initialization transistor T7 may be connected to a second initialization voltage line VL2. The second initialization transistor T7 may be turned on by a second initialization control signal GB applied from the second initialization control line GBL to initialize the anode of the organic light emitting element OLED. The second initialization control signal GB may be the same as or different from the first initialization control signal GI.

[0094] Unlike the present invention, even if the minimum current of the driving transistor T1 for displaying a black image flows as the driving current, if the organic light emitting element OLED emits light, the black image may not be properly displayed. However, according to the present invention, the second initialization transistor T7 can disperse a portion of the minimum current of the driving transistor T1 as a bypass current to a current path other than the current path on the organic light emitting element OLED side. Here, the minimum current of the driving transistor T1 may refer to a current under a condition where the gate-source voltage Vgs of the driving transistor T1 is lower than a threshold voltage (Vth) and the driving transistor T1 is turned off. In this way, the minimum driving current (e.g., a current of 10 pA or less) under the condition of turning off the driving transistor T1 is transmitted to the organic light emitting element OLED to display a black image. When the minimum driving current for displaying a black image flows, the bypass current has a significant effect. On the other hand, when a large driving current for displaying an image such as a normal image or a white image flows, the bypass current has almost no effect. Therefore, when a driving current for displaying a black image flows, an accurate black luminance image is realized from the driving current using the first initialization transistor T7, thereby improving the contrast ratio and providing a display device with improved display quality.

[0095] A gate electrode of the bias transistor T8 may be connected to the second initialization control line GBL, a first electrode of the bias transistor T8 may be connected to a bias voltage line VL3 to which a bias voltage Vobs is provided, and a second electrode of the bias transistor T8 may be connected to the source electrode of the driving transistor T1.

[0096] One end of the first storage capacitor Cst1 may be connected to the gate electrode of the driving transistor T1, and the other end may be connected to the driving voltage line PL. The first storage capacitor Cst1 may be connected between the driving voltage line PL and a first node N1. The first storage capacitor Cst1 may store a voltage between the driving voltage ELVDD and the first node N1.

[0097] The anode of the organic light emitting device OLED may be connected to a repair line and may be separated from the pixel circuit PC. The cathode of the organic light emitting device OLED may be connected to a common voltage line that applies a common voltage ELVSS. The organic light emitting device OLED may emit light by receiving a driving current from the driving transistor T1, thereby displaying an image. The driving voltage ELVDD may be a predetermined high-level voltage, and the common voltage ELVSS may be a voltage lower than the driving voltage ELVDD or a ground voltage.

[0098] The operation process of the pixel P will now be described. During the initialization period, a high-level first initialization control signal GI may be supplied to the first initialization transistor T4 via the first initialization control line GIL, and a low-level second initialization control signal GB may be supplied to the second initialization transistor T7 via the second initialization control line GBL. As a result, the first initialization transistor T4 and the second initialization transistor T7 may be turned on. A first initialization voltage Vint applied from the first initialization voltage line VL1 may be transmitted to the gate electrode of the driving transistor T1 via the first initialization transistor T4, and a second initialization voltage Vaint may be transmitted to the anode via the second initialization transistor T7. As a result, the voltages of the gate electrode and anode of the driving transistor T1 may be initialized.

[0099] Thereafter, during a data write period, a low-level scan signal GW is supplied via the scan line GWL, turning on the switching transistor T2. A compensation scan signal GC is supplied via the compensation scan signal GSL, turning on the compensation transistor T3. The switching transistor T2 transfers the data signal Dm from the data line DL to the source electrode of the driving transistor T1, and the driving transistor T1 is diode-coupled by the compensation transistor T3. As a result, a compensation voltage that is reduced from the data signal Dm by the threshold voltage of the driving transistor T1 is applied to the gate electrode of the driving transistor T1.

[0100] The driving voltage ELVDD and the compensation voltage are applied to both ends of the first storage capacitor Cst1, and a charge corresponding to the voltage difference between both ends of the first storage capacitor Cst1 can be stored in the first storage capacitor Cst1.

[0101] Thereafter, during the light-emitting period, the light-emitting control signal EM supplied from the light-emitting control line EML changes from high to low, turning on the operation control transistor T5 and the light-emitting control transistor T6, generating a driving current due to the voltage difference between the gate electrode voltage of the driving transistor T1 and the driving voltage ELVDD, and the driving current is supplied to the organic light-emitting element OLED via the light-emitting control transistor T6, causing it to emit light.

[0102] The characteristics of the driving transistor T1 and the light-emitting element may differ for each of the plurality of pixels P. In particular, the color coordinates of the display device 1 may vary (e.g., become reddish) when driven at a high frequency. However, according to the present invention, the voltage of the source electrode of the driving transistor T1 may be controlled by the bias voltage Vobs via the bias transistor T8. This may improve the brightness deviation (current deviation) and color coordinate variation between pixels by controlling the driving current. Therefore, a display device 1 with improved display quality may be provided.

[0103] 6 is an equivalent circuit diagram of a dummy pixel DP according to an embodiment of the present invention. The dummy pixel DP in FIG. 6 exemplarily illustrates one dummy pixel DP among a plurality of dummy pixels DP, which is connected to the pixel P in FIG. 5 by a repair line. For example, the dummy pixel DP in FIG. 6 may be a dummy pixel located in the i-th row.

[0104] 6 may be a dummy pixel located in the i-th row. The dummy pixel DP may be connected to the scan line GWL, the first initialization control line GIL, and the emission control line EML corresponding to the i-th row, respectively, and may receive the i-th scan signal GW, the i-th first initialization control signal GI, and the i-th emission control signal EM.

[0105] 6, the dummy pixel DP is connected to the scan line GWL, the first initialization control line GIL, the second initialization control line GBL, the compensation scan line GCL, and the emission control line EML, respectively, and may receive the scan signal GW, the first initialization control signal GI, the second initialization control signal GB, the compensation scan signal GC, and the emission control line EM. For example, the scan line GWL, the first initialization control line GIL, the second initialization control line GBL, the compensation scan line GCL, and the emission control line EML in FIG. 6 may be signal lines corresponding to the pixel P located in the i-th row.

[0106] The dummy pixel DP may receive a data signal Dm through a dummy data line DDL. For example, the dummy data line DDL in FIG. 6 may be connected to a data line DLj (see FIG. 1) corresponding to a pixel Pij (see FIG. 3) located in the j-th column.

[0107] The dummy pixel DP may include a dummy circuit DC. The dummy circuit DC may include a plurality of transistors DT1, DT2, DT3, DT4, DT5, DT6, DT8, DT9, and DT10, a storage capacitive element, and a compensation capacitive element. The plurality of transistors DT1, DT2, DT3, DT4, DT5, DT6, DT8, DT9, and DT10 of the dummy circuit DC may include a driving transistor DT1, a switching transistor DT2, a compensation transistor DT3, a first initialization transistor DT4, an operation control transistor DT5, an emission control transistor DT6, a bias transistor DT8, a capacitance control transistor DT9, and a capacitance initialization transistor DT10. The storage capacitive element and the compensation capacitive element may be capacitors. In this specification, the storage capacitive element may be represented by a second storage capacitor Cst2, and the compensation capacitive element may be represented by a compensation capacitor Ccomp. The elements of the dummy circuit DC may differ in size and capacitance from those of the pixel circuit PC (see FIG. 5).

[0108] The dummy circuit DC of the dummy pixel DP is almost the same as the pixel circuit PC of the pixel P shown in Fig. 5, except for some differences. Hereinafter, a redundant description will be omitted and the differences will be mainly described.

[0109] A gate electrode of the capacitance control transistor DT9 is connected to an emission control line EML and may receive an emission control signal EM. A first electrode of the capacitance control transistor DT9 may be connected to a repair line RL via an output node DNo, and a second electrode of the capacitance control transistor DT9 may be connected to a compensation node DNc. The capacitance control transistor DT9 may be turned on by the emission control signal EM to supply energy stored in the compensation capacitor Ccomp to the repair line RL.

[0110] A gate electrode of the capacitive element initialization transistor DT10 may be connected to a second initialization control line GBL and may receive a second initialization control signal GB. A first electrode of the capacitive element initialization transistor DT10 may be connected to the compensation node DNc, and a second electrode of the capacitive element initialization transistor DT10 may be connected to a second initialization voltage line VL2. The capacitive element initialization transistor DT10 may be turned on in response to the second initialization control signal GB and may supply the second initialization voltage Vaint to the compensation capacitor Ccomp so that the compensation capacitor Ccomp is charged with an amount of charge corresponding to the difference between the driving voltage ELVDD and the second initialization voltage Vaint.

[0111] The driving voltage ELVDD and the voltage of the compensation node DNc are applied to both ends of the compensation capacitor Ccomp, and a charge corresponding to the voltage difference between both ends of the compensation capacitor Ccomp can be stored in the compensation capacitor Ccomp.

[0112] The dummy pixels DP do not include an organic light-emitting element OLED. However, the dummy pixels DP may also include a light-emitting element depending on the design. When the dummy pixels DP include a light-emitting element, the light-emitting element may function as a circuit element without actually emitting light. For example, the light-emitting element may function as one of the capacitors included in the dummy pixels.

[0113] The operation of the dummy pixel DP will now be described. During the initialization period, a low-level first initialization control signal GI may be supplied to the initialization transistor DT4 via the first initialization control line GIL, and a low-level second initialization control signal GB may be supplied to the capacitive element initialization transistor DT10 via the second initialization control line GBL. As a result, the initialization transistor DT4 and the capacitive element initialization transistor DT10 may be turned on. A first initialization voltage Vint applied from the first initialization voltage line VL1 may be transferred to the gate electrode of the driving transistor DT1 via the first initialization transistor DT4, and a second initialization voltage Vaint applied from the second initialization voltage line VL2 may be transferred to the anode via the capacitive element initialization transistor DT10. As a result, the gate electrode of the driving transistor DT1 may be initialized, and an amount of charge corresponding to the difference between the driving voltage ELVDD and the second initialization voltage Vaint may be charged in the compensation capacitor Ccomp.

[0114] Thereafter, during a data write period, a low-level scan signal GW is supplied via the scan line GWL, turning on the switching transistor DT2 and the compensation transistor DT3. The switching transistor DT2 transfers the data signal Dm from the dummy data line DDL to the source electrode of the driving transistor DT1, and the driving transistor DT1 is diode-coupled by the compensation transistor DT3. As a result, a compensation voltage, which is reduced from the data signal Dm by the threshold voltage of the driving transistor DT1, is applied to the gate electrode of the driving transistor DT1.

[0115] The driving voltage ELVDD and the compensation voltage are applied to both ends of the second storage capacitor Cst2, and a charge corresponding to the voltage difference between both ends of the second storage capacitor Cst2 may be stored in the second storage capacitor Cst2.

[0116] Thereafter, during the light-emitting period, the light-emitting control signal EM supplied from the light-emitting control line EML changes from high to low, turning on the operation control transistor DT5 and the light-emitting control transistor DT6. As a result, a driving current is generated due to the voltage difference between the gate electrode voltage of the driving transistor DT1 and the driving voltage ELVDD. The driving current is supplied to the OLED of the repaired pixel via the light-emitting control transistor DT6 through the repair line RL. At this time, the current supplied to the OLED of the repaired pixel may be increased or decreased depending on the energy stored in the compensation capacitor Ccomp. That is, when the light-emitting control signal EM changes from high to low, the capacitance control transistor DT9 is turned on, and energy corresponding to the charge stored in the compensation capacitor Ccomp is supplied to the output node DNo. The resulting change in the potential of the output node DNo may change the amount of current supplied via the repair line RL.

[0117] The voltage of the source electrode of the driving transistor DT1 can be controlled by the bias voltage Vobs through the bias transistor DT8, thereby controlling the driving current and improving the brightness deviation (current deviation) and color coordinate change for each pixel.

[0118] 7 is an equivalent circuit diagram of a portion of pixels according to an embodiment of the present invention. The plurality of pixels P may include a first pixel P1, a second pixel P2, and a third pixel P3 that emit light of different colors. Fig. 7 is an equivalent circuit diagram showing the first pixel P1, the second pixel P2, and the third pixel P3 that emit light of different colors. In describing Fig. 7, descriptions that overlap with the description of the components in Fig. 5 will be omitted, and differences will be mainly described.

[0119] 7, a first pixel P1, a second pixel P2, and a third pixel P3 may share one of a plurality of control lines CL1-CLn (see FIG. 1). The first pixel P1 may be electrically connected to a first data line DL1, which is one of a plurality of data lines DL1-DLm. The second pixel P2 may be electrically connected to a second data line DL2, which is another one of the plurality of data lines DL1-DLm. The third pixel P3 may be electrically connected to a third data line DL3, which is another one of the plurality of data lines DL1-DLm.

[0120] The first pixel P1 may include a first pixel circuit PC1 and a first organic light emitting device OLED1. The first pixel circuit PC1's second-first initialization transistor T7-1 is connected between the second-first initialization voltage line VL2-1 and the anode of the first organic light emitting device OLED1 and may receive a second initialization control signal GB. The first pixel P1 may emit light of a first color. For example, the first color light may be red light.

[0121] The second pixel P2 may include a second pixel circuit PC2 and a second organic light emitting element OLED2. The second-second initialization transistor T7-2 of the second pixel circuit PC2 is connected between a second-second initialization voltage line VL2-2 and the anode of the second organic light emitting element OLED2 and may receive a second initialization control signal GB. The second pixel P2 may emit light of a second color different from the first color. For example, the second color light may be green light.

[0122] The third pixel P3 may include a third pixel circuit PC3 and a third organic light emitting device OLED3. The second-second initialization transistor T7-2 of the third pixel circuit PC3 is connected between the second-second initialization voltage line VL2-2 and the anode of the third organic light emitting device OLED3 and may receive a second initialization control signal GB. The third pixel P3 may emit light of a third color different from the first color and the second color. For example, the third color light may be blue light.

[0123] A 2-1 initialization voltage Vaint1 may be applied to the 2-1 initialization voltage line VL2-1. A 2-2 initialization voltage Vaint2 may be applied to the 2-2 initialization voltage line VL2-2. The 2-1 initialization voltage Vaint1 may have a lower level than the 2-2 initialization voltage Vaint2. For example, the 2-1 initialization voltage Vaint1 may be 0.3V (volt), and the 2-2 initialization voltage Vaint2 may be 1.5V.

[0124] The first pixel circuit PC1 of the first pixel P1 may be connected to a second-first initialization voltage line VL2-1, which receives a second-first initialization voltage Vaint1. The first pixel circuit PC1 may be electrically connected to a first organic light emitting element OLED1 that emits light of a first color. The second pixel circuit PC2 of the second pixel P2 may be connected to a second initialization voltage line VL2-2, which receives a second-second initialization voltage Vaint2 having a voltage level higher than the second-first initialization voltage Vaint1. The second pixel circuit PC2 may be electrically connected to a second organic light emitting element OLED2 that emits light of a second color. The third pixel circuit PC3 of the third pixel P3 may be connected to a second initialization voltage line VL2-2, which receives a second-second initialization voltage Vaint2. The third pixel circuit PDC3 may be electrically connected to a third organic light emitting element OLED3 that emits light of a third color. That is, the initialization voltages Vaint1 and Vaint2 may be provided differently depending on the type of pixel.

[0125] 7 exemplarily illustrates that the first pixel circuit PC1 is connected to the 2-1 initialization voltage line VL2-1, and the second pixel circuit PC2 and the third pixel circuit PC3 are connected to the 2-2 initialization voltage line VL2-2, but the initialization voltages provided to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 according to an embodiment of the present invention are not limited thereto. For example, the first pixel circuit PDC1, the second pixel circuit PDC2, and the third pixel circuit PDC3 may be respectively connected to different initialization voltage lines and provided with different initialization voltages.

[0126] Figure 8 is a layout diagram schematically showing the positions of transistors T1 to T8 and storage capacitor Cst in each pixel included in the display device 1 of Figure 1. Figures 9 to 19 are layout diagrams schematically showing components such as transistors T1 to T8 and storage capacitor Cst of the display device 1 shown in Figure 8 by layer.

[0127] 8 to 19, the display device 1 may include a first pixel P1, a second pixel P2, and a third pixel P3. The first pixel P1 may include a first pixel circuit PC1, the second pixel P2 may include a second pixel circuit PC2, and the third pixel P3 may include a third pixel circuit PC3. For convenience of explanation, some conductive patterns will be described below based on the first pixel circuit PC1, but the same components may also be arranged in the second pixel circuit PC2 and the third pixel circuit PC3.

[0128] The structures illustrated in FIGS. 8 to 19 may be repeatedly arranged in a first direction (eg, x-direction) and / or a second direction (eg, y-direction).

[0129] FIG. 9 illustrates the bottom conductive layer BML.

[0130] 8 and 9, a portion of the lower conductive layer BML has a shape corresponding to the driving transistor T1 and serves as a lower protective metal that protects a portion of the first semiconductor layer 1100 overlapping with the lower conductive layer BML. The lower conductive layer BML in each of the first to third pixels P1, P2, and P3 includes a portion extending in a first direction and a portion extending in a second direction, and therefore the lower conductive layer BML in the first to third pixels P1, P2, and P3 may be integrally formed.

[0131] The lower conductive layer BML may be electrically connected to the driving voltage line PL (FIG. 18), and therefore the same electrical signal as that applied to the driving voltage line PL may be applied to the lower conductive layer BML. That is, the driving voltage ELVDD applied to the driving voltage line PL may also be applied to the lower conductive layer BML.

[0132] The lower conductive layer BML may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. For example, the lower conductive layer BML may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). Such a lower conductive layer BML may have a multilayer structure, such as a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo.

[0133] Fig. 10 illustrates a first semiconductor layer 1100 on the lower conductive layer BML, and Fig. 11 illustrates a first conductive layer 1200 on the first semiconductor layer 1100. Fig. 12 illustrates both the first semiconductor layer 1100 and the first conductive layer 1200, and illustrates the arrangement of the drive transistor T1, the switching transistor T2, the operation control transistor T5, the light-emitting control transistor T6, the second initialization transistor T7, and the bias transistor T8.

[0134] 8 and 10 to 12, the first semiconductor layer 1100 may include a first semiconductor pattern 1110 and a second semiconductor pattern 1120. That is, the first semiconductor pattern 1110 and the second semiconductor pattern 1120 may be disposed on the same layer. Each of the first semiconductor pattern 1110 and the second semiconductor pattern 1120 may be disposed for each pixel. For example, one first semiconductor pattern 1110 and one second semiconductor pattern 1120 may be disposed for each of the first pixel P1, the second pixel P2, and the third pixel P3.

[0135] The driving transistor T1, the switching transistor T2, the operation control transistor T5, the emission control transistor T6, the second initialization transistor T7, and the bias transistor T8 may be located along the first semiconductor layer 1100. The driving transistor T1, the switching transistor T2, the operation control transistor T5, the emission control transistor T6, and the second initialization transistor T7 may be located in the first semiconductor pattern 1110. The bias transistor T8 may be located in the second semiconductor pattern 1120.

[0136] The first semiconductor layer 1100 may include a silicon semiconductor material. For example, the first semiconductor layer 1100 may include amorphous silicon or polysilicon. For example, the first semiconductor layer 1100 may include polysilicon crystallized at a low temperature. The first semiconductor layer 1100 may include a channel region overlapping the gate electrode and source and drain regions disposed on both sides of the channel region. The source and drain regions may be doped regions with impurities added thereto.

[0137] The first conductive layer 1200 may be disposed on the first semiconductor layer 1100. The first conductive layer 1200 may include a first conductive pattern 1210, a second conductive pattern 1220, an emission control line EML, a second initialization control line GBL, and a second-second initialization voltage line VL2-2. That is, the first conductive pattern 1210, the second conductive pattern 1220, the emission control line EML, the second initialization control line GBL, and the second-second initialization voltage line VL2-2 may be disposed on the same layer. The first conductive layer 1200 may be referred to as a first gate layer.

[0138] The first conductive pattern 1210 and the second conductive pattern 1220 may each have an isolated shape. The first conductive pattern 1210 and the second conductive pattern 1220 may each be arranged for each pixel. For example, one first conductive pattern 1210 and one second conductive pattern 1220 may be arranged for each of the first pixel P1, the second pixel P2, and the third pixel P3.

[0139] The first conductive pattern 1210, the second conductive pattern 1220, the light emitting control line EML, and the second initialization control line GBL overlap the first semiconductor layer 1100 and serve as gate electrodes of transistors.

[0140] The portion of the first conductive pattern 1210 overlapping with the first semiconductor pattern 1110 may be the gate electrode of the driving transistor T1. The first conductive pattern 1210 may overlap with a portion of an electrode of a second conductive layer 1300 (see FIG. 13), which will be described later, thereby forming the storage capacitor Cst shown in FIG. 8. That is, the first conductive pattern 1210 may be one electrode of the storage capacitor Cst. For example, the first conductive pattern 1210 may be a lower electrode of the storage capacitor Cst.

[0141] The portion of the second conductive pattern 1220 overlapping the first semiconductor pattern 1110 may be a gate electrode of the switching transistor T2. The second conductive pattern 1220 may be electrically connected to a scan line GWL (FIG. 17) described below and may receive a scan signal GW. That is, the scan signal GW may be applied to a pixel via the second conductive pattern 1220.

[0142] The light-emitting control line EML, the second initialization control line GBL, and the 2-2nd initialization voltage line VL2-2 may extend in a first direction (e.g., the x-direction). The light-emitting control line EML may transmit a light-emitting control signal EM to each pixel. The second initialization control line GBL may transmit a second initialization control signal GB to each pixel. The 2-2nd initialization voltage line VL2-2 may transmit a 2-2nd initialization voltage Vaint2 to the second pixel P2 and the third pixel P3, respectively.

[0143] A portion of the emission control line EML overlapping the first semiconductor pattern 1110 may be a gate electrode of the operation control transistor T5, and another portion of the emission control line EML overlapping the first semiconductor pattern 1110 may be a gate electrode of the emission control transistor T6.

[0144] The portion where the second initialization control line GBL overlaps with the first semiconductor pattern 1110 may be the gate electrode of the second initialization transistor T7.

[0145] In one embodiment, the second initialization transistor T7 of the first pixel P1 may receive a 2-1 initialization voltage Vaint1 via a 2-1 initialization voltage line VL2-1 of the third conductive layer 1500 (described below). In one embodiment, the second initialization transistor T7 of the second pixel P2 may receive a 2-2 initialization voltage Vaint2 via a 2-2 initialization voltage line VL2-2 of the first conductive layer 1200. In one embodiment, the second initialization transistor T7 of the third pixel P3 may receive a 2-2 initialization voltage Vaint2 via a 2-2 initialization voltage line VL2-2 of the first conductive layer 1200.

[0146] The portion where the second initialization control line GBL overlaps with the second semiconductor pattern 1120 may be the gate electrode of the bias transistor T8.

[0147] The first conductive layer 1200 may include a metal, an alloy, a metal nitride, or a conductive metal oxide. For example, the first conductive layer 1200 may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The first conductive layer 1200 may have a multilayer structure.

[0148] FIG. 13 illustrates a second conductive layer 1300 on the first conductive layer 1200 .

[0149] Figure 13 illustrates a second conductive layer 1300 on the first conductive layer 1200, Figure 14 illustrates a second semiconductor layer 1400 on the second conductive layer 1300, and Figure 15 illustrates a third conductive layer 1500 on the second semiconductor layer 1400. Figure 16 illustrates the second conductive layer 1300, the second semiconductor layer 1400, and the third conductive layer 1500 together, and illustrates the arrangement of the compensation transistor T3 and the first initialization transistor T4.

[0150] 8 and 13 to 16, the second conductive layer 1300 may include a third conductive pattern 1310, a fourth conductive pattern 1320, and a fifth conductive pattern 1330. That is, the third conductive pattern 1310, the fourth conductive pattern 1320, and the fifth conductive pattern 1330 may be disposed on the same layer. The second conductive layer 1300 may be referred to as a second gate layer.

[0151] The third conductive pattern 1310 may be arranged to overlap the first conductive pattern 1210. The third conductive pattern 1310 may be arranged on the first conductive pattern 1210. In one embodiment, the third conductive pattern 1310 may overlap the first conductive pattern 1210 arranged in each of the first to third pixels P1, P2, and P3, and may be integrally provided in the first to third pixels P1, P2, and P3.

[0152] The third conductive pattern 1310 may overlap the first conductive pattern 1210 to form a storage capacitor Cst (see FIG. 8). That is, the third conductive pattern 1310 may be one electrode of the storage capacitor Cst shown in FIG. 8. For example, the third conductive pattern 1310 may be an upper electrode of the storage capacitor Cst.

[0153] The third conductive pattern 1310 may have a closed opening 1310OP. The first conductive pattern 1210 may be electrically connected to a first connecting electrode 1630 (see FIG. 17) described below through the opening 1310OP of the third conductive pattern 1310.

[0154] The fourth conductive pattern 1320 and the fifth conductive pattern 1330 may each have an isolated shape. The fourth conductive pattern 1320 and the fifth conductive pattern 1330 may each be arranged for each pixel. For example, one fourth conductive pattern 1320 and one fifth conductive pattern 1330 may each be arranged for the first pixel P1, the second pixel P2, and the third pixel P3.

[0155] The fourth conductive pattern 1320 may be electrically connected to a compensation scan line GCL (see FIG. 17) described below. A compensation scan signal GC may be transmitted to the fourth conductive pattern 1320 through the compensation scan line GCL. An overlapping portion of the fourth conductive pattern 1320 and a third semiconductor pattern 1410 described below may be a lower gate electrode of the compensation transistor T3.

[0156] The fifth conductive pattern 1330 may be electrically connected to a first initialization control line GIL (see FIG. 17) described below. A first initialization control signal GI may be transmitted to the fifth conductive pattern 1330 through the first initialization control line GIL. An overlapping portion of the fifth conductive pattern 1330 and a third semiconductor pattern 1410 described below may be a lower gate electrode of the first initialization transistor T4.

[0157] The second conductive layer 1300 may include a metal, an alloy, a metal nitride, or a conductive metal oxide. For example, the second conductive layer 1300 may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The second conductive layer 1300 may have a multilayer structure.

[0158] The second semiconductor layer 1400 may be disposed on the second conductive layer 1300. The second semiconductor layer 1400 may include a third semiconductor pattern 1410. The third semiconductor pattern 1410 may be disposed for each pixel. For example, one third semiconductor pattern 1410 may be disposed for each of the first pixel P1, the second pixel P2, and the third pixel P3. A compensation transistor T3 and a first initialization transistor T4 may be located in the third semiconductor pattern 1410.

[0159] The second semiconductor layer 1400 may include an oxide semiconductor material. For example, the second semiconductor layer 1400 may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the second semiconductor layer 1400 may be an ITZO (InSnZnO) semiconductor layer or an IGZO (InGaZnO) semiconductor layer. Oxide semiconductors have a wide band gap (approximately 3.1 eV), high carrier mobility, and low leakage current, which provides the advantages of minimal voltage drop even with long operating times and minimal luminance change due to voltage drop even at low operating frequencies. The second semiconductor layer 1400 may include a channel region overlapping the gate electrode, and a source region and a drain region disposed on both sides of the channel region.

[0160] The third conductive layer 1500 may be disposed on the second semiconductor layer 1400. The third conductive layer 1500 may include a sixth conductive pattern 1510, a seventh conductive pattern 1520, a repair line RL, and a 2-1 initialization voltage line VL2-1. That is, the sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1 initialization voltage line VL2-1 may be disposed in the same layer. The third conductive layer 1500 may be referred to as a third gate layer.

[0161] The sixth conductive pattern 1510 and the seventh conductive pattern 1520 may each have an isolated shape. The sixth conductive pattern 1510 and the seventh conductive pattern 1520 may each be arranged for each pixel. For example, one sixth conductive pattern 1510 and one seventh conductive pattern 1520 may be arranged for each of the first pixel P1, the second pixel P2, and the third pixel P3.

[0162] The sixth conductive pattern 1510 and the seventh conductive pattern 1520 overlap the second semiconductor layer 1400 and serve as gate electrodes of the transistors.

[0163] The portion of the sixth conductive pattern 1510 overlapping with the third semiconductor pattern 1410 may be a gate electrode of the compensation transistor T3. For example, the portion of the sixth conductive pattern 1510 overlapping with the third semiconductor pattern 1410 may be an upper gate electrode of the compensation transistor T3. The sixth conductive pattern 1510 may be electrically connected to a compensation scan line GCL (see FIG. 17) described below and may receive a compensation scan signal GC.

[0164] The portion of the seventh conductive pattern 1520 overlapping the third semiconductor pattern 1410 may be the gate electrode of the first initialization transistor T4. For example, the portion of the seventh conductive pattern 1512 overlapping the third semiconductor pattern 1410 may be the upper gate electrode of the first initialization transistor T4. The seventh conductive pattern 1520 may be electrically connected to a first initialization control line GIL (see FIG. 17) described below and may receive a first initialization control signal GI.

[0165] The repair line RL may extend in a first direction (e.g., the x-direction). The repair line RL may be connected to a dummy pixel DP (see FIGS. 1 to 3) and connected to a light-emitting element of a defective pixel among the pixels P. The repair line RL may be disposed to overlap a 1-1 pixel connecting electrode 1620a electrically connected to a first pixel electrode 210a of a first pixel P1, a 1-2 pixel connecting electrode 1620b electrically connected to a second pixel electrode 210b of a second pixel P2, and a 1-3 pixel connecting electrode 1620c electrically connected to a third pixel electrode 210c of a third pixel P3, which will be described later. For example, if the first pixel P1 is a defective pixel, a laser may be irradiated onto the area where the 1-1 pixel connecting electrode 1620a and the repair line RL overlap to connect the 1-1 pixel connecting electrode 1620a and the repair line RL, and the repair line RL may be electrically connected to the first pixel electrode 210a of the first pixel P1.

[0166] The 2-1st initialization voltage line VL2-1 may extend in a first direction (eg, the x-direction) and may transmit a 2-1st initialization voltage Vaint1 to the first pixel P1.

[0167] The third conductive layer 1500 may include a metal, an alloy, a metal nitride, or a conductive metal oxide. For example, the third conductive layer 1500 may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The third conductive layer 1500 may have a multilayer structure.

[0168] Figure 17 illustrates a fourth conductive layer 1600 on the third conductive layer 1500. Figure 18 illustrates a fifth conductive layer 1700 on the fourth conductive layer 1600. Figure 19 illustrates a pixel electrode layer 2000 on the fifth conductive layer 1700. Figure 20A is a layout diagram showing some layers of a display device according to an embodiment of the present invention. Figure 20A illustrates the third conductive layer 1500, the fourth conductive layer 1600, the fifth conductive layer 1700, and the pixel electrode layer 2000.

[0169] 8 and 17 to 20A, the fourth conductive layer 1600 may include a voltage transmission line 1610, a first pixel connecting electrode 1620, a first connecting electrode 1630, a second connecting electrode 1640, a third connecting electrode 1650, a fourth connecting electrode 1660, a fifth connecting electrode 1670, a first initialization voltage line VL1, a first initialization control line GIL, a scan line GWL, a compensation scan line GCL, and a bias voltage line VL3. That is, the components included in the fourth conductive layer 1600 may be arranged on the same layer. The fourth conductive layer 1600 may be referred to as a first source / drain layer or a first connecting electrode layer.

[0170] The voltage transmission line 1610 may extend in a first direction (e.g., the x-direction). The voltage transmission line 1610 may be electrically connected to each of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 and may transmit a voltage thereto. A portion of the voltage transmission line 1610 may overlap with the repair line RL. Because a portion of the voltage transmission line 1610 overlaps with the repair line RL, a parasitic capacitor may be formed in the overlapping region between the voltage transmission line 1610 and the repair line RL.

[0171] In one embodiment, the voltage transmission line 1610 may be electrically connected to a voltage line transmitting a DC voltage (or a constant voltage). For example, the voltage transmission line 1610 may be electrically connected to a voltage line transmitting a driving voltage ELVDD, a common voltage ELVSS, a first initialization voltage Vint, a 2-1st initialization voltage Vaint1, or a 2-2nd initialization voltage Vaint2. In the embodiment described with reference to FIGS. 8 and 20A, the voltage transmission line 1610 is exemplarily illustrated as being electrically connected to a driving voltage line PL (described later) to transmit the driving voltage ELVDD.

[0172] In one embodiment, the voltage transmission line 1610 may be disposed in the same layer as the first pixel connecting electrode 1620. However, embodiments of the present invention are not limited thereto, and in other embodiments, the voltage transmission line 1610 and the first pixel connecting electrode 1620 may be disposed in different layers.

[0173] The voltage transmission line 1610 may be electrically connected to the lower conductive layer BML (see FIG. 9) through a first-1 contact hole CNT1a. The voltage transmission line 1610 may be electrically connected to the third conductive pattern 1310 (see FIG. 16) through a first-2 contact hole CNT1b. The voltage transmission line 1610 may be electrically connected to the first semiconductor pattern 1110 (see FIG. 10) through a first-3 contact hole CNT1c. A driving voltage ELVDD may be transmitted to the storage capacitor Cst and the operation control transistor T5 through the voltage transmission line 1610.

[0174] The first pixel connecting electrode 1620 may be spaced apart from the voltage transmission line 1610. The first pixel connecting electrode 1620 may be electrically insulated from the voltage transmission line 1610.

[0175] The first pixel connecting electrode 1620 may be disposed for each pixel. For example, one first pixel connecting electrode 1620 may be disposed for each of the first pixel P1, the second pixel P2, and the third pixel P3. For example, the 1-1 pixel connecting electrode 1620a may be disposed for the first pixel P1, the 1-2 pixel connecting electrode 1620b may be disposed for the second pixel P2, and the 1-3 pixel connecting electrode 1620c may be disposed for the third pixel P3. The 1-1 pixel connecting electrode 1620a, the 1-2 pixel connecting electrode 1620b, and the 1-3 pixel connecting electrode 1620c may be disposed apart from the voltage transmission line 1610.

[0176] The first pixel connecting electrode 1620 may be electrically connected to the organic light emitting element of each pixel. For example, the 1-1 pixel connecting electrode 1620a may be electrically connected to the organic light emitting element of the first pixel P1, the 1-2 pixel connecting electrode 1620b may be electrically connected to the organic light emitting element of the second pixel P2, and the 1-3 pixel connecting electrode 1620c may be electrically connected to the organic light emitting element of the third pixel P3.

[0177] The first pixel connecting electrode 1620 may be electrically connected to the pixel electrode of the organic light emitting device of each pixel via a second pixel connecting electrode 1710 (described below). For example, the 1-1 pixel connecting electrode 1620a may be electrically connected to the first pixel electrode 210a of the organic light emitting device of the first pixel P1 via the 2-1 pixel connecting electrode 1710a, the 1-2 pixel connecting electrode 1620b may be electrically connected to the second pixel electrode 210b of the organic light emitting device of the second pixel P2 via the 2-2 pixel connecting electrode 1710b, and the 1-3 pixel connecting electrode 1620c may be electrically connected to the third pixel electrode 210c of the organic light emitting device of the third pixel P3 via the 2-3 pixel connecting electrode 1710c.

[0178] At least a portion of the 1-1th pixel connecting electrode 1620a may overlap with the repair line RL, at least a portion of the 1-2nd pixel connecting electrode 1620b may overlap with the repair line RL, and at least a portion of the 1-3rd pixel connecting electrode 1620c may overlap with the repair line RL. Because the 1-1st pixel connecting electrode 1620a, the 1-2nd pixel connecting electrode 1620b, and the 1-3rd pixel connecting electrode 1620c each overlap with the repair line RL, a parasitic capacitor may be formed in the overlapping region between the 1st pixel connecting electrode 1620 and the repair line RL.

[0179] The first pixel connecting electrode 1620 may be electrically connected to the first semiconductor pattern 1110 through the second contact hole CNT2. For example, the 1-1th pixel connecting electrode 1620a may be electrically connected to the first semiconductor pattern 1110 through the second contact hole CNT2. The first pixel connecting electrode 1620 may electrically connect the first semiconductor pattern 1110 and the organic light emitting element of each pixel.

[0180] The first linking electrode 1630, the second linking electrode 1640, the third linking electrode 1650, the fourth linking electrode 1660, and the fifth linking electrode 1670 may each have an isolated shape. The first linking electrode 1630, the second linking electrode 1640, the third linking electrode 1650, the fourth linking electrode 1660, and the fifth linking electrode 1670 may be disposed for each pixel. For example, one first linking electrode 1630, the second linking electrode 1640, the third linking electrode 1650, the fourth linking electrode 1660, and the fifth linking electrode 1670 may be disposed for each of the first pixel P1, the second pixel P2, and the third pixel P3.

[0181] The first connecting electrode 1630 may electrically connect the first conductive pattern 1210 and the third semiconductor pattern 1410. The first connecting electrode 1630 may be electrically connected to the first conductive pattern 1210 through a 3-1 contact hole CNT3a. The first connecting electrode 1630 may be electrically connected to the third semiconductor pattern 1410 through a 3-2 contact hole CNT3b. The first connecting electrode 1630 may electrically connect the driving transistor T1 and the compensation transistor T3. The first connecting electrode 1630 may electrically connect the storage capacitor Cst and the compensation transistor T3.

[0182] The second connecting electrode 1640 may electrically connect the first semiconductor pattern 1110 and the third semiconductor pattern 1410. The second connecting electrode 1640 may be electrically connected to the first semiconductor pattern 1110 through a 4-1 contact hole CNT4a. The second connecting electrode 1640 may be electrically connected to the third semiconductor pattern 1410 through a 4-2 contact hole CNT4b. The second connecting electrode 1640 may electrically connect the driving transistor T1 and the compensation transistor T3. The second connecting electrode 1640 may electrically connect the emission control transistor T6 and the compensation transistor T3.

[0183] The third connecting electrode 1650 may be electrically connected to the first semiconductor pattern 1110 (see FIG. 10) through a fifth contact hole CNT5. For example, in the first pixel circuit PC1, the third connecting electrode 1650 may be electrically connected to a first data line DL1 (described below). That is, in the first pixel circuit PC1, the third connecting electrode 1650 may transfer a data signal Dm applied through the first data line DL1 to the first semiconductor pattern 1110.

[0184] The fourth connecting electrode 1660 may electrically connect the first semiconductor pattern 1110 and the second semiconductor pattern 1120. The fourth connecting electrode 1660 may be electrically connected to the first semiconductor pattern 1110 through a 6-1 contact hole CNT6a. The fourth connecting electrode 1660 may be electrically connected to the second semiconductor pattern 1120 through a 6-2 contact hole CNT6b. The fourth connecting electrode 1660 may electrically connect the bias transistor T8 and the operation control transistor T5.

[0185] In the first pixel circuit PC1, the fifth connecting electrode 1670 may electrically connect the first semiconductor pattern 1110 and the 2-1 initialization voltage line VL2-1. In the second pixel circuit PC2 and the third pixel circuit PC3, the fifth connecting electrode 1670 may electrically connect the first semiconductor pattern 1110 and the 2-2 initialization voltage line VL2-2.

[0186] In the first pixel circuit PC1, the fifth connecting electrode 1670 may be electrically connected to the first semiconductor pattern 1110 through a 7-1 contact hole CNT7a and may be electrically connected to a 2-1 initialization voltage line VL2-1 through a 7-2 contact hole CNT7b. A 2-1 initialization voltage Vaint1 may be transmitted to the first semiconductor pattern 1110 of the first pixel P1 via the fifth connecting electrode 1670. The fifth connecting electrode 1670 may transmit the 2-1 initialization voltage Vaint1 to the second initialization transistor T7 of the first pixel P1.

[0187] In each of the second pixel circuit PC2 and the third pixel circuit PC3, the fifth connecting electrode 1670 may be electrically connected to the first semiconductor pattern 1110 through a 7-1 contact hole CNT7a and may be electrically connected to the 2-2 initialization voltage line VL2-2 through a 7-2 contact hole CNT7b. In each of the second pixel P2 and the third pixel P3, the 2-2 initialization voltage Vaint2 may be transmitted to the first semiconductor pattern 1110 via the fifth connecting electrode 1670. The fifth connecting electrode 1670 may transmit the 2-2 initialization voltage Vaint2 to the second initialization transistor T7 of the second pixel P2 and the third pixel P3.

[0188] The first initialization control line GIL, the compensation scan line GCL, the bias voltage line VL3, and the first initialization voltage line VL1 may extend in a first direction (eg, the x direction).

[0189] The first initialization control line GIL may transmit a first initialization control signal GI. The first initialization control line GIL may electrically connect the fifth conductive pattern 1330 and the seventh conductive pattern 1520. The first initialization control line GIL may be electrically connected to the fifth conductive pattern 1330 through an 8-1 contact hole CNT8a. The first initialization control line GIL may be electrically connected to the seventh conductive pattern 1520 through an 8-2 contact hole CNT8b. That is, the first initialization control signal GI may be transmitted to each of the fifth conductive pattern 1330 and the seventh conductive pattern 1520.

[0190] The scan line GWL may transmit a scan signal GW to each pixel. The scan line GWL may be electrically connected to the second conductive pattern 1220 through a ninth contact hole CNT9. That is, the scan signal GW may be transmitted to the second conductive pattern 1220. The scan line GWL may transmit the scan signal GW to the gate electrode of the switching transistor T2.

[0191] The compensation scan line GCL may transmit a compensation scan signal GC to each pixel. The compensation scan line GCL may electrically connect the fourth conductive pattern 1320 and the sixth conductive pattern 1510. The compensation scan line GCL may be electrically connected to the fourth conductive pattern 1320 through a 10-1 contact hole CNT10a. The compensation scan line GCL may be electrically connected to the sixth conductive pattern 1510 through a 10-2 contact hole CNT10b. That is, the compensation scan signal GC may be transmitted to each of the fourth conductive pattern 1320 and the sixth conductive pattern 1510.

[0192] A bias voltage Vobs may be applied to the bias voltage line VL3. The bias voltage line VL3 may be electrically connected to the second semiconductor pattern 1120 through the eleventh contact hole CNT11. That is, the bias voltage Vobs may be transmitted to the second semiconductor pattern 1120.

[0193] A first initialization voltage Vint may be applied to the first initialization voltage line VL1. The first initialization voltage line VL1 may be electrically connected to the third semiconductor pattern 1410 through the twelfth contact hole CNT12. That is, the first initialization voltage Vint may be applied to the third semiconductor pattern 1410.

[0194] The fourth conductive layer 1600 may include a metal, an alloy, a metal nitride, or a conductive metal oxide. For example, the fourth conductive layer 1600 may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The fourth conductive layer 1600 may have a multilayer structure.

[0195] The fifth conductive layer 1700 may be disposed on the fourth conductive layer 1600. The fifth conductive layer 1700 may include a second pixel connecting electrode 1710, a driving voltage line PL, a first data line DL1, a second data line DL2, and a third data line DL3. That is, the second pixel connecting electrode 1710, the driving voltage line PL, the first data line DL1, the second data line DL2, and the third data line DL3 may be disposed on the same layer. The fifth conductive layer 1700 may be referred to as a second source / drain layer or a second connecting electrode layer.

[0196] The second pixel connecting electrode 1710 may be disposed for each pixel. For example, one second pixel connecting electrode 1710 may be disposed for each of the first pixel P1, the second pixel P2, and the third pixel P3. For example, the 2-1 pixel connecting electrode 1710a may be disposed for the first pixel P1, the 2-2 pixel connecting electrode 1710b may be disposed for the second pixel P2, and the 2-3 pixel connecting electrode 1710c may be disposed for the third pixel P3.

[0197] The second pixel connecting electrode 1710 may be disposed so that at least a portion thereof overlaps with the first pixel connecting electrode 1620. At least a portion of the 2-1 pixel connecting electrode 1710a may overlap with the 1-1 pixel connecting electrode 1620a. At least a portion of the 2-2 pixel connecting electrode 1710b may overlap with the 1-2 pixel connecting electrode 1620b. At least a portion of the 2-3 pixel connecting electrode 1710c may overlap with the 1-3 pixel connecting electrode 1620c.

[0198] The second pixel connecting electrodes 1710 may be electrically connected to the organic light emitting element of each pixel. For example, the 2-1 pixel connecting electrode 1710a may be electrically connected to the organic light emitting element of the first pixel P1, the 2-2 pixel connecting electrode 1710b may be electrically connected to the organic light emitting element of the second pixel P2, and the 2-3 pixel connecting electrode 1710c may be electrically connected to the organic light emitting element of the third pixel P3.

[0199] The second pixel connecting electrode 1710 may be electrically connected to the first pixel connecting electrode 1620. For example, the 2-1 pixel connecting electrode 1710a may be electrically connected to the 1-1 pixel connecting electrode 1620a through the 13-1 contact hole CNT13a. For example, the 2-2 pixel connecting electrode 1710b may be electrically connected to the 1-2 pixel connecting electrode 1620b through the 13-2 contact hole CNT13b. For example, the 2-3 pixel connecting electrode 1710c may be electrically connected to the 1-3 pixel connecting electrode 1620c through the 13-3 contact hole CNT13c.

[0200] The second pixel connecting electrode 1710 may electrically connect the first pixel connecting electrode 1620 and the pixel electrode of the organic light emitting element of each pixel. For example, the 2-1 pixel connecting electrode 1710a may electrically connect the 1-1 pixel connecting electrode 1620a to the first pixel electrode 210a of the first pixel P1. For example, the 2-2 pixel connecting electrode 1710b may electrically connect the 1-2 pixel connecting electrode 1620b to the second pixel electrode 210b of the second pixel P2. For example, the 2-3 pixel connecting electrode 1710c may electrically connect the 1-3 pixel connecting electrode 1620c to the third pixel electrode 210c of the third pixel P3.

[0201] The driving voltage line PL may apply a driving voltage ELVDD to each pixel. The driving voltage line PL may extend in a second direction (e.g., the y direction). The driving voltage line PL may be electrically connected to the voltage transmission line 1610 through a fourteenth contact hole CNT14.

[0202] The first, second, and third data lines DL1, DL2, and DL3 may be electrically connected to the first, second, and third pixel circuits PC1, PC2, and PC3, respectively. The first, second, and third data lines DL1, DL2, and DL3 may transmit a data signal Dm to the first, second, and third pixels P1, P2, and P3, respectively. The first, second, and third data lines DL1, DL2, and DL3 may extend in a second direction (e.g., the y-direction).

[0203] In the first pixel circuit PC1, the first data line DL1 may be electrically connected to the third connecting electrode 1650 through the fifteenth contact hole CNT15. ​​Similarly, in the second pixel circuit PC2, the second data line DL2 may be electrically connected to the third connecting electrode 1650 of the second pixel circuit PC2, and in the third pixel circuit PC3, the third data line DL3 may be electrically connected to the third connecting electrode 1650 of the third pixel circuit PC3. Since the third connecting electrode 1650 is electrically connected to the first semiconductor pattern 1110 (see FIG. 10), a data signal Dm applied to the first data line DL1 may be transmitted to the first semiconductor pattern 1110. The third connecting electrode 1650 may transmit the data signal Dm to the switching transistor T2.

[0204] The fifth conductive layer 1700 may include a metal, an alloy, a metal nitride, or a conductive metal oxide. For example, the fifth conductive layer 1700 may include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The fifth conductive layer 1700 may have a multilayer structure.

[0205] A pixel electrode layer 2000 may be disposed on the fifth conductive layer 1700. The pixel electrode layer 2000 may include a first pixel electrode 210a of the organic light-emitting element of the first pixel P1, a second pixel electrode 210b of the organic light-emitting element of the second pixel P2, and a third pixel electrode 210c of the organic light-emitting element of the third pixel P3.

[0206] The first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may be spaced apart from each other. Each of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may be a (semi-)transparent electrode or a reflective electrode. For example, each of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may include a reflective layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof, and a transparent or semi-transparent electrode layer disposed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). For example, the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may each have a three-layer structure of ITO / Ag / ITO.

[0207] The first pixel electrode 210a may be electrically connected to the 2-1 pixel connecting electrode 1710a through a 16th contact hole CNT16. The second pixel electrode 210b may be electrically connected to the 2-2 pixel connecting electrode 1710b through a 17th contact hole CNT17. The third pixel electrode 210c may be electrically connected to the 2-3 pixel connecting electrode 1710c through an 18th contact hole CNT18.

[0208] The first to third pixel electrodes 210a, 210b, and 210c of each pixel may be electrically connected to the first semiconductor pattern 1110 (see FIG. 10) through a first pixel connecting electrode 1620 and a second pixel connecting electrode 1710. For example, the first pixel electrode 210a may be electrically connected to the first semiconductor pattern 1110 through a 1-1th pixel connecting electrode 1620a and a 2-1st pixel connecting electrode 1710a. The first pixel connecting electrode 1620 and the second pixel connecting electrode 1710 may electrically connect the organic light emitting element and the second initialization transistor T7 of each pixel.

[0209] Figure 20B is an enlarged view of region "A" in Figure 20A. For convenience of illustration, the first to third pixel electrodes 210a, 210b, and 210c are omitted in Figure 20B.

[0210] 20A and 20B, the repair line RL may include a portion overlapping with each of the 1-1th pixel connecting electrode 1620a, the 1-2nd pixel connecting electrode 1620b, and the 1-3rd pixel connecting electrode 1620c, and a portion overlapping with the voltage transmission line 1610.

[0211] For example, the repair line RL may include a 1-1 portion RL1a overlapping with the 1-1 pixel connecting electrode 1620a, a 1-2 portion RL1b overlapping with the 1-2 pixel connecting electrode 1620b, and a 1-3 portion RL1c overlapping with the 1-3 pixel connecting electrode 1620c. The 1-1 portion RL1a of the repair line RL may be a portion to be irradiated with a laser during the repair process if the first pixel P1 is a defective pixel. The 1-2 portion RL1b of the repair line RL may be a portion to be irradiated with a laser during the repair process if the second pixel P2 is a defective pixel. The 1-3 portion RL1c of the repair line RL may be a portion to be irradiated with a laser during the repair process if the third pixel P3 is a defective pixel.

[0212] For example, the repair line RL may include a second portion RL2 overlapping with the voltage transmission line 1610. In one embodiment, the second portion RL2 of the repair line RL overlapping with the voltage transmission line 1610 may include a 2-1 portion RL2a arranged between the 1-1 portion RL1a and the 1-2 portion RL1b, and a 2-2 portion RL2b arranged between the 1-2 portion RL1b and the 1-3 portion RL1c.

[0213] The 1-1th pixel connecting electrode 1620a may include a portion 1620ap overlapping with the repair line RL, the 1-2nd pixel connecting electrode 1620b may include a portion 1620bp overlapping with the repair line RL, and the 1-3rd pixel connecting electrode 1620c may include a portion 1620cp overlapping with the repair line RL.

[0214] The voltage transmission line 1610 may include a first portion 1610pa and a second portion 1610pb overlapping the repair line RL. The first portion 1610pa of the voltage transmission line 1610 may be located between a portion 1620ap of the 1-1th pixel connecting electrode 1620a overlapping the repair line RL and a portion 1620bp of the 1-2nd pixel connecting electrode 1620b overlapping the repair line RL. The second portion 1610pb of the voltage transmission line 1610 may be located between a portion 1620bp of the 1-2th pixel connecting electrode 1620b overlapping the repair line RL and a portion 1620cp of the 1-3rd pixel connecting electrode 1620c overlapping the repair line RL.

[0215] The area (size) of the first portion 1610pa of the voltage transmission wiring 1610 is larger than the area (size) of the portion 1620ap of the 1-1th pixel connecting electrode 1620a that overlaps with the repair line RL. The area (size) of the first portion 1610pa of the voltage transmission wiring 1610 is larger than the area (size) of the portion 1620bp of the 1-2th pixel connecting electrode 1620b that overlaps with the repair line RL. The area (size) of the first portion 1610pa of the voltage transmission wiring 1610 is larger than the area (size) of the portion 1620cp of the 1-3th pixel connecting electrode 1620c that overlaps with the repair line RL.

[0216] The area (size) of the second portion 1610pb of the voltage transmission wiring 1610 is larger than the area (size) of the portion 1620ap of the 1-1th pixel connecting electrode 1620a that overlaps with the repair line RL. The area (size) of the second portion 1610pb of the voltage transmission wiring 1610 is larger than the area (size) of the portion 1620bp of the 1-2nd pixel connecting electrode 1620b that overlaps with the repair line RL. The area (size) of the second portion 1610pb of the voltage transmission wiring 1610 is larger than the area (size) of the portion 1620cp of the 1-3rd pixel connecting electrode 1620c that overlaps with the repair line RL.

[0217] The width W2a of the first portion 1610pa of the voltage transmission line 1610 along the first direction (e.g., the x direction) is larger than the width W1a of the portion 1620ap of the 1-1 pixel connecting electrode 1620a that overlaps with the repair line RL along the first direction (e.g., the x direction). In other words, the width W2a of the 2-1 portion RL2a of the repair line RL along the first direction (e.g., the x direction) is larger than the width W1a of the 1-1 portion RL1a along the first direction (e.g., the x direction).

[0218] The width W2a of the first portion 1610pa of the voltage transmission line 1610 along the first direction (e.g., the x direction) is larger than the width W1b of the first-2 pixel connecting electrode 1620b along the first direction (e.g., the x direction) of the portion 1620bp that overlaps with the repair line RL. In other words, the width W2a of the 2-1 portion RL2a of the repair line RL along the first direction (e.g., the x direction) is larger than the width W1b of the 1-2 portion RL1b along the first direction (e.g., the x direction).

[0219] The width W2a of the voltage transmission line 1610 along the first direction (e.g., the x direction) at the first portion 1610pa is larger than the width W1c of the 1-3 pixel connecting electrode 1620c along the first direction (e.g., the x direction) at the portion 1620cp that overlaps with the repair line RL. In other words, the width W2a of the 2-1 portion RL2a of the repair line RL along the first direction (e.g., the x direction) is larger than the width W1c of the 1-3 portion RL1c along the first direction (e.g., the x direction).

[0220] The width W2b of the voltage transmission line 1610 in the first direction (e.g., x-direction) at the second portion 1610pb is larger than the width W1a of the 1-1 pixel connecting electrode 1620a in the first direction (e.g., x-direction) at the portion 1620ap that overlaps with the repair line RL. In other words, the width W2b of the 2-2 portion RL2b of the repair line RL in the first direction (e.g., x-direction) is larger than the width W1a of the 1-1 portion RL1a in the first direction (e.g., x-direction).

[0221] The width W2b of the voltage transmission line 1610 in the first direction (e.g., x-direction) at the second portion 1610pb is larger than the width W1b of the 1-2nd pixel connecting electrode 1620b in the first direction (e.g., x-direction) at the portion 1620bp that overlaps with the repair line RL. In other words, the width W2b of the 2-2nd portion RL2b of the repair line RL in the first direction (e.g., x-direction) is larger than the width W1b of the 1-2nd pixel connecting electrode 1620b in the first direction (e.g., x-direction) at the portion 1620bp that overlaps with the repair line RL.

[0222] The width W2b of the second portion 1610pb of the voltage transmission line 1610 along the first direction (e.g., the x direction) is larger than the width W1c of the portion 1620cp of the first-third pixel connecting electrode 1620c that overlaps with the repair line RL along the first direction (e.g., the x direction). In other words, the width W2b of the 2-2 portion RL2b of the repair line RL along the first direction (e.g., the x direction) is larger than the width W1c of the portion 1620cp of the first-third pixel connecting electrode 1620c that overlaps with the repair line RL along the first direction (e.g., the x direction).

[0223] In the display device 1 according to an embodiment of the present invention, the voltage transmission line 1610 may be formed to overlap the repair line RL over an area larger than the area of ​​the overlapping region of the first pixel connecting electrode 1620 and the repair line RL. This may reduce the influence of a parasitic capacitor formed by the overlapping region of the pixel connecting electrode 1620 and the repair line RL on adjacent pixels. Specifically, this may reduce the coupling between the parasitic capacitors formed in the overlapping region of the first pixel connecting electrode 1620 and the repair line RL in a defective pixel and a pixel adjacent to the defective pixel. This may reduce the brightness difference of the display device 1 due to voltage, thereby improving the display quality of the display device 1. In particular, when the organic light emitting device included in each pixel has a tandem structure in which two light emitting units are connected in series, this may significantly reduce the influence of the coupling between the parasitic capacitors formed in the overlapping region of the first pixel connecting electrode 1620 and the repair line RL in a defective pixel and a pixel adjacent to the defective pixel.

[0224] FIG. 21A is a layout diagram showing some layers of a display device according to another embodiment of the present invention. FIG. 21A illustrates a modified embodiment of the embodiment described with reference to FIGS. 8 to 20B. Like FIG. 20A, FIG. 21A also illustrates a third conductive layer 1500, a fourth conductive layer 1600, a fifth conductive layer 1700, and a pixel electrode layer 2000. In FIG. 21A, the lower conductive layer BML, the first semiconductor layer 1100, the first conductive layer 1200, the second conductive layer 1300, and the second semiconductor layer 1400 are omitted for convenience of explanation and may be the same as those described in FIGS. 9 to 14. FIG. 21B is an enlarged view of region "B" in FIG. 21A.

[0225] 21A and 21B show a modified embodiment of the embodiment described based on FIGS. 20A and 20B, and the following description will focus on the differences and omit redundant explanations.

[0226] 21A and 21B, the repair line RL may include portions having different widths in a second direction (e.g., the y direction). For example, the width of the portion overlapping with the voltage transmission line 1610 in the second direction (e.g., the y direction) is wider than the width of the portions of the repair line RL overlapping with the 1-1 pixel connecting electrode 1620a, the 1-2 pixel connecting electrode 1620b, and the 1-3 pixel connecting electrode 1620c in the second direction (e.g., the y direction).

[0227] For example, the width W4 of the 2-1 portion RL2a of the repair line RL along the second direction (e.g., the y direction) is wider than the width W3 of the 1-1 portion RL1a along the second direction (e.g., the y direction). For example, the width W4 of the 2-1 portion RL2a of the repair line RL along the second direction (e.g., the y direction) is wider than the width W3 of the 1-2 portion RL1b of the repair line RL along the second direction (e.g., the y direction). For example, the width W4 of the 2-1 portion RL2a of the repair line RL along the second direction (e.g., the y direction) is wider than the width W3 of the 1-3 portion RL1c of the repair line RL along the second direction (e.g., the y direction). Similarly, the width along the second direction (e.g., the y direction) of the 2-2 portion RL2b of the repair line RL is wider than the width W3 along the second direction (e.g., the y direction) of the 1-1 portion RL1a, the 1-2 portion RL1b, and / or the 1-3 portion RL1c.

[0228] The "width" of a component created herein may be defined as the maximum width or average width of the component. In one embodiment, the widths of the first-first portion RL1a, the first-second portion RL1b, and the first-third portion RL1c of the repair line RL along the second direction are illustrated as being the same, but are not limited thereto. Also, the widths of the second-first portion RL2a and the second-second portion RL2b of the repair line RL along the second direction are illustrated as being the same, but are not limited thereto. However, even if the widths along the second direction of the 1-1 portion RL1a, the 1-2 portion RL1b, and the 1-3 portion RL1c of the repair line RL are different from each other, and the widths along the second direction of the 2-1 portion RL2a and the 2-2 portion RL2b are different from each other, the widths along the second direction of the 2-1 portion RL2a and the 2-2 portion RL2b are larger than the widths along the second direction of the 1-1 portion RL1a, the 1-2 portion RL1b, and the 1-3 portion RL1c.

[0229] The width W4 of the first portion 1610pa of the voltage transmission wiring 1610 along the second direction (e.g., the y direction) is wider than the width W3 of the portion 1620ap of the 1-1th pixel connecting electrode 1620a that overlaps with the repair line RL along the second direction (e.g., the y direction). The width W4 of the first portion 1610pa of the voltage transmission wiring 1610 along the second direction (e.g., the y direction) is wider than the width W3 of the portion 1620bp of the 1-2th pixel connecting electrode 1620b that overlaps with the repair line RL along the second direction (e.g., the y direction). The width W4 of the first portion 1610pa of the voltage transmission wiring 1610 along the second direction (e.g., the y direction) is wider than the width W3 of the portion 1620cp of the 1-3th pixel connecting electrode 1620c that overlaps with the repair line RL along the second direction (e.g., the y direction). Similarly, the width along the second direction (e.g., the y direction) of the second portion 1610pb of the voltage transmission wiring 1610 is wider than the width along the second direction of the portion 1620ap of the 1-1 pixel connecting electrode 1620a that overlaps with the repair line RL, the width along the second direction of the portion 1620bp of the 1-2 pixel connecting electrode 1620b that overlaps with the repair line RL, and / or the width along the second direction of the portion 1620cp of the 1-3 pixel connecting electrode 1620c that overlaps with the repair line RL.

[0230] Fig. 22 is a cross-sectional view schematically illustrating a cross section of the display unit 10 of the display device 1 according to an embodiment. Fig. 22 schematically illustrates a portion of the cross section corresponding to the first pixel P1 in the display unit 10 of the display device 1 according to an embodiment described with reference to Figs. 8 to 20B.

[0231] 22, the display device 1 may include a substrate 100, at least one thin film transistor TFT1, TFT2 disposed on the substrate 100, a repair line RL, a first organic light emitting element OLED1, and an encapsulating member 300.

[0232] The substrate 100 may include glass, metal, or a polymer resin. In one embodiment, the substrate 100 may be flexible or bendable. In such a case, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 may have a multilayer structure including two layers of such polymer resins and a barrier layer containing an inorganic material (such as silicon oxide, silicon nitride, or silicon oxynitride) sandwiched between the two layers.

[0233] A bottom conductive layer BML may be disposed on the substrate 100 .

[0234] The display device 1 may include a buffer layer 102 disposed on the lower conductive layer BML. The buffer layer 102 may prevent metal atoms or impurities from diffusing from the substrate 100 to the first semiconductor layer 1100 (see FIG. 10) located thereon. The buffer layer 102 may include an insulating material. For example, the buffer layer 102 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0235] The first thin film transistor TFT1 may be disposed on the buffer layer 102. The first thin film transistor TFT1 may include a first active layer Act1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1. The first thin film transistor TFT1 may be electrically connected to the first organic light emitting element OLED1. In one embodiment, the first thin film transistor TFT1 may be the light emitting control transistor T6 (see FIG. 5).

[0236] A first semiconductor layer 1100 (see FIG. 10) may be disposed on the buffer layer 102. A first active layer Act1 of the first thin film transistor TFT1 may be disposed on the buffer layer 102.

[0237] In one embodiment, the first active layer Act1 of the first thin film transistor TFT1 may correspond to the first semiconductor pattern 1110 of the first semiconductor layer 1100. The first active layer Act1 of the first thin film transistor TFT1 may include a silicon semiconductor material. For example, the first active layer Act1 may include amorphous silicon or polysilicon. For example, the first active layer Act1 may include polysilicon crystallized at a low temperature. The first active layer Act1 may include a channel region overlapping the first gate electrode GE1 and source and drain regions disposed on either side of the channel region.

[0238] The display device 1 may include a first gate insulating layer 103 disposed on the first semiconductor layer 1100 (see FIG. 10). The first gate insulating layer 103 may cover the first semiconductor layer 1100 (see FIG. 10) and be disposed on the buffer layer 102. The first gate insulating layer 103 may include an insulating material. For example, the first gate insulating layer 103 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0239] The first conductive layer 1200 (see FIG. 11 ) may be disposed on the first gate insulating layer 103. The first gate electrode GE1 of the first thin film transistor TFT1 may be disposed on the first gate insulating layer 103. In one embodiment, the first gate electrode GE1 of the first thin film transistor TFT1 may correspond to a part of the emission control line EML of the first conductive layer 1200.

[0240] The display device 1 may include a second gate insulating layer 104 disposed on the first conductive layer 1200 (see FIG. 11 ). The second gate insulating layer 104 may cover the first conductive layer 1200 (see FIG. 11 ) and be disposed on the first gate insulating layer 103. The second gate insulating layer 104 may include an insulating material. For example, the second gate insulating layer 104 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0241] The second thin film transistor TFT2 may be disposed on the second gate insulating layer 104. The second thin film transistor TFT2 may include a second active layer Act2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2. In one embodiment, the second thin film transistor TFT2 may be the compensation transistor T3 (see FIG. 5) or the first initialization transistor T4 (see FIG. 5).

[0242] The second conductive layer 1300 (see FIG. 13) may be disposed on the second gate insulating layer 104. In FIG. 22, a fourth conductive pattern 1320 of the second conductive layer 1300 is exemplarily illustrated, and the fourth conductive pattern 1320 may be a lower gate electrode of the second thin film transistor TFT2. The fourth conductive pattern 1320 may be disposed on the second gate insulating layer 104.

[0243] The display device 1 may include a first interlayer insulating layer 105 disposed on the second conductive layer 1300 (see FIG. 13). The first interlayer insulating layer 105 may cover the second conductive layer 1300 (see FIG. 13) and be disposed on the second gate insulating layer 104. The first interlayer insulating layer 105 may include an insulating material. For example, the first interlayer insulating layer 105 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0244] A second semiconductor layer 1400 (see FIG. 14) may be disposed on the first interlayer insulating layer 105. A second active layer Act2 of the second thin film transistor TFT2 may be disposed on the first interlayer insulating layer 105.

[0245] In one embodiment, the second active layer Act2 of the second thin film transistor TFT2 may correspond to the third semiconductor pattern 1410 of the second semiconductor layer 1400. The second active layer Act2 of the second thin film transistor TFT2 may include an oxide semiconductor material. For example, the second active layer Act2 may include an oxide of at least one material selected from the group including indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0246] The display device 1 may include a third gate insulating layer 106 disposed on the second semiconductor layer 1400 (see FIG. 14). The third gate insulating layer 106 may cover the second semiconductor layer 1400 (see FIG. 14) and be disposed on the first interlayer insulating layer 105. The third gate insulating layer 106 may include an insulating material. For example, the third gate insulating layer 106 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0247] A third conductive layer 1500 (see FIG. 15) may be disposed on the third gate insulating layer 106. A second gate electrode GE2 of the second thin film transistor TFT2 may be disposed on the third gate insulating layer 106. In one embodiment, the second gate electrode GE2 of the second thin film transistor TFT2 may correspond to a sixth conductive pattern 1510 of the third conductive layer 1500. Because the third conductive layer 1500 (see FIG. 15) includes a repair line RL, the repair line RL may be disposed in the same layer as the second gate electrode GE2 of the second thin film transistor TFT2.

[0248] The display device 1 may include a second interlayer insulating layer 107 disposed on the third conductive layer 1500 (see FIG. 15). The second interlayer insulating layer 107 may cover the third conductive layer 1500 (see FIG. 15) and be disposed on the third gate insulating layer 106. The second interlayer insulating layer 107 may include an insulating material. For example, the second interlayer insulating layer 107 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0249] 22, the upper surfaces of the buffer layer 102, the first gate insulating layer 103, the second gate insulating layer 104, the first interlayer insulating layer 105, the third gate insulating layer 106, and the second interlayer insulating layer 107 are shown flat for convenience, but the present invention is not limited thereto. For example, the buffer layer 102, the first gate insulating layer 103, the second gate insulating layer 104, the first interlayer insulating layer 105, the third gate insulating layer 106, and the second interlayer insulating layer 107 may each be an inorganic insulating layer containing an inorganic material and may be disposed to a substantially uniform thickness along the profile of the component.

[0250] The fourth conductive layer 1600 (see FIG. 17) may be disposed on the second interlayer insulating layer 107. The first source electrode SE1 and the first drain electrode DE1 of the first thin film transistor TFT1 may be disposed on the second interlayer insulating layer 107. In one embodiment, the first drain electrode DE1 of the first thin film transistor TFT1 may correspond to the 1-1th pixel connecting electrode 1620a. The second source electrode SE2 and the first drain electrode DE2 of the second thin film transistor TFT2 may be disposed on the second interlayer insulating layer 107. Because the fourth conductive layer 1600 (see FIG. 17) includes a voltage transmission line 1610, the voltage transmission line 1610 may be disposed on the same layer as the first source / drain electrodes SE1 and DE1 of the first thin film transistor TFT1, the second source / drain electrodes SE2 and DE2 of the second thin film transistor TFT2, and the 1-1th pixel connecting electrode 1620a.

[0251] 22, the repair line RL may overlap with the 1-1 pixel connecting electrode 1620a to form a first parasitic capacitor, and may overlap with the voltage transmission line 1610 to form a second parasitic capacitor. To form a relatively large second parasitic capacitor by overlapping with the repair line RL, the voltage transmission line 1610 may be disposed in the layer closest to the repair line RL. For example, no other conductive layer may be disposed between the repair line RL and the voltage transmission line 1610 in the z direction. For example, as described with reference to FIG. 22, if the repair line RL is formed in the third conductive layer 1500, the voltage transmission line 1610 may be formed in the fourth conductive layer 1600, which is the conductive layer closest to the third conductive layer 1500.

[0252] The display device 1 may include a first planarization layer 108 disposed on the fourth conductive layer 1600 (see FIG. 17). The first planarization layer 108 may cover the fourth conductive layer 1600 (see FIG. 17) and be disposed on the second interlayer insulating layer 107. The first planarization layer 108 may provide a flat upper surface on the fourth conductive layer 1600 (see FIG. 17). The first planarization layer 108 may include an organic insulating material. For example, the first planarization layer 108 may include photoresist, BCB (Benzocyclobutene), polyimide, HMDSO (hexamethyldisiloxane), polymethyl methacrylate (PMMA), polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a mixture thereof.

[0253] A fifth conductive layer 1700 (see FIG. 18) may be disposed on the first planarization layer 108.

[0254] 22 exemplarily illustrates a second pixel connecting electrode 1710a and a driving voltage line PL included in the fifth conductive layer 1700. The second pixel connecting electrode 1710a and the driving voltage line PL may be disposed on the first planarization layer 108. The second pixel connecting electrode 1710a may be electrically connected to the 1-1th pixel connecting electrode 1620a and may electrically connect the first thin film transistor TFT1 to the first organic light emitting element OLED1. In one embodiment, the driving voltage line PL may be electrically connected to the voltage transmission line 1610 and may transmit a driving voltage ELVDD to the voltage transmission line 1610.

[0255] The display device 1 may include a second planarization layer 109 disposed on the fifth conductive layer 1700 (see FIG. 18). The second planarization layer 109 may cover the fifth conductive layer 1700 (see FIG. 18) and be disposed on the first planarization layer 108. The second planarization layer 109 may provide a flat upper surface on the fifth conductive layer 1700 (see FIG. 18). The second planarization layer 109 may include an organic insulating material. For example, the second planarization layer 109 may include photoresist, BCB (Benzocyclobutene), polyimide, HMDSO (hexamethyldisiloxane), polymethyl methacrylate (PMMA), polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a mixture thereof.

[0256] A first organic light emitting element OLED1 may be located on the second planarization layer 109. The first organic light emitting element OLED1 may include a first pixel electrode 210a, an intermediate layer 220 including an emission layer, and a counter electrode 230.

[0257] A pixel defining (defining) layer 110 may be disposed on the second planarization layer 109. The pixel defining (defining) layer 110 increases the distance between the edge of the first pixel electrode 210a and the counter electrode 230 on the first pixel electrode 210a, thereby preventing arcing or the like at the edge of the first pixel electrode 210a. The pixel defining (defining) layer 110 may be made of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin, and may be formed by a method such as spin coating.

[0258] At least a portion of the intermediate layer 220 of the first organic light emitting element OLED1 may be located within a pixel opening 110OP formed by the pixel defining film 110.

[0259] The intermediate layer 220 may include an emissive layer. The emissive layer may include an organic material containing a fluorescent or phosphorescent material that emits red, green, blue, or white light. The emissive layer may be a low-molecular-weight organic material or a high-molecular-weight organic material. Functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be optionally disposed below and above the emissive layer.

[0260] The light-emitting layer may have a patterned shape corresponding to the first pixel electrode 210a. For example, the layers other than the light-emitting layer included in the intermediate layer 220 may be integrated across the first to third pixel electrodes 210a, 210b, and 210c (see FIG. 19).

[0261] The counter electrode 230 may be a translucent electrode or a reflective electrode. For example, the counter electrode 230 may be a transparent or semi-transparent electrode and may include a thin metal film with a low work function, such as Li, Ca, LiF, Al, Ag, Mg, or a compound thereof. The counter electrode 230 may also include a transparent conductive oxide (TCO) film, such as ITO, IZO, ZnO, or In2O3, located on the thin metal film. The counter electrode 230 may be integrally formed over the entire surface of the active region AA (see FIG. 1) and disposed on the intermediate layer 220 and the pixel defining layer 110.

[0262] The encapsulating member 300 may be disposed on the first organic light emitting element OLED1 to encapsulate the first organic light emitting element OLED1. The encapsulating member 300 may include at least one inorganic film layer and at least one organic film layer. For example, the encapsulating member 300 may include a first inorganic encapsulating layer 310, an organic encapsulating layer 320, and a second inorganic encapsulating layer 330, which are stacked in order.

[0263] The first inorganic sealing layer 310 and the second inorganic sealing layer 330 are made of silicon oxide (SiO2), silicon nitride (SiNX The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may have a single layer or multi-layer structure including the inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0264] The organic encapsulation layer 320 can relieve internal stress in the first inorganic encapsulation layer 310 and / or the second inorganic encapsulation layer 330. The organic encapsulation layer 320 can include a polymer-based material. The polymer-based material can include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or any combination thereof.

[0265] The organic encapsulation layer 320 may be formed by applying a flowable material containing a monomer and then reacting the monomer to form a polymer using heat or light such as ultraviolet light, or by applying a polymer material.

[0266] The display device 1 may further include a color filter layer. The color filter layer may include a first color filter, a second color filter, and a third color filter corresponding to a first pixel P1, a second pixel P2, and a third pixel P3, respectively, which emit different colors. For example, in FIG. 22, the first color filter may be disposed to correspond to an emission region of a first organic light emitting element OLED1. In one embodiment, the first color filter may be a red color filter, the second color filter may be a green color filter, and the third color filter may be a blue color filter.

[0267] Fig. 23 is a cross-sectional view schematically illustrating a cross section of a display unit of a display device 1' according to an embodiment. Fig. 23 is a modified embodiment of Fig. 22, and redundant explanations will be omitted and differences will be mainly explained.

[0268] Referring to FIG. 23, the 1-1 pixel connecting electrode 1620a and the voltage transmission line 1610' may be disposed on different layers.

[0269] In one embodiment, the repair line RL′ may be formed in a conductive layer not adjacent to the 1-1th pixel connecting electrode 1620a to reduce the size of the parasitic capacitor between the repair line RL′ and the 1-1th pixel connecting electrode 1620a. For example, the repair line RL′ may be formed in the second semiconductor layer 1400 (see FIG. 14). For example, the repair line RL′ may be disposed in the same layer as the second active layer Act2 of the second thin film transistor TF2. However, this is merely an example and is not limiting. The repair line RL′ may be disposed in various other ways, such as in the second conductive layer 1300 (see FIG. 13).

[0270] In order to overlap with the repair line RL' and form a relatively large parasitic capacitor, the voltage transmission line 1610' may be disposed in the layer closest to the repair line RL'. For example, as shown in FIG. 23, if the repair line RL' is formed in the second semiconductor layer 1400 (see FIG. 14), the voltage transmission line 1610' may be formed in the third conductive layer 1500, which is the conductive layer closest to the second semiconductor layer 1400 (see FIG. 14). That is, the voltage transmission line 1610' may be disposed on the third gate insulating layer 106 and in the same layer as the second gate electrode GE2 of the second thin film transistor TFT2. However, this is merely an example, and the position of the voltage transmission line 1610' may be varied depending on the arrangement of the repair line RL'.

[0271] The display device according to the embodiment may be applied to various electronic devices. The electronic device according to the embodiment may include the display device described above (e.g., the display device of FIG. 1) and may further include a module or device having other additional functions in addition to the display device.

[0272] FIG. 24 is a block diagram of an electronic device according to one embodiment.

[0273] Referring to FIG. 24, an electronic device 1000 according to an embodiment may include a display module 1001, a processor 1002, a memory 1003, and a power module 1004.

[0274] The processor 1002 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0275] The memory 1003 may store data information necessary for the operation of the processor 1002 and the display module 1001. When the processor 1002 executes an application stored in the memory 1003, it transmits image data signals and / or input control signals to the display module 1001, which may process the provided signals and output image information via a display screen.

[0276] The power supply module 1004 may include a power supply module such as a power adapter or a battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for operation of the electronic device 1000.

[0277] At least one of the components of the electronic device 1001 described above may be included in the display device according to the above-described embodiment. Furthermore, some of the individual modules functionally included in one module may be included in the display device, while other modules may be provided separately from the display device. For example, the display device may include the display module 1001, and the processor 1002, memory 1003, and power supply module 1004 may be provided in the form of other devices within the electronic device 1001 that are not a display device.

[0278] In one embodiment, the display device includes a display module 1001 that operates based on a video data signal and receives input control signals from a processor 1002 .

[0279] FIG. 25 is a schematic diagram of an electronic device according to various embodiments.

[0280] Referring to FIG. 25, various electronic devices to which the display device according to the embodiment can be applied include not only electronic devices for displaying images such as a smartphone 1000a, a tablet PC 1000b, a laptop 1000c, a TV 1000d, and a desk monitor 1000e, but also wearable electronic devices including a display module such as smart glasses 1000f, a head-mounted display 1000g, and a smart watch 1000h, and vehicular electronic devices 1000i including a display module such as a CID (Center Information Display) and a room mirror display arranged on an automobile's instrument panel, center fascia, or dashboard.

[0281] Although the present invention has been described based on the embodiments shown in the drawings, these are merely examples, and those skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the true technical scope of the present invention should be determined by the technical spirit of the claims.

[0282] According to a preferred specific embodiment, it is as follows:

[0283] The background and issues of this case are as follows (i) to (v).

[0284] (i) In a display panel in which light-emitting elements such as organic light-emitting diodes (OLEDs) or other pixels (sub-pixels) are arranged in a matrix, defective pixels such as bright spots (bright spots) or dark spots (black spots / dark spots) may occur.

[0285] (ii) After inspecting the backplane or array board for disconnections, or after inspecting the display panel for lighting, repairs may be performed using laser irradiation. The simplest repair method is to use laser irradiation to make bright spots less noticeable by darkening them.

[0286] (iii) On the other hand, during repair, it is preferable to convert a defective pixel into a pixel that operates normally.

[0287] (iv) It is also possible to provide a conductive layer pattern or wiring (repair wiring) for repair by laser irradiation.

[0288] (v) Furthermore, the parasitic capacitor between the repair wiring or conductive layer pattern and the pixel electrode should be designed to suppress the effect on brightness caused by coupling between adjacent pixels.

[0289] In a specific embodiment of the present application, at least one of A7 to A13 below is assumed, particularly on the premise that at least a part of A1 to A6 below is satisfied.

[0290] A1 A wide driving voltage line (PL) extending in the data line direction (y direction) is provided for each data line (data lines DL1 to DL3) (FIG. 18 of the present application). A driving voltage supply line (voltage transmission wiring 1610) extending in the scanning line direction (x direction) is provided for each scanning line (scan line GCL) (FIG. 17 of the present application). In addition, the drive voltage line (PL) in the data line direction (y direction) and the drive voltage supply line (voltage transmission wiring 1610) in the scanning line (scan line GCL) direction are stacked with one or more insulating layers (second interlayer insulating layer 107) in between, and are connected by contact holes (CNT14) provided for one or more pixels. (Figures 22 and 17-18 of the present application)

[0291] A2 includes a drain electrode (DE1) of a driving transistor (TFT1) in a pixel circuit for each pixel, and island-shaped pixel connecting electrodes (1620a, 1620b, 1620c) continuous therewith. These pixel connecting electrodes (1620a, 1620b, 1620c) are formed in the same layer as the driving voltage supply lines (voltage transmission wiring 1610) that extend in the scanning line direction (x direction). (Figures 22 and 17-18 of the present application)

[0292] A3 The pixel connecting electrodes (1620a, 1620b, 1620c) (Figure 17 of the present application) connected to the drain electrode (DE1) of the driving transistor (TFT1) are connected to the upper pixel electrodes (210a, 210b, 210c) (Figure 22 of the present application) through island-shaped connecting electrodes (1710a, 1710b, 1710c) (Figure 18 of the present application) formed simultaneously with the driving voltage line (PL) in the data line direction (y direction) and contact holes (CNT16 to CNT18 in Figure 19 and CNT13a to CNT13c in Figure 18). (Figures 22 and 17-19 of the present application)

[0293] A4: The pixel circuit arrangement regions (PC1, PC2, PC3) for each primary color are arranged in stripe-shaped regions extending in the data line direction (y direction). (Figures 17 and 19 of the present application)

[0294] A5 In the case of a display panel using an organic light-emitting element (OLED), the light-emitting areas of the red and green pixels (and pixel electrodes 210a, 210b) are arranged alternately in the data line direction (y direction) so as to overlap with the arrangement area (PC1) of the pixel circuit of the red pixel. Furthermore, the light-emitting regions of the blue pixels are arranged alternately in the data line direction (y direction) along the boundary between the arrangement region (PC2) of the green pixel circuits and the arrangement region (PC3) of the blue pixel circuits. (Figure 19 of the present application)

[0295] A6 The connecting electrodes (1710a, 1710b, 1710c) for the red, green, and blue pixels are arranged in approximately a straight line in the scanning line direction (x direction) so as to pass through the area between the light-emitting area of ​​the red pixel (and pixel electrode 210a) and the light-emitting area of ​​the green pixel (pixel electrode 210b). (Figs. 18-19 of the present application)

[0296] A7 Repair wiring (repair line RL) is provided that extends in a substantially straight line in the scanning line direction (x direction) so as to overlap the connecting electrodes (1710a, 1710b, 1710c) for the red, green, and blue pixels. (Figs. 16 and 20A of the present application)

[0297] A8 Along the repair data line (dummy data line DDL), a repair pixel circuit (dummy circuit DC) is provided for each scanning line (scan line GCL) or for each repair wiring (repair line RL). (Figure 3 of the present application)

[0298] A9 When repairing a defective pixel, the organic light-emitting element (OLED, E in Figure 3) of the defective pixel is irradiated with a laser to separate it from the pixel circuit of the defective pixel and connect it to the repair wiring (repair line RL). (Figures 2 to 4 of the present application)

[0299] A10: Repair extension data lines (connecting lines GL) are provided corresponding to a plurality of pixel circuit rows, extending in the scanning line direction (x direction) from one end of the repair data line (dummy data line DDL). When repairing a defective pixel, the data line (data line DL) to which the pixel circuit of the defective pixel was connected is connected to a repair extension data line (connection line GL) by laser irradiation. (Figure 3 of the present application)

[0300] A11 The repair pixel circuit (dummy circuit DC) has the same structure (transistors DT1 to DT8 and capacitor Cst) as the pixel circuit (PC), and is equipped with a "capacitance control transistor DT9" for "supplying the energy stored in the compensation capacitor Ccomp to" the repair wiring (repair line RL, and a "capacitive element initialization transistor DT10" for supplying an initialization voltage to the "compensation capacitor Ccomp." (Figure 6 of the present application)

[0301] A12 The driving voltage supply line (voltage transmission wiring 1610) in the scanning line direction (x direction) (Figure 17 of the present application) has island-shaped portions ("first portion 1610pa", "second portion 1610pb") that overlap with the repair wiring (repair line RL) at the end of a branch line that extends along the boundary of the arrangement area (PC1, PC2, PC3) of the primary color pixel circuits. (Figure 17 of the present application)

[0302] A13 The island-shaped portions (1610pa, 1610pb) of the driving voltage supply line (voltage transmission wiring 1610) have larger dimensions in the scanning line direction (x-direction) and data line direction (y-direction) and also have a larger area than the island-shaped connecting electrodes (1710a, 1710b, 1710c) located nearby. This makes it possible to reduce or prevent coupling of parasitic capacitance between pixels adjacent in the scanning line direction (x direction). (Figures 20B and 21B of the present application) [Explanation of symbols]

[0303] 10 Display section 20 Gate Driver 30 Source Driver 40 Control Unit 50 Power supply section P pixel DP dummy pixel RL Repair Wire GL connection line DL data line DDL Dummy Data Line BML bottom conductive layer 1100 First semiconductor layer 1200 First conductive layer 1300 Second conductive layer 1400 Second semiconductor layer 1500 Third conductive layer 1600 4th conductive layer 1700 5th conductive layer 2000 pixel electrode layer 1610 Voltage transmission wiring 1620 First pixel connecting electrode 1710 Second pixel connecting electrode 210a, 210b, 210c First to third pixel electrodes PL drive voltage line

Claims

1. a substrate including an active region and a dummy region disposed outside the active region; a pixel circuit disposed in the active region; a light emitting device electrically connected to the pixel circuit and including a pixel electrode; a dummy circuit disposed in the dummy region; a repair line extending in a first direction on the substrate, electrically connected to the dummy circuit, and connectable to the light emitting element; a pixel connecting electrode disposed to overlap the repair line and electrically connected to the pixel electrode; a voltage transmission line disposed overlapping the repair line and spaced apart from the pixel connecting electrode, for transmitting a voltage to the pixel circuit; a portion of the voltage transmission wiring overlapping the repair line having a larger area than a portion of the pixel connecting electrode overlapping the repair line;

2. 2. The display device of claim 1, wherein the width of the voltage transmission wiring along the first direction at the portion overlapping with the repair line is wider than the width of the pixel connecting electrode along the first direction at the portion overlapping with the repair line.

3. 3. The display device of claim 2, wherein the width of the repair line along a second direction perpendicular to the first direction at the portion where the repair line overlaps with the voltage transmission wiring is wider than the width of the repair line along the second direction at the portion where the repair line overlaps with the pixel connecting electrode.

4. 4. The display device of claim 3, wherein the width of the voltage transmission wiring along the second direction at the portion overlapping with the repair line is wider than the width of the pixel connecting electrode along the second direction at the portion overlapping with the repair line.

5. The display device according to claim 1 , further comprising a voltage line disposed on the voltage transmission wiring and transmitting a voltage to the voltage transmission wiring.

6. The display device of claim 5 , wherein the voltage lines carry a DC voltage.

7. The display device of claim 6 , wherein the voltage line transmits a driving voltage ELVDD.

8. a first transistor disposed on the substrate and including a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer; a second transistor including a second semiconductor layer disposed on the first gate electrode and a second gate electrode overlapping the second semiconductor layer, The display device according to claim 1 , wherein the repair line is arranged on the same layer as the second gate electrode of the second transistor.

9. the first semiconductor layer comprises a silicon semiconductor material; The display device of claim 8 , wherein the second semiconductor layer includes an oxide semiconductor material.

10. The display device of claim 1 , wherein the pixel connecting electrodes and the voltage transmission lines are disposed on the same layer.

11. The display device of claim 1 , wherein the pixel connecting electrode and the voltage transmission line are disposed on different layers.

12. a substrate including an active region and a dummy region disposed outside the active region; a plurality of pixels disposed in the active region, each pixel including a pixel circuit and a light emitting element; a dummy circuit disposed in the dummy region; a first semiconductor layer disposed on the substrate; a first gate layer disposed on the first semiconductor layer; a second gate layer disposed on the first gate layer; a second semiconductor layer disposed on the second gate layer; a third gate layer disposed on the second semiconductor layer, connected to the dummy circuit, and connectable to the light emitting element of a defective pixel among the plurality of pixels, the third gate layer including a repair line extending in a first direction; a connecting electrode layer disposed on the third gate layer, overlapping the repair line and including a pixel connecting electrode electrically connected to a pixel electrode of the light emitting device, and a voltage transmission line overlapping the repair line and spaced apart from the pixel connecting electrode; a portion of the voltage transmission wiring overlapping the repair line having a larger area than a portion of the pixel connecting electrode overlapping the repair line;

13. The display device of claim 12 , wherein a width of the portion of the voltage transmission wiring overlapping the repair line in the first direction is wider than a width of the portion of the pixel connecting electrode overlapping the repair line in the first direction.

14. 14. The display device of claim 13, wherein a width of the portion of the repair line that overlaps with the voltage transmission wiring along a second direction perpendicular to the first direction is wider than a width of the portion of the repair line that overlaps with the pixel connecting electrode along the second direction.

15. The display device of claim 14 , wherein a width of the portion of the voltage transmission wiring overlapping the repair line in the second direction is wider than a width of the portion of the pixel connecting electrode overlapping the repair line in the second direction.

16. The display device of claim 12 , further comprising a voltage line disposed on the connecting electrode layer and transmitting a voltage to the voltage transmission wiring.

17. 17. The display device of claim 16, wherein the voltage lines carry a DC voltage.

18. The display device of claim 17 , wherein the voltage line transmits a driving voltage ELVDD.

19. The display device of claim 12 , wherein the connecting electrode layer further comprises a scan line extending in the first direction, spaced apart from the voltage transmission line, and transmitting a scan signal.

20. a substrate including an active region and a dummy region disposed outside the active region; a first pixel disposed in the active region, the first pixel including a first pixel circuit and a first light-emitting element; a second pixel disposed in the active region, the second pixel including a second pixel circuit and a second light-emitting element; a dummy circuit disposed in the dummy region; a repair line extending in a first direction on the substrate, electrically connected to the dummy circuit, and arranged to be connectable to the first light emitting element or the second light emitting element; a first pixel connecting electrode disposed to overlap the repair line and electrically connected to the first pixel electrode of the first light emitting device; a second pixel connecting electrode disposed to overlap the repair line and electrically connected to the second pixel electrode of the second light emitting element; a voltage transmission line disposed to overlap the repair line, spaced apart from the first pixel connecting electrode and the second pixel connecting electrode, and electrically connected to the first pixel circuit and the second pixel circuit, an area of ​​a portion of the voltage transmission wiring overlapping with the repair line is larger than an area of ​​a portion of the first pixel connecting electrode overlapping with the repair line; A display device, wherein the portion of the voltage transmission wiring that overlaps with the repair line is located between the portion of the first pixel connecting electrode that overlaps with the repair line and the portion of the second pixel connecting electrode that overlaps with the repair line.

21. In an electronic device including a display device, The display device includes: a substrate including an active region and a dummy region disposed outside the active region; a pixel circuit disposed in the active region; a light emitting device electrically connected to the pixel circuit and including a pixel electrode; a dummy circuit disposed in the dummy region; a repair line extending in a first direction on the substrate, electrically connected to the dummy circuit, and connectable to the light emitting element; a pixel connecting electrode disposed to overlap the repair line and electrically connected to the pixel electrode; a voltage transmission line disposed overlapping the repair line and spaced apart from the pixel connecting electrode, for transmitting a voltage to the pixel circuit; an area of ​​a portion of the voltage transmission wiring overlapping with the repair line being larger than an area of ​​a portion of the pixel connecting electrode overlapping with the repair line;

22. A display module; a processor; a power supply module; a memory; and 22. The electronic device of claim 21, wherein the display device includes at least one of the display module, the processor, the power supply module, or the memory.

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