Display device and electronic apparatus

Abstract

To provide a display device.SOLUTION: A display device comprises: a first pixel circuit and a second pixel circuit adjacent to each other along a first direction and each including a driving transistor and a first capacitor that are arranged on a substrate; a first light-emitting diode electrically connected to the first pixel circuit; a second light-emitting diode electrically connected to the second pixel circuit; a first horizontal voltage line extending in the first direction, and electrically connected to a semiconductor layer of a first transistor, which is electrically connected to the driving transistor of the first pixel circuit and a pixel electrode of the first light-emitting diode; and a second horizontal voltage line extending in the first direction, and electrically connected to a semiconductor layer of a second transistor, which is electrically connected to the driving transistor of the second pixel circuit and a pixel electrode of the second light-emitting diode. The first horizontal voltage line and the second horizontal voltage line are arranged on different layers from each other, and overlap with each other in a plan view.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] The present invention relates to a display device and an electronic device including the same. [Background technology]

[0002] Recently, the applications of display devices have become more diverse. As the range of uses of display devices has expanded, the demand for high-resolution display devices has also increased. To manufacture high-resolution display devices, it is necessary to arrange electronic elements with diverse configurations in a small area. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Korean Patent Publication No. 2023-0106789 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention provides a structure of a display device. [Means for solving the problem]

[0005] One embodiment of the present invention discloses a display device including: a first pixel circuit and a second pixel circuit adjacent to each other along a first direction, each pixel circuit including a driving transistor and a first capacitor disposed on a substrate; a first light-emitting diode electrically connected to the first pixel circuit; a second light-emitting diode electrically connected to the second pixel circuit; a first horizontal voltage line extending along the first direction and electrically connected to a semiconductor layer of a first transistor electrically connected to a pixel electrode of the driving transistor of the first pixel circuit and the first light-emitting diode; a second horizontal voltage line extending along the first direction and electrically connected to a semiconductor layer of a second transistor electrically connected to the driving transistor of the second pixel circuit and the pixel electrode of the second light-emitting diode; and a first gate line extending along the first direction and electrically connected to a gate electrode of the first transistor of the first pixel circuit and a gate electrode of the second transistor of the second pixel circuit, respectively; wherein the first horizontal voltage line and the second horizontal voltage line are disposed on different layers but overlap each other in a plan view.

[0006] The second horizontal voltage line may be disposed on the same layer as the first gate line.

[0007] The pixel element may further include a lower metal layer interposed between an upper surface of the substrate and the driving transistor of the first pixel circuit and between the upper surface of the substrate and the driving transistor of the second pixel circuit.

[0008] The lower metal layer may include: a first main portion overlapping a channel region of the driving transistor of the first pixel circuit; a second main portion overlapping a channel region of the driving transistor of the second pixel circuit; a first branch portion extending in the first direction to connect the first main portion and the second main portion to each other; and a second branch portion connected to the first main portion and the second main portion, respectively, and extending in a second direction.

[0009] The second branch section may intersect with the first horizontal voltage line and the second horizontal voltage line in a plan view.

[0010] The pixel circuit may further include a horizontal driving voltage line overlapping the driving transistor of the first pixel circuit and the driving transistor of the second pixel circuit and extending along the first direction, wherein the horizontal driving voltage line overlaps the first branch section.

[0011] Each of the first pixel circuit and the second pixel circuit may further include a compensation transistor including a compensation semiconductor layer and a compensation gate electrode, and electrically connected to the driving transistor, and the first horizontal voltage line may be disposed on the same layer as the compensation gate electrode of the compensation transistor.

[0012] The pixel circuit may further include a first connecting electrode electrically connecting the compensation semiconductor layer of the compensation transistor of the first pixel circuit to the driving gate electrode of the driving transistor of the first pixel circuit, and the first connecting electrode may overlap one of the second branch portions of the lower metal layer.

[0013] The pixel electrode may further include a driving voltage line extending in a second direction intersecting the first direction to pass through the first pixel circuit.

[0014] The driving voltage line may overlap the one of the second branch portions of the lower metal layer corresponding to the first pixel circuit and the first connecting electrode.

[0015] The driving voltage line can overlap the compensation gate electrode of the first pixel circuit in a plan view.

[0016] The first pixel circuit may further include a first initialization transistor including a first initialization semiconductor layer integrally connected with the compensation semiconductor layer of the compensation transistor and a first initialization gate electrode, and the driving voltage line may overlap the first initialization gate electrode.

[0017] The pixel circuit further includes a third pixel circuit disposed on the opposite side of the first pixel circuit with the second pixel circuit in between, and a first separation distance between the drive transistor of the second pixel circuit and the drive transistor of the third pixel circuit is greater than a second separation distance between the drive transistor of the second pixel circuit and the drive transistor of the first pixel circuit.

[0018] A planar shape of the channel region of the driving transistor of the third pixel circuit may be different from a planar shape of the channel region of the driving transistor of the second pixel circuit or a planar shape of the channel region of the driving transistor of the first pixel circuit.

[0019] The third pixel circuit may further include a third transistor electrically connected to the driving transistor of the third pixel circuit and a pixel electrode of a third light emitting diode electrically connected to the third pixel circuit, and the second horizontal voltage line may be electrically connected to the third transistor of the third pixel circuit.

[0020] The third pixel circuit may further include a third transistor electrically connected to the driving transistor of the third pixel circuit and a pixel electrode of a third light emitting diode electrically connected to the third pixel circuit, and a third horizontal voltage line electrically connected to the third transistor of the third pixel circuit may be disposed on a different layer from the first horizontal voltage line and the second horizontal voltage line but may overlap with the first horizontal voltage line and the second horizontal voltage line.

[0021] The pixel circuit may further include a first vertical voltage line extending along a second direction intersecting the first direction and passing through a space between the second pixel circuit and the third pixel circuit having the first separation distance, wherein the first horizontal voltage line is electrically connected to the first vertical voltage line.

[0022] The first horizontal voltage line may further include a bridge portion protruding from the first horizontal voltage line, and the bridge portion may be connected to the first vertical voltage line.

[0023] The display panel may further include a connection electrode disposed on the bridge portion and below the first vertical voltage line, wherein the bridge portion and the first vertical voltage line are electrically connected to each other through the connection electrode.

[0024] The first horizontal voltage line may be connected to the first vertical voltage line via a bridge portion disposed on a layer different from that of the first horizontal voltage line.

[0025] Each of the first pixel circuit and the second pixel circuit may further include a data write transistor electrically connected to the driving transistor and the first capacitor, and a first data line electrically connected to the data write transistor of the first pixel circuit and a second data line electrically connected to the data write transistor of the second pixel circuit may have different shapes from each other in a planar view.

[0026] Another embodiment of the present invention discloses an electronic device including: a first pixel circuit and a second pixel circuit adjacent to each other along a first direction, each pixel circuit including a driving transistor and a first capacitor disposed on a substrate; a first light emitting diode and a second light emitting diode electrically connected to the first pixel circuit and the second pixel circuit, respectively; a first horizontal voltage line extending along the first direction and electrically connected to a semiconductor layer of a first transistor electrically connected to a pixel electrode of the driving transistor and the first light emitting diode of the first pixel circuit; a second horizontal voltage line extending along the first direction and electrically connected to a semiconductor layer of a second transistor electrically connected to a pixel electrode of the driving transistor and the second light emitting diode of the second pixel circuit; and a first gate line extending along the first direction and electrically connected to a gate electrode of the first transistor of the first pixel circuit and a gate electrode of the second transistor of the second pixel circuit, respectively;

[0027] The pixel element may further include a lower metal layer interposed between an upper surface of the substrate and the driving transistor of the first pixel circuit and between the upper surface of the substrate and the driving transistor of the second pixel circuit, and the lower metal layer may include: a first main portion overlapping a channel region of the driving transistor of the first pixel circuit; a second main portion overlapping a channel region of the driving transistor of the second pixel circuit; a first branch portion extending in the first direction to connect the first main portion and the second main portion to each other; and a second branch portion connected to the first main portion and the second main portion and extending in a second direction.

[0028] The second branch section may intersect with the first horizontal voltage line and the second horizontal voltage line in a plan view.

[0029] The pixel circuit may further include a horizontal driving voltage line overlapping the driving transistor of the first pixel circuit and the driving transistor of the second pixel circuit and extending along the first direction, wherein the horizontal driving voltage line may overlap the first branch portion.

[0030] The pixel circuit may further include a third pixel circuit disposed on the opposite side of the first pixel circuit with the second pixel circuit interposed therebetween, wherein a first distance between the driving transistor of the second pixel circuit and the driving transistor of the third pixel circuit is greater than a second distance between the driving transistor of the second pixel circuit and the driving transistor of the first pixel circuit, and a planar shape of a channel region of the driving transistor of the third pixel circuit may be different from a planar shape of the channel region of the driving transistor of the second pixel circuit or a planar shape of the channel region of the driving transistor of the first pixel circuit.

[0031] The pixel circuit may further include a first vertical voltage line extending along a second direction intersecting the first direction and passing through a space between the second pixel circuit and the third pixel circuit having the first separation distance, wherein the first horizontal voltage line is electrically connected to the first vertical voltage line.

[0032] The first horizontal voltage line may further include a bridge portion protruding from the first horizontal voltage line, and the bridge portion may be connected to the first vertical voltage line.

[0033] The display panel may further include a connection electrode disposed on the bridge portion and below the first vertical voltage line, wherein the bridge portion and the first vertical voltage line are electrically connected to each other through the connection electrode.

[0034] The first horizontal voltage line may be connected to the first vertical voltage line via a bridge portion disposed on a layer different from that of the first horizontal voltage line.

[0035] The electronic device may be a mobile phone, a laptop, a tablet personal computer (PC), a smartphone, a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player (PMP), a navigation system, an Ultra Mobile PC (UMPC), a television, a monitor, a smart watch, a watch phone, a glasses-type display, a head-mounted display (HMD), or an automotive display device. [Effects of the Invention]

[0036] According to some embodiments of the present invention, it is possible to improve the integration density of pixel circuits, minimize the occurrence of unintended parasitic capacitance, and provide a high-quality display device. The above-described advantages are merely examples, and the advantages of the present invention are not limited to those described above. [Brief explanation of the drawings]

[0037] [Figure 1] 1 is a plan view schematically illustrating a display device according to an embodiment of the present invention; [Figure 2] 1 is a block diagram illustrating a display device according to an embodiment of the present invention; [Figure 3]2 is an equivalent circuit diagram showing one light emitting diode and a pixel circuit arranged in a display device according to an embodiment of the present invention. FIG. [Figure 4] 1 is a cross-sectional view showing a part of a display area of ​​a display device according to an embodiment of the present invention. [Figure 5] 1 is a plan view schematically showing a part of wiring arranged in a display area of ​​a display device according to an embodiment of the present invention; [Figure 6] 2 is a plan view illustrating first to third pixel circuits of a display device according to an embodiment of the present invention. FIG. [Figure 7] 7A to 7C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 6. [Figure 8] 7A to 7C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 6. [Figure 9] 7A to 7C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 6. [Figure 10] 7A to 7C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 6. [Figure 11] 7A to 7C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 6. [Figure 12] 7A to 7C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 6. [Figure 13] 7A to 7C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 6. [Figure 14] 7A to 7C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 6. [Figure 15] 7A to 7C are plan views illustrating a process of forming the first to third pixel circuits illustrated in FIG. 6. [Figure 16] 4 is a plan view schematically illustrating a second initialization horizontal voltage line passing through first to third pixel circuits of a display device according to an embodiment of the present invention. FIG. [Figure 17] 17A and 17B are cross-sectional views taken along the lines AA' and BB' in FIG. 16. [Figure 18]3 is a plan view schematically illustrating an initialization horizontal voltage line passing through first to third pixel circuits of a display device according to an embodiment of the present invention. FIG. [Figure 19] FIG. 19 is a cross-sectional view taken along the line CC' in FIG. [Figure 20] 4 is a plan view illustrating an electrical connection between a second initialization horizontal voltage line and a second initialization vertical voltage line of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0038] The present invention can be modified in various ways and can have various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. The advantages and features of the present invention, and methods for achieving them, will become clearer with reference to the embodiments described in detail below in conjunction with the drawings. However, the present invention is not limited to the embodiments described below, and can be embodied in various forms.

[0039] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, identical or corresponding components will be given the same drawing numbers and duplicate descriptions thereof will be omitted.

[0040] In the following embodiments, terms such as first and second are used to distinguish one component from another, without any limiting meaning.

[0041] In the following embodiments, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0042] In the following embodiments, terms such as "comprise" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0043] In the following embodiments, when a part such as a film, region, or component is said to be on or above another part, this does not only include the case where it is directly on top of the other part, but also the case where another film, region, component, etc. is interposed between them.

[0044] In the drawings, the size of components may be exaggerated or reduced for the sake of convenience. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for the sake of convenience, and the present invention is not necessarily limited to what is shown in the drawings.

[0045] If an embodiment can be implemented differently, the order of certain steps may be performed differently than described. For example, two steps described in succession may be performed substantially simultaneously or may be performed in the reverse order of that described.

[0046] In the following embodiments, when a film, region, component, etc. is said to be connected, it includes not only the case where the film, region, component, etc. is directly connected, but also the case where the film, region, component, etc. is indirectly connected by another film, region, component, etc. being interposed between them. For example, in this specification, when a film, region, component, etc. is said to be electrically connected, it includes not only the case where the film, region, component, etc. is directly electrically connected, but also the case where the film, region, component, etc. is indirectly electrically connected by another film, region, component, etc. being interposed between them.

[0047] FIG. 1 is a plan view schematically showing a display device according to one embodiment of the present invention.

[0048] 1, a display device 1 may include a display area DA for displaying an image and an outer area PA outside the display area DA. The display area DA may be entirely surrounded by the outer area PA.

[0049] In a plan view, the display area DA may have a substantially rectangular shape with rounded corners. In other embodiments, the display area DA may have a polygonal shape such as a triangle, a square, a pentagon, or a hexagon, or a circular, elliptical, or irregular shape.

[0050] The display device 1 of FIG. 1 is a device for displaying moving images and still images and may be used in portable electronic devices such as mobile phones, laptops, tablet personal computers (PCs), mobile phones, smartphones, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs). The display device 1 may also be used in electronic devices for the Internet of Things (IoT), such as televisions, monitors, billboards, and wearable electronic devices such as smart watches, watch phones, eyeglass displays, and head-mounted displays (HMDs). The display device 1 according to an embodiment may also be used in automotive dashboards, center information displays (CIDs) located in the center fascia or dashboard of an automobile, room mirror displays replacing the side mirrors of an automobile, and display electronic devices located behind the front seats for rear-seat entertainment in an automobile.

[0051] FIG. 2 is a block diagram schematically illustrating a display device according to an embodiment of the present invention.

[0052] 1 and 2, a display device 1 according to an embodiment may include a pixel unit 11, a gate driving circuit 13, a data driving circuit 15, a power supply circuit 17, and a controller 19.

[0053] The pixel unit 11 may include a plurality of pixels arranged in a display area DA (FIG. 1). The plurality of pixels may be arranged in various patterns, such as a stripe array, a pentatile (diamond) array, or a mosaic array, to implement an image. Each pixel emits light through a light emitting diode (LED), and each light emitting diode (LED) may be electrically connected to a pixel circuit (PC). Each pixel circuit (PC) is electrically connected to a gate line (GL) and a data line (DL), and may include a plurality of transistors and at least one capacitor.

[0054] The outer area PA (FIG. 1) may include various conductive lines transmitting electrical signals to the display area DA (FIG. 1), outer circuits electrically connected to the pixel circuits, and pads for mounting a printed circuit board or a driver IC chip. For example, the outer area PA (FIG. 1) may include a gate driver circuit 13, a data driver circuit 15, a power supply circuit 17, and a controller 19.

[0055] The gate driving circuit 13 is electrically connected to the plurality of gate lines GL, generates gate signals in response to a control signal GCS from the controller 19, and sequentially supplies the gate signals to the gate lines GL. The gate signals are also gate control signals that control the turn-on and turn-off of transistors electrically connected to the gate lines GL. The gate signals are also square wave signals that include an on voltage at which the transistors are turned on and an off voltage at which the transistors are turned off. In one embodiment, the on voltage may be a high-level voltage (first-level voltage) or a low-level voltage (second-level voltage).

[0056] 2, any one pixel circuit PC is illustrated as being connected to one gate line GL, but this is merely an example, and one pixel circuit PC may be connected to two or more gate lines, and the gate driving circuit 13 may supply two or more gate signals having different timings for applying on-voltages to the gate lines. For example, the pixel circuit PC may be electrically connected to a plurality of gate lines, and the gate driving circuit 13 may apply the scan signal GW, the first initialization control signal GI, the second initialization control signal GB, the compensation scan signal GC, and the light emission control signal EM to the pixel circuit PC via the gate lines, respectively.

[0057] The data driving circuit 15 is connected to a plurality of data lines DL and may supply a data signal Dm to the data lines DL in response to a control signal DCS from the controller 19. The data signal Dm supplied to the data lines DL may be provided to the pixel circuits PC. The data driving circuit 15 may convert input image data having gray levels input from the controller 19 into a data signal Dm in the form of a voltage or current.

[0058] The power supply circuit 17 may generate voltages required to drive the pixel circuit PC and the light emitting diode LED in response to a control signal PCS from the controller 19. The power supply circuit 17 may generate a driving voltage ELVDD and a common voltage ELVSS and supply them to the pixel circuit PC and the light emitting diode LED, respectively. The driving voltage ELVDD is also a high-level voltage provided to a first electrode (or pixel electrode, anode) of the light emitting diode LED. The common voltage ELVSS is also a low-level voltage provided to a second electrode (or counter electrode, cathode) of the light emitting diode LED. The power supply circuit 17 may generate a bias voltage Vobs, a first initialization voltage Vint, and a second initialization voltage Vint and supply them to the pixel circuit PC.

[0059] The voltage level of the driving voltage ELVDD is higher than the voltage level of the common voltage ELVSS. The voltage levels of the first initialization voltage Vint and the second initialization voltage Vaint are higher than the voltage level of the common voltage ELVSS. The voltage level of the bias voltage Vobs is higher than the voltage level of the driving voltage ELVDD.

[0060] The controller 19 may generate control signals GCS, DCS, and PCS based on an externally input signal and supply them to the gate drive circuit 13, the data drive circuit 15, and the power supply circuit 17. The control signal GCS output to the gate drive circuit 13 may include a plurality of clock signals and a gate start signal. The control signal DCS output to the data drive circuit 15 may include a source start signal and a clock signal.

[0061] FIG. 3 is an equivalent circuit diagram showing one of the light emitting diodes and a pixel circuit arranged in a display device according to an embodiment of the present invention.

[0062] 3, the pixel circuits PC are respectively connected to gate lines, for example, a scan line GWL, a first initialization control line GIL, a second initialization control line GBL, a compensation scan line GCL, and an emission control line EML, and may receive a scan signal GW, a first initialization control signal GI, a second initialization control signal GB, a compensation scan signal GC, and an emission control signal EM. For example, the scan line GWL, the first initialization control line GIL, the second initialization control line GBL, the compensation scan line GCL, and the emission control line EML in FIG. 3 are also gate lines connected to the pixel circuits PC located in the ith row (i is a natural number).

[0063] The pixel circuits PC may receive a data signal Dm via a data line DL. For example, the data line DL in FIG. 3 is also a signal line connected to the pixel circuits PC located in the j-th column (j is a natural number).

[0064] The pixel circuit PC of the display device according to this embodiment is electrically connected to a light emitting diode LED that emits light of a predetermined color, and the light emitting diode LED may include a first electrode (pixel electrode, anode), a second electrode (counter electrode, cathode), and an intermediate layer therebetween.

[0065] The pixel circuit PC may include a plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 and capacitors Cst and Ca. The plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 may include a drive transistor T1, a data write transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, a light-emitting control transistor T6, a second initialization transistor T7, and a bias transistor T8. The capacitors Cst and Ca may include a first capacitor Cst and a second capacitor Ca.

[0066] In one embodiment, some of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 are PMOS (p-channel MOSFETs) and the remaining transistors are NMOS (n-channel MOSFETs). For example, the driving transistor T1, the data writing transistor T2, the operation control transistor T5, the light-emitting control transistor T6, the second initialization transistor T7, and the bias transistor T8 of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 are PMOS, and the compensation transistor T3 and the first initialization transistor T4 are NMOS. Alternatively, the compensation transistor T3 and the first initialization transistor T4 of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be PMOS, and the remaining transistors may be NMOS. Alternatively, the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may all be NMOS or all PMOS. Hereinafter, an embodiment will be mainly described in which the compensation transistor T3 and the first initialization transistor T4 are NMOS (n-channel MOSFETs) including an oxide semiconductor, and the rest are PMOS (p-channel MOSFETs).

[0067] At least one of the plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 is also a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and at least one of the plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 is also a transistor having an oxide semiconductor layer.

[0068] The driving transistor T1, which directly affects the brightness of the display device, is configured to include a semiconductor layer made of highly reliable polycrystalline silicon, thereby enabling a high-resolution display device. Meanwhile, oxide semiconductors have high carrier mobility and low leakage current, so voltage drop is not significant even with long drive times. That is, low-frequency drive is possible because image color shift due to voltage drop is not significant even during low-frequency drive. Because oxide semiconductors have the advantage of low leakage current, at least one of the compensation transistor T3 and the first initialization transistor T4, which are connected to the drive gate electrode of the driving transistor T1, can be made of an oxide semiconductor to prevent leakage current from flowing through the drive gate electrode and reduce power consumption. For example, the driving transistor T1, the data write transistor T2, the operation control transistor T5, the light-emitting control transistor T6, the second initialization transistor T7, and the bias transistor T8 can also be transistors having low-temperature polysilicon semiconductor layers, and the compensation transistor T3 and the first initialization transistor T4 can also be transistors having oxide semiconductor layers.

[0069] The driving transistor T1 may be connected between a driving voltage line (or vertical driving voltage line, PL) that provides a driving voltage ELVDD and the light emitting diode LED. A gate electrode of the driving transistor T1 may be connected to one end of a first capacitor Cst, which is a storage capacitor. A gate electrode of the driving transistor T1 may be connected to a first node N1. A source electrode of the driving transistor T1 may be connected to the driving voltage line PL via an operation control transistor T5. A drain electrode of the driving transistor T1 may be electrically connected to a pixel electrode (e.g., an anode) of the light emitting diode LED via an emission control transistor T6. The driving transistor T1 may receive a data signal Dm transmitted through a data line DL via a switching operation of the data write transistor T2 and supply a driving current to the light emitting diode LED.

[0070] The gate electrode of the data write transistor T2 may be connected to the scan line GWL. The first electrode of the data write transistor T2 may be connected to the data line DL, and the second electrode may be connected to the source electrode of the drive transistor T1. The data write transistor T2 is turned on by a scan signal GW transmitted through the scan line GWL to transmit a data signal Dm transmitted to the data line DL to the source electrode of the drive transistor T1. The data signal Dm may be transmitted to the gate electrode of the drive transistor T1 by the compensation transistor T3, which is turned on at the same time.

[0071] The gate electrode of the compensation transistor T3 may be connected to the compensation scan line GCL. The first electrode of the compensation transistor T3 may be connected to the drain electrode of the driving transistor T1, and the second electrode of the compensation transistor T3 may be connected to the first node N1. The compensation transistor T3 is turned on by a compensation scan signal GC transmitted through the compensation scan line GCL to connect the gate electrode and drain electrode of the driving transistor T1 to each other, thereby diode-connecting the driving transistor T1 and compensating for the threshold voltage Vth of the driving transistor T1.

[0072] The gate electrode of the first initialization transistor T4 may be connected to a first initialization control line GIL. The first electrode of the first initialization transistor T4 may be connected to a first initialization voltage line VIL, and the second electrode may be connected to a first node N1. The first initialization transistor T4 is turned on by a first initialization control signal GI applied from the first initialization control line GIL to transmit a first initialization voltage Vint to the gate electrode of the driving transistor T1, thereby initializing the potential of the gate electrode of the driving transistor T1 (i.e., the potential of the first node N1) to a predetermined voltage. The first initialization voltage Vint may have a voltage level higher than or similar to the common voltage ELVSS.

[0073] The gate electrode of the operation control transistor T5 may be connected to the emission control line EML, the first electrode of the operation control transistor T5 may be connected to the driving voltage line PL, and the second electrode of the operation control transistor T5 may be connected to the source electrode of the driving transistor T1.

[0074] A gate electrode of the emission control transistor T6 may be connected to an emission control line EML. A first electrode of the emission control transistor T6 may be connected to a drain electrode of the driving transistor T1, and a second electrode of the emission control transistor T6 may be electrically connected to a pixel electrode of the light emitting diode LED. The operation control transistor T5 and the emission control transistor T6 may be simultaneously turned on by an emission control signal EM applied from the emission control line EML. The driving voltage ELVDD applied through the turned-on operation control transistor T5 may be compensated through the driving transistor T1 and then transmitted to the light emitting diode LED.

[0075] A gate electrode of the second initialization transistor T7 may be connected to a second initialization control line GBL. A first electrode of the second initialization transistor T7 may be connected to a pixel electrode of the light emitting diode LED, and a second electrode of the second initialization transistor T7 may be connected to a second initialization voltage line VAL. The second initialization transistor T7 may be turned on by a second initialization control signal GB applied from the second initialization control line GBL to initialize the pixel electrode of the light emitting diode LED. The second initialization control signal GB may be the same as or different from the first initialization control signal GI.

[0076] In a comparative example of the present invention, even if the minimum current of the driving transistor T1 required to display a black image flows as a driving current, the black image may not be properly displayed if the light-emitting diode LED emits light. However, according to the present invention, the second initialization transistor T7 can disperse a portion of the minimum current of the driving transistor T1 as a bypass current to a current path other than the current path of the light-emitting diode LED. Here, the minimum current of the driving transistor T1 refers to the current when the gate-source voltage Vgs of the driving transistor T1 is lower than a threshold voltage (Vth) and the driving transistor T1 is turned off. In this way, the minimum driving current (e.g., a current of 10 pA or less) required to turn off the driving transistor T1 is transmitted to the light-emitting diode LED, thereby displaying an image with black brightness. When the minimum driving current required to display a black image flows, the bypass current has a significant effect. However, when a large driving current required to display an image such as a normal image or a white image flows, the bypass current has almost no effect. Therefore, when a driving current for displaying a black image flows, an accurate black luminance image can be realized using the second initialization transistor T7 from the driving current, thereby improving the contrast ratio and providing a display device with improved display quality.

[0077] A gate electrode of the bias transistor T8 may be connected to the second initialization control line GBL, a first electrode of the bias transistor T8 may be connected to a bias voltage line VOL to which a bias voltage Vobs is provided, and a second electrode of the bias transistor T8 may be connected to the source electrode of the driving transistor T1.

[0078] One end of the first capacitor Cst may be connected to the gate electrode of the driving transistor T1, and the other end may be connected to the driving voltage line PL. The first capacitor Cst may be connected between the driving voltage line PL and a first node N1. The first capacitor Cst may store a voltage between the driving voltage ELVDD and the first node N1.

[0079] The second capacitor Ca is an auxiliary capacitor and may be electrically connected to the light-emitting control transistor T6, the second initialization transistor T7, and the first electrode of the light-emitting diode LED. The second capacitor Ca stores and maintains a voltage corresponding to the voltage difference between the first electrode of the light-emitting diode LED and the common voltage line VSL while the second initialization transistor T7 is turned on, thereby preventing an increase in black brightness when the light-emitting control transistor T6 is turned off.

[0080] The pixel electrode of the light emitting diode LED receives a driving current from the driving transistor T1 to emit light and display an image. The driving voltage ELVDD is a predetermined high-level voltage, and the common voltage ELVSS is a voltage lower than the driving voltage ELVDD.

[0081] The operation of the pixel circuit PC and the light emitting diode LED will now be described.

[0082] During the initialization period, a high-level first initialization control signal GI may be supplied to the first initialization transistor T4 via the first initialization control line GIL, and a low-level second initialization control signal GB may be supplied to the second initialization transistor T7 via the second initialization control line GBL. As a result, the first initialization transistor T4 and the second initialization transistor T7 may be turned on. A first initialization voltage Vint applied from the first initialization voltage line VIL may be transferred to the gate electrode of the driving transistor T1 via the first initialization transistor T4, and a second initialization voltage Vaint applied via the second initialization voltage line VAL may be transferred to the anode via the second initialization transistor T7. As a result, the voltages of the gate electrode and anode of the driving transistor T1 may be initialized.

[0083] Thereafter, during a data write period, a low-level scan signal GW is supplied through the scan line GWL, and a high-level compensation scan signal GC is supplied through the compensation scan line GCL, turning on the data write transistor T2 and the compensation transistor T3. The data write transistor T2 transfers a data signal Dm from the data line DL to the source electrode of the drive transistor T1, and the drive transistor T1 may be diode-coupled by the compensation transistor T3. As a result, a compensation voltage, which is reduced by the threshold voltage of the drive transistor T1 due to the data signal Dm, may be applied to the gate electrode of the drive transistor T1.

[0084] The drive voltage ELVDD and the compensation voltage are applied to both ends of the storage capacitor Cst1, and a charge corresponding to the voltage difference between both ends of the storage capacitor Cst1 can be stored in the storage capacitor Cst1.

[0085] Thereafter, during the light-emitting period, the light-emitting control signal EM supplied from the light-emitting control line EML changes from high to low, turning on the operation control transistor T5 and the light-emitting control transistor T6. Then, a driving current is generated due to the voltage difference between the gate electrode voltage of the driving transistor T1 and the driving voltage ELVDD, and the driving current is supplied to the light-emitting diode LED via the light-emitting control transistor T6, causing it to emit light.

[0086] The characteristics of the light emitting diodes LED that emit different light and / or the characteristics of the driving transistors T1 of each pixel circuit PC may differ from one another. In particular, the color coordinates of the display device 1 may vary (e.g., reddish) when driven at high frequencies. However, according to the present invention, the voltage of the source electrode of the driving transistor T1 may be controlled by the bias voltage Vobs via the bias transistor T8. This may improve the brightness deviation (current deviation) and color coordinate variation between pixels by controlling the driving current. Therefore, a display device with improved display quality may be provided.

[0087] FIG. 4 is a cross-sectional view showing a part of a display area of ​​a display device according to an embodiment of the present invention.

[0088] Referring to FIG. 4, a pixel circuit PC may be disposed on a substrate 100, and a light emitting diode LED may be disposed on the pixel circuit PC.

[0089] The substrate 100 may include glass, ceramic, metal, plastic, or any other flexible or bendable material. If the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate, and cellulose acetate propionate (CAP).

[0090] The substrate 100 may have a single-layer or multi-layer structure of the above materials, and in the case of a multi-layer structure, may further include an inorganic layer. For example, the substrate 100 may include a first organic base layer, a first inorganic barrier layer, a second organic base layer, and a second inorganic barrier layer. The first organic base layer and the second organic base layer may each include a polymer resin. The first inorganic barrier layer and the second inorganic barrier layer are barrier layers that prevent the penetration of external foreign substances and may be a single layer or multi-layer including an inorganic insulator such as silicon nitride and / or silicon oxide.

[0091] A lower metal layer BML may be disposed on the substrate 100. The lower metal layer BML may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In some embodiments, the lower metal layer BML may be a single layer of molybdenum, a bilayer structure in which a molybdenum layer and a titanium layer are stacked, or a trilayer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0092] The lower metal layer BML may have a constant voltage level. For example, the lower metal layer BML may be electrically connected to the driving voltage line PL described with reference to FIG. 3 and have the same voltage level (e.g., driving voltage ELVDD, FIG. 3) as the driving voltage line PL. The lower metal layer BML may prevent negative charges from accumulating under the semiconductor layer (hereinafter referred to as the first semiconductor layer or driving semiconductor layer; A1) of the driving transistor T1, thereby preventing or minimizing the problem of image retention due to negative charges. When viewed perpendicularly to the top surface of the substrate 100, the lower metal layer BML may entirely overlap the channel region C1 of the driving semiconductor layer A1 of the driving transistor T1.

[0093] The buffer layer 111 may be disposed on the lower metal layer BML. The buffer layer 111 may be an inorganic insulating layer containing an inorganic insulating material such as silicon nitride and / or silicon oxide, and may have a single-layer or multi-layer structure containing the aforementioned materials.

[0094] A transistor including a silicon semiconductor layer may be disposed on the buffer layer 111. In this regard, Figure 4 illustrates a driving semiconductor layer A1 of the driving transistor T1, which corresponds to a part of the first silicon semiconductor pattern 1110. The driving semiconductor layer A1 includes a channel region C1 and impurity regions doped with impurities disposed on both sides of the channel region C1. In this regard, Figure 4 illustrates a first region B1, which is one of the impurity regions disposed on one side of the channel region C1.

[0095] The first gate insulating layer 112 may be disposed on the first silicon semiconductor pattern 1110, for example, the driving semiconductor layer A1. The first gate insulating layer 112 may be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0096] The first conductive pattern 1210 may be disposed on the first gate insulating layer 112. The first conductive pattern 1210 may include a driving gate electrode G1 and / or a lower electrode CE1 of a first capacitor Cst. The first conductive pattern 1210 may function as the lower electrode CE1 of a storage capacitor Cst or as the driving gate electrode G1. In other words, the driving gate electrode G1 and the lower electrode CE1 may be integrally formed.

[0097] The first conductive pattern 1210, e.g., the driving gate electrode G1 and / or the lower electrode CE1 of the first capacitor Cst, may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed of a single layer or multiple layers including the above materials. In some embodiments, the driving gate electrode G1 and / or the lower electrode CE1 of the first capacitor Cst may include a single layer of molybdenum.

[0098] The second gate insulating layer 113 may be disposed on the driving gate electrode G1 and / or the lower electrode CE1 of the first capacitor Cst. The second gate insulating layer 113 may be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0099] Another conductive pattern (hereinafter referred to as a third conductive pattern 1310) may be disposed on the second gate insulating layer 113. The third conductive pattern 1310 may include an upper electrode CE2 of the first capacitor Cst. The third conductive pattern 1310, for example, the upper electrode CE2 of the first capacitor Cst, may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials. In some embodiments, the upper electrode CE2 may include the same material as the lower electrode CE1 and / or the lower metal layer BML.

[0100] The upper electrode CE2 may overlap the drive gate electrode G1 and / or the lower electrode CE1. The upper electrode CE2 may include an opening 1310OP so that the first connecting electrode 1630, which electrically connects the drive gate electrode G1 of the drive transistor T1 and the compensation semiconductor layer A3 of the compensation transistor T3, is connected to the drive gate electrode G1. The opening 1310OP may overlap a portion of the drive gate electrode G1.

[0101] The first interlayer insulating layer 114 may be disposed on the upper electrode CE2. The first interlayer insulating layer 114 may be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0102] An oxide semiconductor pattern 1410 may be disposed on the first interlayer insulating layer 114. In this regard, Figure 4 illustrates a compensation semiconductor layer A3 of the compensation transistor T3, which corresponds to a part of the oxide semiconductor pattern 1410. The oxide semiconductor pattern 1410 may include ITZO (InSnZnO), IGZO (InGaZnO), or the like.

[0103] The compensation semiconductor layer A3 includes a channel region C3 and conductive regions disposed on both sides of the channel region C3, and FIG. 4 illustrates one region B3 of the conductive regions disposed on one side of the channel region C3. The compensation semiconductor layer A3 and the driving semiconductor layer A1 may be disposed on different layers. For example, the driving semiconductor layer A1 may be disposed on the buffer layer 111, and the compensation semiconductor layer A3 may be disposed on the first interlayer insulating layer 114. In other words, the vertical distance from the substrate 100 to the compensation semiconductor layer A3 may be greater than the vertical distance from the substrate 100 to the driving semiconductor layer A1.

[0104] The third gate electrode G3 may be disposed below and / or above the compensation semiconductor layer A3. In one embodiment, FIG. 4 illustrates the third gate electrode G3 including a lower compensation gate electrode G3a disposed below the compensation semiconductor layer A3 and an upper compensation gate electrode G3b disposed on the compensation semiconductor layer A3. In other embodiments, either the lower compensation gate electrode G3a or the upper compensation gate electrode G3b may be omitted.

[0105] The lower compensation gate electrode G3a may include the same material as the upper electrode CE2 and may be located on the same layer (e.g., the second gate insulating layer 113). The upper compensation gate electrode G3b may be disposed on the compensation semiconductor layer A3 with the third gate insulating layer 115 sandwiched therebetween. The upper compensation gate electrode G3b may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials.

[0106] 4 illustrates that the third gate insulating layer 115 is disposed only between the upper compensation gate electrode G3b and the compensation semiconductor layer A3, but the present invention is not limited thereto. In other embodiments, the third gate insulating layer 115 may be formed to entirely cover the substrate 100, similar to other insulating layers, for example, the first gate insulating layer 112. The third gate insulating layer 115 may also be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0107] The second interlayer insulating layer 116 may be disposed on the upper compensation gate electrode G3b. The second interlayer insulating layer 116 may be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0108] The first connecting electrode 1630 and the compensation scan line GCL may be disposed on the second interlayer insulating layer 116. The first connecting electrode 1630 and the compensation scan line GCL may be formed of a single layer or multiple layers including aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu). In one embodiment, the first connecting electrode 1630 and the compensation scan line GCL may have an aluminum / titanium / aluminum three-layer structure. The compensation scan line GCL may be electrically connected to the upper compensation gate electrode G3b through a contact hole penetrating the second interlayer insulating layer 116.

[0109] The first organic insulating layer 121 may be formed on the first connecting electrode 1630 and the compensation scan line GCL. The first organic insulating layer 121 may include an organic material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0110] The driving voltage line PL may be disposed on the first organic insulating layer 121. The driving voltage line PL may overlap the driving transistor T1 and the first capacitor Cst. In some embodiments, the driving voltage line PL may overlap the compensation transistor T3. The driving voltage line PL may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above materials. In one embodiment, the driving voltage line PL may have a three-layer structure of aluminum layer / titanium layer / aluminum layer.

[0111] The second organic insulating layer 123 may be disposed on the driving voltage line PL. The second organic insulating layer 123 may include an organic material such as BCB (Benzocyclobutene), polyimide, or HMDSO (hexamethyldisiloxane).

[0112] The light emitting diode LED may be formed on the second organic insulating layer 123. The light emitting diode LED may include a pixel electrode 210, an intermediate layer 220, and a counter electrode 230 disposed in relation to the second organic insulating layer 123.

[0113] The edge of the pixel electrode 210 may be covered by the bank layer 130, and an inner portion of the pixel electrode 210 may overlap the intermediate layer 220 through an opening 130OP of the bank layer 130. The pixel electrode 210 may be formed for each light emitting diode LED, whereas the counter electrode 230 may be formed corresponding to a plurality of light emitting diodes LED. In other words, a plurality of light emitting diodes LED may share the counter electrode 230, and the stacked structure of the pixel electrode 210, the intermediate layer 220, and the counter electrode 230 may correspond to the light emitting diode LED.

[0114] The intermediate layer 220 may include an emissive layer. In some embodiments, the intermediate layer 220 may further include an emissive layer and a functional layer. The functional layer may include a hole-transporting layer (HIL), a hole-injecting layer (HIL), an electron-transporting layer (ETL), and / or an electron-injecting layer (EIL). In still other embodiments, the intermediate layer 220 may include a first stack including an emissive layer and a functional layer, a second stack including an emissive layer and a functional layer, and a charge-generation layer between the first stack and the second stack. The charge-generation layer may include a negative charge-generation layer and a positive charge-generation layer. The negative charge-generation layer and the positive charge-generation layer may further increase the luminous efficiency of a tandem light-emitting diode (LED) having multiple emissive layers.

[0115] The negative charge generation layer may also be an n-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metal material. The positive charge generation layer may also be a p-type charge generation layer. The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metal material.

[0116] An encapsulation layer 300 may be disposed on the light-emitting diode LED. The encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 4 illustrates that, in one embodiment, the encapsulation layer 300 includes a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include silicon oxide, silicon nitride, and / or silicon oxynitride, and the organic encapsulation layer 320 may include an organic insulator.

[0117] 5 is a plan view schematically illustrating a portion of wiring arranged in a display area of ​​a display device according to an embodiment of the present invention. Pixel circuits PC may be arranged in a first direction (e.g., ±x direction) and a second direction (e.g., ±y direction) in the display area DA, and FIG. 5 illustrates pixel circuits PC arranged in the same row, e.g., the i-th row.

[0118] The pixel circuits PC may be electrically connected to the light emitting diodes, respectively. For convenience of explanation, the pixel circuits PC electrically connected to the first, second, and third light emitting diodes emitting light of different colors will be referred to as the first, second, and third pixel circuits PC1, PC2, and PC3.

[0119] The first pixel circuit PC1 may be electrically connected to a first light emitting diode emitting light of a first color, the second pixel circuit PC2 may be electrically connected to a second light emitting diode emitting light of a second color, and the third pixel circuit PC3 may be electrically connected to a third light emitting diode emitting light of a third color. In some embodiments, the first color, the second color, and the third color may be selected from red, green, and blue as lights of different colors.

[0120] The first to third pixel circuits PC1, PC2, and PC3 may be repeatedly arranged along a first direction (e.g., ±x direction). The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may be arranged in this order along the first direction (e.g., ±x direction), and the distance between the second pixel circuit PC2 and the third pixel circuit PC3 may be greater than the distance between the second pixel circuit PC2 and the first pixel circuit PC1.

[0121] In the display area DA, lines electrically connected to the pixel circuits PC, for example, first conductive lines (hereinafter referred to as horizontal conductive lines) extending along a first direction (e.g., ±x direction) and second conductive lines (hereinafter referred to as vertical conductive lines) extending along a second direction (e.g., ±y direction), may be arranged.

[0122] The horizontal conductive lines extending along the first direction (e.g., ±x direction) may include a first initialization horizontal voltage line HVIL, a first initialization control line GIL, a scan line GWL, a compensation scan line GCL, an emission control line EML, a repair line RL, a second initialization control line GBL, a bias voltage line VOL, and a second initialization horizontal voltage line HVAL. The second initialization horizontal voltage line HVAL may include a 2-1st initialization horizontal voltage line HVAL(R) and a 2-2nd initialization horizontal voltage line HVAL(GB).

[0123] The vertical conductive lines extending along the second direction (e.g., ±y direction) may include a first initialization vertical voltage line VVIL, a common voltage line VSL providing a common voltage ELVSS (FIG. 3), and a second initialization vertical voltage line VVAL. The second initialization vertical voltage line VVAL may include a 2-1 initialization vertical voltage line VVAL(R) and a 2-2 initialization vertical voltage line VVAL(GB).

[0124] The first initialization vertical voltage line VVIL and the first initialization horizontal voltage line HVIL, which provide the first initialization voltage Vint, may be electrically connected in the display area DA. The second-first initialization horizontal voltage line HVAL(R) and the second-first initialization vertical voltage line VVAL(R), which provide the second-first initialization voltage Vaint(R) to the first pixel circuit PC1, may be electrically connected in the display area DA. The second-second initialization vertical voltage line VVAL(GB) and the second-second initialization horizontal voltage line HVAL(GB), which provide the second-second initialization voltage Vaint(GB) to the second pixel circuit PC2 and the second pixel circuit PC3, may be electrically connected in the display area DA.

[0125] 5 illustrates that the second pixel circuit PC2 and the third pixel circuit PC3 are electrically connected to the same voltage line, for example, the 2-2 initialization vertical voltage line VVAL(GB) and / or the 2-2 initialization horizontal voltage line HVAL(GB), but the present invention is not limited thereto. In another embodiment, the horizontal and vertical voltage lines for applying the second initialization voltage to the second pixel circuit PC2 and the horizontal and vertical voltage lines for applying the second initialization voltage to the third pixel circuit PC3 may be independent of each other.

[0126] 6 is a plan view illustrating first to third pixel circuits of a display device according to an embodiment of the present invention, in which a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3 are arranged along the i-th row.

[0127] 6, the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may each include a plurality of transistors and capacitors. In some embodiments, FIG. 6 illustrates that the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 each include the eight transistors T1, T2, T3, T4, T5, T6, T7, and T8 and the first capacitor Cst described with reference to FIG.

[0128] The driving transistor T1 may overlap the first capacitor Cst. The switching transistors (e.g., T2, T3, T4, T5, T6, T7, and T8) may be arranged above and / or below the driving transistor T1 and / or the first capacitor Cst in a planar view. In one embodiment, FIG. 6 illustrates that the data write transistor T2, the compensation transistor T3, and the first initialization transistor T4 are arranged above (e.g., in the +y direction) the driving transistor T1 and / or the first capacitor Cst in a planar view. The operation control transistor T5, the light-emitting control transistor T6, the second initialization transistor T7, and the bias transistor T8 may be arranged below (e.g., in the -y direction) the driving transistor T1 and / or the first capacitor Cst in a planar view.

[0129] The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 are arranged along a first direction, and a first separation distance between the second pixel circuit PC2 and the third pixel circuit PC3 may be greater than a second separation distance between the first pixel circuit PC1 and the second pixel circuit PC2. A vertical voltage line VCL may be disposed in a space (hereinafter referred to as a separation space IVA) between the second pixel circuit PC2 and the third pixel circuit PC3, which has the first separation distance. The vertical voltage line VCL shown in FIG. 6 may also be the first initialization vertical voltage line VVIL, the common voltage line VSL, the 2-1st initialization vertical voltage line VVAL(R), and / or the 2-2nd initialization vertical voltage line VVAL(GB) described with reference to FIG. 5.

[0130] 7 to 15 are plan views showing processes for forming the first to third pixel circuits shown in FIG.

[0131] 7, a lower metal layer BML may be disposed on a substrate. The lower metal layer BML may include main portions BMLc corresponding to the first to third pixel circuits PC1, PC2, and PC3, respectively. The lower metal layer BML may include first branch portions BMLa connecting the main portions BMLc along a first direction (e.g., ±x direction) and second branch portions BMLb connecting the main portions BMLc arranged in pixel circuits arranged in different rows along a second direction (e.g., ±y direction). The main portions BMLc, the first branch portions BMLa, and the second branch portions BMLb may be integrally connected.

[0132] The lower metal layer BML is electrically connected to the driving voltage line PL (FIG. 3) and may have the same voltage level as the driving voltage line PL (FIG. 14) described below.

[0133] The lower metal layer BML may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In some embodiments, the lower metal layer BML may be a single layer of molybdenum, a bilayer structure in which a molybdenum layer and a titanium layer are stacked, or a trilayer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0134] 7 and 8, a buffer layer 111 (FIG. 4) may be disposed on the lower metal layer BML, and a first silicon semiconductor pattern 1110 and a second silicon semiconductor pattern 1120 may be disposed on the buffer layer 111 (FIG. 4).

[0135] The first silicon semiconductor patterns 1110 and the second silicon semiconductor patterns 1120 may be arranged corresponding to the first to third pixel circuits PC1, PC2, and PC3, respectively. The first silicon semiconductor patterns 1110 arranged in the first to third pixel circuits PC1, PC2, and PC3, respectively, may be separated and spaced apart from each other. The first silicon semiconductor patterns 1110 and the second silicon semiconductor patterns 1120 corresponding to the same pixel circuit may also be spaced apart from each other, but the present invention is not limited thereto. In another embodiment, the first silicon semiconductor patterns 1110 and the second silicon semiconductor patterns 1120 corresponding to the same pixel circuit may be integrally connected.

[0136] The first silicon semiconductor pattern 1110 may include a driving semiconductor layer A1 of the driving transistor T1 (FIG. 6), a semiconductor layer of the data write transistor T2 (FIG. 6) (hereinafter referred to as a data write semiconductor layer A2), a semiconductor layer of the operation control transistor T5 (FIG. 6) (hereinafter referred to as an operation control semiconductor layer A5), a semiconductor layer of the light-emitting control transistor T6 (FIG. 6) (hereinafter referred to as a light-emitting control semiconductor layer A6), and a semiconductor layer of the second initialization transistor T7 (FIG. 6) (hereinafter referred to as a second initialization semiconductor layer A7), as described with reference to FIG. 6. The second silicon semiconductor pattern 1120 may include a semiconductor layer of the bias transistor T8 (FIG. 6) (hereinafter referred to as a bias semiconductor layer; A8).

[0137] The first silicon semiconductor pattern 1110 and the second silicon semiconductor pattern 1120 may include amorphous silicon or polysilicon. For example, the first silicon semiconductor pattern 1110 and the second silicon semiconductor pattern 1120 may include polysilicon crystallized at a low temperature.

[0138] 8 and 9, the first gate insulating layer 112 (FIG. 4) may be disposed on the first silicon semiconductor pattern 1110 and the second silicon semiconductor pattern 1120, and the first conductive pattern 1210, the second conductive pattern 1220, the emission control line EML, the second initialization control line GBL, and the 2-2nd initialization horizontal voltage line HVAL(GB) may be disposed on the first gate insulating layer 112 (FIG. 4).

[0139] The first conductive pattern 1210, the second conductive pattern 1220, the light emitting control line EML, the second initialization control line GBL, and the 2-2nd initialization horizontal voltage line HVAL(GB) may include the same material. The first conductive pattern 1210, the second conductive pattern 1220, the light emitting control line EML, the second initialization control line GBL, and the 2-2nd initialization horizontal voltage line HVAL(GB) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials.

[0140] The first conductive pattern 1210, the second conductive pattern 1220, the emission control line EML, and the second initialization control line GBL may each include a gate electrode overlapping the first silicon semiconductor pattern 1110 and / or the second silicon semiconductor pattern 1120.

[0141] The first conductive pattern 1210 may be disposed in each of the first to third pixel circuits PC1, PC2, and PC3 and may have an isolated shape. The first conductive pattern 1210 may include a driving gate electrode G1 of the driving transistor T1. The driving semiconductor layer A1 may include a channel region overlapping the first conductive pattern 1210, which is the driving gate electrode G1, and source and drain regions disposed on both sides of the channel region. Referring to FIGS. 7 and 9, the channel region of the driving semiconductor layer A1 may overlap a portion (e.g., a main portion, BMLc) of the lower metal layer BML. The channel region of the driving semiconductor layer A1 of each of the first and second pixel circuits PC1 and PC2 may have a shape with multiple bends (e.g., an omega shape). Considering the efficiency of the third light emitting diode electrically connected to the third pixel circuit PC3, the channel region of the driving semiconductor layer A1 of the third pixel circuit PC3 may have a linear shape.

[0142] The fact that the separation distance between the second pixel circuit PC2 and the third pixel circuit PC3 is greater than the separation distance between the second pixel circuit PC2 and the first pixel circuit PC1 can be confirmed by the fact that the separation distance between the drive transistor T1 of the second pixel circuit PC2 and the drive transistor T1 of the third pixel circuit PC3 is greater than the separation distance between the drive transistor T1 of the second pixel circuit PC2 and the drive transistor T1 of the first pixel circuit PC1. For example, this can be confirmed by the fact that the first separation distance DS1 between the channel region of the drive transistor T1 of the second pixel circuit PC2 and the channel region of the drive transistor T1 of the third pixel circuit PC3, measured along a first direction (e.g., the ±x direction), is greater than the second separation distance DS2 between the channel region of the drive transistor T1 of the second pixel circuit PC2 and the channel region of the drive transistor T1 of the first pixel circuit PC1. In other words, it can be confirmed that the first separation distance DS1 between the driving gate electrode G1 of the driving transistor T1 of the second pixel circuit PC2 and the driving gate electrode G1 of the driving transistor T1 of the third pixel circuit PC3 measured along the first direction (e.g., the ±x direction) is greater than the second separation distance DS2 between the driving gate electrode G1 of the driving transistor T1 of the second pixel circuit PC2 and the driving gate electrode G1 of the driving transistor T1 of the first pixel circuit PC1.

[0143] In some embodiments, the first conductive pattern 1210 may include the bottom electrode CE1 of the first capacitor Cst, and may also be the driving gate electrode G1 and / or the bottom electrode CE1 of the first capacitor Cst.

[0144] The second conductive patterns 1220 may be disposed in the first, second, and third pixel circuits PC1, PC2, and PC3, respectively, and may have an isolated shape. The second conductive patterns 1220 may include the second gate electrode G2 of the data write transistor T2. The data write semiconductor layer A2 may include a channel region overlapping the second gate electrode G2 of the data write transistor T2, and source and drain regions disposed on both sides of the channel region.

[0145] The emission control line EML may extend along a first direction (e.g., ±x direction) to pass through the first to third pixel circuits PC1, PC2, and PC3. The emission control line EML may include an operation control gate electrode G5 of the operation control transistor T5 and an emission control gate electrode G6 of the emission control transistor T6. The operation control semiconductor layer A5 may include a channel region overlapping the operation control gate electrode G5, and source and drain regions disposed on both sides of the channel region. The emission control semiconductor layer A6 may include a channel region overlapping the emission control gate electrode G6, and source and drain regions disposed on both sides of the channel region.

[0146] The second initialization control line GBL may extend along a first direction (e.g., ±x direction) to pass through the first to third pixel circuits PC1, PC2, and PC3. The second initialization control line GBL may include a second initialization gate electrode G7 of the second initialization transistor T7 and a bias gate electrode G8 of the bias transistor T8. The second initialization semiconductor layer A7 may include a channel region overlapping the second initialization gate electrode G7, and source and drain regions disposed on both sides of the channel region. The bias semiconductor layer A8 may include a channel region overlapping the bias gate electrode G8, and source and drain regions disposed on both sides of the channel region.

[0147] A second gate insulating layer 113 (FIG. 4) may be disposed on the first conductive pattern 1210, the second conductive pattern 1220, the emission control line EML, the second initialization control line GBL, and the 2-2nd initialization horizontal voltage line HVAL(GB) described with reference to FIG. 9. Then, a third conductive pattern 1310, a fourth conductive pattern 1320, a fifth conductive pattern 1330, and a bridge pattern 1340 may be disposed on the second gate insulating layer 113 (FIG. 4), as shown in FIG.

[0148] The third conductive pattern 1310, the fourth conductive pattern 1320, and the fifth conductive pattern 1330 may include the same material. The third conductive pattern 1310, the fourth conductive pattern 1320, the fifth conductive pattern 1330, and the bridge pattern 1340 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials.

[0149] 9 and 10, the third conductive pattern 1310 (FIG. 10) may be disposed to overlap the first conductive pattern 1210 (FIG. 9). The third conductive pattern 1310 may be a horizontal driving voltage line having a driving voltage level and may extend along a first direction (e.g., ±x direction) to pass through the first to third pixel circuits PC1, PC2, and PC3.

[0150] In one embodiment, the third conductive pattern 1310 may include a first portion 1311 overlapping the first conductive pattern 1210 (FIG. 9) arranged in each of the first to third pixel circuits PC1, PC2, and PC3, and a second portion 1312 extending along a first direction (e.g., the x-direction) to connect the first portions 1311 arranged in each of the first to third pixel circuits PC1, PC2, and PC3.

[0151] The first conductive patterns 1210 disposed in the first, second, and third pixel circuits PC1, PC2, and PC3 may correspond to the lower electrodes CE1 of the first capacitors Cst, and the first portions 1311 of the third conductive patterns 1310 disposed in the first, second, and third pixel circuits PC1, PC2, and PC3 may correspond to the upper electrodes CE2 of the first capacitors Cst.

[0152] 7 and 10, a first portion 1311 of the third conductive pattern 1310 may overlap a main portion BMLc of the lower metal layer BML, and a second portion 1312 of the third conductive pattern 1310 may overlap a first branch portion BMLa of the lower metal layer BML.

[0153] By arranging the third conductive pattern 1310 and the lower metal layer BML, which have the same voltage level, to overlap each other, coupling between the driving transistor T1 and its surrounding components (wiring or electrodes) can be prevented, and the transistors, voltage lines, and signal lines of the first to third pixel circuits PC1, PC2, and PC3 can be efficiently arranged in a limited space, thereby improving space efficiency (e.g., improving integration). The third conductive pattern 1310 has a closed-shaped opening 1310OP.

[0154] The fourth conductive pattern 1320 and the fifth conductive pattern 1330 may be disposed in the first to third pixel circuits PC1, PC2, and PC3, respectively. The fourth conductive pattern 1320 and the fifth conductive pattern 1330 may have an isolated shape.

[0155] The fourth conductive pattern 1320 may correspond to a lower compensation gate electrode G3a of a compensation transistor T3, which will be described later, and the fifth conductive pattern 1330 may correspond to a lower first initialization gate electrode G4a of a first initialization transistor T4, which will be described later.

[0156] The bridge pattern 1340 may be disposed in the separation space IVA between the second pixel circuit PC2 and the third pixel circuit PC3.

[0157] The first interlayer insulating layer 114 (FIG. 4) may be disposed on the third conductive pattern 1310, the fourth conductive pattern 1320, the fifth conductive pattern 1330, and the bridge pattern 1340 described with reference to FIG. 10. Then, as shown in FIG. 11, an oxide semiconductor pattern 1410 may be formed on the first interlayer insulating layer 114 (FIG. 4).

[0158] 11, the oxide semiconductor pattern 1410 may have a folded shape. For example, the oxide semiconductor pattern 1410 may include a portion corresponding to the compensation semiconductor layer A3 extending along a first direction (e.g., ±x direction) to overlap with the fourth conductive pattern 1320, and a portion corresponding to the first initialization semiconductor layer A4 extending along a second direction (e.g., ±y direction) to overlap with the fifth conductive pattern 1330.

[0159] The oxide semiconductor pattern 1410 may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, etc. Oxide semiconductors have a wide band gap (approximately 3.1 eV), high carrier mobility, and low leakage current, so that voltage drop is not large even with long driving times, and brightness change due to voltage drop is not large even with low frequency driving.

[0160] 12, a sixth conductive pattern 1510, a seventh conductive pattern 1520, a repair line RL, and a 2-1st initialization horizontal voltage line HVAL(R) may be disposed on the structure described with reference to FIG.

[0161] The sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL(R) may include the same material. The sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL(R) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials. In one embodiment, the sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL(R) may have a three-layer structure of aluminum layer / titanium layer / aluminum layer.

[0162] The sixth conductive pattern 1510 and the seventh conductive pattern 1520 may be disposed in the first to third pixel circuits PC1, PC2, and PC3, respectively. The sixth conductive pattern 1510 and the seventh conductive pattern 1520 may have an isolated shape.

[0163] The sixth conductive pattern 1510 and the seventh conductive pattern 1520 may each include a gate electrode overlapping the oxide semiconductor pattern 1410. The sixth conductive pattern 1510 may include an upper compensation gate electrode G3b overlapping a portion of the oxide semiconductor pattern 1410, for example, the compensation semiconductor layer A3. The seventh conductive pattern 1520 may include an upper first initialization gate electrode G4b overlapping a portion of the oxide semiconductor pattern 1410, for example, the first initialization semiconductor layer A4.

[0164] The compensation semiconductor layer A3 disposed in each of the first to third pixel circuits PC1, PC2, and PC3 may include a channel region overlapping the fourth conductive pattern 1320 disposed under the compensation semiconductor layer A3 and the sixth conductive pattern 1510 disposed on the compensation semiconductor layer A3, and source and drain regions disposed on both sides of the channel region. The first initialization semiconductor layer A4 disposed in each of the first to third pixel circuits PC1, PC2, and PC3 may include a channel region overlapping the fifth conductive pattern 1330 disposed under the first initialization semiconductor layer A4 and the seventh conductive pattern 1520 disposed on the first initialization semiconductor layer A4, and source and drain regions disposed on both sides of the channel region.

[0165] The fourth conductive pattern 1320 and the sixth conductive pattern 1510 may correspond to the lower compensation gate electrode G3a and the upper compensation gate electrode G3b of the compensation transistor T3, respectively. The fifth conductive pattern 1330 and the seventh conductive pattern 1520 may correspond to the lower first initialization gate electrode G4a and the upper first initialization gate electrode G4b of the first initialization transistor T4, respectively.

[0166] 12 illustrates that the compensation transistor T3 includes a dual gate electrode of a lower compensation gate electrode G3a and an upper compensation gate electrode G3b, and the first initialization transistor T4 includes a dual gate electrode of a lower first initialization gate electrode G4a and an upper first initialization gate electrode G4b, but the present invention is not limited thereto. In another embodiment, the compensation transistor T3 may include one of the lower compensation gate electrode G3a and the upper compensation gate electrode G3b, and the first initialization transistor T4 may include one of the lower first initialization gate electrode G4a and the upper first initialization gate electrode G4b.

[0167] The 2-1st initialization horizontal voltage line HVAL(R) may be disposed on the same layer as the sixth conductive pattern 1510, which is the gate electrode of the compensation transistor T3 (e.g., the upper compensation gate electrode G3b), the seventh conductive pattern 1520, which is the gate electrode of the first initialization transistor T4 (e.g., the upper first initialization gate electrode G4b), and the repair line RL. For example, the 2-1st initialization horizontal voltage line HVAL(R), the sixth conductive pattern 1510, the seventh conductive pattern 1520, and the repair line RL may each be disposed on the third gate insulating layer 115 (FIG. 4).

[0168] 4, the third gate insulating layers 115 (FIG. 4) disposed below the sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL(R) may be separated from one another, but the present invention is not limited thereto. In other embodiments, the third gate insulating layers 115 (FIG. 4) disposed below the sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL(R) may be integrally connected.

[0169] The 2-1st initialization horizontal voltage line HVAL(R) and the 2-2nd initialization horizontal voltage line HVAL(GB) may overlap each other. The 2-2nd initialization horizontal voltage line HVAL(GB) and the 2-1st initialization horizontal voltage line HVAL(R) may have a constant voltage level. For example, the 2-2nd initialization horizontal voltage line HVAL(GB) and the 2-1st initialization horizontal voltage line HVAL(R) may have the same or similar voltage levels. By overlapping the 2-2nd initialization horizontal voltage line HVAL(GB) and the 2-1st initialization horizontal voltage line HVAL(R), which have the same or similar voltage levels, the 2-2nd initialization horizontal voltage line HVAL(GB) and the 2-1st initialization horizontal voltage line HVAL(R) may be arranged to minimize the occurrence of parasitic capacitance between the electrodes, voltage lines, and / or signal lines of the transistors of the first to third pixel circuits PC1, PC2, and PC3 in a limited space, thereby efficiently utilizing the space (e.g., improving the integration density).

[0170] As shown in FIG. 12, each of the 2-1st initialization horizontal voltage line HVAL(R) and the 2-2nd initialization horizontal voltage line HVAL(GB) may cross the second branch portion BMLb of the lower metal layer BML in a plan view.

[0171] 12 illustrates that the 2-1st initialization horizontal voltage line HVAL(R) is disposed on the same layer and includes the same material as the sixth conductive pattern 1510, which is the upper compensation gate electrode G3b of the compensation transistor T3, and / or the seventh conductive pattern 1520, which is the first upper initialization gate electrode G4b of the first initialization transistor T4, but the present invention is not limited thereto. In another embodiment, the 2-1st initialization horizontal voltage line HVAL(R) may be disposed on the same layer and include the same material as the fourth conductive pattern 1320, which is the lower compensation gate electrode G3a of the compensation transistor T3, and / or the fifth conductive pattern 1330, which is the first lower initialization gate electrode G4a of the first initialization transistor T4.

[0172] A second interlayer insulating layer 116 (FIG. 4) may be disposed on the sixth conductive pattern 1510, the seventh conductive pattern 1520, the repair line RL, and the 2-1st initialization horizontal voltage line HVAL(R) described with reference to FIG. 12. Then, as shown in FIG. 13, a voltage transmission line 1610, a first pixel connecting electrode 1620, a first connecting electrode 1630, a second connecting electrode 1640, a third connecting electrode 1650, a fourth connecting electrode 1660, a fifth connecting electrode 1670, a first initialization horizontal voltage line HVIL, a first initialization control line GIL, a scan line GWL, a compensation scan line GCL, and a bias voltage line VOL may be disposed on the second interlayer insulating layer 116.

[0173] The voltage transmission line 1610, the first pixel connecting electrode 1620, the first connecting electrode 1630, the second connecting electrode 1640, the third connecting electrode 1650, the fourth connecting electrode 1660, the fifth connecting electrode 1670, the first initialization horizontal voltage line HVIL, the first initialization control line GIL, the scan line GWL, the compensation scan line GCL, and the bias voltage line VOL may include the same material. The voltage transmission line 1610, the first pixel connecting electrode 1620, the first connecting electrode 1630, the second connecting electrode 1640, the third connecting electrode 1650, the fourth connecting electrode 1660, the fifth connecting electrode 1670, the first initialization horizontal voltage line HVIL, the first initialization control line GIL, the scan line GWL, the compensation scan line GCL, and the bias voltage line VOL may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0174] The voltage transmission line 1610 may extend in a first direction (e.g., ±x direction). The voltage transmission line 1610 passes through each of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3. The voltage transmission line 1610 may overlap with the third conductive pattern 1310 ( FIG. 11 ). In some embodiments, the voltage transmission line 1610 may include a main portion extending in the first direction (e.g., ±x direction) and overlapping with the third conductive pattern 1310, and branch portions extending from the main portion along a second direction (e.g., ±y direction). The branch portions may overlap with the emission control line EML and / or the repair line RL.

[0175] In one embodiment, the voltage transmission line 1610 may have a voltage level of the driving voltage ELVDD (FIG. 3). In one embodiment, the voltage transmission line 1610 may be electrically connected to a driving voltage line PL (described later) and may have a voltage level of the driving voltage ELVDD (FIG. 3).

[0176] The voltage transmission wiring 1610 may be electrically connected to the lower metal layer BML (see FIG. 7) through the first-1 contact hole CNT1a. The voltage transmission wiring 1610 may be electrically connected to the third conductive pattern 1310 (see FIG. 12) through the second-1 contact hole CNT1b. The voltage transmission wiring 1610 may be electrically connected to the first silicon semiconductor pattern 1110 (see FIG. 8) through the third contact hole CNT1c. The lower metal layer (BML, see FIG. 7) may have a voltage level of the driving voltage ELVDD through the connection structure between the voltage transmission wiring 1610 and the lower metal layer (BML, see FIG. 7) through the first-1 contact hole CNT1a. The voltage transmission wiring 1610 may provide the driving voltage ELVDD to the upper electrode CE2 (see FIG. 10) of the storage capacitor Cst and the operation control semiconductor layer A5 (see FIG. 8) of the operation control transistor T5 via the first-second contact hole CNT1b and the first-third contact hole CNT1c.

[0177] The first pixel connecting electrode 1620 may be spaced apart from the voltage transmission line 1610. The first pixel connecting electrode 1620 may be electrically insulated from the voltage transmission line 1610.

[0178] The first pixel connecting electrode 1620 may be disposed in the same layer as the voltage transmission line 1610. The first pixel connecting electrode 1620 may include a 1-1 pixel connecting electrode 1620a, a 1-2 pixel connecting electrode 1620b, and a 1-3 pixel connecting electrode 1620c disposed in the first to third pixel circuits PC1, PC2, and PC3, respectively. The 1-1 pixel connecting electrode 1620a, the 1-2 pixel connecting electrode 1620b, and the 1-3 pixel connecting electrode 1620c may be disposed apart from the voltage transmission line 1610.

[0179] The first pixel connecting electrode 1620 may be electrically connected to the first silicon semiconductor pattern 1110 through the second contact hole CNT2. For example, the 1-1 pixel connecting electrode 1620a may be electrically connected to the first silicon semiconductor pattern 1110 (see FIG. 9) corresponding to the first pixel circuit PC1 through the second contact hole CNT2. The first pixel connecting electrode 1620 may be electrically connected to the emission control semiconductor layer A6 (see FIG. 9) of the emission control transistor T6 (see FIG. 9) and / or the second initialization semiconductor layer A7 (see FIG. 9) of the second initialization transistor T7 formed along the first silicon semiconductor pattern 1110.

[0180] The first linking electrode 1630, the second linking electrode 1640, the third linking electrode 1650, the fourth linking electrode 1660, and the fifth linking electrode 1670 may each have an isolated shape. The first linking electrode 1630, the second linking electrode 1640, the third linking electrode 1650, the fourth linking electrode 1660, and the fifth linking electrode 1670 may be disposed in the first to third pixel circuits PC1, PC2, and PC3, respectively.

[0181] The first connecting electrode 1630 may electrically connect the first conductive pattern 1210 (see FIG. 9) and the oxide semiconductor pattern 1410 (see FIG. 11). The first connecting electrode 1630 may be electrically connected to the first conductive pattern 1210 (see FIG. 9) through the 3-1 contact hole CNT3a. The first connecting electrode 1630 may be electrically connected to the oxide semiconductor pattern 1410 (e.g., the compensation semiconductor layer A3 of the compensation transistor T3, see FIG. 11) through the 3-2 contact hole CNT3b. The first connecting electrode 1630 may electrically connect the driving gate electrode G1 of the driving transistor T1 (see FIG. 9) and the compensation semiconductor layer A3 of the compensation transistor T3 (see FIG. 11). The first connecting electrode 1630 may electrically connect the storage capacitor Cst and the compensation transistor T3.

[0182] The first connecting electrode 1630 may overlap a portion of the lower metal layer BML (see FIG. 7), for example, the second branch portion BMLb.

[0183] The second connecting electrode 1640 may electrically connect the first silicon semiconductor pattern 1110 (see FIG. 9) and the oxide semiconductor pattern 1410 (see FIG. 12). The second connecting electrode 1640 may be electrically connected to the first silicon semiconductor pattern 1110 (see FIG. 9) through the 4-1 contact hole CNT4a. The second connecting electrode 1640 may be electrically connected to the oxide semiconductor pattern 1410 (see FIG. 12) through the 4-2 contact hole CNT4b. The second connecting electrode 1640 may electrically connect the driving semiconductor layer A1 of the driving transistor T1 (see FIG. 9) and the compensation semiconductor layer A3 of the compensation transistor T3 (see FIG. 12). The second connecting electrode 1640 may electrically connect the emission control semiconductor layer A6 of the emission control transistor T6 (see FIG. 9) and the compensation semiconductor layer A3 of the compensation transistor T3 (see FIG. 12).

[0184] The third connecting electrode 1650 may be electrically connected to the first silicon semiconductor pattern 1110 (see FIG. 9) through the fifth contact hole CNT5. For example, the third connecting electrode 1650 corresponding to the first pixel circuit PC1 may be electrically connected to the first data line DL1, which will be described later with reference to FIG. 14. That is, the third connecting electrode 1650 corresponding to the first pixel circuit PC1 may transmit a data signal applied to the first data line DL1 to the data write semiconductor layer A2 (see FIG. 9) of the data write transistor T2.

[0185] The fourth connecting electrode 1660 may electrically connect the first silicon semiconductor pattern 1110 (see FIG. 9) and the second silicon semiconductor pattern 1120 (see FIG. 9). The fourth connecting electrode 1660 may be electrically connected to the first silicon semiconductor pattern 1110 (see FIG. 9) through the 6-1 contact hole CNT6a. The fourth connecting electrode 1660 may be electrically connected to the second silicon semiconductor pattern 1120 (see FIG. 9) through the 6-2 contact hole CNT6b. The fourth connecting electrode 1660 may electrically connect the operation control semiconductor layer A5 (see FIG. 9) of the operation control transistor T5 formed along the first silicon semiconductor pattern 1110 (see FIG. 9) and the bias semiconductor layer A8 (see FIG. 9) of the bias transistor T8 formed along the second silicon semiconductor pattern 1120 (see FIG. 9).

[0186] The fifth connecting electrode 1670 corresponding to the first pixel circuit PC1 may electrically connect the first silicon semiconductor pattern 1110 (see FIG. 9) corresponding to the first pixel circuit PC1 to the 2-1st initialization horizontal voltage line HVAL(R). The fifth connecting electrode 1670 corresponding to the first pixel circuit PC1 may electrically connect the second initialization semiconductor layer A7 (see FIG. 9) of the second initialization transistor T7 formed along the first silicon semiconductor pattern 1110 (see FIG. 9) to the 2-1st initialization horizontal voltage line HVAL(R).

[0187] The fifth connecting electrode 1670 corresponding to the first pixel circuit PC1 may be electrically connected to the second initialization semiconductor layer A7 (see FIG. 9) of the second initialization transistor T7 corresponding to the first pixel circuit PC1 through the 7-1 contact hole CNT7a and may be electrically connected to the 2-1 initialization horizontal voltage line HVAL(R) through the 7-2 contact hole CNT7b. The 2-1 initialization horizontal voltage line HVAL(R) may transmit the 2-1 initialization voltage Vaint(R) to the second initialization transistor T7 of the first pixel circuit PC1 through the fifth connecting electrode 1670.

[0188] The fifth connecting electrode 1670 corresponding to the second pixel circuit PC2 and the third pixel circuit PC3 may electrically connect the first silicon semiconductor pattern 1110 (see FIG. 9) and the 2-2 initialization horizontal voltage line HVAL(GB) corresponding to the second pixel circuit PC2 and the third pixel circuit PC3, respectively. The fifth connecting electrode 1670 corresponding to the second pixel circuit PC2 and the third pixel circuit PC3 may electrically connect the second initialization semiconductor layer A7 (see FIG. 9) of the second initialization transistor T7 and the 2-2 initialization horizontal voltage line HVAL(GB) corresponding to the second pixel circuit PC2 and the third pixel circuit PC3, respectively.

[0189] The fifth connecting electrodes 1670 corresponding to the second pixel circuits PC2 and the third pixel circuits PC3 are electrically connected to the second initialization semiconductor layers A7 (see FIG. 9) of the second initialization transistors T7 corresponding to the second pixel circuits PC2 and the third pixel circuits PC3 through the 7-1 contact holes CNT7a. The fifth connecting electrodes 1670 corresponding to the second pixel circuits PC2 and the third pixel circuits PC3 may be electrically connected to the 2-2 initialization horizontal voltage line HVAL(GB) through the 7-2 contact holes CNT7b. The 2-2 initialization horizontal voltage line HVAL(GB) may transmit the 2-2 initialization voltage Vaint(GB) to the second initialization transistors T7 (see FIG. 9) corresponding to the second pixel circuits PC2 and the third pixel circuits PC3 through the fifth connecting electrodes 1670 disposed in the second pixel circuits PC2 and the third pixel circuits PC3. In some embodiments, the 2-1st initialization voltage Vaint(R) and the 2-2nd initialization voltage Vaint(GB) may have the same voltage level.

[0190] The first initialization control line GIL, the scan line GWL, the compensation scan line GCL, the bias voltage line VOL, and the first initialization horizontal voltage line HVIL may extend in a first direction (for example, ±x direction).

[0191] The first initialization control line GIL may be electrically connected to the fifth conductive pattern 1330 (see FIG. 12) and the seventh conductive pattern 1520 (see FIG. 12) of each of the first to third pixel circuits PC1, PC2, and PC3. The first initialization control line GIL may be electrically connected to the fifth conductive pattern 1330 (see FIG. 12) of each of the first to third pixel circuits PC1, PC2, and PC3 through an 8-1 contact hole CNT8a. The first initialization control line GIL may be electrically connected to the seventh conductive pattern 1520 (see FIG. 12) of each of the first to third pixel circuits PC1, PC2, and PC3 through an 8-2 contact hole CNT8b. The first initialization control line GIL may provide a first initialization control signal GI (see FIG. 3) to the fifth conductive pattern 1330 (see FIG. 12), which is the lower first initialization gate electrode G4a of the first initialization transistor T4, and the seventh conductive pattern 1520 (see FIG. 12), which is the upper first initialization gate electrode G4b.

[0192] The scan line GWL may be electrically connected to the second conductive pattern 1220 (see FIG. 9) of each of the first to third pixel circuits PC1, PC2, and PC3 through the ninth contact hole CNT9. The scan line GWL may provide a scan signal GW (see FIG. 3) to the second conductive pattern 1220 (see FIG. 9), which is the data write gate electrode G2 (see FIG. 9) of the data write transistor T2 of each of the first to third pixel circuits PC1, PC2, and PC3.

[0193] The compensation scan line GCL may be electrically connected to the fourth conductive pattern 1320 (see FIG. 12) and the sixth conductive pattern 1510 (see FIG. 12) of each of the first through third pixel circuits PC1, PC2, and PC3. The compensation scan line GCL may be electrically connected to the fourth conductive pattern 1320 (see FIG. 12) of each of the first through third pixel circuits PC1, PC2, and PC3 through the 10-1 contact hole CNT10a. The compensation scan line GCL may be electrically connected to the sixth conductive pattern 1510 (see FIG. 12) of each of the first through third pixel circuits PC1, PC2, and PC3 through the 10-2 contact hole CNT10b. The compensation scan line GCL may provide a compensation scan signal GC (see FIG. 3) to the fourth conductive pattern 1320 (see FIG. 10), which is the lower compensation gate electrode G3a of the compensation transistor T3, and the sixth conductive pattern 1510, which is the upper compensation gate electrode G3b.

[0194] The bias voltage line VOL may be electrically connected to the second silicon semiconductor pattern 1120 (see FIG. 9) of each of the first through third pixel circuits PC1, PC2, and PC3 through the eleventh contact hole CNT11. The bias voltage line VOL may provide the bias voltage Vobs (see FIG. 3) to the bias semiconductor layer A8 (see FIG. 9) of the bias transistor T8 of each of the first through third pixel circuits PC1, PC2, and PC3.

[0195] The first initialization horizontal voltage line HVIL may be electrically connected to the oxide semiconductor patterns 1410 (FIG. 11) of the first to third pixel circuits PC1, PC2, and PC3 through the twelfth contact holes CNT12. That is, the first initialization horizontal voltage line HVIL may provide the first initialization voltage Vint (see FIG. 4) to the first initialization transistor T4 formed along the oxide semiconductor patterns 1410 (FIG. 11).

[0196] After disposing the second organic insulating layer 123 (see FIG. 4) on the structure described with reference to FIG. 13, the second pixel connecting electrode 1710, the driving voltage line PL, the first data line DL1, the second data line DL2, the third data line DL3, and the vertical voltage line VCL may be disposed on the second organic insulating layer 123 (see FIG. 4) as shown in FIG. 14.

[0197] 14, the driving voltage line PL, the first data line DL1, the second data line DL2, the third data line DL3, and the vertical voltage line VCL may extend along a second direction (e.g., the ±y direction). The driving voltage line PL, the first data line DL1, the second data line DL2, the third data line DL3, the vertical voltage line VCL, and the second pixel connecting electrode 1710 may include the same material.

[0198] The driving voltage line PL, the first data line DL1, the second data line DL2, the third data line DL3, the vertical voltage line VCL, and the second pixel connecting electrode 1710 may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0199] The driving voltage lines PL may be disposed in the first, second, and third pixel circuits PC1, PC2, and PC3, respectively. The driving voltage lines PL corresponding to any one of the first, second, and third pixel circuits PC1, PC2, and PC3 may be electrically connected to the voltage transmission line 1610 (see FIG. 13) through the fourteenth contact hole CNT14. The shapes and areas of the driving voltage lines PL disposed in the first, second, and third pixel circuits PC1, PC2, and PC3 may be different from each other.

[0200] The driving voltage line PL disposed in each of the first through third pixel circuits PC1, PC2, and PC3 may overlap the gate electrode of the compensation transistor T3 of each of the first through third pixel circuits PC1, PC2, and PC3, for example, the lower compensation gate electrode G3a and the upper compensation gate electrode G3b in FIG. 12, and may also overlap the first connecting electrode 1630 corresponding to each of the first through third pixel circuits PC1, PC2, and PC3. Here, the first connecting electrode 1630 may connect the compensation semiconductor layer of the compensation transistor T3 to the driving gate electrode G1 of the driving transistor T1. This overlapping structure may prevent unwanted parasitic capacitance from affecting the compensation transistor T3 and the first connecting electrode 1630. Referring to FIG. 14, in a plan view, the first connecting electrode 1630 overlaps the driving voltage line PL and the second branch portion BMLb of the lower metal layer BML (see FIG. 7) having the same constant voltage level (e.g., the driving voltage ELVDD level), thereby more effectively preventing the occurrence of the parasitic capacitance.

[0201] The first, second, and third data lines DL1, DL2, and DL3 may be electrically connected to the data write transistors T2 (see FIG. 9) of the first, second, and third pixel circuits PC1, PC2, and PC3, respectively. The first, second, and third data lines DL1, DL2, and DL3 may transmit a data signal Dm (see FIG. 3) to the first, second, and third pixel circuits PC1, PC2, and PC3, respectively.

[0202] The first data line DL1 may be electrically connected to the third connecting electrode 1650 (see FIG. 13) corresponding to the first pixel circuit PC1 through the fifteenth contact hole CNT15. ​​Similarly, the second data line DL2 may be electrically connected to the third connecting electrode 1650 corresponding to the second pixel circuit PC2 through the fifteenth contact hole CNT15, and the third data line DL3 may be electrically connected to the third connecting electrode 1650 corresponding to the third pixel circuit PC3 through the fifteenth contact hole CNT15. ​​The third connecting electrode 1650 corresponding to each of the first through third pixel circuits PC1, PC2, and PC3 is electrically connected to the first silicon semiconductor pattern 1110 (see FIG. 8) of the corresponding pixel circuit, and may provide a data signal Dm (see FIG. 3) to the data write transistor T2 formed along the first silicon semiconductor pattern 1110.

[0203] The shapes of the first data line DL1, the second data line DL2, and the third data line DL3 may be different from each other in a plan view. For example, the first data line DL1 and the second data line DL2 may pass through the region corresponding to the second pixel circuit PC2 while having different planar shapes from each other. For example, the first data line DL1 and the second data line DL2 may be asymmetric with respect to a virtual line extending in the second direction (e.g., the ±y direction) between the first data line DL1 and the second data line DL2. The planar shape of the third data line DL3 may be different from the planar shapes of the first data line DL1 and the second data line DL2.

[0204] The first data line DL1, the second data line DL2, and the third data line DL3 can intersect with the 2-1st initialization horizontal voltage line HVAL(R) and the 2-2nd initialization horizontal voltage line HVAL(GB) in plan view.

[0205] The vertical voltage line VCL may be disposed in the separation space IVA between the second pixel circuit PC2 and the third pixel circuit PC3. For example, the vertical voltage line VCL may be disposed between the second data line DL2 and the driving voltage line PL of the third pixel circuit PC3.

[0206] The vertical voltage line VCL may be electrically connected to voltage lines extending in a first direction (e.g., ±x direction). In one embodiment, Figure 14 illustrates that the vertical voltage line VCL is connected to the sixth connecting electrode 1680 through a contact hole CNT-VC1, the sixth connecting electrode 1680 is connected to the bridge pattern 1340 disposed immediately below through a contact hole CNT-VC2, and the bridge pattern 1340 is electrically connected to the first initialization horizontal voltage line HVIL through a contact hole CNT-VC3.

[0207] The second pixel connecting electrode 1710 may be electrically connected to the first pixel connecting electrode 1620 (see FIG. 13). For example, the 2-1 pixel connecting electrode 1710a may be electrically connected to the 1-1 pixel connecting electrode 1620a (see FIG. 13) through the 13-1 contact hole CNT13a. For example, the 2-2 pixel connecting electrode 1710b may be electrically connected to the 1-2 pixel connecting electrode 1620b (see FIG. 13) through the 13-2 contact hole CNT13b. For example, the 2-3 pixel connecting electrode 1710c may be electrically connected to the 1-3 pixel connecting electrode 1620c (see FIG. 13) through the 13-3 contact hole CNT13c.

[0208] A second organic insulating layer 123 (see FIG. 4) may be disposed on the structure described with reference to FIG. 14. Then, a pixel electrode as shown in FIG. 15 may be disposed on the second organic insulating layer 123 (see FIG. 4).

[0209] 15, a first pixel electrode 210a electrically connected to the first pixel circuit PC1, a second pixel electrode 210b electrically connected to the second pixel circuit PC2, and a third pixel electrode 210c electrically connected to the third pixel circuit PC3 may be spaced apart from one another. In one embodiment, the first pixel electrodes 210a and the second pixel electrodes 210b may be arranged alternately in the same column along a second direction (e.g., the y direction). The third pixel electrode 210c may be arranged in a column adjacent to the column in which the first pixel electrodes 210a and the second pixel electrodes 210b are arranged.

[0210] The pixel electrodes may be electrically connected to the first, second, and third pixel circuits PC1, PC2, and PC3, respectively, via the second pixel connecting electrode 1710 (see FIG. 14) and the first pixel connecting electrode 1620 (see FIG. 13). The first pixel electrode 210a may be connected to the 2-1 pixel connecting electrode 1710a (see FIG. 14) via the 16-1 contact hole CNT16a, and the 2-1 pixel connecting electrode 1710a may be electrically connected to the 1-1 pixel connecting electrode 1620a (see FIG. 13) via the 13-1 contact hole CNT13a (see FIG. 14). The second pixel electrode 210b may be electrically connected to the 2-2 pixel connecting electrode 1710b (see FIG. 14) through the 16-2 contact hole CNT16b, and the 2-2 pixel connecting electrode 1710b may be electrically connected to the 1-2 pixel connecting electrode 1620b (see FIG. 13) through the 13-2 contact hole CNT13b (see FIG. 14). The third pixel electrode 210c may be electrically connected to the 2-3 pixel connecting electrode 1710c (see FIG. 14) through the 16-3 contact hole CNT16c, and the 2-3 pixel connecting electrode 1710c may be electrically connected to the 1-3 pixel connecting electrode 1620c (see FIG. 13) through the 13-3 contact hole CNT13c (see FIG. 14).

[0211] FIG. 16 is a plan view schematically showing a second initialization horizontal voltage line passing through the first to third pixel circuits of a display device according to one embodiment of the present invention, and FIG. 17 is a cross-sectional view along lines A-A' and B-B' in FIG. 16.

[0212] 16, the 2-1st initialization horizontal voltage line HVAL(R) and the 2-2nd initialization horizontal voltage line HVAL(GB) may extend along a first direction (e.g., the ±x direction) while overlapping each other. For example, as shown in FIGS. 16 and 17, the 2-1st initialization horizontal voltage line HVAL(R) may be disposed on the 2-2nd initialization horizontal voltage line HVAL(GB) and overlap the 2-2nd initialization horizontal voltage line HVAL(GB). Insulating layers, for example, a second gate insulating layer 113, a first interlayer insulating layer 114, and a third gate insulating layer 115, may be interposed between the 2-1st initialization horizontal voltage line HVAL(R) and the 2-2nd initialization horizontal voltage line HVAL(GB).

[0213] The 2-1st initialization horizontal voltage line HVAL(R) and the 2-2nd initialization horizontal voltage line HVAL(GB) may be electrically connected to the second initialization transistors T7 of different pixel circuits. In one embodiment, the 2-1st initialization horizontal voltage line HVAL(R) may be electrically connected to the second initialization transistor T7 of the first pixel circuit PC1, and the 2-2nd initialization horizontal voltage line HVAL(GB) may be electrically connected to the second initialization transistors T7 of the second and third pixel circuits PC2 and PC3.

[0214] 16 and 17, the 2-1st initialization horizontal voltage line HVAL(R) may be electrically connected to the second initialization transistor T7 corresponding to the first pixel circuit PC1. The 2-1st initialization horizontal voltage line HVAL(R) may include a protruding portion RP protruding in a second direction (e.g., the ±y direction). The fifth connecting electrode 1670 may have an isolated shape in a plan view and may overlap the protruding portion RP of the 2-1st initialization horizontal voltage line HVAL(R) and the second initialization semiconductor layer A7.

[0215] The fifth connecting electrode 1670 may be electrically connected to the second initialization semiconductor layer A7 of the second initialization transistor T7 through a 7-1 contact hole CNT7a that penetrates the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116, and may be electrically connected to the protruding portion RP of the 2-1 initialization horizontal voltage line HVAL(R) through a 7-2 contact hole CNT7b that penetrates the second interlayer insulating layer 116.

[0216] 16 and 17, the 2-2 initialization horizontal voltage line HVAL(GB) may be electrically connected to the second initialization transistor T7 corresponding to each of the second pixel circuit PC2 and the third pixel circuit PC3. The 2-2 initialization horizontal voltage line HVAL(GB) may include a protruding portion RP' protruding in a second direction (e.g., the ±y direction). The fifth connecting electrode 1670 corresponding to each of the second pixel circuit PC2 and the third pixel circuit PC3 may have an isolated shape in a plan view and may overlap the protruding portion RP' of the 2-2 initialization horizontal voltage line HVAL(GB) and the second initialization semiconductor layer A7.

[0217] The fifth connecting electrode 1670 may be electrically connected to the second initialization semiconductor layer A7 of the second initialization transistor T7 corresponding to the second pixel circuit PC2 through a 7-1 contact hole CNT7a that penetrates the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116. The fifth connecting electrode 1670 may be electrically connected to the protruding portion RP′ of the 2-2 initialization horizontal voltage line HVAL(GB) through a 7-2 contact hole CNT7b that penetrates the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116.

[0218] 17 illustrates that the second initialization transistor T7 corresponding to the second pixel circuit PC2 is electrically connected to the 2-2 initialization horizontal voltage line HVAL(GB) through the fifth connecting electrode 1670, but the present invention is not limited thereto. The electrical connection structure between the 2-2 initialization horizontal voltage line HVAL(GB) and the second initialization transistor T7 corresponding to the third pixel circuit PC3 may have the same structure as the structure shown by the BB' line in FIG.

[0219] According to an embodiment of the present invention, one of the first to third pixel circuits PC1, PC2, and PC3 is connected to a second initialization horizontal voltage line different from the other one (or the rest), thereby effectively implementing a black image of the first to third LEDs having different light-emitting characteristics and improving power consumption.

[0220] In some embodiments, the 2-1 initialization voltage Vaint(R) provided through the 2-1 initialization horizontal voltage line HVAL(R) and the 2-2 initialization voltage Vaint(GB) provided through the 2-2 initialization horizontal voltage line HVAL(GB) are higher than the voltage level of the common voltage ELVSS (FIG. 3), but the difference between the 2-1 initialization voltage Vaint(R) and the common voltage ELVSS (FIG. 3) is about +1.2 V to about +1.8 V. In some embodiments, the 2-1 initialization voltage Vaint(R) provided through the 2-1 initialization horizontal voltage line HVAL(R) may be higher than the 2-2 initialization voltage Vaint(GB) provided through the 2-2 initialization horizontal voltage line HVAL(GB). In yet another embodiment, the 2-1 initialization voltage Vaint(R) provided through the 2-1 initialization horizontal voltage line HVAL(R) and the 2-2 initialization voltage Vaint(GB) provided through the 2-2 initialization horizontal voltage line HVAL(GB) may be the same. In yet another embodiment, the 2-1 initialization voltage Vaint(R) provided through the 2-1 initialization horizontal voltage line HVAL(R) may be lower than the 2-2 initialization voltage Vaint(GB) provided through the 2-2 initialization horizontal voltage line HVAL(GB).

[0221] FIG. 18 is a plan view schematically showing an initialization horizontal voltage line passing through the first to third pixel circuits of a display device according to one embodiment of the present invention, and FIG. 19 is a cross-sectional view taken along line CC' in FIG.

[0222] In the display device described with reference to FIGS. 6 to 17, it has been described that any one of the first to third pixel circuits PC1, PC2, and PC3 is electrically connected to the 2-1 initialization horizontal voltage line HVAL(R), and the remaining pixel circuits are electrically connected to the 2-2 initialization horizontal voltage line HVAL(GB), but the present invention is not limited thereto.

[0223] As another embodiment, referring to FIG. 18, the 2-1st initialization horizontal voltage line HVAL(R), the 2-2nd initialization horizontal voltage line HVAL(G), and the 2-3rd initialization horizontal voltage line HVAL(B) may extend along a first direction (e.g., x-direction) while overlapping each other.

[0224] 19, the 2-1st initialization horizontal voltage line HVAL(R) may be disposed on the 2-2nd initialization horizontal voltage line HVAL(G), which may be disposed on the 2-3rd initialization horizontal voltage line HVAL(B). In some embodiments, a first interlayer insulating layer 114 and a third gate insulating layer 115 may be interposed between the 2-1st initialization horizontal voltage line HVAL(R) and the 2-2nd initialization horizontal voltage line HVAL(G). A second gate insulating layer 113 may be interposed between the 2-2nd initialization horizontal voltage line HVAL(G) and the 2-3rd initialization horizontal voltage line HVAL(B).

[0225] The 2-1st initialization horizontal voltage line HVAL(R), the 2-2nd initialization horizontal voltage line HVAL(G), and the 2-3rd initialization horizontal voltage line HVAL(B) may be electrically connected to second initialization transistors T7 of different pixel circuits.

[0226] 18, the 2-1st initialization horizontal voltage line HVAL(R) may be electrically connected to the second initialization transistor T7 corresponding to the first pixel circuit PC1. The 2-1st initialization horizontal voltage line HVAL(R) may include a protruding portion RP protruding in a second direction (e.g., ±y direction). The fifth connecting electrode 1670 corresponding to the first pixel circuit PC1 may have an isolated shape in a plan view and may overlap the protruding portion RP of the 2-1st initialization horizontal voltage line HVAL(R) and the second initialization semiconductor layer A7 of the second initialization transistor T7 corresponding to the first pixel circuit PC1. The fifth connecting electrode 1670 corresponding to the first pixel circuit PC1 may be connected to the protruding portion RP of the 2-1st initialization horizontal voltage line HVAL(R) and the second initialization semiconductor layer A7 of the second initialization transistor T7 via the 7-2nd contact hole CNT7b and the 7-1st contact hole CNT7a, respectively.

[0227] The 2-2 initialization horizontal voltage line HVAL(G) may be electrically connected to the second initialization transistor T7 of the second pixel circuit PC2. The 2-2 initialization horizontal voltage line HVAL(G) may include a protruding portion RP' protruding along a second direction (e.g., the ±y direction). The fifth connecting electrode 1670 corresponding to the second pixel circuit PC2 may have an isolated shape in a plan view and overlap the protruding portion RP' of the 2-2 initialization horizontal voltage line HVAL(G) and the second initialization semiconductor layer of the second initialization transistor T7 corresponding to the second pixel circuit PC2. The fifth connecting electrode 1670 corresponding to the second pixel circuit PC2 may be connected to the protruding portion RP' of the 2-2 initialization horizontal voltage line HVAL(G) and the second initialization semiconductor layer of the second initialization transistor T7 via the 7-2 contact hole CNT7b and the 7-1 contact hole CNT7a, respectively.

[0228] The second-third initialization horizontal voltage line HVAL(B) may be electrically connected to the second initialization transistor T7 of the third pixel circuit PC3. The second-third initialization horizontal voltage line HVAL(B) may include a protruding portion RP" protruding along a second direction (e.g., the ±y direction). The fifth connecting electrode 1670 corresponding to the third pixel circuit PC3 may have an isolated shape in a plan view and overlap the protruding portion RP" of the second-third initialization horizontal voltage line HVAL(B) and the second initialization semiconductor layer of the second initialization transistor T7 corresponding to the third pixel circuit PC3. The fifth connecting electrode 1670 corresponding to the third pixel circuit PC3 may be connected to the protruding portion RP" of the second-third initialization horizontal voltage line HVAL(B) and the second initialization semiconductor layer of the second initialization transistor T7 via the 7-2 contact hole CNT7b and the 7-1 contact hole CNT7a, respectively.

[0229] FIG. 20 is a plan view illustrating an electrical connection between a second initialization horizontal voltage line and a second initialization vertical voltage line of a display device according to an embodiment of the present invention.

[0230] Referring to FIG. 20, the 2-1st initialization horizontal voltage line HVAL(R) passes through the first to third pixel circuits PC1, PC2, and PC3 arranged in the (i)th row, and may be electrically connected to the 2-1st initialization vertical voltage line VVAL(R) passing through the separation space IVA between the second pixel circuit PC2 and the third pixel circuit PC3.

[0231] The 2-1st initialization horizontal voltage line HVAL(R) may include a bridge portion HVAL-B extending toward the (i+1)th row in a second direction (e.g., ±y direction). The bridge portion HVAL-B may be integrally formed with the 2-1st initialization horizontal voltage line HVAL(R) using the same material. The bridge portion HVAL-B may be located in a space IVA between the second pixel circuit PC2 and the third pixel circuit PC3 arranged in the (i+1)th row. Although FIG. 20 illustrates that the bridge portion HVAL-B is integral with the 2-1st initialization horizontal voltage line HVAL(R), the present invention is not limited thereto. In another embodiment, the bridge portion HVAL-B may be located on a different layer from the 2-1st initialization horizontal voltage line HVAL(R) and connected to the 2-1st initialization horizontal voltage line HVAL(R) through a contact hole penetrating an insulating layer interposed between the 2-1st initialization horizontal voltage line HVAL(R) and the bridge portion HVAL-B. Through such a configuration, the distance between the signal lines, such as the first initialization control line GIL, the scan line GWL, and / or the compensation scan line GCL, that intersect with the bridge portion HVAL-B in a vertical direction (e.g., in a direction away from the top surface of the substrate along the +z direction) can be increased, thereby minimizing or preventing coupling between the first initialization control line GIL, the scan line GWL, and / or the compensation scan line GCL and the bridge portion HVAL-B.

[0232] The 2-1st initialization vertical voltage line VVAL(R) may be electrically connected to the bridge portion HVAL-B of the 2-1st initialization horizontal voltage line HVAL(R). For example, the 2-1st initialization vertical voltage line VVAL(R) and the bridge portion HVAL-B of the 2-1st initialization horizontal voltage line HVAL(R) may be electrically connected to each other through a connecting electrode 1680' overlapping a portion of the bridge portion HVAL-B and a portion of the 2-1st initialization vertical voltage line VVAL(R) in the separation space IVA. For example, the connecting electrode 1680' may be connected to the bridge portion HVAL-B through a contact hole CNT-VA1, and the 2-1st initialization vertical voltage line VVAL(R) may be connected to the connecting electrode 1680' through a contact hole CNT-VA2.

[0233] 20 illustrates an electrical connection between the 2-1st initialization horizontal voltage line HVAL(R) and the 2-1st initialization vertical voltage line VVAL(R), but the present invention is not limited thereto. The 2-2nd initialization horizontal voltage line HVAL(GB) described with reference to FIG. 16 also includes a bridge portion extending toward the (i+1)th row, and the bridge portion of the 2-2nd initialization horizontal voltage line HVAL(GB) may be electrically connected to the 2-2nd initialization vertical voltage line (HVAL(GB), FIG. 5) passing through the isolation space IVA.

[0234] While the present invention has been described above based on one embodiment shown in the drawings, this is merely an example, and those skilled in the art will understand that various modifications and variations of the embodiment are possible. Therefore, the true technical scope of protection of the present invention should be determined by the technical spirit of the claims. [Explanation of symbols]

[0235] GWL scan line GCL Compensated Scan Line GIL First initialization control line GBL Second initialization control line EML Light Emission Control Line HVIL First initialization horizontal voltage line VVIL First initialization vertical voltage line HVAL(R) 2nd-1st Initialization Horizontal Voltage Line VVAL(R) 2nd-1st initialization vertical voltage line VVAL(GB) 2nd-2nd initialization vertical voltage line HVAL(GB) 2nd-2nd initialization horizontal voltage line 1310 Third conductive pattern (horizontal drive voltage line)

Claims

1. a first pixel circuit and a second pixel circuit, each including a driving transistor and a first capacitor disposed on a substrate, adjacent to each other along a first direction; a first light emitting diode electrically connected to the first pixel circuit; a second light emitting diode electrically connected to the second pixel circuit; a first horizontal voltage line extending along the first direction and electrically connected to a semiconductor layer of a first transistor electrically connected to the driving transistor of the first pixel circuit and the pixel electrode of the first light emitting diode; a second horizontal voltage line extending along the first direction and electrically connected to a semiconductor layer of a second transistor electrically connected to the driving transistor of the second pixel circuit and the pixel electrode of the second light emitting diode; a first gate line extending along the first direction and electrically connected to a gate electrode of the first transistor of the first pixel circuit and a gate electrode of the second transistor of the second pixel circuit, The display device, wherein the first horizontal voltage line and the second horizontal voltage line are arranged on different layers but overlap each other in a plan view.

2. The display device according to claim 1 , wherein the second horizontal voltage line is arranged on the same layer as the first gate line.

3. a lower metal layer interposed between an upper surface of the substrate and the driving transistor of the first pixel circuit and between the upper surface of the substrate and the driving transistor of the second pixel circuit; The lower metal layer is a first main portion overlapping a channel region of the driving transistor of the first pixel circuit; a second main portion overlapping a channel region of the driving transistor of the second pixel circuit; a first branch portion extending in the first direction to connect the first main portion and the second main portion to each other; The display device of claim 1 , further comprising: second branch portions connected to the first main portion and the second main portion, respectively, and extending in a second direction.

4. The second branch portion is The display device according to claim 3 , wherein the first horizontal voltage line and the second horizontal voltage line intersect in a plan view.

5. a horizontal driving voltage line overlapping the driving transistor of the first pixel circuit and the driving transistor of the second pixel circuit and extending along the first direction; The display device of claim 3 , wherein the horizontal driving voltage line overlaps with the first branch portion.

6. Each of the first pixel circuit and the second pixel circuit is a compensation transistor including a compensation semiconductor layer and a compensation gate electrode, the compensation transistor being electrically connected to the driving transistor; The display device according to claim 3 , wherein the first horizontal voltage line is arranged on the same layer as the compensation gate electrode of the compensation transistor.

7. a first connecting electrode electrically connecting the compensation semiconductor layer of the compensation transistor of the first pixel circuit to a driving gate electrode of the driving transistor of the first pixel circuit; The display device of claim 6 , wherein the first connecting electrode overlaps one of the second branch portions of the lower metal layer.

8. The display device of claim 7 , further comprising a driving voltage line extending along a second direction intersecting the first direction so as to pass through the first pixel circuit.

9. The driving voltage line is The display device of claim 8 , wherein the first connecting electrode overlaps with the one of the second branch portions of the lower metal layer corresponding to the first pixel circuit.

10. The driving voltage line is The display device according to claim 8 , wherein the compensation gate electrode overlaps the compensation gate electrode of the first pixel circuit in a plan view.

11. The first pixel circuit a first initialization transistor including a first initialization semiconductor layer integrally connected with the compensation semiconductor layer of the compensation transistor and a first initialization gate electrode; The display device according to claim 8 , wherein the driving voltage line overlaps the first initialization gate electrode.

12. a third pixel circuit disposed on the opposite side of the first pixel circuit with the second pixel circuit interposed therebetween; 2. The display device of claim 1, wherein a first separation distance between the drive transistor of the second pixel circuit and the drive transistor of the third pixel circuit is greater than a second separation distance between the drive transistor of the second pixel circuit and the drive transistor of the first pixel circuit.

13. The planar shape of the channel region of the driving transistor of the third pixel circuit is The display device according to claim 12 , wherein the planar shape of the channel region of the driving transistor of the second pixel circuit is different from the planar shape of the channel region of the driving transistor of the first pixel circuit.

14. The third pixel circuit a third transistor electrically connected to the driving transistor of the third pixel circuit and a pixel electrode of a third light emitting diode electrically connected to the third pixel circuit; The display device of claim 12 , wherein the second horizontal voltage line is electrically connected to the third transistor of the third pixel circuit.

15. The third pixel circuit a third transistor electrically connected to the driving transistor of the third pixel circuit and a pixel electrode of a third light emitting diode electrically connected to the third pixel circuit; a third horizontal voltage line electrically connected to the third transistor of the third pixel circuit, The display device of claim 12 , wherein the first horizontal voltage line and the second horizontal voltage line are arranged on a different layer from each other but overlap with the first horizontal voltage line and the second horizontal voltage line.

16. a first vertical voltage line extending along a second direction intersecting the first direction and passing through a separation space between the second pixel circuit and the third pixel circuit, the separation space having the first separation distance; The display device of claim 12, wherein the first horizontal voltage line is electrically connected to the first vertical voltage line.

17. the first horizontal voltage line further includes a bridge portion protruding from the first horizontal voltage line, The display device of claim 16 , wherein the bridge portion is connected to the first vertical voltage line.

18. a connecting electrode disposed on the bridge portion and below the first vertical voltage line; The display device of claim 17 , wherein the bridge portion and the first vertical voltage line are electrically connected to each other through the connecting electrode.

19. The display device of claim 16, wherein the first horizontal voltage line is connected to the first vertical voltage line via a bridge portion disposed on a layer different from that on which the first horizontal voltage line is disposed.

20. Each of the first pixel circuit and the second pixel circuit is the data write transistor is electrically connected to the driving transistor and the first capacitor; 2. The display device of claim 1, wherein a first data line electrically connected to the data writing transistor of the first pixel circuit and a second data line electrically connected to the data writing transistor of the second pixel circuit have different shapes in a plan view.

21. a first pixel circuit and a second pixel circuit, each including a driving transistor and a first capacitor, disposed on a substrate and adjacent to each other along a first direction; a first light emitting diode and a second light emitting diode electrically connected to the first pixel circuit and the second pixel circuit, respectively; a first horizontal voltage line extending along the first direction and electrically connected to a semiconductor layer of a first transistor electrically connected to the driving transistor of the first pixel circuit and the pixel electrode of the first light emitting diode; a second horizontal voltage line extending along the first direction and electrically connected to a semiconductor layer of a second transistor electrically connected to the driving transistor of the second pixel circuit and the pixel electrode of the second light emitting diode; a first gate line extending along the first direction and electrically connected to a gate electrode of the first transistor of the first pixel circuit and a gate electrode of the second transistor of the second pixel circuit, the first horizontal voltage line and the second horizontal voltage line are arranged on different layers but overlap each other in a plan view.

22. a lower metal layer interposed between an upper surface of the substrate and the driving transistor of the first pixel circuit and between the upper surface of the substrate and the driving transistor of the second pixel circuit; The lower metal layer is a first main portion overlapping a channel region of the driving transistor of the first pixel circuit; a second main portion overlapping a channel region of the driving transistor of the second pixel circuit; a first branch portion extending in the first direction to connect the first main portion and the second main portion to each other; 22. The electronic device of claim 21, further comprising: second branch portions connected to the first main portion and the second main portion, respectively, and extending in a second direction.

23. The electronic device according to claim 22 , wherein the second branch portion intersects with the first horizontal voltage line and the second horizontal voltage line in a plan view.

24. a horizontal driving voltage line overlapping the driving transistor of the first pixel circuit and the driving transistor of the second pixel circuit and extending along the first direction; The electronic device of claim 22 , wherein the horizontal driving voltage line overlaps with the first branch portion.

25. a third pixel circuit disposed on the opposite side of the first pixel circuit with the second pixel circuit interposed therebetween; a first separation distance between the drive transistor of the second pixel circuit and the drive transistor of the third pixel circuit is greater than a second separation distance between the drive transistor of the second pixel circuit and the drive transistor of the first pixel circuit; The planar shape of the channel region of the driving transistor of the third pixel circuit is The electronic device according to claim 21 , wherein a planar shape of the channel region of the driving transistor of the second pixel circuit is different from a planar shape of the channel region of the driving transistor of the first pixel circuit.

26. a first vertical voltage line extending along a second direction intersecting the first direction and passing through a separation space between the second pixel circuit and the third pixel circuit, the separation space having the first separation distance; The electronic device of claim 25 , wherein the first horizontal voltage line is electrically connected to the first vertical voltage line.

27. the first horizontal voltage line further includes a bridge portion protruding from the first horizontal voltage line, The electronic device of claim 26 , wherein the bridge portion is connected to the first vertical voltage line.

28. a connecting electrode disposed on the bridge portion and below the first vertical voltage line; The electronic device of claim 27 , wherein the bridge portion and the first vertical voltage line are electrically connected to each other through the connecting electrode.

29. 27. The electronic device of claim 26, wherein the first horizontal voltage line is connected to the first vertical voltage line via a bridge portion disposed on a layer different from that of the first horizontal voltage line.

30. The electronic device includes:

22. The electronic device of claim 21, which is a mobile phone, a laptop, a tablet personal computer (PC), a smartphone, a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player (PMP), a navigation system, an Ultra Mobile PC (UMPC), a television, a monitor, a smart watch, a watch phone, a glasses-type display, a head-mounted display (HMD), or an automotive display device.

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