Display device

Abstract

To provide a display device.SOLUTION: A display device includes: a first pixel circuit and a second pixel circuit arranged on a substrate and adjacent to each other in a first direction; and a first conductive layer arranged on the first and second pixel circuits and including a first data line connected to the first pixel circuit, a second data line connected to the second pixel circuit, a first voltage line superimposed on the first pixel circuit, and a second voltage line superimposed on the second pixel circuit. Each of the first and second pixel circuits includes: a first transistor including a first semiconductor pattern and a first gate electrode on the first semiconductor pattern; a second transistor including a second semiconductor pattern arranged on the first semiconductor pattern and a second gate electrode on the second semiconductor pattern; and a connection electrode for connecting one terminal of the first transistor and one terminal of the second transistor. In a plan view, the connection electrode of the second pixel circuit is arranged between the first voltage line and the first data line.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] Recently, display devices have become lighter and thinner, and their applications have become more diverse. Such display devices may include a plurality of pixels. Each pixel may include a light emitting diode (LED) and a pixel circuit for controlling the brightness of the LED. The pixel circuit may include a transistor and a capacitor connected to wiring such as a data line, a gate line, and a voltage line.

[0003] As display devices are widely used and the number of functions that can be applied to or associated with display devices increases, various types of display devices are being designed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Korean Patent Publication No. 10-2023-0168257 (KR2023-0168257A) [Patent Document 2] Korean Patent Publication No. 10-2023-0166164 (KR2023-0166164A) Summary of the Invention [Problem to be solved by the invention]

[0005] As display devices have become higher resolution, the distance between a data line and an adjacent driving transistor has decreased, and the parasitic capacitance between the data line and the driving transistor has increased. As a result, when an electrical signal is applied to the data line, the brightness of adjacent pixels changes, causing unevenness in the image displayed by the display device.

[0006] The present invention aims to solve various problems, including those mentioned above, and aims to provide a display device that displays high-quality images, but these problems are merely examples and are not intended to limit the scope of the present invention. [Means for solving the problem]

[0007] According to one aspect of the present invention, there is provided a display device including: a first pixel circuit and a second pixel circuit arranged on a substrate and adjacent to each other in a first direction; and a first conductive layer arranged above the first pixel circuit and the second pixel circuit, the first conductive layer including a first data line connected to the first pixel circuit, a second data line connected to the second pixel circuit, a first voltage line overlapping the first pixel circuit, and a second voltage line overlapping the second pixel circuit, wherein each of the first pixel circuit and the second pixel circuit includes: a first transistor including a first semiconductor pattern and a first gate electrode on the first semiconductor pattern; a second semiconductor pattern arranged on the first semiconductor pattern and a second transistor including a second gate electrode on the second semiconductor pattern; and a connecting electrode connecting one terminal of the first transistor and one terminal of the second transistor, wherein, in a plan view, the connecting electrode of the second pixel circuit is arranged between the first voltage line and the first data line.

[0008] In one embodiment, the pixel may further include a second conductive layer disposed on the first conductive layer, the second conductive layer including a first pixel electrode connected to the first pixel circuit and a second pixel electrode connected to the second pixel circuit, and a pixel defining film disposed on the second conductive layer, the pixel defining film defining a first pixel opening overlapping the first pixel electrode and a second pixel opening overlapping the second pixel electrode, wherein the first data line may be disposed spaced apart from the first pixel opening and the second pixel opening in a planar view.

[0009] In an embodiment, the first pixel opening and the second pixel opening may overlap the first voltage line.

[0010] In an exemplary embodiment, a portion of the first voltage line overlapping the first pixel opening may be symmetrical with respect to an imaginary line passing through a center of the first pixel opening.

[0011] In one embodiment, the pixel may further include a third pixel circuit disposed on the substrate and adjacent to the second pixel circuit in the first direction, and the first conductive layer may further include a third data line connected to the third pixel circuit and a third voltage line overlapping the third pixel circuit.

[0012] In one embodiment, the second conductive layer further includes a third pixel electrode connected to the third pixel circuit, the pixel defining film further defines a third pixel opening overlapping the third pixel electrode, and the second data line may overlap the third pixel opening.

[0013] In one embodiment, the first conductive layer further includes a first voltage transmission wiring extending in a second direction intersecting the first direction and overlapping the third pixel opening, and a portion of the second data line and a portion of the first voltage transmission wiring overlapping the third pixel opening may be symmetrical with respect to a virtual straight line passing through the center of the third pixel opening.

[0014] In one embodiment, each of the first pixel circuit and the second pixel circuit further includes a conductive pattern disposed on the first gate electrode, and the conductive pattern of the second pixel circuit may extend to an area where the first data line and a drain region of the first transistor of the second pixel circuit overlap.

[0015] In an embodiment, the display device may further include a third conductive layer disposed on the conductive pattern and including the first voltage line, the second voltage line, and a second voltage transmission wiring connected to the conductive pattern.

[0016] In an embodiment, the first semiconductor pattern may include a silicon-based semiconductor material, and the second semiconductor pattern may include an oxide-based semiconductor material.

[0017] According to another aspect of the present invention, a semiconductor device may include: a first semiconductor layer disposed on a substrate and including a first semiconductor pattern and a second semiconductor pattern adjacent to each other in a first direction; a first conductive layer disposed on the first semiconductor layer; a second conductive layer disposed on the first conductive layer and including a conductive pattern; a second semiconductor layer disposed on the second conductive layer and including a third semiconductor pattern and a fourth semiconductor pattern; a third conductive layer disposed on the second semiconductor layer; a fourth conductive layer disposed on the third conductive layer and including a first connecting electrode connecting the first semiconductor pattern and the third semiconductor pattern and a second connecting electrode connecting the second semiconductor pattern and the fourth semiconductor pattern; and a fifth conductive layer disposed on the fourth conductive layer and including a first voltage line, a first data line, a second voltage line, and a second data line arranged sequentially along the first direction, wherein the first data line is connected to the first semiconductor pattern and the second data line is connected to the second semiconductor pattern, and the second connecting electrode is arranged between the first voltage line and the first data line in a plan view.

[0018] In one embodiment, the display device further includes a sixth conductive layer disposed on the fifth conductive layer and including a first pixel electrode and a second pixel electrode overlapping the first voltage line, and a pixel defining film disposed on the sixth conductive layer and defining a first pixel opening overlapping the first pixel electrode and a second pixel opening overlapping the second pixel electrode, and in a planar view, the first data line may be disposed spaced apart from the first pixel opening and the second pixel opening.

[0019] In an embodiment, a portion of the first voltage line overlapping the first pixel opening may be symmetrical with respect to an imaginary line passing through a center of the first pixel opening.

[0020] In an embodiment, a portion of the first voltage line overlapping the second pixel opening may be symmetrical with respect to an imaginary line passing through a center of the first pixel opening.

[0021] In one embodiment, the fifth conductive layer may further include a first voltage transmission line, a third voltage line, and a third data line arranged sequentially from the second data line along the first direction, and the sixth conductive layer may further include a third pixel electrode overlapping the second voltage line, the second data line, the first voltage transmission line, and the third voltage line.

[0022] In one embodiment, the pixel defining layer may further define a third pixel opening overlapping the third pixel electrode, and the second data line and the first voltage transmission line may overlap the third pixel opening.

[0023] In an exemplary embodiment, a portion of the second data line and a portion of the first voltage transmission line overlapping the third pixel opening may be symmetrical with respect to an imaginary line passing through the center of the third pixel opening.

[0024] In an embodiment, the conductive pattern may extend to an area where the first data line and the second semiconductor pattern overlap.

[0025] In an embodiment, the fourth conductive layer may further include a second voltage transmission wiring connected to the first voltage line, the second voltage line, and the conductive pattern.

[0026] In an embodiment, the first semiconductor pattern may include a silicon-based semiconductor material, and the second semiconductor pattern may include an oxide-based semiconductor material.

[0027] Other aspects, features, and advantages beyond those described above will become apparent from the following drawings, claims, and detailed description of the invention. [Effects of the Invention]

[0028] According to an embodiment of the present invention, a display device that displays high-quality images by reducing the parasitic capacitance between a data line and a driving transistor can be realized, although it should be understood that the scope of the present invention is not limited by such an effect. [Brief explanation of the drawings]

[0029] [Figure 1A] 1 is a plan view schematically illustrating a display device according to an embodiment of the present invention; [Figure 1B] 1 is a plan view schematically illustrating a display device according to an embodiment of the present invention; [Figure 2] 1 is a diagram schematically illustrating a display device according to an embodiment of the present invention; [Figure 3] 1 is an equivalent circuit diagram of one pixel included in a display device according to an embodiment of the present invention; [Figure 4] 1 is a schematic layout diagram of a part of a display device according to an embodiment of the present invention; [Figure 5] 1 is a layout diagram showing a schematic layer-by-layer view of a portion of a display device according to an embodiment of the present invention; [Figure 6] 1 is a layout diagram showing a schematic layer-by-layer view of a portion of a display device according to an embodiment of the present invention; [Figure 7] 1 is a layout diagram showing a schematic layer-by-layer view of a portion of a display device according to an embodiment of the present invention; [Figure 8] 1 is a layout diagram showing a schematic layer-by-layer view of a portion of a display device according to an embodiment of the present invention; [Figure 9] 1 is a layout diagram showing a schematic layer-by-layer view of a portion of a display device according to an embodiment of the present invention; [Figure 10] 1 is a layout diagram showing a schematic layer-by-layer view of a portion of a display device according to an embodiment of the present invention; [Figure 11] 1 is a layout diagram showing a schematic layer-by-layer view of a portion of a display device according to an embodiment of the present invention; [Figure 12] 1 is a layout diagram showing a schematic layer-by-layer view of a portion of a display device according to an embodiment of the present invention; [Figure 13]1 is a layout diagram showing a schematic layer-by-layer view of a portion of a display device according to an embodiment of the present invention; [Figure 14] 1 is a layout diagram showing a schematic layer-by-layer view of a portion of a display device according to an embodiment of the present invention; [Figure 15] 1 is a layout diagram showing a schematic layer-by-layer view of a portion of a display device according to an embodiment of the present invention; [Figure 16] 1 is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention. [Figure 17] 1 is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention. [Figure 18A] 2 is a schematic layout diagram of pixel electrodes, voltage lines, and data lines of a display device according to an embodiment of the present invention; [Figure 18B] 1 is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0030] The present invention can be modified in various ways and can have various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. The advantages and features of the present invention, and methods for achieving them, will become clearer with reference to the embodiments described in detail below in conjunction with the drawings. However, the present invention is not limited to the embodiments described below, and can be embodied in various forms.

[0031] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, identical or corresponding components will be denoted by the same reference numerals, and duplicate descriptions thereof will be omitted.

[0032] In this specification, the terms "first", "second", etc. are not meant to be limiting but are used to distinguish one component from another.

[0033] In this specification, the singular expression includes the plural expression unless the context clearly indicates otherwise.

[0034] In this specification, the terms "comprise" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may also be added.

[0035] In this specification, when a part such as a film, region, or component is said to be on or above another part, this includes not only when it is directly on top of the other part, but also when another film, region, component, etc. is interposed between them.

[0036] As used herein, when a membrane, region, component, etc. is said to be connected, this includes cases where the membrane, region, component, etc. is directly connected, and / or cases where the membrane, region, component, etc. is indirectly connected by another membrane, region, component, etc. For example, as used herein, when a membrane, region, component, etc. is said to be electrically connected, this includes cases where the membrane, region, component, etc. is directly electrically connected, and / or cases where the membrane, region, component, etc. is indirectly electrically connected by another membrane, region, component, etc.,

[0037] In this specification, "A and / or B" refers to A, B, or A and B. And "at least one of A and B" refers to A, B, or A and B.

[0038] In this specification, the x-direction, y-direction, and z-direction are not limited to directions along the three axes of a Cartesian coordinate system, but may be interpreted in a broad sense to include such directions. For example, the x-direction, y-direction, and z-direction may be orthogonal to each other, but may also refer to different directions that are not orthogonal to each other.

[0039] In this specification, "planar view" means when the target portion is viewed from above (for example, when viewed from a direction perpendicular to the top surface of the substrate), and "cross-sectional view" means when the target portion is cut vertically and viewed from the side.

[0040] In this specification, when a first component "overlaps" a second component, it means that the first component is located above or below the second component, and at least a portion of the first component overlaps with the second component on a plane.

[0041] In the drawings, the size of components may be exaggerated or reduced for the sake of convenience. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for the sake of convenience, and the present invention is not necessarily limited to what is shown in the drawings.

[0042] 1A and 1B are plan views each schematically illustrating a display device according to an embodiment of the present invention.

[0043] 1A and 1B, the display device 10 may include a display area DA for displaying an image and a peripheral area PA outside the display area DA. The display device 10 may provide a predetermined image using light emitted from a plurality of pixels arranged in the display area DA. In a plan view, the display area DA may be rectangular. In other embodiments, the display area DA may be other polygonal shapes, circular shapes, oval shapes, irregular shapes, etc. The display area DA may have rounded corners.

[0044] In one embodiment, the display device 10 may have a display area DA whose length in a first direction (x direction) is longer than its length in a second direction (y direction) as shown in Fig. 1A. In another embodiment, the display device 10 may have a display area DA whose length in the first direction (x direction) is shorter than its length in the second direction (y direction) as shown in Fig. 1B.

[0045] The peripheral area PA is an area disposed around the display area DA and may surround at least a portion of the display area DA. In one embodiment, the peripheral area PA may be a type of non-display area where no pixels are disposed. Various wirings and circuits transmitting electrical signals to the display area DA, as well as pads to which printed circuit boards and driver IC chips are attached, may be located in the peripheral area PA.

[0046] The display device 10 according to an embodiment of the present invention is a device for displaying moving and still images, and may be used as a display screen for various products, such as portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs), as well as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices. The display device 10 according to an embodiment may also be used in wearable devices, such as smart watches, watch phones, eyeglass displays, and head-mounted displays (HMDs). The display device 10 according to an embodiment may also be used as a center information display (CID) disposed in an automobile instrument panel, a center fascia or dashboard of an automobile, a room mirror display replacing an automobile's side mirrors, or a display disposed behind the front seats for rear-seat entertainment.

[0047] FIG. 2 is a diagram schematically illustrating a display device according to an embodiment of the present invention.

[0048] Referring to FIG. 2, a display device 10 according to an embodiment may include a pixel unit 11, a gate driving circuit 13, a data driving circuit 15, a power supply circuit 17, and a controller 19.

[0049] The pixel unit 11 may be provided in a display area DA (see FIG. 1A) of the display device 10, and the gate drive circuit 13, the data drive circuit 15, the power supply circuit 17, and the controller 19 may be provided in a peripheral area (PA (see FIG. 1A)).

[0050] The pixel unit 11 may include a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels P connected thereto. Each pixel P refers to a sub-pixel. Each pixel P may include a pixel circuit and a display element connected to the pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. The display element may be an organic light-emitting diode.

[0051] In one embodiment, the pixel P may emit red, green, and blue light. In another embodiment, the pixel P may emit red, green, blue, and white light. The pixel circuit of each pixel P may be connected to at least one corresponding gate line among the plurality of gate lines GL and a corresponding data line among the plurality of data lines DL.

[0052] The data lines DL may be connected to pixels P whose pixel circuits are located in the same column. The data lines DL may transmit data signals to the connected pixels P in synchronization with respective gate signals. The gate lines GL may be connected to pixels P whose pixel circuits are located in the same row. The gate lines GL may transmit gate signals to the connected pixels P.

[0053] The gate driving circuit 13 may be connected to a plurality of gate lines GL. The gate driving circuit 13 may generate gate signals GW, GI, GC, GB, and EM in response to a control signal GCS from the controller 19 and sequentially supply the gate signals to each of the gate lines GL. Each of the gate lines GL may be connected to the gate of a transistor included in a pixel circuit. Each of the gate signals GW, GI, GC, GB, and EM may be a gate control signal that controls the turn-on and turn-off of a transistor connected to the corresponding gate line. Each of the gate signals GW, GI, GC, GB, and EM may be a square wave signal including an on-voltage at which the transistor is turned on and an off-voltage at which the transistor is turned off.

[0054] 2, one pixel P is illustrated as being connected to one gate line GL, but this is merely an example, and one pixel P may be connected to two or more gate lines, and the gate driving circuit 13 may supply two or more gate signals GW, GI, GC, GB, and EM to the gate lines, each of which has a different timing at which an on-voltage is applied. For example, the pixel P may be connected to first through fifth gate lines, and the gate driving circuit 13 may apply a first gate signal GW, a second gate signal GC, a third gate signal GI, a fourth gate signal GB, and a light emission control signal (fifth gate signal) EM to the first gate line, the second gate line, the third gate line, the fourth gate line, and the fifth gate line, respectively.

[0055] The data driving circuit 15 may be connected to a plurality of data lines DL. The data driving circuit 15 may convert input image data having grayscales input from the controller 19 into a data signal Dm in response to a control signal DCS from the controller 19, and provide the data signal Dm to the data lines DL.

[0056] The power supply circuit 17 may generate voltages required to drive the pixel P in response to a control signal PCS from the controller 19. The power supply circuit 17 may generate a first power supply voltage ELVDD and a second power supply voltage ELVSS and supply them to the pixel P. The first power supply voltage ELVDD may be a high-level voltage provided to a first electrode (pixel electrode or anode) of a display element included in the pixel P. The second power supply voltage ELVSS may be a low-level voltage provided to a second electrode (counter electrode or cathode) of a display element included in the pixel P. The power supply circuit 17 may generate a first initialization voltage Vint, a second initialization voltage Vaint, and a bias voltage Vobs and supply them to the pixel P.

[0057] In one embodiment, the power supply circuit 17 may supply second initialization voltages Vaint having different levels to the pixels P. For example, the power supply circuit 17 may supply a 2-1 initialization voltage through a 2-1 initialization voltage line to a first pixel emitting a first color, and a 2-2 initialization voltage through a 2-2 initialization voltage line to a second pixel emitting a second color different from the first color. In this case, the 2-1 initialization voltage and the 2-2 initialization voltage have different levels.

[0058] The controller 19 may generate control signals GCS, DCS, and PCS based on an externally input signal and supply the control signals GCS, DCS, and PCS to the gate drive circuit 13, the data drive circuit 15, and the power supply circuit 17. The control signal GCS output to the gate drive circuit 13 may include a gate start signal and a clock signal. The control signal DCS output to the data drive circuit 15 may include a source start signal and a clock signal.

[0059] A portion or all of the gate driving circuit 13 may be formed directly in the peripheral area PA (see FIG. 1A) of the substrate. The data driving circuit 15, the power supply circuit 17, and the controller 19 may be formed as separate integrated circuit chips or as a single integrated circuit chip and disposed on a flexible printed circuit board (PCB) electrically connected to pads disposed on one side of the substrate. In another embodiment, at least a portion of the data driving circuit 15, the power supply circuit 17, and the controller 19 may be disposed directly on the substrate using a chip-on-glass (COG) or chip-on-plastic (COP) method.

[0060] FIG. 3 is an equivalent circuit diagram of one pixel included in a display device according to an embodiment of the present invention.

[0061] 3, a pixel P may include an organic light emitting diode OLED as a display element and a pixel circuit PC electrically connected to the organic light emitting diode OLED. The pixel circuit PC may include first through eighth transistors T1 through T8 and a storage capacitor Cst. The first transistor T1 may be a driving transistor that outputs a driving current corresponding to a data signal Dm, and the second through eighth transistors T2 through T8 may be switching transistors that transmit signals.

[0062] The first terminal (first electrode) of each of the first to eighth transistors T1 to T8 may be a source or a drain, and the second terminal (second electrode) may be a terminal different from the first terminal. For example, if the first terminal is a drain, the second terminal may be a source.

[0063] A node to which the gate of the first transistor T1 is connected may be defined as a first node N1, a node to which the first terminal of the first transistor T1 is connected may be defined as a second node N2, and a node to which the second terminal of the first transistor T1 is connected may be defined as a third node N3.

[0064] The pixel circuit PC of each pixel P may be connected to a first gate line GWL transmitting a first gate signal GW, a second gate line GCL transmitting a second gate signal GC, a third gate line GIL transmitting a third gate signal GI, a fourth gate line GBL transmitting a fourth gate signal GB, an emission control line EML (fifth gate line) transmitting an emission control signal EM, a data line DL transmitting a data signal Dm, a driving voltage line PL transmitting a first power supply voltage ELVDD, a first initialization voltage line VL1 transmitting a first initialization voltage Vint, a second initialization voltage line VL2 transmitting a second initialization voltage Vaint, and a bias voltage line VL3 transmitting a bias voltage Vobs.

[0065] The first transistor T1 may include a gate (or gate electrode) connected to a first node N1, a first terminal connected to a second node N2, and a second terminal connected to a third node N3. The first terminal of the first transistor T1 may be connected to a driving voltage line PL via a fifth transistor T5, and the second terminal of the first transistor T1 may be connected to a pixel electrode (or anode) of the organic light emitting diode OLED via a sixth transistor T6. The first transistor T1 receives a data signal Dm through a switching operation of the second transistor T2 and controls the amount of driving current flowing to the pixel electrode of the organic light emitting diode OLED.

[0066] The second transistor T2 may be connected between the data line DL and the first transistor T1. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to a second node N2. The second transistor T2 is turned on by a first gate signal GW transmitted to the first gate line GWL to electrically connect the data line DL and the second node N2 and transmit a data signal Dm from the data line DL to the second node N2.

[0067] The third transistor T3 may be connected between the gate of the first transistor T1 and the second terminal of the first transistor T1. The third transistor T3 may include a gate connected to the second gate line GCL, a first terminal connected to the first node N1, and a second terminal connected to a third node N3. The third transistor T3 may be turned on by a second gate signal GC transmitted to the second gate line GCL to diode-connect the gate of the first transistor T1 and the second terminal of the first transistor T1.

[0068] The fourth transistor T4 may be connected between the first initialization voltage line VL1 and the gate of the first transistor T1. The fourth transistor T4 may include a gate connected to the third gate line GIL, a first terminal connected to the first node N1, and a second terminal connected to the first initialization voltage line VL1. The fourth transistor T4 may be turned on in response to a third gate signal GI transmitted to the third gate line GIL to transmit the first initialization voltage Vint from the first initialization voltage line VL1 to the first node N1 to initialize the first node N1.

[0069] The fifth transistor T5 may be connected between the driving voltage line PL and the first transistor T1, and may include a gate connected to the emission control line EML, a first terminal connected to the driving voltage line PL, and a second terminal connected to the second node N2.

[0070] The sixth transistor T6 may be connected between the first transistor T1 and the organic light emitting diode OLED. The sixth transistor T6 may include a gate connected to an emission control line EML, a first terminal connected to a third node N3, and a second terminal connected to a pixel electrode of the organic light emitting diode OLED. The fifth transistor T5 and the sixth transistor T6 may be simultaneously turned on by an emission control signal EM transmitted to the emission control line EML, so that a driving current may flow to the pixel electrode of the organic light emitting diode OLED.

[0071] The seventh transistor T7 may be connected between the second initialization voltage line VL2 and the organic light emitting diode OLED. The seventh transistor T7 may have a gate connected to the fourth gate line GBL, a first terminal connected to the second initialization voltage line VL2, and a second terminal connected to a pixel electrode of the organic light emitting diode OLED. The seventh transistor T7 may be turned on in response to a fourth gate signal GB transmitted to the fourth gate line GBL to transmit a second initialization voltage Vaint from the second initialization voltage line VL2 to the pixel electrode of the organic light emitting diode OLED, thereby initializing the pixel electrode of the organic light emitting diode OLED. The seventh transistor T7 provides a bypass current path other than the current path of the organic light emitting diode OLED, allowing the display device 10 (see FIG. 1A) to display an image with a higher contrast ratio.

[0072] The eighth transistor T8 may be connected between the bias voltage line VL3 and the first transistor T1. The eighth transistor T8 may include a gate connected to the fourth gate line GBL, a first terminal connected to the second node N2, and a second terminal connected to the bias voltage line VL3. The eighth transistor T8 may be turned on in response to a fourth gate signal GB transmitted to the fourth gate line GBL and transmit a bias voltage Vobs from the bias voltage line VL3 to the second node N2. The eighth transistor T8 may improve brightness deviation due to differences in electrical characteristics between pixels P by controlling the voltage of the second node N2. Furthermore, if the display device 10 supports a variable refresh rate, it may reduce color coordinate changes during high frequency driving and prevent or reduce degradation of the first transistor T1 during low frequency driving.

[0073] The storage capacitor Cst may be connected between the driving voltage line PL and the gate of the first transistor T1. A first capacitor electrode of the storage capacitor Cst may be connected to the first node N1, and a second capacitor electrode of the storage capacitor Cst may be connected to the driving voltage line PL. The storage capacitor Cst may store a voltage corresponding to the threshold voltage of the first transistor T1 and the data signal Dm.

[0074] The organic light emitting diode OLED may include a pixel electrode (e.g., an anode), a counter electrode (e.g., a cathode) facing the pixel electrode, and an intermediate layer interposed between the pixel electrode and the counter electrode. The counter electrode may be a common layer common to the plurality of pixels P and supplied with the second power supply voltage ELVSS.

[0075] Some of the first through eighth transistors T1 through T8 may be P-channel transistors, and the remaining some may be N-channel transistors. In one embodiment, the first transistor T1, the second transistor T2, and the fifth through eighth transistors T5 through T8 may be P-channel transistors, and the third transistor T3 and the fourth transistor T4 may be N-channel transistors. In another embodiment, the first through eighth transistors T1 through T8 may all be N-channel transistors or all be P-channel transistors.

[0076] In one embodiment, some transistors included in the pixel circuit PC may be oxide thin film transistors, and the remaining transistors may be silicon thin film transistors. For example, the first transistor T1, the second transistor T2, and the fifth through eighth transistors T5 through T8 may be silicon thin film transistors, and the third transistor T3 and the fourth transistor T4 may be oxide thin film transistors. The oxide thin film transistors may have active patterns including an oxide-based semiconductor material. The silicon thin film transistors may be low temperature polysilicon (LTPS) thin film transistors whose active patterns include a silicon-based semiconductor material, such as amorphous silicon or polysilicon.

[0077] 3 illustrates that the pixel circuit PC includes first through eighth transistors T1 through T8 and a storage capacitor Cst, the present invention is not limited thereto, and the transistors and capacitors may be variously modified in design, such as by omitting or adding some.

[0078] FIG. 4 is a schematic layout diagram of a portion of a display device according to one embodiment of the present invention, and each of FIGS. 5 to 15 is a schematic layout diagram of a portion of a display device according to one embodiment of the present invention, layer by layer.

[0079] 4 to 15, the display area DA (see FIG. 1A) of the display device 10 may include a first area PCA1 in which a first pixel circuit PC1 is arranged, a second area PCA2 in which a second pixel circuit PC2 is arranged, and a third area PCA3 in which a third pixel circuit PC3 is arranged. The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may be sequentially arranged adjacent to each other in a first direction (x direction). The first pixel circuit PC1 may be connected to a first organic light emitting diode (OLED) emitting a first color, the second pixel circuit PC2 may be connected to a second organic light emitting diode (OLED) emitting a second color, and the third pixel circuit PC3 may be connected to a third organic light emitting diode (OLED) emitting a third color.

[0080] The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may include similar or identical components. Hereinafter, the components of the first pixel circuit PC1 will be used as a reference, and unless otherwise specified, the second pixel circuit PC2 and the third pixel circuit PC3 each include components corresponding to the components of the first pixel circuit PC1.

[0081] 4 to 15 may be repeatedly arranged in a first direction (x direction) and a second direction (y direction), which will be described below with reference to FIGS.

[0082] 5 illustrates the lower conductive layer BML. The lower conductive layer BML may include a body portion, a first connector extending from the body portion in a first direction (x-direction), and a second connector extending from the body portion in a second direction (y-direction). The body portion of the lower conductive layer BML overlaps the channel region A1 of the first transistor T1 and may prevent or reduce degradation of the first transistor T1 due to external light, etc.

[0083] The lower conductive layer BML may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), indium tin oxide (ITO), indium zinc oxide (IZO), etc., and may be a multi-layer or single layer containing the above materials. For example, the lower conductive layer BML may have a single layer structure of molybdenum (Mo).

[0084] FIG. 6 illustrates a first semiconductor layer 1100 disposed on a lower conductive layer BML, and FIG. 7 illustrates a first conductive layer 1200 disposed on the first semiconductor layer 1100. For ease of explanation, FIG. 8 illustrates the first semiconductor layer 1100 and the first conductive layer 1200 overlapping each other. At least one insulating layer may be disposed between the lower conductive layer BML and the first semiconductor layer 1100, and between the first semiconductor layer 1100 and the first conductive layer 1200. The first semiconductor layer 1100 may include a silicon-based semiconductor material, such as amorphous silicon or polycrystalline silicon. The first conductive layer 1200 may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be a multilayer or single layer containing the above materials. For example, the first conductive layer 1200 may have a single layer structure of molybdenum (Mo).

[0085] The first semiconductor layer 1100 may include a first semiconductor pattern 1110 and a second semiconductor pattern 1120 spaced apart from the first semiconductor pattern 1110. The first semiconductor pattern 1110 may include a channel region A1 of the first transistor T1, a channel region a2 of the second transistor T2, a channel region A5 of the fifth transistor T5, a channel region A6 of the sixth transistor T6, and a channel region A7 of the seventh transistor T7, and each of the second semiconductor patterns 1120 may include a channel region A8 of the eighth transistor T8. A source region and a drain region may be disposed on both sides of each of the channel regions A1, A2, A5, A6, A7, and A8. The source regions S1, S2, S5, S6, S7, and S8 and the drain regions D1, D2, D5, D6, D7, and D8 may be regions doped with impurities.

[0086] For convenience of illustration, FIG. 8 separately shows the gate electrodes G1, G2, G5, G6, G7, G8, channel regions A1, A2, A5, A6, A7, A8, source regions S1, S2, S5, S6, S7, S8, and drain regions D1, D2, D5, D6, D7, D8 of the transistors in the first pixel circuit PC1 and the third pixel circuit PC3. However, it can be understood that the gate electrodes, channel regions, source regions, and drain regions of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are also arranged in corresponding positions in the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3, respectively.

[0087] The first semiconductor patterns 1110 may include a 1-1 semiconductor pattern 1111 arranged in the first region PCA1, a 1-2 semiconductor pattern 1112 arranged in the second region PCA2, and a 1-3 semiconductor pattern 1113 arranged in the third region PCA3. For example, the first to third pixel circuits PC1, PC2, and PC3 may each include a first semiconductor pattern 1110, and the first semiconductor pattern 1110 of the first pixel circuit PC1 may be referred to as the 1-1 semiconductor pattern 1111, the first semiconductor pattern 1110 of the second pixel circuit PC2 may be referred to as the 1-2 semiconductor pattern 1112, and the first semiconductor pattern 1110 of the third pixel circuit PC3 may be referred to as the 1-3 semiconductor pattern 1113.

[0088] The 1-1 semiconductor pattern 1111, the 1-2 semiconductor pattern 1112, and the 1-3 semiconductor pattern 1113 may be sequentially arranged adjacent to each other in a first direction (x-direction). In one embodiment, the channel region A1 of the first transistor T1 of each of the 1-1 semiconductor pattern 1111 and the 1-2 semiconductor pattern 1112 may have a bent shape to widen the driving range of the first transistor T1. Meanwhile, the channel region A1 of the first transistor T1 of the 1-3 semiconductor pattern 1113 may have a linear shape.

[0089] The first conductive layer 1200 may include a first conductive pattern 1210, a second conductive pattern 1220, an emission control line EML, a fourth gate line GBL, and a second-second initialization voltage line VL2-2.

[0090] The first conductive pattern 1210 and the second conductive pattern 1220 may have isolated shapes. The first conductive pattern 1210 may overlap a channel region A1 of the first transistor T1 and function as a gate electrode G1 of the first transistor T1. The second conductive pattern 1220 may overlap a channel region a2 of the second transistor T2. A portion of the second conductive pattern 1220 overlapping the channel region a2 of the second transistor T2 may function as a gate electrode G2 of the second transistor T2.

[0091] The emission control line EML extends in the first direction (x-direction) and may transmit a fifth gate signal EM (see FIG. 3) to the pixel circuits PC1, PC2, and PC3 arranged in the same row. The emission control line EML may overlap with the channel region A5 of the fifth transistor T5 and the channel region A6 of the sixth transistor T6. A portion of the emission control line EML overlapping with the channel region A5 of the fifth transistor T5 may function as the gate electrode G5 of the fifth transistor T5, and a portion of the emission control line EML overlapping with the channel region A6 of the sixth transistor T6 may function as the gate electrode G6 of the sixth transistor T6.

[0092] The fourth gate line GBL extends in the first direction (x direction) and may transmit a fourth gate signal GB (see FIG. 3) to pixel circuits PC1, PC2, and PC3 arranged in the same row. The fourth gate line GBL may overlap with a channel region A7 of the seventh transistor T7 and a channel region A8 of the eighth transistor T8. A portion of the fourth gate line GBL overlapping with the channel region A7 of the seventh transistor T7 may function as a gate electrode G7 of the seventh transistor T7, and a portion of the fourth gate line GBL overlapping with the channel region A8 of the eighth transistor T8 may function as a gate electrode G8 of the eighth transistor T8.

[0093] The 2-2 initialization voltage line VL2-2 extends in the first direction (x direction) and may be connected to the 1-2 semiconductor pattern 1112 via the 14th conductive pattern 1670 of the second pixel circuit PC2 (described later) and to the 1-3 semiconductor pattern 1113 via the 14th conductive pattern 1670 of the third pixel circuit PC3. As described above, the power supply circuit 17 (see FIG. 2) may transmit different second initialization voltages Vaint (see FIG. 3) to the pixels. The 2-2 initialization voltage line VL2-2 may transmit the 2-2 initialization voltage to the seventh transistor T7 of the second pixel circuit PC2 and the seventh transistor T7 of the third pixel circuit PC3.

[0094] 9 illustrates a second conductive layer 1300 disposed on the first conductive layer 1200, FIG. 10 illustrates a second semiconductor layer 1400 disposed on the second conductive layer 1300, and FIG. 11 illustrates a third conductive layer 1500 disposed on the second semiconductor layer 1400. For ease of explanation, FIG. 12 illustrates the second conductive layer 1300, the second semiconductor layer 1400, and the third conductive layer 1500 superimposed on each other. At least one insulating layer may be disposed between the first conductive layer 1200 and the second conductive layer 1300, between the second conductive layer 1300 and the second semiconductor layer 1400, and between the second semiconductor layer 1400 and the third conductive layer 1500.

[0095] The second conductive layer 1300 and the third conductive layer 1500 may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be a single layer or multiple layers including the above materials. For example, each of the second conductive layer 1300 and the third conductive layer 1500 may have a molybdenum (Mo) single layer structure.

[0096] The second semiconductor layer 1400 may include an oxide of at least one material selected from the group consisting of oxide-based semiconductor materials, such as indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In one embodiment, the second semiconductor layer 1400 may be IGZO (In-Ga-Zn-O) or ITGZO (In-Sn-Ga-Zn-O).

[0097] The second conductive layer 1300 may include a third conductive pattern 1310, a fourth conductive pattern 1320, a fifth conductive pattern 1330, and a sixth conductive pattern 1340. The second semiconductor layer 1400 may include a third semiconductor pattern 1410.

[0098] The third semiconductor pattern 1410 may include a channel region A3 of the third transistor T3 and a channel region A4 of the fourth transistor T4. A source region and a drain region may be disposed on both sides of each of the channel regions A3 and A4. The source regions S3 and S4 and the drain regions D3 and D4 may be regions doped with impurities. The third semiconductor pattern 1410 may include a 3-1 semiconductor pattern 1411 disposed in the first region PCA1, a 3-2 semiconductor pattern 1412 disposed in the second region PCA2, and a 3-3 semiconductor pattern 1413 disposed in the third region PCA3.

[0099] For convenience of illustration, FIG. 12 shows the gate electrodes, channel regions, source regions, and drain regions of the transistors in the third pixel circuit PC3, but it can be understood that the gate electrodes G3, G4, channel regions A3, A4, source regions S3, S4, and drain regions D3, D4 of the third transistor T3 and the fourth transistor T4 are also arranged in corresponding positions in the first pixel circuit PC1 and the second pixel circuit PC2, respectively.

[0100] The third conductive layer 1500 may include a seventh conductive pattern 1510, an eighth conductive pattern 1520, a repair line RL, and a 2-1st initialization voltage line VL2-1.

[0101] The third conductive pattern 1310 may include a body portion 1311 and a connecting portion 1312 connecting adjacent body portions 1311 in a first direction (x-direction). The body portion 1311 of the third conductive pattern 1310 may overlap the first conductive pattern 1210 of the first conductive layer 1200 to form a storage capacitor Cst (see FIG. 3). For example, the first conductive pattern 1210 may function as a lower capacitor electrode of the storage capacitor Cst, and the third conductive pattern 1310 may function as an upper capacitor electrode of the storage capacitor Cst. The third conductive pattern 1310 may define a first hole 1310OP exposing a portion of the first conductive pattern 1210.

[0102] Each of the fourth conductive pattern 1320, the fifth conductive pattern 1330, the seventh conductive pattern 1510, and the eighth conductive pattern 1520 may have an isolated shape. The fourth conductive pattern 1320 may overlap the seventh conductive pattern 1510, and a channel region A3 of the third transistor T3 may be disposed between the fourth conductive pattern 1320 and the seventh conductive pattern 1510. Each of the fourth conductive pattern 1320 and the seventh conductive pattern 1510 may be connected to a second gate line GCL (described below) and may function as a gate electrode G3 of the third transistor T3. For example, the fourth conductive pattern 1320 may function as a lower gate electrode of the third transistor T3, and the seventh conductive pattern 1510 may function as an upper gate electrode of the third transistor T3.

[0103] The fifth conductive pattern 1330 overlaps with the eighth conductive pattern 1520, and a channel region A4 of the fourth transistor T4 may be disposed between the fifth conductive pattern 1330 and the eighth conductive pattern 1520. The fifth conductive pattern 1330 and the eighth conductive pattern 1520 may be connected to a third gate line GIL (described later) and function as a gate electrode G4 of the fourth transistor T4. For example, the fifth conductive pattern 1330 may function as a lower gate electrode of the fourth transistor T4, and the eighth conductive pattern 1520 may function as an upper gate electrode of the fourth transistor T4.

[0104] The sixth conductive pattern 1340 may be disposed between the second pixel circuit PC2 and the third pixel circuit PC3. For example, the sixth conductive pattern 1340 may be disposed across the second region PCA2 and the third region PCA3. The sixth conductive pattern 1340 may be connected to one of the voltage lines (e.g., the first initialization voltage line VL1, the 2-1st initialization voltage line VL2-1, the 2-2nd initialization voltage line VL2-2, etc.) extending in the first direction (x direction) and the vertical voltage transmission line VLv, which will be described later. In this regard, FIGS. 4, 9, 12, 13, and 14 illustrate that the sixth conductive pattern 1340 is connected to the vertical voltage transmission line VLv through the first initialization voltage line VL1 and the 15th conductive pattern 1680.

[0105] The repair line RL may extend in a first direction (x direction) and may be arranged to connect a dummy pixel circuit arranged in the peripheral area PA (see FIG. 1A) to a light emitting diode corresponding to the defective pixel circuit in place of the defective pixel circuit when a defect occurs in the pixel circuit.

[0106] The 2-1st initialization voltage line VL2-1 may extend in the first direction (x-direction) and may be connected to the 1-1st semiconductor pattern 1111 via the fourteenth conductive pattern 1670 of the first pixel circuit PC1. As described above, the power supply circuit 17 (see FIG. 2) may transmit different second initialization voltages Vaint (see FIG. 3) to the pixels P (see FIG. 2). The 2-1st initialization voltage line VL2-1 may transmit a 2-1st initialization voltage, which is different from the 2-2nd initialization voltage, to the seventh transistor T7 of the first pixel circuit PC1.

[0107] FIG. 13 illustrates a fourth conductive layer 1600 disposed on the third conductive layer 1500, and FIG. 14 illustrates a fifth conductive layer 1700 disposed on the fourth conductive layer 1600. At least one insulating layer may be disposed between the third conductive layer 1500 and the fourth conductive layer 1600, and between the fourth conductive layer 1600 and the fifth conductive layer 1700. Each of the fourth conductive layer 1600 and the fifth conductive layer 1700 may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be a single layer or multilayer containing the above materials. For example, each of the fourth conductive layer 1600 and the fifth conductive layer 1700 may have a Ti / Al / Ti multilayer (stacked) structure.

[0108] 15 illustrates a sixth conductive layer 1800 disposed on the fifth conductive layer 1700. At least one insulating layer may be disposed between the fifth conductive layer 1700 and the sixth conductive layer 1800. The sixth conductive layer 1800 includes a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semi-transparent conductive layer formed on the reflective layer. The transparent or semi-transparent conductive layer includes at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In one embodiment, the sixth conductive layer 1800 may have a multi-layer structure of ITO / Ag / ITO.

[0109] The fourth conductive layer 1600 may include a horizontal voltage transmission wiring 1610, a ninth conductive pattern 1620, a tenth conductive pattern 1630, an eleventh conductive pattern 1640, a twelfth conductive pattern 1650, a thirteenth conductive pattern 1660, a fourteenth conductive pattern 1670, a fifteenth conductive pattern 1680, a first initialization voltage line VL1, a third gate line GIL, a first gate line GWL, a second gate line GCL, and a bias voltage line VL3.

[0110] The fifth conductive layer 1700 may include a sixteenth conductive pattern 1710, a driving voltage line PL, and a data line DL. The sixth conductive layer 1800 may include a first pixel electrode 210a, a second pixel electrode 210b, and a third pixel electrode 210c. The ninth conductive pattern 1620, the tenth conductive pattern 1630, the eleventh conductive pattern 1640, the twelfth conductive pattern 1650, the thirteenth conductive pattern 1660, the fourteenth conductive pattern 1670, the fifteenth conductive pattern 1680, and the sixteenth conductive pattern 1710 may have an isolated shape.

[0111] The horizontal voltage transmission line 1610 extends in the first direction (x-direction) and may be connected to the lower conductive layer BML through the first-1 contact hole CNT1a, the third conductive pattern 1310 through the first-2 contact hole CNT1b, and the first semiconductor pattern 1110 through the first-3 contact hole CNT1c. The horizontal voltage transmission line 1610 may be connected to the first driving voltage line PL1, the second driving voltage line PL2, and the third driving voltage line PL3 through the fourteenth contact hole CNT14 and may transmit the first power supply voltage ELVDD (see FIG. 3). The horizontal voltage transmission line 1610 may connect the source region S5 of the fifth transistor T5, the upper capacitor electrode of the storage capacitor Cst, and the driving voltage line PL.

[0112] The ninth conductive pattern 1620 may be connected to the first semiconductor pattern 1110 through the second contact hole CNT2 and may be connected to the sixteenth conductive pattern 1710 through the thirteenth contact hole CNT13. The ninth conductive pattern 1620 and the sixteenth conductive pattern 1710 may connect the drain region D6 of the sixth transistor T6, the source region S7 of the seventh transistor T7, and the pixel electrode of the organic light emitting diode OLED (see FIG. 3).

[0113] The ninth conductive pattern 1620 may include a 9-1 conductive pattern 1620a arranged in the first region PCA1, a 9-2 conductive pattern 1620b arranged in the second region PCA2, and a 9-3 conductive pattern 1620c arranged in the third region PCA3. Similarly, the sixteenth conductive pattern 1710 may include a 16-1 conductive pattern 1710a arranged in the first region PCA1, a 16-2 conductive pattern 1710b arranged in the second region PCA2, and a 16-3 conductive pattern 1710c arranged in the third region PCA3.

[0114] The first pixel electrode 210a may be connected to the 16-1 conductive pattern 1710a through the 16th contact hole CNT16, the second pixel electrode 210b may be connected to the 16-2 conductive pattern 1710b through the 17th contact hole CNT17, and the third pixel electrode 210c may be connected to the 16-3 conductive pattern 1710c through the 18th contact hole CNT18. That is, the first pixel electrode 210a may be connected to the first pixel circuit PC1, the second pixel electrode 210b may be connected to the second pixel circuit PC2, and the third pixel electrode 210c may be connected to the third pixel circuit PC3.

[0115] The tenth conductive pattern 1630 may be connected to the first conductive pattern 1210 through the 3-1 contact hole CNT3a and the first hole 1310OP of the third conductive pattern 1310, and may be connected to the third semiconductor pattern 1410 through the 3-2 contact hole CNT3b. The tenth conductive pattern 1630 may connect the gate electrode G1 of the first transistor T1, the lower capacitor layer of the storage capacitor Cst, the source region S3 of the third transistor T3, and the drain region D4 of the fourth transistor T4.

[0116] The eleventh conductive pattern 1640 may be connected to the first semiconductor pattern 1110 through the 4-1 contact hole CNT4a and may be connected to the third semiconductor pattern 1410 through the 4-2 contact hole CNT4b. The eleventh conductive pattern 1640 may connect the drain region D3 of the third transistor T3 to the drain region D1 of the first transistor T1. The eleventh conductive pattern 1640 is also referred to as a connecting electrode that connects one terminal of the first transistor T1 to one terminal of the third transistor T3.

[0117] The eleventh conductive pattern 1640 may include an 11-1 conductive pattern 1640a of the first pixel circuit PC1 arranged in the first region PCA1, an 11-2 conductive pattern 1640b of the second pixel circuit PC2 arranged in the second region PCA2, and an 11-3 conductive pattern 1640c of the third pixel circuit PC3 arranged in the third region PCA3. The 11-1 conductive pattern 1640a may connect the 1-1 semiconductor pattern 1111 to the 3-1 semiconductor pattern 1411, the 11-2 conductive pattern 1640b may connect the 1-2 semiconductor pattern 1112 to the 3-2 semiconductor pattern 1412, and the 11-3 conductive pattern 1640c may connect the 1-3 semiconductor pattern 1113 to the 3-3 semiconductor pattern 1413.

[0118] The twelfth conductive pattern 1650 may be connected to the first semiconductor pattern 1110 through the fifth contact hole CNT5 and may be connected to the data line DL through the fifteenth contact hole CNT15. ​​The twelfth conductive pattern 1650 may connect the source region S2 of the second transistor T2 to the data line DL. The first data line DL1 may be connected to the twelfth conductive pattern 1650 of the first pixel circuit PC1, the second data line DL2 may be connected to the twelfth conductive pattern 1650 of the second pixel circuit PC2, and the third data line DL3 may be connected to the twelfth conductive pattern 1650 of the third pixel circuit PC3.

[0119] The thirteenth conductive pattern 1660 may be connected to the first semiconductor pattern 1110 through the 6-1 contact hole CNT6a and may be connected to the second semiconductor pattern 1120 through the 6-2 contact hole CNT6b. The thirteenth conductive pattern 1660 may connect the source region S1 of the first transistor T1, the drain region D2 of the second transistor T2, the drain region D5 of the fifth transistor T5, and the drain region D8 of the eighth transistor T8.

[0120] The fourteenth conductive pattern 1670 may be connected to the first semiconductor pattern 1110 through the seventh-first contact hole CNT7a and may be connected to the second-first initialization voltage line VL2-1 or the second-second initialization voltage line VL2-2 through the seventh-second contact hole CNT7b. The fourteenth conductive pattern 1670 may connect the drain region D7 of the seventh transistor T7 to the first-first initialization voltage line VL2-1 or the second-second initialization voltage line VL2-2. For example, the 14th conductive pattern 1670 arranged in the first region PCA1 may connect the 1-1 semiconductor pattern 1111 to the 2-1 initialization voltage line VL2-1, the 14th conductive pattern 1670 arranged in the second region PCA2 may connect the 1-2 semiconductor pattern 1112 to the 2-2 initialization voltage line VL2-2, and the 14th conductive pattern 1670 arranged in the third region PCA3 may connect the 1-3 semiconductor pattern 1113 to the 2-2 initialization voltage line VL2-2.

[0121] The fifteenth conductive pattern 1680 may be disposed between the second pixel circuit PC2 and the third pixel circuit PC3. For example, the fifteenth conductive pattern 1680 may be disposed in the third region PCA3. The fifteenth conductive pattern 1680 may be connected to the sixth conductive pattern 1340 through a twentieth contact hole CNTv2 and to the vertical voltage transmission line VLv through a twenty-first contact hole CNTv3.

[0122] The first gate line GWL, the second gate line GCL, the third gate line GIL, the first initialization voltage line VL1, and the bias voltage line VL3 may extend in a first direction (x direction). The first gate line GWL may be connected to the second conductive pattern 1220 through a ninth contact hole CNT9. The first gate line GWL may transmit a first gate signal GW (see FIG. 3) to the gate electrode G2 of the second transistor T2.

[0123] The second gate line GCL may be connected to the fourth conductive pattern 1320 through the 10-1 contact hole CNT10a and may be connected to the seventh conductive pattern 1510 through the 10-2 contact hole CNT10b. The second gate line GCL may transmit a second gate signal GC (see FIG. 3) to the gate electrode G3 of the third transistor T3.

[0124] The third gate line GIL may be connected to the fifth conductive pattern 1330 through an 8-1 contact hole CNT8a and to the eighth conductive pattern 1520 through an 8-2 contact hole CNT8b. The third gate line GIL may transmit a third gate signal GI (see FIG. 3) to the gate electrode G4 of the fourth transistor T4.

[0125] The first initialization voltage line VL1 may be connected to the third semiconductor pattern 1410 through the twelfth contact hole CNT12. The first initialization voltage line VL1 may transmit a first initialization voltage Vint (see FIG. 3) to the source region S4 of the fourth transistor T4. In one embodiment, the first initialization voltage line VL1 may be connected to the sixth conductive pattern 1340 through the ninth contact hole CNTv1. As described above, the sixth conductive pattern 1340 is connected to the vertical voltage transmission line VLv through the fifteenth conductive pattern 1680, and the first initialization voltage line VL1 and the vertical voltage transmission line VLv may form a mesh structure.

[0126] The bias voltage line VL3 may be connected to the second semiconductor pattern 1120 through the eleventh contact hole CNT11. The bias voltage line VL3 may transmit a bias voltage Vobs (see FIG. 3) to the source region S8 of the eighth transistor T8.

[0127] The driving voltage lines PL may include a first driving voltage line PL1 arranged in the first region PCA1, a second driving voltage line PL2 arranged in the second region PCA2, and a third driving voltage line PL3 arranged in the third region PCA3. The first driving voltage line PL1 may overlap the first pixel circuit PC1, the second driving voltage line PL2 may overlap the second pixel circuit PC2, and the third driving voltage line PL3 may overlap the third pixel circuit PC3. The first driving voltage line PL1, the second driving voltage line PL2, and the third driving voltage line PL3 may extend in the second direction (y direction) and be connected to the horizontal voltage transmission line 1610 through the fourteenth contact hole CNT14. The driving voltage lines PL may transmit a first power supply voltage ELVDD (see FIG. 3).

[0128] The data lines DL may include a first data line DL1 connected to the first pixel circuit PC1, a second data line DL2 connected to the second pixel circuit PC2, and a third data line DL3 connected to the third pixel circuit PC3. Each of the first, second, and third data lines DL1, DL2, and DL3 may extend in the second direction (y direction) and be connected to the twelfth conductive pattern 1650 via a fifteenth contact hole CNT15. ​​The first data line DL1 may transmit a data signal Dm (see FIG. 3) to the first pixel circuit PC1, the second data line DL2 may transmit a data signal Dm to the second pixel circuit PC2, and the third data line DL3 may transmit a data signal Dm to the third pixel circuit PC3. The first pixel may be a red pixel that emits red light, the second pixel may be a green pixel that emits green light, and the third pixel may be a blue pixel that emits blue light. The first driving voltage line PL1, the first data line DL1, the second driving voltage line PL2, the second data line DL2, the third driving voltage line PL3, and the third data line DL3 may be sequentially arranged along the first direction (x direction). In a plan view, the first data line DL1 may be bent to bypass the 11-2 conductive pattern 1640b and the 16-2 conductive pattern 1710b of the second pixel circuit PC2 and overlap with the second region PCA2. In a plan view, the 11-2 conductive pattern 1640b may be arranged between the first driving voltage line PL1 and the first data line DL1.

[0129] For example, when the conductive pattern 11-2 of the second pixel circuit overlaps with the first data line in a plan view, the conductive pattern 11-2 and the first data line are adjacent to each other in the thickness direction (z direction), and therefore, coupling due to parasitic capacitance may occur between the conductive pattern 11-2 and the first data line. For example, the voltage of the drain region of the first transistor of the second pixel circuit connected to the conductive pattern 11-2 may increase due to a data signal applied to the first data line. Therefore, the brightness of the second organic light emitting diode connected to the second pixel circuit may change depending on the data signal applied to the first data line, resulting in unevenness in the image displayed by the display device.

[0130] Meanwhile, according to an exemplary embodiment of the present invention, the first data line DL1 is spaced a sufficient distance from the 11-2 conductive pattern 1640b in a plan view, thereby reducing parasitic capacitance between the first data line DL1 and the 11-2 conductive pattern 1640b. Therefore, coupling between the first data line DL1 and the 11-2 conductive pattern 1640b of the adjacent second pixel circuit PC2 can be prevented or reduced. Even if the 11-2 conductive pattern 1640b and the first data line DL1 are adjacent in the thickness direction (z direction), the display device 10 can prevent or reduce a change in the luminance of the second pixel circuit PC2 due to the first data line DL1 by spacing them a sufficient distance in a plan view, thereby displaying a high-quality image.

[0131] The first data line DL1 may overlap the drain region D1 of the first transistor T1 of the second pixel circuit PC2 to bypass the 11-2 conductive pattern 1640b. In this case, the third conductive pattern 1310 may extend to an area where the first data line DL1 and the drain region D1 of the first transistor T1 of the second pixel circuit PC2 overlap. In other words, the drain region D1 of the first transistor T1 of the second pixel circuit PC2, the third conductive pattern 1310, and the first data line DL1 may overlap in a plan view. The third conductive pattern 1310 is connected to the horizontal voltage transmission line 1610 to transmit the first power supply voltage ELVDD, and therefore may effectively shield the first transistor T1 of the second pixel circuit PC2 from the first data line DL1.

[0132] In the display area DA (see FIGS. 1A and 1B), the second data line DL2 may have a linear shape extending in the second direction (y direction). The third data line DL3 may extend in the second direction (y direction) but may have a bent shape to be spaced apart from the third driving voltage line PL3 and the pixel electrode of the adjacent pixel P (see FIG. 2).

[0133] The vertical voltage transmission wiring VLv may extend in the second direction (y direction) and be disposed between the second pixel circuit PC2 and the third pixel circuit PC3. As described above, the vertical voltage transmission wiring VLv may be connected to one of the voltage lines (e.g., the first initialization voltage line VL1, the 2-1st initialization voltage line VL2-1, the 2-2nd initialization voltage line VL2-2, etc.) extending in the first direction (x direction) via the sixth conductive pattern 1340 and the fifteenth conductive pattern 1680 to form a mesh structure.

[0134] The first, second, and third pixel electrodes 210a, 210b, and 210c may be arranged in a predetermined pattern. For example, the first and second pixel electrodes 210a, 210b may be alternately arranged in the second direction (y direction), and the third pixel electrode 210c may be arranged in a stripe pattern spaced apart from the first and second pixel electrodes 210a, 210b in the first direction (x direction).

[0135] In one embodiment, the first pixel electrode 210a may be a pixel electrode of a first organic light emitting diode of a first pixel that emits red light, the second pixel electrode 210b may be a pixel electrode of a second organic light emitting diode of a second pixel that emits green light, and the third pixel electrode 210c may be a pixel electrode of a third organic light emitting diode of a third pixel that emits blue light.

[0136] 16 and 17 are cross-sectional views each showing a display device according to an embodiment of the present invention, with FIG. 16 showing a cross-section taken along line II' of the display device 10 shown in FIG.

[0137] For convenience of explanation, each of FIGS. 16 and 17 shows a schematic cross section of the display device 10 from the substrate 100 to the pixel defining film 110.

[0138] 4 and 16, the display device 10 may include a substrate 100. Components of the display device 10 are arranged on the substrate 100, and therefore the substrate 100 may also be said to include a first region PCA1, a second region PCA2, and a third region PCA3. A first pixel circuit PC1 may be arranged in the first region PCA1, a second pixel circuit PC2 may be arranged in the second region PCA2, and a third pixel circuit PC3 may be arranged in the third region PCA3.

[0139] The substrate 100 may include glass, metal, or a polymer resin, such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. In one embodiment, the substrate 100 may have a multilayer structure including two layers containing polymer resin and a barrier layer containing an inorganic material (such as silicon nitride, silicon oxide, or silicon oxynitride) sandwiched between the two layers.

[0140] A first insulating layer 101 may be disposed on the substrate 100, and a lower conductive layer BML may be disposed on the first insulating layer 101. The first insulating layer 101 may be a barrier layer for blocking impurity penetration from the substrate 100. A second insulating layer 102 may be disposed on the lower conductive layer BML, and a first semiconductor layer 1100 (see FIG. 6) may be disposed on the second insulating layer 102. The second insulating layer 102 may be a buffer layer for blocking impurity penetration from the substrate 100 and providing a flat upper surface.

[0141] The first semiconductor layer 1100 may include a first-second semiconductor pattern 1112 including a channel region A1 of the first transistor T1 of the second pixel circuit PC2. The first-second semiconductor pattern 1112 may include a silicon-based semiconductor material. The body portion of the lower conductive layer BML may overlap the channel region A1 of the first transistor T1 and may prevent or reduce degradation of the first transistor T1 due to external light, etc.

[0142] A third insulating layer 103 may be disposed on the first semiconductor layer 1100, and a first conductive layer 1200 (see FIG. 7) may be disposed on the third insulating layer 103. The third insulating layer 103 may be a first gate insulating layer. The first conductive layer 1200 may include a first conductive pattern 1210. The first conductive pattern 1210 may overlap with the channel region A1 of the first transistor T1 on the first-2 semiconductor pattern 1112 and function as a gate electrode of the first transistor T1.

[0143] A fourth insulating layer 104 may be disposed on the first conductive layer 1200, and a second conductive layer 1300 (see FIG. 9 ) may be disposed on the fourth insulating layer 104. The second conductive layer 1300 may include a third conductive pattern 1310 and a fourth conductive pattern 1320. The third conductive pattern 1310 may overlap the first conductive pattern 1210 to form a storage capacitor Cst. For example, the first conductive pattern 1210 may function as a lower capacitor electrode of the storage capacitor Cst, and the third conductive pattern 1310 may function as an upper capacitor electrode of the storage capacitor Cst. The third conductive pattern 1310 may define a first hole 1310OP that exposes a portion of the first conductive pattern 1210.

[0144] A fifth insulating layer 105 may be disposed on the second conductive layer 1300, and a second semiconductor layer (1400, see FIG. 10) may be disposed on the fifth insulating layer 105. The second semiconductor layer 1400 may include a 3-2 semiconductor pattern 1412 disposed on the 1-2 semiconductor pattern 1112. The 3-2 semiconductor pattern 1412 may include a channel region A3 of the third transistor T3 of the second pixel circuit PC2. The 3-2 semiconductor pattern 1412 may include an oxide-based semiconductor material.

[0145] A sixth insulating layer 106 may be disposed on the second semiconductor layer 1400, and a third conductive layer 1500 (see FIG. 11 ) may be disposed on the sixth insulating layer 106. The sixth insulating layer 106 may be a second gate insulating layer. The third conductive layer 1500 may include a seventh conductive pattern 1510. The fourth conductive pattern 1320 may overlap the channel region A3 of the third transistor T3 under the 3-2 semiconductor pattern 1412 and function as a lower gate electrode of the third transistor T3. The seventh conductive pattern 1510 may overlap the channel region A3 of the third transistor T3 on the 3-2 semiconductor pattern 1412 and function as an upper gate electrode of the third transistor T3.

[0146] A seventh insulating layer 107 may be disposed on the third conductive layer 1500, and a fourth conductive layer 1600 (see FIG. 13) may be disposed on the seventh insulating layer 107. The fourth conductive layer 1600 may include a tenth conductive pattern 1630 and an 11-2 conductive pattern 1640b.

[0147] The tenth conductive pattern 1630 may be connected to the 3-2 semiconductor pattern 1412 through a 3-2 contact hole CNT3b (see FIG. 13) that penetrates the sixth insulating layer 106 and the seventh insulating layer 107, and may be connected to the first conductive pattern 1210 through a 3-1 contact hole CNT3a (see FIG. 13) that penetrates the fourth insulating layer 104, the fifth insulating layer 105, the sixth insulating layer 106, and the seventh insulating layer 107. The tenth conductive pattern 1630 may connect one terminal of the third transistor T3 to the gate electrode of the first transistor T1.

[0148] The 11-2 conductive pattern 1640b may be connected to the 3-2 semiconductor pattern 1412 through a 4-2 contact hole CNT4b (see FIG. 13) that penetrates the sixth insulating layer 106 and the seventh insulating layer 107, and may be connected to the 1-2 semiconductor pattern 1112 through a 4-1 contact hole CNT4a (see FIG. 13) that penetrates the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105, the sixth insulating layer 106, and the seventh insulating layer 107. The 11-2 conductive pattern 1640b may function as a connecting electrode CTE that connects one terminal of the first transistor T1 and one terminal of the third transistor T3.

[0149] In one embodiment, the connecting electrode CTE connecting one terminal of the first transistor T1 and one terminal of the third transistor T3 may be included in a conductive layer other than the fourth conductive layer 1600. For example, as shown in FIG. 17 , the connecting electrode CTE may be disposed in the same layer as the gate electrode (seventh conductive pattern 1510) of the third transistor T3. That is, the connecting electrode CTE may be included in the third conductive layer 1500. Alternatively, the display device 10 may further include a seventh conductive layer below the sixth conductive layer 1800, and the connecting electrode CTE may be included in the seventh conductive layer.

[0150] An eighth insulating layer 108 may be disposed on the fourth conductive layer 1600, and a fifth conductive layer 1700 (see FIG. 14) may be disposed on the eighth insulating layer 108. The fifth conductive layer 1700 may include a first data line DL1 and a second driving voltage line PL2 connected to the first pixel circuit PC1.

[0151] To reduce parasitic capacitance between the first data line DL1 and the connecting electrode CTE, the first data line DL1 may detour to a sufficient distance from the connecting electrode CTE and have a bent shape in a plan view. The first data line DL1 may partially overlap the first-second semiconductor pattern 1112 to detour around the connecting electrode CTE. The overlapping region of the first data line DL1 and the first-second semiconductor pattern 1112 may be the drain region D1 of the first transistor T1. The third conductive pattern 1310 may extend to the overlapping region of the first data line DL1 and the drain region D1 of the first transistor T1 and shield the drain region D1 of the first transistor T1 from the first data line DL1. A portion of the second driving voltage line PL2 may overlap the channel region A3 of the third transistor T3 and shield the third transistor T3 from external light.

[0152] A ninth insulating layer 109 may be disposed on the fifth conductive layer 1700, and a sixth conductive layer 1800 (see FIG. 15 ) may be disposed on the ninth insulating layer 109. The sixth conductive layer 1800 may include a second pixel electrode 210b. The second pixel electrode 210b may be a pixel electrode of a second light emitting diode connected to the second pixel circuit PC2. The second pixel electrode 210b may have a protrusion overlapping a portion of the 3-2 semiconductor pattern 1412 and may shield the 3-2 semiconductor pattern 1412 from external light.

[0153] Each of the first to sixth insulating layers 101, 102, 103, 104, 105, and 106 may be a single layer or a multilayer containing an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride. Each of the seventh insulating layer 107, the eighth insulating layer 108, and the ninth insulating layer 109 may be a single layer or a multilayer containing an inorganic material and / or an organic material. Here, the inorganic material may include silicon oxide, silicon nitride, or silicon oxynitride, and the organic material may include acrylic, BCB (benzocyclobutene), HMDSO (hexamethyldisiloxane), or the like.

[0154] The pixel defining layer 110 may be disposed on the sixth conductive layer 1800. The pixel defining layer 110 may include one or more organic materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0155] Figure 18A is a schematic layout diagram of pixel electrodes, voltage lines, and data lines of a display device according to an embodiment of the present invention, and Figure 18B is a schematic cross-sectional view of a display device according to an embodiment of the present invention, taken along line II-II' of the display device 10 shown in Figure 18A.

[0156] 18A shows the fifth conductive layer 1700, the sixth conductive layer 1800, and the openings OP1, OP2, OP3, and OPs of the pixel defining (defining) film 110 superimposed on each other. Fig. 18B schematically illustrates a cross section from the eighth insulating layer 108 to the counter electrode 230 of the display device 10.

[0157] 18A and 18B, a fifth conductive layer 1700 may be disposed on the eighth insulating layer 108. The fifth conductive layer 1700 may include the driving voltage line PL, the data line DL, a sixteenth conductive pattern 1710, and the vertical voltage transmission line VLv.

[0158] The driving voltage lines PL may include a first driving voltage line PL1 disposed in the first region PCA1 and overlapping the first pixel circuit PC1 (see FIG. 4), a second driving voltage line PL2 disposed in the second region PCA2 and overlapping the second pixel circuit PC2 (see FIG. 4), and a third driving voltage line PL3 disposed in the third region PCA3 and overlapping the third pixel circuit PC3 (see FIG. 4). The data lines DL may include a first data line DL1 connected to the first pixel circuit PC1, a second data line DL2 connected to the second pixel circuit PC2, and a third data line DL3 connected to the third pixel circuit PC3. The sixteenth conductive pattern 1710 may include a 16-1 conductive pattern 1710a of the first pixel circuit PC1, a 16-2 conductive pattern 1710b of the second pixel circuit PC2, and a 16-3 conductive pattern 1710c of the third pixel circuit PC3.

[0159] The first driving voltage line PL1, the first data line DL1, the second driving voltage line PL2, the second data line DL2, the third driving voltage line PL3, and the third data line DL3 may be sequentially arranged along the first direction (x direction). The vertical voltage transmission line VLv may be arranged between the second pixel circuit PC2 and the third pixel circuit PC3. For example, the vertical voltage transmission line VLv may be arranged between the second data line DL2 and the third driving voltage line PL3.

[0160] A ninth insulating layer 109 may be disposed on the fifth conductive layer 1700, and a sixth conductive layer 1800 may be disposed on the ninth insulating layer 109. The sixth conductive layer 1800 may include a first pixel electrode 210a connected to the 16-1 conductive pattern 1710a through a 16th contact hole CNT16, a second pixel electrode 210b connected to the 16-2 conductive pattern 1710b through a 17th contact hole CNT17, and a third pixel electrode 210c connected to the 16-3 conductive pattern 1710c through an 18th contact hole CNT18.

[0161] The first pixel electrode 210a may be a pixel electrode of a first organic light emitting diode (not shown) connected to the first pixel circuit PC1, the second pixel electrode 210b may be a pixel electrode of a second organic light emitting diode OLED2 connected to the second pixel circuit PC2, and the third pixel electrode 210c may be a pixel electrode of a third organic light emitting diode OLED3 connected to the third pixel circuit PC3. In one embodiment, the first organic light emitting diode may emit red light, the second organic light emitting diode OLED2 may emit green light, and the third organic light emitting diode OLED3 may emit blue light.

[0162] The first to third pixel electrodes 210a, 210b, and 210c may be repeatedly arranged in a first direction (x direction) and a second direction (y direction) according to a predetermined pattern. For example, the first pixel electrodes 210a and the second pixel electrodes 210b may be alternately arranged along the second direction (y direction), and the third pixel electrode 210c may be spaced apart from the first pixel electrodes 210a and the second pixel electrodes 210b in the first direction (x direction).

[0163] A pixel defining (defining) film 110 may be disposed on the fifth conductive layer 1700. The pixel defining (defining) film 110 may define a first pixel opening OP1 overlapping the first pixel electrode 210a, a second pixel opening OP2 overlapping the second pixel electrode 210b, and a third pixel opening OP3 overlapping the third pixel electrode 210c. The pixel defining (defining) film 110 may cover edges of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c. The pixel definition film 110 can prevent or reduce the occurrence of arcs and the like at the edges of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c by increasing the distance between the edge of the first pixel electrode 210a and the counter electrode 230, the distance between the edge of the second pixel electrode 210b and the counter electrode 230, and the distance between the edge of the third pixel electrode 210c and the counter electrode 230.

[0164] The first pixel aperture OP1 defines a first light-emitting area of ​​the first organic light-emitting diode OLED2 and may overlap the first driving voltage line PL1 in a plan view. The second pixel aperture OP2 defines a second light-emitting area EA2 of the second organic light-emitting diode OLED2 and may overlap the first driving voltage line PL1 in a plan view.

[0165] A line passing through the center of the first pixel aperture OP1 and the center of the second pixel aperture OP2 and extending in the second direction (y direction) may be defined as a first imaginary line CL1. A portion of the first driving voltage line PL1 overlapping the first pixel aperture OP1 may be line-symmetric with respect to the first imaginary line CL1. Similarly, a portion of the first driving voltage line PL1 overlapping the second pixel aperture OP2 may be line-symmetric with respect to the first imaginary line CL1. For example, as shown in FIG. 18B , both boundaries of the first driving voltage line PL1 overlapping the second pixel aperture OP2 may be equally spaced a first distance d1 from the first imaginary line CL1.

[0166] The third pixel aperture OP3 defines a third light-emitting area EA3 of the third organic light-emitting diode OLED3 and may overlap with the second driving voltage line PL2, the second data line DL2, the vertical voltage transmission line VLv, and the third driving voltage line PL3 in a planar view. A line passing through the center of the third pixel aperture OP3 and extending in the second direction (y direction) may be defined as a virtual second line CL2. A portion of the second driving voltage line PL2, a portion of the second data line DL2, a portion of the vertical voltage transmission line VLv, and a portion of the third driving voltage line PL3 that overlap with the third pixel aperture OP3 may be symmetrical with respect to the virtual second line CL2.

[0167] 18B, the boundary of the second data line DL2 and the boundary of the vertical voltage transmission line VLv overlapping the third pixel aperture OP3 may be equally spaced apart from the second imaginary line CL2 by the second distance d2. Similarly, the boundary of the second driving voltage line PL2 and the boundary of the third driving voltage line PL3 overlapping the third pixel aperture OP3 may be equally spaced apart from the second imaginary line CL2 by the third distance d3.

[0168] The fifth conductive layer 1700 is a conductive layer located below the first to third pixel electrodes 210a, 210b, and 210c, and unevenness may be formed on the first to third pixel electrodes 210a, 210b, and 210c by the fifth conductive layer 1700. In the display device according to the embodiment of the present invention, the wiring overlapping with each of the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3 has an axisymmetric shape, which may reduce a deviation in brightness for each pixel according to the user's viewing angle (the angle between the direction perpendicular to the screen and the line of sight).

[0169] In a plan view, the first data line DL1 may be disposed at a distance from the first pixel opening OP1 and the second pixel opening OP2 so as not to overlap with the first pixel opening OP1 and the second pixel opening OP2. In a plan view, the second data line DL2 ... third pixel opening OP3 so as to overlap with the third pixel opening OP3. A portion of the second data line DL2 overlapping with the third pixel opening OP3 may be symmetrical with a portion of the vertical voltage transmission line VLv overlapping with the third pixel opening OP3, with respect to a second imaginary straight line CL2. The third data line DL3 may be disposed at a distance from the third pixel opening OP3 so as not to overlap with the pixel opening.

[0170] The intermediate layer 220 may be disposed on the pixel defining layer 110. The intermediate layer 220 may include a first light-emitting layer (not shown), a second light-emitting layer 222b, and a third light-emitting layer 222c. The first light-emitting layer, the second light-emitting layer 222b, and the third light-emitting layer 222c may each include a polymer or small molecule organic material that emits light of a predetermined color. In one embodiment, the first light-emitting layer may be patterned to correspond to the first pixel electrode 210a, the second light-emitting layer 222b may be patterned to correspond to the second pixel electrode 210b, and the third light-emitting layer 222c may be patterned to correspond to the third pixel electrode 210c.

[0171] The intermediate layer 220 may include a first functional layer 221 disposed below the first light-emitting layer, the second light-emitting layer 222b, and the third light-emitting layer 222c, and a second functional layer 223 disposed on the first light-emitting layer, the second light-emitting layer 222b, and the third light-emitting layer 222c. The first functional layer 221 may be a hole transport layer. Alternatively, the first functional layer 221 may include a hole injection layer and a hole transport layer. The second functional layer 223 may include an electron transport layer and / or an electron injection layer. The first functional layer 221 and the second functional layer 223 may be integrally formed to correspond to a plurality of organic light-emitting diodes (OLEDs). The first functional layer 221 or the second functional layer 223 may be omitted.

[0172] In one embodiment, the intermediate layer 220 may include two or more sequentially stacked light-emitting units and a charge generation layer disposed between the two light-emitting units. When the intermediate layer 220 includes two or more light-emitting units and a charge generation layer, the organic light-emitting diode OLED may be a tandem light-emitting device. The organic light-emitting diode OLED may have a stacked structure of multiple light-emitting units, thereby improving color purity and luminous efficiency.

[0173] One light-emitting unit may include an emissive layer and functional layers below and above the emissive layer. The charge-generating layer may include a negative charge-generating layer and a positive charge-generating layer. The negative charge-generating layer and the positive charge-generating layer may further increase the luminous efficiency of the organic light-emitting diode (OLED), which is a tandem light-emitting element.

[0174] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metal material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metal material.

[0175] A counter electrode 230 may be disposed on the intermediate layer 220. The counter electrode 230 may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), indium tin oxide (ITO), indium zinc oxide (IZO), or any combination thereof. The counter electrode 230 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The counter electrode 230 may be integrally formed to correspond to multiple organic light-emitting diodes (OLEDs).

[0176] When the organic light-emitting diode OLED is a tandem light-emitting element, the functional layer included in the intermediate layer 220 may have a relatively high conductivity. In one embodiment, the display device 10 may include a separator SEP for reducing leakage current between adjacent organic light-emitting diodes OLED. For example, the pixel defining film 110 may define auxiliary openings OPs surrounding a portion of the first pixel opening OP1, a portion of the second pixel opening OP2, and a portion of the third pixel opening OP3. The auxiliary openings OPs may function as separators SEP. The auxiliary openings OPs may be spaced apart from the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3. As shown in FIG. 18B , the side surfaces of the pixel defining film 110 that define the auxiliary openings OPs may have an inverse tapered shape. That is, the side surfaces of the pixel defining film 110 that define the auxiliary openings OPs may have an undercut structure.

[0177] The common layers integrally formed corresponding to the plurality of organic light emitting diodes OLED, for example, the first functional layer 221, the second functional layer 223, and the counter electrode 230, may be separated by separators SEP or may have discontinuous portions that are thinner than the surrounding regions. For example, as shown in FIG. 18B, the first functional layer 221, the second functional layer 223, and the counter electrode 230 disposed on the upper surface of the pixel defining (defining) film 110 may be separated and spaced apart from a dummy layer dm disposed on the bottom surface of the auxiliary opening OPs. However, because the separators SEP do not completely surround each of the first pixel opening OP1, the second pixel opening OP2, and the third pixel opening OP3, the counter electrodes 230 may be integrally formed and connected to each other in the display area DA (see FIG. 1A).

[0178] An encapsulation layer (not shown) may be disposed on the organic light emitting diode OLED. The encapsulation layer may include at least one inorganic film layer and at least one organic film layer.

[0179] Although the present invention has been described with reference to the embodiments shown in the drawings, it will be understood that these are merely examples, and that those skilled in the art will recognize that various modifications and equivalent embodiments are possible. Therefore, the true technical scope of protection of the present invention should be determined by the technical spirit of the claims.

[0180] According to a preferred specific embodiment, it is as follows:

[0181] The background and issues of this case are as follows (i) to (v).

[0182] (i) In a display panel in which light-emitting elements such as organic light-emitting diodes (OLEDs) are arranged in a matrix, a circuit (pixel circuit) for controlling brightness and the like is arranged for each pixel (sub-pixel).

[0183] (ii) Each pixel circuit typically includes transistors such as a drive transistor (the first transistor T1 of the present application (DT in Patent Documents 1 and 2)) that supplies a drive current to the light-emitting element (ED), a write transistor (the second transistor T2) that receives a data signal from the data line (DL), a diode-connected transistor (the third transistor T3 (ST3)) that establishes a diode connection with the drive transistor (the first transistor T1 (DT)) when writing a data signal to the gate electrode (N1) of the drive transistor (the first transistor T1 (DT)), an initialization transistor (the fourth transistor T4 (ST4)) that supplies an initialization voltage to the gate electrode (N1) of the drive transistor (the first transistor T1 (DT)), a first light-emitting control transistor (the fifth transistor T5 (ST5)) that controls the supply of a drive current from the drive voltage line (PL) to the drive transistor (the first transistor T1 (DT)), and a second light-emitting control transistor (the sixth transistor T6 (ST6)) that controls the supply of a drive current from the drive transistor (the first transistor T1 (DT)) to the light-emitting element (ED), as well as a storage capacitor (Cst).

[0184] (iii) In a typical example, the data lines (DL) and the driving voltage lines (PL) extending parallel thereto are disposed on the upper layer side (light emitting element layer side) of the circuit layer (backplane).

[0185] (iv) In a typical example, island-shaped or strip-shaped connecting electrodes (1640a to 1640c in the present application, the third connecting electrode BE3 (

[0163] , Figures 10 to 11) in Patent Document 1, and the fourth connecting electrode BE4 (

[0181] , Figures 10 to 11) in Patent Document 2) for connecting transistors to each other or between a transistor and a storage capacitor (Cst) are arranged on the upper side of the circuit layer (backplane).

[0186] (v) Patent Document 1 also discloses that the data lines (DL) and connecting electrodes (third connecting electrodes BE3 in Patent Document 1) are arranged so as not to overlap with the pixel light-emitting areas (EA1 to EA3).

[0187] In a specific embodiment of the present application, the present invention is based on at least a part of the following A1 to A3 or A1 to A8, and at least one of the following A9 to A16.

[0188] A1 Wide driving voltage lines (PL1 to PL3) extending in the data line direction (y direction) are provided for each data line (data lines DL1 to DL3) (FIG. 14 of the present application). A driving voltage supply line (horizontal voltage transmission wiring 1610) extending in the scanning line direction (x direction) is provided for each scanning line (scan line GCL) (FIG. 13 of the present application). In addition, the drive voltage line (PL) in the data line direction (y direction) and the drive voltage supply line (horizontal voltage transmission wiring 1610) in the scanning line (scan line GCL) direction are stacked with one or more insulating layers (second interlayer insulating layer 107) in between, and are connected by contact holes (CNT14) provided for one or more pixels. (Figs. 16 and 13-14 of the present application)

[0189] A2 Island-shaped connecting electrodes (1640a to 1640c in the present application) that form the drain electrode (N3) of the driving transistor (TFT1), the source electrode (N3) of the diode-connected transistor (third transistor T3), and the source electrode (N3) of the second light-emitting control transistor (sixth transistor T6 (ST6)) are provided in the pixel area. (Figures 4-5 of the present application)

[0190] A3 The island-shaped connecting electrodes (1640a to 1640c in the present invention) are arranged in the same layer as the driving voltage supply lines (horizontal voltage transmission wiring 1610) in the scanning line (scan line GCL) direction. Furthermore, the data lines (DL) are arranged in the same layer as the driving voltage lines (PL1 to PL3). (Figures 13 and 16 of the present application)

[0191] A4: The areas (PCA1, PCA2, PCA3) for arranging pixel circuits of each primary color are arranged in stripe-shaped areas extending in the data line direction (y direction). (Figures 17 and 19 of the present application)

[0192] A5 In the case of a display panel using organic light-emitting elements (OLEDs), the light-emitting areas of the red and green pixels (and pixel electrodes 210a, 210b) are arranged alternately in the data line direction (y direction) so as to overlap the arrangement area (PCA1) of the pixel circuit of the red pixel. Furthermore, the light-emitting regions of the blue pixels (and pixel electrodes 210c) are arranged in the data line direction (y direction) along the boundary line between the arrangement region (PC2A) of the green pixel circuits and the arrangement region (PCA3) of the blue pixel circuits. (Figure 15 of the present application)

[0193] A6 The width (dimension in the scanning line direction) of the pixel circuit arrangement areas (PCA1, PCA2, PCA3) is constant, but the width of the drive voltage lines (PL1 to PL3) arranged within these areas is largest in the arrangement area (PCA1) of the pixel circuits of red pixels, and partially extends slightly beyond both edges. In contrast, the width of the drive voltage lines (PL2 to PL3) in the arrangement area (PCA2) of the pixel circuits of green pixels and in the arrangement area (PCA3) of the pixel circuits of blue pixels is significantly smaller than the width of the pixel circuit arrangement areas (PCA2, PCA3), for example, less than half. (Figure 14 of the present application)

[0194] A7 In the arrangement area (PCA2) of the green pixel circuit, red and green data lines (DL1, DL2) are arranged on either side of the drive voltage line (PL2) (Fig. 14 of the present application).

[0195] A8: In the pixel circuit arrangement area (PCA3) for blue pixels, a blue data line (DL3) and an additional drive voltage supply line (vertical voltage transmission wiring VLv) in the data line direction are arranged on either side of the drive voltage line (PL3) (Fig. 14 of the present application).

[0196] A9 The island-shaped connecting electrode (1640b) for the green pixel is disposed between the driving voltage line (PL1) for the red pixel and the data line (DL1) for the red pixel, and is spaced apart from the red pixel data line DL1. In particular, in the arrangement area (PCA2) of the green pixel circuits, the data line (DL1) for the red pixels is arranged in a space formed away from the arrangement area (PCA1) of the pixel circuits for the red pixels. (Figs. 13-14 of the present application)

[0197] A10 The island-shaped connecting electrodes (1640a, 1640c) for red and blue pixels are arranged so that their entirety overlaps the corresponding driving voltage lines (PL1 and PL3). (Figs. 13-14 of the present application)

[0198] A11 The data line (DL1) for the red pixel is located in the arrangement area (PCA2) of the green pixel circuit, and is arranged so as not to overlap with, and be separated from, the light-emitting areas (and pixel electrodes 210a, 210b) of the red and green pixels. (Figs. 14-15 of the present application)

[0199] A12 The data line (DL3) for the blue pixel is located in the blue pixel circuit arrangement area (PCA3) and is arranged so as to not overlap with, but be separated from, the light-emitting areas of the red, green, and blue pixels (and pixel electrodes 210a, 210b, 210c). (Figs. 14-15 of the present application)

[0200] In the A13 green pixel circuit arrangement area (PCA2), the center lines of the red pixel drive voltage line (PL1) and the light-emitting areas of the red and green pixels (and pixel electrodes 210a, 210b) overlap. The center lines here are lines that extend equally in the scanning line direction. (Figs. 18A-18B of the present application)

[0201] A14 The green data line (DL2) and the additional data line direction drive voltage supply line (vertical voltage transmission wiring VLv) are arranged close to but spaced apart from each other, on either side of the boundary line between the green pixel circuit arrangement area (PCA2) and the blue pixel circuit arrangement area (PCA3). (Figs. 18A-18B of the present application)

[0202] A15 The center line of the area sandwiched between the green data line (DL2) and the additional data line direction driving voltage supply line (vertical voltage transmission wiring VLv) coincides with the center line (the line dividing the light-emitting area of ​​the blue pixel (and pixel electrode 210c) in the scanning line direction) of the blue pixel. In particular, these center lines are located on the boundary between the arrangement area (PCA2) of the green pixel circuits and the arrangement area (PCA3) of the blue pixel circuits (FIGS. 18A and 18B).

[0203] A16 A groove (separator SEP) that separates the common electrode layer is disposed so as to surround the red and green light emitting regions, leaving a part of the periphery of each region. On the other hand, for the blue light emitting region, a groove (separator SEP) is arranged which extends in the data line direction and separates the common electrode layer so as to leave a part of it. [Explanation of symbols]

[0204] 10 Display device 100 boards 1100 First semiconductor layer 1200 First conductive layer 1300 Second conductive layer 1400 Second semiconductor layer 1500 Third conductive layer 1600 4th conductive layer 1700 5th conductive layer 1800 6th conductive layer

Claims

1. a first pixel circuit and a second pixel circuit disposed on a substrate and adjacent to each other in a first direction; a first conductive layer disposed above the first pixel circuit and the second pixel circuit, the first conductive layer including a first data line connected to the first pixel circuit, a second data line connected to the second pixel circuit, a first voltage line overlapping the first pixel circuit, and a second voltage line overlapping the second pixel circuit; Each of the first pixel circuit and the second pixel circuit is a first transistor including a first semiconductor pattern and a first gate electrode on the first semiconductor pattern; a second transistor including a second semiconductor pattern disposed on the first semiconductor pattern and a second gate electrode on the second semiconductor pattern; a connecting electrode connecting one terminal of the first transistor and one terminal of the second transistor, In a plan view, a connecting electrode of the second pixel circuit is disposed between the first voltage line and the first data line.

2. a second conductive layer disposed on the first conductive layer, the second conductive layer including a first pixel electrode connected to the first pixel circuit and a second pixel electrode connected to the second pixel circuit; a pixel defining film disposed on the second conductive layer and defining a first pixel opening overlapping the first pixel electrode and a second pixel opening overlapping the second pixel electrode; The display device according to claim 1 , wherein the first data line is disposed apart from the first pixel opening and the second pixel opening in a plan view.

3. The display device according to claim 2 , wherein the first pixel opening and the second pixel opening overlap the first voltage line.

4. The display device according to claim 3 , wherein the part of the first voltage line overlapping the first pixel aperture is symmetrical with respect to an imaginary straight line passing through the center of the first pixel aperture.

5. a third pixel circuit disposed on the substrate and adjacent to the second pixel circuit in the first direction; The display device of claim 2 , wherein the first conductive layer further comprises a third data line connected to the third pixel circuit and a third voltage line overlapping the third pixel circuit.

6. the second conductive layer further includes a third pixel electrode connected to the third pixel circuit; the pixel defining layer further defines a third pixel opening overlapping the third pixel electrode; The display device of claim 5 , wherein the second data line overlaps the third pixel opening.

7. the first conductive layer further includes a first voltage transmission wiring extending in a second direction intersecting the first direction and overlapping the third pixel opening; 7. The display device according to claim 6, wherein the portion of the second data line and the portion of the first voltage transmission wiring that overlap with the third pixel opening are symmetrical with respect to a virtual straight line that passes through the center of the third pixel opening.

8. Each of the first pixel circuit and the second pixel circuit a conductive pattern disposed on the first gate electrode; The display device according to claim 1 , wherein the conductive pattern of the second pixel circuit extends to a region where the first data line and a drain region of the first transistor of the second pixel circuit overlap.

9. 10. The display device of claim 8, further comprising a third conductive layer disposed on the conductive pattern and including the first voltage line, the second voltage line, and a second voltage transmission wiring connected to the conductive pattern.

10. The display device of claim 1 , wherein the first semiconductor pattern includes a silicon-based semiconductor material, and the second semiconductor pattern includes an oxide-based semiconductor material.

11. a first semiconductor layer disposed on a substrate and including a first semiconductor pattern and a second semiconductor pattern disposed adjacent to each other in a first direction; a first conductive layer disposed on the first semiconductor layer; a second conductive layer disposed on the first conductive layer and including a conductive pattern; a second semiconductor layer disposed on the second conductive layer and including a third semiconductor pattern and a fourth semiconductor pattern; a third conductive layer disposed on the second semiconductor layer; a fourth conductive layer disposed on the third conductive layer, the fourth conductive layer including a first connecting electrode connecting the first semiconductor pattern and the third semiconductor pattern and a second connecting electrode connecting the second semiconductor pattern and the fourth semiconductor pattern; a fifth conductive layer disposed on the fourth conductive layer, the fifth conductive layer including a first voltage line, a first data line, a second voltage line, and a second data line, which are sequentially disposed along the first direction; the first data line is connected to the first semiconductor pattern, the second data line is connected to the second semiconductor pattern, and in a plan view, the second connecting electrode is disposed between the first voltage line and the first data line.

12. a sixth conductive layer disposed on the fifth conductive layer and including a first pixel electrode and a second pixel electrode overlapping the first voltage line; a pixel defining film disposed on the sixth conductive layer and defining a first pixel opening overlapping the first pixel electrode and a second pixel opening overlapping the second pixel electrode; The display device according to claim 11 , wherein the first data line is disposed apart from the first pixel opening and the second pixel opening in a plan view.

13. The display device according to claim 12 , wherein the part of the first voltage line overlapping the first pixel aperture is symmetrical with respect to an imaginary line passing through the center of the first pixel aperture.

14. The display device according to claim 12 , wherein the part of the first voltage line overlapping the second pixel opening is symmetrical with respect to an imaginary line passing through the center of the first pixel opening.

15. the fifth conductive layer further includes a first voltage transmission line, a third voltage line, and a third data line, which are sequentially arranged from the second data line along the first direction; The display device of claim 12 , wherein the sixth conductive layer further includes a third pixel electrode overlapping the second voltage line, the second data line, the first voltage transmission wiring, and the third voltage line.

16. the pixel defining film further defines a third pixel opening overlapping the third pixel electrode; The display device of claim 15 , wherein the second data line and the first voltage transmission wiring overlap the third pixel opening.

17. 17. The display device of claim 16, wherein a portion of the second data line and a portion of the first voltage transmission wiring that overlap with the third pixel opening are symmetrical with respect to a virtual straight line that passes through the center of the third pixel opening.

18. The display device of claim 11 , wherein the conductive pattern extends in an area where the first data line and the second semiconductor pattern overlap.

19. 19. The display device of claim 18, wherein the fourth conductive layer further includes a second voltage transmission wiring connected to the first voltage line, the second voltage line, and the conductive pattern.

20. The display device of claim 11 , wherein the first semiconductor pattern includes a silicon-based semiconductor material, and the second semiconductor pattern includes an oxide-based semiconductor material.

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