Semiconductor unit, battery unit, and vehicle

Abstract

To detect a temperature of a transistor chip.SOLUTION: A semiconductor unit 41 comprises a semiconductor device 40, a control section 33, and a resistance section 36. In the semiconductor device 40, a second electrode pad and a control pad are provided on a front face of a transistor chip 42, and a first electrode pad is provided on a rear face of the transistor chip 42. An ON / OFF operation between the first electrode pad and the second electrode pad is performed in response to a voltage which is inputted to the control pad. There are included a first terminal which is electrically connected to the first electrode pad, a second terminal which is electrically connected to the second electrode pad, and a control terminal which is electrically connected to the control pad. The control section 33 is electrically connected to the control terminal and controls the transistor chip 42. The resistance section 36 is provided between the control terminal and the control section 33. The second electrode pad is separated into two regions in a center of the front face of the transistor chip 42. A temperature sensitive diode 80 is disposed between the two regions.SELECTED DRAWING: Figure 18

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor unit, a battery unit, and a vehicle. [Background technology]

[0002] For example, in an electrically powered vehicle such as a hybrid vehicle or an electric vehicle, as shown in Fig. 53, a relay unit 200 is provided between the positive electrode of a battery 210 and an inverter circuit 230 that controls a motor 220 that drives the electrically powered vehicle. The relay unit 200 includes a main relay 201, which is a mechanical contact type relay, and a pre-charge relay circuit 202 connected in parallel with the main relay 201 (see, for example, Patent Document 1). A capacitor 240 is provided between the relay unit 200 and the inverter circuit 230. The pre-charge relay circuit 202 is a circuit for preventing a rush current from flowing from the battery to the inverter circuit, and is a circuit in which a mechanical contact type relay 203 and a current limiting resistor 204 are connected in series. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-161009

[0004] [overview] When the pre-charge relay circuit 202 limits the inrush current from the battery 210 to the capacitor 240, most of the power consumption is consumed by the current limiting resistor 204. For this reason, in order to suppress the inrush current, it is necessary to use a current limiting resistor 204 with a large resistance value, and because the power consumption by this resistor is large, it is necessary to increase the size of the current limiting resistor 204.

[0005] Furthermore, the mechanical contact type main relay 201 and pre-charge relay circuit 202 themselves were large and heavy. In addition, when a high voltage and large current flowed, the contacts of the main relay 201 would weld together, making it impossible to cut off the current, arcing would occur, and there was a limit to the number of times it could be opened and closed, making it unreliable as a relay. Furthermore, the main relay 201 and pre-charge relay circuit 202 also had the problem of making noise when opening and closing.

[0006] Furthermore, in order to prevent a large current from flowing from the battery to the inverter circuit, it is necessary to detect the temperature of an element provided between the battery and the inverter circuit, which is caused by the large current flowing.

[0007] A semiconductor unit according to one embodiment of the present disclosure comprises a semiconductor device having a transistor chip with a second electrode pad and a control pad on the front surface thereof, a first electrode pad on the back surface thereof, and an on / off operation between the first electrode pad and the second electrode pad in response to a voltage input to the control pad, the semiconductor device having a first terminal electrically connected to the first electrode pad, a second terminal electrically connected to the second electrode pad, and a control terminal electrically connected to the control pad; a control unit electrically connected to the control terminal and controlling the transistor chip; and a resistor unit provided between the control terminal and the control unit, the second electrode pad being separated into two regions at the center of the front surface of the transistor chip, and a temperature-sensitive diode being disposed between the two regions. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram schematically showing a part of the electrical configuration of a vehicle equipped with a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram that schematically shows the electrical configuration of the relay unit and its periphery in FIG. [Figure 3A]FIG. 3A is a graph showing the relationship between the collector current flowing through the IGBT of the semiconductor device and the collector-emitter voltage during vehicle power running. [Figure 3B] FIG. 3B is a graph showing the relationship between the current flowing through the diode of the semiconductor device and the forward voltage during vehicle regeneration. [Figure 4A] FIG. 4A is a schematic cross-sectional view of the IGBT of the first embodiment. [Figure 4B] FIG. 4B is a schematic cross-sectional view of an IGBT of the comparative example. [Figure 5] FIG. 5 is a schematic cross-sectional view of a diode. [Figure 6] FIG. 6 is a perspective view of a semiconductor module including a semiconductor device. [Figure 7] FIG. 7 is a schematic plan view of a semiconductor module showing the layout of semiconductor devices. [Figure 8] FIG. 8 is a cross-sectional view of the semiconductor module taken along line 8-8 in FIG. [Figure 9] FIG. 9 is a bottom view of the semiconductor module. [Figure 10] FIG. 10 is a side view of the semiconductor unit. [Figure 11] FIG. 11 is a graph showing the transition of the collector-emitter voltage and the terminal voltage of the capacitor during precharge control in the first comparative example. [Figure 12] FIG. 12 is a graph showing the transition of the current flowing through the semiconductor module in the precharge control of the first comparative example. [Figure 13] FIG. 13 is a graph showing the transition of the collector-emitter voltage and the terminal voltage of the capacitor during precharge control in the second comparative example. [Figure 14] FIG. 14 is a graph showing the transition of the current flowing through the semiconductor module in the precharge control of the second comparative example. [Figure 15] FIG. 15 is a graph showing the transition of the collector-emitter voltage and the terminal voltage of the capacitor during the precharge control of the first embodiment. [Figure 16]FIG. 16 is a graph showing the transition of the current flowing through the semiconductor module during the precharge control of the first embodiment. [Figure 17] FIG. 17 is a circuit diagram of a semiconductor device of a comparative example. [Figure 18] FIG. 18 is a circuit diagram of a semiconductor unit according to the second embodiment. [Figure 19] FIG. 19 is a perspective view of a semiconductor module. [Figure 20] FIG. 20 is a schematic plan view of a semiconductor module showing the layout of semiconductor devices. [Figure 21] FIG. 21 is a plan view of an IGBT showing the arrangement of electrode pads of the IGBT. [Figure 22] FIG. 22 is a plan view of the diode showing the arrangement of the electrode pads of the diode. [Figure 23] FIG. 23 is a perspective cross-sectional view of an RC-IGBT, which is a semiconductor device according to the third embodiment. [Figure 24] FIG. 24 is a bottom view of the RC-IGBT. [Figure 25] FIG. 25 is a schematic plan view of a semiconductor module showing the layout of semiconductor devices. [Figure 26A] FIG. 26A is a graph showing the transition of the current flowing through the IGBT and diode of the RC-IGBT and the temperature of the RC-IGBT. [Figure 26B] Figure 26B is a comparative example in which the IGBT and the diode are formed separately, with the upper graph showing the current flowing through the IGBT and the temperature of the IGBT over time, and the lower graph showing the current flowing through the diode and the temperature of the diode over time. [Figure 27] FIG. 27 is a circuit diagram of a semiconductor unit according to the fourth embodiment. [Figure 28] FIG. 28 is a schematic plan view of a semiconductor module showing the layout of semiconductor devices. [Figure 29] FIG. 29 is a circuit diagram of a semiconductor unit according to the fifth embodiment. [Figure 30]FIG. 30 is a schematic plan view of a semiconductor module showing the layout of semiconductor devices. [Figure 31A] FIG. 31A is a graph showing the relationship between the magnitude of the powering current when it flows through an IGBT and a MOSFET and the voltage between the terminals of the semiconductor module. [Figure 31B] FIG. 31B is a graph showing the relationship between the current flowing through the diode of the semiconductor device and the forward voltage during vehicle regeneration. [Figure 32] FIG. 32 is a circuit diagram of a semiconductor unit according to the sixth embodiment. [Figure 33] FIG. 33 is a graph showing the transition of the gate drive signal of each IGBT. [Figure 34] FIG. 34 is a circuit diagram of a semiconductor unit according to a modified example. [Figure 35] FIG. 35 is a circuit diagram of a semiconductor unit according to a modified example. [Figure 36] FIG. 36 is a schematic plan view showing the layout of semiconductor devices in a semiconductor module according to a modified example. [Figure 37] FIG. 37 is a schematic plan view showing the layout of semiconductor devices in a semiconductor module according to a modified example. [Figure 38] 38 is a cross-sectional view of the semiconductor module taken along line 38-38 in FIG. [Figure 39] FIG. 39 is a schematic plan view of a semiconductor module according to a modified example. [Figure 40] FIG. 40 is a bottom view of an RC-IGBT of a semiconductor device according to a modified example. [Figure 41] FIG. 41 is a bottom view of an RC-IGBT of a semiconductor device according to a modified example. [Figure 42] FIG. 42 is a bottom view of an RC-IGBT of a semiconductor device according to a modified example. [Figure 43] FIG. 43 is a schematic plan view of a semiconductor module according to a modified example. [Figure 44] 44A and 44B are maps showing the relationship between the terminal voltage of the capacitor and the frequency during intermittent operation of the IGBT in the semiconductor unit of the modified example. [Figure 45] FIG. 45 is a map showing the relationship between the terminal voltage of the capacitor and the frequency during intermittent operation of the IGBT in the semiconductor unit of the modified example. [Figure 46] 46A and 46B are maps showing the relationship between the terminal voltage of the capacitor and the gate-emitter voltage of the IGBT in the semiconductor unit of the modified example. [Figure 47] FIG. 47 is a map showing the relationship between the terminal voltage of the capacitor and the gate-emitter voltage of the IGBT in the semiconductor unit of the modified example. [Figure 48] 48A and 48B are maps showing the relationship between the terminal voltage of the capacitor and the duty ratio of the IGBT in the semiconductor unit of the modified example. [Figure 49] FIG. 49 is a map showing the relationship between the terminal voltage of the capacitor and the duty ratio of the IGBT in the semiconductor unit of the modified example. [Figure 50] FIG. 50 is a schematic circuit diagram of a modified relay unit and its periphery. [Figure 51] FIG. 51 is a schematic circuit diagram of a modified relay unit and its periphery. [Figure 52] FIG. 52 is a block diagram that schematically shows a part of the electrical configuration of a vehicle according to a modified example. [Figure 53] FIG. 53 is a schematic circuit diagram of a conventional relay unit and its periphery.

[0009] [Detailed explanation] Hereinafter, embodiments of a semiconductor device, a semiconductor module, a semiconductor unit, a relay unit, a battery unit, and a vehicle will be described with reference to the drawings. The embodiments shown below are examples of configurations and methods for embodying technical ideas, and are not intended to limit the materials, shapes, structures, arrangements, dimensions, etc. of each component to those described below. Various modifications can be made to the following embodiments.

[0010] In this specification, "a state in which component A is connected to component B" includes a case in which component A and component B are directly physically connected, as well as a case in which component A and component B are indirectly connected via another component that does not affect the electrical connection state.

[0011] Similarly, "a state in which component C is provided between component A and component B" includes a case in which component A and component C, or component B and component C, are directly connected, as well as a case in which component A and component C, or component B and component C, are indirectly connected via another component that does not affect the electrical connection state.

[0012] (First embodiment) As shown in FIG. 1, a vehicle 1, which is an electrically powered vehicle such as a hybrid vehicle or an electric vehicle, includes a battery unit 20, a motor 11, an inverter circuit 12, and a capacitor 13. The motor 11 is connected to the inverter circuit 12. An example of the motor 11 is a three-phase AC motor. For example, a three-phase induction motor can be used as the three-phase AC motor. The inverter circuit 12 is electrically connected to the battery unit 20 by a high-voltage line HL and a low-voltage line LL. The inverter circuit 12 converts the output power of the battery unit 20 into AC power (for example, U-phase, V-phase, and W-phase AC power) that drives the motor 11. The capacitor 13 is provided between the battery unit 20 and the inverter circuit 12. The capacitor 13 is connected in parallel with the inverter circuit 12. An example of the capacitor 13 is a film capacitor or an electrolytic capacitor.

[0013] The battery unit 20 includes a battery module 21, which is an example of a battery made up of a plurality of battery cells, and a relay unit 30 that controls the flow of current from the battery module 21. The battery unit 20 is integrated by housing the battery module 21 and the relay unit 30 in a case (not shown). An example of a battery cell is a lithium-ion battery. The positive and negative electrodes of the battery module 21 are connected to the relay unit 30. The relay unit 30 is provided between the battery module 21 and the inverter circuit 12. More specifically, the relay unit 30 is provided in a portion between the battery module 21 and the capacitor 13 on the high-voltage side line HL and the low-voltage side line LL. A boost circuit may be provided between the relay unit 30 and the capacitor 13.

[0014] The relay unit 30 includes a first relay unit 31, a second relay unit 32, and a control circuit 33, which is an example of a control unit. The first relay unit 31 is provided on a high-voltage side line HL between the positive electrode of the battery module 21 and the inverter circuit 12, and the second relay unit 32 is provided on a low-voltage side line LL between the negative electrode of the battery module 21 and the inverter circuit 12.

[0015] The control circuit 33 controls each of the first relay unit 31 and the second relay unit 32. For example, when a start switch (main switch) of the vehicle 1 is turned on, the control circuit 33 turns on the first relay unit 31 and the second relay unit 32, and when the start switch is turned off, the control circuit 33 turns off the first relay unit 31 and the second relay unit 32. By turning on and off the first relay unit 31 and the second relay unit 32, the supply and cut-off of current from the battery module 21 to the inverter circuit 12 and the supply and cut-off of current from the inverter circuit 12 to the battery module 21 are controlled.

[0016] In the vehicle 1, during power running in which power is supplied from the battery module 21 to the motor 11 via the inverter circuit 12, an example of the magnitude of the current supplied from the battery module 21 to the inverter circuit 12 is 400 A. On the other hand, during regeneration in which the kinetic energy of the motor 11, such as during braking, is supplied as power to the battery module 21 via the inverter circuit 12, an example of the magnitude of the current supplied from the inverter circuit 12 to the battery module 21 is 400 A. In this way, the first relay unit 31 allows both the flow of current from the battery module 21 to the inverter circuit 12 and the flow of current from the inverter circuit 12 to the battery module 21.

[0017] FIG. 2 is a circuit diagram of the relay unit 30. As shown in FIG. The first relay section 31 provided in the high-voltage line HL includes a semiconductor module 40. The second relay section 32 provided in the low-voltage line LL is a mechanical contact relay. In the relay unit 30, the semiconductor module 40 and a gate control circuit 34 form a semiconductor unit 41.

[0018] The semiconductor module 40 includes a semiconductor device 40A. The semiconductor device 40A is provided between the positive electrode of the battery module 21 (see FIG. 1) and the inverter circuit 12 (see FIG. 1) electrically connected to the battery module 21.

[0019] The semiconductor device 40A includes an IGBT (Insulated Gate Bipolar Transistor) 42, which is an example of a transistor, and a diode 43 connected in anti-parallel to the IGBT 42. More specifically, the emitter of the IGBT 42 is connected to the anode of the diode 43, and the collector of the IGBT 42 is connected to the cathode of the diode 43.

[0020] The collector of the IGBT 42 is connected to the positive electrode of the battery module 21. That is, the collector of the IGBT 42 is an example of a first terminal connected to the positive electrode of the battery module 21 in the semiconductor device 40A. The emitter of the IGBT 42 is connected to the upper-stage switching element of the inverter circuit 12. That is, the emitter of the IGBT 42 is an example of a second terminal connected to the inverter circuit 12 in the semiconductor device 40A. The emitter of the IGBT 42 is also connected to a first terminal of the capacitor 13. The second terminal of the capacitor 13 is connected to the second relay unit 32.

[0021] The IGBT 42 is formed from a silicon (Si) device and is configured so that the withstand voltage between the collector and emitter in the off state is 600 V. The diode 43 is also formed from a silicon (Si) device and is configured so that the withstand voltage (reverse voltage VR) is 600 V. In other words, in this embodiment, the withstand voltage between the collector and emitter of the IGBT 42 is equal to the withstand voltage of the diode 43.

[0022] The control circuit 33 includes a gate control circuit 34 and a relay control circuit 35 . The gate control circuit 34 is electrically connected to the gate of the IGBT 42. The gate control circuit 34 generates a gate drive signal Sg, which is a voltage signal to be applied to the gate of the IGBT 42, and outputs it to the gate of the IGBT 42. The IGBT 42 operates based on the gate drive signal Sg.

[0023] The relay control circuit 35 is electrically connected to the second relay unit 32. The relay control circuit 35 generates a control signal Sr that controls the on / off of the second relay unit 32 and outputs it to the second relay unit 32. The second relay unit 32 performs an on / off operation based on the control signal Sr.

[0024] A current limiting resistor 36 is provided between the gate control circuit 34 and the semiconductor module 40. More specifically, the current limiting resistor 36 is provided between the gate control circuit 34 and the gate of the IGBT 42. The current limiting resistor 36 preferably has a resistance of 100 Ω or more. In this embodiment, the current limiting resistor 36 has a resistance of 500 Ω.

[0025] In the semiconductor module 40 configured as described above, current flows through the IGBT 42 when the vehicle 1 is powered, and current flows through the diode 43 when the vehicle 1 is regenerating. Fig. 3A shows an example of the relationship between the total collector current Ic flowing through the collector of the IGBT 42 when the vehicle 1 is powered and the collector-emitter voltage Vce of the IGBT 42. Fig. 3B shows an example of the relationship between the current If flowing through the diode 43 and the forward voltage Vf of the diode 43 when the vehicle 1 is regenerating.

[0026] [IGBT structure] The structure of the IGBT 42 will be described with reference to FIGS. 4A and 4B. 4A, the IGBT 42 is a trench-gate IGBT. The IGBT 42 includes an n-type semiconductor substrate 50. The semiconductor substrate 50 is, for example, a silicon substrate, and has a front surface 50A and a back surface 50B on the opposite side. A unit cell 51 that constitutes a part of the IGBT 42 is fabricated in the surface region of the semiconductor substrate 50.

[0027] The semiconductor substrate 50 is formed by, in order from the rear surface 50B side, + collector region 52, n +The semiconductor substrate 50 includes a p-type buffer region 53 and an n-type drift region 54. The collector region 52 and the buffer region 53 are formed in the back surface region of the semiconductor substrate 50. The collector region 52 is exposed from the back surface 50B of the semiconductor substrate 50. The collector region 52 contains B (boron) as a p-type impurity. The buffer region 53 is formed on the collector region 52 so as to be in contact with the collector region 52. The drift region 54 is formed using a portion of the semiconductor substrate 50. A portion of the drift region 54 is exposed from the front surface 50A of the semiconductor substrate 50 (not shown). The buffer region 53 and the drift region 54 each contain one of P (phosphorus), As (arsenic), or Sb (antimony) as an n-type impurity.

[0028] A plurality of gate trenches 55 are formed at intervals in the surface region of the semiconductor substrate 50. Each gate trench 55 penetrates the base region 59 and has a bottom located in the drift region 54. A gate electrode 57 is buried in each gate trench 55 via a gate insulating film 56. On the sides of the plurality of gate trenches 55, n-type trenches 55 are arranged in order from the front surface 50A side to the back surface 50B side of the semiconductor substrate 50. + type emitter region 58, p - A mold base region 59 and a drift region 54 are formed.

[0029] The base region 59 is shared by one gate trench 55 and the other gate trench 55. The emitter region 58 is formed along one side surface and the other side surface of the gate trench 55 so as to be exposed from the surface 50A of the semiconductor substrate 50. The emitter region 58 contains one of P (phosphorus), As (arsenic), and Sb (antimony) as an n-type impurity. The surface region of the base region 59 is provided with p-type impurities sandwiched between the emitter regions 58. + A p-type contact region 60 is formed in the base region 59. The base region 59 and the contact region 60 contain B (boron) as a p-type impurity.

[0030] The region between the emitter region 58 and the drift region 54 in the base region 59 is a channel region 61, which forms a plurality of unit cells 51 that constitute part of the IGBT 42. In the cross-sectional view of FIG. 4A , each unit cell 51 is defined as a region sandwiched between the center line of one gate trench 55 and the center line of the other gate trench 55.

[0031] An insulating film 62 made of, for example, silicon oxide (SiO2) is formed on the surface 50A of the semiconductor substrate 50 so as to cover the gate trench 55. A contact hole 62a is formed in the insulating film 62, exposing a part of the emitter region 58 and the contact region 60. An emitter electrode 63 made of, for example, aluminum (AlSiCu, AlCu, etc.) is formed on the insulating film 62. The emitter electrode 63 extends from above the insulating film 62 into the contact hole 62a and is electrically connected to the emitter region 58 and the contact region 60 within the contact hole 62a.

[0032] A collector electrode 64 made of, for example, aluminum (AlSiCu, AlCu, etc.) is formed on the back surface 50B of the semiconductor substrate 50. The collector electrode 64 is electrically connected to the collector region 52.

[0033] As described above, the IGBT 42 is turned on when the start switch is turned on, and therefore the number of times the IGBT 42 is switched is smaller than, for example, the number of times the switching elements of the inverter circuit 12 are switched on. The IGBT 42 used in this manner does not need to have a high operating speed. However, since the IGBT 42 is in the on state throughout the period from when the start switch (main switch) of the vehicle 1 is turned on until when it is turned off, it is preferable that the conduction loss of the IGBT 42 is small.

[0034] In view of this, the IGBT 42 reduces the conduction loss by adopting a structure that reduces the operating speed. The structure that reduces the conduction loss of the IGBT 42 will be described with reference to Figures 4A and 4B.

[0035] 4B shows the configuration of a comparative IGBT for comparison with the configuration of IGBT 42. The comparative IGBT differs in that a lattice defect layer 65 is formed and in the impurity concentration of collector region 52.

[0036] The lattice defect layer 65 is interposed between the drift region 54 and the buffer region 53. The lattice defect layer 65 is in contact with the drift region 54 and the buffer region 53. The lattice defect layer 65 is a high-resistance layer in which lattice defects are introduced by charged particles, and the resistivity (resistance value) is made higher than that of the collector region 52 and the buffer region 53. The charged particles are, for example, n-type impurities and argon (Ar).

[0037] When the charged particles are n-type impurities, the lattice defect layer 65 is a region where the n-type impurities exist without becoming donors. In other words, the lattice defect layer 65 is a high-resistance layer in which the lattice defects are not restored because the n-type impurities remain inactive after implantation, resulting in a high resistivity (resistance value). When the charged particles are argon (Ar), the lattice defect layer 65 is a high-resistance layer in which the lattice defect concentration is made higher than the lattice defect concentration in the buffer region 53, resulting in a high resistivity (resistance value). When protons (H + ) or helium (He) may be employed.

[0038] The comparative IGBT is capable of high-speed switching because the lattice defect layer 65 can control the lifetime of minority carriers, but conduction loss increases because the lattice defect layer 65 exists in the semiconductor substrate 50. In this regard, the IGBT 42 of the present embodiment does not have the lattice defect layer 65, so high-speed switching cannot be achieved, but conduction loss can be reduced.

[0039] The impurity concentration of the collector region 52 of the IGBT 42 is higher than that of the collector region 52 of the comparative IGBT. An example of the impurity concentration of the collector region 52 of the comparative IGBT is 1E+16 cm -3 The impurity concentration of the collector region 52 of the IGBT 42 is 1E+18 cm-3 In this embodiment, the impurity concentration of the collector region 52 of the IGBT 42 is preferably 1E+18 cm -3 is.

[0040] [Diode structure] Next, a description will be given of the configuration of the diode 43. FIG.

[0041] The diode 43 includes an n-type semiconductor substrate 70. The semiconductor substrate 70 is, for example, a silicon substrate, and has a front surface 70A and a back surface 70B on the opposite side. + Type region 71 and n - The semiconductor substrate 70 includes an n-type region 72. + On the type region 71, n - The n-type region 72 is formed by epitaxial growth. + Type region 71 and n - The n-type region 72 is a semiconductor region containing n-type impurities. Examples of the n-type impurities that can be contained include nitrogen (N), phosphorus (P), and arsenic (As). + The impurity concentration of the n-type region 71 is - The impurity concentration of the n-type region 72 is higher than that of the n-type region 73. + The thickness of the mold region 71 is n - The thickness of the mold region 72 is smaller than that of the mold region 72. + The thickness of the mold region 71 is n - It may be greater than or equal to the thickness of the mold region 72 .

[0042] n - A p-type region 73 is formed in the surface region of the p-type region 72. The p-type region 73 is a semiconductor region containing p-type impurities. For example, boron (B) can be used as the contained p-type impurity. In this embodiment, the impurity concentration of the p-type region 73 is increased to reduce the conduction loss of the diode 43. In one example, the impurity concentration of the p-type region 73 is 1E+17 cm -3 In this embodiment, the impurity concentration of the p-type region 73 is preferably 1E+17 cm-3 The semiconductor substrate 70 has a p-type region 73 and an n-type region 74. - A pn junction is formed between the semiconductor layer 71 and the semiconductor layer 72 .

[0043] An anode electrode pad 76 is formed on the front surface 70A of the semiconductor substrate 70. The anode electrode pad 76 is connected to the p-type region 73. A cathode electrode 77 is formed on the rear surface 70B of the semiconductor substrate 70. The cathode electrode 77 is connected to the n-type region 73 on the rear surface 70B of the semiconductor substrate 70. + It is connected to the mold region 71 .

[0044] [Configuration of Semiconductor Module 40] The configuration of the semiconductor module 40 will be described with reference to FIGS. 6 and 7, the semiconductor module 40 has a control terminal 45 protruding from a sealing resin 48 as an external terminal, a connection terminal 46 on the battery unit 20 (see FIG. 1) side, and a connection terminal 47 on the inverter circuit 12 (see FIG. 1) side. As shown in FIG. 7, the semiconductor module 40 modularizes an IGBT 42 and a diode 43 in a single package. The semiconductor module 40 includes a metal substrate 44. The semiconductor module 40 is formed to have a rectangular shape in a planar view. In the following description, the longitudinal direction of the semiconductor module 40 in a planar view is defined as a "first direction X," a direction perpendicular to the first direction X in a planar view is defined as a "second direction Y," and a direction perpendicular to both the first direction X and the second direction Y is defined as a "third direction Z."

[0045] As shown in FIG. 8, the metal substrate 44 is configured by laminating a heat sink 44a, an insulating substrate 44b, a first wiring portion 44c, and a second wiring portion 44d. The heat sink 44a is made of copper (Cu). As shown in Figures 8 and 9, the heat sink 44a is exposed from a bottom surface 48A of the sealing resin 48. The shape of the heat sink 44a in a plan view is a rectangle with its longitudinal axis extending in the first direction X. The heat sink 44a may be made of aluminum (Al), for example, or the heat sink 44a may be omitted and the insulating substrate 44b may be directly exposed.

[0046] The insulating substrate 44b is fixed to the heat sink 44a. The insulating substrate 44b is made of, for example, Si3N4. As shown in FIGS. 8 and 9, the insulating substrate 44b has a rectangular shape in a plan view with its longitudinal axis extending in the first direction X. The area of ​​the insulating substrate 44b in a plan view is larger than the area of ​​the heat sink 44a in a plan view. That is, the insulating substrate 44b protrudes from the heat sink 44a in at least one of the first direction X and the second direction Y. In this embodiment, the insulating substrate 44b protrudes from the heat sink 44a in both the first direction X and the second direction Y.

[0047] As shown in Fig. 8, the first wiring portion 44c and the second wiring portion 44d are fixed to an insulating substrate 44b. The first wiring portion 44c and the second wiring portion 44d are made of copper (Cu). The first wiring portion 44c and the second wiring portion 44d are electrically insulated from each other. As shown in Fig. 7, the first wiring portion 44c has a rectangular shape in a plan view with its longitudinal direction aligned in the first direction X.

[0048] A connection terminal 46 is connected to the end of the first wiring portion 44c opposite to the second wiring portion 44d in the first direction X. The connection terminal 46 is connected to the high-voltage side line HL on the battery module 21 side. That is, the connection terminal 46 is electrically connected to the positive electrode of the battery module 21. The connection terminal 46 is made of, for example, copper (Cu). The shape of the connection terminal 46 in a plan view is a rectangle with the long side extending in the first direction X.

[0049] A connection terminal 47 is connected to the second wiring portion 44d. The connection terminal 47 is connected to the high-voltage side line HL on the inverter circuit 12 side. That is, the connection terminal 47 is electrically connected to the inverter circuit 12. The connection terminal 47 is made of, for example, copper (Cu). The position of the connection terminal 47 in the second direction Y is the same as the position of the connection terminal 46 in the second direction Y. The shape of the connection terminal 47 in a plan view is a rectangle with its longitudinal direction in the first direction X, which is the same as the shape of the connection terminal 46.

[0050] The IGBT 42 and the diode 43 are mounted on the first wiring portion 44c of the metal substrate 44. The IGBT 42 and the diode 43 are provided as individual semiconductor chips. In the second direction Y, the diode 43 is disposed on the second wiring portion 44d side of the IGBT 42. The collector electrode 64 (see FIG. 4A) of the IGBT 42 is electrically connected to the first wiring portion 44c by a conductive material such as solder. The cathode electrode 77 of the diode 43 is electrically connected to the first wiring portion 44c by a conductive material such as solder.

[0051] An emitter electrode pad 66 and a gate electrode pad 67 are formed on the surface of the IGBT 42. An anode electrode pad 76a is formed on the surface of the diode 43. The emitter electrode pad 66 of the IGBT 42, the anode electrode pad 76a of the diode 43, and the second wiring portion 44d are electrically connected by a plurality of (six in FIG. 7) power wires 49a. In a plan view, the power wires 49a extend along the second direction Y. The power wires 49a are bonding wires made of, for example, aluminum (Al).

[0052] The emitter electrode pad 66, the gate electrode pad 67, and the anode electrode pad 76a are made of aluminum (Al), nickel (Ni), or the like. A first metal electrode layer (not shown) is formed on the emitter electrode pad 66, and a second metal electrode layer (not shown) is formed on the gate electrode pad 67. In addition, a third metal electrode layer (not shown) is formed on the anode electrode pad 76a.

[0053] The control terminal 45 in this embodiment is a gate terminal. The control terminal 45 is arranged on the opposite side of the IGBT 42 from the diode 43 in the second direction Y. The control terminal 45 is arranged apart from the first wiring portion 44c in the second direction Y. The control terminal 45 is electrically connected to the gate control circuit 34 (see FIG. 2).

[0054] The gate electrode pad 67 is formed on the surface of the IGBT 42 on the side of the control terminal 45. The gate electrode pad 67 and the control terminal 45 of the IGBT 42 are electrically connected by a control wire 49b. The control wire 49b is a bonding wire made of, for example, aluminum (Al).

[0055] As shown in FIGS. 6 and 10, each of the control terminals 45 is formed in an L-shape. As shown in FIG. 10, the control circuit 33 includes a control board 33a on which at least a gate control circuit 34 (see FIG. 2) is formed. The control board 33a may also include a relay control circuit 35 (see FIG. 2). The control board 33a is connected to the control terminals 45. The control board 33a faces the semiconductor module 40 across a gap in the third direction Z. More specifically, the control board 33a faces the top surface 48B of the sealing resin 48 of the semiconductor module 40, opposite the bottom surface 48A. In this manner, the semiconductor module 40 and the control circuit 33 (control board 33a) are assembled to form the semiconductor unit 41.

[0056] [Precharge] 1, 2, and 11 to 16, the control of the semiconductor module 40 when the start switch is turned on will be described.

[0057] If the start switch is turned on when the charge capacity of the capacitor 13 is zero or close to zero, an inrush current due to a potential difference between the battery module 21 and the capacitor 13 may flow to the semiconductor module 40 when power is supplied from the battery module 21 to the inverter circuit 12. Therefore, pre-charge control is executed to prevent the inrush current from flowing to the semiconductor module 40. In pre-charge control, when power supply from the battery module 21 to the inverter circuit 12 starts, the gate control circuit 34 limits the current flowing from the battery module 21 to the semiconductor module 40, thereby gradually charging the capacitor 13. The pre-charge control starts when the start switch (main switch) of the vehicle 1 is turned on, and ends when the voltage between the terminals of the capacitor 13 reaches or exceeds a threshold value. The threshold value is a voltage value for determining that the capacitor 13 is fully charged. An example of the threshold value is a voltage equal to or greater than 80% of the voltage of the battery module 21 (hereinafter referred to as "battery voltage VB").

[0058] When a start switch (main switch) of the vehicle 1 is turned on, the control circuit 33 causes the gate control circuit to generate a gate drive signal Sg and outputs it to the IGBT . In the precharge control, the gate control circuit 34 controls the IGBT 42 so that the capacitor 13 is gradually charged. Specifically, the gate control circuit 34 sets the voltage applied to the gate of the IGBT 42 to be lower than the voltage applied to the gate when the IGBT 42 is fully on. The voltage applied to the gate of the IGBT 42 in the precharge control is preferably a voltage slightly higher than the threshold voltage Vth of the IGBT 42. That is, in the precharge control, a current flows through the IGBT 42, but the voltage applied to the gate of the IGBT 42 is set so that the current is sufficiently smaller than the current that flows through the IGBT 42 when the IGBT 42 is fully on. In this embodiment, the voltage applied to the gate of the IGBT 42 when the IGBT 42 is fully on is 20 V, and the voltage applied to the gate of the IGBT 42 in the precharge control is 8 to 10 V. Furthermore, the gate control circuit 34 intermittently operates the IGBT 42 using intermittent control. The frequency of the intermittent operation of the IGBT 42 is preferably 1000 Hz or less. In this embodiment, the frequency of the intermittent operation of the IGBT 42 is 200 Hz. The duty ratio of the IGBT 42 is preferably less than 50%. In this embodiment, the duty ratio of the IGBT 42 is 5%.

[0059] After the precharge control is completed, the voltage across the capacitor 13 becomes a sufficiently high voltage equal to or higher than the threshold value, so that the gate control circuit generates a gate drive signal Sg that turns the IGBT fully on and outputs it to the IGBT .

[0060] The termination condition for the precharge control can be changed arbitrarily. For example, the precharge control may be terminated when a predetermined time has elapsed since the start of the precharge control. Here, the predetermined time is the time required for the charge capacity of the capacitor 13 to be charged from 0 to full charge through the precharge control, and is set in advance through testing or the like.

[0061] Next, the transitions of the terminal voltage of the capacitor 13, the voltage of the IGBT 42, and the current flowing through the semiconductor module 40 during precharge control will be described. The first comparison precharge control, which is a first comparative example, applies a voltage of 10 V to the gate of the IGBT 42 while maintaining the IGBT 42 in a constantly on state. The second comparison precharge control, which is a second comparative example, applies a voltage of 20 V to the gate of the IGBT 42 and operates the IGBT 42 intermittently. The second comparison precharge control operates the IGBT 42 intermittently through intermittent control. The frequency at which the IGBT 42 is intermittently operated is 10 kHz, and the duty ratio is 50%. In the first comparison precharge control and the second comparison precharge control, the current limiting resistor 36 provided between the gate control circuit 34 and the semiconductor module 40 is 50 Ω.

[0062] As shown in FIG. 11, in the first comparison precharge control, the collector-emitter voltage V CE gradually decreases, while the voltage VC across the terminals of the capacitor 13 increases. CE The voltage VC across the terminals of the capacitor 13 changes as a linear function.

[0063] 12, in the first comparison pre-charge control, a high current flows constantly through the semiconductor module 40 from the start of the control until the capacitor 13 is fully charged. In FIG. 11, a current of about 70 A at 400 V flows through the semiconductor module 40 for 3 msec, causing the temperature of the IGBT 42 to become excessively high.

[0064] As shown in FIG. 13, in the second comparison precharge control, the IGBT 42 is intermittently operated at high speed, so that the collector-emitter voltage V CE A surge voltage is generated between the collector and emitter. CEThe peak of V V gradually decreases over time from the start of the second comparison pre-charge control. On the other hand, the inter-terminal voltage VC of the capacitor 13 increases over time from the start of the second comparison pre-charge control.

[0065] As shown in Figure 14, during the second comparison pre-charge control, a large current flows intermittently through the semiconductor module 40 from the start of the control until the capacitor 13 is fully charged. The peak current during the second comparison pre-charge control gradually decreases over time. When the second comparison pre-charge control starts, a current exceeding 800 A flows through the high-voltage line HL. Because such a large current flows intermittently through the semiconductor module 40 and changes rapidly, the parasitic inductance in the circuit and the surge voltage generated by the current change increase. Furthermore, because the period during which no current flows through the IGBT 42 is short, the temperature of the IGBT 42 becomes excessively high.

[0066] In view of this problem, in this embodiment, the voltage applied to the gate of the IGBT 42 is reduced, and the IGBT 42 is intermittently operated slower than in the second comparison pre-charge control. In this case, as shown in FIG. 15, the collector-emitter voltage V CE decreases stepwise with the lapse of time from the start of the precharge control. On the other hand, the terminal voltage VC of the capacitor 13 increases stepwise with the lapse of time from the start of the precharge control of this embodiment.

[0067] As shown in Fig. 16, in the precharge control of this embodiment, current flows intermittently through the semiconductor module 40 over a period from the start of the control until the capacitor 13 is fully charged. The current flowing through the semiconductor module 40 is approximately 80 A to 100 A. That is, the magnitude of the current flowing through the semiconductor module 40 in the precharge control of this embodiment is sufficiently smaller than the magnitude of the current flowing through the semiconductor module 40 in the second comparative precharge control. Furthermore, because the period during which no current flows through the IGBT 42 is long, the IGBT 42 is cooled during this period during which no current flows. Therefore, the temperature of the IGBT 42 is prevented from becoming excessively high.

[0068] A first effect of the present embodiment will be described. Fig. 17 shows a semiconductor device 40X, which is a first relay unit, as an example for comparison with the semiconductor device 40A of the present embodiment. First, the configuration of the semiconductor device 40X, which is a comparative example, will be described.

[0069] The semiconductor device 40X includes MOSFETs 42x and 42y connected in series. Specifically, the drain of the MOSFET 42x is connected to the battery module 21, and the source of the MOSFET 42x is connected to the source of the MOSFET 42y. The drain of the MOSFET 42y is connected to the inverter circuit 12. The MOSFET 42x has a body diode 43x, and the MOSFET 42y has a body diode 43y. The body diode 43x has an anode at the source side of the MOSFET 42x and a cathode at the drain side of the MOSFET 42x. The body diode 43y has an anode at the source side of the MOSFET 42y and a cathode at the drain side of the MOSFET 42y. When a current flows from the battery module 21 to the inverter circuit 12 or from the inverter circuit 12 to the battery module 21, the MOSFETs 42x and 42y are simultaneously turned on, causing the current to flow through the MOSFETs 42x and 42y. That is, the semiconductor device 40X is capable of bidirectional conduction.

[0070] Furthermore, since the MOSFETs 42x and 42y are each formed of a silicon carbide (SiC) device, a high breakdown voltage and a low on-resistance can be simultaneously achieved. However, since the semiconductor device 40X has a configuration in which the MOSFET 42x and the MOSFET 42y are connected in series, the on-resistance becomes high and the cost of the semiconductor device 40X becomes high.

[0071] In view of this situation, in this embodiment, the semiconductor device 40A is composed of an IGBT 42 and a diode 43 connected in reverse to the IGBT 42, and therefore the number of transistor elements can be reduced compared to the semiconductor device 40X, thereby reducing costs.

[0072] Next, a second effect of this embodiment will be described. When the inverter circuit 12 is short-circuited, a large current flows from the battery module 21 to the inverter circuit 12. As a result, a large current also flows through the semiconductor module 40 provided between the battery module 21 and the inverter circuit 12.

[0073] Therefore, in order to prevent a large current from flowing from the battery module 21 to the inverter circuit 12, the IGBT 42 of the semiconductor module 40 is turned off when a large current flows from the battery module 21 to the inverter circuit 12. When the IGBT 42 is turned off, if the speed at which the IGBT 42 changes from the on state to the off state is fast, the magnitude of the current flowing through the IGBT 42 changes abruptly, resulting in the generation of a surge voltage.

[0074] Therefore, in this embodiment, the current limiting resistor 36 provided between the gate of the IGBT 42 and the gate control circuit 34 has a resistance value greater than that of a current limiting resistor provided between, for example, the gate of a switching element (e.g., an IGBT) of the inverter circuit 12 and the gate control circuit that controls the switching element. Specifically, the current limiting resistor 36 has a resistance of 100 Ω or more, and in this embodiment, a current limiting resistor 36 of 500 Ω is used. This slows down the speed at which the IGBT 42 changes from an ON state to an OFF state. This slows down the rate at which the current flowing through the IGBT 42 changes, thereby suppressing the occurrence of surge voltage.

[0075] According to this embodiment, the following effects can be further obtained. (1-1) The semiconductor device 40A is provided between the battery module 21 and the inverter circuit 12 and includes an IGBT 42 and a diode 43 reverse-connected to the IGBT 42. The collector of the IGBT 42 is connected to the positive electrode of the battery module 21, and the emitter of the IGBT 42 is connected to the inverter circuit 12. The withstand voltage of the semiconductor device 40A is equal to or higher than the battery voltage VB. This configuration allows the semiconductor device 40A to function as a main relay and a pre-charge relay circuit. That is, the current-limiting resistor for suppressing inrush current from the battery module 21, the mechanical contact relay of the pre-charge relay circuit, and the mechanical contact main relay can be omitted from the relay unit. This prevents problems such as welding of the contacts of the mechanical contact main relay, which makes it impossible to interrupt current, arc discharge, and reduced reliability as a relay due to a limited number of opening and closing cycles, as well as noise when the main relay and the pre-charge relay circuit open and close. This prevents reduced reliability and noise generation, while also reducing the size and weight of the relay unit 30.

[0076] Incidentally, when a mechanical contact type relay is provided on the high-voltage line HL through which a current of 400 A flows from the battery module 21 to the inverter circuit 12, the relay has a size of 100 mm or more in width, 60 mm or more in length, and 70 mm or more in height in a plan view of the relay. An example of the relay has a width of 111 mm, a length of 63 mm, and a height of 75 mm.

[0077] In this regard, the semiconductor module 40 including the semiconductor device 40A has a dimension of 60 mm or less in the first direction X, a dimension of 60 mm or less in the second direction Y, and a height dimension of 12 mm or less. Therefore, the first relay unit 31 can be made smaller than a mechanical contact type relay.

[0078] (1-2) In the semiconductor device 40A, during precharge control, the IGBT 42 operates intermittently, and the voltage applied to the gate of the IGBT 42 is lower than the voltage applied to the gate when the IGBT 42 is fully on. With this configuration, the current flowing from the battery module 21 to the capacitor 13 can be limited, thereby preventing a large current from flowing from the battery module 21 to the capacitor 13.

[0079] (1-3) In the semiconductor device 40A, during precharge control, the frequency when the IGBT 42 operates intermittently is 1000 Hz or less, and the duty ratio when the IGBT 42 operates intermittently is less than 50%. This configuration further limits the current flowing from the battery module 21 to the capacitor 13, thereby further preventing a large current from flowing from the battery module 21 to the capacitor 13. This therefore prevents a temperature rise in the IGBT 42. Furthermore, in the semiconductor device 40A of this embodiment, during precharge control, the duty ratio when the IGBT 42 operates intermittently is 5%. This therefore further prevents a large current from flowing from the battery module 21 to the capacitor 13.

[0080] (1-4) The current limiting resistor 36 provided between the gate of the IGBT 42 of the semiconductor device 40A and the gate control circuit 34 has a resistance of 100 Ω or more. This configuration slows down the speed at which the IGBT 42 changes from an ON state to an OFF state when it is turned off. This makes it possible to suppress the occurrence of surge voltages. Furthermore, the current limiting resistor 36 of this embodiment has a resistance of 500 Ω. This further reduces the occurrence of surge voltages.

[0081] (1-5) The IGBT 42 of the semiconductor device 40A has a structure in which the lattice defect layer 65 is not interposed between the buffer region 53 and the drift region 54. Therefore, the conduction loss of the IGBT 42 can be reduced compared to a structure in which the lattice defect layer 65 is formed in the IGBT 42.

[0082] (1-6) The impurity concentration in the collector region 52 of the IGBT 42 is increased to reduce the conduction loss of the IGBT 42. This reduces the loss in the IGBT 42 when a power current flows from the battery module 21 to the inverter circuit 12 or the capacitor 13.

[0083] (1-7) The impurity concentration of the p-type region 73, which serves as the anode region of the diode 43, is increased to reduce the conduction loss of the diode 43. This reduces the loss in the diode 43 when a regenerative current flows from the inverter circuit 12 to the battery module 21.

[0084] (Second embodiment) 18 to 22, a semiconductor unit 41 of the second embodiment will be described. The semiconductor unit 41 of the second embodiment differs from the semiconductor unit 41 of the first embodiment in that the semiconductor unit 41 detects the temperature and overcurrent of the IGBT 42. In the following description, components common to the semiconductor unit 41 of the first embodiment are denoted by the same reference numerals, and descriptions thereof may be omitted.

[0085] As shown in FIG. 18 , the IGBT 42 is provided with a temperature sensing diode 80 for detecting the temperature of the IGBT 42 and a current sense diode 81 for detecting the current flowing through the IGBT 42. The current sense diode 81 is provided so that the current sense ratio, which is the ratio of the current flowing from the current sense diode 81 to the current flowing from the emitter of the IGBT 42, is, for example, 1 / 1000. A sense resistor 83 is provided between the gate control circuit 34 and the current sense diode 81. The gate control circuit 34 is connected to both ends of the sense resistor 83 and detects the current flowing from the emitter of the IGBT 42 based on the current flowing through the sense resistor 83. The gate control circuit 34 turns the IGBT 42 off when the current flowing through the sense resistor 83 is equal to or greater than a threshold value.

[0086] The control circuit 33 includes a temperature detection circuit 37. The temperature detection circuit 37 is connected to the anode and cathode of the temperature sensing diode 80. More specifically, the temperature detection circuit 37 supplies a preset current to the temperature sensing diode 80 and measures the voltage across the temperature sensing diode 80 at that time. The temperature sensing diode 80 has a characteristic in which its threshold voltage decreases as its temperature increases. For this reason, for example, the temperature detection circuit 37 outputs a signal to the gate control circuit 34 when the voltage across the temperature sensing diode 80 reaches or exceeds a threshold value corresponding to the temperature threshold of the IGBT 42. Here, the temperature threshold is a temperature at which the IGBT 42 may fail, and is set in advance by testing or the like.

[0087] 19 and 20, the semiconductor module 40 includes five control terminals 45 connected to the IGBTs 42. As shown in Fig. 19, each control terminal 45 is bent into an L shape. Each control terminal 45 is electrically connected to the control circuit 33 (see Fig. 18).

[0088] 20, the IGBT 42 and the diode 43 are connected by six power wires 49a. The power wires 49a are connected to the second wiring portion 44d. The IGBT 42 is connected to five control terminals 45 by five control wires 49b.

[0089] FIG. 21 shows the electrode configuration of the IGBT 42. A guard ring 90 is formed on the outer periphery of the surface of the IGBT 42 opposite to the metal substrate 44 (see FIG. 20 ). A pair of emitter electrode pads 91A, 91B, a gate electrode pad 92, a temperature sensing diode 80, an anode electrode pad 93, a cathode electrode pad 94, a current sense 81, a current sense pad 95, and an emitter potential pad 96 are formed in a region Rg1 within the guard ring 90. A collector electrode (not shown) is formed on the back surface of the IGBT 42 facing the metal substrate 44. The emitter electrode pads 91A, 91B, the gate electrode pad 92, the anode electrode pad 93, the cathode electrode pad 94, the current sense pad 95, and the emitter potential pad 96 are provided with metal electrode layers similar to the first metal electrode layer of the emitter electrode pad 66 and the second metal electrode layer of the gate electrode pad 67 of the first embodiment.

[0090] The pair of emitter electrode pads 91A, 91B are electrically connected to the emitter electrode 63 (see FIG. 4A). A power wire 49a (see FIG. 20) is connected to each of the emitter electrode pads 91A, 91B. The emitter electrode pads 91A, 91B are arranged with a slight gap in the first direction X. Notches 97 are formed by cutting the emitter electrode pads 91A, 91B in the second direction Y on one side of the emitter electrode pads 91A, 91B in the second direction Y, i.e., on the side where the control terminal 45 (see FIG. 20) for the IGBT 42 is arranged. These notches 97 form regions that become recesses that are recessed in a direction (second direction Y) perpendicular to the arrangement direction. In the region surrounded by this region and the guard ring 90, a gate electrode pad 92, an anode electrode pad 93, a cathode electrode pad 94, a current sense pad 95, and an emitter potential pad 96 are arranged along the first direction X. Each of the gate electrode pad 92, the anode electrode pad 93, the cathode electrode pad 94, and the current sense pad 95 is connected to the control terminal 45 by a control wire 49b (see FIG. 20).

[0091] The gate electrode pad 92 is electrically connected to the gate electrode 57 (see FIG. 4A) and is electrically connected to the gate control circuit (see FIG. 18) via the control terminal 45 (see FIG. 20). The anode electrode pad 93 and the cathode electrode pad 94 are electrically connected to the temperature detection circuit 37 (see FIG. 18) via the control terminal 45. The current sense 81 is formed by a pattern separated from the emitter electrode 63 (see FIG. 4A) to which the emitter electrode pads 91A and 91B are connected, and is electrically connected to the current sense pad 95. The current sense pad 95 is electrically connected to the gate control circuit 34 via the control terminal 45. The emitter potential pad 96 serves as a reference voltage when generating the gate drive signal Sg. The emitter potential pad 96 is electrically connected to the gate control circuit 34 via the control terminal 45.

[0092] A recess 98 is formed in the emitter electrode pad 91B in a portion corresponding to the center of the surface of the IGBT 42, recessed in the first direction X so as to move away from the emitter electrode pad 91A. A temperature-sensitive diode 80 is formed in the recess 98. That is, the temperature-sensitive diode 80 is formed in the center of the surface of the IGBT 42. The temperature-sensitive diode 80 is also disposed between the two emitter electrode pads 91A and 91B. The area of ​​the temperature-sensitive diode 80 is smaller than the areas of the gate electrode pad 92, the anode electrode pad 93, the cathode electrode pad 94, the current sense pad 95, and the emitter potential pad 96. The temperature-sensitive diode 80 is electrically connected to the anode electrode pad 93 and the cathode electrode pad 94. More specifically, a wiring pattern is formed on the surface of the IGBT 42. The temperature-sensitive diode 80, the anode electrode pad 93, and the cathode electrode pad 94 are connected in series by the wiring pattern. As a result, the temperature sensitive diode 80 is electrically connected to the temperature detection circuit 37 (see FIG. 18).

[0093] FIG. 22 shows the electrode configuration of the diode 43. A guard ring 100 is formed on the outer periphery of the surface of the diode 43 opposite to the metal substrate 44 (see FIG. 20 ). An anode electrode pad 101 is formed in region Rg2 within the guard ring 100. A cathode electrode (not shown) is formed on the back surface of the diode 43 facing the metal substrate 44. A third metal electrode layer is formed on the anode electrode pad 101, similar to the anode electrode pad 76 of the first embodiment.

[0094] However, if the inverter circuit 12 is short-circuited, a large current flows from the battery module 21 to the inverter circuit 12. Therefore, a large current may also flow to the semiconductor module 40 provided between the battery module 21 and the inverter circuit 12.

[0095] Therefore, in order to prevent a large current from flowing from the battery module 21 to the inverter circuit 12, the control circuit 33 changes the IGBT 42 of the semiconductor module 40 from an ON state to an OFF state when a large current flows from the battery module 21 to the inverter circuit 12. In one example, when the temperature of the IGBT 42 becomes equal to or higher than a temperature threshold, that is, when the control circuit 33 receives a signal from the temperature detection circuit 37, the control circuit 33 changes the IGBT 42 from an ON state to an OFF state. More specifically, the control circuit 33 outputs a gate drive signal Sg (current reduction signal) to the gate of the IGBT 42 via the gate control circuit 34, which changes the IGBT 42 to an OFF state.

[0096] However, when the IGBT 42 is turned off, if the speed at which the IGBT 42 changes from an on state to an off state is fast, the magnitude of the current flowing through the IGBT 42 changes abruptly, resulting in the generation of a surge voltage. Therefore, in this embodiment, the current-limiting resistor 36 provided between the gate of the IGBT 42 and the gate control circuit 34 has a resistance greater than that of a current-limiting resistor provided between the gate of a switching element (e.g., an IGBT) of the inverter circuit 12 and a gate control circuit that controls the on / off of the switching element. Specifically, the resistance of the current-limiting resistor provided between the switching element and the gate control circuit is several ohms to several tens of ohms, while the resistance of the current-limiting resistor 36 is 100 ohms or greater. In this embodiment, a current-limiting resistor 36 with a resistance of 500 ohms is used. This reduces the speed at which the IGBT 42 changes from an on state to an off state. This slows down the rate at which the current flowing through the IGBT 42 changes, thereby suppressing the generation of a surge voltage.

[0097] According to this embodiment, the following effects can be obtained. (2-1) The IGBT 42 is provided with a current sensor 81 through which a current proportional to the current flowing from the emitter of the IGBT 42 flows. The gate control circuit 34 detects the current flowing through the IGBT 42 based on the current flowing through a sense resistor 83 connected to the current sensor 81. If the detected current is equal to or greater than a threshold, the gate control circuit 34 turns the IGBT 42 off. With this configuration, if an overcurrent flows through the IGBT 42, the IGBT 42 can be turned off and the current can be cut off. Therefore, compared to a mechanical contact type relay, the current can be cut off more reliably in a shorter time, eliminating the need for a fuse. Furthermore, compared to a mechanical contact type relay, the gate control circuit 34 can be made smaller.

[0098] (2-2) When the temperature of the IGBT 42 is equal to or higher than the temperature threshold, the IGBT 42 is turned off. With this configuration, when the temperature of the IGBT 42 rises due to a large current flowing through the IGBT 42, the current flowing through the IGBT 42 can be cut off.

[0099] (Third embodiment) 23 to 26B, a semiconductor unit 41 of the third embodiment will be described. The semiconductor unit 41 of the present embodiment is different from the semiconductor unit 41 of the second embodiment in the configuration of the semiconductor module 40. In the following description, components common to the configuration of the semiconductor unit 41 of the second embodiment will be denoted by the same reference numerals, and their description may be omitted.

[0100] 25 includes an RC (Reverse Conduction)-IGBT (Reverse Conduction Insulated Gate Bipolar Transistor) as a semiconductor device 40A including an IGBT 42 and a diode 43. The arrangement of the electrode pads of the RC-IGBT is the same as the arrangement of the electrode pads of the IGBT 42 of the second embodiment. Therefore, the electrode pads of the semiconductor device 40A are designated by the same reference numerals as those of the IGBT 42.

[0101] Fig. 23 shows an example of a cross-sectional structure of an RC-IGBT including an IGBT 42 and a diode 43 in a semiconductor module 40. As shown in Fig. 23, the IGBT 42 and the diode 43 are formed on the same semiconductor substrate 110. That is, the IGBT 42 and the diode 43 are integrated into a single chip.

[0102] As shown in FIG. 23, the surface layer of the semiconductor substrate 110 on the surface 110A side contains p - A n-type channel region 111 is formed on the back surface 110B side of the semiconductor substrate 110 relative to the channel region 111. - In this embodiment, an n-type drift region 112 is formed. - A semiconductor substrate of the same type is used as the semiconductor substrate 110 , and the drift region 112 is formed by utilizing a part of the semiconductor substrate 110 .

[0103] The semiconductor substrate 110 has a surface layer on the rear surface 110B side thereof, and a p + collector region 113 and n +An n-type cathode region 114 is formed in the drift region 112. In this embodiment, an n-type buffer region 115 is formed to extend between the drift region 112 and the collector region 113, and between the drift region 112 and the cathode region 114. The collector region 113 and the cathode region 114 are electrically connected to the drift region 112 via the buffer region 115. The collector region 113 and the cathode region 114 are formed to be exposed from the back surface 110B side of the semiconductor substrate 110.

[0104] The cathode region 114 is formed across the boundary between the collector region 113 and the buffer region 115. The end of the cathode region 114 on the front surface 110A side of the semiconductor substrate 110 is located within the buffer region 115.

[0105] A plurality of trench gate structures 116 extending in a band shape in plan view are formed in a surface layer portion on the front surface 110A side of the semiconductor substrate 110. Each trench gate structure 116 includes a gate electrode 119 embedded in a gate trench 117 formed by digging down into the semiconductor substrate 110, with a gate insulating film 118 sandwiched therebetween. The gate trench 117 penetrates the channel region 111 and has a bottom located within the drift region 112. In this embodiment, the gate insulating film 118 also covers the front surface 110A of the semiconductor substrate 110.

[0106] The surface layer of the channel region 111 on the side of each trench gate structure 116 is exposed from the surface 110A of the semiconductor substrate 110. + As a result, on the sides of each trench gate structure 116, n-type emitter regions 120 are formed in the order from the front surface 110A side to the back surface 110B side of the semiconductor substrate 110. + type emitter region 120, p - a channel region 111 of the n-type; -A drift region 112 of a type is formed in the gate trench 117. The channel region 111 is shared by a plurality of adjacent trench gate structures 116. A gate electrode 119 faces the emitter region 120, the channel region 111, and the drift region 112, with a gate insulating film 118 sandwiched therebetween, in a gate trench 117.

[0107] A plurality of contact recesses 121 are formed between the plurality of trench gate structures 116 in the surface layer portion of the channel region 111. Each contact recess 121 is formed in a strip shape in a plan view extending in the same direction as the plurality of trench gate structures 116. Each contact recess 121 is formed by digging down the surface layer portion on the surface 110A side of the semiconductor substrate 110 so that its bottom is located within the channel region 111. In the thickness direction of the semiconductor substrate 110, the depth of the contact recess 121 is smaller than the depth of the trench gate structure 116 (gate trench 117).

[0108] The emitter region 120 is exposed from the side of each contact recess 121. In this embodiment, a p-type impurity region having a p-type impurity concentration higher than the p-type impurity concentration of the channel region 111 is formed in the channel region 111 from below the emitter region 120 along the side and bottom of the contact recess 121. + The emitter region 120 may be exposed over the entire side of the contact recess 121, and the contact region 122 may be formed only along the bottom of the contact recess 121.

[0109] An insulating layer 123 is formed on the surface 110A of the semiconductor substrate 110 so as to cover the trench gate structure 116. The insulating layer 123 may have a multilayer structure in which a plurality of insulating films are stacked, or may have a single-layer structure made of a single insulating film. The insulating layer 123 may include, for example, an oxide film (SiO2) or a nitride film (SiN). Contact holes 124 are formed in the insulating layer 123 to expose the contact recesses 121 formed in the semiconductor substrate 110.

[0110] The contact hole 124 extends in a band shape in plan view in the same direction as the contact recess 121, and communicates with the contact recess 121 formed in the surface layer portion on the surface 110A side of the semiconductor substrate 110. The inner wall of the contact hole 124 is formed flush with the inner wall of the contact recess 121.

[0111] An emitter electrode 126 is formed on the insulating layer 123 via a barrier metal layer 125. The barrier metal layer 125 is a metal layer for preventing the emitter electrode 126 from diffusing outside the contact hole 124 and the contact recess 121. In this embodiment, the barrier metal layer 125 has a layered structure including a titanium layer and a titanium nitride layer stacked in this order from the semiconductor substrate 110 side. The surface of the barrier metal layer 125 facing the semiconductor substrate 110 and the back surface on the opposite side are formed along the inner wall of the contact recess 121, the inner wall of the contact hole 124, and the surface of the insulating layer 123 outside the contact hole 124.

[0112] The emitter electrode 126 is formed on the barrier metal layer 125 so as to fill the contact recess 121 and the contact hole 124 and cover the entire surface of the insulating layer 123. The emitter electrode 126 is electrically connected to the channel region 111, the emitter region 120, the contact region 122, etc. via the barrier metal layer 125 within the contact recess 121.

[0113] A collector electrode 127 is formed on the rear surface 110B of the semiconductor substrate 110 so as to be electrically connected to the collector region 113 and the cathode region 114. The diode 43 is formed by a pn junction between the channel region 111 and the drift region 112. The diode 43 includes the channel region 111 as an anode region. The diode 43 is electrically connected to the emitter electrode 126 via the channel region 111, and is electrically connected to the collector electrode 127 via the cathode region 114. As described above, the RC-IGBT of this embodiment has a configuration in which the anode of the diode 43 is electrically connected to the emitter electrode 126 of the IGBT 42, and the cathode of the diode 43 is electrically connected to the collector electrode 127 of the IGBT 42.

[0114] 24 shows the back surface 110B of the semiconductor substrate 110. In the following description, for convenience, one direction of the back surface 110B is defined as the "W direction," and the direction perpendicular to the W direction when the semiconductor substrate 110 is viewed from the back surface 110B is defined as the "V direction."

[0115] 24, a cathode region 114 (cross-hatched portion) and a collector region 113 are formed in a surface layer portion on the back surface 110B side of the semiconductor substrate 110. In this embodiment, the cathode region 114 has a higher n-type impurity concentration than the p-type impurity concentration of the collector region 113, and is formed so that the p-type impurity of the collector region 113 is offset by the n-type impurity.

[0116] The cathode region 114 is formed in a predetermined pattern. More specifically, the cathode region 114 has a line-shaped pattern that is continuously routed. Specifically, the cathode region 114 includes a plurality of first lines 114a and a plurality of second lines 114b. The plurality of first lines 114a extend along the W direction and are formed at intervals along the V direction. The plurality of second lines 114b extend along the V direction and connect the first lines 114a that are adjacent to each other in the W direction. The length in the W direction of some of the plurality of first lines 114a is shorter than the length in the W direction of the remaining plurality of first lines 114a. Some of the plurality of first lines 114a are located at the center in the V direction on the back surface 110B of the semiconductor substrate 110. The second lines 114b are arranged alternately in the V direction, with the second lines 114b connecting one end in the W direction of the first lines 114a adjacent in the V direction and the second lines 114b connecting the other end in the W direction of the first lines 114a adjacent in the V direction. In this embodiment, the cathode region 114 is not formed in a region corresponding to the region Rp where the gate electrode pad 92, the anode electrode pad 93, the cathode electrode pad 94, the current sense pad 95, and the emitter potential pad 96 (all see FIG. 21) are arranged.

[0117] The line width of the cathode region 114, defined by the width of the first lines 114a in the V direction and the width of the second lines 114b in the W direction, is, for example, 1 μm or more and 100 μm or less, more preferably 10 μm or more and 50 μm or less. The cathode region 114 may have a uniform line width as shown in FIG. 24, or may have a non-uniform line width (not shown). As an example of a non-uniform line width, for example, the line width of some of the multiple first lines 114a in the cathode region 114 may be different from the line width of the remaining multiple first lines 114a. Furthermore, the line width of some of the multiple second lines 114b in the cathode region 114 may be different from the line width of the remaining multiple second lines 114b.

[0118] FIG. 25 shows the layout of the semiconductor module 40 of this embodiment. The semiconductor device 40A as an RC-IGBT is mounted on a first wiring portion 44c formed on an insulating substrate 44b of the metal substrate 44. More specifically, a collector electrode 127 (see FIG. 23) of the semiconductor device 40A is electrically connected to the first wiring portion 44c by solder or the like.

[0119] The emitter electrode pads 91A, 91B and the second wiring portion 44d of the semiconductor device 40A are connected by power wires 49a. In one example, the number of power wires 49a is six.

[0120] The semiconductor device 40A is connected to five control terminals 45 by five control wires 49b. More specifically, the gate electrode pad 92, current sense pad 95, anode electrode pad 93, cathode electrode pad 94, and emitter potential pad 96 (all see FIG. 21) of the semiconductor device 40A are connected to the five control terminals 45 by the control wires 49b, respectively.

[0121] The operation of this embodiment will be described with reference to FIGS. 26A and 26B. The upper graph in FIG. 26A schematically illustrates the temperature of an RC-IGBT including an IGBT 42 and a diode 43 that constitute the RC-IGBT. The lower bar graph in FIG. 26A illustrates the transition of the absolute value of the current flowing through the RC-IGBT. In the lower graph in FIG. 26A, the hatched bars illustrate the current flowing through the diode 43 in the RC-IGBT, and the open bars illustrate the current flowing through the IGBT 42 in the RC-IGBT. The upper graph in FIG. 26B illustrates the transition of the temperature of the IGBT 42 when the IGBT 42 and the diode 43 are configured on separate semiconductor chips, and the upper bar graph in FIG. 26B illustrates the transition of the current flowing through the IGBT 42. The lower graph in FIG. 26B illustrates the transition of the temperature of the diode 43 when the IGBT 42 and the diode 43 are configured on separate semiconductor chips, and the lower bar graph in FIG. 26B illustrates the transition of the current flowing through the diode 43.

[0122] In a configuration in which a semiconductor element such as an IGBT or a diode is bonded to a bonding wire, temperature changes at the bonded portion between the semiconductor element and the bonding wire can cause the semiconductor element and the bonding wire to peel off. The possibility of peeling between the semiconductor element and the bonding wire increases as the number of repeated temperature changes at the bonded portion between the semiconductor element and the bonding wire increases. The relationship between the number of repeated temperature changes at the bonded portion between the semiconductor element and the bonding wire and peeling between the semiconductor element and the bonding wire is indicated as power cycle resistance. As the amount of temperature change at the bonded portion between the semiconductor element and the bonding wire increases, the number of repeated temperature changes at the bonded portion between the semiconductor element and the bonding wire before the semiconductor element and the bonding wire peel off decreases. In other words, as the amount of temperature change at the bonded portion between the semiconductor element and the bonding wire increases, the power cycle resistance decreases.

[0123] 26B, when a powering current flows from the battery module 21 to the inverter circuit 12, the powering current flows through the IGBT 42, causing the temperature of the IGBT 42 to rise, but no powering current flows through the diode 43, causing the temperature of the diode 43 to not rise. Also, when a regenerative current flows from the inverter circuit 12 to the battery module 21, the regenerative current flows through the diode 43, causing the temperature of the diode 43 to rise, but no regenerative current flows through the IGBT 42, causing the temperature of the IGBT 42 to not rise.

[0124] In this way, when a powering current flows and when a regenerative current flows, the temperature of the IGBT 42 repeatedly changes, and the temperature of the diode 43 also repeatedly changes. Furthermore, when a regenerative current flows, the temperature of the IGBT 42 drops, so the temperature change of the IGBT 42 increases. Furthermore, when a powering current flows, the temperature of the diode 43 drops, so the temperature change of the diode 43 increases. As a result, the power cycle resistance decreases.

[0125] In this regard, in the present embodiment, the IGBT 42 and the diode 43 are formed on the same semiconductor chip, and therefore the temperature of the RC-IGBT increases both when the temperature of the IGBT 42 increases and when the temperature of the diode 43 increases. Therefore, as shown in FIG. 26A , the temperature change of the RC-IGBT is small when a powering current flows and when a regenerative current flows. In addition, as long as a powering current and a regenerative current flow, temperature changes of the IGBT 42 and the diode 43 that affect the power cycle resistance are unlikely to occur, and the number of times that the temperature changes of the IGBT 42 and the diode 43 occur is reduced. Therefore, the RC-IGBT can be used for a long period of time.

[0126] According to this embodiment, the following effects can be obtained. (3-1) The IGBT 42 and the diode 43 are formed on the same semiconductor substrate 110. With this configuration, compared to when the IGBT 42 and the diode 43 are formed on separate semiconductor substrates, there is no need for a power wire to electrically connect the IGBT 42 and the diode 43. This simplifies the configuration of the semiconductor module 40. In addition, the temperature change of each semiconductor element is reduced, improving the reliability of the power cycle.

[0127] (Fourth embodiment) 27 and 28, a semiconductor unit 41 of the fourth embodiment will be described. The semiconductor unit 41 of the present embodiment differs from the semiconductor unit 41 of the second embodiment in the configurations of the semiconductor module 40 and the control circuit 33. In the following description, components common to the configuration of the semiconductor unit 41 of the second embodiment will be denoted by the same reference numerals, and their description may be omitted.

[0128] 27, a semiconductor device 40A of a semiconductor module 40 includes an IGBT 42 and an RB (Reverse Blocking)-IGBT 42rb (reverse blocking insulated gate bipolar transistor) connected in parallel to the IGBT 42. In one example, the emitter of the RB-IGBT 42rb is connected to the collector of the IGBT 42, and the collector of the RB-IGBT 42rb is connected to the emitter of the IGBT 42.

[0129] The gate of the IGBT 42 is connected to a current limiting resistor 36. The gate of the IGBT 42rb is connected to a current limiting resistor 36rb. In one example, the resistance value of the current limiting resistor 36 is equal to the resistance value of the current limiting resistor 36rb. The gate drive signal Sg from the gate control circuit 34 is supplied simultaneously to the gate of the IGBT 42 and the gate of the RB-IGBT 42rb via the current limiting resistors 36 and 36rb. Therefore, the IGBT 42 and the RB-IGBT 42rb operate synchronously, turning on and off simultaneously. The RB-IGBT 42rb has voltage resistance characteristics in both the forward and reverse directions. The resistance value of the current limiting resistor 36 may be different from the resistance value of the current limiting resistor 36rb.

[0130] As shown in FIG. 27, the RB-IGBT 42rb is provided with a temperature sensing diode 80rb for detecting the temperature of the RB-IGBT 42rb and a current sensor 81rb for detecting the current flowing through the RB-IGBT 42rb. The current sensor 81rb is provided so that the current sense ratio, which is the ratio of the current flowing from the current sensor 81rb to the current flowing from the emitter of the RB-IGBT 42rb, is, for example, 1 / 1000. A sense resistor 83rb is provided between the gate control circuit 34 and the current sensor 81rb. The gate control circuit 34 is connected to both ends of the sense resistor 83rb and detects the current flowing from the emitter of the RB-IGBT 42rb based on the voltage across the sense resistor 83rb. The gate control circuit 34 turns the RB-IGBT 42rb off when the voltage across the sense resistor 83rb is equal to or greater than a first threshold.

[0131] The control circuit 33 includes a temperature detection circuit 37rb. The temperature detection circuit 37rb is connected to the anode and cathode of the temperature-sensing diode 80rb. The temperature detection circuit 37rb supplies a predetermined current to the temperature-sensing diode 80rb and measures the voltage across the temperature-sensing diode 80rb at that time. The temperature detection circuit 37rb outputs the measured voltage across the temperature-sensing diode 80rb to the gate control circuit 34. The temperature-sensing diode 80rb has a characteristic in which its threshold voltage decreases as its temperature increases. Therefore, the temperature of the temperature-sensing diode 80rb, i.e., the temperature of the RB-IGBT 42rb, can be determined from the voltage across the temperature-sensing diode 80rb. For example, the temperature detection circuit 37rb outputs a signal to the gate control circuit 34 when the voltage across the temperature-sensing diode 80rb exceeds a threshold value corresponding to the temperature threshold of the IGBT 42rb. Here, the temperature threshold is a temperature at which the IGBT 42rb may fail and is set in advance through testing or the like.

[0132] In one example, when the voltage across the temperature sensing diode 80rb becomes equal to or greater than a threshold, the control circuit 33 switches the RB-IGBT 42rb from an ON state to an OFF state. More specifically, the control circuit 33 outputs a gate drive signal Sg (current reduction signal) that switches the RB-IGBT 42rb to an OFF state via the gate control circuit 34 to the gate of the RB-IGBT 42rb. In this way, in this embodiment, when the temperature of at least one of the IGBT 42 and the RB-IGBT 42rb becomes equal to or greater than a temperature threshold, the IGBT 42 and the RB-IGBTrb switch to an OFF state.

[0133] 28 shows the layout of the semiconductor module 40 of this embodiment. In the following description, the same components as those in the semiconductor module 40 of the second embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0134] 28, the shapes of the first wiring portion 44c and the second wiring portion 44d formed on the insulating substrate 44b of the metal substrate 44 are different from the first wiring portion 44c and the second wiring portion 44d of the second embodiment. The first wiring portion 44c and the second wiring portion 44d of the present embodiment have the same shape. In a plan view, the first wiring portion 44c and the second wiring portion 44d each include a rectangle whose longitudinal axis is in the first direction X.

[0135] The IGBT 42 is mounted on the first wiring portion 44c. The RB-IGBT 42rb is mounted on the second wiring portion 44d. The arrangement position of the IGBT 42 and the arrangement position of the RB-IGBT 42rb are different from each other in the first direction X. In one example, as shown in FIG. 28 , the IGBT 42 is arranged closer to the connection terminal 46 than the RB-IGBT 42rb in the first direction X.

[0136] The emitter electrode pads 91A, 91B of the IGBT 42 and the second wiring portion 44d are connected by power wires 49a. In one example, the number of power wires 49a is six. In one example, similar to the IGBT 42, the RB-IGBT 42rb has a collector electrode (not shown) formed on the surface (back surface) facing the first wiring portion 44c in the third direction Z, and emitter electrode pads 91rbA and 91rbB formed on the surface opposite the back surface in the third direction Z. Also, similar to the IGBT 42, a gate electrode pad 92, a temperature sensing diode 80rb, an anode electrode pad 93rb, a cathode electrode pad 94rb, a current sense 81rb, a current sense pad 95rb, and an emitter potential pad 96rb are formed on the surface of the RB-IGBT 42rb.

[0137] The emitter electrode pads 91rbA, 91rbB of the RB-IGBT 42rb and the first wiring portion 44c are connected by power wires 49c. In one example, the number of power wires 49c is six.

[0138] The semiconductor module 40 has control terminals 45A and 45B. Five of each of the control terminals 45A and 45B are provided. The control terminal 45A is electrically connected to the IGBT 42, and the control terminal 45B is electrically connected to the RB-IGBT 42rb. In the first direction X, the positions of the five control terminals 45A and the positions of the five control terminals 45B are different from each other. In one example, as shown in FIG. 28 , the five control terminals 45A are arranged closer to the connection terminal 46 than the five control terminals 45B in the first direction X. In the second direction Y, the control terminals 45A are arranged on the opposite side of the first wiring portion 44c from the side on which the second wiring portion 44d is arranged. The control terminals 45B are arranged on the opposite side of the second wiring portion 44d from the side on which the first wiring portion 44c is arranged in the second direction Y. The five control terminals 45B are arranged so as to overlap the RB-IGBT 42rb when viewed from the first direction X.

[0139] In the IGBT 42, as in the second embodiment, the gate electrode pad 92, current sense pad 95, anode electrode pad 93, cathode electrode pad 94, and emitter potential pad 96 are connected to five control terminals 45A by control wires 49b, respectively.

[0140] In the RB-IGBT 42rb, similar to the IGBT 42, the gate electrode pad 92rb, the current sense pad 95rb, the anode electrode pad 93rb, the cathode electrode pad 94rb, and the emitter potential pad 96rb are connected to five control terminals 45B by control wires 49d, respectively.

[0141] According to this embodiment, in addition to the effects of the second embodiment, the following effects can be obtained. (4-1) The RB-IGBT 42rb is provided with a current sensor 81rb through which a current proportional to the current flowing from the emitter of the RB-IGBT 42rb flows. The gate control circuit 34 detects the current flowing through the RB-IGBT 42rb based on the current flowing through a sense resistor 83rb connected to the current sensor 81rb. If the detected current is equal to or greater than a threshold, the RB-IGBT 42rb is turned off. With this configuration, if an overcurrent flows through the RB-IGBT 42rb, the RB-IGBT 42rb is turned off, thereby interrupting the current. Furthermore, compared to a mechanical contact type relay, this can be made smaller and can interrupt the current reliably in a short time.

[0142] (4-2) When the temperature of the RB-IGBT 42rb is equal to or higher than the temperature threshold, the RB-IGBT 42rb is turned off. With this configuration, when the temperature of the RB-IGBT 42rb rises due to a large current flowing through the RB-IGBT 42rb, the current flowing through the RB-IGBT 42rb can be cut off. In other words, the RB-IGBT 42rb can cut off the current even when there is an overcurrent or the temperature becomes excessively high, even for regenerative current.

[0143] (Fifth embodiment) 29 to 31B, a semiconductor unit 41 of the fifth embodiment will be described. The semiconductor unit 41 of the present embodiment is different from the semiconductor unit 41 of the first embodiment in the configuration of the semiconductor module 40. In the following description, components common to the configuration of the semiconductor unit 41 of the first embodiment will be denoted by the same reference numerals, and their description may be omitted.

[0144] As shown in FIG. 29, a semiconductor device 40A of a semiconductor module 40 of this embodiment includes an IGBT 42, a diode 43, and a MOSFET (metal-oxide-semiconductor field-effect transistor) 140. An example of the MOSFET 140 is a MOSFET formed on a semiconductor substrate of silicon carbide (SiC), a so-called wide-gap semiconductor. The MOSFET 140 of this embodiment is an N-channel MOSFET. The MOSFET 140 has a body diode 140a. The MOSFET 140 may also be a MOSFET formed from a nitride semiconductor such as gallium nitride (GaN).

[0145] In the semiconductor device 40A, a diode 43 is connected in anti-parallel to an IGBT 42, and a MOSFET 140 is connected in parallel. More specifically, the emitter of the IGBT 42 is connected to the anode of the diode 43 and the source of the MOSFET 140. The collector of the IGBT 42 is connected to the cathode of the diode 43 and the drain of the MOSFET 140.

[0146] The gate of the IGBT 42 and the gate of the MOSFET 140 are connected to the gate control circuit 34. A current limiting resistor 36 is provided between the gate of the IGBT 42 and the gate control circuit 34, and a current limiting resistor 36m is provided between the gate of the MOSFET 140 and the gate control circuit 34. The gate control circuit 34 outputs a gate drive signal Sg to the gate of the IGBT 42 and the gate of the MOSFET 140, respectively. The gate drive signal Sg is a signal common to the IGBT 42 and the MOSFET 140. Therefore, the IGBT 42 and the MOSFET 140 operate in synchronization based on the gate drive signal Sg.

[0147] FIG. 30 shows the layout of the semiconductor module 40 of this embodiment. 30, a first wiring portion 143, a second wiring portion 144, and two third wiring portions 170 and 171 are provided on an insulating substrate 44b of a metal substrate 44. In one example, the first wiring portion 143 and the second wiring portion 144 are arranged to face each other with a gap in between in the first direction X. A connection terminal 46 is connected to the first wiring portion 143, and a connection terminal 47 is connected to the second wiring portion 144. In one example, the third wiring portions 170 and 171 are arranged at positions overlapping with the connection terminal 46 when viewed from the second direction Y.

[0148] The IGBT 42, the diode 43, and the MOSFET 140 are arranged on the first wiring portion 143 with gaps in the second direction Y. The collector electrode 64 of the IGBT 42, the cathode electrode 77 of the diode 43, and the drain electrode of the MOSFET 140 are electrically connected to the first wiring portion 143 by solder or the like.

[0149] The IGBT 42 has an emitter electrode pad 66 and a gate electrode pad 67. In this embodiment, the IGBT 42 does not have an anode electrode pad 93, a cathode electrode pad 94, a current sense pad 95, or an emitter potential pad 96, but may have these pads. The diode 43 has an anode electrode pad 76a. The MOSFET 140 has a source electrode pad 145 and a gate electrode pad 146. The emitter electrode pad 66 of the IGBT 42 and the second wiring portion 144 are connected by a power wire 147a, the anode electrode pad 76a of the diode 43 and the second wiring portion 144 are connected by a power wire 147b, and the source electrode pad 145 of the MOSFET 140 and the second wiring portion 144 are connected by a power wire 147c. In one example, the number of power wires 147a is four, the number of power wires 147b is two, and the number of power wires 147c is two.

[0150] The semiconductor module 40 has control terminals 149a and 149b. The gate and emitter of the IGBT 42 and the gate and source of the MOSFET 140 are electrically connected to the control terminals 149a and 149b. Specifically, the gate electrode pad 67 of the IGBT 42 is electrically connected to the third wiring portion 170 by a control wire 148a, and the gate electrode pad 146 of the MOSFET 140 is electrically connected to the third wiring portion 170 by a control wire 148b. The emitter electrode pad 66 of the IGBT 42 is electrically connected to the third wiring portion 171 by a control wire 148c, and the source electrode pad 145 of the MOSFET 140 is electrically connected to the third wiring portion 171 by a control wire 148d. The third wiring portion 170 is connected to the control terminal 149a by a control wire 148e, and the third wiring portion 171 is connected to the control terminal 149b by a control wire 148f.

[0151] Incidentally, the MOSFET 140 has a characteristic that it can pass a current in a voltage region where the collector-emitter voltage of the IGBT 42 is lower than the offset voltage. On the other hand, the current flowing through the MOSFET 140 is smaller than the current flowing through the IGBT 42. In addition, the increase in the current flowing through the MOSFET 140 with respect to an increase in the drain-source voltage of the MOSFET 140 is smaller than the increase in the current flowing through the IGBT 42 with respect to an increase in the collector-emitter voltage of the IGBT 42.

[0152] Furthermore, when the gate of MOSFET 140 is turned on, it serves as a path for a regenerative current to flow from the source to the drain. The reverse conduction characteristics of MOSFET 140 allow a current to flow at a voltage lower than the turn-on voltage of diode 43. Meanwhile, the current flowing in the reverse direction in MOSFET 140 is smaller than the current flowing in diode 43. In addition, the increase in the current flowing in the reverse direction in MOSFET 140 with respect to an increase in the source-drain voltage of MOSFET 140 is smaller than the increase in the current flowing in diode 43 with respect to an increase in the voltage across both terminals of diode 43.

[0153] When a powering current is supplied from the battery module 21 to the inverter circuit 12, the powering current flows through the IGBT 42 and the MOSFET 140. Fig. 31A shows the relationship between the magnitude of the powering current and the voltage between the terminals of the semiconductor module 40 when the powering current flows through the IGBT 42 and the MOSFET 140. The dashed line graph in Fig. 31A shows the transition of the current flowing through the MOSFET 140, the dashed line graph in Fig. 31A shows the transition of the current flowing through the IGBT 42, and the solid line graph in Fig. 31A shows the transition of the total current (powering current) of the MOSFET 140 and the IGBT 42.

[0154] 31A, when the collector-emitter voltage of the IGBT 42 is less than the offset voltage (0.7 V in FIG. 31A), a powering current flows through the MOSFET 140, but no powering current flows through the IGBT 42. When the collector-emitter voltage of the IGBT 42 becomes equal to or greater than the offset voltage, a powering current flows through the MOSFET 140, and in addition, a powering current flows through the IGBT 42.

[0155] When a regenerative current is supplied from the inverter circuit 12 to the battery module 21, the regenerative current flows through the diode 43 and also flows through the MOSFET 140. Fig. 31B shows the relationship between the magnitude of the regenerative current and the voltage between the terminals of the semiconductor module 40 when the regenerative current flows in the reverse direction through the diode 43 and the MOSFET 140. The dashed line graph in Fig. 31B shows the transition of the current flowing in the reverse direction through the MOSFET 140, the dashed-dotted line graph in Fig. 31B shows the transition of the current flowing through the diode 43a, and the solid line graph in Fig. 31B shows the transition of the total current (regenerative current) through the diode 43a and the MOSFET 140.

[0156] 31B, when the voltage across diode 43a is less than the rise voltage (0.7 V in FIG. 31B), a regenerative current flows through MOSFET 140, but not through diode 43a. When the voltage across diode 43a becomes equal to or greater than the rise voltage, a regenerative current flows through MOSFET 140, and also through diode 43a. In this way, by adding MOSFET 140 to semiconductor device 40A, conduction loss when the powering current and regenerative current are low can be reduced.

[0157] According to this embodiment, the following effects can be obtained. (5-1) The semiconductor device 40A includes an IGBT 42, a diode 43 connected in anti-parallel to the IGBT 42, and a MOSFET 140 connected in parallel to the IGBT 42. With this configuration, when a powering current is supplied from the battery module 21 to the inverter circuit 12, the powering current flows through the MOSFET 140 in a voltage region where the collector-emitter voltage of the IGBT 42 is less than the offset voltage. Furthermore, when a regenerative current is supplied from the inverter circuit 12 to the battery module 21, the regenerative current flows through the MOSFET 140 in a voltage region where the voltage is less than the rise voltage of the diode 43a. Therefore, the powering current can be supplied more quickly from the battery module 21 to the inverter circuit 12, and the regenerative current can be supplied more quickly from the inverter circuit 12 to the battery module 21.

[0158] (Sixth embodiment) 32 and 33, a semiconductor unit 41 of the sixth embodiment will be described. The semiconductor unit 41 of the present embodiment is different from the semiconductor unit 41 of the first embodiment in the configuration of the control circuit 33 and the control of the semiconductor unit 41. In the following description, components common to the configuration of the semiconductor unit 41 of the first embodiment are denoted by the same reference numerals, and their description may be omitted.

[0159] 32, a semiconductor unit 41 of this embodiment includes a first semiconductor device 40A, a second semiconductor device 40B, and a third semiconductor device 40C. The first semiconductor device 40A includes an IGBT 42a and a diode 43a, the second semiconductor device 40B includes an IGBT 42b and a diode 43b, and the third semiconductor device 40C includes an IGBT 42c and a diode 43c. The IGBTs 42a to 42c are connected in parallel. The diodes 43a to 43c are connected in parallel.

[0160] In the first semiconductor device 40A, a diode 43a is connected in antiparallel to the IGBT 42a. More specifically, the anode of the diode 43a is connected to the emitter of the IGBT 42a, and the cathode of the diode 43a is connected to the collector of the IGBT 42a.

[0161] In the second semiconductor device 40B, a diode 43b is connected in antiparallel to an IGBT 42b. More specifically, the anode of the diode 43b is connected to the emitter of the IGBT 42b, and the cathode of the diode 43b is connected to the collector of the IGBT 42b.

[0162] In the third semiconductor device 40C, a diode 43c is connected in antiparallel to an IGBT 42c. More specifically, the anode of the diode 43c is connected to the emitter of the IGBT 42c, and the cathode of the diode 43c is connected to the collector of the IGBT 42c.

[0163] The control circuit 33 includes a first gate control circuit 34A, a second gate control circuit 34B, and a third gate control circuit 34C. The first gate control circuit 34A is electrically connected to the gate of IGBT 42a, the second gate control circuit 34B is connected to the gate of IGBT 42b, and the third gate control circuit 34C is connected to the gate of IGBT 42c. Current limiting resistors 36 are provided between the first gate control circuit 34A and the gate of IGBT 42a, between the second gate control circuit 34B and the gate of IGBT 42b, and between the third gate control circuit 34C and the gate of IGBT 42c. The resistance values ​​of these three current limiting resistors 36 are equal to one another. The resistance value of the current limiting resistors 36 is preferably 100 Ω or greater. In this embodiment, the resistance value of the current limiting resistor 36 is 500 Ω.

[0164] The first gate control circuit 34A outputs a gate drive signal Sga to the gate of the IGBT 42a, the second gate control circuit 34B outputs a gate drive signal Sgb to the gate of the IGBT 42b, and the third gate control circuit 34C outputs a gate drive signal Sgc to the gate of the IGBT 42c. In this way, the IGBTs 42a to 42c can be individually controlled by the gate control circuits 34A to 34C.

[0165] As shown in FIG. 33 , in the precharge control of this embodiment, the timing at which the gate drive signal Sga is input to the gate of the IGBT 42a, the timing at which the gate drive signal Sgb is input to the gate of the IGBT 42b, and the timing at which the gate drive signal Sgc is input to the gate of the IGBT 42c are all different. Specifically, the gate drive signal Sga is first input to the gate of the IGBT 42a. After the IGBT 42a is again turned off, the gate drive signal Sgb is input to the gate of the IGBT 42b. After the IGBT 42b is again turned off, the gate drive signal Sgc is input to the gate of the IGBT 42c. After the IGBT 42c is again turned off, the gate drive signal Sga is input to the gate of the IGBT 42a. This cycle is repeated to perform the precharge control.

[0166] According to this embodiment, the following effects can be obtained. (6-1) The control circuit 33 individually controls each of the IGBTs 42a to 42c during precharge control. Specifically, the control circuit 33 applies voltages to the gates of the IGBTs 42a to 42c at different timings during precharge control. With this configuration, the timings at which current flows through the IGBTs 42a to 42c differ from one another, and therefore the timings at which heat is generated due to the current flowing through the IGBTs 42a to 42c differ from one another. This prevents the temperature of the IGBTs 42a to 42c from becoming excessively high during precharge control. In addition, because the IGBTs 42a to 42c are not driven by a single gate drive circuit, i.e., the IGBTs 42a to 42c are not simultaneously turned on and off, it is possible to prevent current from concentrating on one of the IGBTs 42a to 42c. Furthermore, compared to a semiconductor unit 41 consisting of one IGBT 42, the amount of current interrupted by each IGBT 42a to 42c is approximately one-third, and since each IGBT 42a to 42c does not turn on or off simultaneously, surge voltages do not overlap with each other, thereby reducing the surge voltage at the collector of each IGBT 42a to 42c.

[0167] (Variation) The above-described embodiments are merely examples of possible forms of the semiconductor device, semiconductor module, semiconductor unit, relay unit, battery unit, and vehicle according to the present invention, and are not intended to limit the forms thereof. In addition to the above-described embodiments, the semiconductor device, semiconductor module, semiconductor unit, relay unit, battery unit, and vehicle according to the present invention may also take the following modified forms, or a combination of at least two mutually consistent modified forms.

[0168] In the first to fifth embodiments, the number of IGBTs 42 in the semiconductor device 40A can be changed arbitrarily. For example, the semiconductor device 40A may have a plurality of IGBTs 42 connected in parallel. In this modification, the configuration of the control circuit 33 may be changed to the configuration of the control circuit 33 in the sixth embodiment.

[0169] The configuration of the semiconductor device 40A is not limited to the configurations of the above-described embodiments, and may be the configuration shown in FIG. 34 or FIG. As shown in FIG. 34 , the semiconductor device 40A includes a MOSFET 140 and a diode 43 connected in anti-parallel to the MOSFET 140. More specifically, the anode of the diode 43 is connected to the source of the MOSFET 140, and the cathode of the diode 43 is connected to the drain of the MOSFET 140. The source and drain of the MOSFET 140 are connected to the high-voltage line HL. The MOSFET 140 is, for example, an N-channel MOSFET. The drain of the MOSFET 140 serves as a first terminal of the semiconductor device 40A connected to the positive electrode of the battery module 21, and the source of the MOSFET 140 serves as a second terminal of the semiconductor device 40A connected to the inverter circuit 12. The gate of the MOSFET 140 is connected to the gate control circuit 34. The MOSFET 140 may be a MOSFET formed using a silicon (Si) semiconductor substrate, or may be a MOSFET formed using a silicon carbide (SiC) or gallium nitride (GaN) semiconductor substrate. The silicon (Si) MOSFET may have a superjunction structure. The gallium nitride (GaN) MOSFET may have a HEMT structure.

[0170] When a current flows from the battery module 21 toward the inverter circuit 12, the current flows through the MOSFET 140. On the other hand, when a current flows from the inverter circuit 12 toward the battery module 21, the current flows in the reverse direction of the diode 43 and each MOSFET 140, and through the body diode 140a.

[0171] 35, the semiconductor device 40A includes a MOSFET 140 having a body diode 140a. The source and drain of the MOSFET 140 are connected to the high-voltage side line HL. The gate of the MOSFET 140 is connected to the gate control circuit 34. The MOSFET 140 is, for example, an N-channel MOSFET. The drain of the MOSFET 140 serves as a first terminal of the semiconductor device 40A connected to the positive electrode of the battery module 21, and the source of the MOSFET 140 serves as a second terminal of the semiconductor device 40A connected to the inverter circuit 12.

[0172] When a current flows from the battery module 21 toward the inverter circuit 12, the current flows through the MOSFET 140. On the other hand, when a current flows from the inverter circuit 12 toward the battery module 21, the current flows in the reverse direction of the MOSFET 140 or through the body diode 140a.

[0173] 34 or 35, MOSFET 140 may have a current sense for detecting the current flowing through the MOSFET. A current proportional to the current flowing through the MOSFET flows through the current sense. In this case, the MOSFET having the current sense is preferably provided with a current sense pad 95.

[0174] 34 or 35, the MOSFET 140 may have a temperature-sensitive diode for detecting the temperature of the MOSFET. In this case, the MOSFET having the temperature-sensitive diode is preferably provided with an anode electrode pad 93 and a cathode electrode pad 94.

[0175] In the modification shown in FIG. 34 or FIG. 35, the configuration of the gate control circuit 34 may be changed to the configuration of the gate control circuit 34 in the sixth embodiment. The number of semiconductor devices in the semiconductor module 40 can be changed arbitrarily. In one example, the semiconductor module 40 has a plurality of semiconductor devices. In this case, the plurality of semiconductor devices are connected in parallel to each other.

[0176] FIG. 36 shows a configuration in which a semiconductor module 40 is made up of two semiconductor devices 40A and 40B. A first wiring portion 150 and a second wiring portion 151 are provided on the insulating substrate 44b of the metal substrate 44. The first wiring portion 150 and the second wiring portion 151 are arranged along the first direction X. A connection terminal 46 is connected to the end of the first wiring portion 150 on the side opposite to the side on which the second wiring portion 151 is arranged in the first direction X. A connection terminal 47 is connected to the second wiring portion 151.

[0177] The first wiring portion 150 is mounted with the IGBT 42a and diode 43a of the semiconductor device 40A and the IGBT 42b and diode 43b of the semiconductor device 40B. The IGBT 42a and the diode 43a are arranged at intervals from each other along the first direction X. The IGBT 42b and the diode 43b are arranged at intervals from each other along the first direction X. The IGBT 42a and the IGBT 42b are arranged at intervals from each other in the second direction Y. The diode 43a and the diode 43b are arranged at intervals from each other in the second direction Y.

[0178] The emitter electrode pad 66a of the IGBT 42a, the anode electrode pad 76a of the diode 43a, and the second wiring portion 151 are connected by a plurality of power wires 49a (six power wires 49a in FIG. 36). The emitter electrode pad 66b of the IGBT 42b, the anode electrode pad 76b of the diode 43b, and the second wiring portion 151 are connected by a plurality of power wires 49e (six power wires 49e in FIG. 36).

[0179] The semiconductor module 40 has two control terminals 45a and 45b. The control terminal 45a is electrically connected to a gate electrode pad 67a of the IGBT 42a by a control wire 49b. The control terminal 45b is electrically connected to a gate electrode pad 67b of the IGBT 42b by a control wire 49f.

[0180] In the semiconductor device 40A, a flat clip may be used instead of a power wire to connect the IGBT 42, the diode 43, and the second wiring portion 44d. Specifically, as shown in FIG. 37, a clip 152 is connected to the emitter electrode pad 66 of the IGBT 42, the anode electrode pad 76a of the diode 43, and the second wiring portion 44d. In one example, the clip 152 is made of copper (Cu). As shown in FIG. 38, the clip 152 has a first contact portion 153 for contacting the emitter electrode pad 66, a second contact portion 154 for contacting the anode electrode pad 76a, and a third contact portion 155 for contacting the second wiring portion 44d.

[0181] In the first embodiment, the semiconductor module 40 may have an emitter terminal 45x electrically connected to the emitter of the IGBT 42, in addition to the control terminal 45 electrically connected to the gate of the IGBT 42, as shown in Fig. 39 for example. The emitter terminal 45x is connected to the emitter electrode pad 66 of the IGBT 42 by a wire 49x. The shape of the emitter terminal 45x is the same as that of the control terminal 45, for example.

[0182] In the first embodiment, the arrangement of the control terminals 45 can be changed as desired. For example, in a plan view of the semiconductor module 40, the control terminals 45 may be arranged adjacent to either the connection terminal 46 or the connection terminal 47 in the second direction Y. Note that the control terminals 45 (45A, 45B) in the second to sixth embodiments can also be changed in the same way.

[0183] In the third embodiment, the layout of the cathode region 114 in the RC-IGBT of the semiconductor device 40A can be changed as desired. As an example, the layout of the cathode region 114 may be as shown in FIGS.

[0184] 40, the cathode region 114 of the first modified example, like the third embodiment, includes a plurality of first lines 114a extending along the W direction and spaced apart along the V direction, and a plurality of second lines 114b extending along the V direction and connecting adjacent first lines 114a in the V direction. In the cathode region 114 shown in FIG. 40, the lengths of the plurality of first lines 114a in the W direction are equal to each other. The lengths of the plurality of second lines 114b in the V direction are also equal to each other. As shown in FIG. 40, the cathode region 114 is formed on the back surface 110B of the semiconductor substrate 110, biased toward one side in the W direction relative to the region Rp.

[0185] 41, similar to the third embodiment, the cathode region 114 of the second modified example includes a plurality of first lines 114a extending along the W direction and formed at intervals along the V direction, and a plurality of second lines 114b extending along the V direction and connecting the plurality of first lines 114a adjacent in the V direction. In the cathode region 114 of the second modified example, the second lines 114b connect one end portion in the W direction of the plurality of first lines 114a adjacent in the V direction.

[0186] 42, in the third modified example, the region Rp is located at the center of the semiconductor substrate 110. The cathode region 114 of the third modified example is formed in a rectangular ring shape in plan view so as to surround the region Rp. The cathode region 114 of the third modified example includes a plurality of first lines 114a extending along the W direction and formed at intervals along the V direction, and a plurality of second lines 114b extending along the V direction and connecting the plurality of first lines 114a adjacent to each other in the V direction.

[0187] In the second to fourth embodiments, the order in which the gate electrode pad 92, the anode electrode pad 93, the cathode electrode pad 94, the current sense pad 95, and the emitter potential pad 96 of the IGBT 42 are arranged in the first direction X can be changed as desired.

[0188] In the second to fourth embodiments, the position of the temperature sensitive diode 80 of the IGBT 42 can be changed arbitrarily. In the second to fourth embodiments, either the temperature sensing diode 80 or the current sense 81 may be omitted from the IGBT 42. Also, the anode electrode pad 93 and the cathode electrode pad 94 may be omitted from an IGBT in which the temperature sensing diode 80 is omitted. Also, the current sense pad 95 may be omitted from an IGBT in which the current sense 81 is omitted.

[0189] In the fifth embodiment, the arrangement of the IGBT 42, the diode 43, and the MOSFET 140 in the semiconductor module 40 can be changed as desired. For example, as shown in Fig. 43, the IGBT 42 and the diode 43 may be arranged so that they overlap when viewed from the first direction X. In this case, the emitter electrode pad 66 of the IGBT 42, the anode electrode pad 76a of the diode 43, and the second wiring portion 144 are connected by a power wire 147a.

[0190] In the sixth embodiment, the first semiconductor device 40A may have the IGBT 42a and diode 43a configured as RC-IGBTs as in the third embodiment. The second semiconductor device 40B may have the IGBT 42b and diode 43b configured as RC-IGBTs as in the third embodiment. The third semiconductor device 40C may have the IGBT 42c and diode 43c configured as RC-IGBTs as in the third embodiment.

[0191] In each embodiment, the IGBTs 42, 42a to 42c may be planar gate IGBTs instead of trench gate IGBTs. In the sixth embodiment, the control circuit 33 may vary only one of the application timings of voltages to the gates of the IGBTs 42a to 42c. For example, the application timing of voltage to the gate of the IGBT 42b may be varied from the application timing of voltages to the gates of the IGBTs 42a and 42c. Because the IGBTs 42a and 42c are arranged with the IGBT 42b sandwiched between them, i.e., because the IGBTs 42a and 42c are spaced apart from each other, the thermal influence that the IGBTs 42a and 42c have on each other is small. Therefore, varying the application timing of voltage to the IGBT 42b can prevent the temperatures of the IGBTs 42a to 42c from becoming excessively high.

[0192] When the current flowing through the IGBT 42 becomes equal to or greater than a threshold value or when the temperature of the IGBT 42 becomes equal to or greater than a temperature threshold value, the control circuit 33 turns the IGBT 42 off. However, the method for turning the IGBT 42 off may be changed as follows (A1) or (A2).

[0193] (A1) The number and wire diameter of each of the power wires 49a are set so that the power wires 49a break when the current flowing through the IGBT 42 is equal to or greater than a threshold value. Meanwhile, the number and wire diameter of each of the power wires 49a are set within a range that does not excessively increase the conduction loss of the semiconductor module 40. The number and wire diameter of the power wires 49a are set so that the power wires 49a do not break even if a current flows for a certain period of time when the drive current and regenerative current are equal to or greater than the rated current but less than twice the rated current. The threshold value is preferably equal to or greater than two times the rated current but less than four times the rated current. An example of the rated current is the current that flows from the battery module 21 to the capacitor 13 when the battery module 21 is fully charged and the capacity of the capacitor 13 is zero. In one example, the number and wire diameter of the power wires 49a are set so that the power wires 49a break when a current twice the preset rated current flows for a certain period of time as the threshold value. Furthermore, for example, the number and diameter of the power wires 49a may be set so that the wire breaks when a current three times the rated current flows as a threshold for a certain period of time.

[0194] According to this configuration, when a large current flows from the battery module 21 toward the inverter circuit 12 and the large current flows through the semiconductor module 40, the power wire 49a breaks, cutting off the supply of the large current to the inverter circuit 12. This turns off the IGBT 42. Since the power wire 49a thus functions as a fuse, a fuse can be omitted.

[0195] The above modification of (A1) can also be applied to the configuration of the semiconductor unit 41 shown in Figures 34 and 35. In this case, instead of the IGBT 42, the number and diameter of the power wires connected to the MOSFET 140 are set so that the power wires are disconnected when the current flowing through the MOSFET 140 is equal to or greater than a threshold. The number and diameter of the power wires are set in the same way as the number and diameter of the power wires 49a in (A1) above.

[0196] (A2) The voltage applied to the gate of the IGBT 42 is set to be equal to or lower than the voltage at which the collector current Ic saturates at a predetermined current when a voltage is applied to the gate. That is, the control circuit 33 controls the voltage between the emitter and gate of the IGBT 42 to be equal to or lower than the voltage at which the current flowing through the IGBT 42 saturates at a predetermined current. An example of the voltage applied to the gate of the IGBT 42 that saturates the collector current Ic at a predetermined current is 10 V.

[0197] With this configuration, even if a large current flows from the battery module 21 toward the inverter circuit 12, only a current corresponding to the voltage applied to the gate of the IGBT 42 set as described above flows from the semiconductor module 40 to the inverter circuit 12. This prevents a large current from flowing through the inverter circuit 12 and causing the inverter circuit 12 to break down, making it possible to omit a fuse.

[0198] The above modification (A2) can also be applied to the configuration of the semiconductor unit 41 shown in Fig. 34 and Fig. 35. In this case, the voltage applied to the gate of the MOSFET 140 instead of the IGBT 42 is set to be equal to or lower than the voltage at which the drain current saturates at a predetermined current when a voltage is applied to the gate.

[0199] In the above modifications (A1) and (A2), the number of IGBTs 42 (the number of MOSFETs 140) can be changed arbitrarily. In one example, the semiconductor module 40 includes a plurality of IGBTs (a plurality of MOSFETs).

[0200] In each embodiment, the precharge control can be changed as in the following (B1) to (B6). Also, (B1) to (B6) can be combined with each other as long as there is no technical contradiction.

[0201] (B1) The control circuit 33 sets the frequency at which the IGBT 42 operates intermittently when the terminal voltage of the capacitor 13 is equal to or greater than the threshold Xc to be higher than the frequency at which the IGBT 42 operates intermittently when the terminal voltage of the capacitor 13 is less than the threshold Xc. Here, the threshold Xc is a value at which it can be determined that a large current caused by a potential difference between the battery module 21 and the capacitor 13 will not flow, and is set in advance by testing or the like. The control circuit 33 sets the frequency at which the IGBT 42 operates intermittently from the terminal voltage of the capacitor 13 using a map, function, or the like that is information indicating the relationship between the terminal voltage of the capacitor 13 and the frequency at which the IGBT 42 operates intermittently. FIG. 44(a) is a map that is a first example of information indicating the relationship between the terminal voltage of the capacitor 13 and the frequency at which the IGBT 42 operates intermittently. As shown in FIG. 44(a), in a region where the terminal voltage of the capacitor 13 is less than a threshold value Xc, the frequency at which the IGBT 42 operates intermittently is set to a first frequency f1, and in a region where the terminal voltage of the capacitor 13 is equal to or greater than the threshold value Xc, the frequency at which the IGBT 42 operates intermittently is set to a second frequency f2 that is higher than the first frequency f1. FIG. 44(b) is a map that is a second example of information indicating the relationship between the terminal voltage of the capacitor 13 and the frequency at which the IGBT 42 operates intermittently. As shown in FIG. 44(b), in a region where the terminal voltage of the capacitor 13 is less than the threshold value Xc, the frequency at which the IGBT 42 operates intermittently is set to the first frequency f1. In a region where the terminal voltage of the capacitor 13 is equal to or greater than the threshold value Xc and equal to or less than an upper limit value Xd that is greater than the threshold value Xc, the frequency at which the IGBT 42 operates intermittently increases as the terminal voltage of the capacitor 13 increases. In a region where the intermittent voltage of the capacitor 13 is equal to or higher than the threshold value Xd, the frequency at which the IGBT 42 operates intermittently is set to the second frequency f2. The threshold value Xd can be changed as desired within a range that is higher than the threshold value Xc and equal to or lower than the inter-terminal voltage when the capacitor 13 is fully charged.

[0202] 44(a), the charging speed of the capacitor 13 increases by intermittently operating the IGBT 42 at the second frequency f2. Also, according to the configuration using the map of FIG. 44(b), the charging speed of the capacitor 13 increases by intermittently operating the IGBT 42 at a frequency equal to or higher than the threshold value Xc. Therefore, compared to the case where the first frequency f1 is always maintained during precharge control to charge the capacitor 13, the capacitor 13 can be fully charged more quickly.

[0203] (B2) The control circuit 33 increases the frequency at which the IGBT 42 operates intermittently as the voltage across the capacitor 13 increases. The control circuit 33 sets the frequency at which the IGBT 42 operates intermittently from the voltage across the capacitor 13 using a map, function, or the like that is information indicating the relationship between the voltage across the capacitor 13 and the frequency at which the IGBT 42 operates intermittently. FIG. 45 is a map that is information indicating the relationship between the voltage across the capacitor 13 and the frequency at which the IGBT 42 operates intermittently in (B2). In a first example, as shown by the solid line in FIG. 45, the relationship between the voltage across the capacitor 13 and the frequency at which the IGBT 42 operates intermittently is represented by a linear function. In a second example, as shown by the dashed-dotted line in FIG. 45, the relationship between the voltage across the capacitor 13 and the frequency at which the IGBT 42 operates intermittently is represented by a quadratic function. In the second example, in a region where the terminal voltage of capacitor 13 is low, the frequency at which IGBT 42 operates intermittently is approximately the first frequency f1, and in a region where the terminal voltage of capacitor 13 is high, the frequency at which IGBT 42 operates intermittently increases rapidly as the terminal voltage increases.

[0204] According to this configuration, as the voltage across the terminals of the capacitor 13 increases, the intermittent operation of the IGBT 42 becomes faster, thereby increasing the charging speed of the capacitor 13. Therefore, compared to when the first frequency f1 is always maintained during precharge control to charge the capacitor 13, the capacitor 13 can be fully charged more quickly.

[0205] (B3) The control circuit 33 sets the voltage Vge applied to the gate of the IGBT 42 when the terminal voltage of the capacitor 13 is equal to or greater than the threshold Xc to be higher than the voltage Vge applied to the gate of the IGBT 42 when the terminal voltage of the capacitor 13 is less than the threshold Xc. The control circuit 33 sets the voltage Vge applied to the gate of the IGBT 42 from the terminal voltage of the capacitor 13 using a map, function, or the like that is information indicating the relationship between the terminal voltage of the capacitor 13 and the voltage Vge applied to the gate of the IGBT 42. FIG. 46(a) is a map that is a first example of information indicating the relationship between the terminal voltage of the capacitor 13 and the voltage Vge applied to the gate of the IGBT 42. As shown in FIG. 46(a), in a region where the terminal voltage of the capacitor 13 is less than the threshold Xc, the voltage Vge applied to the gate of the IGBT 42 is set to a first voltage Vge1. On the other hand, in a region where the inter-terminal voltage of the capacitor 13 is equal to or higher than the threshold value Xc, the voltage Vge applied to the gate of the IGBT 42 is set to a second voltage Vge2 that is higher than the first voltage Vge1. FIG. 46(b) is a map that is a second example of information showing the relationship between the inter-terminal voltage of the capacitor 13 and the voltage Vge applied to the gate of the IGBT 42. As shown in FIG. 46(b), in a region where the inter-terminal voltage of the capacitor 13 is lower than the threshold value Xc, the voltage Vge applied to the gate of the IGBT 42 is set to the first voltage Vge1. In a region where the inter-terminal voltage of the capacitor 13 is equal to or higher than the threshold value Xc and equal to or lower than the upper limit value Xd, the voltage Vge applied to the gate of the IGBT 42 increases as the inter-terminal voltage of the capacitor 13 increases. In a region where the inter-terminal voltage of the capacitor 13 is equal to or higher than the threshold value Xd, the voltage Vge applied to the gate of the IGBT 42 is set to the second voltage Vge2.

[0206] 46(a), the current flowing through the IGBT 42 increases when the second voltage Vge2 is applied to the gate of the IGBT 42, thereby increasing the charging speed of the capacitor 13. Furthermore, the current flowing through the IGBT 42 increases when the voltage is equal to or greater than the threshold value Xc, thereby increasing the charging speed of the capacitor 13. Therefore, the capacitor 13 can be fully charged more quickly than when the voltage applied to the gate of the IGBT 42 is always maintained at the first voltage Vge1 during precharge control to charge the capacitor 13.

[0207] (B4) The control circuit 33 increases the voltage Vge applied to the gate of the IGBT 42 as the voltage across the capacitor 13 increases. The control circuit 33 sets the voltage Vge applied to the IGBT 42 from the voltage across the capacitor 13 using a map, function, or the like that is information indicating the relationship between the voltage across the capacitor 13 and the voltage Vge applied to the gate of the IGBT 42. FIG. 47 is a map that is information indicating the relationship between the voltage across the capacitor 13 and the voltage Vge applied to the gate of the IGBT 42 in (B4). In a first example, as shown by the solid line in FIG. 47, the relationship between the voltage across the capacitor 13 and the voltage Vge applied to the gate of the IGBT 42 is represented by a linear function. In a second example, as shown by the dashed-dotted line in FIG. 47, the relationship between the voltage across the capacitor 13 and the voltage Vge applied to the gate of the IGBT 42 is represented by a quadratic function. In the second example, in a region where the inter-terminal voltage of the capacitor 13 is low, the voltage Vge applied to the gate of the IGBT 42 is approximately the first voltage Vge1, and in a region where the inter-terminal voltage of the capacitor 13 is high, the voltage Vge applied to the gate of the IGBT 42 increases rapidly as the inter-terminal voltage increases.

[0208] According to this configuration, the charging speed of the capacitor 13 increases by increasing the voltage applied to the gate of the IGBT 42 as the inter-terminal voltage of the capacitor 13 increases. Therefore, the capacitor 13 can be fully charged more quickly than when the voltage applied to the gate of the IGBT 42 is always maintained at the first voltage Vge1 during precharge control to charge the capacitor 13.

[0209] (B5) The control circuit 33 sets the duty ratio of the IGBT 42 when the terminal voltage of the capacitor 13 is equal to or greater than the threshold Xc to be higher than the duty ratio of the IGBT 42 when the terminal voltage of the capacitor 13 is less than the threshold Xc. The control circuit 33 sets the duty ratio of the IGBT 42 from the terminal voltage of the capacitor 13 using a map, function, or the like that is information indicating the relationship between the terminal voltage of the capacitor 13 and the duty ratio of the IGBT 42. FIG. 48(a) is a map that is a first example of information indicating the relationship between the terminal voltage of the capacitor 13 and the duty ratio of the IGBT 42. As shown in FIG. 48(a), in a region where the terminal voltage of the capacitor 13 is less than the threshold Xc, the duty ratio of the IGBT 42 is set to a first duty ratio D1, and in a region where the terminal voltage of the capacitor 13 is equal to or greater than the threshold Xc, the duty ratio of the IGBT 42 is set to a second duty ratio D2 that is higher than the first duty ratio D1. Fig. 48(b) is a map that is a second example of information indicating the relationship between the terminal voltage of the capacitor 13 and the duty ratio of the IGBT 42. As shown in Fig. 48(b), in a region where the terminal voltage of the capacitor 13 is less than the threshold Xc, the duty ratio of the IGBT 42 is set to a first duty ratio D1. In a region where the terminal voltage of the capacitor 13 is equal to or greater than the threshold Xc and equal to or less than an upper limit value Xd that is greater than the threshold Xc, the duty ratio of the IGBT 42 increases as the terminal voltage of the capacitor 13 increases. In a region where the terminal voltage of the capacitor 13 is equal to or greater than the threshold Xd, the duty ratio of the IGBT 42 is set to a second duty ratio D2.

[0210] 48(a), the duty ratio of the IGBT 42 is set to the second duty ratio D2, which increases the current flowing through the IGBT 42, thereby increasing the charging speed of the capacitor 13. Furthermore, the map of FIG. 48(b) is used, which increases the duty ratio of the IGBT 42 above the threshold Xc, thereby increasing the charging speed of the capacitor 13. Therefore, compared to when the duty ratio of the IGBT 42 is always maintained at the first duty ratio D1 during precharge control to charge the capacitor 13, the capacitor 13 can be fully charged more quickly.

[0211] (B6) The control circuit 33 increases the duty ratio of the IGBT 42 as the voltage across the capacitor 13 increases. The control circuit 33 sets the duty ratio of the IGBT 42 from the voltage across the capacitor 13 using a map, function, or the like that is information indicating the relationship between the voltage across the capacitor 13 and the duty ratio of the IGBT 42. FIG. 49 is a map that is information indicating the relationship between the voltage across the capacitor 13 and the duty ratio of the IGBT 42 in (B6). In a first example, as shown by the solid line in FIG. 49, the relationship between the voltage across the capacitor 13 and the duty ratio of the IGBT 42 is represented by a linear function. In a second example, as shown by the dashed dotted line in FIG. 49, the relationship between the voltage across the capacitor 13 and the duty ratio of the IGBT 42 is represented by a quadratic function. In the second example, in a region where the terminal voltage of the capacitor 13 is low, the duty ratio of the IGBT 42 is approximately the first duty ratio D1, and in a region where the terminal voltage of the capacitor 13 is high, the duty ratio of the IGBT 42 increases rapidly as the terminal voltage increases.

[0212] According to this configuration, the charge speed of the capacitor 13 increases by increasing the duty ratio of the IGBT 42 as the voltage across the terminals of the capacitor 13 increases. Therefore, the capacitor 13 can be fully charged more quickly than when the capacitor 13 is charged by always maintaining the duty ratio of the IGBT 42 at the first duty ratio D1 during precharge control.

[0213] In the above (B1) to (B6), the IGBT 42 is controlled by monitoring the terminal voltage of the capacitor 13, but this is not limiting and the IGBT 42 may be controlled based on the collector-emitter voltage of the IGBT 42, for example. In this case, the above controls (B1) to (B6) can be modified as shown in the following (C1) to (C6). Even if the above controls (B1) to (B6) are modified as shown in (C1) to (C6), the same effects as those of (B1) to (B6) can be obtained.

[0214] (C1) The control circuit 33 sets the frequency at which the IGBT 42 operates intermittently when the collector-emitter voltage of the IGBT 42 is below a threshold value to be higher than the frequency at which the IGBT 42 operates intermittently when the collector-emitter voltage of the IGBT 42 is equal to or higher than the threshold value. The control circuit 33 sets the frequency at which the IGBT 42 operates intermittently from the collector-emitter voltage of the IGBT 42 using a map, function, or the like that is information indicating the relationship between the collector-emitter voltage of the IGBT 42 and the frequency at which the IGBT 42 operates intermittently.

[0215] (C2) The control circuit 33 increases the frequency at which the IGBT 42 operates intermittently as the collector-emitter voltage of the IGBT 42 decreases. The control circuit 33 sets the frequency at which the IGBT 42 operates intermittently from the collector-emitter voltage of the IGBT 42 using a map, function, or the like, which is information indicating the relationship between the collector-emitter voltage of the IGBT 42 and the frequency at which the IGBT 42 operates intermittently.

[0216] (C3) The control circuit 33 sets the voltage Vge applied to the gate of the IGBT 42 when the collector-emitter voltage of the IGBT 42 is less than the threshold value to be higher than the voltage Vge applied to the gate of the IGBT 42 when the collector-emitter voltage of the IGBT 42 is equal to or greater than the threshold value. The control circuit 33 sets the voltage Vge applied to the gate of the IGBT 42 from the collector-emitter voltage of the IGBT 42 using a map, function, or the like that is information indicating the relationship between the collector-emitter voltage of the IGBT 42 and the voltage Vge applied to the gate of the IGBT 42.

[0217] (C4) The control circuit 33 increases the voltage Vge applied to the gate of the IGBT 42 as the collector-emitter voltage of the IGBT 42 decreases. The control circuit 33 sets the voltage Vge applied to the gate of the IGBT 42 from the collector-emitter voltage of the IGBT 42 using a map, function, or the like, which is information indicating the relationship between the collector-emitter voltage of the IGBT 42 and the voltage Vge applied to the gate of the IGBT 42.

[0218] (C5) The control circuit 33 sets the duty ratio of the IGBT 42 when the collector-emitter voltage of the IGBT 42 is less than the threshold value to be higher than the duty ratio of the IGBT 42 when the collector-emitter voltage of the IGBT 42 is equal to or greater than the threshold value. The control circuit 33 sets the duty ratio of the IGBT 42 from the collector-emitter voltage of the IGBT 42 using a map, function, or the like that is information indicating the relationship between the collector-emitter voltage of the IGBT 42 and the duty ratio of the IGBT 42.

[0219] (C6) The control circuit 33 increases the duty ratio of the IGBT 42 as the collector-emitter voltage of the IGBT 42 decreases. The control circuit 33 sets the duty ratio of the IGBT 42 from the collector-emitter voltage of the IGBT 42 using a map, a function, or the like, which is information indicating the relationship between the collector-emitter voltage of the IGBT 42 and the duty ratio of the IGBT 42.

[0220] In each embodiment, the configuration of the relay unit 30 can be changed as shown in (D1) and (D2) below. (D1) As shown in Fig. 50, the second relay section 32 is omitted from the relay unit 30. That is, the low-voltage side line LL directly connects the negative electrode of the battery module 21 and the lower-stage switching element of the inverter circuit 12.

[0221] (D2) As shown in FIG. 51 , the second relay section 32 includes a semiconductor module 40 including semiconductor devices having transistors such as IGBTs and MOSFETs instead of a mechanical contact relay. The relay unit 30 of this modification includes a positive-side semiconductor module provided between the positive electrode of the battery module 21 and the inverter circuit 12, and a negative-side semiconductor module provided between the negative electrode of the battery module 21 and the inverter circuit 12. The relay unit 30 of this modification can also be described as a relay unit including a positive-side semiconductor device provided between the positive electrode of the battery module 21 and the inverter circuit 12, and a negative-side semiconductor device provided between the negative electrode of the battery module 21 and the inverter circuit 12. The semiconductor module 40 of the second relay section 32 may have the same configuration as the semiconductor module 40 of the first relay section 31, or may have a different configuration from the semiconductor module 40. The semiconductor device of the second relay section 32 may have the same configuration as the semiconductor device 40A, or may have a different configuration from the semiconductor device 40A. The number of semiconductor devices in the semiconductor module of the second relay section 32 may be different from the number of semiconductor devices in the semiconductor module 40 of the first relay section 31.

[0222] In each embodiment, the semiconductor device, semiconductor module, and semiconductor unit are applied to the relay unit 30 provided between the battery module 21 and the inverter circuit 12, but the application of the semiconductor device, semiconductor module, and semiconductor unit is not limited to this. For example, as shown in Fig. 52, the semiconductor device, semiconductor module, and semiconductor unit of each embodiment may be applied to a plurality of relay units mounted on the vehicle 1.

[0223] 52 is configured to be able to charge the battery module 21 from a quick charging station SQC, which is an external power source. The vehicle 1 also includes a normal charging plug 4 and a DC / AC converter 5 electrically connected to the normal charging plug 4. For example, when the normal charging plug 4 is connected to a commercial AC power source, AC power supplied to the normal charging plug 4 is converted into DC power by the DC / AC converter 5 and charged to the battery module 21. In the vehicle 1 configured as described above, the semiconductor device, semiconductor module, and semiconductor unit according to each embodiment can be applied to relay units 161 and 162 provided between the battery module 21 and a connection port 160 of a charging plug (not shown) of the quick charging station SQC. The semiconductor device, semiconductor module, and semiconductor unit according to each embodiment can also be applied to relay units 163 and 164 provided between the DC / AC converter 5 and the battery module 21. The semiconductor device, semiconductor module, and semiconductor unit of each embodiment can also be applied to a relay section 165 provided between the battery module 21 and an in-vehicle device (for example, an accessory device 6) to which power is supplied from the battery module 21. Examples of the accessory device 6 are audio equipment and car navigation devices. In addition, in the modification shown in Fig. 52, by applying the semiconductor device of each embodiment to each of the relay sections 161 to 164, each of the relay sections 161 to 164 can also be integrated into a single package.

[0224] (Addendum) Next, the technical ideas that can be understood from the above-described embodiments and modifications will be described below. (Appendix A1) A semiconductor unit provided between a motor and an inverter circuit that controls the motor, the semiconductor unit comprising: a transistor provided between the inverter circuit and a positive electrode of a battery that supplies power to the inverter circuit, the transistor controlling the supply of power from the battery to the inverter circuit; a diode connected in anti-parallel to the transistor; and a control unit connected to a control terminal of the transistor and controlling a control voltage that is a voltage applied to the control terminal, wherein the control unit controls the control voltage to cause the transistor to operate intermittently when power supply from the battery to the inverter circuit starts, and sets the control voltage applied to the control terminal of the transistor lower than the control voltage when the transistor is fully on.

[0225] (Appendix A2) The semiconductor unit according to Appendix A1, wherein the control voltage when the transistor is intermittently operating is approximately half of the control voltage when the transistor is fully on.

[0226] (Appendix A3) The semiconductor unit according to appendix A1 or A2, wherein the frequency when the transistor operates intermittently is 1000 Hz or less. (Appendix A4) The semiconductor unit according to Appendix A3, wherein the frequency when the transistor operates intermittently is 200 Hz.

[0227] (Appendix A5) The semiconductor unit according to any one of Appendices A1 to A4, wherein the duty ratio when the transistor operates intermittently is less than 50%. (Appendix A6) The semiconductor unit according to appendix A5, wherein the transistor operates intermittently with a duty ratio of 5%.

[0228] (Appendix A7) A semiconductor unit described in any one of Appendices A1 to A6, wherein a capacitor is connected in parallel with the inverter circuit between the battery and the inverter circuit, and the control unit increases the frequency at which the transistor operates intermittently when the terminal voltage of the capacitor is equal to or higher than a threshold value, compared to the frequency at which the transistor operates intermittently when the terminal voltage of the capacitor is less than the threshold value.

[0229] (Appendix A8) The semiconductor unit according to appendix A7, wherein the control unit increases the frequency at which the transistor operates intermittently as the intermittent voltage of the capacitor increases. (Appendix A9) A semiconductor unit described in any one of Appendices A1 to A8, wherein a capacitor is connected in parallel with the inverter circuit between the battery and the inverter circuit, and the control unit sets the control voltage when the transistor operates intermittently when the terminal voltage of the capacitor is equal to or higher than a threshold value to be higher than the control voltage when the transistor operates intermittently when the terminal voltage of the capacitor is less than the threshold value.

[0230] (Appendix A10) The semiconductor unit according to appendix A9, wherein the control unit increases the control voltage when the transistor operates intermittently as the intermittent voltage of the capacitor increases.

[0231] (Appendix A11) A semiconductor unit described in any one of Appendices A1 to A10, wherein a capacitor is connected in parallel with the inverter circuit between the battery and the inverter circuit, and the control unit makes the control voltage when the capacitor is fully charged equal to the control voltage when the transistor is fully on.

[0232] (Appendix A12) The semiconductor unit according to any one of Appendices A1 to A11, comprising a plurality of the transistors, the plurality of transistors being connected in parallel with each other. (Additional Note A13) The semiconductor unit according to Additional Note A12, wherein the control unit controls the plurality of transistors individually.

[0233] (Additional Note A14) The semiconductor unit according to Additional Note A13, wherein the control unit applies control voltages to the plurality of transistors at different timings. (Appendix A15) A battery unit comprising the battery and the semiconductor unit according to any one of Appendices A1 to A14.

[0234] (Appendix A16) A vehicle comprising: the battery unit according to Appendix A15; the inverter circuit; a capacitor connected in parallel to the inverter circuit; and the motor. (Appendix B1) A semiconductor unit comprising: a semiconductor device having a transistor provided between a positive electrode of a battery and an inverter circuit electrically connected to the battery; a control unit connected to a control terminal of the transistor and controlling the transistor; and a resistance unit provided between the control terminal and the control unit, wherein the control unit controls the transistor to turn off when a current flowing through the transistor is equal to or greater than a threshold, and the resistance value of the resistance unit is 100 Ω or greater.

[0235] (Appendix B2) The semiconductor unit according to appendix B1, wherein the transistor has a current sense through which a current proportional to a current flowing through the transistor flows. (Appendix B3) The semiconductor unit according to appendix B1 or B2, wherein the transistor further includes a temperature-sensitive diode.

[0236] (Appendix B4) The semiconductor unit described in Appendix B3, wherein the control unit further includes a temperature detection circuit that detects the temperature of the transistor from the temperature-sensitive diode, and the control unit supplies a current reduction signal to the control terminal of the transistor when the temperature detected by the temperature detection circuit is equal to or higher than a temperature threshold.

[0237] (Appendix B5) The semiconductor unit according to appendix B3 or B4, wherein the transistor is provided as a semiconductor chip, and the temperature-sensitive diode is located in the center of the semiconductor chip.

[0238] (Appendix B6) A semiconductor unit as described in Appendix B5, wherein the transistor is an IGBT, an emitter electrode pad is provided on the surface of the semiconductor chip, a collector electrode is provided on the back surface of the semiconductor chip, the emitter electrode pad is separated into two at the center of the surface of the semiconductor chip, and the temperature-sensitive diode is arranged between the two emitter electrode pads.

[0239] (Appendix B7) A semiconductor unit as described in Appendix B6, wherein the transistor has a current sense through which a current proportional to a current flowing in the transistor flows, and the surface of the semiconductor chip is provided with a gate electrode pad, a current sense pad electrically connected to the current sense, an anode electrode pad electrically connected to the anode of the temperature sensitive diode, and a cathode electrode pad electrically connected to the cathode of the temperature sensitive diode, and the two emitter electrode pads have cutouts cut out in a direction perpendicular to an arrangement direction of the two emitter electrode pads in a plan view of the transistor, and the cutouts form an area recessed in a direction perpendicular to the arrangement direction, and in the area, the gate electrode pad, the current sense pad, the anode electrode pad, and the cathode electrode pad are arranged along a direction parallel to the arrangement direction.

[0240] (Appendix B8) The semiconductor unit according to any one of Appendices B1 to B7, wherein the semiconductor unit includes a plurality of the semiconductor devices, and the transistors of the plurality of semiconductor devices are connected in parallel to each other.

[0241] (Appendix B9) The semiconductor unit according to Appendix B8, wherein the transistors of the plurality of semiconductor devices each include a temperature-sensitive diode. (Appendix B10) The semiconductor unit described in Appendix B9, wherein the control unit includes a plurality of temperature detection circuits, each of which detects the temperature of a transistor of each of the plurality of semiconductor devices from a temperature-sensitive diode of the semiconductor device, and the control unit supplies a current reduction signal to each of the control terminals of the transistors of the plurality of semiconductor devices when at least one of the temperatures detected by the plurality of temperature detection circuits is equal to or higher than a temperature threshold value.

[0242] (Appendix B11) A battery unit comprising the battery and the semiconductor unit according to any one of Appendices B1 to B10. (Appendix B12) A vehicle comprising the battery unit according to appendix B11, the inverter circuit, and a motor driven by the inverter circuit.

[0243] (Appendix C1) A semiconductor unit comprising: a semiconductor device having a transistor provided between a positive electrode of a battery and an inverter circuit electrically connected to the battery; and a control unit connected to a control terminal of the transistor and controlling the transistor, wherein the transistor is an IGBT or a MOSFET, and the control unit controls the voltage between the emitter or source and gate of the transistor to be equal to or lower than the voltage at which a current flowing through the transistor saturates at a predetermined current.

[0244] (Appendix C2) The semiconductor unit according to Appendix C1, wherein the semiconductor unit includes a plurality of the semiconductor devices, and the transistors of the plurality of semiconductor devices are connected in parallel to each other.

[0245] (Appendix C3) The semiconductor unit described in Appendix C1 or C2, wherein the control unit controls the voltage between the emitter or source and gate of each of the transistors of the plurality of semiconductor devices so that the current flowing through each of the plurality of transistors is equal to or less than the saturation current.

[0246] (Appendix C4) A battery unit comprising the battery and the semiconductor unit according to any one of Appendices C1 to C3. (Appendix C5) A vehicle comprising the battery unit according to appendix C4, the inverter circuit, and a motor driven by the inverter circuit.

[0247] (Appendix D1) A semiconductor device comprising: a transistor provided between a positive electrode of a battery and an inverter circuit electrically connected to the battery; and at least one bonding wire connected to the transistor, wherein the number of the bonding wires and the diameter of the bonding wires are set so that the bonding wire breaks when the current flowing through the transistor is equal to or greater than a threshold value.

[0248] (Appendix D2) The semiconductor device according to appendix D1, wherein the threshold value is equal to or greater than two times and equal to or less than four times the rated current of the transistor. (Appendix D3) A semiconductor unit comprising the semiconductor device according to appendix D1 or D2 and a control unit that controls the semiconductor device.

[0249] (Appendix D4) The semiconductor unit according to appendix D3, wherein the semiconductor unit includes a plurality of the semiconductor devices, and the transistors of the plurality of semiconductor devices are connected in parallel to each other.

[0250] (Appendix D5) A battery unit comprising the battery and the semiconductor unit according to appendix D3 or D4. (Appendix D6) A vehicle comprising the battery unit according to appendix D5, the inverter circuit, and a motor driven by the inverter circuit.

[0251] (Appendix E1) A first terminal on the battery side; a second terminal on the inverter circuit side; A semiconductor device comprising: the semiconductor device is configured to allow a current to be supplied from the first terminal to the second terminal and to allow a current to be supplied from the second terminal to the first terminal by controlling a voltage applied to a control terminal of the transistor; The withstand voltage between the first terminal and the second terminal is equal to or greater than the voltage between the battery and the inverter circuit. Semiconductor device.

[0252] (Appendix E2) the transistor is an IGBT, the semiconductor device further includes a diode connected in anti-parallel to the IGBT; The collector of the IGBT becomes the first terminal, and the emitter of the IGBT becomes the second terminal. 10. The semiconductor device according to claim 1,

[0253] (Appendix E3) The IGBT and the diode are provided as separate semiconductor chips. 10. The semiconductor device according to claim 9, wherein the semiconductor device is a semiconductor device according to claim 1,

[0254] (Appendix E4) The IGBT and the diode are formed on the same semiconductor substrate. 10. The semiconductor device according to claim 9, wherein the semiconductor device is a semiconductor device according to claim 1,

[0255] (Appendix E5) the semiconductor device further includes a MOSFET connected in parallel with the IGBT; The MOSFET includes a body diode as a freewheeling diode. The semiconductor device according to any one of Appendixes E2 to E4.

[0256] (Appendix E6) The IGBT and the MOSFET are turned on and off at the same time. The semiconductor device according to Appendix E5.

[0257] (Appendix E7) the transistor is an IGBT, the semiconductor device further includes a MOSFET connected in parallel to the IGBT; The MOSFET includes a body diode as a freewheeling diode. 10. The semiconductor device according to claim 1,

[0258] (Appendix E8) The IGBT and the MOSFET are turned on and off at the same time. The semiconductor device according to Appendix E7.

[0259] (Appendix E9) the transistor is a MOSFET; The semiconductor device further includes a diode connected in antiparallel to the MOSFET. 10. The semiconductor device according to claim 1,

[0260] (Appendix E10) The MOSFET and the diode are provided as separate semiconductor chips. The semiconductor device according to Appendix E9.

[0261] (Appendix E11) The MOSFET includes a body diode as a freewheeling diode. The semiconductor device according to Appendix E9 or E10.

[0262] (Appendix E12) The transistor is a MOSFET that includes a body diode as a freewheeling diode. 10. The semiconductor device according to claim 1,

[0263] (Appendix E13) The positive electrode of the battery; an IGBT provided between the battery and an inverter circuit electrically connected thereto; an RB-IGBT connected in anti-parallel to the IGBT; Semiconductor device.

[0264] (Appendix E14) The IGBT and the RB-IGBT are turned on and off at the same time. 10. The semiconductor device according to claim E13.

[0265] (Appendix E15) A semiconductor module including a plurality of semiconductor devices connected in parallel, Each of the plurality of semiconductor devices is a semiconductor device according to any one of appendices E1 to E14. Semiconductor module.

[0266] (Appendix E16) A relay unit comprising a semiconductor module according to appendix E15. (Appendix E17) A relay unit comprising the semiconductor device according to any one of appendices E1 to E14.

[0267] (Appendix E18) The inverter circuit further includes a mechanical contact relay provided between the negative terminal of the battery and the inverter circuit. 1. A relay unit as described in Annex E16 or E17.

[0268] (Appendix E19) a positive-side semiconductor device provided between the positive electrode of the battery and the inverter circuit; a negative-side semiconductor device provided between the negative electrode of the battery and the inverter circuit; Equipped with The positive electrode side semiconductor device is a semiconductor device according to any one of appendices E1 to E14. Relay unit.

[0269] (Appendix E20) a positive-side semiconductor module provided between the positive electrode of the battery and the inverter circuit; a negative-side semiconductor module provided between the negative electrode of the battery and the inverter circuit; Equipped with The positive-side semiconductor module is a semiconductor module described in Appendix E15. Relay unit.

[0270] (Appendix E21) the battery; A relay unit according to any one of appendices E16 to E20; A battery unit comprising:

[0271] (Appendix E22) a battery unit as described in Appendix E21; the inverter circuit; a motor driven by the inverter circuit; A vehicle equipped with:

[0272] (Appendix F1) a transistor having a first terminal on the battery side, a second terminal on the inverter circuit side, and a control terminal; a semiconductor device having a diode connected to the first terminal and the second terminal, the transistor is configured to allow a current to be supplied from the first terminal to the second terminal by controlling a voltage applied to the control terminal, and the diode is configured to allow a current to be supplied from the second terminal to the first terminal; a withstand voltage between the first terminal and the second terminal is equal to or greater than a voltage between the battery and the inverter circuit; A current limiting resistor is connected to the control terminal, a control unit electrically connected to the control terminal and controlling a control voltage that controls an on / off operation of the transistor; the current limiting resistor is provided between the control terminal and the control unit, The control unit controls the control voltage so as to cause the transistor to operate intermittently when power supply from the first terminal to the second terminal starts, and sets the control voltage of the transistor lower than the control voltage when the transistor is fully on. Semiconductor device.

[0273] (Appendix F2) the transistor is an IGBT, the diode is connected in anti-parallel to the IGBT; The collector of the IGBT becomes the first terminal, and the emitter of the IGBT becomes the second terminal. 10. The semiconductor device according to claim 1.

[0274] (Appendix F3) The IGBT and the diode are provided as separate semiconductor chips and sealed in a single sealing resin. 10. The semiconductor device according to claim F2.

[0275] (Appendix F4) The IGBT and the diode are formed on the same semiconductor substrate. 10. The semiconductor device according to claim F2.

[0276] (Appendix F5) the semiconductor device further includes a MOSFET connected in parallel with the IGBT; The MOSFET includes a body diode as a freewheeling diode. The semiconductor device according to any one of appendices F2 to F4.

[0277] (Appendix F6) The IGBT and the MOSFET are turned on and off at the same time. 10. The semiconductor device according to claim F5.

[0278] (Appendix F7) the transistor is an IGBT, the semiconductor device further includes a MOSFET connected in parallel to the IGBT; The MOSFET includes a body diode as a freewheeling diode. 10. The semiconductor device according to claim 1.

[0279] (Appendix F8) The IGBT and the MOSFET are turned on and off at the same time. 10. The semiconductor device according to claim F7.

[0280] (Appendix F9) the transistor is a MOSFET formed of silicon carbide; The semiconductor device further includes a diode connected in antiparallel to the MOSFET. 10. The semiconductor device according to claim 1.

[0281] (Appendix F10) The MOSFET and the diode are provided as separate semiconductor chips and sealed in a single sealing resin. 10. The semiconductor device according to claim F9.

[0282] (Appendix F11) The MOSFET includes a body diode as a freewheeling diode. The semiconductor device according to appendix F9 or F10.

[0283] (Appendix F12) The transistor is a MOSFET that includes a body diode as a freewheeling diode. 10. The semiconductor device according to claim 1.

[0284] (Appendix F13) The transistor has a temperature sensitive diode, The control voltage applied to the control terminal is controlled in accordance with the output of the temperature sensitive diode. 10. The semiconductor device according to claim 1.

[0285] (Appendix F14) The temperature-sensitive diode is formed in the center of the surface of the transistor. 10. The semiconductor device according to claim F13.

[0286] (Appendix F15) The control unit applies the control voltage to the control terminal, the control voltage changing stepwise over time from the start of power supply from the first terminal to the second terminal. The semiconductor device according to any one of appendices F1 to F14.

[0287] (Appendix F16) a first semiconductor device including an IGBT having a first terminal on the battery side and a second terminal on the inverter circuit side, and a first temperature sensitive diode; a second semiconductor device having an RB-IGBT and a second temperature-sensitive diode connected in anti-parallel to the IGBT; Semiconductor device.

[0288] (Appendix F17) The IGBT and the RB-IGBT are turned on and off at the same time. 10. The semiconductor device according to claim F16.

[0289] (Appendix F18) the first semiconductor device includes a first current sensor through which a current proportional to a current flowing from the emitter of the IGBT flows; The second semiconductor device includes a second current sensor through which a current proportional to a current flowing from the emitter of the RB-IGBT flows. The semiconductor device according to appendix F16 or F17.

[0290] (Appendix F19) When at least one of the temperature of the IGBT and the temperature of the RB-IGBT is equal to or higher than a temperature threshold, the IGBT and the RB-IGBT are turned off. 10. The semiconductor device according to claim F16.

[0291] (Appendix F20) When at least one of the current flowing through the IGBT and the current flowing through the RB-IGBT is equal to or greater than a threshold, the IGBT and the RB-IGBT are turned off. 10. The semiconductor device according to claim F18.

[0292] (Appendix F21) The first temperature sensitive diode is formed at the center of the surface of the IGBT. The semiconductor device according to any one of appendices F16 to F20.

[0293] (Appendix F22) a first current limiting resistor connected to the gate of the IGBT; a second current limiting resistor connected to the gate of the RB-IGBT; Equipped with The resistance value of the first current limiting resistor and the resistance value of the second current limiting resistor are different from each other. The semiconductor device according to any one of appendices F16 to F21.

[0294] (Appendix F23) A semiconductor module including a plurality of semiconductor devices connected in parallel, Each of the plurality of semiconductor devices is a semiconductor device according to any one of appendices F1 to F22. Semiconductor module.

[0295] (Appendix F24) A relay unit comprising a semiconductor module according to appendix F23. (Appendix F25) A relay unit comprising the semiconductor device according to any one of appendices F1 to F22.

[0296] (Appendix F26) The inverter circuit is further provided with a mechanical contact relay provided between the negative terminal of the battery and the inverter circuit. Relay units as described in Annex F24 or F25.

[0297] (Appendix F27) a positive-side semiconductor device provided between the positive electrode of the battery and the inverter circuit; a negative-side semiconductor device provided between the negative electrode of the battery and the inverter circuit; Equipped with The positive electrode side semiconductor device is a semiconductor device according to any one of appendices F1 to F22. Relay unit.

[0298] (Appendix F28) a positive-side semiconductor module provided between the positive electrode of the battery and the inverter circuit; a negative-side semiconductor module provided between the negative electrode of the battery and the inverter circuit; Equipped with The positive-side semiconductor module is a semiconductor module described in Appendix F23. Relay unit.

[0299] (Appendix F29) a relay unit according to any one of appendices F24 to F28; a battery connected to the relay unit; A battery unit comprising:

[0300] (Appendix F30) a battery unit as described in Appendix F29; an inverter circuit connected to the battery of the battery unit via the relay unit; a motor driven by the inverter circuit; A vehicle equipped with:

[0301] (Appendix G1) a first switching element having a first terminal, a second terminal, and a control terminal for controlling a switching operation between the first terminal and the second terminal; a second switching element connected in parallel between the first terminal and the second terminal of the first switching element, The voltage applied to the control terminal is lower than the voltage applied to the control terminal when the first switching element is fully on, and is applied so that the voltage between the first terminal and the second terminal of the first switching element changes stepwise over time. Semiconductor device.

[0302] (Appendix G2) The voltage applied to the control terminal is applied so that the voltage between the first terminal and the second terminal of the first switching element changes stepwise multiple times over time. 10. The semiconductor device according to claim 1.

[0303] (Appendix G3) The first switching element is operated intermittently, and the frequency of the intermittent operation is 1000 Hz or less. The semiconductor device according to appendix G1 or G2.

[0304] (Appendix G4) the first switching element is a MOSFET formed of silicon carbide, The second switching element is a diode connected in antiparallel to the MOSFET. The semiconductor device according to any one of appendices G1 to G3.

[0305] (Appendix G5) the first switching element further includes a temperature sensitive diode; The temperature-sensitive diode is located at the center of the surface of the semiconductor chip of the first switching element. The semiconductor device according to any one of appendices G1 to G4.

[0306] (Appendix G6) The first switching element is operated intermittently to perform pre-charging, which gradually charges a capacitor provided between the second terminal and an inverter circuit connected to the second terminal. The semiconductor device according to any one of Appendices G1 to G5.

[0307] (Appendix G7) the first switching element has a sense terminal; The voltage applied to the control terminal varies depending on the voltage difference between the sense terminal and the second terminal. A semiconductor device according to any one of Appendices G1 to G6.

[0308] (Appendix G8) further comprising a third switching element connected in parallel to the first switching element; the first switching element is an IGBT, The third switching element is a SiC MOSFET or a GaN MOSFET. A semiconductor device according to any one of Appendices G1 to G7.

[0309] (Appendix G9) a first switching element having a first terminal to which an input voltage from a positive electrode of a battery is applied, and a second terminal that outputs a voltage corresponding to the input voltage applied to the first terminal to an inverter circuit in response to a voltage applied to a control terminal; a second switching element connected in parallel between the first terminal and the second terminal; a third switching element different from the first switching element, between the negative electrode of the battery and the inverter circuit; the first switching element is configured to allow a current to be supplied from the first terminal to the second terminal and to allow a current to be supplied from the second terminal to the first terminal in response to a voltage applied to the control terminal; The device has a temperature sensing diode for detecting the temperature of the first switching element, and controls the first switching element in response to the temperature of the first switching element. Semiconductor device.

[0310] (Appendix G10) The temperature sensing diode is disposed in the center of the first switching element. 10. The semiconductor device according to claim 9.

[0311] (Appendix G11) the third switching element is a mechanical contact relay, a sealing resin for sealing the temperature sensitive diode and the first switching element; The semiconductor device according to appendix G9 or G10.

[0312] (Appendix G12) the first switching element is an IGBT, the second switching element is a diode, the first terminal is a collector of the IGBT, and the second terminal is an emitter of the IGBT; The cathode of the diode is connected to the first terminal, and the anode of the diode is connected to the second terminal. The semiconductor device according to any one of appendices G1 to G8.

[0313] (Appendix G13) The IGBT and the diode are provided as separate semiconductor chips. The semiconductor device according to any one of Appendix G12.

[0314] (Appendix G14) The IGBT and the diode are formed on the same semiconductor substrate. 10. The semiconductor device according to claim 12.

[0315] (Appendix G15) the semiconductor device further includes a MOSFET connected in parallel with the IGBT; The MOSFET includes a body diode as a freewheeling diode. A semiconductor device according to any one of appendices G12 to G14.

[0316] (Appendix G16) The IGBT and the MOSFET are turned on and off at the same time. 10. The semiconductor device according to claim 15.

[0317] (Appendix G17) A first terminal; A second terminal; an IGBT having a control terminal that controls a switching operation between the first terminal and the second terminal; an RB-IGBT connected in anti-parallel to the IGBT; Semiconductor device.

[0318] (Appendix G18) the first terminal is connected to a positive electrode of a battery; The second terminal is connected to an inverter circuit that receives voltage from the battery and operates. 10. The semiconductor device according to claim 17.

[0319] (Appendix G19) A semiconductor device according to appendix G7; a control circuit that controls the control terminal of the first switching element; a sense resistor provided between the second terminal and the sense terminal; The control circuit detects the current flowing from the second terminal of the first switching element based on the voltage generated across the sense resistor. Semiconductor unit.

[0320] (Appendix G20) The control circuit turns the first switching element off when the voltage generated across the sense resistor is equal to or greater than a threshold value. 10. A semiconductor unit as described in Appendix G19. [Explanation of symbols]

[0321] 1 vehicle, 11 motor, 12 inverter circuit, 13 capacitor, 20 battery unit, 21 battery module (battery), 30 relay unit, 32 second relay unit (mechanical contact type relay), 33 control circuit (control unit), 34 gate control circuit, 36 current limiting resistor, 37 temperature detection circuit, 40 semiconductor module, 40A first semiconductor device (semiconductor device), 40B second semiconductor device (semiconductor device), 40C third semiconductor device (semiconductor device), 41 semiconductor unit, 42, 42rb, 42a, 42b, 42c IGBT, 43, 43a, 43b, 43c diode, 49a power wire, 50, 110 semiconductor substrate, 64 collector electrode, 66 emitter electrode pad, 67 gate electrode pad, 76a anode electrode pad, 80 temperature sensitive diode, 81 current sense, 91A, 91B emitter electrode pad, 92 gate electrode pad, 93 Anode electrode pad, 94 cathode electrode pad, 95 current sense pad, 97 notch, 101 anode electrode pad, 102 current sense pad, 140 MOSFET, 140a body diode, X first direction (arrangement direction), Y second direction (direction perpendicular to the arrangement direction).

Claims

1. a semiconductor device comprising: a transistor chip having a rectangular shape, a second electrode pad and a control pad provided on a front surface of the transistor chip, a first electrode pad provided on a back surface of the transistor chip, the transistor chip performing an on / off operation between the first electrode pad and the second electrode pad in response to a voltage input to the control pad; a first terminal electrically connected to the first electrode pad, a second terminal electrically connected to the second electrode pad, and a control terminal electrically connected to the control pad; a control unit electrically connected to the control terminal to control the transistor chip; a resistor portion provided between the control terminal and the control portion; Equipped with the second electrode pad is separated into two regions at the center of the surface of the transistor chip; A temperature sensitive diode is disposed between the two regions. Semiconductor unit.

2. the control unit controls the transistor chip so as to turn off the transistor chip when a current flowing through the transistor chip is equal to or greater than a threshold value. The semiconductor unit according to claim 1 .

3. The resistance value of the resistor portion is 100Ω or more. The semiconductor unit according to claim 1 .

4. the transistor chip is an IGBT, the first electrode pad is a collector electrode, and the second electrode pad is an emitter electrode; The semiconductor unit according to claim 1 .

5. the transistor chip is a MOSFET configured with a silicon carbide (SiC) semiconductor substrate, the first electrode pad is a drain electrode, and the second electrode pad is a source electrode; The semiconductor unit according to claim 1 .

6. a gate electrode pad, an anode electrode pad electrically connected to the anode of the temperature-sensitive diode, and a cathode electrode pad electrically connected to the cathode of the temperature-sensitive diode are provided on a surface of the transistor chip; the gate electrode pad, the anode electrode pad, and the cathode electrode pad are arranged along one side of the transistor chip; The semiconductor unit according to claim 1 .

7. the transistor chip has a notch portion configured so that the second electrode pad is recessed in a direction perpendicular to an arrangement direction of the two regions in a plan view of the transistor chip, the gate electrode pad, the anode electrode pad, and the cathode electrode pad are disposed in the notches; The semiconductor unit according to claim 6 .

8. the control unit further includes a temperature detection circuit that detects the temperature of the transistor chip in response to a signal from the temperature-sensitive diode; the control unit supplies a current reduction signal to the control terminal of the transistor chip when the signal detected by the temperature detection circuit is equal to or greater than a threshold value. The semiconductor unit according to claim 1 .

9. the semiconductor unit includes a plurality of the transistor chips, The plurality of transistor chips are connected in parallel to each other. The semiconductor unit according to claim 1 .

10. Each of the plurality of transistor chips includes the temperature sensitive diode. The semiconductor unit according to claim 9 .

11. the control unit includes a plurality of temperature detection circuits, the plurality of temperature detection circuits receive signals from the respective temperature-sensitive diodes of the plurality of transistor chips; the control unit supplies a current reduction signal to each of the control terminals of the plurality of transistor chips when at least one of the signals corresponding to the temperatures detected by the plurality of temperature detection circuits is equal to or greater than a threshold value. The semiconductor unit according to claim 10.

12. The semiconductor unit according to claim 1 ; a battery electrically connected to the first terminal; A battery unit comprising:

13. The battery unit according to claim 12; an inverter circuit electrically connected to the second terminal; a motor driven by the inverter circuit; A vehicle equipped with:

14. The vehicle according to claim 13 , further comprising a mechanical relay unit connected in parallel with the semiconductor unit between the battery and the inverter circuit.

15. a semiconductor device comprising a first terminal, a second terminal, and a control terminal, wherein a second electrode pad electrically connected to the second terminal and a control pad electrically connected to the control terminal are provided on a front surface, and a first electrode pad is provided on a back surface, and a rectangular transistor chip is provided which performs an on / off operation between the first electrode pad and the second electrode pad in response to a voltage input to the control pad, wherein the first terminal is electrically connected to the first electrode pad, the second terminal is electrically connected to the second electrode pad, and the control terminal is electrically connected to the control pad; a control unit electrically connected to the control terminal and controlling an ON / OFF operation between the first electrode pad and the second electrode pad; Equipped with the transistor chip further includes a third electrode pad and a fourth electrode pad connected to a temperature sensitive diode; the control pad, the third electrode pad, and the fourth electrode pad are arranged along one side of the transistor chip. Semiconductor unit.

16. a current limiting resistor electrically connected to the control terminal; a diode connected in anti-parallel to the transistor chip; Further provided with The semiconductor unit according to claim 15.

17. the second electrode pad is separated into two regions at the center of the surface of the transistor chip; The temperature sensitive diode is disposed between the two regions; a notch portion configured so that the second electrode pad is recessed in a direction perpendicular to the arrangement direction of the two regions in a plan view of the transistor chip; the control pad, the third electrode pad, and the fourth electrode pad are disposed in the notch portion; The semiconductor unit according to claim 15.

18. the transistor chip is a MOSFET configured with a silicon carbide (SiC) semiconductor substrate, the first electrode pad is a drain electrode, and the second electrode pad is a source electrode; The semiconductor unit according to claim 15.

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