Noise information estimation program and noise information estimation method and information processor

Abstract

To efficiently acquire information about noise.SOLUTION: A processing part 12 acquires multiple output distributions representing the distribution of output states for multiple quantum bits corresponding to each of multiple quantum circuits when multiple quantum circuits are executed multiple times for multiple quantum bits. The processing part 12 determines the execution success or failure of each of multiple quantum circuits based on the deviation degree between each of the multiple output distributions and a uniform distribution. The processing part 12 estimates information regarding the noise of each quantum bit based on the execution success / failure determination results for each quantum circuit and the number of quantum gates applied to each quantum bit within each quantum circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a noise information estimation program, a noise information estimation method, and an information processing device. [Background technology]

[0002] Quantum computers can execute calculations in parallel by utilizing quantum mechanical effects. Calculations that utilize quantum mechanical effects are called quantum computing. Quantum computers are expected to achieve exponential improvements in computational speed compared to classical computers (also known as von Neumann computers) by performing quantum computations.

[0003] Quantum computers perform quantum computations using qubits. A qubit is a unit of information that can be in a superposition of |0> and |1> states. When a qubit is measured, its state changes probabilistically to |0> or |1>. By measuring the state of a qubit multiple times, the state of the qubit before the measurement can be estimated based on the probability of occurrence of |0> and |1>.

[0004] A quantum computing system uses quantum bits to change their state and calculates the result by statistically processing the measurement results of multiple calculations. The quantum bits can be changed to a desired state by applying a specific quantum gate.

[0005] The order of quantum gates that act on each qubit to allow a quantum computer to perform a quantum computation can be modeled as a quantum circuit. The quantum computer performs quantum gate operations on the qubits according to the quantum circuit and measures the final qubit state. The measurement results are statistically processed by a classical computer.

[0006] If the state of the quantum bits changes accurately in accordance with the quantum gate operation, the correct calculation result can be obtained. However, quantum bits are susceptible to noise, which causes errors. This makes error correction important, but it is expected to take more than 10 years until a quantum computer capable of error correction is realized. Therefore, the most realistic option with current technology is to make effective use of NISQ (Noisy Intermediate Scale Quantum) computers, which do not have error correction capabilities.

[0007] In addition, when multiple quantum processors are connected to form a logical quantum bit, a system has been proposed in which, even if an error is detected in the first group of quantum processors, the error is checked again by the second group of quantum processors, thereby reducing the probability of inappropriate error correction.

[0008] There are also proposals for systems that perform continuous, parallel, in-situ optimization of qubit performance while error correction operations on the quantum system are running. Others have proposed methods to estimate the value of error-free observables using extrapolation by increasing the error rate of the quantum computer, sampling at different error rates, and fitting the resulting measurements to a multi-exponential decay curve.

[0009] Furthermore, there have been proposals for systems that dynamically calculate bias-correction weights that can be used to probabilistically cancel the noise introduced by individual measurements of the quantum state and calculate adjusted (noise-free) expectation values ​​for the quantum. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2022-161129 [Patent Document 2] Japanese Patent Publication No. 2022-172094 [Patent Document 3] US Patent Application Publication No. 2023 / 0196173 [Patent Document 4] US Patent Application Publication No. 2023 / 0196172 Summary of the Invention [Problem to be solved by the invention]

[0011] Computational processing on NISQ computers is affected by noise. Quantum circuits can be optimized depending on the state of the noise. The state of the noise changes over time. Therefore, it is possible to periodically measure the latest state of the noise using existing methods such as Randomized Benchmarking (RB).

[0012] However, measuring the noise state takes time. For example, if noise state measurements are frequently performed using RB to obtain the latest noise state, the actual calculation process may be postponed.

[0013] In one aspect, the present invention aims to efficiently obtain information about noise. [Means for solving the problem]

[0014] In one embodiment, a noise information estimation program is provided. The noise information estimation program causes a computer to execute the following process. The computer acquires multiple output distributions indicating distributions of output states of multiple quantum bits corresponding to multiple quantum circuits when multiple quantum circuits are each executed multiple times for multiple quantum bits. The computer determines whether each of the multiple quantum circuits has executed successfully based on the degree of deviation between each of the multiple output distributions and a uniform distribution. The computer estimates information about the noise of each of the multiple quantum bits based on the determination result of whether each of the multiple quantum circuits has executed successfully and the number of quantum gates applied to each of the multiple quantum bits in each of the multiple quantum circuits.

[0015] In one aspect, a noise information estimation method executed by a computer is provided.In another aspect, an information processing device having a storage unit and a processing unit is provided. [Effects of the Invention]

[0016] In one aspect, information about noise can be obtained efficiently. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 2 illustrates an example of a noise information estimation method according to the first embodiment. [Figure 2] FIG. 10 illustrates an example of a quantum computing system according to a second embodiment. [Figure 3] FIG. 1 is a diagram illustrating an example of hardware of a quantum computing system. [Figure 4] FIG. 1 is a diagram illustrating an example of a quantum circuit. [Figure 5] FIG. 1 is a diagram illustrating an example of a quantum circuit. [Figure 6] FIG. 10 is a diagram illustrating an example of an adjacent relationship between quantum bits. [Figure 7] FIG. 10 is a diagram illustrating an example of an error rate for each quantum bit. [Figure 8] FIG. 1 is a diagram illustrating an example of how a quantum computing system is used by a user. [Figure 9] FIG. 1 is a diagram illustrating an example of the functions of a classical computer. [Figure 10] FIG. 1 is a diagram illustrating an example of a quantum circuit for the Grover algorithm. [Figure 11] FIG. 10 is a diagram illustrating an example of an output distribution according to noise. [Figure 12] 10 is a flowchart illustrating an example of a safety range update. [Figure 13] 10 is a flowchart showing an example of a determination process A. [Figure 14] FIG. 1 is a diagram illustrating an example of a quantum algorithm involving iteration. [Figure 15] FIG. 10 is a diagram illustrating an example of a quantum circuit executed at the end of an execution period. [Figure 16]FIG. 10 is a diagram showing an example of a gate pattern in which a partial amplification distribution is an expected output value. [Figure 17] 10 is a flowchart showing an example of a determination process B. [Figure 18] FIG. 1 is a diagram illustrating an example (part 1) of a quantum circuit. [Figure 19] FIG. 10 is a diagram showing an example (part 1) of an output distribution. [Figure 20] FIG. 10 is a diagram illustrating an example (part 2) of a quantum circuit. [Figure 21] FIG. 10 is a diagram showing an example (part 2) of the output distribution. [Figure 22] 10A and 10B are diagrams illustrating examples of gate number information when execution is successful / failed. [Figure 23] FIG. 10 is a diagram illustrating an example of calculation of a safety range of the number of applicable gates. [Figure 24] FIG. 10 is a diagram illustrating an example of safety range information. [Figure 25] 10 is a flowchart illustrating an example of processing when a quantum circuit is executed. [Figure 26] 10 is a flowchart illustrating an example of adjustment processing in a quantum circuit execution method. [Figure 27] FIG. 1 is a diagram illustrating an example of the number of gates / density of a quantum circuit. [Figure 28] FIG. 10 is a diagram illustrating an example of gate count / density after optimization. DETAILED DESCRIPTION OF THE INVENTION

[0018] The present embodiment will be described below with reference to the drawings. Note that each embodiment can be implemented in combination with a plurality of other embodiments within a range that does not contradict each other. [First embodiment] The first embodiment is a noise information estimation method for efficiently acquiring information about noise.

[0019] A first embodiment will be described. FIG. 1 is a diagram illustrating an example of a noise information estimation method according to a first embodiment. FIG. 1 illustrates an information processing device 10 that executes the noise information estimation method. The information processing device 10 can execute the noise information estimation method by, for example, executing a noise information estimation program. The information processing device 10 is connected to a quantum computer 20. The quantum computer 20 performs quantum operations based on a quantum circuit. The quantum computer 20 performs quantum operations using quantum bits.

[0020] Graph 21 shows, as an example, eight quantum bits q0 to q7 in quantum computer 20 and the adjacency relationships between these quantum bits. One node in graph 21 corresponds to one quantum bit. An edge connecting two nodes in graph 21 indicates that the two quantum bits corresponding to the two nodes are adjacent.

[0021] The storage unit 11 may be a volatile semiconductor memory such as a random access memory (RAM), or a non-volatile storage such as a hard disk drive (HDD) or flash memory. The processing unit 12 is a processor such as a central processing unit (CPU), a graphics processing unit (GPU), or a digital signal processor (DSP). However, the processing unit 12 may also include an application-specific electronic circuit such as an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The processor executes a program stored in a memory such as a RAM (which may be the storage unit 11). A set of multiple processors may be called a "multiprocessor" or simply a "processor."

[0022] The storage unit 11 stores information about the multiple quantum circuits executed by the quantum computer 20 and the execution results of each of the multiple quantum circuits. The execution results of the quantum circuits indicate the distribution of output values ​​of each quantum bit, i.e., the output distribution, obtained by measuring the values ​​of the multiple quantum bits multiple times.

[0023] The processing unit 12 acquires from the storage unit 11 a plurality of output distributions corresponding to a plurality of quantum circuits executed by the quantum computer 20. The processing unit 12 may generate an output distribution for each quantum circuit based on the measurement values ​​of each quantum bit obtained from the quantum computer 20 for each quantum circuit, and store the generated output distribution in the storage unit 11.

[0024] For example, the processing unit 12 acquires an output distribution D1 for the quantum circuit C1. The processing unit 12 also acquires an output distribution D2 for the quantum circuit C2. The processing unit 12 similarly acquires output distributions for the other quantum circuits. That is, the processing unit 12 acquires multiple output distributions that indicate the distribution of output states of multiple quantum bits corresponding to multiple quantum circuits when multiple quantum circuits are each executed multiple times for multiple quantum bits.

[0025] Here, the quantum circuits C1, C2, ... used in the noise estimation process are selected from all quantum circuits executed by the quantum computer 20 within a certain period of time, and are expected to have a partly-amplified distribution in the observation frequency of each output. A partly-amplified distribution is a distribution in which the frequency of a specific set of values ​​of multiple quantum bits is higher than the frequency of other sets. All of the output distributions D1, D2, ... correspond to the partly-amplified distribution. Furthermore, the "certain period" is preferably a period close to the present time in order to grasp the latest noise state.

[0026] In many representative quantum algorithms, superposition is used to parallelize multiple calculations, while wave interference is used to amplify only the probability of the desired state (combination of quantum bit values). In other words, the following can be expected regarding the success or failure of the execution of a quantum circuit. If only the probability of occurrence of some states is amplified, i.e., if a partial amplification distribution is obtained, it is highly likely that the calculation was successful. Conversely, if the probability of occurrence of all states is roughly the same, i.e., close to a uniform distribution, it is highly likely that the calculation failed.

[0027] For example, the processing unit 12 may identify a quantum circuit to be used in the noise estimation process based on whether the algorithm of the executed quantum circuit corresponds to a specific algorithm in which the output expected value becomes a partial amplification distribution.

[0028] Examples of specific algorithms in which the output expectation value is a partially amplified distribution include QAOA (Quantum Approximate Optimization Algorithm), VQE (Variational Quantum Eigensolver), Grover's algorithm, and Shor's algorithm. However, in algorithms that involve iterations (VQA: Variational Quantum Algorithm), such as QAOA and VQE, the desired state is approached through iterations. For this reason, among quantum circuits in these algorithms, the output expectation value of a quantum circuit near the final iteration is a partially amplified distribution.

[0029] The processing unit 12 determines whether each of the multiple quantum circuits has been executed successfully based on the degree of deviation between each of the multiple output distributions and the uniform distribution E (step S1). For example, the processing unit 12 can calculate the degree of deviation between the output distribution and the uniform distribution E using an existing method. One example of the degree of deviation is the Hellinger distance. However, a measure other than the Hellinger distance may be used to measure the deviation between the output distribution and the uniform distribution E. Other examples of the measure include the Kullback-Leibler divergence, the Jensen-Shannon divergence, the Wasserstein distance, and the Shannon entropy.

[0030] For example, if the deviation between the output distribution and the uniform distribution E is equal to or greater than a threshold, the processing unit 12 determines that a partially amplified distribution has been obtained as the output distribution, and determines that the execution of the quantum circuit in question has been successful. On the other hand, if the deviation between the output distribution and the uniform distribution E is smaller than the threshold, the processing unit 12 determines that a partially amplified distribution has not been obtained as the output distribution, and determines that the execution of the quantum circuit in question has failed.

[0031] For example, the processing unit 12 calculates the degree of deviation between the output distribution D1 and the uniform distribution E and compares the calculated degree of deviation with a threshold. The degree of deviation between the output distribution D1 and the uniform distribution E is smaller than the threshold. In this case, the processing unit 12 determines that the execution of the quantum circuit C1 by the quantum computer 20 has failed.

[0032] Furthermore, the processing unit 12 calculates the degree of deviation between the output distribution D2 and the uniform distribution E, and compares the calculated degree of deviation with a threshold. The degree of deviation between the output distribution D2 and the uniform distribution E is equal to or greater than the threshold. In this case, the processing unit 12 determines that the quantum computer 20 has successfully executed the quantum circuit C2. The processing unit 12 can similarly determine the success or failure of execution for other quantum circuits.

[0033] The processing unit 12 estimates information about noise for each of the multiple quantum bits based on the determination result of whether each of the multiple quantum circuits has been executed successfully and the number of quantum gates applied to each of the multiple quantum bits in each of the multiple quantum circuits (step S2).

[0034] Specifically, the processing unit 12 acquires the number of quantum gates applied to the quantum bits for each quantum circuit that has been successfully executed, i.e., the number of applied gates, for each quantum bit. Here, the number of quantum gates counted is, for example, the number of basis gates (basis quantum gates). For example, if there are three basis gates, SX, CX, and RZ, the number of applied gates is counted for each of the basis gates (SX, RZ) for one quantum bit and the basis gate (CX) for two quantum bits. The same applies to the counting of the number of applied gates described below.

[0035] Then, the processing unit 12 specifies, for each quantum bit, the range of the number of applicable gates when execution is successful. Also, the processing unit 12 acquires the number of applicable gates for each quantum bit for each quantum circuit that has failed to execute. Then, the processing unit 12 specifies, for each quantum bit, the range of the number of applicable gates when execution is unsuccessful.

[0036] Generally, the greater the number of gates applied to a quantum bit, the greater the quantum bit noise and the higher the error rate. That is, the information on the range of gates applied when each quantum bit is successfully executed and the range of gates applied when execution fails reflects the noise state of the quantum bit. Therefore, the information on the range of gates applied when each quantum bit is successfully executed and the range of gates applied when execution fails can be said to be an example of information on the noise of the quantum bit.

[0037] For example, the processing unit 12 acquires, for a quantum bit of interest, the range of the number of gates to be applied when execution is successful, excluding the range of the number of gates to be applied when execution fails, and determines the range of 0 to the lower limit of the acquired range as the safe range of the number of gates to be applied for that quantum bit. Furthermore, for example, the processing unit 12 determines the overlapping range of the range of the number of gates to be applied when execution is successful and the range of the number of gates to be applied when execution fails as the quasi-safe range of the number of gates to be applied for that quantum bit. If the number of gates to be applied is within the safe range, it is highly likely that quantum operations can be performed safely on that quantum bit without the influence of noise. Furthermore, if the number of gates to be applied is within the quasi-safe range, there is a possibility that errors may occur, but quantum operations can be performed appropriately using that quantum bit. The safe range and quasi-safe range also reflect the influence of noise conditions for each quantum bit. Therefore, information about the safe range and quasi-safe range can also be considered examples of information about noise for that quantum bit.

[0038] In addition, the information on the safe range and quasi-safe range may include not only the number of gates applied per quantum bit, but also the range of density of the number of gates applied to quantum bits adjacent to the quantum bit, i.e., the range of the average value of the number of gates applied to adjacent quantum bits.

[0039] Thus, for example, the processing unit 12 obtains information such as the safe range 0 ≦ r ≦ R1 of the number of gates applied to the qubit q0 and the quasi-safe range R1 < r ≦ R2. The processing unit 12 can similarly obtain information on the safe range and the quasi-safe range for the other qubits q1 to q7. Note that the processing unit 12 can obtain the safe range and the quasi-safe range for each qubit with respect to the base gates for one qubit and the base gates for two qubits, respectively.

[0040] Based on the information on the safe range and the quasi-safe range, the processing unit 12 may adjust the number of gates applied to each qubit for the newly executed quantum circuit. For example, first, the processing unit 12 performs qubit mapping to determine which physical qubit on the quantum processor to assign the logical qubits of the quantum circuit so that the number of gates applied is within the safe range for the corresponding quantum circuit. If the processing unit 12 can perform qubit mapping that keeps the number of gates applied to each physical qubit within the safe range, it adopts such mapping. On the other hand, if the processing unit 12 cannot perform qubit mapping that keeps the number of gates applied to each physical qubit within the safe range, it allows the number of gates applied within the quasi-safe range for all or part of the corresponding qubits and performs qubit mapping and adopts such mapping.

[0041] Based on the qubit mapping adopted by the above method, the processing unit 12 instructs the quantum computer 20 to execute the corresponding quantum circuit. Thus, the processing unit 12 can instruct the quantum computer 20 to execute a quantum circuit in consideration of the noise state of each qubit.

[0042] As described above, according to the information processing apparatus 10, a plurality of output distributions corresponding to a plurality of quantum circuits executed by the quantum computer 20 including a plurality of qubits are acquired. The success or failure of each of the plurality of quantum circuits is determined based on the degree of divergence between each of the plurality of output distributions and the uniform distribution. Information regarding the noise of each of the plurality of qubits is estimated based on the determination result of the success or failure of each of the plurality of quantum circuits and the number of quantum gates applied to each of the plurality of qubits in each of the plurality of quantum circuits. Thereby, the information processing apparatus 10 can efficiently acquire information regarding noise.

[0043] By the way, as an existing method for measuring the magnitude of noise in the quantum computer 20, the aforementioned RB may be used. For example, by RB, the average error rate for a specific set of quantum gates is measured. Also, by applying RB, the measurement of the noise state may be performed in more detail. For example, Interleaved RB (IRB) is a technique for measuring the average error rate for each quantum gate instead of a set of gates. In IRB, for a random gate sequence in RB, a quantum circuit in which a gate operation for which the error rate is to be measured is sandwiched is prepared, and the average success probability of the target gate operation is calculated. Also, Simultaneous RB (SimRB) is a technique for measuring the error rate due to crosstalk. In SimRB, for pairs of qubits for which the influence of crosstalk is to be measured, RB is executed simultaneously, and the average success probability is calculated.

[0044] However, in the existing measurement of error rates by RB, IRB, SimRB, etc., it takes a long time to execute. This is because for each qubit, each qubit pair, and each quantum gate operation, a large number of quantum circuits, that is, randomly selected gate sequences, are to be executed. Basically, the execution time becomes longer in the order of RB < IRB < SimRB. Therefore, when using the existing measurement method, there is a possibility of deteriorating the congestion situation of the quantum computer 20.

[0045] Furthermore, to execute quantum circuits more accurately, it is desirable to keep track of the latest noise state. Because the noise state of each qubit changes over time, it is possible to measure the noise state frequently. However, existing methods such as RB take a long time to execute, and frequent measurement of the noise state significantly worsens the congestion of the quantum computer 20.

[0046] In contrast, the information processing device 10 can indirectly grasp the magnitude of noise of each quantum bit based on the execution results of the quantum circuit by the quantum computer 20, without measuring it using existing methods such as RB. Furthermore, the information processing device 10 does not put pressure on the usage time of the quantum computer 20, so it does not worsen the congestion situation. For example, the information processing device 10 can continue to grasp the latest noise state by periodically executing the above-mentioned noise information estimation method. Furthermore, as described above, the information processing device 10 can increase the success rate of quantum circuit execution by performing quantum bit allocation and quantum circuit optimization based on information about the estimated noise, i.e., information about the safe range and quasi-safe range.

[0047] [Second embodiment] Next, a second embodiment will be described. FIG. 2 is a diagram illustrating an example of a quantum computing system according to a second embodiment. The quantum computing system 300 is a computer system using quantum devices. The quantum computing system 300 includes a classical computer 100 and a quantum computer 200. Terminal devices 401, 402, and so on are connected to the classical computer 100 via a network 30. The terminal devices 401, 402, and so on are computers used by users who request quantum computing by the quantum computing system 300. The classical computer 100 receives computation requests, including quantum circuits, from the terminal devices 401, 402, and so on. A quantum circuit indicates the order of operations on quantum bits by arranging elements such as quantum gates. A quantum bit is a bit that can represent a superposition of a "0" state and a "1" state.

[0048] The classical computer 100 instructs the quantum computer 200 to execute quantum computation in accordance with the quantum circuits received from the terminal devices 401, 402, .... The classical computer 100 also acquires measurement results of each quantum bit from the quantum computer 200. The classical computer 100 is an example of an information processing device 10.

[0049] Quantum computer 200 has multiple quantum bits and devices for manipulating each of the multiple quantum bits. Quantum computer 200 is a NISQ computer. The multiple quantum bits of quantum computer 200 can be realized using, for example, a superconducting method, an ion trap method, or a diamond spin method. Quantum computing system 300 has multiple quantum computers including quantum computer 200.

[0050] FIG. 3 is a diagram illustrating an example of hardware of a quantum computing system. A classical computer 100 is entirely controlled by a processor 101. A memory 102 and multiple peripheral devices are connected to the processor 101 via a bus 109. The processor 101 may be a multiprocessor. The processor 101 is, for example, a CPU, an MPU (Micro Processing Unit), or a DSP. At least a portion of the functions realized by the processor 101 executing a program may be realized by an electronic circuit such as an ASIC or a PLD (Programmable Logic Device). The processor 101 may also be referred to as a "processor circuitry." The processor 101 is an example of the processing unit 12 of the first embodiment.

[0051] The memory 102 is used as a main storage device of the classical computer 100. The memory 102 temporarily stores at least a portion of the OS (Operating System) program and application programs to be executed by the processor 101. The memory 102 also stores various data used in processing by the processor 101. A volatile semiconductor storage device such as a RAM is used as the memory 102, for example.

[0052] The peripheral devices connected to the bus 109 include a storage device 103, a GPU 104, an input interface 105, an optical drive device 106, a device connection interface 107, and network interfaces 108a and 108b.

[0053] The storage device 103 writes and reads data electrically or magnetically to and from a built-in recording medium. The storage device 103 is used as an auxiliary storage device for the classical computer 100. The storage device 103 stores an OS program, application programs, and various data. Note that, for example, an HDD or an SSD (Solid State Drive) can be used as the storage device 103. The memory 102 or the storage device 103 is an example of the storage unit 11 of the first embodiment.

[0054] The GPU 104 is an arithmetic unit that performs image processing. The GPU 104 is an example of a graphics controller. The monitor 31 is connected to the GPU 104. The GPU 104 displays an image on the screen of the monitor 31 in accordance with an instruction from the processor 101. The monitor 31 may be a display device using organic EL (Electro Luminescence) or a liquid crystal display device.

[0055] The input interface 105 is connected to a keyboard 32 and a mouse 33. The input interface 105 transmits signals sent from the keyboard 32 and the mouse 33 to the processor 101. The mouse 33 is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

[0056] The optical drive device 106 uses a laser beam or the like to read data recorded on the optical disc 34 or write data to the optical disc 34. The optical disc 34 is a portable recording medium on which data is recorded so that it can be read by reflected light. The optical disc 34 includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), and a CD-R (Recordable) / RW (Rewritable).

[0057] The device connection interface 107 is a communication interface for connecting peripheral devices to the classical computer 100. For example, a memory device 35 or a memory reader / writer 36 can be connected to the device connection interface 107. The memory device 35 is a recording medium equipped with a function for communicating with the device connection interface 107. The memory reader / writer 36 is a device for writing data to the memory card 37 or reading data from the memory card 37. The memory card 37 is a card-type recording medium.

[0058] The network interface 108a is connected to the network 30. The network interface 108a transmits and receives data to and from other computers or communication devices via the network 30. The network interface 108a is a wired communication interface connected by a cable to a wired communication device such as a switch or a router. The network interface 108a may also be a wireless communication interface connected by radio waves to a wireless communication device such as a base station or an access point.

[0059] The network interface 108b is an interface for connecting to the quantum computer 200. The processor 101 transmits a quantum circuit to the quantum computer 200 via the network interface 108b and causes the quantum computer 200 to execute a quantum computation. The processor 101 also obtains the result of the quantum computation via the network interface 108b.

[0060] The classical computer 100 can realize the processing functions of the second embodiment with the hardware described above. The device shown in the first embodiment can also be realized with hardware similar to that of the classical computer 100 shown in FIG.

[0061] The classical computer 100 realizes the processing functions of the second embodiment by executing a program recorded on, for example, a computer-readable recording medium. The program describing the processing to be executed by the classical computer 100 can be recorded on various recording media. For example, the program to be executed by the classical computer 100 can be stored in a storage device 103. The processor 101 loads at least a portion of the program in the storage device 103 into the memory 102 and executes the program. The program to be executed by the classical computer 100 can also be recorded on a portable recording medium such as an optical disk 34, a memory device 35, or a memory card 37. The program stored on the portable recording medium becomes executable after being installed on the storage device 103, for example, under the control of the processor 101. The processor 101 can also read and execute the program directly from the portable recording medium.

[0062] Quantum computer 200 includes a control device 210 and a quantum device 220. Control device 210 performs gate operations on quantum bits in the quantum device according to a quantum circuit. Quantum device 220 includes multiple quantum bits. Quantum device 220 may be, for example, one or multiple quantum processing units (QPUs).

[0063] Next, we will explain quantum circuits that can be executed by the quantum computer 200. In a quantum circuit, operations to be performed on quantum bits are represented by an array of quantum gates. Figure 4 shows an example of a quantum circuit. Unlike classical bits, which can only be in the state "0" or "1," quantum bits can be in a superposition state |ψ> of "0" and "1." The superposition state |ψ> is expressed by the following equation (1).

[0064] |ψ>=α|0>+β|1> (1) |0> (zeroket) corresponds to the state corresponding to 0 of the classical bit. |1> (iteket) corresponds to the state corresponding to 1 of the classical bit. α and β are complex numbers and are called probability amplitudes. When the state |ψ> is measured, |α| 2 |0> is observed with probability |β| 2 |1> is observed with probability |α| 2 +|β| 2 =1.

[0065] In a quantum circuit, quantum bits are described vertically. In addition, operations on each quantum bit are described chronologically from left to right. Operations on quantum bits are called quantum gates. A quantum gate that operates on N quantum bits is called an N-qubit gate.

[0066] In the example of quantum circuit 40 in FIG. 4, first, two quantum bits q1 and q2 exist (T1). Next, a Hadamard gate (H gate) acts on quantum bit q1 (T2). Next, a CNOT gate acts on quantum bits q1 and q2, with quantum bit q1 as the control bit (T3). Both the H gate and the CNOT gate are types of quantum gates. Then, the values ​​of quantum bits q1 and q2 are measured (T4). In the measurement at T4, the values ​​of quantum bits q1 and q2 are read out.

[0067] However, NISQ computers are subject to noise during calculations, meaning that errors will occur probabilistically in the results of NISQ computer calculations. FIG. 5 is a diagram showing an example of a quantum circuit. The quantum circuit 41 indicates that |0> is inverted to |1> and observation is performed. The expected value of the measurement result of the quantum circuit 41 is |1>. However, when such a quantum circuit 41 is executed many times, due to the influence of noise, it is possible that |0> is observed, for example, once in 100 times. In this case, due to the influence of noise, a bit inversion occurs with an error rate of 1%.

[0068] Next, to explain the influence of noise on multiple quantum bits, the adjacent relationship between quantum bits will be illustrated. 6 is a diagram showing an example of the adjacency relationships of quantum bits. Graph 230 shows an example of the adjacency relationships of eight quantum bits q0 to q7 included in quantum device 220. Nodes in graph 230 represent quantum bits. An edge connecting two nodes indicates that the two quantum bits corresponding to those two nodes are adjacent. Graph 230 shows the adjacency relationships of each of the eight quantum bits q0 to q7.

[0069] The noise state differs for each qubit, so the frequency and magnitude of errors vary from qubit to qubit. FIG. 7 is a diagram showing an example of the error rate for each quantum bit. Graph 231 shows the error rate for each node and edge of graph 230. The numbers in the nodes indicate the error rate of the quantum bit measurement operation. For example, the error rate for the quantum bit q0 measurement operation is 0.2%. The error rate for the quantum bit q4 measurement operation is 2.1%. The numbers attached to the edges indicate the error rate that occurs in two quantum gate operations. For example, the error rate for two quantum gate operations for quantum bits q0 and q1 is 0.7%. The error rate for two quantum gate operations for quantum bits q2 and q4 is 5.2%.

[0070] However, there are various other types of errors that can occur besides the errors mentioned here. For example, there are errors that occur when manipulating a single quantum bit. There are also errors that occur when an operation on one quantum bit affects the state of another quantum bit (called crosstalk).

[0071] The classical computer 100 takes into consideration the noise state and switches the execution method and optimization method of the quantum circuit by the quantum computer 200. For example, the classical computer 100 avoids noisy quantum bits (physical quantum bits) and assigns the logical quantum bits of the quantum circuit to quantum bits (physical quantum bits) on the quantum device 220.

[0072] Alternatively, the classical computer 100 adjusts the quantum circuit optimization method and adjusts the degree of gate reduction so that the effects of noise are within an acceptable range. Here, quantum circuit optimization is a process of converting a quantum gate or combination of quantum gates in a quantum circuit into another quantum gate or combination of quantum gates, thereby reducing the number of gates and improving noise resistance. For example, when the noise is relatively large, the classical computer 100 applies multiple optimization algorithms and significantly reduces the number of gates over time. On the other hand, when the noise is relatively small, the classical computer 100 applies only a small number of optimization algorithms and completes the optimization process in a short time.

[0073] The frequency and magnitude of errors occurring in each quantum bit change over time. For this reason, the quantum computing system 300 periodically measures the noise state, grasps the latest noise state, and performs the optimization described above. Existing methods for measuring the noise state include the aforementioned RB, IRB, and SimRB. However, measuring the error rate using RB, IRB, and SimRB takes a long time.

[0074] The quantum computing system 300 provides a quantum computing environment as a quantum cloud service. Next, an example of how the quantum computing system 300 is used by a user will be described. 8 is a diagram showing an example of how a user uses the quantum computing system. First, the user defines a quantum circuit using a terminal device 401, 402, etc., and then uses the terminal device 401, 402, etc. to send a job to perform calculations using the defined quantum circuit to the quantum computing system 300. For example, user U1 uses the terminal device 401 to create a quantum program P1 that defines a quantum circuit, and sends a job corresponding to the quantum program P1 from the terminal device 401 to the quantum computing system 300. Furthermore, user U2 uses the terminal device 402 to create a quantum program P2 that defines a quantum circuit, and sends a job corresponding to the quantum program P2 from the terminal device 402 to the quantum computing system 300.

[0075] The classical computer 100 receives these jobs. For example, the classical computer 100 functions as a job scheduler that submits jobs to the quantum computer 200, and has an execution queue EQ1 that holds the jobs. The classical computer 100 stores the received jobs in the execution queue EQ1.

[0076] The job scheduler determines which job to execute next, extracts the job from execution EQ1, and executes it on quantum computers 200, 200a, and 200b. Here, quantum computers 200a and 200b are quantum computers included in quantum computing system 300. Then, the job scheduler obtains the execution results of the jobs from quantum computers 200, 200a, and 200b, and transmits the execution results to terminal devices 401 and 402 used by users U1 and U2.

[0077] Currently, the number of quantum computers and the number of available quantum bits in the quantum computing system 300 are both low. This means that job execution wait times are very long. In other words, the system is in a very congested state. It can take anywhere from 60 minutes to more than a day for a job to be executed after it enters the execution queue EQ1.

[0078] Therefore, in the quantum computing system 300, if existing processes such as RB, IRB, and SimRB are periodically executed to update noise information, user jobs cannot be executed while the processes are being executed, and user jobs are postponed, which contributes to congestion. Also, if the execution frequency of RB, etc. is increased, it becomes possible to provide more accurate and up-to-date noise information, but the congestion situation worsens accordingly.

[0079] Therefore, the quantum computing system 300 makes it possible to indirectly grasp the magnitude of noise of each quantum bit with relatively little additional processing cost without worsening the congestion situation of the quantum cloud service. Specifically, the classical computer 100 has the following functions.

[0080] 9 is a diagram illustrating an example of the functions of a classical computer. The classical computer 100 has an execution result storage unit 110, a job scheduler 120, an execution method adjustment unit 130, and a safety range update unit 140. The execution result storage unit 110 uses a storage area of ​​the memory 102 or the storage device 103. The job scheduler 120, the execution method adjustment unit 130, and the safety range update unit 140 are realized by the processor 101 executing a program stored in the memory 102. However, the job scheduler 120 may be realized by a classical computer other than the classical computer 100 that is included in the quantum computing system 300.

[0081] In the following, the quantum computer 200 will be mainly exemplified, but the classical computer 100 also performs the same processing as that performed on the quantum computer 200 on other quantum computers including the quantum computers 200a and 200b.

[0082] The execution result storage unit 110 stores information on the execution results of the quantum circuit by the quantum computer 200. The information held in the execution result storage unit 110 includes the execution history of the quantum circuit.

[0083] The job scheduler 120 holds jobs received from the terminal devices 401, 402, etc. in the execution queue EQ1. The job scheduler 120 selects the next job to be executed from the jobs held in the execution queue EQ1 and instructs the execution method adjustment unit 130. The job scheduler 120 obtains the execution results of the quantum circuit from the quantum computer 200 and responds to the terminal devices 401, 402, etc. that sent the jobs.

[0084] The execution method adjustment unit 130 adjusts the execution method of the job, i.e., the quantum circuit, based on the latest safety range determined by the safety range update unit 140. The safety range indicates the range of the number of gates allowed per quantum bit and the range of gate density for adjacent quantum bits. The gate density is the average number of gates for each quantum bit adjacent to the quantum bit of interest. In addition, the adjustment of the execution method involves adjusting quantum bit allocation and the degree of optimization.

[0085] The execution method adjustment unit 130 causes the quantum computer 200 to execute the quantum circuit based on the result of the execution method adjustment. The quantum computer 200 outputs the execution result of the quantum circuit to the classical computer 100. The execution result of the quantum circuit by the quantum computer 200 is stored in the execution result storage unit 110. In addition, the execution result of the quantum circuit by the quantum computer 200 is returned to the job scheduler 120.

[0086] The safety range update unit 140 updates the latest safety range at regular intervals based on the execution result of the quantum circuit within the time window. For example, the safety range update unit 140 stores information on the latest safety range in the execution result storage unit 110. The safety range update unit 140 notifies the execution method adjustment unit 130 of the latest safety range. Note that the time window is a time range within T seconds from the present time. The value of T is determined in advance.

[0087] Many representative quantum algorithms use superposition to parallelize multiple calculations, while using wave interference to amplify only the probability of the desired state occurring. In other words, the following can be expected regarding the success or failure of a quantum circuit: if the occurrence probability of each state is a partially amplified distribution, the calculation is likely to have been successful. On the other hand, if the occurrence probability of all states is roughly the same, i.e., close to a uniform distribution, the calculation is likely to have failed.

[0088] Therefore, by calculating the deviation (distance) between the output distribution of a quantum circuit and a uniform distribution, it is possible to estimate the success or failure of the execution of the quantum circuit and obtain information on the number of gates applied in the case of success or failure. For example, if the deviation (distance) from the uniform distribution is greater than or equal to a threshold, it is judged to be successful.

[0089] This allows us to indirectly estimate the magnitude of noise. For example, the number of gates that are acceptable for success, or the number of gates that are not acceptable, is an indicator that reflects the magnitude of noise. This indicator can be used to adjust the execution method of the quantum circuit. That is, it is possible to adjust the qubit allocation and the degree of minimization so that the number of gates is within the acceptable limit.

[0090] Next, we will explain the output when the quantum circuit is executed successfully / unsuccessfully. FIG. 10 is a diagram showing an example of a quantum circuit for the Grover algorithm. Quantum circuit 50 is an example of a quantum circuit for the Grover algorithm. "U3" in quantum circuit 50 indicates a unitary rotation gate. In the U3 gate, rotation angles around three axes in the Bloch sphere are specified. Also, "X" in quantum circuit 50 indicates an X gate that performs bit inversion.

[0091] In the quantum circuit 50, a calculation using five quantum bits q0 to q4 is performed, and a five-bit measurement value (c) is obtained. The desired state of the quantum circuit 50 is 11111. The quantum circuit 50 is executed under the conditions of no noise, small noise, and large noise. The number of executions (number of shots) is 1024. The basis gates are SX, CX, and RZ.

[0092] The error rate, that is, the magnitude of noise, is as follows for small noise and large noise. In the case of low noise, the error rate for one quantum gate is 0.5%, the error rate for two quantum gates is 1%, the error rate for misjudging 0 as 1 in measurement is 1%, and the error rate for misjudging 1 as 0 in measurement is 5%.

[0093] In the case of high noise, the error rate for one quantum gate is 1%, the error rate for two quantum gates is 5%, the error rate for misjudging 0 as 1 in measurement is 1%, and the error rate for misjudging 1 as 0 in measurement is 5%.

[0094] In the absence of noise, all error rates are 0%. The output distributions obtained for the quantum circuit 50 in the absence of noise, small noise, and large noise cases are as follows: FIG. 11 shows examples of output distributions depending on noise. FIG. 11(A) illustrates an output distribution 60 when there is no noise. FIG. 11(B) illustrates an output distribution 61 when there is little noise. FIG. 11(C) illustrates an output distribution 62 when there is much noise. The horizontal axis of the output distributions 60, 61, and 62 indicates the measured state. The vertical axis of the output distributions 60, 61, and 62 indicates the observation probability.

[0095] The degree of deviation between each output distribution and the uniform distribution is expressed, for example, by the Hellinger distance. The Hellinger distance between output distribution 60 and the uniform distribution is 0.4965. The Hellinger distance between output distribution 61 and the uniform distribution is 0.1210. The Hellinger distance between output distribution 62 and the uniform distribution is 0.0426. Thus, the greater the noise, the closer the distribution approaches the uniform distribution, and the greater the probability that a state other than the desired state will be observed.

[0096] Therefore, the safe range update unit 140 can compare the deviation between each output distribution and the uniform distribution with a threshold value to determine whether the execution of the quantum circuit 50 has been successful. For example, the safe range update unit 140 can determine that the execution has been successful when the deviation is equal to or greater than the threshold value, and can determine that the execution has failed when the deviation is smaller than the threshold value.

[0097] Note that a measure other than the Hellinger distance may be used as the divergence. As described above, other measures such as the Kullback-Leibler divergence, the Jensen-Shannon divergence, the Wasserstein distance, and the Shannon entropy may be used as the divergence.

[0098] Next, the processing procedure of the classical computer 100 will be explained. 12 is a flowchart showing an example of a safe range update. The classical computer 100 executes the following safe range update at a predetermined cycle.

[0099] (S10) The safe range update unit 140 updates the set of quantum circuits CS T For example, the safe range update unit 140 acquires the quantum circuit set CS based on the execution history of the quantum circuit stored in the execution result storage unit 110. T can be obtained.

[0100] (S11) The safe range update unit 140 updates each quantum circuit c∈CS T Steps S12 to S15 are repeatedly executed each time. (S12) The safety range update unit 140 determines whether the output expected value of the quantum circuit c is a partial amplification distribution. If the output expected value of the quantum circuit c is a partial amplification distribution, the process proceeds to step S13. If the output expected value of the quantum circuit c is not a partial amplification distribution, the process proceeds to step S11, and the next quantum circuit c∈CS T is selected. Step S12 is referred to as determination process A. Details of determination process A will be described later.

[0101] (S13) The safety range update unit 140 determines whether the execution of quantum circuit c was successful. If it is determined that the execution of quantum circuit c was successful, the process proceeds to step S14. If it is determined that the execution of quantum circuit c was unsuccessful, the process proceeds to step S15. The determination of the success or failure of the execution in step S13 is made based on a comparison between the output distribution of quantum circuit c and a uniform distribution. Step S13 is referred to as determination process B. Details of determination process B will be described later.

[0102] (S14) The safety range update unit 140 updates the gate number information upon successful execution. Then, the process proceeds to step S16. The gate number information upon successful execution indicates the applied gate number and applied gate density for each quantum bit of the quantum circuit c upon successful execution.

[0103] (S15) The safety range update unit 140 updates the gate number information at the time of execution failure. The gate number information at the time of execution failure indicates the number of applied gates and applied gate density for each quantum bit of the quantum circuit c that has failed to execute.

[0104] (S16) The safe range update unit 140 updates each quantum circuit c∈CS T When the repetition of each step is completed, the process proceeds to step S17. (S17) The safety range update unit 140 calculates the safety range of the number of gates / density applied for each quantum bit from the gate number information when the execution succeeded / failed. Then, the safety range update process ends. Details of the gate number information and safety range information will be described later.

[0105] As mentioned above, in many representative quantum algorithms such as QAOA, VQE, Grover's algorithm, and Shor's algorithm, the output expectation of a quantum circuit is a partially amplified distribution. However, in algorithms that involve iteration (VQA) such as QAOA and VQE, the desired state is approached through iterations, so the output expectation near the final iteration is a partially amplified distribution.

[0106] Furthermore, it is expected that most of the quantum circuits transmitted to the quantum computing system 300 will have output expected values ​​that follow a partial amplification distribution. However, there may be cases where quantum circuits whose output expected values ​​do not follow a partial amplification distribution are transmitted. An example of a quantum circuit whose output expected values ​​do not follow a partial amplification distribution is a circuit made up of a random gate array, i.e., a random circuit.

[0107] From step S13 onwards, it is assumed that the output expected value of quantum circuit c will be a partial amplified distribution, so in decision process A of step S12, it is determined whether the output expected value of quantum circuit c will be a partial amplified distribution, and step S13 is executed only if it is a partial amplified distribution.

[0108] 13 is a flowchart showing an example of the determination process A. The determination process A corresponds to step S12. (S20) The safe range update unit 140 determines whether or not the quantum circuit c was executed near the final iteration of the "quantum algorithm with iterations, in which a partial amplification distribution is the final expected value." If the quantum circuit c was executed near the final iteration of the "quantum algorithm with iterations, in which a partial amplification distribution is the final expected value," the process proceeds to step S23. If the quantum circuit c was not executed near the final iteration of the "quantum algorithm with iterations, in which a partial amplification distribution is the final expected value," the process proceeds to step S21.

[0109] (S21) The safety range update unit 140 determines whether or not the quantum circuit c includes a gate pattern specific to a quantum algorithm that uses a partial amplification distribution as an expected value. If the quantum circuit c includes a gate pattern specific to a quantum algorithm that uses a partial amplification distribution as an expected value, the process proceeds to step S23. If the quantum circuit c does not include a gate pattern specific to a quantum algorithm that uses a partial amplification distribution as an expected value, the process proceeds to step S22.

[0110] (S22) The safe range update unit 140 determines that the output expected value of the quantum circuit c is not a partial amplification distribution. Then, the determination process A ends. (S23) The safe range update unit 140 determines that the output expected value of the quantum circuit c is a partially amplified distribution. Then, the determination process A ends.

[0111] In this way, the safety range update unit 140 performs the determination process A by detecting that the "quantum algorithm in which the output expected value is partially amplified distribution" has been executed. For example, in step S20, the safe range update unit 140 first detects that the user has executed an iterative quantum algorithm (VQA) such as VQE. The safe range update unit 140 can perform this detection by detecting that an API (Application Programming Interface) for VQA has been executed or that the quantum circuit c matches a typical ansatz circuit used in VQE or the like. Then, if the quantum circuit c was executed towards the end of the VQA execution period, the safe range update unit 140 determines Yes in step S20.

[0112] Next, an example of the quantum algorithm (VQA) detected in step S20 will be described. FIG. 14 shows an example of a quantum algorithm involving iteration. FIG. 14(A) illustrates source code 70 of an API for executing VQE. The API is provided by an SDK (Software Development Kit) for using quantum cloud services. FIG. 14(B) illustrates a typical ansatz circuit 51 used in VQE and the like. The ansatz circuit 51 shows an example of a three-qubit TwoLocal configuration.

[0113] When the quantum computing system 300 provides an API indicated by the source code 70 for executing VQA, the safety range update unit 140 determines that a quantum algorithm involving iteration has been executed when the API has been executed.

[0114] Alternatively, the safe range update unit 140 determines that a quantum algorithm involving iterations has been executed when the quantum circuit c matches a typical ansatz circuit 51 used in VQE or the like. Here, typical ansatz circuits (TwoLocal, RealAmplitudes, etc.) have fixed shapes. Therefore, the safe range update unit 140 can detect that a quantum algorithm involving iterations, such as VQE, has been executed from the match between the typical ansatz circuit and the quantum circuit c.

[0115] Furthermore, as described above, in step S20, the safety range update unit 140 also determines whether or not the quantum circuit c was executed at the end of the VQA (or VQE) execution period. FIG. 15 is a diagram showing an example of a quantum circuit executed at the end of an execution period. The execution result storage unit 110 holds the execution history of multiple quantum circuits requested for execution by multiple users. The execution history is information in which the execution results of multiple quantum circuits are arranged in order of execution time. A time chart 80 shows the execution history of multiple quantum circuits. The direction from left to right on the time chart 80 is the positive direction of time. The time window W T is a period within T seconds from the present time, and is the target period for the safety range update process. The VQE execution period is a period during which the quantum circuit for VQE is executed. The end of the VQE execution period is a period during which a predetermined number of quantum circuits (four in the example of FIG. 15) up to the final quantum circuit in the VQE execution period are executed. This predetermined number is determined in advance. In the example of FIG. 15, quantum circuit c is the quantum circuit executed at the end of the VQE execution period.

[0116] When the safe range update unit 140 detects that the quantum circuit c has been executed by VQE and that it was executed towards the end of the VQE execution period, the result of the determination in step S20 is Yes.

[0117] Next, a specific example of the determination in step S21 will be described. FIG. 16 is a diagram showing an example of a gate pattern in which a partial amplification distribution is used as an expected output value. As mentioned above, the Grover algorithm is an example of a quantum algorithm in which a partial amplification distribution is used as an expected output value. In the Grover algorithm, a gate pattern 52 appears repeatedly. The gate pattern 52 shows an example of a gate pattern specific to the Grover algorithm. The quantum circuit 50 in FIG. 10 is an example of an overall image of a quantum circuit for the Grover algorithm.

[0118] In step S21, if the gate pattern 52 is included in the quantum circuit c, the safe range update unit 140 determines that the quantum circuit c is a quantum circuit of the Grover algorithm, and the result of step S21 is Yes.

[0119] In this way, the safety range update unit 140 can determine whether the output expected value of quantum circuit c is a partial amplification distribution based on whether quantum circuit c includes a gate pattern specific to a quantum algorithm that has a partial amplification distribution as the output expected value.

[0120] In step S21, the safe range update unit 140 determines whether the quantum circuit c has features specific to each quantum algorithm. Therefore, the safe range update unit 140 may create a machine learning model to make the determination, rather than determining whether a gate pattern is included. That is, for example, the safe range update unit 140 may receive, as input, feature quantities corresponding to the structure of the quantum circuit, and train a machine learning model that outputs the name of the quantum algorithm. Then, the safe range update unit 140 may use the machine learning model to determine whether the quantum circuit c is a "quantum algorithm whose output expected value is a partially amplified distribution."

[0121] In this way, if the answer is Yes in step S20 or step S21, the safe range update unit 140 determines that the output expected value of the quantum circuit c is a partially amplified distribution. 17 is a flowchart showing an example of the determination process B. The determination process B corresponds to step S13.

[0122] (S30) The safe range update unit 140 calculates the Hellinger distance D between the output distribution of the quantum circuit c and the uniform distribution. The Hellinger distance D is an example of the degree of deviation between the output distribution of the quantum circuit c and the uniform distribution.

[0123] (S31) The safe range update unit 140 determines whether the Hellinger distance D is equal to or greater than a threshold (D≧threshold). If D≧threshold, the process proceeds to step S32. If D<threshold, the process proceeds to step S33.

[0124] (S32) The safe range update unit 140 determines that the execution was successful for the quantum circuit c. Then, the determination process B ends. (S33) The safe range update unit 140 determines that the execution of the quantum circuit c has failed, and the determination process B ends.

[0125] Next, a specific example of the determination process B will be explained using two quantum circuits of the Grover algorithm with different depths as examples. These two quantum circuits are assumed to be executed with the same noise level. Furthermore, the threshold value in step S31 is set to D=0.06. First, of the two quantum circuits with different depths, the shallower quantum circuit will be illustrated.

[0126] 18 is a diagram showing an example (part 1) of a quantum circuit. The quantum circuit 53 is an example of a quantum circuit of the Grover algorithm. The quantum circuit 53 corresponds to a shallow quantum circuit. 19 is a diagram showing an example (part 1) of the output distribution. Output distribution 63 shows an example of the output distribution of quantum circuit 53. The horizontal axis of output distribution 63 indicates a state represented by a set of five quantum bit values, and the vertical axis indicates the observation probability of that state. In the example of output distribution 63, the Hellinger distance D from the uniform distribution is 0.0625. Therefore, since D=0.0625≧threshold TD=0.06, the safety range update unit 140 determines that the quantum circuit 53 has successfully executed.

[0127] Next, we will explain the deeper quantum circuit of the two quantum circuits with different depths. FIG. 20 is a diagram showing an example (part 2) of a quantum circuit. The quantum circuit 54 is an example of a quantum circuit of the Grover algorithm. The quantum circuit 54 corresponds to a deep quantum circuit. In the quantum circuit 54, a pattern P is repeated three times. The pattern P is a gate pattern specific to the Grover algorithm.

[0128] 21 is a diagram showing an example (part 2) of the output distribution. Output distribution 64 shows an example of the output distribution of quantum circuit 54. The horizontal axis of output distribution 64 indicates a state represented by a set of five quantum bit values, and the vertical axis indicates the observation probability of that state. In the example of output distribution 64, the Hellinger distance D from the uniform distribution is 0.0398. Therefore, since D=0.0398<threshold value TD=0.06, the safety range update unit 140 determines that the quantum circuit 54 has failed to execute.

[0129] Note that even for the same quantum circuit, the success / failure of execution changes depending on the magnitude of noise. For example, for the output distribution 61 (in the case of small noise) and the output distribution 62 (in the case of large noise) in FIG. 11 described above, the threshold TD is set to 0.06. Then, the safety range update unit 140 determines that the output distribution 61 in the case of small noise is an execution success. On the other hand, the safety range update unit 140 determines that the output distribution 62 in the case of large noise is an execution failure.

[0130] Next, an example of updating the gate number information in steps S14 and S15 will be described. 22 is a diagram showing an example of gate number information when execution is successful / failed. The combination of the execution success / failure information and the number / density of gates included in quantum circuit c is an index that indirectly reflects the magnitude of noise. For example, the number / density of gates that increases the probability of success changes depending on the magnitude of noise.

[0131] Therefore, the safe range update unit 140 updates the quantum bit q i (Physical qubit q i ) and the total number of 1-quantum gates and 2-quantum gates applied to the qubit q. i The number of gates to be applied is G(P1,P2,q i ) P1 is set to "S" (successful execution) or "F" (failed execution). P2 is set to "1q" (one quantum gate) or "2q" (two quantum gates). The reason for counting one quantum gate and two quantum gates separately is that the error rates for each gate typically differ greatly.

[0132] Furthermore, the safe range update unit 140 updates the quantum bit q for the quantum circuit c. i We calculate the density of one quantum gate and the density of two quantum gates applied to the surrounding area including qubit q. i The density of quantum gates is calculated by dividing the total number of 1-qubit gates applied to the surrounding area by the number of qubits in the surrounding area. i is the total number of quantum gates applied to the peripheral region of the device divided by the number of quantum bits in the peripheral region.

[0133] Here, each qubit is often affected by crosstalk from surrounding qubits. Therefore, as an index that reflects the influence of crosstalk, we calculate the density of the number of applied gates taking into account the surrounding area, i.e., the average number of gates per qubit. i The density of quantum gates applied to the surrounding area of ​​GD(P1,P2,q i ) where D stands for density. The settings for P1 and P2 are G(P1,P2,q i ) is the same as the surrounding area, q i The number of adjacent bits to be considered is determined in advance. For example, i Alternatively, the peripheral region may be a region of one bit, i.e., a region of one edge adjacent to the quantum bit q. i In contrast, the peripheral region may be a range of two bits, that is, a range of adjacent quantum bits separated by a maximum of two edges.

[0134] The gate number information 111 is G(P1, P2, q i ) and GD(P1,P2,q i ) is an example of information that holds the number of gates information 111. The number of gates information 111 is stored for each quantum circuit in, for example, the execution result storage unit 110. The number of gates information 111 is stored in the quantum bits of the QPU, G(S, 1q, q i ), G(S,2q,q i ), GD(S,1q,q i ) and GD(S,2q,q i ) items.

[0135] The QPU qubit section includes the qubit q in quantum device 220. i , i.e., the physical qubit q i The identification information of G(S,1q,q i ) item is G(S,1q,q i ) is registered. i The value of G(S,2q,qi) is registered in the field of GD(S,1q,q i ) item is GD(S,1q,q i ) is registered. i ) item is GD(S,2q,q i ) value is registered.

[0136] The gate number information 111 in FIG. 22 is G(P1, P2, q i ) and GD(P1,P2,q i ) is shown as an example. The adjacency relationship of the quantum bits q0 to q7 is expressed by a graph 230. The basis gates, that is, the basis quantum gates are SX, CX, and RZ. In addition, the quantum bit q i is the quantum bit q of the quantum device 220. i shall be allocated to

[0137] G is the quantum bit q i is the number of gates applied to the quantum circuit 53, which is a count value after decomposing each quantum gate into basis gates. i is the density of the number of gates applied in the area around the qubit q i The area around the qubit q i Let us assume that the range that can be reached by one edge is the range up to one adjacent quantum bit.

[0138] For example, the gate number information 111 includes, for the quantum bit q0, G(S,1q,q i ) = 29, G(S, 2q, q i ) = 38, GD(S,1q,q i) = 51, GD(S, 2q, q i )=77. i =q0.

[0139] Number of gates information 111 has similar records for the other quantum bits q1 to q4. However, since quantum bits q5 to q7 of quantum device 220 were not used in the quantum circuit corresponding to number of gates information 111, "N / A" (Not Available) is entered in each item for those quantum bits q5 to q7.

[0140] Here, for example, GD(S,1q,q0) is calculated as follows: The area surrounding quantum bit q0 corresponds to quantum bits q0, q1, and q2. Therefore, the gate density in the area surrounding quantum bit q0, i.e., the average number of gates per quantum bit, GD(S,1q,q0), is calculated as GD(S,1q,q0) = (29 + 57 + 68) / 3 ≒ 51.

[0141] Furthermore, GD(S,2q,q3) is calculated as follows. The area surrounding qubit q3 corresponds to qubits q1, q2, and q3. Note that qubit q5 is not used, so it is excluded from the density calculation. Therefore, the gate density of the area surrounding qubit q3, i.e., the average number of gates per qubit, GD(S,1q,q3), is calculated as GD(S,1q,q3) = (67 + 127 + 86) / 3 ≒ 93.

[0142] Then, in step S17, the safety range update unit 140 performs the following process: First, the safety range update unit 140 updates the time window W T Based on the G and GD calculated for each quantum circuit c in the i ) The range of values ​​for GD is RGD(P1,P2,q i ) where R stands for range.

[0143] For example, the time window W TThe set of quantum circuits executed within the 1000} The safety range update unit 140 finds G and GD for each cj included in the set.

[0144] RG(S,1q,q i ) is c1~c 1000 G(S,1q,q i ) is determined as the minimum to maximum value. For example, RG(S,1q,q i ) = 20~153.

[0145] Similarly, the safety range update unit 140 updates c1 to c2 for all combinations of S / F (success / failure), 1q / 2q, and q0 to q7. 1000 RG and RGD are calculated from the minimum and maximum values ​​of G and GD.

[0146] Furthermore, the safety range update unit 140 checks the overlap of the ranges of the number of gates when the execution is successful / failed based on RG, and calculates the safety range SRG(P2,q i ) and the quasi-safety range SSRG(P2,q i ) is calculated for each quantum bit. Here, the S in SRG stands for safe. The SS in SSRG stands for semisafe.

[0147] Furthermore, the safety range update unit 140 checks the overlap of the gate density ranges when the execution is successful / failed based on the RGD, and updates the safety range SRGD(P2,q i ) and the quasi-safety range SSRGD(P2,q i ) for each quantum bit.

[0148] It should be noted that P2 of SRG, SSRG, SRGD, and SSRGD is set to either "1q" (one quantum gate) or "2q" (two quantum gates). The safety range SRG / SRGD is a range of gate count / density where only successful cases exist. The quasi-safe range SSRG / SSRGD is a range of gate count / density where successful cases and unsuccessful cases exist together. The safety range update unit 140 adds the "interval of gate count / density that is greater than or equal to 0 and less than L" to the safety range SRG / SRGD. Here, L is the smaller of the minimum value of the safety range and the minimum value of the quasi-safe range. The likelihood of success decreases in the order of safety range > quasi-safe range > other ranges.

[0149] Here, there may be other reasons for the failure of quantum circuit execution besides noise. For example, in VQA, convergence to a desired state may not occur due to reasons such as insufficient expressive power of the ansatz circuit (insufficient parameters) or an inappropriate optimization algorithm. For this reason, the safe range update unit 140 uses gate number information when execution is successful as the core of its index, and gate number information when execution fails as only additional information. The safe range update unit 140 does not use a range of gate numbers that only includes failure cases as an index.

[0150] 23A and 23B are diagrams illustrating an example of calculation of the safety range of the number of applicable gates. Fig. 23A illustrates a relationship 90 between RG(S, 1q, q0), RG(F, 1q, q0), the safety range SRG(1q, q0), and the quasi-safety range SSRG(1q, q0). Fig. 23B illustrates a relationship 91 between RGD(S, 1q, q0), RGD(F, 1q, q0), and the safety range SRGD(1q, q0).

[0151] In the example of FIG. 23, it is assumed that RG(S, 1q, q0)=20 to 90, RG(F, 1q, q0)=70 to 200, RGD(S, 1q, q0)=25 to 70, and RGD(F, 1q, q0)=90 to 190.

[0152] In this case, as shown by the relationship 90, SRG(1q, q0) = 0 to 69, and SSRG(1q, q0) = 70 to 90. Furthermore, as shown in relationship 91, SRGD(1q, q0) = 0 to 70. Note that, for RGD(S, 1q, q0) = 25 to 70 and RGD(F, 1q, q0) = 90 to 190, there is no overlapping range, so SSRGD(1q, q0) = none.

[0153] The safe range update unit 140 can calculate SRG, SSRG, SRGD, and SSRGD in the same way for other quantum bits and two-quantum gates. FIG. 24 is a diagram illustrating an example of the safety range information.

[0154] The safe range information 112 is information that holds SRG, SSRG, SRGD, and SSRGD for each quantum bit. The safe range information 112 is stored in, for example, the execution result storage unit 110. The safe range information 112 holds the quantum bits of the QPU, SRG(1q,q i ), SSRG(1q,q i ), SRGD(1q,q i ), SSRGD(1q,q i ), SRG(2q,q i ), SSRG(2q,q i ), SRGD(2q,q i ), SSRGD(2q,q i ) items.

[0155] The QPU qubit section includes the qubit q in quantum device 220. i , i.e., the physical qubit q i The identification information of SRG(1q,q i ) item, SRG(1q,q i ) value is registered. i ) item, SSRG(1q,q i ) value is registered. i ) item, SRGD(1q,q i ) value is registered. i ) item, SSRGD(1q,q i ) value is registered. i ) item, SRG(2q,qi ) value is registered. i ) item, SSRG(2q,q i ) value is registered. i ) item, SRGD(2q,q i ) value is registered. i ) item, SSRGD(2q,q i ) value is registered.

[0156] For example, the safe range information 112 includes SRG(1q,q i ) = 0 to 69, SSRG(1q,q i )=70~90, SRGD(1q,q i ) = 0 to 70, SSRGD(1q,q i ) = None, SRG(2q,q i ) = 0 to 30, SSRG(2q,q i ) = None, SRGD(2q,q i ) = 0 to 25, SSRGD(2q,q i )=26 to 40. i =q0.

[0157] Safe range information 112 also has records containing the values ​​of SRG, SSRG, SRGD, and SSRGD for the other quantum bits q1 to q7, similar to quantum bit q0. The execution method adjustment unit 130 adjusts the execution method of a quantum circuit to be newly executed based on the safe range information 112. Next, the processing procedure when a quantum circuit is executed based on the safe range information 112 will be described.

[0158] FIG. 25 is a flowchart showing an example of processing when a quantum circuit is executed. (S40) The execution method adjustment unit 130 performs adjustment processing of the quantum circuit execution method upon receiving an instruction to execute the quantum circuit from the job scheduler 120. Details of this adjustment processing will be described later.

[0159] (S41) Based on the result of the adjustment process in step S40, the execution method adjustment unit 130 instructs the quantum computer 200 to execute the quantum circuit. The quantum computer 200 executes the quantum circuit based on the instruction from the execution method adjustment unit 130. Then, the processing during quantum circuit execution ends.

[0160] Here, the result of the adjustment process by the execution method adjustment unit 130 indicates the correspondence (quantum bit allocation) between the logical quantum bits of the quantum circuit and the physical quantum bits of the quantum device 220 (QPU).

[0161] FIG. 26 is a flowchart showing an example of adjustment processing in the quantum circuit execution method. The adjustment process of the quantum circuit execution method corresponds to step S40. (S50) The execution method adjustment unit 130 sets the degree of optimization for the quantum circuit to be executed to the minimum, that is, the lightest optimization.

[0162] (S51) The execution method adjustment unit 130 creates candidates M1, M2, ... for quantum bit allocation. Here, as described above, quantum bit allocation indicates the correspondence between logical quantum bits in a quantum circuit and physical quantum bits on the quantum device 220 (QPU).

[0163] (S52) The execution method adjustment unit 130 determines the allocation M for all quantum bits (physical quantum bits) such that the number of gates / density falls within the safety range indicated by the safety range information 112. a1 ,M a2 Determine whether ,... exists. M a1 ,M a2 If there are any, the process proceeds to step S53. a1 ,M a2 If no such list exists, the process proceeds to step S54.

[0164] (S53) The execution method adjustment unit 130 a1 ,M a2 For example, the execution method adjustment unit 130 may adopt any one of M a1 ,Ma2 ,... may be randomly selected, and the adjustment process is then complete.

[0165] (S54) The execution method adjustment unit 130 determines the allocation M for all quantum bits (physical quantum bits) such that the number of gates / density falls within the safe range or quasi-safe range indicated by the safe range information 112. b1 ,M b2 Determine whether ,... exists. M b1 ,M b2 If there are any, the process proceeds to step S55. b1 ,M b2 If no such list exists, the process proceeds to step S56.

[0166] (S55) The execution method adjustment unit 130 b1 ,M b2 ,..., the one with the largest number of qubits that fall within the safety range is adopted. Then the adjustment process ends. (S56) The execution method adjustment unit 130 executes optimization of the quantum circuit.

[0167] (S57) The execution method adjustment unit 130 creates candidates M1, M2, . . . for allocation of quantum bits. (S58) Execution method adjustment unit 130 determines whether the maximum number of quantum bits that fall within the safe range or quasi-safe range has increased as a result of optimization. If the maximum number of quantum bits that fall within the safe range or quasi-safe range has increased, processing proceeds to step S60. If the maximum number of quantum bits that fall within the safe range or quasi-safe range has not increased, processing proceeds to step S59.

[0168] (S59) The execution method adjustment unit 130 adopts the execution method M1, M2, ... that has the largest number of quantum bits that fall within the safe range or semi-safe range, and the adjustment process then ends.

[0169] (S60) The execution method adjustment unit 130 increases the degree of optimization, and the process then proceeds to step S52. Next, an example of adjusting the execution method of a quantum circuit based on the safe range information 112 will be described.

[0170] FIG. 27 is a diagram showing an example of the number of gates / density of a quantum circuit. Below, an example of adjusting the execution method for quantum circuit c having the gate count / density shown in table 113 is shown. For example, table 113 may be created by execution method adjustment unit 130 based on quantum circuit c and stored in execution result storage unit 110. Quantum circuit c includes three quantum bits q0 to q2. The gate density is the average number of gates in a region including one adjacent quantum bit. The average number of gates corresponds to GD.

[0171] The number of 1 quantum gates (1 qubit gates), 1 quantum gate density, number of 2 quantum gates (2 qubit gates), and 2 quantum gate density for quantum bit q0 are "100," "105," "20," and "30," respectively.

[0172] The number of single quantum gates, the density of single quantum gates, the number of double quantum gates, and the density of double quantum gates for the quantum bit q1 are "110," "93," "40," and "27," respectively. The number of single quantum gates, single quantum gate density, number of double quantum gates, and double quantum gate density of the quantum bit q2 are "70," "90," "20," and "29," respectively.

[0173] The execution method adjustment unit 130 allocates and optimizes qubits so that the gate count / density of as many qubits as possible falls within a safe range or a quasi-safe range, as follows: First, the execution method adjustment unit 130 sets the degree of optimization to the minimum.

[0174] Next, the execution method adjustment unit 130 generates quantum bit allocation candidates M1, M2, .... The execution method adjustment unit 130 can use any quantum bit allocation method to generate the quantum bit allocation candidates M1, M2, ....

[0175] For example, the execution method adjustment unit 130 may i) is assigned to the quantum bit with the largest maximum value, and the quantum bit with the largest 2-quantum gate density in the quantum circuit c is assigned to the quantum bit with the largest maximum value. This is a method of assigning quantum bits with small error rates first. i ) is considered to be an index that is inversely correlated with the error rate, so SRGD(2q,q i ) is assigned first. This gives us the following allocation candidates M1 and M2:

[0176] M1:(q3->q0),(q2->q2),(q4->q1) M2:(q2->q0),(q3->q2),(q4->q1) Here, "->" is an arrow going from left to right. The left side of the arrow is the quantum bit number of quantum device 220 (QPU), and the right side of the arrow is the quantum bit number of quantum circuit c. For example, (q3->q0) indicates that physical quantum bit q3 of quantum device 220 is assigned to logical quantum bit q0 of quantum circuit c.

[0177] In addition, for both M1 and M2, none of q0, q1, and q2 of quantum circuit c fall within the quasi-safe range. The execution method adjustment unit 130 performs the determination in step S52 for M1 and M2. In this case, neither M1 nor M2 satisfies the condition in step S52. Therefore, the execution method adjustment unit 130 determines No in step S52.

[0178] Then, the execution method adjustment unit 130 performs the determination in step S54 for M1 and M2. In this case, neither M1 nor M2 satisfies the condition in step S54. Therefore, the execution method adjustment unit 130 determines No in step S54.

[0179] Then, the execution method adjustment unit 130 performs optimization in step S56 on quantum circuit c to reduce the number of gates. Because this is the first optimization run on quantum circuit c, the degree of optimization is minimum.

[0180] FIG. 28 is a diagram showing an example of gate count / density after optimization. Table 114 is an example of the gate counts / densities of quantum bits q0 to q3 of quantum circuit c after optimization. For example, table 114 may be created by execution method adjustment unit 130 based on quantum circuit c after optimization, and stored in execution result storage unit 110.

[0181] The number of 1 quantum gates, 1 quantum gate density, number of 2 quantum gates, and 2 quantum gate density of the quantum bit q0 are "80," "85," "18," and "23," respectively. The number of single quantum gates, the density of single quantum gates, the number of double quantum gates, and the density of double quantum gates for the quantum bit q1 are "90," "77," "35," and "27," respectively.

[0182] The number of single quantum gates, the density of single quantum gates, the number of double quantum gates, and the density of double quantum gates for the quantum bit q2 are "60," "75," "15," and "25," respectively. The execution method adjustment unit 130 creates the quantum bit allocation candidates M1 and M2 again in the same way as the method illustrated in Fig. 27. In this way, the execution method adjustment unit 130 obtains the next M1 and M2.

[0183] M1:(q3->q1),(q2->q2),(q4->q0) M2:(q2->q1),(q3->q2),(q4->q0) In M1, q1 and q2 of quantum circuit c are within the safe range. q0 of quantum circuit c is outside the safe range but within the semi-safe range.

[0184] In M2, q2 of quantum circuit c is within the safe range. q0 and q1 of quantum circuit c are outside the safe range but within the semi-safe range. The execution method adjustment unit 130 performs the determination in step S58 for the newly created M1 and M2. Before optimization, the number of quantum bits that fall within the safe range or quasi-safe range for M1 is 0, and for M2 it is 0. The maximum value of these is 0.

[0185] After optimization, the number of qubits that are within the safe or semi-safe range is 3 for M1 and 3 for M2. The maximum of these is 3. Therefore, the new M1 and M2 satisfy the condition in step S58. Therefore, the execution method adjustment unit 130 determines "Yes" in step S58. Then, in step S60, the execution method adjustment unit 130 increases the degree of optimization, and the process proceeds to step S52.

[0186] The execution method adjustment unit 130 performs the determination in step S52 for the new M1 and M2. Since there are quantum bits in M1 and M2 that are not within the safety range, neither M1 nor M2 satisfies the condition in step S52. Therefore, the execution method adjustment unit 130 determines No in step S52.

[0187] The execution method adjustment unit 130 performs the determination in step S54 for the new M1 and M2. Both M1 and M2 satisfy the condition in step S54. Therefore, the execution method adjustment unit 130 determines Yes in step S54.

[0188] Then, the execution method adjustment unit 130 selects the allocation destination of M1 or M2 that has the largest number of quantum bits that are within the safety range. In this case, the execution method adjustment unit 130 selects M1. Since the allocation has been decided to be M1, the execution method adjustment unit 130 ends the adjustment process of the execution method.

[0189] In this way, the classical computer 100 can use the safe range information 112 to adjust the execution method (qubit allocation and degree of optimization) of the quantum circuit. In addition to the above, safe range information 112 can also be used for the following purposes. For example, safe range information 112 can be used for any action that requires only a rough understanding of the noise level. More specifically, execution method adjustment unit 130 may monitor increases or decreases in the safe range (i.e., the number of gates / density allowed for successful execution) based on safe range information 112, and may identify the timing when recalibration is required by detecting an increase in the noise level. Recalibration refers to adjusting the control method of the quantum bit so that the error rate is reduced; for example, in the case of a superconducting quantum bit, this may involve adjusting the intensity of the microwaves irradiated.

[0190] Alternatively, the classical computer 100 may disclose the safety range information 112 to a user, thereby enabling the user to (roughly) understand the characteristics of the quantum device 220 (QPU). For example, instead of disclosing the specific error rate for each quantum bit, the safety range for each quantum bit, i.e., the number of gates required to increase the probability of success, may be disclosed. This allows the user to select the quantum device 220 (QPU) and quantum bits to use by looking at the safety range values. In other words, the classical computer 100 can assist the user in efficiently selecting the quantum device 220 (QPU) and quantum bits to use for executing a quantum circuit.

[0191] Furthermore, the noise estimation process by the classical computer 100 functions well even when the quantum cloud service is congested. For example, the greater the number and types of user jobs (quantum circuits) being executed, the more accurately an index value that reflects the magnitude of noise, i.e., the number of permissible / unpermissible gates, can be obtained. Furthermore, when the classical computer 100 is not congested, it may execute RB or the like to directly calculate the error rate.

[0192] As described above, the classical computer 100 executes the following processes. The processor 101 acquires multiple output distributions corresponding to multiple quantum circuits executed by the quantum computer 200 including multiple quantum bits. That is, the processor 101 acquires multiple output distributions indicating the distribution of output states of multiple quantum bits corresponding to each of the multiple quantum circuits when the multiple quantum circuits are each executed multiple times for the multiple quantum bits. The processor 101 determines whether each of the multiple quantum circuits has been executed successfully based on the degree of deviation between each of the multiple output distributions and a uniform distribution. The processor 101 estimates information about the noise of each of the multiple quantum bits based on the determination result of the execution success or failure of each of the multiple quantum circuits and the number of quantum gates applied to each of the multiple quantum bits in each of the multiple quantum circuits.

[0193] This allows the classical computer 100 to efficiently acquire information about noise for each quantum bit. The classical computer 100 does not need to measure noise using existing methods such as RM, and the use time of the quantum computer 200 is not restricted by noise measurement.

[0194] For example, in determining whether execution is successful, the processor 101 compares the deviation between the output distribution and the uniform distribution with a threshold. If the deviation is equal to or greater than the threshold, the processor 101 determines that the quantum circuit corresponding to the output distribution has executed successfully, and if the deviation is less than the threshold, the processor 101 determines that the quantum circuit has executed unsuccessfully.

[0195] This allows the classical computer 100 to efficiently determine whether or not a quantum circuit whose output expected value is a partially amplified distribution is executed successfully. In estimating the noise information, processor 101 acquires, for each successfully executed quantum circuit, first information indicating the number of quantum gates applied to each of the multiple quantum bits (physical quantum bits) in the quantum circuits that have been successfully executed. Processor 101 also acquires, for each unsuccessful quantum circuit, second information indicating the number of quantum gates applied to each of the multiple quantum bits in the quantum circuits that have been unsuccessfully executed. Processor 101 then generates safe range information indicating the range of the number of quantum gates that are allowable to be applied to each of the multiple quantum bits, based on the first information and second information acquired for each of the multiple quantum circuits.

[0196] This allows the classical computer 100 to efficiently acquire information about the noise of each quantum bit. As described above, the safe range information is information that indirectly reflects the noise of each quantum bit. The number of quantum gates applied to a quantum bit is, for example, the number of one-quantum gates and the number of two-quantum gates. The number of quantum gates may also be the number of basis gates (basis quantum gates) used in various quantum gates.

[0197] For example, the first information and the second information may include an average value of the number of quantum gates applied to a qubit and other qubits adjacent to the qubit. Furthermore, the safe range information may include a range of average values ​​of the number of quantum gates that are allowed to be applied to a qubit and other qubits adjacent to the qubit. For example, the safe range information may include not only information on the safe ranges SRG and SRGD but also information on the quasi-safe ranges SSRG and SSRGD, as exemplified by the above-mentioned safe range information 112.

[0198] This allows the classical computer 100 to obtain information about the noise for each quantum bit with higher accuracy. In addition, after generating the safe range information, when the processor 101 executes the first quantum circuit using a quantum computer, it adjusts the number of quantum gates applied to the quantum bit (physical quantum bit) used to execute the first quantum circuit to within the range indicated by the safe range information.

[0199] This allows the classical computer 100 to increase the probability of successful execution of the first quantum circuit. As a result, the classical computer 100 can increase the reliability of operations performed by the NISQ computer (quantum computer 200). Note that the processor 101 may adjust the average number of quantum gates applied to the qubit used to execute the first quantum circuit and other qubits adjacent to the qubit so that the average number of applied gates for these qubits falls within the range of the average number of applied gates indicated by the safe range information.

[0200] Furthermore, based on information about the second quantum circuit executed by the quantum computer 200 or a quantum algorithm program corresponding to the second quantum circuit, the processor 101 determines whether the output distribution of the quantum computer 200 for the second quantum circuit is expected to be a distribution in which the occurrence probability of a specific state is amplified (a partially amplified distribution). If the result of the determination is true, the processor 101 uses the output distribution for the second quantum circuit to estimate information about noise. If the result of the determination is false, the processor 101 does not use the output distribution for the second quantum circuit to estimate information about noise.

[0201] This allows the classical computer 100 to appropriately select a quantum circuit to be used for estimating information about noise, thereby improving the accuracy of the estimated information. For example, the processor 101 can determine whether the structure of the second quantum circuit corresponds to a specific quantum circuit structure or quantum algorithm whose output expectation value is a partial amplification distribution, and if so, determine to use the output of the second quantum circuit for estimating information about noise.

[0202] The information processing of the first embodiment can be realized by having the processing unit 12 execute a program. The information processing of the second embodiment can be realized by having the processor 101 execute a program. The program can be recorded on a computer-readable recording medium such as an optical disc 34 or a memory card 37.

[0203] For example, the program can be distributed by distributing a recording medium on which the program is recorded. Alternatively, the program may be stored in another computer and distributed via a network. A computer may store (install) a program recorded on a recording medium or a program received from another computer in a storage device such as memory 102 or storage device 103, and then read and execute the program from the storage device. [Explanation of symbols]

[0204] 10. Information processing equipment 11 Storage section 12 Processing section 20 Quantum Computer 21 graphs S1, S2 steps

Claims

1. acquiring a plurality of output distributions that indicate distributions of output states of the plurality of quantum bits corresponding to each of the plurality of quantum circuits when the plurality of quantum circuits are each executed a plurality of times for the plurality of quantum bits; determining whether each of the plurality of quantum circuits is executed successfully based on a deviation between each of the plurality of output distributions and a uniform distribution; estimating information about noise of each of the plurality of quantum bits based on the determination result of the success or failure of the execution of each of the plurality of quantum circuits and the number of quantum gates applied to each of the plurality of quantum bits in each of the plurality of quantum circuits; A noise information estimation program that causes a computer to execute processing.

2. In determining whether the execution is successful, the deviation degree is compared with a threshold value, and if the deviation degree is equal to or greater than the threshold value, the execution is determined to be successful, and if the deviation degree is less than the threshold value, the execution is determined to be unsuccessful.

2. The noise information estimation program according to claim 1, which causes the computer to execute processing.

3. In the above estimation, acquire, for each of the plurality of quantum circuits, first information indicating the number of quantum gates applied to each of the plurality of quantum bits in a quantum circuit that has been successfully executed among the plurality of quantum circuits, and acquire, for each of the plurality of quantum circuits, second information indicating the number of quantum gates applied to each of the plurality of quantum bits in a quantum circuit that has been unsuccessfully executed among the plurality of quantum circuits; generating safety range information indicating a range of quantum gate numbers that are permissible for application to each of the plurality of quantum bits, based on the first information and the second information acquired for each of the plurality of quantum circuits; 2. The noise information estimation program according to claim 1, which causes the computer to execute processing.

4. the first information and the second information include an average value of the number of quantum gates applied to a quantum bit and another quantum bit adjacent to the quantum bit; the safety range information includes a range of average values ​​of quantum gate numbers that are allowed to be applied to the quantum bit and the other quantum bits adjacent to the quantum bit; The noise information estimation program according to claim 3.

5. After generating the safe range information, when executing the first quantum circuit by the quantum computer, adjusting the number of quantum gates applied to the quantum bits used to execute the first quantum circuit to be within the range indicated by the safe range information.

4. The noise information estimation program according to claim 3, which causes the computer to execute processing.

6. determining whether or not the output distribution of the quantum computer for the second quantum circuit is expected to be a distribution in which the occurrence probability of a specific state is amplified, based on information about the second quantum circuit executed by the quantum computer or a quantum algorithm program corresponding to the second quantum circuit; If the result of the determination is true, using the output distribution for the second quantum circuit to estimate information about the noise; If the result of the determination is false, the output distribution for the second quantum circuit is not used to estimate information about the noise.

2. The noise information estimation program according to claim 1, which causes the computer to execute processing.

7. The computer acquiring a plurality of output distributions that indicate distributions of output states of the plurality of quantum bits corresponding to each of the plurality of quantum circuits when the plurality of quantum circuits are each executed a plurality of times for the plurality of quantum bits; determining whether each of the plurality of quantum circuits is executed successfully based on a deviation between each of the plurality of output distributions and a uniform distribution; estimating information about noise of each of the plurality of quantum bits based on the determination result of the success or failure of the execution of each of the plurality of quantum circuits and the number of quantum gates applied to each of the plurality of quantum bits in each of the plurality of quantum circuits; Noise information estimation method.

8. a storage unit configured to store information on a plurality of output distributions indicating distributions of output states of the plurality of quantum bits corresponding to each of the plurality of quantum circuits when the plurality of quantum circuits are each executed a plurality of times for the plurality of quantum bits; a processing unit that determines whether each of the plurality of quantum circuits has been executed successfully based on the degree of deviation between each of the plurality of output distributions and a uniform distribution, and that estimates information about noise of each of the plurality of quantum bits based on the determination result of whether each of the plurality of quantum circuits has been executed successfully and the number of quantum gates applied to each of the plurality of quantum bits in each of the plurality of quantum circuits; An information processing device having the above.

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