Semiconductor device

Abstract

To provide a semiconductor device with high functionality.SOLUTION: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first semiconductor layer, a first gate electrode, a first electrode, and a second electrode. The second transistor includes a second semiconductor layer, a second gate electrode, a third electrode, and a fourth electrode. The first gate electrode is connected to the second gate electrode, and the second electrode is connected to the third electrode. A first insulating layer, a second insulating layer, and the second semiconductor layer are stacked over the first semiconductor layer. Hydrogen is less likely to diffuse in the first insulating layer than in the second insulating layer. The second insulating layer includes an oxide, the first semiconductor layer includes polycrystalline silicon, and the second semiconductor layer includes a metal oxide. The first transistor is a p-channel transistor and the second transistor is an n-channel transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a display device, and a driver circuit of a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] Display devices are used in a variety of devices, including mobile information terminals such as smartphones and television sets. In recent years, there has been a demand for improved screen occupancy rates in devices that use display devices, and to achieve this, display devices are being required to have a smaller area other than the display area (a narrower frame). Furthermore, a system-on-panel, in which part or all of the driver circuitry is fabricated on the same substrate as the pixel area, is effective in meeting this demand. Patent Documents 1 and 2 disclose techniques for configuring inverter circuits, shift register circuits, and the like, used in the driver circuits of display devices with unipolar transistors. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-325798 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-277652 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment of the present invention is to provide a semiconductor device with high functionality.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device, display device, or electronic device.An object of one embodiment of the present invention is to provide a semiconductor device, display device, or electronic device with reduced power consumption.An object of one embodiment of the present invention is to provide a semiconductor device that can achieve a narrower frame of a display device.An object of one embodiment of the present invention is to provide a semiconductor device, display device, or electronic device with a novel structure.An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0006] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0007] One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor. The first transistor includes a first semiconductor layer, a first gate electrode, a first electrode, and a second electrode. The second transistor includes a second semiconductor layer, a second gate electrode, a third electrode, and a fourth electrode. The first gate electrode and the second gate electrode are electrically connected to each other. The second electrode and the third electrode are electrically connected to each other. The semiconductor device further includes a first insulating layer over the first semiconductor layer and a second insulating layer over the first insulating layer. The second semiconductor layer is provided on and in contact with the second insulating layer. Hydrogen is less likely to diffuse through the first insulating layer than through the second insulating layer. The second insulating layer includes an oxide, the first semiconductor layer includes polycrystalline silicon, and the second semiconductor layer includes a metal oxide. The first transistor is a p-type transistor, and the second transistor is an n-type transistor.

[0008] In the above, it is preferable that a first potential is applied to the first electrode, and a second potential lower than the first potential is applied to the fourth electrode.

[0009] Another embodiment of the present invention is a semiconductor device including a control circuit, a first transistor, and a second transistor. The control circuit includes a first wiring and a second wiring. The control circuit receives a plurality of signals and has a function of controlling the first wiring and the second wiring to have potentials that are inverted from each other, based on the plurality of signals. The first transistor includes a first semiconductor layer, a first gate electrode, a first electrode, and a second electrode. The second transistor includes a second semiconductor layer, a second gate electrode, a third electrode, and a fourth electrode. The second electrode and the third electrode are electrically connected to each other. The first gate electrode and the second gate electrode are electrically connected to the first wiring. The semiconductor device further includes a first insulating layer over the first semiconductor layer and a second insulating layer over the first insulating layer. The second semiconductor layer is provided on and in contact with the second insulating layer. Hydrogen is less likely to diffuse into the first insulating layer than into the second insulating layer. The second insulating layer includes an oxide, the first semiconductor layer includes polycrystalline silicon, and the second semiconductor layer includes a metal oxide. The first transistor is a p-type transistor, and the second transistor is an n-type transistor.

[0010] In the above, it is preferable that a first potential is applied to the first electrode and a second potential lower than the first potential is applied to the fourth electrode. Furthermore, it is preferable that either the first potential or the second potential is applied to the second electrode depending on the potential of the first wiring.

[0011] In any of the above, it is preferable that the device further includes an amplifier circuit. In this case, it is preferable that the amplifier circuit is electrically connected to the first wiring and the second wiring and has a first output terminal. Furthermore, it is preferable that the amplifier circuit has a function of outputting a potential synchronized with the potential of the first wiring to the first output terminal. In this case, it is preferable that the potential of the first output terminal and the potential of the second electrode are mutually inverted.

[0012] In the above, the amplifier circuit preferably includes a third transistor, a fourth transistor, and a fifth transistor. The third transistor is preferably a p-type transistor, and the fourth and fifth transistors are preferably n-type transistors. Preferably, the gates of the third and fifth transistors are electrically connected to the second wiring, the gate of the fourth transistor is electrically connected to the first wiring, one of the source and drain of the third transistor, one of the source and drain of the fourth transistor, and one of the source and drain of the fifth transistor are electrically connected to the first output terminal, and the other of the source and drain of the third transistor and the other of the fourth transistor are electrically connected to each other.

[0013] Another embodiment of the present invention is a display device including any one of the above semiconductor devices and a pixel. In this case, the pixel preferably includes a display element and a sixth transistor. The sixth transistor is preferably provided on the same surface as the first transistor or the second transistor. The display element is preferably a liquid crystal element, an organic EL element, or a light-emitting diode.

[0014] Another embodiment of the present invention is an electronic device including any of the above display devices and at least one of an antenna, a battery, a housing, a camera, a speaker, a microphone, and an operation button. [Effects of the Invention]

[0015] According to one embodiment of the present invention, a highly functional semiconductor device can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device, display device, or electronic device can be provided. According to one embodiment of the present invention, a semiconductor device, display device, or electronic device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device that can achieve a narrower frame of a display device can be provided. According to one embodiment of the present invention, a semiconductor device, display device, or electronic device having a novel structure can be provided. According to one embodiment of the present invention, at least one of the problems of the prior art can be alleviated.

[0016] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0017] [Figure 1] 1A is a diagram showing an example of the configuration of a sequential circuit, FIG. 1B is a timing chart of the sequential circuit, and FIG. 1C is a schematic cross-sectional view of the sequential circuit. [Figure 2] 2A and 2B are diagrams illustrating an example of the configuration of a sequential circuit. [Figure 3] 3A and 3B are diagrams illustrating configuration examples of sequential circuits. [Figure 4] FIG. 4 is a diagram illustrating an example of the configuration of a sequential circuit. [Figure 5] 5A and 5B are diagrams illustrating configuration examples of sequential circuits. [Figure 6] 6A and 6B are diagrams illustrating configuration examples of sequential circuits. [Figure 7] Fig. 7A is a diagram showing an example of the configuration of a sequential circuit, Fig. 7B is a circuit diagram of a shift register, and Fig. 7C is a timing chart. [Figure 8] 8A is a circuit diagram of a shift register, and FIG. 8B is a circuit diagram of an inverter circuit. [Figure 9]Figure 9A is a block diagram of a display device, and Figure 9B is a circuit diagram of a pixel. [Figure 10] 10A and 10B are schematic top and cross-sectional views of an inverter circuit. [Figure 11] 11A to 11C are cross-sectional schematic diagrams of inverter circuits. [Figure 12] Figure 12A is a block diagram of a display device, and Figures 12B and 12C are circuit diagrams of pixel circuits. [Figure 13] 13A and 13B are diagrams showing an example of the configuration of a display module. [Figure 14] 14A and 14B are diagrams showing configuration examples of electronic devices. [Figure 15] 15A to 15E are diagrams showing configuration examples of electronic devices. [Figure 16] 16A to 16G are diagrams showing configuration examples of electronic devices. [Figure 17] 17A to 17D are diagrams showing configuration examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0019] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0020] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0021] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0022] A transistor is a type of semiconductor element that can amplify current or voltage, and perform switching operations to control conduction or non-conduction. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) or a TFT (Thin Film Transistor).

[0023] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0024] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. For example, "something that has some kind of electrical action" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, coils, capacitive elements, and other elements with various functions.

[0025] In this specification, a node refers to an element (for example, a wiring) that allows electrical connection of elements that make up a circuit. Therefore, a "node to which A is connected" refers to a wiring that is electrically connected to A and can be considered to have the same potential as A. Even if one or more elements (for example, a switch, transistor, capacitance element, inductor, resistance element, diode, etc.) that allow electrical connection are placed along the wiring, the wiring is considered to be a node to which A is connected as long as it has the same potential as A.

[0026] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) images etc. on a display surface, and therefore the display panel is one aspect of an output device.

[0027] In addition, in this specification, a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or having an IC mounted on the substrate using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, display module, or simply a display panel.

[0028] (Embodiment 1) In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention will be described.

[0029] [Configuration example 1] 1A shows a configuration example of a sequential circuit 10 of one embodiment of the present invention. The sequential circuit 10 includes a circuit 11, a circuit 12, and a circuit 13. The circuit 11 includes a wiring 15a and a wiring 15b. The circuits 11 and 12 are electrically connected through the wiring 15a and the wiring 15b. The circuits 11 and 13 are electrically connected through the wiring 15a.

[0030] The circuit 11 has a function of outputting a first signal to the wiring 15a and a second signal to the wiring 15b in accordance with the potentials of the signal LIN and the signal RIN. That is, the circuit 11 can also be called a control circuit.

[0031] The second signal is an inverted version of the first signal. That is, when the first signal and the second signal each have two types of potentials, high and low, when the circuit 11 outputs a high potential to the wiring 15a, the circuit 11 outputs a low potential to the wiring 15b, and when the circuit 11 outputs a low potential to the wiring 15a, the circuit 11 outputs a high potential to the wiring 15b.

[0032] The circuit 12 has a function of outputting either the signal CLK or the potential VSS to the output terminal OUTA based on signals input to the wirings 15a and 15b. The circuit 12 outputs the signal CLK when the wiring 15a is at a high potential and outputs the potential VSS when the wiring 15a is at a low potential. The circuit 12 can be called an amplifier circuit, a buffer circuit, or the like.

[0033] The signal CLK can be a clock signal. The clock signal preferably has a duty ratio (the ratio of the period during which the signal is at high level potential in one cycle) of 45% or more and 55% or less. More preferably, the clock signal has a duty ratio of 50%. Note that the duty ratio of the clock signal is not limited to the above and can be changed as appropriate depending on the driving method.

[0034] In this specification, a clock signal refers to a signal in which high and low potentials are repeated, and the interval between the rising edge of one potential and the rising edge of the next potential, or the interval between the falling edge of one potential and the falling edge of the next potential, is constant. In this specification, a pulse signal refers to a signal whose potential changes over time. Pulse signals also include signals whose potential changes periodically. For example, pulse signals include signals whose potential changes periodically, such as rectangular waves, triangular waves, sawtooth waves, and sine waves. Therefore, a clock signal can also be considered one form of a pulse signal.

[0035] Here, the potential VDD can be higher than the potential VSS. The signal CLK is a signal that alternately receives high and low potentials. In this case, the low potential of the signal CLK is preferably the same as the potential VSS. Note that instead of the signal CLK, a high potential (e.g., potential VDD) may be applied to one of the source and drain of the transistor 21.

[0036] The circuit 13 has a function of outputting either a potential VDD or a potential VSS to the output terminal OUTB depending on the potential of the wiring 15a. When the wiring 15a is at a high potential, the circuit 13 outputs a low potential VSS, and when the wiring 15a is at a low potential, the circuit 13 outputs a high potential VDD. That is, the circuit 13 can output a signal that is an inversion of the first signal to the output terminal OUTB. In other words, the circuit 13 can output a signal similar to the second signal to the output terminal OUTB. The circuit 13 can be called an inverter circuit, for example.

[0037] The sequential circuit 10 functions as a flip-flop circuit and can be used as part of a shift register circuit. For example, the sequential circuit 10 can be used as part of a drive circuit of a display device. In particular, the sequential circuit 10 can be suitably used as part of a scan line drive circuit (also called a gate driver circuit) of a display device.

[0038] When the sequential circuit 10 is applied to a scanning line driving circuit, scanning lines (also called gate lines) connected to multiple pixels of a display device can be connected to at least one or both of the output terminals OUTA and OUTB. By connecting scanning lines to both the output terminals OUTA and OUTB, it becomes possible to drive pixels with two types of scanning line signals, thereby realizing more multifunctional pixels.

[0039] The circuit 11 includes transistors 31 to 34. The transistors 31 to 34 are preferably n-channel transistors.

[0040] The transistors 31 and 34 are turned on or off in accordance with the potential of the signal LIN, while the transistors 32 and 33 are turned on or off in accordance with the potential of the signal RIN.

[0041] When the signal LIN is at a high potential and the signal RIN is at a low potential, the transistor 31 is on and the transistor 33 is off, and the wiring to which the potential VDD is applied is electrically connected to the wiring 15a. The transistor 34 is on and the transistor 32 is off, and the wiring to which the potential VSS is applied is electrically connected to the wiring 15b. On the other hand, when the signal LIN is at a low potential and the signal RIN is at a high potential, the on / off states of the transistors are reversed, and the wiring 15a is electrically connected to the wiring to which the potential VSS is applied, and the wiring 15b is electrically connected to the wiring to which the potential VDD is applied.

[0042] The circuit 12 includes a transistor 21 and a transistor 22. The transistors 21 and 22 are preferably n-channel transistors.

[0043] In the circuit 12, the transistor 21 has a gate electrically connected to a wiring 15a, one of its source and drain electrically connected to a wiring to which a signal CLK is applied, and the other electrically connected to one of the source and drain of the transistor 22 and an output terminal OUTA. The transistor 22 has a gate electrically connected to a wiring 15b, and the other of its source and drain electrically connected to a wiring to which a potential VSS is applied. Note that the output terminal OUTA is a portion to which an output potential from the circuit 12 is applied, and may be part of a wiring or part of an electrode.

[0044] In the circuit 12, when the wiring 15a is at a high potential and the wiring 15b is at a low potential, the signal CLK is output to the output terminal OUTA via the transistor 21. On the other hand, when the wiring 15a is at a low potential and the wiring 15b is at a high potential, the potential VSS is output to the output terminal OUTA via the transistor 22.

[0045] The circuit 13 includes a transistor 25 and a transistor 26. The transistor 25 is preferably a p-channel transistor (p-type transistor), and the transistor 26 is preferably an n-channel transistor (n-type transistor).

[0046] In the circuit 13, the transistor 25 has a gate electrically connected to a wiring 15a, one of its source and drain electrically connected to a wiring to which a potential VDD is applied, and the other electrically connected to one of the source and drain of the transistor 26 and the output terminal OUTB. The transistor 26 has a gate electrically connected to the wiring 15a, and the other of its source and drain electrically connected to a wiring to which a potential VSS is applied. Note that the output terminal OUTB is a portion to which an output potential from the circuit 13 is applied, and may be part of a wiring or part of an electrode.

[0047] In the circuit 13, when the wiring 15a is at a high potential, the potential VSS is output to the output terminal OUTB through the transistor 26. On the other hand, when the wiring 15a is at a low potential, the potential VDD is output to the output terminal OUTB through the transistor 25.

[0048] 1B is a timing chart showing an example of a method for driving the sequential circuit 10. FIG. 1B schematically shows changes over time in potential at the signals LIN, RIN, CLK, output terminal OUTA, and output terminal OUTB.

[0049] Before time T1, both the signals LIN and RIN are at low potential, and a low potential is output from the output terminal OUTA and a high potential is output from the output terminal OUTB, regardless of the potential of the signal CLK.

[0050] At time T1, the signal LIN goes to high potential. Also, during the period T1-T2, the signal CLK is at low potential. As a result, during the period T1-T2, the signal CLK (i.e., low potential) is output to the output terminal OUTA, and the signal CLK is at low potential to the output terminal OUTB.

[0051] Subsequently, at time T2, the signal LIN goes low. As a result, all four transistors in the circuit 11 are turned off, and the potentials of the wirings 15a and 15b are maintained. The signal CLK also goes high at time T2. As a result, during the period T2-T3, a high potential is output to the output terminal OUTA, and a low potential continues to be output to the output terminal OUTB.

[0052] Subsequently, at time T3, the signal RIN goes high. This causes the wiring 15a to go low and the wiring 15b to go high. Therefore, during the period T3-T4, the output terminal OUTA is supplied with a low potential and the output terminal OUTB is supplied with a high potential.

[0053] At time T4, the signal RIN goes low. This turns off all the transistors in the circuit 11, and the potentials of the wirings 15a and 15b are maintained. Therefore, after time T4, a low potential is output to the output terminal OUTA, and a high potential is output to the output terminal OUTB.

[0054] Before time T1 and after time T4, both the signal LIN and the signal RIN are at low potential, and therefore, these periods can be considered as periods in which the sequential circuit 10 is in a standby state (also called a non-operating state or a non-selected state). During these periods, a low potential is output to the output terminal OUTA, and a high potential is output to the output terminal OUTB.

[0055] As shown in FIG. 1B, the signal output to the output terminal OUTA is high only during the period T2-T3 and is always low during the other periods. That is, the signal output to the output terminal OUTA of the sequential circuit 10 can be referred to as a normally low signal. On the other hand, the signal output to the output terminal OUTB is low only during the period T1-T3 and is always high during the other periods. That is, the signal output to the output terminal OUTB can be referred to as a normally high signal. In this way, the sequential circuit 10 can output two types of signals, normally low and normally high. Therefore, when the sequential circuit 10 is used, for example, in a scanning line driving circuit of a display device, the pixels of the display device can be driven by these two types of signals. This makes it possible to realize a multifunctional display device.

[0056] The above is a description of an example of the operation method of the sequential circuit 10.

[0057] Here, it is preferable to use a transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed as an n-channel transistor included in the sequential circuit 10. Such a transistor has a significantly lower leakage current flowing between the source and drain in an off state than a transistor in which silicon is used. By using such a transistor in the circuits 11, 12, and 13, the power consumption of each can be significantly reduced.

[0058] Furthermore, it is preferable to use a transistor having silicon in a semiconductor layer in which a channel is formed as a p-channel transistor constituting the sequential circuit 10. Examples of silicon include single crystal silicon, polycrystalline silicon, and amorphous silicon. In particular, it is preferable to use a transistor having low temperature polysilicon (LTPS) in the semiconductor layer (hereinafter also referred to as an LTPS transistor). LTPS transistors have high field-effect mobility and excellent frequency characteristics. Furthermore, since LTPS transistors can pass a large current in the on state, the time required for charging and discharging the wiring connected to the output terminal OUTB can be shortened. As a result, particularly in the circuit 13, by configuring a CMOS (Complementary Metal Oxide Semiconductor) circuit using the n-channel transistor 26 and the p-channel transistor 25, it is possible to realize the circuit 13 with high driving capability and low power consumption.

[0059] A p-channel transistor and an n-channel transistor applicable to the sequential circuit 10 are preferably fabricated over the same substrate. The stacked structure of the sequential circuit 10 will be described below. Figure 1C shows, as an example, a schematic cross-sectional view of the sequential circuit 10, including cross sections of transistors 25 and 26 in the channel length direction of the circuit 13.

[0060] The transistor 25 and the transistor 26 are provided over an insulating layer 60. In FIG. 1C, an example is shown in which so-called top-gate transistors in which gate electrodes are provided above a semiconductor layer are applied as the transistor 25 and the transistor 26. Note that the structure of the transistor is not limited to this.

[0061] The transistor 25 has a semiconductor layer 51, a gate insulating layer 52, and a gate electrode 53. The semiconductor layer 51 contains polycrystalline silicon. The semiconductor layer 51 has a pair of low-resistance regions 51p that exhibit p-type conductivity and sandwich a channel formation region therebetween. The transistor 26 has a semiconductor layer 56, a gate insulating layer 57, and a gate electrode 58. The semiconductor layer 56 contains metal oxide. The semiconductor layer 56 has a pair of low-resistance regions 56n that exhibit n-type conductivity and sandwich a channel formation region therebetween.

[0062] The semiconductor layer 51 of the transistor 25 is provided over an insulating layer 60. An insulating layer 61 is provided to cover the transistor 25, and an insulating layer 62 and an insulating layer 63 are stacked over the insulating layer 61. A semiconductor layer 56 of the transistor 26 is provided in contact with a top surface of the insulating layer 63. An insulating layer 64 is provided to cover the transistor 26.

[0063] Conductive layers 54a, 54b, and 54c are provided on the insulating layer 64. A portion of the conductive layer 54a corresponds to a wiring to which a potential VDD is applied. A portion of the conductive layer 54c corresponds to a wiring to which a potential VSS is applied. A portion of the conductive layer 54b corresponds to an output terminal OUTB. The gate electrode 53 and the gate electrode 58 are electrically connected in a region not shown.

[0064] The conductive layers 54a and 54b are electrically connected to the low-resistance region 51p through openings provided in the insulating layers 64, 63, 62, and 61. The conductive layers 54b and 54c are electrically connected to the low-resistance region 56n through openings provided in the insulating layer 64.

[0065] Here, since the reliability of polycrystalline silicon is improved by terminating dangling bonds of silicon with hydrogen atoms, the semiconductor layer 51 and its periphery (such as the insulating layer 61) may contain hydrogen atoms, hydrogen molecules, or compounds containing hydrogen (such as water) that are formed during the manufacturing process. Meanwhile, in an oxide semiconductor, hydrogen is an element that can serve as a carrier source, so it is preferable to reduce the hydrogen concentration in and around the semiconductor layer 56 of the transistor 26 as much as possible. Furthermore, in an oxide semiconductor, oxygen vacancies can also serve as a carrier source, so it is preferable that an oxide with reduced hydrogen be provided in contact with the semiconductor layer 56 of the transistor 26.

[0066] Therefore, the semiconductor layer 51 of the transistor 25 and the semiconductor layer 56 of the transistor 26 are preferably isolated from each other by an insulating layer 62 that has a barrier property against hydrogen and water. Furthermore, the semiconductor layer 56 of the transistor 26 is preferably provided on and in contact with an insulating layer 63 containing oxide. In this case, the insulating layer 62 includes a material that is less permeable to hydrogen and water (less permeable to hydrogen and water) than at least the insulating layers 61 and 63.

[0067] More specifically, an inorganic insulating film containing silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide can be used as the insulating layer 62. An oxide film such as silicon oxide or silicon oxynitride can be used as the insulating layer 63. In this case, the insulating layer 63 is preferably a film from which oxygen is released when heated.

[0068] By configuring the two types of transistors that make up the sequential circuit 10 as described here, it is possible to realize a sequential circuit that combines high driving capability, low power consumption, and high reliability.

[0069] The above is the explanation of the laminated structure.

[0070] [Configuration example 2] A sequential circuit having a different configuration from the above configuration example 1 will be described below.

[0071] [Configuration Example 2-1] 2A shows an example of the configuration of a sequential circuit 10a. The sequential circuit 10a is different from the sequential circuit 10 described above mainly in the configurations of circuits 11 and 12. Circuit 13 has the same configuration as the sequential circuit 10 described above, so its description will be omitted.

[0072] The circuit 11 includes transistors 41 to 46 and a capacitor C2. The circuit 11 receives input of a signal LIN, a signal CLK2, a signal CLK3, and a signal RIN.

[0073] The circuit 12 includes a transistor 21, a transistor 22, a transistor 23, and a capacitor C1. The circuit 12 also receives a signal CLK1.

[0074] The circuit 11 and the circuit 13 are supplied with a high potential VDD and a low potential VSS.

[0075] The above-described n-channel transistors are preferably used as the transistors 41 to 46 and the transistors 21 to 23. In particular, it is preferable to use a transistor in which an oxide semiconductor is used as a semiconductor in which a channel is formed.

[0076] The circuit 11 has a function of outputting a first signal to the wiring 15a and a second signal, which is an inverted version of the first signal, to the wiring 15b in accordance with various input signals.

[0077] Specifically, the transistor 41 has a gate electrically connected to a wiring to which a signal LIN is applied, one of its source and drain electrically connected to the wiring 15a, and one of the source and drain of the transistor 45 electrically connected to a wiring to which a potential VDD is applied. The transistor 42 has a gate electrically connected to a wiring to which a signal CLK3 is applied, one of its source and drain electrically connected to one of the source and drain of the transistor 43 electrically connected to a wiring to which a potential VDD is applied. The transistor 43 has a gate electrically connected to a wiring to which a signal CLK2 is applied, and the other of its source and drain electrically connected to the wiring 15b, one electrode of the capacitor C2, and the gate of the transistor 45. The transistor 44 has a gate electrically connected to a wiring to which a signal RIN is applied, one of its source and drain electrically connected to the wiring 15b, and the other to a wiring to which a potential VDD is applied. The transistor 45 has the other of its source and drain electrically connected to a wiring to which a potential VSS is applied. The transistor 46 has a gate electrically connected to a wiring to which a signal LIN is applied, one of a source and a drain electrically connected to the wiring 15b, and the other electrically connected to a wiring to which a potential VSS is applied. The capacitor C2 has another electrode electrically connected to the wiring to which the potential VSS is applied.

[0078] The circuit 12 included in the sequential circuit 10a has a configuration in which a transistor 23 and a capacitor C1 are added to the configuration shown in FIG. 1A.

[0079] The transistor 23 has a gate electrically connected to a wiring to which a potential VDD is applied, one of its source and drain electrically connected to the wiring 15a, and the other electrically connected to the gate of the transistor 21. The capacitor C1 has one electrode electrically connected to the gate of the transistor 21, and the other electrode electrically connected to the other of the source and drain of the transistor 21. One of the source and drain of the transistor 21 is electrically connected to a wiring to which a signal CLK1 is applied.

[0080] When a high potential is applied to the wiring 15a, the high potential is applied to the gate of the transistor 21 through the transistor 23, turning on the transistor 21. If the high potential applied to the wiring 15a is equal to the potential VDD, the gate of the transistor 21 is applied with a potential that is lower than the potential VDD by the threshold voltage of the transistor 23. Because the output terminal OUTA and the gate of the transistor 21 are electrically connected through the capacitor C1, the potential of the output terminal OUTA increases due to the bootstrap effect. Accordingly, the potential of the gate of the transistor 21 (the potential of the other of the source and drain of the transistor 23) increases. Since the gate potential of the transistor 21 increases to, for example, a potential nearly twice the potential VDD, the potential VDD can be output to the output terminal OUTA without being affected by the threshold voltage of the transistor 21. This allows the sequential circuit 10a to have high output performance without increasing the number of power supply potentials.

[0081] After that, when the potential of the other of the source and drain of the transistor 23 exceeds the potential VDD, the transistor 23 is turned off, so that the gate of the transistor 21 and the wiring 15a are electrically disconnected, and the gate of the transistor 22 is brought into a floating state. Furthermore, because the transistor 23 is turned off, the potential of the wiring 15a does not rise above the output potential of the circuit 12, so that a potential higher than the output potential can be prevented from being applied to the transistors, etc. in the circuit 12 through the wiring 15a. This can improve the reliability of the sequential circuit 10a.

[0082] [Configuration Example 2-2] 2B shows an example of the configuration of a sequential circuit 10b. The sequential circuit 10b differs from the sequential circuit 10a in that the transistor configuration is different.

[0083] In the sequential circuit 10b, the n-channel transistors included in the circuit 11, the circuit 12, and the circuit 13 are transistors with back gates.

[0084] The back gates of the transistor 45 and the transistor 22 are electrically connected to a wiring to which the potential VSS is applied. That is, the back gates of the transistor 45 and the transistor 22 are electrically connected to the sources.

[0085] When the sequential circuit 10b is used in a scan line driver circuit, the period during which the wiring 15b is at a high potential is significantly longer than the period during which it is at a low potential. Therefore, the transistors 45 and 22, whose gates are connected to the wiring 15b, are on for significantly longer periods than they are off. Therefore, the threshold voltages of the transistors 45 and 22 are more likely to fluctuate than those of other transistors. Specifically, the threshold voltages of the transistors are more likely to shift in the positive direction.

[0086] Therefore, the transistor 45 and the transistor 22 have a pair of gates that overlap with each other with a semiconductor layer sandwiched therebetween, and one of the gates is electrically connected to a wiring to which a low potential is applied (a wiring to which a potential VSS is applied). This configuration can suitably prevent the threshold voltages of the transistor 45 and the transistor 22 from shifting in the positive direction. Therefore, the reliability of the sequential circuit 10b, and further the reliability of a semiconductor device, a display device, an electronic device, or the like that uses the sequential circuit 10b, can be improved.

[0087] Furthermore, by electrically connecting one of the gates to the source of the transistor 45 and the transistor 22, the threshold voltage can be prevented from becoming negative. That is, the transistor 45 and the transistor 22 can be easily made normally-off. Furthermore, by electrically connecting one of the gates to the source of the transistor 45 and the transistor 22, the saturation property can be improved. This simplifies the design of the circuits 11 and 12 and enables the realization of circuits that can operate stably.

[0088] On the other hand, the n-channel transistors other than the transistor 45 and the transistor 22 are transistors in which a pair of gates are electrically connected to each other. By electrically connecting a pair of gates that overlap with each other with a semiconductor layer sandwiched therebetween, the on-state current of the transistor can be increased, thereby improving the driving capability of the sequential circuit 10b.

[0089] [Configuration Example 2-3] In the sequential circuit 10a, a potential obtained by inverting the potential of the wiring 15a is applied to the wiring 15b. Meanwhile, the circuit 13 can output a signal obtained by inverting the potential of the wiring 15a to the output terminal OUTB. Therefore, the configuration of the circuit 11 can be simplified by supplying (feeding back) the output potential of the output terminal OUTB to the wiring 15b.

[0090] FIG. 3A shows an example of the configuration of the sequential circuit 10c.

[0091] The sequential circuit 10c is different from the sequential circuit 10a mainly in the configuration of the circuit 11. Specifically, in the sequential circuit 10c, the wiring 15b is electrically connected to the output terminal OUTB of the circuit 13. Furthermore, compared to the sequential circuit 10a, the sequential circuit 10c does not include the transistor 46 that functions as a switch that controls conduction / non-conduction between the wiring 15b and the potential VSS.

[0092] FIG. 3B shows an example of the configuration of the sequential circuit 10d.

[0093] The sequential circuit 10d is the same as the sequential circuit 10c except that the transistor 42, the transistor 43, and the capacitor C2 are further omitted.

[0094] Note that the configuration is not limited to the above, and one or more of the transistors 42, 43, 44, and 46 may be omitted from the configuration of the sequential circuit 10a.

[0095] [Configuration Example 2-4] 4 shows an example of a sequential circuit 10e having a different configuration from the above. For ease of viewing, the positions of the circuits 12 and 13 in the sequential circuit 10e are swapped.

[0096] The circuit 11 includes a transistor 41, a transistor 46, and a transistor 47. The transistor 47 has a gate electrically connected to a wiring to which a signal RES is applied, one of a source and a drain electrically connected to the wiring 15a, and the other electrically connected to a wiring to which a potential VSS is applied.

[0097] The signal RES is supplied with, for example, a signal that controls the reset operation of the sequential circuit 10e.

[0098] In the circuit 13, the gates of the transistor 25 and the transistor 26 are electrically connected to the wiring 15a, and the output terminal OUTB is electrically connected to the wiring 15b.

[0099] The circuit 12 includes a transistor 21, a transistor 22, and a capacitor C1.

[0100] The transistor 21 has a gate electrically connected to the wiring 15a, one of its source and drain electrically connected to a wiring to which a signal CLK1 is applied, and the other electrically connected to the output terminal OUTA. The transistor 22 has a gate electrically connected to the wiring 15b, one of its source and drain electrically connected to the output terminal OUTA, and the other electrically connected to a wiring to which a potential VSS is applied. The capacitor C1 has one electrode electrically connected to the wiring 15a and the gate of the transistor 21, and the other electrode electrically connected to the output terminal OUTA.

[0101] In the sequential circuit 10e, even after the signal LIN is applied with a high potential and then changes to a low potential, the output signals to the output terminals OUTA and OUTB are maintained. Furthermore, when a high potential is applied to the signal RES and the transistor 47 is turned on, the potential VSS, which is a low potential, is supplied to the wiring 15a, and the state of the sequential circuit 10e can be reset.

[0102] [Configuration Example 2-5] 5A shows an example of a sequential circuit 10f having a different configuration from the above-described sequential circuit 10a. The sequential circuit 10f differs from the above-described sequential circuit 10a mainly in that the configuration of the circuit 12 is different.

[0103] The circuit 12 includes a transistor 22, a transistor 24n, and a transistor 24p. The transistor 24n is an n-channel transistor, and the transistor 24p is a p-channel transistor.

[0104] The transistors 24n and 24p have their sources and drains electrically connected to each other, forming a so-called analog switch. The gate of the transistor 24n is electrically connected to the wiring 15a, and the gate of the transistor 24p is electrically connected to the wiring 15b. When the wiring 15a is at a high potential and the wiring 15b is at a low potential, the analog switch is on and the transistor 22 is off, thereby establishing electrical continuity between the wiring to which the signal CLK1 is applied and the output terminal OUTA. On the other hand, when the wiring 15a is at a low potential and the wiring 15b is at a high potential, the analog switch is off and the transistor 22 is on, establishing electrical continuity between the wiring to which the potential VSS is applied and the output terminal OUTA.

[0105] In this way, p-channel transistors can be applied to other circuits as well as the circuit 13. Although the example in which p-channel transistors are applied to the circuit 12 is shown here, they can also be applied to the circuit 11.

[0106] Note that although the configurations of the circuit 11 and the circuit 13 are the same as those of the sequential circuit 10a, the present invention is not limited to this and various configurations exemplified above can be applied. For example, by electrically connecting the output terminal OUTB of the circuit 13 to the wiring 15b, some transistors in the circuit 11 can be omitted, thereby simplifying the circuit.

[0107] 5B shows a sequential circuit 10g that is partially different from the above-described circuit. The sequential circuit 10g further includes a transistor 23 in the circuit 12.

[0108] The transistor 23 has a gate to which a potential VDD is applied, one of a source and a drain electrically connected to the wiring 15a, and the other electrically connected to the gate of the transistor 24n. By providing the transistor 23, a potential higher than the potential VDD can be supplied to the gate of the transistor 24n, as described above, and the influence of the threshold voltage of the transistor 24n can be suppressed.

[0109] Although not shown here, a capacitor C1 may be provided between the gate of the transistor 24n and the output terminal OUTA, similar to the sequential circuit 10a.

[0110] [Modification] 6A is an example of the sequential circuit 10f in which the circuit 13 is omitted. The sequential circuit 10h can output the signal CLK1 or the potential VSS from the output terminal OUT.

[0111] A sequential circuit 10i shown in FIG. 6B is an example in which a transistor 23 is added to the circuit 12 of the sequential circuit 10h.

[0112] The above is a description of the modified example.

[0113] In the sequential circuits 10c to 10i, the n-channel transistor may be the transistor having a back gate as exemplified in the sequential circuit 10b. In this case, it is preferable to select and use a transistor whose pair of gates are electrically connected, a transistor whose one gate is electrically connected to a source, or a transistor without a back gate.

[0114] [Driver circuit configuration example] An example of a driving circuit that is configured by connecting sequential circuits in multiple stages and functions as a shift register will be described below.

[0115] [Driver circuit configuration example 1] 7A is a diagram illustrating input / output terminals of a sequential circuit 30. The sequential circuit 30 has input terminals to which signals LIN, RIN, CLK1, CLK2, and CLK3 are respectively input, and output terminals OUTA and OUTB. The sequential circuit 30 can be, for example, the sequential circuit 10a, 10b, or 10c described above.

[0116] 7B shows an example of the configuration of the driving circuit 40. The driving circuit 40 has a plurality of sequential circuits 30. FIG. 7B shows sequential circuits 30_1 to 30_6. Hereinafter, the n-th sequential circuit from the side closest to the input of the driving circuit 40 will be referred to as sequential circuit 30_n (n is an integer equal to or greater than 1).

[0117] The sequential circuit 30_n uses any three of the signals CK1 to CK4 as the signals CLK1, CLK2, and CLK3. The combinations of the signals CK1 to CK4 are the same for every four stages. That is, the same signals are input to the sequential circuit 30_n and the sequential circuit 30_n+4 as the signals CLK1, CLK2, and CLK3.

[0118] Moreover, the output terminal OUTA and the output terminal OUTB of the sequential circuit 30_n are connected to output wirings OUTAn and OUTBn, respectively.

[0119] The sequential circuit 30_1 receives the signal SP as the signal LIN. The sequential circuit 30_n, where n is 2 or greater, receives the signal LIN from the output terminal OUTA of the sequential circuit 30_n−1 in the previous stage. The sequential circuit 30_n receives the signal RIN from the output terminal OUTA of the sequential circuit 30_n+2.

[0120] Specifically, the sequential circuit 30_1 receives the signals CK1, CK2, CK3, and SP, and the signal at the output terminal OUTA of the sequential circuit 30_3, and outputs output signals to the wirings OUTA1 and OUTB1. The sequential circuit 30_2 receives the signals CK2, CK3, and CK4, the signal at the output terminal OUTA of the sequential circuit 30_1, and the signal at the output terminal OUTA of the sequential circuit 30_4, and outputs output signals to the wirings OUTA2 and OUTB2.

[0121] 7C shows a timing chart relating to the driving method of the driving circuit 40. From the top, FIG. 7C shows the time changes in potential for the signal SP, signals CK1 to CK4, wirings OUTA1 to OUTA6, and wirings OUTB1 to OUTB6.

[0122] At time T0, the signal SP is at a high potential and the signal CK1 is at a low potential. At this time, low potentials are output to the wirings OUTA1 to OUTA6, and high potentials are output to the wirings OUTB2 to OUTB6. Furthermore, since the signal SP is at a high potential, a low potential is output to the wiring OUTB1.

[0123] At time T1, the signal CK1 changes from low potential to high potential, causing the sequential circuit 30_1 to output a high potential to the wiring OUTA1, while maintaining a low potential to the wiring OUTB1. Also at time T1, a low potential is output to the wiring OUTB2. Thereafter, signals CK1 to CK4 sequentially output high potentials to the wirings OUTA2 and subsequent wirings, and low potentials to the wirings OUTB2 and subsequent wirings.

[0124] The signals CK1 to CK4 are clock signals that are shifted by a quarter period, respectively, and therefore, as shown in Fig. 7C, signals such as the signal CK1 that are shifted by a quarter period are output to the wiring OUTA1 to OUTA6 and the wiring OUTB1 to OUTB6.

[0125] [Driver circuit configuration example 2] FIG. 8A shows an example of the configuration of a drive circuit 40a that is partially different from the configuration described above.

[0126] The driving circuit 40a is supplied with signals CK1 and CK2 as clock signals. The driving circuit 40a also includes a plurality of inverter circuits 80.

[0127] Either signal CK1 or signal CK2 is input to the input terminal of inverter circuit 80, and its inverted signal is output from the output terminal. The two inverted signals are shifted by a half period from signals CK1 and CK2, respectively, and are therefore similar to signals CK3 and CK4 in configuration example 1 above.

[0128] 8A, a pair of inverter circuits 80 is provided for every four sequential circuits 30_n. More specifically, three sequential circuits 30 are connected to one inverter circuit 80. By reducing the number of sequential circuits connected to one inverter circuit 80 in this way, the output capacity required of the inverter circuit 80 can be reduced, and the circuit size can be reduced.

[0129] The inverter circuit 80 preferably uses transistors formed through the same process as the sequential circuit 30. FIG. 8B shows an example of a configuration applicable to the inverter circuit 80. The inverter circuit 80 has a configuration similar to that of the circuit 13, and includes a p-channel transistor 81 and an n-channel transistor 82. As shown in FIG. 8B, for example, when a clock signal CK is input to the inverter circuit 80, an inverted clock signal CKB obtained by inverting the clock signal CK can be output.

[0130] The configuration of the drive circuit is not limited to this, and signals, wiring, etc. can be changed as appropriate according to the configuration of the sequential circuit used. For example, by using a sequential circuit with few input signals, such as the sequential circuit 10d and the sequential circuit 10e, it is possible to reduce one or both of the wiring and signals, thereby simplifying the drive circuit.

[0131] The above is a description of an example of the configuration of the drive circuit.

[0132] [Example of display device configuration] A structural example of a display device to which the driver circuit of one embodiment of the present invention can be applied will be described below.

[0133] 9A shows a block diagram of the display device 70. The display device 70 has a display unit DI, a pair of drive circuits GD, and a drive circuit SD.

[0134] The display unit DI has a plurality of pixels pix arranged in a matrix, each of which has one or more display elements and one or more transistors.

[0135] The driver circuit GD functions as a gate line driver circuit (also called a scanning line driver circuit or a gate driver), and the driver circuit SD functions as a source line driver circuit (also called a signal line driver circuit or a source driver).

[0136] The various sequential circuits exemplified above and the driver circuits using the sequential circuits can be used for the driver circuit GD.

[0137] Of the pixels pix provided in the display unit DI, the pixels pix located in odd-numbered rows are electrically connected to one drive circuit GD, and the pixels pix located in even-numbered rows are electrically connected to the other drive circuit GD. By using this configuration, the area occupied by each drive circuit GD can be reduced, and a display device with a narrow frame can be realized.

[0138] The driving circuit GD and the pixel pix are electrically connected via scanning lines GL1 and GL2, and the driving circuit SD and the pixel pix are electrically connected via signal lines SL.

[0139] Here, the output signal of the output terminal OUTA of the sequential circuit exemplified above is applied to the scanning line GL1. The output signal of the output terminal OUTB is applied to the scanning line GL2. Therefore, the scanning line GL1 is always applied with a high potential when selected and a low potential when not selected. On the other hand, the scanning line GL2 is always applied with a low potential when selected and a high potential when not selected.

[0140] FIG. 9B shows an example of a pixel pix. The pixel pix is ​​an example in which a light-emitting element is used as a display element. The pixel pix has a transistor 71, a transistor 72, a transistor 73, a light-emitting element 74, and a capacitor CS. The transistor 71 functions as a selection transistor. The transistor 72 functions as a drive transistor that controls the current flowing to the light-emitting element 74. The transistor 73 has a function of blocking the current flowing to the light-emitting element 74. The transistors 71 and 73 are n-channel transistors, and the transistor 72 is a p-channel transistor.

[0141] The transistor 71 has a gate electrically connected to the scan line GL1, one of its source and drain electrically connected to the signal line SL, and the other electrically connected to the gate of the transistor 72 and one electrode of the capacitor CS. The transistor 72 has one of its source and drain electrically connected to the wiring AL and the other electrode of the capacitor CS, and the other electrically connected to one of the source and drain of the transistor 73. The transistor 73 has a gate electrically connected to the scan line GL2, and the other of its source and drain electrically connected to one electrode of the light-emitting element 74. The light-emitting element 74 has the other electrode electrically connected to the wiring CL. An anode potential is applied to the wiring AL, and a cathode potential lower than the anode potential is applied to the wiring CL.

[0142] When writing the potential of the signal line SL to the pixel pix, a high potential is applied to the scanning line GL1, causing the transistor 71 to be conductive. At this time, a low potential is applied to the scanning line GL2, causing the transistor 73 to be non-conductive, and cutting off the current flowing to the light-emitting element 74. In this way, it is possible to prevent the light-emitting element 74 from emitting light at an unintended brightness when writing data to the pixel pix, thereby improving display quality.

[0143] After the write operation to pixel pix is ​​completed, a low potential is applied to scanning line GL1, turning off transistor 71. A high potential is applied to scanning line GL2, turning on transistor 73, and a current corresponding to the gate potential of transistor 72 flows through transistor 73 to light-emitting element 74.

[0144] The configuration of the pixel pix is ​​not limited to this, and various configurations are possible. For example, it is preferable to have a configuration that includes at least transistors whose gates are connected to the scanning lines GL1 and GL2, respectively.

[0145] The above is a description of an example of the configuration of the display device.

[0146] [Transistor configuration example] Hereinafter, a more specific configuration example of a transistor that can be applied to the above-described sequential circuits, driver circuits, display devices, etc. will be described. Here, the description will be made taking as an example an inverter circuit including a transistor having polycrystalline silicon in a channel formation region (LTPS transistor) and a transistor having an oxide semiconductor in a channel formation region (OS transistor).

[0147] [Configuration example 1] 10A shows a schematic top view of an inverter circuit. The inverter circuit includes a transistor 310 and a transistor 350. The transistor 310 is an LTPS transistor, and the transistor 350 is an OS transistor. The transistor 310 can be used as the above-described transistor 25, etc. The transistor 350 can be used as the above-described transistor 26, etc.

[0148] The OS transistor may be a transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed. The semiconductor layer preferably contains, for example, indium, M (M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more selected from aluminum, gallium, yttrium, and tin. In particular, an oxide containing indium, gallium, and zinc (also referred to as IGZO) is preferably used for the semiconductor layer of the OS transistor. Alternatively, an oxide containing indium, tin, and zinc is preferably used. Alternatively, an oxide containing indium, gallium, tin, and zinc is preferably used.

[0149] A transistor using an oxide semiconductor, which has a wider band gap and a lower carrier density than silicon, can have an extremely small off-state current, which enables charge stored in a capacitor connected in series with the transistor to be held for a long period of time.

[0150] 10A functions as an input terminal IN. A part of the conductive layer 314b functions as a part of the output terminal OUT. A part of the conductive layer 314c functions as a wiring to which a potential VSS is applied. A part of the conductive layer 314d functions as a wiring to which a potential VDD is applied.

[0151] 10A shows an example having six transistors 310 connected in parallel and four transistors 350 connected in parallel. When a large current needs to flow, for example, using transistors with relatively small channel lengths in parallel rather than using a single transistor with a large channel width can reduce heat generation due to the current and improve the reliability of the circuit.

[0152] Fig. 10B is a schematic cross-sectional view taken along the dashed line AB in Fig. 10A, showing the cross sections of the transistor 310 and the transistor 350 in the channel length direction.

[0153] An insulating layer 321 is provided over a substrate 301 , and a transistor 310 and a transistor 350 are provided over the insulating layer 321 .

[0154] The transistor 310 includes a semiconductor layer 311, an insulating layer 312 covering the semiconductor layer 311, and a conductive layer 313 located over the insulating layer 312 and overlapping with the semiconductor layer 311. An insulating layer 322 covering the conductive layer 313 and the insulating layer 312, an insulating layer 352 over the insulating layer 322, an insulating layer 326 over the insulating layer 352, and the like are provided. The semiconductor layer 311 contains polycrystalline silicon. The semiconductor layer 311 includes a channel formation region 311i and a pair of low-resistance regions 311p sandwiching the channel formation region 311i. A part of the insulating layer 312 functions as a gate insulating layer of the transistor 310. A part of the conductive layer 313 functions as a gate electrode of the transistor 310.

[0155] The insulating layer 322 preferably has a laminated structure in which a first insulating film having barrier properties against hydrogen and water and a second insulating film containing an oxide are laminated. The first insulating film corresponds to the insulating layer 62 illustrated in FIG. 1C and the like, and the second insulating film corresponds to the insulating layer 63. The above description can be used for materials that can be used for the first insulating film and the second insulating film.

[0156] The low-resistance region 311p is a region containing an impurity element. For example, if the transistor 310 is an n-channel transistor, phosphorus, arsenic, or the like may be added to the low-resistance region 311p. On the other hand, if the transistor 310 is a p-channel transistor, boron, aluminum, or the like may be added to the low-resistance region 311p. Here, the transistor 310 is a p-channel transistor. Furthermore, in order to control the threshold voltage of the transistor 310, the above-mentioned impurities may be added to the channel formation region 311i.

[0157] The transistor 350 includes a conductive layer 313 over an insulating layer 312, an insulating layer 322 covering the conductive layer 313, a semiconductor layer 351 over the insulating layer 322, an insulating layer 352 covering the semiconductor layer 351, and a conductive layer 353a located over the insulating layer 352 and overlapping with the semiconductor layer 351. An insulating layer 326 is provided to cover the insulating layer 352 and the conductive layer 353a. The semiconductor layer 351 includes an oxide semiconductor.

[0158] A region of the semiconductor layer 351 overlapping with either or both of the conductive layer 353a and the conductive layer 313 functions as a channel formation region. Part of the insulating layer 322 functions as a back-gate insulating layer (second gate insulating layer) of the transistor 350. Part of the insulating layer 352 functions as a gate insulating layer (first gate insulating layer) of the transistor 350. Another part of the conductive layer 313 functions as a back-gate electrode (second gate electrode) of the transistor 350. Part of the conductive layer 353a functions as a gate electrode (first gate electrode) of the transistor 350.

[0159] A conductive layer 314a, a conductive layer 314b, and a conductive layer 314c are provided over the insulating layer 326. The conductive layer 314a and the conductive layer 314b are provided in the insulating layer 326, the insulating layer 352, the insulating layer 322, and the insulating layer 312, and are electrically connected to the low-resistance region 311p through openings that reach the low-resistance region 311p. The conductive layer 314b and the conductive layer 314c are provided in the insulating layer 326 and the insulating layer 352, and are electrically connected to the semiconductor layer 351 through openings that reach the semiconductor layer 351.

[0160] 10A and 10B, the conductive layer 313 serves as both the gate electrode of the transistor 310 and the backgate electrode of the transistor 350. The conductive layer 353a and the conductive layer 313 are electrically connected to each other through an opening indicated by a dashed line, and are supplied with the same potential input from the input terminal IN.

[0161] An example of a transistor configuration that is partially different from the above will be described below.

[0162] [Configuration example 2] 11A illustrates an example in which a transistor 310a having a pair of gate electrodes is used instead of the transistor 310. The transistor 310a differs from the transistor 310 mainly in that a conductive layer 315 and an insulating layer 316 are included.

[0163] The conductive layer 315 is provided over the insulating layer 321. An insulating layer 316 is provided to cover the conductive layer 315 and the insulating layer 321. The semiconductor layer 311 is provided so that at least a channel formation region 311i overlaps with the conductive layer 315 with the insulating layer 316 interposed therebetween.

[0164] In the transistor 310a, part of the conductive layer 313 functions as a first gate electrode, and part of the conductive layer 315 functions as a second gate electrode. In this case, part of the insulating layer 312 functions as a first gate insulating layer, and part of the insulating layer 316 functions as a second gate insulating layer.

[0165] Here, when the first gate electrode and the second gate electrode are electrically connected, the conductive layer 313 and the conductive layer 315 may be electrically connected through openings provided in the insulating layer 312 and the insulating layer 316 in a region not shown. When the second gate electrode and the source or drain are electrically connected, the conductive layer 314a or the conductive layer 314b may be electrically connected to the conductive layer 315 through openings provided in the insulating layer 322, the insulating layer 312, and the insulating layer 316 in a region not shown.

[0166] [Configuration Example 3] 11B shows an example in which a transistor 350a is used instead of the transistor 350 in FIG. 10B. The transistor 350a differs mainly in that the shape of the insulating layer 352 is different.

[0167] The insulating layer 352 is processed using the same resist mask as the conductive layer 353b. A surface of a region of the semiconductor layer 351 that is not covered with the insulating layer 352 is in contact with the insulating layer 326. In the region of the semiconductor layer 351 that is in contact with the insulating layer 326, more carriers can be present than in the channel formation region, and therefore, the electrical resistance can be suitably reduced.

[0168] 11B shows an example in which the end of the conductive layer 353b is located inside the end of the insulating layer 352. With this configuration, a relatively high-resistance region can be provided in the semiconductor layer 351 between the channel formation region and the low-resistance region. That is, an LDD (Lightly Doped Drain) structure is realized, thereby improving reliability. However, the present invention is not limited to this. The end of the conductive layer 353b and the end of the insulating layer 352 may be processed so that they roughly coincide with each other, and the insulating layer 352 and the conductive layer 353b may be processed so that their top surfaces roughly coincide with each other.

[0169] In this specification, the phrase "top surface shapes generally match" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" also applies.

[0170] [Configuration Example 4] 11C shows an example in which a transistor 310a and a transistor 350a are used. The above description can be applied to the configurations of the transistor 310a and the transistor 350a.

[0171] The above is a description of an example of the configuration of a transistor.

[0172] [About metal oxides] Metal oxides that can be used for the semiconductor layer of an OS transistor will be described below.

[0173] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides. For example, nitrogen-containing metal oxides such as zinc oxynitride (ZnON) may be used for the semiconductor layer.

[0174] In this specification, etc., they may be referred to as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite). CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration.

[0175] For example, the semiconductor layer can be made of a cloud-aligned composite (CAC)-oxide semiconductor (OS).

[0176] CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and functions as a semiconductor as a whole. When CAC-OS or CAC-metal oxide is used in the semiconductor layer of a transistor, the conductive function is a function of allowing electrons (or holes) to flow as carriers, and the insulating function is a function of preventing the flow of electrons as carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0177] Furthermore, CAC-OS or CAC-metal oxide has conductive regions and insulating regions. The conductive regions have the above-mentioned conductive function, and the insulating regions have the above-mentioned insulating function. In addition, the conductive regions and the insulating regions may be separated at the nanoparticle level in the material. In addition, the conductive regions and the insulating regions may be unevenly distributed in the material. In addition, the conductive regions may be observed as connected in a cloud-like shape with the periphery blurred.

[0178] In addition, in CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may be dispersed in the material with sizes of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0179] Furthermore, the CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, the CAC-OS or CAC-metal oxide is composed of a component with a wide gap due to an insulating region and a component with a narrow gap due to a conductive region. In this configuration, when carriers flow, the carriers mainly flow in the component with the narrow gap. Furthermore, the component with the narrow gap acts complementarily with the component with the wide gap, and carriers also flow in the component with the wide gap in conjunction with the component with the narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, the transistor can achieve high current driving power in the on state, i.e., a large on-state current, and high field-effect mobility.

[0180] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0181] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors, such as c-axis aligned crystalline oxide semiconductors (CAAC-OS), polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0182] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0183] Nanocrystals are basically hexagonal, but not necessarily regular hexagonal, and may have non-regular hexagonal shapes. The distortion may also result in pentagonal, heptagonal, or other lattice arrangements. It is difficult to identify clear grain boundaries in CAAC-OS even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction or the change in interatomic bond distance caused by substitution with metal elements.

[0184] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. Note that indium and the element M are mutually substituted, and when the element M in an (M,Zn) layer is substituted with indium, the layer can also be referred to as an (In,M,Zn) layer. When the indium in an In layer is substituted with the element M, the layer can also be referred to as an (In,M) layer.

[0185] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is difficult to identify clear grain boundaries in CAAC-OS, so it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. In addition, since the crystallinity of metal oxides can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS is not prone to impurities and defects (oxygen vacancies (V OIt can also be said that these metal oxides have low oxygen vacancies. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0186] The nc-OS has periodic atomic arrangement in a small region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0187] Indium-gallium-zinc oxide (IGZO), a type of metal oxide containing indium, gallium, and zinc, can sometimes have a stable structure when made into the above-mentioned nanocrystals. In particular, because IGZO tends to have difficulty growing crystals in the atmosphere, it may be structurally more stable when made into small crystals (such as the above-mentioned nanocrystals) than large crystals (here, crystals of a few millimeters or a few centimeters).

[0188] The a-like OS is a metal oxide having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0189] Oxide semiconductors (metal oxides) have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0190] A metal oxide film functioning as a semiconductor layer can be formed using either or both of an inert gas and an oxygen gas. The oxygen flow rate (oxygen partial pressure) during the formation of the metal oxide film is not particularly limited. However, in order to obtain a transistor with high field-effect mobility, the oxygen flow rate (oxygen partial pressure) during the formation of the metal oxide film is preferably 0% to 30%, more preferably 5% to 30%, and even more preferably 7% to 15%.

[0191] The metal oxide preferably has an energy gap of 2 eV or more, more preferably 2.5 eV or more, and further preferably 3 eV or more. By using a metal oxide with such a wide energy gap, the off-state current of a transistor can be reduced.

[0192] The substrate temperature during deposition of the metal oxide film is preferably 350° C. or lower, more preferably room temperature or higher and 200° C. or lower, and even more preferably room temperature or higher and 130° C. If the substrate temperature during deposition of the metal oxide film is room temperature, productivity can be increased, which is preferable.

[0193] The metal oxide film can be formed by sputtering, or by other methods such as PLD, PECVD, thermal CVD, ALD, and vacuum deposition.

[0194] This concludes the explanation of metal oxides.

[0195] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0196] (Embodiment 2) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 12A to 12C.

[0197] 12A includes a pixel portion 502, a driver circuit portion 504, a protective circuit 506, and a terminal portion 507. Note that the protective circuit 506 may not be provided.

[0198] The pixel section 502 has pixel circuits 501 arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). Each pixel circuit 501 has a circuit for driving a display element.

[0199] The driver circuit unit 504 includes driver circuits such as a gate driver 504a that outputs scan signals to the gate lines GL_1 to GL_X and a source driver 504b that supplies data signals to the data lines DL_1 to DL_Y. The gate driver 504a may include at least a shift register. The source driver 504b may include, for example, a plurality of analog switches. Alternatively, the source driver 504b may include a shift register.

[0200] The sequential circuit of one embodiment of the present invention can be applied to the gate driver 504a. The sequential circuit of one embodiment of the present invention can also be applied to the source driver 504b.

[0201] The terminal portion 507 is a portion provided with terminals for inputting power, control signals, image signals, and the like from an external circuit to the display device.

[0202] The protection circuit 506 is a circuit that, when a potential outside a certain range is applied to a wiring connected to the protection circuit 506, brings the wiring into a conductive state with another wiring. The protection circuit 506 shown in Fig. 12A is connected to various wirings, such as a gate line GL that is a wiring between the gate driver 504a and the pixel circuit 501, or a data line DL that is a wiring between the source driver 504b and the pixel circuit 501. Note that in Fig. 12A, the protection circuit 506 is hatched to distinguish it from the pixel circuit 501.

[0203] Furthermore, the gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel unit 502, or a substrate on which a gate driver circuit or a source driver circuit is separately formed (for example, a drive circuit substrate formed of a single crystal semiconductor or a polycrystalline semiconductor) may be mounted on the substrate on which the pixel unit 502 is provided by COG or TAB (Tape Automated Bonding).

[0204] 12B and 12C show an example of the configuration of a pixel circuit that can be applied to pixel circuit 501. 12B and 12C show a pixel circuit in the mth row and nth column (m is a natural number greater than or equal to 1 and less than or equal to X, and n is a natural number greater than or equal to 1 and less than or equal to Y).

[0205] 12B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL, and the like.

[0206] The potential of one of the pair of electrodes of the liquid crystal element 570 is set as appropriate according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by written data. Note that a common potential may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Alternatively, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuits 501 in each row.

[0207] 12C includes a transistor 552, a transistor 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL_a, a potential supply line VL_b, and the like.

[0208] A potential VDD, which is a high power supply potential, is applied to one of the potential supply lines VL_a and VL_b, and a potential VSS, which is a low power supply potential, is applied to the other. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the gate of the transistor 554, thereby controlling the luminance of light emitted from the light-emitting element 572.

[0209] When a light-emitting element is used as a display element, it is preferable to use an EL element such as an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode). Examples of light-emitting materials that EL elements have include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (quantum dot materials, etc.). LEDs such as micro LEDs (light-emitting diodes) can also be used as light-emitting elements.

[0210] LEDs come in a variety of sizes, from large to small, including macro LEDs (also known as giant LEDs), mini LEDs, and micro LEDs. Here, LED chips with a side dimension of over 1 mm are called macro LEDs, those with a side dimension of over 100 μm but less than 1 mm are called mini LEDs, and those with a side dimension of 100 μm or less are called micro LEDs. Micro LEDs are particularly preferable as the LED element used in pixels. Using micro LEDs makes it possible to realize extremely high-definition display devices.

[0211] The transistor 550 shown in FIG. 12B or the transistors 552 and 554 shown in FIG. 12C are preferably provided over the same substrate as the transistors included in the gate driver 504a.

[0212] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented by appropriately combining with other configuration examples or drawings.

[0213] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0214] (Embodiment 3) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

[0215] A display module 6000 shown in FIG. 13A has a display device 6006 connected by an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

[0216] For example, a display device manufactured using one embodiment of the present invention can be used as the display device 6006. The display device 6006 can provide a display module with extremely low power consumption.

[0217] The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be changed appropriately to match the size of the display device 6006.

[0218] The display device 6006 may have a function as a touch panel.

[0219] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0220] The printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting video signals and clock signals, a battery control circuit, and the like.

[0221] FIG. 13B is a schematic cross-sectional view of the display module 6000 when an optical touch sensor is provided.

[0222] The display module 6000 has a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. The display module 6000 also has a pair of light guiding sections (light guiding section 6017a, light guiding section 6017b) in an area surrounded by an upper cover 6001 and a lower cover 6002.

[0223] The display device 6006 is provided so as to overlap a printed circuit board 6010, a battery 6011, and the like with a frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to a light guide portion 6017a and a light guide portion 6017b.

[0224] Light 6018 emitted from light-emitting unit 6015 passes through light-guiding unit 6017a, passes through the upper part of display device 6006, and reaches light-receiving unit 6016 through light-guiding unit 6017b. When light 6018 is blocked by a detectable object such as a finger or a stylus, a touch operation can be detected.

[0225] A plurality of light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light-receiving units 6016 are provided at positions facing the light-emitting units 6015. This makes it possible to obtain information about the position where a touch operation is performed.

[0226] The light-emitting unit 6015 may be a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared light. The light-receiving unit 6016 may be a photoelectric element that receives the light emitted by the light-emitting unit 6015 and converts it into an electrical signal. Preferably, a photodiode that can receive infrared light may be used.

[0227] The light guiding portions 6017a and 6017b that control the path of the light 6018 allow the light emitting portion 6015 and the light receiving portion 6016 to be disposed below the display device 6006, thereby preventing external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, using a resin that absorbs visible light and transmits infrared light can more effectively prevent the touch sensor from malfunctioning.

[0228] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0229] (Fourth embodiment) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described.

[0230] Electronic device 6500 shown in FIG. 14A is a portable information terminal that can be used as a smartphone.

[0231] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0232] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0233] FIG. 14B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0234] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0235] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0236] A part of the display panel 6511 is folded back in an area outside the display unit 6502. An FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is also connected to a terminal provided on a printed circuit board 6517.

[0237] The flexible display panel of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0238] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0239] (Embodiment 5) In this embodiment, electronic devices including a display device manufactured using one embodiment of the present invention will be described.

[0240] The electronic devices exemplified below each include a display device according to one embodiment of the present invention in a display portion. Therefore, the electronic devices can achieve high resolution. Furthermore, the electronic devices can also have both high resolution and a large screen.

[0241] The display portion of the electronic device of one embodiment of the present invention can display images with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0242] Examples of electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0243] An electronic device to which one embodiment of the present invention is applied can be incorporated along a flat or curved surface of an inner or outer wall of a house or building, or the interior or exterior of an automobile or the like.

[0244] FIG. 15A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0245] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. The camera 8000 also has a detachable lens 8006 attached thereto.

[0246] The camera 8000 may have the lens 8006 and the housing integrated together.

[0247] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display unit 8002 that functions as a touch panel.

[0248] The housing 8001 has a mount with electrodes, and can be connected to a finder 8100 as well as a strobe device and the like.

[0249] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0250] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display unit 8102.

[0251] The button 8103 has a function such as a power button.

[0252] The display device of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a finder 8100. Note that the camera 8000 may have a built-in finder.

[0253] FIG. 15B is a diagram showing the appearance of the head mounted display 8200.

[0254] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 has a built-in battery 8206.

[0255] A cable 8205 supplies power from a battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like, and can display received video information on a display portion 8204. The main body 8203 also includes a camera, and can use information on the movement of the user's eyeballs or eyelids as an input means.

[0256] The wearing unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes at positions that come into contact with the user and capable of detecting a current that flows in accordance with the movement of the user's eyeballs. The wearing unit 8201 may also have a function of monitoring the user's pulse rate based on the current that flows through the electrodes. The wearing unit 8201 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204 or a function of changing the image displayed on the display unit 8204 in accordance with the movement of the user's head.

[0257] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0258] 15C, 15D, and 15E are diagrams showing the appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display unit 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0259] A user can view the display on the display portion 8302 through the lens 8305. Note that it is preferable to arrange the display portion 8302 in a curved manner because the user can feel a high sense of presence. In addition, by viewing different images displayed in different regions of the display portion 8302 through the lens 8305, it is possible to perform 3D display using parallax. Note that the present invention is not limited to a configuration in which one display portion 8302 is provided, and two display portions 8302 may be provided, with one display portion being provided for each eye of the user.

[0260] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. The display device including the semiconductor device of one embodiment of the present invention has extremely high definition; therefore, even when an image is enlarged using the lens 8305 as in FIG. 15E, pixels are not visible to a user, and more realistic images can be displayed.

[0261] The electronic device shown in Figures 16A to 16G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0262] 16A to 16G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic device are not limited to these, and the electronic device may have various other functions. The electronic device may have multiple display units. Furthermore, the electronic device may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on the display unit, etc.

[0263] The electronic device shown in FIGS. 16A to 16G will be described in detail below.

[0264] 16A is a perspective view showing a television device 9100. The television device 9100 can incorporate a display unit 9001 with a large screen, for example, 50 inches or more, or 100 inches or more.

[0265] FIG. 16B is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. The mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text or image information on multiple surfaces thereof. FIG. 16B shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and the strength of antenna reception. Alternatively, an icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0266] 16C is a perspective view showing mobile information terminal 9102. Mobile information terminal 9102 has a function of displaying information on three or more sides of display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, while carrying mobile information terminal 9102 in a breast pocket of clothes, the user can check information 9053 displayed in a position that can be observed from above mobile information terminal 9102. The user can check the display without taking mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0267] 16D is a perspective view showing a wristwatch-type mobile information terminal 9200. The display surface of the display unit 9001 is curved, and a display can be displayed along the curved display surface. The mobile information terminal 9200 can also perform hands-free conversations by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and reception with another information terminal or charge itself via a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0268] 16E, 16F, and 16G are perspective views showing a foldable mobile information terminal 9201. FIG. 16E shows the mobile information terminal 9201 in an unfolded state, FIG. 16G shows it in a folded state, and FIG. 16F is a perspective view showing a state in the process of changing from one of FIG. 16E and FIG. 16G to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent viewability of the display. A display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0269] 17A shows an example of a television device. A television device 7100 has a display unit 7500 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0270] 17A can be operated not only by operation switches provided on the housing 7101 but also by a separate remote control 7111. Alternatively, a touch panel may be applied to the display portion 7500, and the television 7100 may be operated by touching the touch panel. The remote control 7111 may have a display portion in addition to operation buttons.

[0271] The television device 7100 may include not only a television broadcast receiver but also a communication device for network connection.

[0272] 17B shows a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7500 is incorporated in the housing 7211.

[0273] 17C and 17D show an example of a digital signage.

[0274] 17C includes a housing 7301, a display unit 7500, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0275] 17D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the pillar 7401.

[0276] The larger the display unit 7500, the more information can be provided at one time, and the larger the display unit 7500 is, the more easily it will catch people's attention, which will have the effect of increasing the advertising effectiveness of advertisements, for example.

[0277] It is preferable to use a touch panel for the display unit 7500 so that the user can operate it. This allows the display unit 7500 to be used not only for advertising purposes but also for providing users with information they require, such as route information, traffic information, and commercial facility guidance information.

[0278] 17C and 17D , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311, and the display on the display unit 7500 can be switched by operating the information terminal 7311.

[0279] Furthermore, a game using the information terminal device 7311 as an operation means (controller) can be executed on the digital signage 7300 or the digital signage 7400. This allows an unspecified number of users to simultaneously participate in and enjoy the game.

[0280] The display device of one embodiment of the present invention can be applied to the display portion 7500 in FIGS. 17A to 17D.

[0281] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification. [Explanation of symbols]

[0282] LIN, RIN, RES, CLK: Signal: IN: Input terminal: OUT: Output terminal: OUTA, OUTB: Output terminal: SP: Signal: GD, SD: Driver circuit: 10, 10a to 10i: Sequential circuit: 11 to 13: Circuit: 15a, 15b: Wiring: 21, 22, 23: Transistor: 24n, 24p: Transistor: 25, 26: Transistor: 30: Sequential circuit: 31 to 34: Transistor: 40, 40a: Driver circuit: 41 to 47: Transistor: 51: Semiconductor layer: 51p: Low resistance region: 52: Gate insulating layer: 53: Gate electrode: 54a: Conductive layer: 54b: Conductive layer: 54c: Conductive layer: 56n: Low resistance region: 56: Semiconductor Body layer: 57: Gate insulating layer: 58: Gate electrode: 60-64: Insulating layer: 70: Display device: 71-73: Transistor: 74: Light-emitting element: 80: Inverter circuit: 81: Transistor: 82: Transistor: 301: Substrate: 310, 310a: Transistor: 311: Semiconductor layer: 311i: Channel forming region: 311n: Resistance region: 311p: Resistance region: 312: Insulating layer: 313: Conductive layer: 314a-314d: Conductive layer: 315: Conductive layer: 316: Insulating layer: 321, 322: Insulating layer: 326: Insulating layer: 350, 350a: Transistor: 351: Semiconductor layer: 352: Insulating layer: 353a, 353b: Conductive layer

Claims

[Claim 1] a first transistor and a second transistor; the first transistor has a first semiconductor layer, a first gate electrode, a first electrode, and a second electrode; the second transistor has a second semiconductor layer, a second gate electrode, a third electrode, and a fourth electrode; the first gate electrode and the second gate electrode are electrically connected to each other; the second electrode and the third electrode are electrically connected to each other, a first insulating layer on the first semiconductor layer and a second insulating layer on the first insulating layer; the second semiconductor layer is provided on and in contact with the second insulating layer; the first insulating layer is less susceptible to hydrogen diffusion than the second insulating layer; the second insulating layer includes an oxide; the first semiconductor layer includes polycrystalline silicon; the second semiconductor layer includes a metal oxide; the first transistor is a p-type transistor, the second transistor is an n-type transistor; Semiconductor device.

Images