Display device

Abstract

To provide a display device capable of achieving an improvement in yield.SOLUTION: A display device according to an embodiment includes: a display area including a plurality of pixels; a plurality of display elements arranged in the plurality of pixels, respectively, each display element including an organic layer that emits light according to an application of voltage; a dummy pixel area including a plurality of dummy pixels, the dummy pixel area being located outside the display area; and a partition wall including a conductive lower portion and an upper portion having an end projecting from a side face of the lower portion, the partition wall surrounding each of the plurality of pixels and each of the plurality of dummy pixels. The partition wall has an outer peripheral portion located outside the dummy pixel area and is separated into a plurality of segments by slits which each pass through the display area and the dummy pixel area to reach the outer peripheral portion.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have come into practical use. Techniques for improving the yield of such display devices are needed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device that can improve yield. [Means for solving the problem]

[0005] In general, according to an embodiment, a display device includes a display area including a plurality of pixels, a plurality of display elements disposed in the plurality of pixels, each display element including an organic layer that emits light in response to application of a voltage, a dummy pixel area including a plurality of dummy pixels and positioned outside the display area, and a partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion, surrounding each of the plurality of pixels and the plurality of dummy pixels. The partition wall has a peripheral portion positioned outside the dummy pixel area, and is divided into a plurality of segments by slits that pass through the display area and the dummy pixel area to the peripheral portion.

[0006] According to another aspect of the embodiment, a display device includes a display region including a plurality of pixels, a plurality of display elements disposed in the plurality of pixels, each display element including an organic layer that emits light in response to application of a voltage, and a partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion, surrounding each of the plurality of pixels. The partition wall has a peripheral portion located outside the display region, and is divided into a plurality of segments by slits that pass through the display region to the peripheral portion. The slits have a first width in the display region, and a second width greater than the first width in at least a portion of the peripheral portion. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view showing some elements of the display device. [Figure 5] FIG. 5 is a schematic plan view showing an example of a configuration applicable to the partition wall according to the first embodiment. [Figure 6] FIG. 6 is a schematic plan view showing an example of the relationship between the sealing layer and the slits according to the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view of the display device taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a flowchart showing an example of a method for manufacturing a display device. [Figure 9A] FIG. 9A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 9B] FIG. 9B is a schematic cross-sectional view showing a step subsequent to FIG. 9A. [Figure 9C] FIG. 9C is a schematic cross-sectional view showing a step subsequent to FIG. 9B. [Figure 9D] FIG. 9D is a schematic cross-sectional view showing a step subsequent to FIG. 9C. [Figure 9E] FIG. 9E is a schematic cross-sectional view showing a step subsequent to FIG. 9D. [Figure 9F] FIG. 9F is a schematic cross-sectional view showing a step subsequent to FIG. 9E. [Figure 9G] FIG. 9G is a schematic cross-sectional view showing a step subsequent to FIG. 9F. [Figure 9H] FIG. 9H is a schematic cross-sectional view showing a step subsequent to FIG. 9G. [Figure 9I] FIG. 9I is a schematic cross-sectional view showing a step subsequent to FIG. 9H. [Figure 9J] FIG. 9J is a schematic cross-sectional view showing a step subsequent to FIG. 9I. [Figure 10] FIG. 10 is a diagram for explaining the effects of the display device according to the first embodiment. [Figure 11] FIG. 11 is a diagram for explaining the effects of the display device according to the first embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view of a configuration according to a comparative example to the first embodiment. [Figure 13] FIG. 13 is a schematic plan view of a partition wall according to a comparative example to the first embodiment. [Figure 14] FIG. 14 is a schematic plan view showing the configuration according to the second embodiment. [Figure 15] FIG. 15 is a schematic plan view showing the configuration according to the third embodiment. [Figure 16] FIG. 16 is a schematic plan view showing the configuration according to the fourth embodiment. [Figure 17] FIG. 17 is a schematic plan view showing the configuration according to the fifth embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view of the display device taken along line XVIII-XVIII in FIG. [Figure 19] FIG. 19 is a schematic plan view showing the configuration according to the sixth embodiment. [Figure 20] FIG. 20 is a schematic plan view showing the configuration according to the seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 and the display area DA in a plan view is circular. However, the shape of the substrate 10 and the display area DA in a plan view is not limited to circular, and may be other shapes such as rectangular, square, or elliptical.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1 (first subpixel), a green subpixel SP2 (second subpixel), and a red subpixel SP3 (third subpixel). The pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The display device DSP further includes a terminal section T arranged in the peripheral area SA. To the terminal section T, for example, a flexible circuit board is connected that supplies voltages and signals for driving the display device DSP.

[0015] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0016] In the display area DA, a plurality of scanning lines G that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines S that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL are arranged. In the example of Fig. 1, the scanning lines G and the power supply lines PL extend in the X direction, and the signal lines S extend in the Y direction.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line G. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line S, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0018] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3 that constitute one pixel PX. In the example of Fig. 2, the subpixels SP1 and SP3 are aligned in the Y direction. Furthermore, the subpixels SP1 and SP3 are aligned with the subpixel SP2 in the X direction.

[0020] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP2 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0021] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 2, the pixel openings AP1 and AP3 are quadrangles with the same area. On the other hand, the pixel opening AP2 is a rectangle that is longer in the Y direction than the pixel openings AP1 and AP3. However, the shapes of the pixel openings AP1, AP2, and AP3 are not limited to this example.

[0022] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0023] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 (first display element) of the subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 (second display element) of the subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 (third display element) of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0024] Conductive partition walls 6 are disposed above the rib layer 5. The partition walls 6 function as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition walls 6 entirely overlap the rib layer 5 and have the same planar shape as the rib layer 5. The partition walls 6 surround each of the multiple pixels PX arranged in the display area DA. More specifically, the partition walls 6 surround each of the subpixels SP1, SP2, and SP3.

[0025] As will be described in detail later, the partition wall 6 has a plurality of slits SL. In the example of Fig. 2, each slit SL extends in the Y direction. For example, the sub-pixels SP1, SP2, and SP3 that make up one pixel PX are arranged between two slits SL that are adjacent to each other in the X direction.

[0026] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines G, signal lines S, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0027] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3 , the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0028] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhanging shape.

[0029] In the example of FIG. 3, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0030] 3, the upper portion 62 includes a first top layer 65 and a second top layer 66 disposed on the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, the present invention is not limited to this, and the first top layer 65 and the second top layer 66 may have the same width.

[0031] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0032] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0033] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0034] Sealing layers SE11, SE12, and SE13 (first to third sealing layers) are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the display element DE1 and the partition wall 6 around it. The sealing layer SE12 continuously covers the display element DE2 and the partition wall 6 around it. The sealing layer SE13 continuously covers the display element DE3 and the partition wall 6 around it.

[0035] 3, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6. In addition, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact with each other above the partition wall 6.

[0036] For example, gaps are formed between the sealing layers SE11, SE12, and SE13 and the upper portion 62 of the partition wall 6. The stacked films FL1, FL2, and FL3 may be disposed in at least a part of these gaps.

[0037] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0038] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive). Electrodes constituting the touch panel may be disposed on the sealing layer SE2.

[0039] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0040] The lower electrodes LE1, LE2, and LE3 each include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0041] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0042] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0043] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0045] The first top layer 65 of the partition wall 6 is formed of, for example, a metal material. The second top layer 66 of the partition wall 6 is formed of, for example, a conductive oxide. Examples of the metal material that can be used to form the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the second top layer 66 include ITO or IZO. The upper portion 62 may include three or more layers or may be formed of a single layer. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0046] A common voltage is supplied to the partition wall 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel voltage corresponding to the video signal of the signal line S is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0047] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0048] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0049] 4 is a schematic plan view showing some elements of the display device DSP. The partition walls 6 and the upper electrodes UE1, UE2, and UE3 constitute a common electrode CE that applies a common voltage to the display elements DE1, DE2, and DE3. The common electrode CE has, for example, a circular shape and entirely overlaps the display area DA.

[0050] The common electrode CE has a plurality of slits SL, at least one end of which reaches the outer edge (the outline in a plan view) of the common electrode CE. In the example of Fig. 4, both ends of the slits SL reach the outer edge of the common electrode CE. This divides the common electrode CE into a plurality of segments SG spaced apart by each slit SL.

[0051] In the example of Fig. 4, the slits SL extend in the Y direction. As another example, the slits SL may extend parallel to the X direction. The number of slits SL provided in the common electrode CE is not particularly limited. In one example, at least 17 slits SL are provided, thereby dividing the common electrode CE into at least 18 segments.

[0052] The intervals between the slits SL in the X direction are, for example, constant. In this case, the width of each segment SG in the X direction is also constant. As another example, the intervals between the slits SL and the width of the segments SG do not have to be constant.

[0053] Each segment SG has a first end Ea and a second end Eb in the extension direction of the slit SL (Y direction in this embodiment). The first end Ea is connected to a power supply line PW provided in the peripheral area SA. The power supply line PW is connected to a terminal portion T. A common voltage is applied to each segment SG from the terminal portion T via the power supply line PW. In the example of FIG. 4, the second ends Eb of each segment SG are separated by the slit SL and are not connected by a conductive member such as the power supply line PW.

[0054] 5 is a schematic plan view showing an example of a configuration applicable to the partition wall 6 according to this embodiment. In this drawing, attention is focused on the vicinity of the first end Ea of each segment SG.

[0055] In this embodiment, a dummy pixel area DM is provided outside the display area DA. The dummy pixel area DM is part of the peripheral area SA described above. The dummy pixel area DM includes a plurality of dummy pixels DPX and surrounds the display area DA. From another perspective, the plurality of dummy pixels DPX are arranged to surround the plurality of pixels PX arranged in the display area DA.

[0056] For example, the dummy pixel DPX includes dummy subpixels DP1, DP2, and DP3. The dummy subpixels DP1, DP2, and DP3 have structures similar to those of the subpixels SP1, SP2, and SP3, respectively. However, the dummy subpixels DP1, DP2, and DP3 are configured not to emit light. Such a configuration can be achieved, for example, by cutting a portion of the pixel circuit 1 in each of the dummy subpixels DP1, DP2, and DP3. Furthermore, the pixel apertures AP1, AP2, and AP3 may be omitted in each of the dummy subpixels DP1, DP2, and DP3.

[0057] A portion of the partition 6 is located in the dummy pixel region DM and surrounds each of the dummy pixels DPX. More specifically, the partition 6 surrounds each of the dummy subpixels DP1, DP2, and DP3. The shape and layout of the openings of the partition 6 in each of the dummy subpixels DP1, DP2, and DP3 are similar to the shape and layout of the openings of the partition 6 in each of the subpixels SP1, SP2, and SP3.

[0058] In the example of Fig. 5, the partition wall 6 further includes an outer peripheral portion OP located outside the dummy pixel region DM. For example, the outer peripheral portion OP does not have openings like those of the dummy subpixels DP1, DP2, and DP3. However, the outer peripheral portion OP may have openings of different shapes from those of the dummy subpixels DP1, DP2, and DP3. The outer peripheral portion OP is connected to the power supply line PW shown in Fig. 4 via multiple contact portions CT.

[0059] For example, the outer peripheral portion OP surrounds the display area DA and the dummy pixel area DM. As another example, the outer peripheral portion OP may be provided in part of the periphery of the display area DA and the dummy pixel area DM.

[0060] The slits SL are provided in portions of the partition walls 6 that extend parallel to the Y direction. Specifically, in the example of FIG. 5, the slits SL are provided in each portion of the partition walls 6 that is located between pixels PX adjacent to each other in the X direction. However, the form of the slits SL is not limited to this example. For example, two or more pixels PX aligned in the X direction may be located between adjacent slits SL.

[0061] The ends of the slits SL are located in the outer peripheral portion OP, that is, the slits SL pass through the display area DA and the dummy pixel area DM to reach the outer peripheral portion OP.

[0062] In the example of Fig. 5, the end of the slit SL does not reach the outer edge Eop of the outer peripheral portion OP. As a result, a continuous portion PP that is not separated by the slit SL is formed between the end of the slit SL and the outer edge Eop. The continuous portion PP connects the first ends Ea of the segments SG. A plurality of contact portions CT are located in the continuous portion PP.

[0063] 4, the second end Eb of the segment SG is not connected by a continuous portion PP, etc. In other words, the second end Eb reaches the outer edge Eop of the outer periphery portion OP.

[0064] The pixel PX has a width Wy in the Y direction (extension direction of the slit SL). The width of the dummy pixel DPX in the Y direction is, for example, equal to the width Wy. The width Wy corresponds to the pitch of the multiple pixels PX aligned in the Y direction. For example, the length Ls of the slit SL in the outer peripheral portion OP is equal to or greater than the width Wy (Ls≧Wy).

[0065] The slit SL has a width Ws1 (first width) in the display area DA. The slit SL also has a width Ws2 (second width) in at least a part of the outer peripheral portion OP. The width Ws2 is greater than the width Ws1 (Ws2>Ws1).

[0066] From another perspective, the slit SL has a widened portion Ps1 located in the outer peripheral portion OP. In the example of Fig. 5, the slit SL located in the outer peripheral portion OP is entirely composed of the widened portion Ps1. As another example, the slit SL may have a narrow portion in the outer peripheral portion OP that is narrower than the widened portion Ps1.

[0067] 6 is a schematic plan view showing an example of the relationship between the sealing layers SE11, SE12, and SE13 and the slits SL. The sealing layers SE11 and SE12 are formed in an island shape in the subpixels SP1 and SP3, respectively. The sealing layer SE12 is formed continuously across, for example, multiple subpixels SP2 aligned in the Y direction. As another example, the sealing layer SE12 may be formed for each subpixel SP2.

[0068] The ends of the sealing layers SE11, SE12, and SE13 are entirely located above the partition wall 6. In the example of Fig. 6, none of the sealing layers SE11, SE12, and SE13 overlaps with the slit SL. However, at least one of the sealing layers SE11, SE12, and SE13 may overlap with the slit SL.

[0069] The slit SL extends in the Y direction between the sealing layer SE11 and the sealing layer SE12 and between the sealing layer SE13 and the sealing layer SE12. The portion of the partition wall 6 where the slit SL is provided is divided by the slit SL into partition walls 6A and 6B.

[0070] Fig. 7 is a schematic cross-sectional view of the display device DSP taken along line VII-VII in Fig. 6. In this figure, elements below the organic insulating layer 12 and elements above the resin layer RS1 are omitted.

[0071] 7, the partition walls 6A and 6B each have an overhanging shape in which both ends of the upper part 62 protrude beyond the side surfaces of the lower part 61 (the side surfaces of the shaft layer 64). In the example of FIG. 7, the ends of the bottom layer 63 of the partition walls 6A and 6B also protrude beyond the side surfaces of the shaft layer 64 in the slit SL.

[0072] An end E11 of the sealing layer SE11 is located above the partition wall 6A. An end E12 of the sealing layer SE12 is located above the partition wall 6B. The sealing layer SE11 continuously covers the display element DE1 of the subpixel SP1 and part of the partition wall 6A. The sealing layer SE12 continuously covers the display element DE2 of the subpixel SP2 and part of the partition wall 6B.

[0073] For example, the rib layer 5 does not open at the slits SL. In this case, the slits SL entirely overlap the rib layer 5. For example, the slits SL are filled with the resin layer RS1. The resin layer RS1 covers the rib layer 5 at the slits SL.

[0074] The lower electrodes LE1, LE2, and LE3 do not overlap the slits SL, so that external light L incident on the slits SL is transmitted downward without being blocked by the partition walls 6 and the lower electrodes LE1, LE2, and LE3.

[0075] Next, an example of a manufacturing method of the display device DSP will be described. Fig. 8 is a flowchart showing an example of a manufacturing method of the display device DSP. Figs. 9A to 9J are schematic cross-sectional views showing the manufacturing process of the display device DSP. Figs. 9A to 9J mainly focus on the display area DA, and omit elements below the organic insulating layer 12.

[0076] In forming the display device DSP, first, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10 (step PR1 in FIG. 8). Next, as shown in FIG. 9A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR2 in FIG. 8).

[0077] Next, as shown in Fig. 9B, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed (step PR3 in Fig. 8). At this point, pixel openings AP1, AP2, and AP3 are not provided in the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0078] After the rib layer 5 is formed, a step for forming the partition walls 6 is performed (step PR4 in FIG. 8). In step PR4, as shown in FIG. 9C, a first layer L1 to be processed into the bottom layer 63, a second layer L2 to be processed into the shaft layer 64, a third layer L3 to be processed into the first top layer 65, and a fourth layer L4 to be processed into the second top layer 66 are formed in this order. Furthermore, a resist R1 is disposed on the fourth layer L4. The resist R1 is patterned into the shape of the partition walls 6. The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can be formed by, for example, sputtering.

[0079] Then, using the resist R1 as a mask, the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 are patterned. In one example, the first layer L1 is formed of titanium nitride, the second layer L2 is formed of aluminum, the third layer L3 is formed of titanium, and the fourth layer L4 is formed of ITO. In this case, the patterning may include wet etching to remove portions of the fourth layer L4 exposed by the resist R1, dry etching to remove portions of the first layer L1, the second layer L2, and the third layer L3 exposed by the resist R1, and wet etching to reduce the width of the second layer L2.

[0080] After step PR4, as shown in FIG. 9D, the partition walls 6 are formed in the display area DA. The slits SL described above are also formed by the patterning. After the partition walls 6 are formed, the resist R1 is removed (peeled off). In the wet etching that reduces the width of the second layer L2 described above, the second top layer 66 (fourth layer L4) may also be slightly eroded. If this erosion occurs, the width of the second top layer 66 will be smaller than the width of the first top layer 65.

[0081] Next, a step for providing pixel openings AP1, AP2, and AP3 is performed (step PR5 in FIG. 8). In this step PR5, a resist R2 is formed to cover the partition wall 6, as shown in FIG. 9E. Furthermore, using the resist R2 as a mask, dry etching is performed on the rib layer 5. As a result, pixel openings AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed in the rib layer 5, as shown in FIG. 9F. After the dry etching, the resist R2 is removed (peeled off).

[0082] After step PR5, a step for forming display element DE1 is performed (step PR6 in FIG. 8). To form display element DE1, first, as shown in FIG. 9G, a stacked film FL1 and a sealing layer SE11 are formed. As shown in FIG. 3, the stacked film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed by, for example, vapor deposition. The sealing layer SE11 can be formed by, for example, CVD.

[0083] The stacked film FL1 and the sealing layer SE11 are formed not only in the display area DA but also in the peripheral area SA. The stacked film FL1 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the stacked film FL1 and the partition walls 6.

[0084] Next, the stacked film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist R3 is disposed on the sealing layer SE11, as shown in FIG. 9G. The resist R3 covers the subpixel SP1 and part of the partition wall 6 around it.

[0085] Then, an etching process is performed using the resist R3 as a mask. As a result, as shown in FIG. 9H, the stacked film FL1 and the portions of the sealing layer SE11 that are exposed by the resist R3 are removed. This forms a display element DE1 in the subpixel SP1. The etching process includes wet etching and dry etching that are sequentially performed on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist R3 is removed (peeled off).

[0086] In addition, when wet etching the stacked film FL1, the stacked film FL1 located above the partition wall 6 and below the sealing layer SE11 is also removed. As a result, a gap is formed between the sealing layer SE11 above the partition wall 6 and the partition wall 6. The stacked film FL1 that constitutes the display element DE1 is completely surrounded by the sealing layer SE11 and the partition wall 6, and is therefore not eroded by the wet etching.

[0087] After step PR6, a step for forming display element DE2 is performed (step PR7 in FIG. 8). Display element DE2 can be formed using the same procedure as display element DE1. That is, when forming display element DE2, a stacked film FL2 and a sealing layer SE12 are formed over the entire display area DA and peripheral area SA. As shown in FIG. 3, stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2.

[0088] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed by, for example, vapor deposition. The sealing layer SE12 can be formed by, for example, CVD. The stacked film FL2 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE12 continuously covers each divided part of the stacked film FL2 and the partition walls 6. By patterning the stacked film FL2 and the sealing layer SE2, a display element DE2 is formed in the subpixel SP2, as shown in FIG. 9I.

[0089] After step PR7, a step for forming display element DE3 is performed (step PR8 in FIG. 8). Display element DE3 can be formed using the same procedure as display elements DE1 and DE2. That is, when forming display element DE3, a stacked film FL3 and a sealing layer SE13 are formed over the entire display area DA and peripheral area SA. As shown in FIG. 3, stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0090] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed by, for example, vapor deposition. The sealing layer SE13 can be formed by, for example, CVD. The stacked film FL3 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE13 continuously covers each divided part of the stacked film FL3 and the partition walls 6. By patterning the stacked film FL3 and the sealing layer SE13, a display element DE3 is formed in the subpixel SP3, as shown in FIG. 9J.

[0091] After step PR8, a resin layer RS1, a sealing layer SE2, and a resin layer RS2 are formed in this order (step PR9 in FIG. 8). The resin layers RS1 and RS2 can be formed by, for example, an inkjet method. The sealing layer SE2 can be formed by, for example, CVD.

[0092] Here, some effects achieved by the display device DSP according to this embodiment will be described. 10 and 11 are diagrams for explaining the effects of the display device DSP according to this embodiment. An electronic device incorporating the display device DSP may include an antenna AT1 for near-field communication (NFC). The antenna AT1 is disposed, for example, facing the rear surface of the display device DSP (the lower surface of the substrate 10 shown in FIG. 3), and wirelessly communicates with an antenna AT2 of another electronic device via the display device DSP.

[0093] During wireless communication between the antennas AT1 and AT2, the magnetic field M1 generated by the antenna AT1 generates an eddy current I in the common electrode CE. The eddy current I generates a magnetic field M2 that cancels out the magnetic field M1, thereby attenuating the signal strength. This can reduce communication sensitivity when wireless communication is performed via the display device DSP. In particular, when the lattice-shaped partition walls 6, primarily made of a metal material, are formed over the entire display area DA, the common electrode CE has low resistance. This generates a large eddy current I and the accompanying strong magnetic field M2, which can easily reduce communication sensitivity.

[0094] In contrast, in this embodiment, the common electrode CE is divided into multiple segments SG by slits SL. In this case, large eddy currents are less likely to occur in the common electrode CE, thereby suppressing a decrease in communication sensitivity. Although eddy currents may occur in each segment SG, the impact of these eddy currents on communication sensitivity is minor compared to the eddy current I that occurs throughout the entire undivided common electrode CE.

[0095] Furthermore, electronic devices incorporating a display device DSP may include an optical sensor such as an illuminance sensor that detects external light. When such an optical sensor is disposed on the rear side of the display device DSP, the display device DSP needs to be translucent.

[0096] However, each of the lower electrodes LE1, LE2, and LE3 includes the above-mentioned reflective layer. Furthermore, the partition wall 6, at least a part of which is made of a metal material, has a light-shielding property. Therefore, most of the light incident on the display surface of the display device DSP can be reflected or blocked without being transmitted to the rear surface.

[0097] In contrast, when the partition walls 6 are provided with slits SL as in this embodiment, part of the light incident on the display surface is transmitted to the rear surface side of the display device DSP through the slits SL, such as external light L shown in Fig. 6. This can improve the light transmittance of the display device DSP.

[0098] As described above, according to this embodiment, it is possible to provide a display device DSP that is compatible with antennas and optical sensors for wireless communication. Furthermore, as will be described below, according to this embodiment, it is possible to improve the yield of the display device DSP.

[0099] 12 is a schematic cross-sectional view of the display device DSP immediately after the display element DE1 is formed. The cross-section in this figure shows the same area as in FIG. 7, and includes the subpixel SP1, the partition walls 6A and 6B, and the slit SL.

[0100] 12, a large step having a complex shape is formed near the slit SL by the end E11 of the sealing layer SE11 and the partition wall 6A, which makes it easy for air bubbles to form in the slit SL during the manufacturing process of the display device DSP.

[0101] If step PR7 for forming display element DE2 is performed with air bubbles present, the air bubbles will burst during the reduced-pressure drying of the resist used to pattern stacked film FL2 and sealing layer SE12, exposing areas that should be covered by the resist. The same thing can happen in step PR8, which is performed thereafter.

[0102] Fig. 13 is a schematic plan view of a partition wall 6 according to a comparative example of the present embodiment. In this figure, as in Fig. 5, attention is focused on the vicinity of the first end Ea of each segment SG. In this comparative example, each slit SL does not reach the outer peripheral portion OP.

[0103] The above-mentioned phenomenon of resist popping is likely to occur near the first end Ea, for example, at position Q indicated by the chain circle in Fig. 13. Therefore, if the distance between the first end Ea and the display area DA is short, in other words, if the end of the slit SL is close to the display area DA, problems caused by resist popping may extend to the display area DA.

[0104] In contrast, in this embodiment, as shown in Figure 5, the slits SL reach the outer peripheral portion OP. In this case, a sufficient distance can be secured between the first end Ea of each segment (the end of each slit SL) and the display area DA. Therefore, even if the resist bursts near the end of the slit SL, the effect is less likely to extend to the display area DA, resulting in improved yield of the display device DSP. As described above, if the length Ls of the slit SL in the outer peripheral portion OP is equal to or greater than the width Wy of the pixel PX, this effect can be further enhanced.

[0105] In this embodiment, the slit SL is widened at the outer periphery OP, which reduces the likelihood of bubbles forming near the ends of the slit SL, which can cause the resist to burst. In addition to the above, various other advantageous effects can be obtained from this embodiment.

[0106] [Second embodiment] A second embodiment will now be described. In this embodiment, the same configuration as in the first embodiment can be applied to configurations that are not specifically mentioned.

[0107] 14 is a schematic plan view showing the configuration according to the second embodiment, in which the focus is on the vicinity of the first end Ea of each segment SG, as in FIG.

[0108] In the example of Fig. 14, the ends of each slit SL are located closer to the outer edge Eop of the outer peripheral portion OP than in the example of Fig. 5. This also increases the length Ls of the slit SL in the outer peripheral portion OP. For example, the length Ls is at least twice the width Wy of the pixel PX in the Y direction (Ls ≥ 2 × Wy).

[0109] As in the first embodiment, the slit SL has a wide portion Ps1. Furthermore, the slit SL has a narrow portion Ps2 in the outer peripheral portion OP. The narrow portion Ps2 is located between the wide portion Ps1 and the dummy pixel region DM.

[0110] The narrow portion Ps2 has a width Ws3 that is smaller than the width Ws2 of the wide portion Ps1 (Ws2>Ws3). As an example, the width Ws3 is equal to the width Ws1. As another example, the width Ws3 may be greater than the width Ws1 and less than the width Ws2. The lengths of the wide portion Ps1 and the narrow portion Ps2 in the Y direction are not particularly limited, but in one example, they are equal.

[0111] By increasing the length Ls of the slit SL in the outer peripheral portion OP as in this embodiment, the position where the above-mentioned resist bursting phenomenon can occur can be further away from the display area DA.

[0112] [Third embodiment] A third embodiment will now be described. Configurations that are not specifically mentioned in this embodiment can be similar to those in the above-described embodiments.

[0113] Fig. 15 is a schematic plan view showing a configuration according to the third embodiment. In this figure, as in Fig. 5, attention is focused on the vicinity of the first end Ea of each segment SG. As in the example of Fig. 14, the slit SL has a wide portion Ps1 and a narrow portion Ps2.

[0114] 15, the slit SL (widened portion Ps1) reaches the outer edge Eop of the outer peripheral portion OP. Each segment SG is connected to the power supply line PW shown in FIG. 4 via a contact portion CT.

[0115] If the slit SL reaches the outer edge Eop as in this embodiment, even if the above-mentioned bubbles are generated, the bubbles can easily escape from the opening of the slit SL at the outer edge Eop, thereby more effectively suppressing the phenomenon of the resist bursting.

[0116] [Fourth embodiment] A fourth embodiment will now be described. Configurations that are not specifically mentioned in this embodiment can be the same as those in the above-described embodiments.

[0117] Fig. 16 is a schematic plan view showing a configuration according to the fourth embodiment. As with Fig. 5, this figure focuses on the vicinity of the first end Ea of each segment SG. In the example of Fig. 16, the partition wall 6 includes multiple connection portions CN that connect adjacent segments SG across the slits SL. The rest of the configuration is the same as the example of Fig. 5, but similar connection portions CN can also be provided in the configurations of Figs. 14 and 15.

[0118] For example, the connection portion CN is disposed at a position adjacent to the subpixel SP3 or the dummy subpixel DP3 in the X direction. By providing such a connection portion CN, the resistance of the partition wall 6 can be reduced.

[0119] If connecting portions CN are provided in all of the slits SL, the effect of suppressing the eddy current described above will be reduced. Therefore, it is preferable that there be a slit SL that does not have a connecting portion CN, such as the slit SL at the right end in FIG.

[0120] [Fifth embodiment] A fifth embodiment will be described. Configurations that are not specifically mentioned in this embodiment can be the same as those in the above-described embodiments.

[0121] Fig. 17 is a schematic plan view showing a configuration according to the fifth embodiment. In this figure, the partition wall 6, sealing layers SE11, SE12, SE13, and slits SL are shown, as in Fig. 6. The sealing layer SE11 is indicated by a diagonal line pattern.

[0122] 17, the sealing layer SE11 not only covers the subpixel SP1 but also overlaps with the slit SL. Specifically, the sealing layer SE11 has a rectangular shape that is elongated in the X direction and crosses the slit SL in a plan view. A similar configuration can be applied to the sealing layer SE11 of the dummy subpixel DP1. Note that some of the sealing layers SE11 arranged in the display region DA and the dummy pixel region DM do not need to overlap with the slit SL.

[0123] Fig. 18 is a schematic cross-sectional view of the display device DSP taken along line XVIII-XVIII in Fig. 17. In this figure, elements below the organic insulating layer 12 and elements above the resin layer RS1 are omitted.

[0124] 18, the sealing layer SE11 continuously covers the display element DE1, the partition wall 6A, and the slit SL of the subpixel SP1. Furthermore, part of the sealing layer SE11 is located inside the slit SL. In other words, the sealing layer SE11 fills at least part of the slit SL.

[0125] An end E11 of the sealing layer SE11 is located above the partition wall 6B. An end E12 of the sealing layer SE12 of the subpixel SP2 is also located above the partition wall 6B. These ends E11 and E12 are spaced apart in the X direction.

[0126] 18, a gap GP1 is formed below the sealing layer SE11 covering the slit SL. The gap GP1 corresponds to the gap between the upper surface of the rib layer 5 and the lower surface of the sealing layer SE11. Furthermore, a gap GP2 is formed above the partition wall 6A and below the sealing layer SE11. The gap GP2 corresponds to the gap between the upper portion 62 of the partition wall 6A and the lower surface of the sealing layer SE11. A stacked film FL1 may be present in part of these gaps GP1 and GP2.

[0127] The manufacturing method of the display device DSP according to this embodiment is the same as that described in the first embodiment. In step PR6 for forming the display element DE1, before wet etching the stacked film FL1, the stacked film FL1 is also formed in the areas corresponding to the gaps GP1 and GP2. In the wet etching, the stacked film FL1 in these areas is removed by the etching solution penetrating below the sealing layer SE11 from near the end of the sealing layer SE11. This forms the gaps GP1 and GP2.

[0128] In this embodiment, when the sealing layer SE11 covers the slit SL near the subpixel SP1, the steps near the slit SL and the complex shape due to the partition walls 6A and 6B are alleviated, making it difficult for air bubbles to occur in the slit SL. This makes it possible to suppress the bursting of the resist formed in steps PR7 and PR8 in the display region DA and the dummy pixel region DM.

[0129] If the stacked film FL1 is formed under the sealing layer SE11 in the slit SL, the upper electrode UE1 may cause electrical conduction between the partition walls 6A and 6B. In this case, the suppression of the eddy current described above is hindered. Furthermore, the stacked film FL1 may reduce the transmittance of the slit SL. In contrast, if the stacked film FL1 below the sealing layer SE11 is removed by etching the stacked film FL1 as described above, electrical conduction between adjacent segments SG through the slit SL can be prevented and the transmittance of the slit SL can be increased.

[0130] [Sixth embodiment] A sixth embodiment will now be described. Configurations that are not specifically mentioned in this embodiment can be similar to those in the above-described embodiments.

[0131] Fig. 19 is a schematic plan view showing a configuration according to the sixth embodiment. In this figure, the partition wall 6, sealing layers SE11, SE12, SE13, and slits SL are shown, as in Fig. 6. The sealing layer SE11 is indicated by a diagonal line pattern.

[0132] 19, the sealing layer SE11 includes a plurality of first portions P1 overlapping the subpixels SP1 and second portions P2 connecting the first portions P1. The second portions P2 overlap the slits SL and extend in the Y direction (the extension direction of the slits SL) between the sealing layers SE12 and SE13.

[0133] When the sealing layer SE11 has such a shape, the slit SL is entirely covered with the sealing layer SE11, which more effectively suppresses the generation of the air bubbles.

[0134] On the other hand, if the slit SL1 is entirely covered with the sealing layer SE11, the laminated film FL1 remains inside the slit SL1, and the upper electrode UE1 included in the laminated film FL1 may cause electrical conduction between the adjacent segments SG. Therefore, if all the slits SL in the display area DA have the same structure as the slit SL1 shown in FIG. 19, the effect of suppressing the eddy current described above may be reduced.

[0135] Therefore, it is preferable to have slits SL that are not entirely covered with the sealing layer SE11 as shown in Fig. 6, or slits SL that include portions that are not covered with the sealing layer SE11 as shown in Fig. 17. As an example, such slits SL and the slits SL shown in Fig. 19 may be arranged alternately in the X direction.

[0136] [Seventh embodiment] A seventh embodiment will now be described. Configurations that are not specifically mentioned in this embodiment can be similar to those in the above-described embodiments.

[0137] In the first embodiment, it is assumed that the display elements DE1, DE2, and DE3 are formed in this order. In the present embodiment, it is assumed that the display element DE2 is formed first, and then the display elements DE1 and DE3 are formed. In such a case, the above-mentioned phenomenon of resist bursting may occur during the formation of the display elements DE1 and DE3. Therefore, as exemplified below, it is preferable to fill at least a portion of the slit SL with a sealing layer SE12.

[0138] Fig. 20 is a schematic plan view showing a configuration according to the seventh embodiment. In this figure, the partition wall 6, sealing layers SE11, SE12, SE13, and slits SL are shown, as in Fig. 6. Furthermore, the sealing layer SE12 is marked with a diagonal line pattern.

[0139] 20 is a strip-shaped sealing layer SE12 that continuously covers the subpixels SP2 aligned in the Y direction. Furthermore, the sealing layer SE12 entirely covers the slits SL, which effectively prevents the generation of air bubbles.

[0140] In addition, in the slits SL that overlap the sealing layer SE12, a stacked film FL2 may be formed below the sealing layer SE12. In this case, the upper electrodes UE2 included in the stacked film FL2 may conduct electricity between adjacent segments SG. Therefore, if all the sealing layers SE12 in the display area DA have the shape shown in FIG. 20, the effect of suppressing the eddy current described above may be reduced.

[0141] Therefore, it is preferable that there are slits SL that are not entirely covered with the sealing layer SE11 as shown in Fig. 6. As an example, such slits SL and the slits SL shown in Fig. 20 may be arranged alternately in the X direction.

[0142] When the display element DE3 is formed first, the sealing layer SE13 may be disposed in the same manner as the sealing layer SE11 illustrated in Figures 17 and 19. This makes it possible to prevent the above-mentioned phenomenon of resist bursting, which may occur when the display elements DE1 and DE2 are formed.

[0143] All display devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0144] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of each of the above-described embodiments, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0145] Furthermore, with regard to other effects brought about by the aspects described in each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0146] DSP...display device, DA...display area, SA...peripheral area, DM...dummy pixel area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13...sealing layer, CE...common electrode, SL...slit, SG...segment, PW...power supply line, T...terminal portion, 1...pixel circuit, 5...rib layer, 6...partition wall, 61...lower part, 62...upper part.

Claims

1. a display area including a plurality of pixels; a plurality of display elements each disposed in the plurality of pixels and each including an organic layer that emits light in response to application of a voltage; a dummy pixel area including a plurality of dummy pixels and located outside the display area; a partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion, the partition wall surrounding each of the plurality of pixels and the plurality of dummy pixels; Equipped with the partition wall has a peripheral portion located outside the dummy pixel region, and is divided into a plurality of segments by slits that pass through the display region and the dummy pixel region and reach the peripheral portion; Display device.

2. a length of the slit in the outer peripheral portion is equal to or greater than a width of the pixel in an extension direction of the slit; The display device according to claim 1 .

3. a length of the slit in the outer peripheral portion is equal to or greater than twice the width of the pixel in the extension direction; The display device according to claim 2 .

4. The slit has a first width in the display area and a second width in at least a part of the outer circumferential portion, the second width being larger than the first width. The display device according to claim 1 .

5. The slit is a widened portion located at the outer periphery and having the second width; a narrow width portion located in the outer periphery between the wide width portion and the dummy pixel region, the narrow width portion having a third width smaller than the second width; Including, The display device according to claim 4 .

6. The third width is equal to the first width. The display device according to claim 5 .

7. The partition wall further includes a connecting portion that connects the plurality of segments across the slit. The display device according to claim 1 .

8. At least one end of the slit reaches the outer edge of the outer circumferential portion. The display device according to claim 1 .

9. Both ends of the slit reach the outer edge of the outer circumferential portion. The display device according to claim 8 .

10. a plurality of sealing layers formed of an inorganic insulating material and covering the plurality of display elements, respectively; At least one of the plurality of sealing layers overlaps with at least a portion of the slit in a plan view. The display device according to any one of claims 1 to 9.

11. At least one of the plurality of sealing layers crosses the slit in a plan view. The display device according to claim 10.

12. At least one of the plurality of sealing layers includes a portion that covers the slit and extends in the extension direction of the slit. The display device according to claim 10.

13. a display area including a plurality of pixels; a plurality of display elements each disposed in the plurality of pixels and each including an organic layer that emits light in response to application of a voltage; a partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion, the partition wall surrounding each of the plurality of pixels; Equipped with the partition wall has an outer periphery portion located outside the display area, and is divided into a plurality of segments by slits that pass through the display area and reach the outer periphery portion; The slit has a first width in the display area and a second width in at least a part of the outer circumferential portion, the second width being larger than the first width. Display device.

14. The slit is a widened portion located at the outer periphery and having the second width; a narrow portion located in the outer periphery between the wide portion and the display area, the narrow portion having a third width smaller than the second width; Including, The display device according to claim 13.

15. The third width is equal to the first width. The display device according to claim 14.

16. a length of the slit in the outer peripheral portion is equal to or greater than a width of the pixel in an extension direction of the slit; The display device according to claim 13.

17. a length of the slit in the outer peripheral portion is equal to or greater than twice the width of the pixel in the extension direction; The display device according to claim 16.

18. The partition wall further includes a connecting portion that connects the plurality of segments across the slit. The display device according to claim 13.

19. At least one end of the slit reaches the outer edge of the outer circumferential portion.

19. A display device according to any one of claims 13 to 18.

20. Both ends of the slit reach the outer edge of the outer circumferential portion.

20. The display device according to claim 19.

Images