Junction structure body with integrated passive component

Abstract

To improve incorporation of a passive electronic component into an electronic system.SOLUTION: According to various embodiments, there is disclosed a junction structure. The junction structure may include an element and a passive electronic component which has a first surface joined to the element and a second surface on the opposite side from the first surface. The passive electronic component may comprise a first anode terminal joined to a corresponding second anode terminal of the element, and a first cathode terminal joined to a corresponding second cathode terminal of the element. The first anode terminal and first cathode terminal may be arranged on the first surface of the passive electronic component.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] This field relates to junction structures with integrated passive components.

[0002] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 62 / 440,161, filed December 29, 2016, and U.S. Provisional Patent Application No. 62 / 518,472, filed June 12, 2017, the entire contents of each of which are incorporated herein by reference in their entirety and for all purposes.

[0003] This application is also related to U.S. Patent Application No. 15 / 426,942, filed February 7, 2017, which is incorporated herein by reference in its entirety and for all purposes. [Background technology]

[0004] Passive electronic components, such as capacitors, resistors, and inductors, play an important role in electronic systems. For example, passive components contribute to signal smoothness and improve the performance of the system's active devices. Efficiently incorporating passive components can be difficult because they occupy valuable space on integrated device dies, packages, and / or system boards. Therefore, there remains a continuing need to improve the integration of passive electronic components into electronic systems. [Brief explanation of the drawings]

[0005] [Figure 1A] 1 is a schematic side view of a bonding structure mounted to a carrier, such as a package substrate, according to various embodiments. [Figure 1B] 1 is a schematic side view of an element and a passive electronic component before forming a bonding structure. [Figure 2] 1B is a schematic enlarged cross-sectional side view of a portion of the bonded structure shown in FIG. 1A. [Figure 3A]1 is a schematic cross-sectional side view of a portion of a passive electronic component configured for a relatively low speed connection. [Figure 3B] FIG. 3B is a schematic circuit diagram of the passive electronic components of FIG. 3A. [Figure 4A] 1 is a schematic cross-sectional side view of a portion of a passive electronic component configured for relatively high speed connection; [Figure 4B] FIG. 4B is a schematic circuit diagram of the passive electronic components of FIG. 4A. [Figure 5A] 1 is a schematic cross-sectional side view of a passive electronic component incorporating a high-K dielectric material defining a capacitive sheet. [Figure 5B] 5B is a schematic cross-sectional side view of the passive electronic component of FIG. 5A with a bonding layer provided over the patterned electrodes. [Figure 5C] 1 is a schematic cross-sectional side view of a portion of a semiconductor element prior to bonding. [Figure 5D] 1 is a schematic cross-sectional side view of a bonded structure in which a semiconductor element is directly bonded to a passive component comprising a high-K dielectric material. [Figure 5E] FIG. 5E is a schematic cross-sectional side view of the bonded structure of FIG. 5D after removal of the sacrificial base. [Figure 5F] 1 is a schematic cross-sectional side view of a passive electronic component having integrated power and ground electrodes; [Figure 5G] FIG. 5F is a plan view of the passive electronic component of FIG. 5F. [Figure 5H] 1 is a schematic cross-sectional side view of a passive electronic component according to another embodiment. [Figure 5I] FIG. 5C is a plan view of the passive electronic component of FIG. 5H. [Figure 6] 1 is a plot of transfer impedance as a function of frequency for various devices having different passive electronic components. [Figure 7A] 2 is a schematic cross-sectional side view of a passive electronic component according to another embodiment. [Figure 7B] 1 is a schematic cross-sectional side view of a passive electronic component according to yet another embodiment. [Figure 7C] 2 is a schematic cross-sectional side view of a passive electronic component according to another embodiment. [Figure 7D]1 is a schematic cross-sectional side view of a passive electronic component in which a capacitor can be defined by aligned fibers. [Figure 8A] 2 is a schematic cross-sectional side view of a first insulating layer, a plurality of capacitors, and a second insulating layer prior to the formation of passive electronic components. [Figure 8B] FIG. 1 is a schematic cross-sectional side view of a first insulating layer, a plurality of capacitors, a second insulating layer, and an intermediate third insulating layer disposed between the first insulating layer and the second insulating layer prior to forming passive electronic components. [Figure 8C] 1 is a schematic cross-sectional side view of a capacitor embedded in an insulating layer prior to the formation of passive electronic components; [Figure 8D] 8A-8C are schematic cross-sectional views of passive electronic components formed using any of the techniques shown in FIGS. 8A-8C. [Figure 8E] 8E is a schematic cross-sectional side view of the passive electronic component shown in FIG. 8D with one or more redistribution layers (RDLs) applied to the passive electronic component. [Figure 9A] 1A-1C are schematic cross-sectional side views of insulating layers used to form passive electronic components, according to various embodiments. [Figure 9B] 9B is a schematic cross-sectional side view of the insulating layer of FIG. 9A having one or more cavities formed therein. [Figure 9C] 1 is a schematic cross-sectional side view of one or more capacitors disposed within a cavity. [Figure 9D] FIG. 9D is a schematic cross-sectional side view of the device of FIG. 9C after providing a first RDL on the insulating layer. [Figure 9E] FIG. 10 is a schematic cross-sectional side view of the passive electronic component after providing a second RDL on the opposite side of the insulating layer. [Figure 10A] 1 is a schematic cross-sectional side view of a first insulating carrier used to form passive electronic components according to another embodiment. [Figure 10B] 1 is a schematic cross-sectional side view of a first insulating carrier having a first adhesive material deposited thereon. [Figure 10C] 1 is a schematic cross-sectional side view of a first insulating carrier having a plurality of capacitors bonded to the first insulating carrier by a first adhesive; [Figure 10D] 1 is a schematic cross-sectional side view of a partially defined component having a second insulating carrier layer adhered to a first adhesive layer by a second adhesive layer. [Figure 10E] 1 is a schematic cross-sectional side view of a passive electronic component having various interconnects and traces defined therein for electrical communication with external elements. [Figure 10F] 1 is a schematic cross-sectional side view of a partially fabricated passive electronic component comprising a capacitor embedded within an insulating layer comprising a plurality of adhesives and molding compounds. [Figure 10G] 1 is a schematic cross-sectional side view of a passive electronic component, according to various embodiments. [Figure 11A] 1 is a schematic cross-sectional side view of a first insulating carrier used to form passive electronic components according to another embodiment. [Figure 11B] 1 is a schematic cross-sectional side view of a first insulating carrier having a first adhesive material deposited thereon. [Figure 11C] 1 is a schematic cross-sectional side view of a first insulating carrier having a plurality of capacitors and a third insulating carrier joined to the first insulating carrier by a first adhesive; [Figure 11D] 1 is a schematic cross-sectional side view of a partially defined component having a second insulating carrier layer adhered to a first adhesive layer and a third carrier by a second adhesive layer. [Figure 11E] 1 is a schematic cross-sectional side view of a passive electronic component having various interconnects and traces defined therein for electrical communication with external elements. [Figure 11F] 1 is a schematic cross-sectional side view of a partially fabricated passive electronic component comprising a capacitor embedded within an insulating layer comprising a plurality of adhesives and molding compounds. [Figure 11G] 1 is a schematic cross-sectional side view of a passive electronic component, according to various embodiments. [Figure 11H] 1 is a schematic cross-sectional side view of a passive electronic component having an additional insulating carrier layer. [Figure 11I] 1 is a schematic cross-sectional side view of a passive electronic component having an additional insulating carrier layer and molding compound over the passive component. [Figure 12A] 1 is a schematic cross-sectional side view of a first insulating carrier having a plurality of contact pads thereon and used to form passive electronic components, according to another embodiment; [Figure 12B] 1 is a schematic cross-sectional side view of a first insulating carrier having a first adhesive material comprising solder electrically and mechanically connecting a capacitor to the first insulating carrier. [Figure 12C] 1 is a schematic cross-sectional side view of a first insulating carrier having a plurality of capacitors and a molding compound disposed around the capacitors. [Figure 12D] 1 is a schematic cross-sectional side view of a partially defined component having a second insulating carrier layer adhered to the first adhesive layer and molding compound by a second adhesive layer. [Figure 12E] 1 is a schematic cross-sectional side view of a passive electronic component having various interconnects and traces defined therein for electrical communication with external elements. [Figure 13A] 1 is a schematic cross-sectional side view of a first insulating carrier having a plurality of contact pads thereon and used to form passive electronic components, according to another embodiment; [Figure 13B] 1 is a schematic cross-sectional side view of a first insulating carrier having a first adhesive material comprising solder electrically and mechanically connecting a capacitor to the first insulating carrier. [Figure 13C] 1 is a schematic cross-sectional side view of a first insulating carrier with the insulating carrier bonded to the first insulating carrier and disposed around a capacitor; [Figure 13D] 13D is a schematic cross-sectional side view of the partially defined component of FIG. 13C with molding compound applied around the capacitor. [Figure 13E] 1 is a schematic cross-sectional side view of a partially defined component with a second insulating carrier disposed over a capacitor. [Figure 13F] 1 is a schematic cross-sectional side view of a passive electronic component having various interconnects and traces defined therein for electrical communication with external elements. [Figure 14A]1 is a schematic cross-sectional side view of a carrier having a plurality of capacitors mounted thereon by an adhesive layer. [Figure 14B] 1A-1D are schematic cross-sectional side views of passive electronic components according to various embodiments. [Figure 15] 1 is a flowchart illustrating a method of forming a bonded structure, according to various embodiments. [Figure 16] FIG. 1 is a schematic system diagram of an electronic system incorporating one or more junction structures, according to various embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0006] Various embodiments disclosed herein relate to bonded structures comprising a semiconductor element and a passive electronic component bonded directly to the semiconductor element without the use of an intervening adhesive. In various embodiments, the passive electronic component comprises a capacitor. In other embodiments, the passive electronic component can comprise other devices, such as an inductor, a resistor, a voltage regulator, a filter, and / or a resonator. Beneficially, the passive electronic component can be incorporated into a passive component layer that is bonded directly to the semiconductor element (e.g., an integrated device die). In illustrated embodiments, for example, the passive component layer can be disposed between the semiconductor element and another system component, such as an interposer or a system board. This can reduce the space occupied by the passive components in an integrated device, package, and / or system board. Furthermore, positioning the passive electronic component closer to the active components of the semiconductor element can beneficially reduce the overall inductance, thereby improving the bandwidth and signal integrity of the semiconductor element compared to passive devices mounted on a package substrate or system board. Additionally, the total capacitance provided by the disclosed embodiments allows for significantly increased capacitance (and reduced inductance) compared to discrete passives mounted on a die.

[0007] In various embodiments, the passive components can comprise layered capacitor structures having large capacitance. In some embodiments, for example, layered capacitors can be used to fabricate high-dielectric-constant (high-K) wafers or sheets. Wafer-to-wafer bonding layers can be provided on a first element, such as a first semiconductor element or wafer (e.g., a processor wafer including multiple processors), and on a second element, such as a second semiconductor element or wafer (e.g., a capacitor wafer defining one or more capacitors). The first and second elements disclosed herein can comprise semiconductor elements formed from semiconductor materials or other non-semiconductor elements, such as various types of optical devices (e.g., lenses, filters, waveguides, etc.). In various embodiments, additional direct bonding layers can be added and prepared for direct bonding to both the capacitor wafer and the processor wafer. The layered capacitor structures disclosed herein can be used as alternating current (AC) coupling capacitors connected in series with a signal path to filter out the direct current (DC) component of the signal for balanced high-speed signal transmission. The layered capacitor structure may also be used as a decoupling capacitor with high capacitance and very low parasitic inductance and resistance to reduce system power delivery network (PDN) impedance. Results show that the capacitor structure enables full frequency range operation with over 1000x reduced PDN impedance compared to the use of discrete capacitors mounted on the die or package substrate.

[0008] Direct bonding between a semiconductor element and a passive component can include, but is not limited to, direct bonding between a corresponding conductive feature of a semiconductor element (e.g., a processor die or wafer) and a passive component (e.g., a bond pad of the semiconductor element and a corresponding contact pad of the passive component) without the use of an intervening adhesive. In some embodiments, the conductive feature may be surrounded by a non-conductive field region. To achieve direct bonding, in some embodiments, the respective bonding surfaces of the conductive feature and the non-conductive field region can be prepared for bonding. Preparation can include providing a non-conductive layer, such as silicon oxide, with exposed conductive features, such as metal bond pads or contacts. The bonding surfaces of the conductive feature and the non-conductive field region can be polished to a very high smoothness (e.g., a surface roughness of less than 20 nm or, more specifically, a surface roughness of less than 5 nm). In some embodiments, the surfaces to be bonded can be terminated with a suitable species and activated before bonding. For example, in some embodiments, the non-conductive surface (e.g., the field region) of the bonding layer to be bonded, such as a silicon oxide material, can be very slightly etched for activation, exposed to a nitrogen-containing solution, and terminated with a nitrogen-containing species. As an example, the surfaces to be bonded (e.g., field regions) may be exposed to a very slight post-etch ammonia dip and / or a nitrogen-containing plasma (with or without a separate etch). In a direct bond interconnect (DBI) process, non-conductive features of the die and passive component layer can be directly bonded to each other without the application of external pressure, even at room temperature, while conductive features of the die and passive component layer can also be directly bonded to each other without any intervening adhesive layer. DBI bonds form bonds stronger than van der Waals bonds, involving significant covalent bonding between the target surfaces.

[0009] In some embodiments, each conductive feature can be flush with the outer surfaces (e.g., field regions) of the semiconductor elements and passive components. In other embodiments, the conductive features may extend above the outer surfaces. In still other embodiments, the conductive features of one or both of the semiconductor elements and passive component layers are recessed relative to the outer surfaces (e.g., non-conductive field regions) of the semiconductor elements and passive components. For example, the conductive features can be recessed relative to the field regions by less than 20 nm, e.g., less than 10 nm.

[0010] Upon preparation of the respective surfaces, the non-conductive field regions (e.g., silicon oxide) of the semiconductor element can be brought into contact with the corresponding non-conductive regions of the passive component. The activated surface interaction allows the non-conductive regions of the semiconductor element to be directly bonded to the corresponding non-conductive regions of the passive component without the use of an intervening adhesive, without the application of external pressure, without the application of voltage, and at room temperature. In various embodiments, the bond strength of the non-conductive regions can include covalent bonds that are larger than van der Waals bonds and can exert significant forces between the conductive features. Prior to any heat treatment, the dielectric-dielectric surface bond energy is between 150 and 300 mJ / m. 2 , which can be in the range of 1500-4000 mJ / m after a period of heat treatment. 2The thickness of the conductive features can be increased to 1000 Å. Whether the conductive features are flush with or recessed from the non-conductive regions, direct bonding of the non-conductive regions can facilitate direct metal-metal bonding between the conductive features. In various embodiments, the semiconductor element and passive component may be heated after bonding at least the non-conductive regions. As discussed above, such heat treatment can strengthen the bond between the non-conductive features, between the conductive features, and / or between opposing conductive and non-conductive regions. In embodiments in which one or both of the conductive features are recessed, an initial gap may exist between the conductive features of the semiconductor element and the passive component layer, and heating after initially bonding the non-conductive regions can expand the conductive elements to close the gap. Whether an initial gap existed or not, heating can create or increase pressure between some opposing conductive elements, assisting in bonding the conductive features and forming a direct electrical and mechanical connection.

[0011] In some embodiments, capacitance can be improved by providing a capacitor with electrode surfaces disposed along a direction generally non-parallel (e.g., generally perpendicular) to the major lateral surfaces of the element (e.g., semiconductor element). Relief providing an increased surface can be relatively simple to pattern compared to the multiple layers and masks required to fabricate laterally extending fins. The capacitor can include first and second electrodes having major surfaces extending along the non-parallel direction and separated by an intervening dielectric. The vertically disposed relieving features (e.g., trenches) of the capacitor can have a high aspect ratio; for example, the first height of the first electrode along the non-parallel direction can be longer than the width of the capacitor along the major lateral surface. The aspect ratio can be defined by dividing the first height by the width and can be greater than 5:1. In such embodiments, providing the capacitor primarily vertically relative to the semiconductor element can beneficially increase the total surface area of ​​the electrodes, improving capacitance compared to other configurations.

[0012] Further details of the direct bonding process used in conjunction with each of the disclosed embodiments can be found throughout U.S. Pat. Nos. 7,126,212, 8,153,505, 7,622,324, 7,602,070, 8,163,373, 8,389,378, and 8,735,219, as well as U.S. patent application Ser. Nos. 14 / 835,379, 62 / 278,354, 62 / 303,930, and 15 / 137,930, the contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0013] FIG. 1A is a schematic side view of a bonding structure 1 mounted to a carrier, such as a package substrate 5, according to various embodiments. While the illustrated carrier comprises a package substrate, in other embodiments, the carrier may comprise an integrated device die or any other suitable element. The package substrate 5 may comprise any suitable substrate configured to be mounted to a system motherboard. For example, in various embodiments, the package substrate 5 may comprise a printed circuit board (PCB), an interposer, a leadframe, a ceramic substrate, a polymer substrate, or any other suitable carrier. As shown in FIG. 1A, the package substrate 5 may comprise a plurality of solder balls 6 that provide electrical connection to a system motherboard (not shown). In other embodiments, the package substrate 5 may be electrically connected to the system motherboard in other ways.

[0014] In FIG. 1A , bonding structure 1 includes an element (e.g., a semiconductor element 2) and a passive electronic component 3 directly electrically and mechanically connected to element 2. While element 2 illustrated in FIG. 1A includes a semiconductor element such as a processor die, other types of integrated device dies or semiconductor elements can be used. For example, in other embodiments, element 2 can include a memory die, a microelectromechanical system (MEMS) die, an optical device or die, an interposer, a reconfiguration die or wafer, or any other suitable device or element. In various embodiments, element 2 illustrated herein can instead include a non-semiconductor element such that passive electronic component 3 can be mechanically and electrically connected to other types of elements, such as optical elements (e.g., optical lenses, waveguides, filters, etc.), which may or may not include semiconductor materials.

[0015] As described herein, in various applications (e.g., high-speed communications or power dies), it can be important to provide passive electronic components (e.g., capacitors) near the active circuitry of the semiconductor element 2 to reduce overall impedance and / or inductance, thereby improving signal integrity and reducing switching noise. Thus, as shown in FIG. 1A , the passive electronic components 3 can be bonded to the active surface 11 of the semiconductor element 2, i.e., the active electronic circuitry can be defined on or near the active surface 11 of the semiconductor element 2. In the illustrated embodiment, the passive electronic components 3 are bonded directly to the active surface 11 of the semiconductor element 2 without the use of an intervening adhesive. However, in other embodiments, the passive electronic components 3 can be attached to the semiconductor element 2, for example, by reflow, a microbump array with conductive pillars, or by thermocompression bonding. Beneficially, bonding the passive electronic components 3 to the front or active surface 11 of the semiconductor element 2 can reduce the length of the signal lines and the overall impedance and / or inductance compared to systems that mount passive devices on a system board or package substrate. Passive components 3 can reduce the voltage requirements of semiconductor element 2 by quieting noise components in passive components 3. Furthermore, bonding passive electronic components 3 to semiconductor element 2 can reduce the overall size of the package since the passives occupy a thin layer bonded to semiconductor element 2. However, those skilled in the art will understand direct bonding of passive electronic components between the carrier and the semiconductor element, for example by through silicon vias (TSVs) on the backside of the semiconductor element.

[0016] As shown in FIG. 1A , the passive electronic component 3 may include a first surface 12 directly bonded to the semiconductor element 2 and a second outer surface 13 opposite the first surface 12 of the passive electronic component 3. A plurality of electrical contacts 4 (e.g., solder balls) may be provided on the second outer surface 13 of the passive electronic component 3. The plurality of electrical contacts 4 may be configured to electrically connect to an external semiconductor element, such as a package substrate 5 (e.g., a printed circuit board, an interposer, etc.) shown in FIG. 1A . Alternatively, the second surface 13 may have exposed contacts or pads configured for direct bonding connection to another element that serves as a carrier for the bonding structure, such as another semiconductor element (e.g., a die or an interposer).

[0017] As shown in FIG. 1A , the passive electronic component 3 can cover (e.g., be disposed on) a majority of the active surface 11 of the semiconductor element 2, e.g., a majority of the surface of the semiconductor element 2 used for processing or other active tasks. For example, in various embodiments, the passive electronic component 3 can cover at least 55%, at least 65%, at least 75%, at least 85%, at least 95%, at least 99%, or at least 100% of the active surface 11 of the semiconductor element 2. While FIG. 1A shows a single, integrated passive component 3 as covering substantially the entire active surface 11 of the semiconductor element 2, in other embodiments, the passive component 3 can comprise multiple discrete or separate passive components bonded to cover a majority of the active surface 11 of the element 2. Additionally, in other embodiments, the passive electronic component 3 can be mechanically and electrically connected to the backside of the semiconductor element 2, i.e., the surface opposite the active surface 11. In such a configuration, even if the passive components 3 are mounted on the backside of the element 2, the lengths of the conductors within the element 2 may be short enough to sufficiently reduce impedance for routing to separate surface-mounted passives on the packaging substrate. Furthermore, as shown in FIG. 1A , the passive electronic components 3 may comprise a sheet bonded (e.g., directly bonded without the use of an intervening adhesive) to the semiconductor element 2, i.e., the passive electronic components 3 may be dimensioned to have a lateral width significantly greater than the thickness of the passive electronic components 3. For example, the passive electronic components 3 may have a lateral width (e.g., as defined along a direction parallel to the active surface 11 of the element 2) that is at least 3 times, at least 5 times, at least 10 times, or at least 50 times the thickness of the component 3 (e.g., as defined along a direction perpendicular to the active surface 11 of the element 2).

[0018] The passive electronic components 3 can be provided on a sacrificial wafer (e.g., silicon or glass), and the semiconductor elements 2 can also be provided on the wafer. The two wafers can be directly bonded to each other at the wafer level (e.g., wafer-to-wafer or wafer-to-wafer) so that multiple passive components 3 can be bonded to corresponding multiple semiconductor elements 2, thereby improving manufacturing throughput. After bonding, the wafer substrate can be thinned or removed before or after dicing. In other embodiments, the passive electronic components 3 can be picked and placed on the semiconductor elements 2, or can be bonded to the semiconductor elements 2 using other processing techniques.

[0019] FIG. 1B is a schematic side view of a semiconductor element 2 including a bulk material portion 37 (e.g., bulk semiconductor material) and an active surface 11, and a passive electronic component 3 prior to forming a bonding structure 1. Unless otherwise noted, features in FIG. 1B may be the same as or generally similar to like-numbered features in FIG. 1A. As explained above, the passive component 3 and the semiconductor element 2 may include respective bonding layers 8a, 8b (see also FIG. 2). In the illustrated embodiment, the bonding layer 8a of the passive electronic component 3 may include one or more conductive features 9a, 9a', such as metal, surrounded by a non-conductive field region (see FIG. 2). Similarly, the bonding layer 8b may include one or more conductive features 9b, 9b', such as metal, surrounded by a non-conductive field region (see FIG. 2), such as silicon oxide. The conductive features 9a, 9a', 9b, 9b' may act as electrical interconnects to provide electrical continuity between the semiconductor element 2 and the passive component 3. The conductive features 9a, 9a', 9b, 9b' may comprise any suitable metal or conductor, such as copper. As explained above, the conductive features 9a, 9a', 9b, 9b' may be recessed downward, protrude above, or be flush with the outer surface of the non-conductive field region.

[0020] 1B , the conductive feature 9a can comprise a first terminal (e.g., an anode of a capacitive device), and the other conductive feature 9a′ can comprise a second terminal (e.g., a cathode of a capacitive device) of a different type than the first terminal. Similarly, the conductive feature 9b can comprise a first terminal (e.g., an anode) of the element 2, and the other conductive feature 9a′ can comprise a second terminal (e.g., a cathode) of the element 2 of a different type than the first terminal. Beneficially, various embodiments disclosed herein can include both an anode and a cathode (e.g., conductive features 9a, 9a′) on the same first surface 12 of the passive electronic component 3. Thus, each anode terminal 9b of the semiconductor element 2 can be bonded to and electrically connected to a corresponding respective anode terminal 9a of the passive electronic component 3 disposed on the first surface 12. The respective cathode terminals 9 b ′ of the semiconductor elements 2 can be bonded and electrically connected to corresponding respective cathode terminals 9 a ′ of the passive electronic components 3 disposed on the first surface 12 .

[0021] Advantageously, providing the anode terminal 9a and the cathode terminal 9a' on the same first surface 12 of the passive electronic component 3 can enable wafer-level bonding of two structures (e.g., bonding the semiconductor element 2 and the passive component 3) along the same side of the passive component 3. Thus, in the embodiments disclosed herein, each opposing side of the passive component 3 can include one or more anodes and one or more cathodes (e.g., different types of terminals). In various embodiments, one or both sides of the component 3 can include one or more dummy terminals. An element (such as the semiconductor element 2) can have contacts connected to (e.g., bonded to) corresponding anode and cathode terminals on one side (e.g., a first side) of the passive component. A second element (such as another semiconductor element, a package substrate, etc.) can have contacts connected to (e.g., bonded to) corresponding second anode and cathode terminals on the opposite side (e.g., a second side) of the passive component 3. 1B , for example, element 2 can be connected to corresponding first and second terminals of different types (e.g., anode and cathode terminals) on a first side of passive component 3. Another element (not shown), such as a package substrate, can be connected to corresponding first and second terminals of different types (e.g., anode and cathode terminals) on an opposite second side of passive component 3, for example, by interconnects 4 (which may comprise solder balls).

[0022] In various embodiments, the anode terminals 9a, 9b are directly bonded to each other without an intervening adhesive. Similarly, the cathode terminals 9a', 9b' can also be directly bonded to each other without an intervening adhesive. In various embodiments, the anode terminals 9a, 9b and the cathode terminals 9a', 9b' can be connected by thermocompression bonding. In other embodiments, the anode terminals 9a, 9b and the cathode terminals 9a', 9b' can be connected by other methods, such as by conductive adhesives such as solder or anisotropic conductive films. Furthermore, as shown in FIG. 1B, various portions of the passive component 3 can have different types of interconnects and / or passive components. For example, one portion of the passive electronic component 3 can include a multilayer capacitive portion similar to the portion illustrated in FIG. 2, and another portion of the passive electronic component 3 can include a series capacitive interconnect similar to that shown in FIG. 4A. Still other portions of the passive electronic component can be provided with low-resistance electrical paths (e.g., feed-through interconnects) as shown in FIG. 3A. Additionally, passive electronic components such as those shown in Figures 7A-7C may also include an anode terminal 9a and a cathode terminal 9a' on the same side of the component.

[0023] FIG. 2 is a schematic, enlarged, cross-sectional side view of the semiconductor element 2 and the passive electronic component 3 shown in FIGS. 1A-1B immediately prior to direct bonding. As discussed above, the passive component 3 can include a bonding layer 8a, and the semiconductor element 2 can include a bonding layer 8b. In the illustrated embodiment, the bonding layer 8a can include one or more conductive features 9a, 9a', such as a metal, surrounded by a non-conductive field region 7a, such as a form of silicon oxide material. Similarly, the bonding layer 8b can include one or more conductive features 9b, 9b', such as a metal, surrounded by a non-conductive field region 7b, such as silicon oxide. The conductive features 9a, 9a', 9b, 9b' can act as electrical interconnects to provide electrical continuity between the semiconductor element 2 and the passive component 3. The conductive features 9a, 9a', 9b, 9b' can include any suitable metal or conductor, such as copper. As explained above, conductive features 9a, 9a', 9b, 9b' may be recessed downward, protrude above, or be flush with the outer surfaces of non-conductive field regions 7a, 7b. Non-conductive field regions 7a, 7b may comprise any suitable non-conductive material, such as silicon oxide, undoped or very lightly doped silicon, silicon nitride, or the like, that can be prepared for direct bonding.

[0024] As described above, the bonding layers 8a, 8b can be polished (e.g., by chemical mechanical polishing, or CMP) to a very low surface roughness (e.g., an RMS roughness of less than 20 nm, or more specifically, less than 5 nm). As described above, the bonding layers 8a, 8b (e.g., non-conductive field regions 7a, 7b) can be activated and terminated with a suitable species, such as nitrogen, by exposure to a nitrogen-containing plasma (e.g., by reactive ion etching) or by very light etching followed by exposure to a nitrogen-containing (e.g., ammonia) solution. The bonding layers 8a, 8b can be brought together at room temperature in some embodiments to form a direct bond between the field regions 7a, 7b. The semiconductor element 2 and the passive component 3 can be heated to strengthen the bond between the field regions 7a, 7b and / or to expand the conductive features 9a and 9b and 9a′ and 9b′ to form an electrical connection. Beneficially, the use of direct bonding can provide a low impedance and low inductance electrical path between the semiconductor element 2 and the passive component 3, which can improve power integrity or signal integrity.

[0025] 2 , the semiconductor element 2 may include internal conductive traces 14 and vias 15 for routing electrical signals within the semiconductor element 2 and / or between the semiconductor element 2 and the passive electronic component 3. The electrical signals may pass to and / or from the passive electronic component 3 through conductive features 9 a, 9 a′ and 9 b, 9 b′ (which may be directly bonded to one another, respectively). The conductive features 9 a, 9 a′ may define, act as, or connect to contact pads 21 on or near the first surface 12 of the passive electronic component 3. As shown in FIG. 2 , in various embodiments, the passive electronic component 3 may include multiple (e.g., two or more, or three or more) conductive layers 16 spaced apart by one or more dielectric or non-conductive layers 10. As shown in FIG. 2 , the bonding structure 1 can include conductive features 9 a, 9 a′, 9 b, and 9 b′ that define an interconnect structure 17, including contact pads 21 and electrical paths or interconnections 18 between the semiconductor element 2 and the electrical contacts 4 on the second surface 13 of the passive electronic component 3. In FIG. 2 , multiple conductive features 9 a, 9 a′, 9 b, and 9 b′ are shown on each of the bonding layers 8 a, 8 b, which can reduce dishing. However, in other embodiments, the contact pads 21 can be defined small enough to avoid the effects of dishing during processing. In such a configuration, each contact pad 21 can include one conductive feature.

[0026] While FIG. 2 illustrates three contact pads 21 and three interconnects 4, the number of contact pads 21 and interconnects 4 may vary in various embodiments. For example, in some embodiments, the pitch of the contact pads 21 on the semiconductor elements 2 and / or passive components 3 may be smaller than the pitch of the interconnects 4. In various implementations, the pitch of the interconnects 4 may be significantly larger than the pitch of the contact pads 21, e.g., the pitch of the interconnects 4 may be at least 10 times, at least 20 times, or at least 30 times the pitch of the contact pads 21. By way of example, the pitch of the interconnects 4 may be in a range of 100 microns to 300 microns, or in a range of 100 microns to 200 microns (e.g., approximately 150 microns). The pitch of the contact pads 21 may be in a range of 0.5 microns to 50 microns, or in a range of 0.5 microns to 20 microns, or in a range of 1 micron to 10 microns (e.g., approximately 5 microns).

[0027] In some embodiments, the first conductive interconnect 18a extends from the first surface 12 (or contact pad 21) to a corresponding electrical contact 4 on the second surface 13 of the passive electronic component 3. The second conductive interconnect 18b and the third conductive interconnect 18c can also extend from the contact pad 21 to a corresponding electrical contact 4 on the second surface 13. In FIG. 2 , for example, each of the conductive electrical interconnects 18a-18c can include a longitudinal conductive portion 19 that extends from the corresponding contact pad 21 at or near the first surface 12 to the corresponding electrical contact 4. As shown in FIG. 2 , the longitudinal portion 19 can extend vertically through the thickness of the passive electronic component 3 (e.g., across the active surface 11 of the semiconductor element 2). The conductive interconnects 18a-18c can include one or more lateral conductive portions 20 that extend laterally outward from the longitudinal conductive portion 19. The longitudinal conductive portions 19 can define a resistive electrical path, and one or more lateral conductive portions 20 can define a capacitive electrical path in parallel with the resistive electrical path. As shown in FIG. 2, one or more lateral conductive portions 20 of a first interconnect 18a can be interleaved with lateral portions 20 of a second interconnect 18b and can be separated by an intervening dielectric layer 10. Similarly, the lateral conductive portions 20 of the second interconnect 18b can be interleaved with lateral portions 20 of a third interconnect 18c and can be separated by an intervening dielectric layer 10. The interleaving of the lateral portions 20 of each interconnect 18a-18c can at least partially define a respective capacitive electrical path, such that each lateral portion 20 acts as an electrode of a capacitor, with the intervening dielectric layer 10 acting as the capacitor dielectric. In various embodiments, the dielectric layer 10 can comprise a high-K dielectric material layer, such as titanates (BaxSr1-xTiO3, Bi4Ti3O12, PbZrxTi1-xO3), niobates (LiNbO3), and / or zirconates (BaZrO3, CaZrO3, etc.). In other embodiments, the dielectric layer 10 can comprise any suitable dielectric material, such as silicon oxide, silicon nitride, etc. In some embodiments, the dielectric layer can have a dielectric constant in the range of 1 to 1000.In some embodiments, the dielectric layer can have a dielectric constant in the range of 1 to 10. As explained above in connection with FIG. 1B, in the illustrated embodiment, the anode and cathode terminals of passive component 3 may be disposed along the same side of component 3.

[0028] In various embodiments, the first interconnect structure 18a and the third interconnect structure 18c can be configured to connect to a power supply, and the second interconnect structure 18b can be configured to connect to electrical ground, or vice versa. The passive electronic component 3 of FIG. 2 can beneficially act as a multilayer decoupling capacitor connected in parallel between the power supply and ground to reduce power distribution network (PDN) impedance, thereby improving power integrity. Additionally, providing decoupling capacitors (e.g., capacitors defined by the interconnect structures 18a-18c) near the active surface 11 of the semiconductor element 2 (e.g., near switches on the fabricated die) can further improve the power integrity of the junction structure 1. Decoupling capacitance in the core region of the die (such as that provided by the disclosed embodiments) can provide a stable power supply to the computational engine within the electronic device. Increasing this decoupling capacitance increases the stability of the voltage swing, reducing the amount of additional margin applied to timing analysis to account for voltage instability. In contrast, adding decoupling capacitance to a parallel plate structure exhibits relatively small capacitance values. Deep trench capacitors can provide higher capacitance but can occupy valuable footprint that can add area and cost to electronic devices.

[0029] FIG. 3A is a schematic cross-sectional side view of a portion of a passive electronic component 3 configured for relatively low-speed connection. FIG. 3B is a schematic circuit diagram of the passive electronic component 3 of FIG. 3A. As shown in FIG. 3A, the passive component 3 can include an electrical path 18 having low resistance and low capacitance between a first surface 12 and a second surface 13 of the passive component 3. For example, in FIG. 3A, the path 18 can include a longitudinal conductive portion 19 that directly connects a contact pad 21 and an electrical contact 4. The longitudinal conductive portion 19 acts to short-circuit signals between the contact pad 21 and the contact 4. Additionally, as shown in FIG. 3A, lateral conductive portions 20 can be disposed offset from the longitudinal conductive portion 19. The lateral conductive portions 20 can be spaced apart from one another along the thickness of the passive component 3 and can be separated by an intervening dielectric layer 10. The electrical pathway 18 defined within the passive component 3 of Figures 3A-3B may be suitable for relatively low speed connections because the longitudinal conductive portion 19 shorts the connection between the contact pad 21 and the electrical contact 4.

[0030] FIG. 4A is a schematic cross-sectional side view of a portion of a passive electronic component 3 configured for high-speed serial link signaling. FIG. 4B is a schematic circuit diagram of the passive electronic component 3 of FIG. 4A. In a serial link, the passive electronic component 3 can act as a DC blocking capacitor, which can serve a variety of purposes. For example, the passive electronic component 3 can adjust the average DC bias level (e.g., filter out DC components), protect the transmitter / receiver from destructive overload events that may result from improper power-up sequencing, and / or function as part of a circuit that detects when a wire is disconnected. In these applications, the DC blocking capacitor does not distort the high-frequency components of a signal passing through it. In various embodiments, all high-frequency components of the signal, except for the DC component, can pass without any distortion. Therefore, a large capacitance value with low connection parasitic resistance and / or inductance can be provided. The embodiments of FIGS. 4A-4B can be useful for frequencies above 500 MHz, although in other embodiments, lower frequency ranges may be used in conjunction with the disclosed embodiments. As shown in Figure 4A, the passive electronic component 3 can include an electrical path including a multilayer capacitor disposed between a contact pad 21 and an electrical contact 4. Indeed, unlike the embodiment of Figure 3A, in Figure 4A the path 18 between the contact pad 21 and the contact 4 is a capacitive electrical path defined by multiple lateral conductive portions 20 spaced apart by intervening dielectric layers 10 spanning the thickness of the passive electronic component 3. The multiple layers shown in Figure 4A can function electrically as multiple capacitors connected electrically in series. The effective capacitance provided by the path 18 in Figure 4A is approximately 10 nF / mm 2 ~1μF / mm 2. Beneficially, in the illustrated embodiment, the capacitors defined along electrical path 18 can filter out DC components of the signal to provide a balanced high-speed signal (e.g., path 18 can act as a high-pass filter). Additionally, positioning passive components 3 closer to the active circuitry of semiconductor element 2 can further improve the performance of junction structure 1 and reduce reflected noise.

[0031] 5A-5I illustrate another embodiment in which a passive electronic component 3 is bonded (e.g., directly bonded) to a semiconductor element 2. As described above in connection with FIG. 1B, in FIGS. 5A-5I, the anode and cathode terminals of the passive electronic component 3 can be disposed along the same side or surface of the component 3. In various configurations, the passive component 3 can comprise a high dielectric constant (high-K) thin-film capacitor layer with integrated interconnects for direct bonding and integration with other components, such as a processor. For example, in the embodiment of FIGS. 5A-5I, the passive component 3 can comprise a dielectric material having a dielectric constant greater than 5, greater than 10, greater than 20, or greater than 100. Such high-K materials can be difficult to fabricate and may be unsuitable for exposure to other types of devices (e.g., processors or other semiconductor fabrication), making it difficult to integrate such materials into conventional semiconductor devices. Thus, in embodiments disclosed herein, the semiconductor elements 2 can be fabricated in one facility (e.g., a complementary metal oxide semiconductor or CMOS facility) and the passive components 3 can be fabricated in another facility that can accommodate the processing parameters of high-K materials. The semiconductor elements 2 and the passive components 3 can include a bonding layer and be directly bonded to connect the semiconductor elements 2 and the passive components 3. Thus, embodiments disclosed herein can enable the separate fabrication and subsequent integration of thin-film, high-K dielectric materials with any suitable type of semiconductor or optical element.

[0032] FIG. 5A is a schematic cross-sectional side view of a passive electronic component 3 incorporating a high-K dielectric material to define a capacitive sheet. The passive electronic component 3 can include a base 122 that can define the capacitive sheet. The base 122 can be sacrificial so that it can be removed before bonding the passive component 3 to the semiconductor element 2. In various embodiments, the base 122 can comprise a semiconductor material such as silicon. The first electrode 120 can be formed on the base 122 by any suitable method. For example, the first electrode 120 can be deposited on the base 122 using a metal organic chemical vapor deposition (MOCVD) process, a physical vapor deposition (PVD) or sputtering process, or a sol-gel process (spin-on and cure). The first electrode 120 can comprise a refractory metal such as platinum (Pt) or ruthenium (Ru). In the illustrated embodiment, the first electrode 120 may be deposited as a continuous or blanket film on the base 122 and may serve as a common electrode for multiple capacitors.

[0033] A high-K dielectric layer 110 can be deposited or otherwise formed on the first electrode 120. For example, in various embodiments, the dielectric layer 110 can be deposited using CVD, PVD, powder sintering, or other suitable techniques. Beneficially, the dielectric layer 110 can have a dielectric constant greater than 5, greater than 10, greater than 20, greater than 100, or greater than 200 (e.g., about 300), or greater than 1000. In various embodiments, for example, the dielectric layer can comprise ternary barium strontium oxide titanate (BaSrTiO3 or BST), other titanates (BaxSr1-xTiO3, Bi4Ti3O12, PbZrxTi1-xO3), niobates (LiNbO3), and / or zirconates (BaZrO3, CaZrO3, etc.) complex oxide high-K materials. Thus, unlike the embodiments of FIGS. 2-4B, only a single thin dielectric layer (rather than multiple alternating layers with conductors) may be used in conjunction with the passive components 3. In some embodiments, multiple layers of dielectric material may be provided to form the dielectric layer 110 .

[0034] A second electrode 121 can be deposited on the dielectric layer 110. The second electrode 121 can be any suitable conductive material, such as a refractory metal, and particularly a noble metal (e.g., Pt or Ru). The refractory or noble metal of one or both of the first electrode 120 and the second electrode 121 (e.g., Pt) can beneficially form a Schottky barrier (as opposed to an ohmic contact), thereby improving the performance of the capacitor. Thus, in the illustrated embodiment, the refractory or noble metal of the electrodes 120, 121 can remain in the final junction structure 1 to provide improved performance. In some embodiments, the noble or refractory metal of the first electrode 120 and / or the second electrode 121 can be plated with another metal (e.g., copper) to reduce resistance. However, in other embodiments, the first electrode 120 and / or the second electrode 121 may be removed after the passive component 3 is formed and replaced with another metal (e.g., copper) that serves as the first electrode 120 and the second electrode 121.

[0035] The second electrode 121 can be patterned to define multiple gaps 123 between portions of the second electrode 121. Patterning the electrode into multiple portions can define the total capacitance provided by the passive electronic component 3. For example, larger portions of the second electrode 121 can provide increased area and increased capacitance, while smaller portions of the second electrode 121 can provide reduced area and reduced capacitance. In various embodiments, the passive component 3 can comprise an array of capacitive cells, where the cells are similar to those illustrated in FIG. 5A. In some embodiments, the passive component 3 can have a capacitance of at least 5 nF / mm 2 , at least 10nF / mm 2 , at least 20nF / mm 2 , at least 50nF / mm 2 , at least 100nF / mm 2 or at least 200nF / mm 2 For example, in various embodiments, the passive component 3 may include a cell having an effective capacitance per unit area of ​​5 nF / mm 2 ~400nF / mm 2 Range: 10nF / mm 2 ~300nF / mm 2 Range: 10nF / mm 2 ~250nF / mm 2 Range: 10nF / mm 2 ~150nF / mm 2 range or 10nF / mm 2 ~100nF / mm 2 In some embodiments, for example, the passive component 3 may include cells having an effective capacitance per unit area in the range of 1 nF / mm 2 ~10nF / mm 2 Range: 10nF / mm 2 ~100nF / mm 2 Range: 100nF / mm 2 ~400nF / mm 2 or within the range of 400nF / mm 2 Larger (e.g., 400 nF / mm 2 ~1000nF / mm2 The passive component 3 may include cells with an effective capacitance per unit area in the range of 0.1 to 1.0 . Advantageously, only high-K dielectric materials may be used, such that there is no low-K material in series with the high-K material. By using only high-K materials, the overall capacitance of the passive component 3 can be improved.

[0036] FIG. 5B is a schematic cross-sectional side view of the passive electronic component 3 of FIG. 5A with a bonding layer 8a disposed on a patterned second electrode 121. The bonding layer 8a can act as an interconnect layer, such as a redistribution layer (RDL), to bond the passive electronic component 3 to other structures, such as element 2. For example, as described above, the bonding layer 8a can include conductive features 9a that connect to or define contact pads and surround non-conductive field regions 7a. The conductive features 9a can comprise any suitable metal, such as copper. The field regions 7a can comprise any suitable non-conductive material, such as silicon oxide. As shown in FIG. 5B, the non-conductive field regions 7a can be disposed within the gaps 123 of FIG. 5A to electrically isolate patterned portions of the second electrode 121 and define separate capacitive cells in some embodiments. Advantageously, providing a bonding layer 8a (e.g., using a metal such as copper) on the passive electronic component 3 allows for the use of low temperature annealing (e.g., below 150°C) to improve direct bonding and reduce or eliminate thermal mismatch of materials due to different coefficients of thermal expansion (CTE). Figure 5C is a schematic cross-sectional side view of a portion of the semiconductor element 2 prior to bonding. The semiconductor element 2 can be the same as or generally similar to the semiconductor element 2 shown in Figure 2, with traces 14 and vias 15 providing electrical continuity with the element 2 between the conductive features 9b and the active circuitry.

[0037] FIG. 5D is a schematic cross-sectional side view of a bonded structure 1 in which a semiconductor element 2 is directly bonded to a passive component 3 comprising a high-K dielectric material. As described above, the bonding layers 8a, 8b of the passive component 3 and the semiconductor element 2 can be polished to a very low surface roughness. The polished surfaces can be activated and terminated with a desired species (such as nitrogen). The bonding layers 8a, 8b can be brought into direct contact (e.g., at room temperature) to form a strong bond between the respective field regions 7a, 7b, such as oxide materials. The structure 1 can be heated to increase the bond strength and create an electrical connection between the conductive features 9a, 9b. Thus, as shown in FIG. 5D, the passive electronic component 3 can be directly bonded to the semiconductor element 2 along a direct bond interface 24 without the use of an intervening adhesive. Beneficially, using direct bonding can provide a low-impedance and low-inductance electrical path between the semiconductor element 2 and the passive component 3, thereby improving power or signal integrity. However, in other embodiments, the conductive features 9a, 9b may be adhered to one another with a conductive adhesive (eg, solder) or may be joined using thermocompression techniques.

[0038] As shown in FIG. 5E , the base 122 can be removed (e.g., by grinding, polishing, etching, etc.) from the backside of the passive electronic component 3. In some embodiments, the first electrode 120 can also be patterned to further define the capacitance of the component 3. For example, a noble or refractory metal can be used during processing to define the passive electronic component 3. In some configurations, it may be desirable to add or deposit additional metal electrodes on the refractory metal to reduce pad resistance or meet specific integration requirements. However, in other embodiments, the noble or refractory metals serving as the first electrode 120 and the second electrode 121 may not be removed and thus may remain in the resulting bonded structure 1. These noble or refractory metals may or may not be patterned to create additional discrete electrode regions. In other embodiments, the first electrode 120 and / or the second electrode 121 can comprise a sacrificial material that can be removed and replaced with another metal. 5E, the passive electronic components 3 are illustrated as being laterally wider than the semiconductor elements 2. However, it should be understood that the passive electronic components 3 may cover only a portion of the semiconductor elements 2. For example, as explained above, the passive components 3 may cover at least 55%, at least 65%, at least 75%, at least 85%, at least 95%, at least 99%, or at least 100% of the active surface 11 of the semiconductor elements 2.

[0039] FIG. 5F is a schematic cross-sectional side view of a passive electronic component 3 having an integrated power electrode 126 (or signal electrode) and ground electrode 125. FIG. 5G is a plan view of the passive electronic component 3 of FIG. 5F. As shown in FIG. 5F, the ground electrode 125 can extend from the first surface 12 through the field region 7a and the dielectric layer 110 and can contact the first electrode 120. In various embodiments, the first electrode 120 can be connected to an electrical ground, which can provide a ground pin or terminal when connected to the semiconductor element 2. The power electrode 126 shown in FIGS. 5A and 5B can provide a capacitive electrical path between the first surface 12 and the first electrode 120. Thus, when connected to the semiconductor element 2, power can be transferred between the first surface 12 and portions of the first electrode 120 (by way of the conductive feature 9a and / or contact pad 21), and the first electrode 120 can then be connected to another structure, such as a package substrate 5. Although not illustrated, the first electrode 120 can be patterned or removed and replaced by an interconnect layer (such as the back end of a wiring metal layer) to provide power along a predefined electrical path.

[0040] Figure 5H is a schematic cross-sectional side view of a passive electronic component 3 according to another embodiment. Figure 5I is a plan view of the passive electronic component 3 of Figure 5H. Unlike the embodiments of Figures 5F and 5G, in Figures 5H and 5I, the passive electronic component 3 can include shorting power electrodes 127 in addition to the power electrodes 126 and ground electrodes 125 shown in Figures 5F and 5G. As shown in Figure 5H, for example, some power electrodes 127 may be connected to the second surface 13 of the component 3 by direct conductive interconnects. Thus, in Figures 5H and 5I, the power electrodes 126 may provide a capacitive electrical path between the conductive feature 9a (or contact pad 21) and the second surface 13, while the shorting power electrodes 127 may provide a conductive or resistive electrical path between the conductive feature 9a (or contact pad 21) and the second surface 13.

[0041] 5A-5I, a high-K, thin-film dielectric material can be used to define the passive electronic components 3. In some embodiments, the passive components 3 can be fabricated in one facility to form the high-K material and electrodes (which may comprise a noble or refractory metal suitable for contacting the high-K material), and the semiconductor elements 2 can be formed in another facility to form the active components and interconnects of the elements 2. Beneficially, the noble or refractory metal can be provided to enable high-temperature processing. As explained above, in some embodiments, the noble or refractory metal can be removed and replaced with another metal, such as copper, or with another metallization or routing layer. In other embodiments, the noble or refractory metal can be retained in the final bonded structure 1. The passive components 3 can be bonded (e.g., directly bonded) to the semiconductor elements 2, which can provide a low-impedance and low-inductance connection to improve the signal integrity and / or power integrity of the bonded structure 1.

[0042] FIG. 6 is a plot of transfer impedance of various devices as a function of signal frequency, including a processor die with no capacitive element (plot A), a processor die with a 100 nF discrete capacitor mounted thereon (plot B), a processor die with a 100 nF capacitor mounted on a package substrate (plot C), a processor die with a 100 nF capacitive sheet similar to that disclosed in the embodiments of FIGS. 1-5I (plot D), a processor die with a 10 nF capacitive sheet similar to that disclosed in the embodiments of FIGS. 1-5I (plot E), and a processor die with a 1 nF capacitive sheet similar to that disclosed in the embodiments of FIGS. 1-5I (plot F). As shown in FIG. 6, the conventional devices reflected in plots A, B, and C have relatively high transfer impedance values ​​at frequencies above 500 MHz and / or above 1 GHz. Such high impedance above 500 MHz or 1 GHz may reduce the power integrity or signal integrity of the processor die. In contrast, as reflected in plots D, E, and F, embodiments disclosed herein can significantly reduce impedance at frequencies above 500 MHz, e.g., 1 GHz or greater, which can provide improved signal or power integrity at these higher frequencies. For example, embodiments disclosed herein can provide impedance at 1 GHz that is at least 10 times, e.g., at least 100 times, less than the impedance of the conventional device shown in plots A-C. At the same capacitance level, the directly bonded capacitance sheet exhibits improved performance over discrete capacitors mounted on either the processor die or the package substrate. Furthermore, as shown in FIG. 6, embodiments disclosed herein can provide reduced impedance even at significantly lower effective capacitances (e.g., capacitances as low as about 1 nF or 10 nF).Thus, embodiments disclosed herein can advantageously provide reduced impedance having effective capacitance values ​​in the range of about 0.5 nF to 10 mF, in the range of about 0.5 nF to 1 mF, in the range of about 0.5 nF to 1 μF, in the range of about 0.5 nF to 150 nF, in the range of about 1 nF to 100 nF, or in the range of about 1 nF to 10 nF.

[0043] FIG. 7A is a schematic cross-sectional side view of a passive electronic component 3 according to another embodiment. Unless otherwise indicated, the passive electronic component 3 of FIG. 7A can be bonded to an element 2 (which may comprise a semiconductor element or a non-semiconductor element) described herein. In various embodiments, the passive electronic component can comprise a first surface 12 bonded directly to the element 2 (not shown in FIG. 7A ) without the use of an intervening adhesive. A second surface 13 can be electrically connected to a package substrate (such as substrate 5) or other packaging or system structure. The passive component 3 shown in FIG. 7A beneficially comprises a capacitor having a majority of its electrode surface disposed non-parallel (e.g., generally perpendicular) to the element 2 and surfaces 12, 13. For example, as shown in FIG. 7A , one or more capacitors 220 can be defined in which a majority of its electrode surface extends generally parallel to a major surface of the passive element 3 (e.g., in the xy plane), e.g., a z-axis, which can be non-parallel or perpendicular to surfaces 12, 13.

[0044] In the embodiment shown in FIG. 7A , capacitor 220 can include a first electrode 221 a (which can include one of an anode and a cathode) and a second electrode 221 b (which can include the other of an anode and a cathode) spaced apart by an intervening dielectric 210. As described above in connection with FIG. 1B , in FIG. 7A , the anode and cathode terminals of passive electronic component 3 can be disposed along the same side or surface of component 3. Capacitor 220 can be defined within base 205, which can include an insulating or dielectric material such as silicon, silicon oxide, or the like. Electrodes 221 a, 221 b and dielectric 210 can include major surfaces that extend primarily along a direction non-parallel to surfaces 12, 13, which corresponds to the z-axis in FIG. 7A . In various embodiments, capacitor 220 can have a serpentine profile extending along the x-axis. For example, as shown in FIG. 7A , the electrodes 221 a, 221 b and the dielectric 210 can have respective longitudinal portions 225 that are generally longitudinal, e.g., extending along a z-axis that is non-parallel or perpendicular to the first surface 12 and the second surface 13. The longitudinal portions 225 can be connected by corresponding transverse portions 226 of the electrodes 221 a, 221 b and the dielectric 210, such that the longitudinal portions 225 and transverse portions 226 define a generally serpentine capacitor within the passive element 3. As shown in FIG. 7A , a capacitance C can be provided between the two electrodes 221 a, 221 b along the entire serpentine capacitor 220. In various embodiments, the total capacitance C along the capacitor 220 can be greater than or equal to 100 nF / mm 2 ~20μF / mm 2 range or 100nF / mm 2 ~10μF / mm 2The dielectric 210 may be in the range of . Advantageously, by using a serpentine capacitor, in which the dominant surface of the capacitor 220 lies along a plane parallel (or nearly parallel) to the longitudinal z-axis, the total surface area of ​​the electrodes 221 a, 221 b can be significantly increased, and therefore the total capacitance provided by the passive element 2 can be correspondingly increased. The electrodes 221 a, 221 b can comprise any suitable type of conductor, such as aluminum, silicon, doped silicon, nickel, or other materials. The dielectric 210 can comprise any suitable dielectric material, such as aluminum oxide, silicon oxide, or the like. In some embodiments, increased capacitance can be provided by using high-dielectric materials (e.g., k>10), such as HfO2, ZrO2, BST, SBT, or the like.

[0045] The capacitor 220 can be electrically connected to the element 2 (not shown) by the upper terminals 231a, 231b and to the package substrate 5 (not shown) or another element by the lower terminals 232a, 232b. As shown in FIG. 7A , the first terminal 231a can provide electrical continuity to the first electrode 221a. The second terminal 231b can provide electrical continuity to the second electrode 221b, which may be of a different type than the first terminal 231a. For example, as shown in FIG. 7A , the first terminal 231a can extend through the insulating base 205 to contact the top of the first electrode 221a and be exposed at the first surface 12 of the passive component 3. The second terminal 231b can extend through the insulating base 205 to contact an extension 236 of the second electrode 221b. 7A, for example, the extension 236 of the second electrode 221b can extend through the material of the first electrode 221a, with a dielectric 210 interposed between the first electrode 221a and the extension 236 of the second electrode 221b. Still other methods for electrically connecting to the capacitor 220 may be suitable.

[0046] 7A , the first lower terminal 232a can provide electrical continuity to the first electrode 221a. The second lower terminal 232b can provide electrical continuity to the second electrode 221b. Thus, in various embodiments, on the first surface 12, the upper terminal 231a can be electrically connected to the first electrode 221a (e.g., one of the anode or the cathode), and the upper terminal 231b can be electrically connected to the second electrode 221b (e.g., the other of the anode and the cathode). On the second surface 13, the lower terminal 232a can be electrically connected to the first electrode 221a (e.g., one of the anode or the cathode), and the lower terminal 232b can be electrically connected to the second electrode 221b (e.g., the other of the anode and the cathode). Thus, each surface 12, 13 can be provided with an anode terminal and a cathode terminal (e.g., different types of terminals).

[0047] The passive electronic component 3 may also have a through-hole signal connector 235 extending through the thickness of the passive electronic component 3. The through-hole signal connector 235 may include a conductor providing a conductive path between a first through-hole signal terminal 234 on the first surface 12 and a second through-hole signal terminal 233 on the second surface 13. Any or all of the upper terminals 231 a, 231 b, the lower terminals 232 a, 232 b, and the through-hole signal terminals 234, 233 may be configured to directly bond to the element 2 and / or the system board. Thus, the passive electronic component 3 shown in FIG. 7A may advantageously provide capacitive and conductive paths throughout the signal path. Thus, passive devices having relatively high capacitance may be provided in-line with an integrated circuit without interfering with direct signal connections and without occupying separate system real estate. Arranging the capacitor 220 so that the majority of the electrode surface is aligned with (or nearly parallel to) the longitudinal direction can beneficially improve capacitance by significantly increasing the effective surface area of ​​the electrodes 221a, 221b.

[0048] As shown in FIG. 7A , the upper terminals 231a, 231b and the through signal terminals 234 can be laterally spaced at a finer pitch than the lower terminals 232a, 232b and the through signal terminals 233. For example, in various embodiments, the upper pitch p1 of the terminals on the first surface 12 (e.g., terminals 231a, 231b, and 234) can be spaced at a pitch of less than 50 microns or less than 40 microns. In various embodiments, the upper pitch p1 can be in the range of 0.5 microns to 50 microns, 0.5 microns to 40 microns, 0.5 microns to 20 microns, 0.5 microns to 10 microns, or 1 micron to 10 microns. The fine pitch of the upper terminals 231a, 231b, and the terminals 234 can provide a relatively large number of channels for connection to the component 2. In contrast, the lower pitch p2 of the lower terminals 232a, 232b, and the terminals 233 can be selected for suitable connection to a system motherboard. The lower pitch p2 can be less than 200 microns or less than 150 microns. For example, the lower pitch p2 can be in the range of 50 microns to 200 microns or in the range of 50 microns to 150 microns. Thus, the passive components serve to provide high capacitance passive devices and serve as interposers without occupying separate real estate.

[0049] The vertical capacitor 220 can be defined in any suitable manner. For example, the second electrode 221b can be defined from an initial planar sheet of porous silicon, porous aluminum, or the like. The top surface of the planar sheet can be masked and etched so that channels can be etched in the sheet of second electrode 221b material. The dielectric 210 can be conformally deposited in the channels on the etched surface of the porous aluminum or porous silicon. For example, the dielectric 210 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). An additional conductive material (e.g., aluminum) can be deposited, coated, or otherwise applied on the dielectric 210 to define the first electrode 221a. In some embodiments, the first electrode 221a and the second electrode 221b can comprise the same material. In other embodiments, the first electrode 221a and the second electrode 221b can comprise different materials. Advantageously, the illustrated structures having vertical channels or fins can be easily defined with fewer masking steps compared to horizontal fins.

[0050] FIG. 7B is a schematic cross-sectional side view of a passive electronic component 3 according to another embodiment. Unless otherwise specified, reference numerals in FIG. 7B refer to the same or similar features as similarly numbered components in FIG. 7A. For example, similar to FIG. 7A, the passive electronic component 3 of FIG. 7B can include a capacitor 220 defining a serpentine pattern along the x-axis, with a majority of the electrode surfaces positioned vertically. The major surfaces of the first electrode 221a and the second electrode 221b and the intervening dielectric 210 can extend primarily non-parallel to or perpendicular to the first surface 12 and the second surface 13. Similar to FIG. 7A, the first upper terminal 231a can be electrically connected to the first electrode 221a at or near the first surface 12. 7A, in FIG. 7B each surface 12, 13 of passive component 3 can include an anode terminal and a cathode terminal, such that the anode terminal and the cathode terminal can be disposed along the same side or surface of component 3 (e.g., terminals 231, 231b on surface 12 and terminals 232a, 232b on surface 13). However, unlike in FIG. 7A, extension 236 of second electrode 221b contacts the corresponding second upper terminal 221b in FIG. 7B, and a separate vertical connector 237 can extend downward into passive element 3 to electrically connect second upper terminal 231b with second electrode 221b.

[0051] FIG. 7C is a schematic cross-sectional side view of a passive electronic component 3 in which one or more serpentine capacitors may be defined along both sides of the second electrode 221b. In various embodiments, multiple separate capacitors may be defined within the passive electronic component 3. Unless otherwise noted, reference numerals in FIG. 7C refer to the same or similar features as similarly numbered components in FIGS. 7A and 7B. Similar to FIGS. 7A-7B, the passive electronic component 3 of FIG. 7C has a majority of its electrode surfaces that may extend generally longitudinally and non-parallel to the first surface 12 and the second surface 13. Furthermore, similar to FIGS. 7A-7B, in FIG. 7C, each surface 12, 13 of the passive component 3 may include an anode and a cathode terminal, such that the anode and cathode terminals may be disposed along the same side or surface of the component 3 (e.g., terminals 231, 231b on surface 12 and terminals 232a, 232b on surface 13). However, unlike the embodiment of FIGS. 7A-7B, in FIG. 7C, an upper capacitor 220a can be defined within an upper portion 240a of the passive component 3, and a lower capacitor 220b can be defined within a lower portion 240b of the passive component 3. In the embodiment of FIG. 7C, both sides of an initial planar sheet of aluminum or silicon can be masked and simultaneously etched to define a channel within the second electrode 221b. A dielectric 210 can be deposited on both the upper and lower portions 240a and 240b. Similarly, a conductive material can be deposited on the dielectric 210 on the upper and lower portions 240a and 240b to define the first electrode 221a. The embodiment of FIG. 7C advantageously further increases the total surface area of ​​the electrodes 221a, 221b and, therefore, the total capacitance of the passive electronic component 3.

[0052] FIG. 7D is a schematic cross-sectional side view of a passive electronic component 3 in which a capacitor 220 can be defined by aligned fibers (e.g., carbon fibers) extending along a non-parallel direction z. Unless otherwise noted, reference numbers in FIG. 7D refer to the same or similar features as similarly numbered components in FIGS. 7A-7C. Similar to FIGS. 7A-7C, the passive electronic component 3 of FIG. 7D can have a majority of its electrode surfaces extending generally longitudinally and non-parallel to the first surface 12 and the second surface 13. Furthermore, similar to FIGS. 7A-7C, in FIG. 7D, each surface 12, 13 of the passive component 3 can include an anode and a cathode terminal, such that the anode and cathode terminals can be disposed along the same side or surface of the component 3 (e.g., terminals 231a, 231b on surface 12 and terminals 232a, 232b on surface 13). In such an embodiment, the fibers (e.g., long carbon fibers) can act as the second electrode 221b. The fibers may be coated with a non-conductive material to define the dielectric 210, and subsequently coated with a conductive material to define the first electrode 221 a. Still other methods of forming the vertical capacitor 220 may be suitable.

[0053] The capacitor 220 illustrated in FIGS. 7A-7D can be elongated, such that the height l of the electrode surface of the capacitor 220 along the non-parallel direction z (e.g., defined by the length of the electrodes 221a, 221b) can be greater than the corresponding width w of the undulations of the capacitor 220 along the major lateral surfaces x, y. As illustrated in FIGS. 7A-7D, the width w can be defined according to the pitch of the capacitor 220, e.g., the width of a single undulation of the capacitor. The aspect ratio of the capacitor 220 can be defined by dividing l by w. In various configurations, the aspect ratio can be greater than 5:1. Beneficially, the elongated capacitor 220 illustrated in FIGS. 7A-7D can provide increased electrode surface area compared to other passive devices without requiring extensive masking processes. The increased surface area can significantly increase the total capacitance, even when used with low-dielectric-constant materials.

[0054] As described herein, various types of elements, such as dies or wafers, may be stacked in three-dimensional configurations as part of various microelectronic packaging schemes. This can include stacking one or more layers of dies or wafers onto a larger base die or wafer, stacking multiple dies or wafers in vertical configurations, and various combinations of both. The dies in the stack can include memory devices, logic devices, processors, discrete devices, etc. In various embodiments disclosed herein, very small or thin-profile capacitors can be embedded in insulating materials and included in stacked die configurations, for example, to isolate adjacent bonded devices.

[0055] Dies or wafers may be bonded in a stacked configuration using a variety of bonding techniques, including direct bonding (see, e.g., U.S. Pat. No. 7,485,968, incorporated herein by reference in its entirety). When using direct bonding techniques to bond stacked dies, it is desirable that the surfaces of the dies to be bonded be extremely flat and smooth. For example, as explained above, the surfaces should have very little surface topology variation so that the surfaces can fit tightly together to form a lasting bond. It is also desirable that the surfaces be clean and free of impurities, particles, or other residues.

[0056] According to various embodiments disclosed herein, capacitors (e.g., multilayer capacitors or other passive components) can be embedded in insulating materials, such as ceramics or polymers, to form wafer-level stackable capacitors or other passive devices. In various embodiments, the use of ceramics, polymers, etc. results in devices that can be planarized to have smoother bonding surfaces than may be possible with some other conventional insulating materials. For example, materials such as co-fired ceramics, liquid crystal polymers (LCPs), glass, silicon, or other semiconductors may be used in various embodiments. In some implementations, the ceramic may be pre-cast, or a paste or liquid may be used to form a self-planarizing bonding surface for the device. The bonding surfaces of capacitor devices can be planarized after firing in preparation for bonding.

[0057] Embedded capacitors can include single or multiple layers of components (to provide the desired capacitance) for electrically coupling the capacitor's terminals. One or more of the capacitors can be embedded in an insulating material (such as the "green sheet" illustrated in the figures) using various techniques. In a first embodiment, the capacitor can be deposited on a layer of insulating material (e.g., a pre-fired ceramic), and another layer of insulating material can be placed or deposited on top of the capacitor. The two layers of insulating material can be pressed together to sandwich the capacitor, and the combination can be fired. The insulating material layers can be joined during firing to form an integrated device with the capacitor embedded therein. Thus, in various embodiments, the capacitor's dielectric material can be monolithically integrated with the layer of insulating material.

[0058] In embodiments where the multilayer capacitor is thicker, additional layers of insulating material can be disposed between the top and bottom insulating layers and around the capacitor (forming an intermediate layer that includes the capacitor). When this combination is fired, all of the insulating material layers can be joined together to form an integrated device. In various embodiments, any number of insulating layers can be used with any number of capacitors or layers of capacitors to form a device. Alternatively, the capacitor can be coated with a liquid or paste insulating material that can be fired or cured to solidify the insulating material and form an embedded device.

[0059] In various embodiments, the insulating material can be selected to have a low coefficient of thermal expansion (CTE) or a CTE that is close to the CTE value of the die (which in some examples may be made of silicon) that will be bonded to the capacitive device. For example, the CTE of the capacitive device can be selected to be similar to the CTE of a logic device, processor, etc. that will be bonded to the capacitive device, thereby allowing a combination of devices to be packaged together (e.g., in a stacked configuration) if desired.

[0060] Vias may be formed through insulating materials in the capacitive device to allow signal or power transmission through the capacitive device or to the embedded capacitor. In various implementations, the vias may be formed before or after firing of the capacitive device. In some embodiments, a redistribution layer may be formed on one or both surfaces of the capacitive device, which may be coupled to the vias if desired.

[0061] Additionally, conductive traces can be coupled to the edge connectors of the capacitor to form external terminals for the capacitor on one or both surfaces of the capacitive device. For example, terminals for the capacitor can be located one on each surface of the capacitive device (e.g., the anode and cathode terminals can be on opposite sides of the capacitive device), both on a single surface of the capacitive device (e.g., the anode and cathode terminals can be on the same side or surface of the capacitive device), or there can be a terminal for each edge connector on each side of the capacitive device (e.g., each surface of the capacitive device can include both an anode and a cathode terminal). Thus, for example, two terminals can be connected to one edge connector of the capacitor and configured to transmit a power signal from one side of the capacitive device to the other. Two other terminals can be connected to a second edge connector of the capacitor and configured to provide a ground from one side of the capacitive device to the other. In such a configuration, one side of the capacitor is coupled to a power signal and the other side of the capacitor is coupled to ground. If desired, the terminals may be coupled to one or more of the vias or to a redistribution layer (RDL) (on one or both surfaces). When direct bonding techniques are used to bond capacitive devices, the terminals, vias, and / or RDL connections may be formed as direct bond interconnects on one or more surfaces of the capacitive device. In such cases, at least some of the interconnects may have a pitch in the 1 micron range, and the vias may have a size in the 10-15 micron range. In one embodiment, direct bond interconnects may be used on only one surface of the capacitive device, with terminals for the capacitors on that surface.

[0062]

[0123] In another embodiment, one or more cavities may be formed in the surface of a pre-fired insulating material layer. A capacitor may be deposited in each cavity, and vias may be formed (in any order) in the insulating layer. A redistribution layer may be formed over the layer and capacitors to embed the capacitors in the device. The opposite surface may be planarized, and another RDL may be formed on the planarized surface, if desired.

[0063] The described techniques can result in fewer processing steps, higher manufacturing throughput, and improved yields. Other advantages of the disclosed techniques will be apparent to those skilled in the art.

[0064] 8A-8C illustrate various techniques for embedding capacitors 220 in insulating layers according to various embodiments. FIGS. 8D-8E are schematic cross-sectional side views of passive electronic components 3 that can be formed using any of the techniques illustrated in FIGS. 8A-8C. FIG. 8A is a schematic cross-sectional side view of a first insulating layer 260a, multiple capacitors 220, and a second insulating layer 260b prior to forming the passive electronic components. The embodiment illustrated in FIGS. 8A-8C illustrates multiple capacitors 220 that may be used in wafer-level processing. In other embodiments, only one capacitor 220 may be provided. The capacitor 220 may comprise any suitable type of capacitor, including, for example, a single-layer capacitor having a single dielectric layer between two conductive electrode layers or a multi-layer capacitor having multiple dielectric layers between multiple conductive electrode layers. The capacitor 220 may also be similar to or the same as any of the capacitive structures disclosed herein, including horizontally or vertically oriented capacitors. The first insulating layer 260a and the second insulating layer 260b can comprise any suitable type of insulating or non-conductive material, such as ceramic, glass, or a polymer. In various embodiments, the first insulating layer 260a and the second insulating layer 260b can comprise a ceramic, such as aluminum oxide. In other embodiments, the first insulating layer 260a and the second insulating layer 260b can comprise a polymer, such as a liquid crystal polymer (LCP).

[0065] In various embodiments, the first insulating layer 260a and the second insulating layer 260b can comprise soft or flexible ceramic green sheets, such as ceramic sheets that harden to form a harder ceramic material when heated or fired above a suitable firing temperature. In such embodiments, the capacitor 220 can be provided on the first insulating layer 260a. The second insulating layer 260b can be provided (e.g., deposited) on the capacitor 220. The first layer 260a and the second layer 260b can be pressed together such that the first layer 260a and the second layer 260b contact each other within the gap 262 and around the edge 261 of the capacitor 220. In various embodiments, the first layer 260a and the second layer 260b can conform correspondingly around the periphery of the capacitor 262 and contact each other when pressed. After pressing, the first layer 260a and second layer 260b and embedded capacitor 220 can be fired or co-fired at a temperature above the ceramic firing temperature to melt or blend the first layer 260a and second layer 260b together to create a harder or more rigid structure.

[0066] The first layer 260a and the second layer 260b can comprise the same material in various embodiments. In other embodiments, the first layer 260a and the second layer 260b can comprise different materials. In configurations in which the first layer 260a and the second layer 260b comprise different materials, the materials can be selected so that they cure at or near the same firing or co-firing temperature, e.g., at a temperature or temperature range at which the first layer 260a and the second layer 260b are sufficiently cured. For example, some materials may comprise a high-temperature ceramic (e.g., having a firing temperature of 1000°C or higher) or a low-temperature ceramic (e.g., having a firing temperature of 500°C or higher, or 600°C or higher, e.g., 500°C to 1200°C or 550°C to 1100°C). The resulting passive electronic component 3 is illustrated in FIG. 8D and is described in more detail below.

[0067] FIG. 8B is a schematic cross-sectional side view of a first insulating layer 260a, a plurality of capacitors 220, a second insulating layer 260b, and an intermediate third insulating layer 260c disposed between the first insulating layer 260a and the second insulating layer 260b, prior to forming the passive electronic component. Unless otherwise noted, the embodiment of FIG. 8B is generally similar or identical to the embodiment of FIG. 8A. For example, as in FIG. 8A, a method for forming the passive component of FIG. 8B may also form the passive component 3 shown in FIG. 8D. However, unlike FIG. 8A, in FIG. 8B, the intermediate third insulating layer 260c may be deposited around the side edges 261 of the capacitors 220 before firing. Beneficially, the third intermediate layer 260c may have a selected thickness such that the first layer 260a and the second layer 260b can contact the intermediate layer 260c with little or no applied pressure. In other configurations, pressure may be applied to contact first layer 260a with third layer 260c, and third layer 260c with second layer 260b. After first layer 260a and second layer 260b are pressed together (with third layer 260c interposed therebetween), first layer 260a, second layer 260b, third layer 260c, and capacitor 220 can be co-fired at a temperature sufficient to fuse or otherwise join layers 260a-260c together to form a unified or integrated device, such as the integrated passive component 3 shown in FIG. 8D.

[0068] FIG. 8C is a schematic cross-sectional side view of a capacitor 220 embedded in an insulating layer 260 prior to forming a passive electronic component. Unless otherwise noted, the embodiment of FIG. 8C is generally similar or identical to the embodiment of FIGS. 8A-8B. For example, as in FIGS. 8A-8B, the method for forming the passive component of FIG. 8B may also form the passive component 3 shown in FIG. 8D. However, in the embodiment of FIGS. 8A-8B, the first, second, and third insulating layers 260a-260c may be formed before being deposited on or connected to the capacitor 220. Unlike the embodiment of FIGS. 8A-8B, in the embodiment of FIG. 8C, a powder or other solid mixture may be provided on a carrier 263. The capacitor 220 may be provided on a power source or mixture, and a solution may be added to the powder or mixture. The solution may thicken the powder or mixture into a soft, flexible insulating layer 260 (e.g., a soft ceramic or polymer). The resulting soft, flexible layer 260 can be molded or otherwise formed over and around the capacitor 220, embedding the capacitor 220 within the insulating layer 260. After molding or forming the insulating layer 260 over the capacitor 220, the insulating layer 260 and the capacitor 260 can be co-fired at a temperature sufficient to melt, mix, or otherwise bond the layers 260 together to form a unified or integrated device, such as the integrated passive component 3 shown in FIG. 8D. The carrier 263 can be removed after co-firing. The embodiment of FIG. 8C can advantageously enable the formation of passive components without utilizing multiple deposition processes, such as those shown in FIGS. 8A-8B. Rather, the base insulating layer 260 can be formed around the capacitor 220 and co-fired to form the passive component 3 with relatively few process steps.

[0069] FIG. 8D is a schematic cross-sectional view of a passive electronic component 3 formed using any of the techniques illustrated in FIGS. 8A-8C. The passive electronic component 3 may include similar or identical features to those illustrated in FIGS. 7A-7D, and reference numerals in FIG. 8D may represent similar components as like reference numerals in FIGS. 7A-7D, except where noted. After co-firing the structure of FIGS. 8A-8C, the capacitor 220 may be embedded within the layer 250 of insulating material. In the illustrated embodiment, for example, the capacitor 220 may be fully embedded within the layer 250 of insulating material such that the layer 250 is disposed along the side edges 261 of the capacitor 220 and along the top and bottom surfaces 264a and 264b of the capacitor 220. In FIG. 8D, the layer 250 of insulating material may comprise a first insulator 210a formed by firing or co-firing the assembly illustrated in FIGS. 8A-8C. Accordingly, the first insulator 210a may comprise a hardened ceramic, polymer, glass, or the like.

[0070] 7A-7D, the capacitor 220 shown in FIG. 8D can be at least partially defined by a first electrode 221a, a second electrode 221b, and a second insulator 210b interposed between the first electrode 221a and the second electrode 221b. The first insulator 210a and the second insulator 210b can be selected to have similar co-firing temperatures and / or to have a relatively low CTE that matches the component to which the passive electronic component 3 is bonded (e.g., the semiconductor element 2, which may comprise silicon). In various embodiments, the insulators 210a, 210b comprise the same material. In other embodiments, the insulators 210a, 210b comprise different materials, each having a firing temperature at which both layers 210a, 210b harden and fuse or melt to each other. Thus, after co-firing the assembly shown in any of FIGS. 8A-8C, the first insulator 210a and the second insulator 210b can fuse or intermix with each other to form a monolithically integrated, unitary, or unified structure. For example, co-firing the first insulator 210a and the second insulator 210b can fuse or intermix portions of the first insulator 210a with portions of the second insulator 210b, for example, at the interface between the two insulators 210a, 210b. Thus, in the embodiment of FIG. 8D, the monolithically integrated insulator 210a of layer 250 can be seamlessly integrated with the insulator 210b of the capacitor 220. As discussed above, in various embodiments, the insulators 210a, 210b can comprise various dielectric materials, such as ceramic dielectric materials. In other embodiments, the insulators 210a and / or 210b can comprise a polymer, glass, or the like.

[0071] 7A-7D, the capacitor 220 can include a first terminal 232a connected to a corresponding first electrode 221a. A second terminal 232b can be connected to a corresponding second electrode 221b of the capacitor 220. Each of the first and second terminals 232a and 232b can be defined at least in part by the outermost layer of each of the electrodes 221a and 221b (e.g., the electrodes 221a and 221b disposed on or near the respective top and bottom surfaces 264a and 264b of the capacitor 220) and by edge connectors 251a and 251b electrically connecting the respective AC electrodes 221a and 221b. For example, as shown in FIG. 8D, the first edge connector 251a can be disposed vertically, e.g., non-parallel to the electrode 221a, and can electrically connect the respective ends of the electrode 221a. Similarly, the second edge connector 251b can be disposed longitudinally, e.g., non-parallel to the electrode 221b, and can electrically connect the respective ends of the electrode 221b. As explained above, the electrodes 221a, 221b can be of different types, e.g., one electrode 221a can comprise an anode and the other electrode 221b can comprise a cathode, or vice versa.

[0072] 7A-7B , one or more through signal connectors 235 (e.g., conductive vias) can extend through the thickness of the passive electronic components 3 from the first surface 265a of the insulating layer 250 to the second surface 265b of the insulating layer 250. In some embodiments, the through signal connectors 235 can be formed after co-firing and formation of the passive components 3. For example, in some embodiments, the insulating layers 260a, 260b, and / or 260c and the capacitor 220 can be co-fired to form the passive components. Holes can then be drilled (e.g., drilled, etched, etc.) through the insulating layer 250, and the through signal connectors 235 can be provided or deposited within the holes. In such configurations where the signal connectors 235 are formed after firing, the conductive material for the connectors 235 may not be able to withstand the high temperatures used during the firing or co-firing process. However, in other embodiments, the connectors 235 can comprise conductors having material properties configured to withstand the high temperatures used to fire the structure. In such a configuration, connector 235 may be co-fired with capacitor 220 and insulating layers 260a-260c.

[0073] FIG. 8E is a schematic cross-sectional side view of the passive electronic component 3 shown in FIG. 8D with one or more redistribution layers (RDLs) 252 a, 252 b (e.g., interconnect layers) deposited on the passive electronic component 3. The RDLs 252 a, 252 b can be provided on at least one of the first surface 265 a and the second surface 265 b of the insulating layer 250. In some embodiments, the RDLs 252 a, 252 b can be pre-formed before being provided on the component 3. For example, in some embodiments, the RDLs 252 a, 252 b can be pre-formed and directly bonded to the component 3 without the use of an intervening adhesive. In other configurations, the RDLs 252 a, 252 b can be built up in a layer above the insulating layer 250. The RDLs 252 a, 252 b can be configured to route electrical signals between selected terminals of the capacitor 220 and corresponding terminals or contact pads of an element to which the passive electronic component 3 is connected. 8E, a first RDL 252a may be provided on a first surface 265a of the insulating layer 250. A second RDL 252b may be provided on a second surface 265b of the insulating layer 250. The RDLs 252a, 252b may include a plurality of metal traces at least partially embedded in corresponding RDL insulating layers 266a, 266b. A first surface 12 of the passive component 3 may be defined at an upper surface of the RDL 252a, and a second surface 13 of the passive component 3 may be defined at a lower surface of the RDL 252b.

[0074] 8E, a first conductive trace 253a or conductive via of each RDL 252a, 252b can be electrically connected to a first electrode or terminal 221a of the capacitor at or by a first terminal 232a. As shown, the trace 253a or via (also referred to as an interconnect) can extend through at least a portion of the insulating material or insulator 210b connecting to the respective terminal of the capacitor. Similarly, a second conductive trace 253b of each RDL 252a, 252b can be electrically connected to a second electrode 221b at or by a second terminal 232b. In the illustrated embodiment, terminals 232a, 232b may be defined at least in part by respective portions of edge connectors 251a, 252b (connecting interleaved electrodes 221a, 221b) and by outermost electrodes 221a, 221b (e.g., electrodes 221a, 221b at or near respective first surface 265a or second surface 265b of capacitor 220). Thus, electrical connections to respective electrodes 221a, 222b may be made to edge connectors 251a, 251b and / or outermost electrodes 221a, 221b at surfaces 265a, 265b.

[0075] The traces 253a, 253b can electrically connect the terminals 232a, 232b to respective interconnects 254a, 254b on the first surface 265a or second surface 265b of the insulating material layer 250. As shown in FIG. 8E , the interconnects 254a, 254b can extend through the RDL insulators 266a, 266b and be exposed at the first surface 12 and the second surface 13. In various embodiments, as described below, the insulating layers 266a, 266b can act as respective layers or substrates through which the interconnects (or portions thereof) can extend to connect to a capacitor. The exposed surfaces of the interconnects 254a, 254b can be configured to electrically connect to other elements, such as element 2 (e.g., a semiconductor element such as an integrated device die), a package substrate, an interposer, etc. As described herein, the RDL insulating layers 266a, 266b and exposed surfaces of the interconnects 254a, 254b at surfaces 12, 13 can be polished and prepared for direct bonding in various embodiments. The insulating layers 266a, 266b and exposed interconnects 254a, 254b can be directly bonded to corresponding insulating and / or conductive features of other elements without the use of an intervening adhesive. In some embodiments, elements can be bonded to both surfaces 12, 13 of the component 3. In other embodiments, elements can be bonded to only one surface 12 or 13 of the passive component 3. In still other embodiments, the insulating layers 266a, 266b and / or interconnects 254a, 254b can be bonded to other elements with various adhesives.

[0076] Similar to the embodiments described above, in some configurations, each surface 12, 13 of the passive component 3 can include a respective first interconnect 254a and second interconnect 254b that connect to different types of terminals 232a, 232b on each side of the capacitor 220. For example, each of the surfaces 265a, 265b of the insulating material 250 can include an anode terminal and a cathode terminal. However, in other embodiments, one surface 265a can include an anode terminal and the other surface 265b can include a cathode terminal. Still other combinations of terminals can be provided herein, for example, based on the structure of the RDLs 252a, 252b and how the RDLs 252a, 252b route electrical signals. For example, in the embodiments disclosed herein, some terminals 232a can be connected to a power source and other terminals 232b can be connected to electrical ground, or vice versa.

[0077] 9A-9E illustrate a process for forming a passive electronic component 3 according to various embodiments. Unless otherwise noted, components in FIGS. 9A-9E can be similar or the same as similarly numbered components in FIGS. 7A-8E. FIG. 9A is a schematic cross-sectional side view of an insulating layer 250. The insulating layer 250 can comprise any suitable type of insulator, such as a ceramic, a polymer, a glass, a semiconductor (e.g., silicon), or the like. Referring to FIG. 9A, one or more cavities 267 can be formed in the insulating layer 250, for example, by etching, drilling, or the like. Also, through-hole signal interconnects 235 (or conductive vias) can be provided through at least a portion of the thickness of the insulating layer 250. For example, in some embodiments, holes can be formed (e.g., drilled, etched, etc.) and a conductive material can be provided in the holes to form the vias or interconnects 235. In FIG. 9C, one or more capacitors 220 can be provided in the cavities 267. In some embodiments, a low CTE insulating filler 268 may be provided over and / or around the capacitor 220 within the cavity 267 to support, stabilize, and / or reduce stress on the capacitor 220 .

[0078] As shown in FIG. 9D, a first RDL 252a can be provided on a first surface 265a of the insulating layer 250. An interconnect 254a in the first RDL 252a can be connected to a corresponding terminal 232a of the capacitor 220, and another interconnect 254b (not shown) in the first RDL 252a can be connected to a corresponding terminal 232b of the capacitor 220. For example, portions of the interconnects 254a, 254b can extend through the insulating layers 266a, 266b (which can act as insulating layers or substrates) of the RDLs 252a, 252b to connect to the capacitor. In FIG. 9E, the backside of the insulating material 250 can be partially removed (e.g., polished, grinded, etched, etc.) to expose the surface 264b of the capacitor 220 and the ends of the vias 235. A second RDL 252b can be provided on surface 265b of insulating material 250 and on surface 264b of capacitor 220. As discussed above, RDLs 252a, 252b can be bonded (e.g., directly bonded in some configurations) to insulating layer 250 and capacitor 220. In other embodiments, RDLs 252a, 252b can be bonded in other ways, for example, using an adhesive. In still other embodiments, RDLs 252a, 252b can be built up layer by layer.

[0079] Similar to the embodiment of FIGS. 8D-8E, in FIG. 9E, the capacitor 3 can be embedded within an insulating layer 250, which can act as an insulating element between the insulating layers 266a, 266b. For example, as shown in FIG. 9E, the insulating layer 250 can be disposed along the side edge 261 of the capacitor 220, and the insulating layer 250 can cover a majority of the side edge 261, for example, all or substantially the entire side edge 261. In the embodiment of FIG. 9E, RDLs 252a, 252b can be provided on the top surface 264a and the bottom surface 264b of the capacitor 220. However, unlike FIGS. 8D-8E, in FIG. 9E, the capacitor 3 is not monolithically integrated with the insulating material 250, but instead is inserted (with a filler 268) into the cavity 267. As with other embodiments disclosed herein, each surface 12, 13 of the passive component 3 can include different types of terminals. For example, each surface 12, 13 can include an anode terminal or interconnect and a cathode terminal or interconnect. In other embodiments, one surface 12 can include only anode terminals or interconnects, and the other surface 13 can include only cathode terminals or interconnects, or vice versa. In various embodiments, the pitch of the interconnects 254a and / or 254b on the first surface 12 of the component can have a smaller pitch than the pitch of the interconnects 254a, 254b on the second surface 13. For example, the interconnects 254a and / or 254b on the first surface 12 can be spaced apart and configured to directly bond to another element. In some embodiments, the pitch of the interconnects 254a and / or 254b on the first surface 12 can be 50 microns or less, 10 microns or less, or 1 micron or less. In some embodiments, the terminals of the capacitor 220 may be connected to corresponding interconnects 254a and / or 254b of the RDL on the first surface 12 and may not be connected to any interconnects on the second surface 13, or vice versa.

[0080] 10A-10G illustrate another method of forming passive electronic components 3, in which the passive components are embedded within an insulating layer 250. FIG. 10A is a schematic cross-sectional side view of a first insulating substrate 270a. The first insulating substrate 270a can comprise any suitable type of insulator, such as ceramic, polymer, glass, or insulating composite. Beneficially, the substrates 270a, 270b can comprise a material having a coefficient of thermal expansion (CTE) of 6 ppm / °C or less, or 5 ppm / °C or less. In various embodiments, the CTE of the substrates 270a, 270b can be in the range of 2 ppm / °C to 6 ppm / °C, 3 ppm / °C to 6 ppm / °C, or 3 ppm / °C to 5 ppm / °C. In various embodiments, the substrates 270a, 270b can comprise the same material. In other embodiments, the substrates 270a, 270b can comprise different materials. 10B, a first adhesive 250a may be applied or deposited onto a first insulating substrate 270a. The first adhesive 250a may comprise any suitable type of adhesive, such as an insulating adhesive. In various embodiments, the first adhesive 250a may comprise a non-conductive epoxy.

[0081] 10C , the capacitor 220 may be provided (e.g., disposed, deposited, etc.) on a first adhesive layer 250a. In some embodiments, the capacitor 220 may be partially embedded within the first adhesive layer 250a, such that at least a portion of the first adhesive layer 250a is disposed along the side edge 261 of the capacitor 220 and at least another portion of the first adhesive layer 250a is disposed along the second surface 264b of the capacitor 220. In FIG. 10D , a second adhesive layer 250b may be provided or deposited over and around the capacitor 220. As shown in FIG. 10D , at least a portion of the second adhesive layer 250b may be disposed along the side edge 261 of the capacitor 220 and at least another portion of the second adhesive layer 250b may be disposed along the first surface 264a of the capacitor 220. 10D, the insulating layer 250 can include a first adhesive layer 250a and a second adhesive layer 250b, and the capacitor 220 can be fully embedded within the insulating layer.

[0082] 10E, conductive interconnects can be formed within the passive component 3. For example, through-holes 235 can be formed in through-holes extending through the thickness of the passive component 3 to provide electrical continuity within the component 3. Additionally, interconnects 254a, 254b can be formed in corresponding holes in the insulating substrates 270a, 270b to electrically connect to corresponding terminals 232a, 232b of the capacitor 220. Thus, in the embodiments disclosed herein, the insulating substrates 270a, 270b can act as interconnect layers to provide electrical continuity with other elements or devices. As with other embodiments disclosed herein, each surface 12, 13 of the passive component 3 can include a different type of terminal; for example, each surface 12, 13 can include an anode terminal or interconnect 254a and a cathode terminal or interconnect 254b. In other embodiments, one surface 12 may include only anode terminations or interconnects and the other surface 13 may include only cathode terminations or interconnects, or vice versa.

[0083] As shown in FIG. 10E, the adhesives 250a, 250b can serve as insulating elements disposed between the first and second substrates. The interconnects 254a, 254b can act as conductive vias extending through at least a portion of the insulating elements (e.g., portions of the first and second adhesives 250a, 250b). Additionally, the interconnects 254a, 254b can extend through the substrates 270a, 270b to connect to the capacitor. The adhesives 250a, 250b can be disposed adjacent to (and / or in contact with) the side edges of the capacitor 220. As shown, the capacitor 220 can be disposed in a first region between the first substrate 270a and the second substrate 270b, and at least a portion of the insulating element (e.g., adhesive 250a, 250b of the insulating material 250) can be disposed in a different second region between the first substrate 270a and the second substrate 270b. Beneficially, the use of low-CTE substrates 270a, 270b and the intervening insulating material 250 can provide an overall passive component 3 with a low overall effective CTE that approximates the CTE of the components on which the passive component 3 is mounted, e.g., the CTE of a semiconductor or silicon substrate. Beneficially, in such a configuration, the overall effective CTE of the passive component 3 (including, for example, the insulating and conductive materials shown in FIG. 10E) can be 8 ppm / °C or less, 7 ppm / °C or less, or 6 ppm / °C or less. In various embodiments, the total effective CTE of the passive component 3 (also referred to herein as the microelectronic device) can be in the range of 3 ppm / °C to 7 ppm / °C, in the range of 4 ppm / °C to 8 ppm / °C, or in the range of 4 ppm / °C to 7 ppm / °C.

[0084] FIG. 10F illustrates an alternative method of forming passive components after the step shown in FIG. 10C. For example, following application of capacitor 220 on first adhesive layer 250a of FIG. 10C, instead of applying second adhesive 250b on capacitor 220 and first adhesive layer 250a as shown in FIG. 10D, molding compound 269 can be applied around at least side edges 261 of capacitor 220. Molding compound 269 can comprise an insulating sublayer of insulating layer 250; for example, molding compound 269 can comprise a non-conductive epoxy, an encapsulant, or the like. In some embodiments, molding compound 269 can be applied around only side edges 261. In other embodiments, molding compound 269 can be applied around side edges 261 and surface 264a of the capacitor. The portion of molding compound 269 above surface 264a can be removed by any suitable method.

[0085] Further, as shown in FIG. 10F, a second adhesive layer 250b (which may comprise a non-conductive or insulating adhesive) may be deposited on the first surface 264a and the upper surface of the molding compound 269. A second insulating substrate 270b may be provided on the second adhesive layer 250b. Thus, in the embodiment of FIG. 10F, the insulating layer 250 may comprise the first adhesive layer 250a, the second adhesive layer 250b, and the molding compound 269. The capacitor 220 may be embedded (e.g., completely embedded) in the insulating layer 250. Referring to FIG. 10G, similar to FIG. 10E, through vias 235 and interconnects 254a, 254b may be provided to provide electrical continuity to the capacitor 220 through the component 3, respectively.

[0086] The adhesives 250a, 250b and molding compound 269 can act as insulating elements disposed between the first substrate 270a and the second substrate 270b. The interconnects 254a, 254b can act as conductive vias extending through at least a portion of the insulating elements (e.g., portions of the first adhesive 250a and the second adhesive 250b). Additionally, the interconnects 254a, 254b can extend through the substrates 270a, 270b to connect to the capacitor. In FIG. 10G, the adhesives 250a, 250b can be disposed adjacent to (and / or in contact with) the top surface of the capacitor 220. The molding compound 269 can be disposed adjacent to (and / or in contact with) the side edges of the capacitor 220. Thus, the capacitor 220 can be embedded within the insulating element (e.g., embedded within the adhesive 250a, 250b and molding compound 269). As shown, the capacitor 220 can be disposed in a first region between the first substrate 270a and the second substrate 270b, and at least a portion of the insulating element (e.g., the adhesive 250a, 250b of the insulating material 250) can be disposed in a different second region between the first substrate 270a and the second substrate 270b. Beneficially, the use of low-CTE substrates 270a, 270b and the intervening insulating material 250 can provide the overall passive component 3 with a low overall effective CTE that approximates the CTE of the component on which the passive component 3 is mounted, e.g., the CTE of a semiconductor or silicon substrate. In such configurations, the overall effective CTE of passive component 3 (including, for example, insulating and conductive materials as shown in FIG. 10G) can beneficially be 8 ppm / °C or less, 7 ppm / °C or less, or 6 ppm / °C or less. In various embodiments, the overall effective CTE of passive component 3 (also referred to herein as a microelectronic device) can be in the range of 3 ppm / °C to 7 ppm / °C, 4 ppm / °C to 8 ppm / °C, or 4 ppm / °C to 7 ppm / °C. Component 3 of FIGS. 10A-10G can comprise a stacked structure that can bond multiple substrates (e.g., substrates 270a, 270b) into one or more capacitors, for example, by one or more adhesives and / or by molding compound.In the illustrated embodiment, the substrates 270a, 270b may comprise materials or layers that are laminated or applied to the capacitor 220 without being deposited using a deposition process.

[0087] 11A-11G illustrate another method of forming passive electronic components 3, in which the passive components are embedded in an insulating layer 250. FIGS. 11A-11B are generally similar to FIGS. 10A-10B, respectively. However, in FIG. 11C, a third insulating substrate 270c can be provided on top of the first adhesive layer 250a and around the capacitor 220. The third insulating substrate 270c can be made of the same material as the substrates 270a and 270b. In other embodiments, the material of the third substrate 270c can be different from the material of the substrates 270a and 270b. The first adhesive layer 250a can be provided on the second surface 264b and on portions of the side edge 261. As shown in FIG. 11C, a first via portion 235a can be advantageously provided through the third insulating substrate 270. The first via portion 235 a may define a portion of a through signal via or interconnect 235 .

[0088] Similar to FIG. 10D , in FIG. 11D , a second adhesive layer 250b can be provided on and around the capacitor 220. For example, the second adhesive layer 250b can be provided around portions of the side edges 261 of the capacitor 220 and on the first surface 264a of the capacitor 220. A second insulating substrate 270b can be provided or deposited on the second adhesive layer 250b. Thus, in FIG. 11D , the capacitor 220 can be embedded within an insulating layer 250, which can include a first adhesive layer 250a and a second adhesive layer 250b. In the illustrated embodiment, for example, the capacitor 220 can be completely or substantially embedded within the insulating layer 250, such that portions of the insulating layer cover most or all of the surface of the capacitor 220.

[0089] Referring to FIG. 11E, interconnects 254a, 254b may be provided to connect to terminals 232a, 232b of capacitor 220. Second via portions 235b may be provided in each of first insulating substrate 270a and second insulating substrate 270b. Second via portions 235b may be electrically connected to first via portions 235a formed through third insulating substrate 270c. For example, in some embodiments, first via portions 235a may be directly bonded to corresponding second via portions 235b without the use of an intervening adhesive. In other embodiments, first via portions 235a may be bonded to second via portions 235b using a conductive adhesive. Advantageously, the use of first via portions 235a in third insulating substrate 270c may enable layer-by-layer construction of resulting through vias or interconnects 235 without providing through holes through insulating layer 250. Alternatively, the third insulating substrate 270c can have a thickness approximately the same as that of the capacitor 220 so that a separate via does not need to be formed through the insulating layer 250.

[0090] As described above, the adhesive materials 250a, 250b and the third substrate 270c can serve as insulating elements disposed between the first substrate 270a and the second substrate 270b. The interconnects 254a, 254b can act as conductive vias extending through at least a portion of the insulating elements (e.g., portions of the first adhesive material 250a and the second adhesive material 250b). Furthermore, the interconnects 254a, 254b can extend through the substrates 270a, 270b to connect to the capacitor. In FIG. 11E, the insulating material 250 can be disposed adjacent to (and / or in contact with) the top surface and side edges of the capacitor 220. Thus, the capacitor 220 can be embedded within the insulating elements. As shown, the capacitor 220 can be disposed in a first region between the first substrate 270a and the second substrate 270b, and at least a portion of the insulating element (e.g., portions of the adhesive 250a, 250b and the third substrate 270c) can be disposed in a different second region between the first substrate 270a and the second substrate 270b. Beneficially, the use of the low-CTE substrates 270a, 270b, the intervening third substrate 270c, and the intervening insulating material 250 can provide an overall passive component 3 with a low overall effective CTE that approximates the CTE of the component on which the passive component 3 is mounted, e.g., the CTE of a semiconductor or silicon substrate. Beneficially, in such a configuration, the overall effective CTE of the passive component 3 (including, for example, the insulating and conductive materials shown in FIG. 11E) can be 8 ppm / °C or less, 7 ppm / °C or less, or 6 ppm / °C or less. In various embodiments, the total effective CTE of the passive component 3 (also referred to herein as the microelectronic device) can be in the range of 3 ppm / °C to 7 ppm / °C, in the range of 4 ppm / °C to 8 ppm / °C, or in the range of 4 ppm / °C to 7 ppm / °C.

[0091] 11F illustrates an alternative method of forming passive components after the step shown in FIG. 11C. For example, following the application of capacitor 220 on first adhesive layer 250a in FIG. 11C, instead of applying second adhesive 250b over capacitor 220, third substrate 270c, and first adhesive layer 250a as shown in FIG. 11D, molding compound 269 can be applied around at least side edges 261 of capacitor 220. Molding compound 269 can comprise an insulating sublayer of insulating layer 250; for example, molding compound 269 can comprise a non-conductive epoxy, an encapsulant, or the like. In some embodiments, molding compound 269 can be applied around only side edges 261. In other embodiments, molding compound 269 can be applied around side edges 261 and surface 264a of the capacitor. The portion of molding compound 269 above surface 264a may be removed in any suitable manner.

[0092] Further, as shown in FIG. 11F, a second adhesive layer 250b (which may comprise a non-conductive or insulating adhesive) may be deposited on the first surface 264a and the upper surface of the molding compound 269. A second insulating substrate 270b may be provided on the second adhesive layer 250b. Thus, in the embodiment of FIG. 11F, the insulating layer 250 may comprise the first adhesive layer 250a, the second adhesive layer 250b, and the molding compound 269. The capacitor 220 may be embedded (e.g., completely embedded) within the insulating layer 250. Referring to FIG. 11G, similar to FIG. 11E, through vias 235 and interconnects 254a, 254b may be provided to provide electrical continuity to the capacitor 220 through the component 3, respectively.

[0093] The adhesives 250a, 250b and molding compound 269 (e.g., insulating material 250) can serve as insulating elements disposed between the first substrate 270a and the second substrate 270b. The interconnects 254a, 254b can act as conductive vias extending through at least a portion of the insulating elements (e.g., the first adhesive 250a and second adhesive 250b portions). Additionally, the interconnects 254a, 254b can extend through the substrates 270a, 270b to connect to the capacitor. In FIG. 11G, the adhesives 250a, 250b can be disposed adjacent to (and / or in contact with) the top surface of the capacitor 220. The molding compound 269 can be disposed adjacent to (and / or in contact with) the side edges of the capacitor 220. Thus, the capacitor 220 can be embedded within the insulating elements (e.g., embedded within the adhesive 250a, 250b and molding compound 269). As shown, the capacitor 220 can be disposed in a first region between the first substrate 270a and the second substrate 270b, and the insulating elements (e.g., the adhesive 250a, 250b of the insulating material 250 and molding compound 269) can be located in a different second region between the first substrate 270a and the second substrate 270b. Beneficially, the use of low-CTE substrates 270a, 270b and intervening insulating elements can provide the overall passive components 3 with a low overall effective CTE that approximates the CTE of the components on which the passive components 3 are mounted, e.g., the CTE of a semiconductor or silicon substrate. In such a configuration, the total effective CTE of passive components 3 (including, for example, insulating and conductive materials as shown in FIG. 11G) can be beneficially 8 ppm / ° C. or less, 7 ppm / ° C. or less, or 6 ppm / ° C. or less. In various embodiments, the total effective CTE of passive components 3 (also referred to herein as microelectronic devices) can be in the range of 3 ppm / ° C. to 7 ppm / ° C., in the range of 4 ppm / ° C. to 8 ppm / ° C., or in the range of 4 ppm / ° C. to 7 ppm / ° C.

[0094] 11H and 11I illustrate alternative configurations to those of FIGS. 11E and 11G, respectively. In FIG. 11H, for example, an additional insulating substrate 270d can be provided around capacitor 220. Substrate 270d can comprise the same or a different material as substrates 270a-270c. In FIG. 11I, molding compound 269 can be provided as part of insulating layer 250. Features of FIGS. 11H and 11I can otherwise be generally similar to those described above in FIGS. 11A-11G. Component 3 of FIGS. 11A-11I can comprise a stacked structure in which multiple substrates (e.g., substrates 270a, 270b) can be bonded to one or more capacitors, for example, by one or more adhesives, by an intervening third substrate 270c, and / or by molding compound. In the illustrated embodiment, the substrates 270a, 270b may comprise materials or layers that are laminated or applied to the capacitor 220 without being deposited using a deposition process.

[0095] 12A-12E illustrate another method of forming passive electronic component 3. In FIG. 12A, first insulating substrate 270a can have a plurality of conductive contact pads 275 on an outer surface of first insulating substrate 270a. In FIG. 12B, capacitor 220 can be connected to contact pads 275 of substrate 270a by a first adhesive, e.g., conductive adhesive 276 comprising solder in the illustrated embodiment. In other embodiments, capacitor 220 can be connected to contact pads 275 by direct bonding without an intervening adhesive. Referring to FIG. 12C, molding compound 269 can be provided around and / or over capacitor 220 and on the surface of substrate layer 270a.

[0096] In FIG. 12D , an adhesive layer 250 b may be disposed on the top surface of the molding compound 269 and on the first surface 264 a of the capacitor 220. A second insulating substrate 270 b may be provided on the adhesive layer 250 b. Thus, in the embodiment of FIG. 12D , the capacitor 220 may be embedded within the insulating layer 250, which may be defined by the molding compound 269 (disposed on the second surface 264 b and side edge 261 of the capacitor 220) and the adhesive layer 250 b (disposed on the first surface 264 a of the capacitor 220). In the illustrated embodiment, the capacitor 220 may be completely or substantially embedded within the insulating layer 250. In FIG. 12E , as described above, various traces and interconnects 254 a, 254 b may pass through portions of the insulating layer 250 to connect to the terminals of the capacitor 220.

[0097] Insulating material 250 (e.g., adhesive 250b and molding compound 269) can serve as an insulating element disposed between first substrate 270a and second substrate 270b. Interconnects 254a, 254b can act as conductive vias extending through at least a portion of the insulating element (e.g., a portion of adhesive 250b). Additionally, interconnects 254a, 254b can extend through substrates 270a, 270b to connect to the capacitor. In FIG. 12E, molding compound 269 can be disposed adjacent to the side edges of capacitor 220. Thus, capacitor 220 can be embedded within the insulating element (e.g., embedded within adhesive 250b and molding compound 269). As shown, the capacitor 220 can be disposed in a first region between the first substrate 270a and the second substrate 270b, and at least a portion of the insulating element can be disposed in a different second region between the first substrate 270a and the second substrate 270b. Beneficially, the use of low-CTE substrates 270a, 270b and intervening insulating elements can provide an overall passive component 3 with a low overall effective CTE that approximates the CTE of the components on which the passive component 3 is mounted, e.g., the CTE of a semiconductor or silicon substrate. Beneficially, in such a configuration, the overall effective CTE of the passive component 3 (including, for example, the insulating and conductive materials shown in FIG. 12E) can be 8 ppm / °C or less, 7 ppm / °C or less, or 6 ppm / °C or less. In various embodiments, the overall effective CTE of passive component 3 (also referred to herein as a microelectronic device) can be in the range of 3 ppm / °C to 7 ppm / °C, in the range of 4 ppm / °C to 8 ppm / °C, or in the range of 4 ppm / °C to 7 ppm / °C. Component 3 of FIGS. 12A-12E can couple multiple substrates (e.g., substrates 270a, 270b) to one or more capacitors, for example, by one or more adhesives and / or by molding compound. In the illustrated embodiment, substrates 270a, 270b may comprise materials or layers that are laminated or applied to capacitor 220 without being deposited using a deposition process.

[0098] 13A-13E illustrate another method of forming a passive electronic component 3. In FIG. 13A, a first insulating substrate 270a can have a plurality of conductive contact pads 275 on an outer surface of the first insulating substrate 270a. In FIG. 13B, a capacitor 220 can be connected to the contact pads 275 of the substrate 270a by a first adhesive, e.g., a conductive adhesive 276 comprising solder in the illustrated embodiment. In other embodiments, the capacitor 220 can be connected to the contact pads 275 by direct bonding without an intervening adhesive. Referring to FIG. 13C, a third insulating substrate 270c having a first via portion 235a can be adhered to a first adhesive layer 250a, which can comprise a non-conductive adhesive. In FIG. 13D, a molding compound 269 can be provided under the surface 264b and around the side edges 261 of the capacitor 220. In Figure 13E, a second adhesive layer 250b can be deposited over the capacitor first surface 264a and over the molding compound 269 and the top surface of the third substrate layer 270c. A second substrate layer 270b can be provided over the second adhesive layer 250b. In Figure 13F, various interconnects 254 and through vias 235 can be provided, as described above.

[0099] The adhesives 250a, 250b, molding compound 269, and substrate 270c can serve as an insulating element disposed between first substrate 270a and second substrate 270b. The interconnects 254a, 254b can act as conductive vias extending through at least a portion of the insulating element. Additionally, the interconnects 254a, 254b can extend through the substrates 270a, 270b to connect to the capacitor. In FIG. 11G, the molding compound 269 can be disposed adjacent to (and / or in contact with) the side edges of the capacitor 220. Thus, the capacitor 220 can be embedded within the insulating element. As shown, the capacitor 220 can be disposed in a first region between the first substrate 270a and the second substrate 270b, and at least a portion of the insulating element can be disposed in a different second region between the first substrate 270a and the second substrate 270b. Beneficially, the use of low-CTE substrates 270a, 270b and intervening insulating elements can provide an overall passive component 3 with a low overall effective CTE that approximates the CTE of the components on which the passive component 3 is mounted, e.g., the CTE of a semiconductor or silicon substrate. Beneficially, in such a configuration, the overall effective CTE of the passive component 3 (including, for example, the insulating and conductive materials shown in FIG. 13F) can be 8 ppm / °C or less, 7 ppm / °C or less, or 6 ppm / °C or less. In various embodiments, the overall effective CTE of passive component 3 (also referred to herein as a microelectronic device) can be in the range of 3 ppm / °C to 7 ppm / °C, in the range of 4 ppm / °C to 8 ppm / °C, or in the range of 4 ppm / °C to 7 ppm / °C. Component 3 of FIGS. 13A-13F can comprise a laminate structure in which multiple substrates (e.g., substrates 270a, 270b) can be coupled to one or more capacitors, for example, by one or more adhesives, an intervening substrate 270c, and / or by molding compound. In the illustrated embodiment, substrates 270a, 270b can comprise materials or layers that are laminated or applied to capacitor 220 without being deposited using a deposition process.

[0100] 14A and 14B illustrate another embodiment of a technique for forming a passive electronic component 3. In FIG. 14A , a carrier 277 may be provided. An adhesive layer 250a may be deposited on the carrier 277. A substrate layer 270 may be adhered to the carrier 277 using the adhesive layer 250a, and the capacitor 220 may be deposited within a cavity in the substrate layer 270a (or the substrate layer 270 may be deposited around a pre-deposited capacitor 220). A molding compound 269 (which may have a low CTE as described above) may be deposited around the capacitor 220, e.g., around the side surfaces 261 of the capacitor 220. An insulating layer 250 may be at least partially defined by the molding compound 269 and the adhesive layer 250a such that the capacitor 220 is embedded within the insulating layer 250, e.g., partially embedded within the insulating layer 250. Carrier 277 can be eliminated in various embodiments, and RDLs 252a, 252b can be provided on opposing sides of molding compound 269 and insulating substrate 270 of capacitor 220. In FIGS. 14A-14B, interconnects 254a, 254b can extend through insulating portions of RDLs 252a, 252b (see layers 266a, 266b above) to connect to the terminals of capacitor 220. The overall effective CTE of passive component 3 (including, for example, insulating and conductive materials shown in FIG. 14B) can be 8 ppm / °C or less, 7 ppm / °C or less, or 6 ppm / °C or less. In various embodiments, the overall effective CTE of passive component 3 (also referred to herein as a microelectronic device) can be in the range of 3 ppm / °C to 7 ppm / °C, 4 ppm / °C to 8 ppm / °C, or 4 ppm / °C to 7 ppm / °C. As mentioned above, the component 3 may comprise a laminate structure.

[0101] As described herein, the passive component 3 (e.g., microelectronic component) embodiments of FIGS. 8A-14B can be bonded (e.g., directly without an intervening adhesive) to one or more other elements (such as one or more semiconductor elements). In some embodiments, the passive component 3 of FIGS. 8A-14B can be bonded directly to elements on one side of the component 3. In other embodiments, the passive component 3 can be bonded directly to elements on opposite sides of the passive component 3, such that the passive component 3 is between the elements. Indeed, such bonding structures can be implemented for any and / or all of the embodiments disclosed herein.

[0102] FIG. 15 is a flowchart illustrating a method 70 for forming a bonding structure, according to various embodiments. The method 70 can begin at block 72 with providing an element having one or more active devices. The element can comprise a semiconductor element, in various embodiments. In other embodiments, the element can comprise a material that may or may not comprise a semiconductor material. In embodiments utilizing semiconductor elements, such as a processor die, the element can be fabricated at a semiconductor processing facility, where semiconductor processing techniques (such as complementary metal oxide semiconductor, or CMOS, processing) can be used to define the active devices on a wafer. The semiconductor processing techniques can be used to form a bonding layer for direct bonding on the element at the semiconductor processing facility. For example, as described above, conductive features and non-conductive field regions can be defined on or near the outer surface of the element. Beneficially, the bonding layer can enable the use of low-temperature anneals to improve bonding and reduce thermal mismatch.

[0103] At block 74, the passive electronic component can be bonded directly to the element without the use of an intervening adhesive. In various embodiments, the anode and cathode terminals of the passive electronic component can be located along the same side of the passive component. The passive component can be any suitable passive component described herein, including a capacitor. The capacitor, in some embodiments, can have a large capacitance defined by a high-K dielectric. In other embodiments, the capacitor can comprise a dielectric with a lower dielectric constant, such as silicon oxide or silicon nitride. In some embodiments, the passive electronic component can be fabricated in a semiconductor processing facility different from that used to fabricate the element. Fabricating the passive component in a different facility can, in some embodiments, allow for high-temperature processing to be used to form the high-K dielectric layer. A bonding layer can also be formed on the passive electronic component in the same manner as the element.

[0104] The wafers with the elements and the wafers with the passive electronic components can be prepared for direct bonding as described above. For example, the bonding layers can be polished to a very high surface smoothness and activated and terminated with the desired species. The non-conductive field regions can be brought into contact with each other at room temperature to form the direct bond. The elements and the passive components can be heated to strengthen the bond and / or create electrical contact between the conductive features.

[0105] In some embodiments, after direct bonding, additional interconnects can be provided on the bonded structures to provide the next level of conductivity with the package substrate. For example, any temporary carrier, such as base 122, can be removed. One or more layers of conductive routing material (back end of the line, or BEOL, layers) can be provided to improve the reliability of the electrical connections with other components (such as package substrates, interposers, or other dies). The bonded wafer can be singulated, for example, by sawing. The singulated bonded structures can be assembled into packages, for example, by attaching the structures to package substrates.

[0106] In some embodiments, such as those illustrated in FIGS. 7A-7B, a passive electronic component can include one or more elongated capacitors with a majority of the electrode surfaces disposed longitudinally. The element can define a major lateral surface. The capacitor can include first and second electrode major surfaces extending along a direction non-parallel to the major lateral surface of the component, the first and second electrodes being separated by a dielectric. In some embodiments, the capacitor can be defined by providing a plurality of fibers extending along non-parallel directions to define a plurality of capacitors. The plurality of fibers can serve as a first electrode, be coated with a non-conductive material that defines a dielectric, and subsequently be coated with a conductive material to define a second electrode. Still other methods of forming capacitors may be suitable.

[0107] In some embodiments, such as those shown in FIGS. 8A-14B, the passive electronic component can include a capacitor embedded within an insulating layer. In some embodiments, the capacitor can be disposed between one or more green sheets, as described above, and the capacitor and green sheets can be co-fired to form a cured passive electronic component. In other embodiments, the capacitor can be disposed within a cavity in an insulating layer. In still other embodiments, the capacitor can be disposed on a first adhesive layer, and a second adhesive layer can be disposed over the capacitor. A first insulating carrier layer and a second insulating carrier layer can be bonded to the first adhesive layer and the second adhesive layer, respectively. In some embodiments, a molding compound can be disposed around the passive component between the first adhesive layer and the second adhesive layer.

[0108] FIG. 16 is a schematic system diagram of an electronic system 80 incorporating one or more bonding structures 1, according to various embodiments. The system 80 can comprise any suitable type of electronic device, such as a mobile electronic device (e.g., a smartphone, a tablet computing device, a laptop computer, etc.), a desktop computer, an automobile or automobile component, a stereo system, a medical device, a camera, or any other suitable type of system. In some embodiments, the electronic system 80 can comprise a microprocessor, a graphics processor, an electronic recording device, or a digital memory. The system 80 can include one or more device packages 82 mechanically and electrically connected to the system 80, for example, by one or more motherboards. Each package 82 can comprise one or more bonding structures 1. The system 80 shown in FIG. 16 can comprise any of the structures 1 and passive components 3 shown and described herein.

[0109] In one embodiment, a bonding structure is disclosed, the bonding structure including an element and a passive electronic component bonded directly to the element without an intervening adhesive. In some embodiments, the passive electronic component comprises a capacitor.

[0110] In another embodiment, a junction structure is disclosed. The junction structure can include an element having one or more active devices at or near the active surface of the element. The junction structure can include a passive electronic component bonded to the element. The passive electronic component can include a sheet having a lateral width at least three times the thickness of the passive electronic component, the sheet covering a majority of the active surface of the element. In some embodiments, the passive electronic component can include a capacitor.

[0111] In another embodiment, a method of forming a bonded structure is disclosed. The method can include providing an element having one or more active devices. The method can include directly bonding a passive electronic component to the element without the use of an intervening adhesive. In some embodiments, the passive electronic component can comprise a capacitor.

[0112] In one embodiment, a microelectronic device is disclosed. The microelectronic component can include a layer of insulating material having a first surface and a second surface. A multilayer capacitor can be embedded within the layer of insulating material between the first surface and the second surface. One or more conductive vias can be formed through the layer of insulating material from the first surface to the second surface. A redistribution layer can be disposed on at least one of the first surface and the second surface, and the redistribution layer can be disposed to electrically couple one or more terminals of the capacitor to one or more interconnects on at least one of the first surface and the second surface.

[0113] In some embodiments, the redistribution layer can be configured to electrically couple two terminals of the multilayer capacitor to at least two interconnects on a first surface and not to the interconnects on a second surface. The redistribution layer can have a substantially planar surface, and the one or more interconnects have a pitch of 1 micron or less. The insulating material can comprise ceramic, glass, or liquid crystal polymer.

[0114] In another embodiment, a method of forming a microelectronic device is disclosed. The method can include depositing a multilayer capacitor on a first layer of insulating material. The method can include depositing a second layer of insulating material on the multilayer capacitor and the first layer of insulating material. The method can include pressing the second layer of insulating material onto the multilayer capacitor and the first layer of insulating material. The method can include co-firing the second layer of insulating material, the multilayer capacitor, and the first layer of insulating material to form an integrated device.

[0115] In some embodiments, the method can include depositing an intermediate layer of insulating material between the first and second layers and around the capacitor before pressing and co-firing. The method can include forming one or more vias through the first and second layers of insulating material after co-firing. The method can include forming one or more vias through the first and second layers of insulating material before co-firing. The method can include forming a redistribution layer on an outer surface of the first or second layer of insulating material, the redistribution layer including one or more electrical interconnects coupled to one or more terminals of the capacitor. The redistribution layer can include at least one interconnect coupled to each of the terminals of the capacitor. The method can include bonding the redistribution layer to the prepared bonding surface by a direct bonding technique without the use of an adhesive.

[0116] In another embodiment, a method of forming a microelectronic device is disclosed. The method can include forming a cavity in a surface of an insulating layer. The method can include forming one or more vias through at least a portion of a thickness of the insulating layer. The method can include depositing a multilayer capacitor within the cavity. The method can include forming a redistribution layer over the capacitor and the insulating layer, the redistribution layer including one or more electrical interconnects coupled to one or more terminals of the capacitor.

[0117] In some embodiments, the method can include planarizing a surface of the insulating layer opposite the redistribution layer and forming another redistribution layer on the planarized surface, where the other redistribution layer can include one or more electrical interconnects coupled to one or more terminals of the capacitor.

[0118] In another embodiment, a junction structure is disclosed. The junction structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can include a capacitor between the first and second surfaces. The capacitor can include first and second terminals on the first surface of the capacitor, a first conductive electrode electrically connected to the first terminal, a second conductive electrode electrically connected to the second terminal, and a high-K dielectric between the first and second conductive electrodes.

[0119] In some embodiments, the high-K dielectric comprises a ceramic. The element can be directly bonded to the passive electronic component without the use of an intervening adhesive. The ceramic dielectric can comprise at least one of a titanate, a niobate, and a zirconate.

[0120] In another embodiment, a microelectronic device is disclosed. The microelectronic device can include an insulating material having a first surface and a second surface. A capacitor can be embedded in the insulating material between the first surface and the second surface, and the capacitor can be monolithically integrated with the insulating material to define a monolithic structure. A first interconnect can be disposed at or through the first surface, and the first interconnect can be electrically connected to a first terminal of the capacitor. The capacitor can include a ceramic dielectric. The ceramic dielectric can include aluminum oxide. The capacitor can include a multilayer capacitor having multiple dielectric layers between multiple conductive layers. The ceramic dielectric can be monolithically integrated with the insulating material. A redistribution layer (RDL) can be connected to one of the first surface and the second surface, and the first interconnect can be at least partially disposed within the RDL. A second interconnect can be disposed at the first surface, and the second interconnect can be electrically connected to a second terminal of the capacitor, and the first terminal is of a different type than the second terminal. A through conductive via can extend through the insulating layer from the first surface to the second surface. A layer of insulating material can be disposed along a top surface of the capacitor, along a bottom surface of the capacitor, and along side edges of the capacitor.

[0121] In another embodiment, a microelectronic device is disclosed. The microelectronic device can include an insulating material having a first surface and a second surface opposite the first surface. A capacitor can be at least partially embedded within the insulating material between the first and second surfaces. An interconnect layer can be disposed on the first surface, and the interconnect layer can be positioned to electrically couple one or more terminals of the capacitor to one or more interconnects extending at or through the first surface of the insulating material.

[0122] In some embodiments, the capacitor can be completely embedded in the insulating material. The capacitor can be partially embedded in the insulating material, with the insulating material disposed along an outer edge of the capacitor. The microelectronic device can include a first insulating substrate, with a first surface of the capacitor mechanically coupled to the first insulating substrate by a first adhesive, and the insulating material comprising the first adhesive. The microelectronic device can include a second insulating substrate, with a second surface of the capacitor mechanically coupled to the second insulating substrate by a second adhesive, and the insulating material further comprising a second adhesive. A molding compound can be disposed around a portion of the capacitor, and the insulating material further comprises a molding compound. A third intermediate insulating substrate can be disposed around the capacitor between the first and second insulating substrates. The first adhesive, in some embodiments, can comprise solder. A second interconnect layer can be disposed on the second surface, and the second interconnect layer can be positioned to electrically couple one or more terminals of the capacitor to one or more interconnects at the second surface of the insulating material. The microelectronic device can include a first interconnect and a second interconnect in the interconnect layer, the first interconnect connected to a first terminal of the capacitor on a first side of the capacitor and the second interconnect connected to a second terminal on the first side, the first terminal being of a different type than the second terminal. The microelectronic device can include a third terminal on the second side of the capacitor and a fourth terminal on the second side, the third terminal being of a different type than the fourth terminal. The layer of insulating material in some embodiments comprises multiple layers. The microelectronic device can include conductive through vias extending through the insulating material. In some embodiments, the bonding structure can comprise a microelectronic device and an element, the element being directly bonded to the microelectronic device without the use of an intervening adhesive.

[0123] In another embodiment, a microelectronic device is disclosed. The microelectronic component can include a first insulating substrate and a capacitor having a first surface and a second surface opposite the first surface, the first surface of the capacitor being mechanically coupled to the first insulating substrate. The microelectronic device can include a second insulating substrate, the second surface of the capacitor being mechanically coupled to the second insulating substrate such that the capacitor is disposed between the first insulating substrate and the second insulating substrate. An insulating element can be disposed between the first insulating substrate and the second insulating substrate. A first interconnect can extend through the first insulating substrate and be electrically connected to a first terminal of the capacitor.

[0124] In some embodiments, a first surface of the capacitor can be mechanically coupled to the first insulating substrate by a first adhesive, the insulating element comprising the first adhesive. A second surface of the capacitor can be mechanically coupled to the second insulating substrate by a second adhesive, the insulating element further comprising a second adhesive. The first adhesive, in some embodiments, can comprise solder. The insulating element can comprise a molding compound disposed around a portion of the capacitor. The insulating element can comprise a third intermediate insulating substrate disposed around the capacitor between the first insulating substrate and the second insulating substrate. A coefficient of thermal expansion (CTE) of one or more of the first insulating substrate and the second insulating substrate can be 5 ppm / °C or less. A CTE of one or more of the first insulating substrate and the second insulating substrate can be in a range of 2 ppm / °C to 5 ppm / °C. A total effective coefficient of thermal expansion (CTE) of the microelectronic device can be 7 ppm / °C or less. The total effective CTE can be in a range of 3 ppm / °C to 7 ppm / °C. The second interconnect can extend through the first insulating substrate, the first interconnect connected to a first terminal of the capacitor on a first side of the capacitor, and the second interconnect connected to a second terminal on the first side, the first terminal being of a different type than the second terminal. The microelectronic component can include a third terminal on a second side of the capacitor and a fourth terminal on the second side, the third terminal being of a different type than the fourth terminal. At least a portion of the insulating element can be disposed adjacent to a side edge of the capacitor. The capacitor can be disposed in a first region between the first substrate and the second substrate, and at least a portion of the insulating element is disposed in a second region between the first substrate and the second substrate, the first region and the second region being different from each other. The bonding structure can include a microelectronic device and an element, the element being directly bonded to the microelectronic device without the use of an intervening adhesive.

[0125] In another embodiment, a method of forming a microelectronic device is disclosed. The method can include mechanically coupling a first surface of a capacitor to a first insulating substrate. The method can include mechanically coupling a second surface of the capacitor to a second insulating substrate such that the capacitor is disposed between the first insulating substrate and the second insulating substrate. The method can include disposing an insulating element between the first insulating substrate and the second insulating substrate. The method can include providing a first interconnect extending through the first insulating substrate and electrically connecting to a first terminal of the capacitor.

[0126] In some embodiments, the method can include adhering the capacitor to a first insulating substrate with an adhesive. The method can include adhering a second substrate to the capacitor with a second adhesive. The method can include providing a molding compound around at least a portion of the capacitor between the first insulating substrate and the second insulating substrate.

[0127] In another embodiment, a bonding structure is disclosed. The bonding structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can include a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element, the first anode terminal and the first cathode terminal being disposed on the first surface of the passive electronic component.

[0128] In some embodiments, the passive electronic component is directly bonded to the element without the use of an intervening adhesive. The passive electronic component may comprise a capacitor. The capacitor may comprise three or more metal layers separated by multiple dielectric layers. The passive electronic component may comprise a third anode terminal and a third cathode terminal on a second surface of the passive electronic component. The element may comprise a semiconductor element. The bonding structure may comprise a plurality of electrical contacts on the second surface of the passive electronic component, the plurality of electrical contacts configured to electrically connect to an external component. The bonding structure may comprise an interconnect structure defining an electrical path between the element and a first electrical contact of the plurality of electrical contacts. The interconnect structure may comprise a conductive electrical interconnect extending from the first surface to the first electrical contact, the conductive electrical interconnect being embedded in a dielectric disposed between the first surface and the second surface. The conductive electrical interconnect may include a longitudinal conductive portion extending from a first contact pad at or near the first surface to the first electrical contact and one or more lateral conductive portions extending laterally outward from the longitudinal conductive portion, the longitudinal conductive portion defining a resistive electrical path and the one or more lateral conductive portions defining a capacitive electrical path parallel to the resistive electrical path. The element may define a major lateral surface, and the capacitor may include first and second electrode surfaces extending along a direction non-parallel to the major lateral surface, the first and second electrode surfaces separated by a dielectric. A first height of the first electrode surface along the non-parallel direction may be greater than a width of the capacitor's relief along the major lateral surface. An aspect ratio may be defined by dividing the first height by the width, and the aspect ratio may be greater than 5:1. At least one of the first and second electrode surfaces may comprise aluminum, silicon, doped silicon, or nickel. The capacitor can include a serpentine pattern extending through the passive electronic component, the serpentine pattern can include longitudinal portions of each of the first and second electrode surfaces and corresponding transverse portions of the first and second electrode surfaces connecting the longitudinal portions.

[0129] In another embodiment, a junction structure is disclosed. The junction structure can include an element having one or more active devices at or near an active surface of the element, the active surface defining a major lateral surface of the junction structure. The junction structure can include a passive electronic component bonded to the element, the passive electronic component comprising a capacitor having first and second electrode surfaces extending along a direction non-parallel to the major lateral surface, the first and second electrode surfaces separated by a dielectric.

[0130] In some embodiments, the passive electronic component can be directly bonded to the element without an intervening adhesive. The first height of the first electrode surface along the non-parallel direction can be greater than the width of the capacitor's undulations along the major lateral surface. The aspect ratio can be defined by dividing the first height by the width, and the aspect ratio is greater than 5:1. At least one of the first electrode surface and the second electrode surface can comprise aluminum. The capacitor can have a serpentine pattern extending through the passive electronic component. The serpentine pattern can include vertical portions of the first electrode surface and the second electrode surface, respectively, and corresponding horizontal portions of the first electrode surface and the second electrode surface connecting the vertical portions. The bonding structure can include a first terminal electrically connected to the first electrode surface and a second terminal electrically connected to the second electrode surface, the first terminal and the second terminal being exposed on the top surface of the passive electronic component. An extension of the second electrode surface can extend through the first electrode surface and connect to the second terminal.

[0131] In another embodiment, a junction structure is disclosed. The junction structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can include a passive device. The passive device can include a first terminal and a second terminal on the first surface of the passive electronic component, a first conductive interconnect electrically connected to the first terminal, a second conductive interconnect electrically connected to the second terminal, and a dielectric between the first conductive interconnect and the second conductive interconnect.

[0132] In some embodiments, the elements may be bonded directly to passive electronic components without the use of an intervening adhesive. The passive devices may comprise capacitors.

[0133] In another embodiment, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component bonded directly to the element without the use of an intervening adhesive.

[0134] In some embodiments, the passive electronic component can comprise a capacitor. The capacitor can comprise three or more metal layers separated by multiple dielectric layers. The capacitor can comprise a dielectric layer having a dielectric constant in the range of 1 to 10. The passive electronic component can comprise a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode, the dielectric material comprising a high-K dielectric. The high-K dielectric can comprise titanates (BaxSr1-xTiO3, Bi4Ti3O12, PbZrxTi1-xO3), niobates (LiNbO3), and / or zirconates (BaZrO3, CaZrO3). The first electrode can comprise a noble metal. The passive electronic component can have a capacitance per unit area in the range of 1 nF / mm2 to 1 μF / mm2. The passive electronic component can have a capacitance per unit area in the range of 5 nF / mm2 to 400 nF / mm2. The passive electronic component may have a capacitance per unit area in the range of 100 nF / mm² to 400 nF / mm². The passive electronic component may have a capacitance per unit area in the range of 400 nF / mm² to 1000 nF / mm². The bonding structure may include a plurality of passive electronic components bonded directly to the element without the use of an intervening adhesive. The passive components may be provided in a passive component layer bonded directly to the element, the passive component layer covering a majority of the element. The passive component may include a first surface bonded directly to the element and a second outer surface opposite the first surface. The bonding structure may include a plurality of electrical contacts on the second outer surface, the plurality of electrical contacts configured to electrically connect to an external component. The bonding structure may include an interconnect structure defining an electrical path between the element and a first electrical contact of the plurality of electrical contacts. The interconnect structure can include a conductive electrical interconnect extending from a first surface to a first electrical contact, the conductive electrical interconnect embedded in a dielectric disposed between the first surface and a second surface.The conductive electrical interconnect can comprise a longitudinal conductive portion extending from a first contact pad at or near the first surface to the first electrical contact and one or more lateral conductive portions extending laterally outward from the longitudinal conductive portion, the longitudinal conductive portion defining a resistive electrical path and the one or more lateral conductive portions defining a capacitive electrical path in parallel with the resistive electrical path. The junction structure can comprise a second interconnect structure comprising a second conductive electrical interconnect extending from the first surface to a second electrical contact of the plurality of electrical contacts. The second conductive electrical interconnect may comprise a second longitudinal conductive portion extending from a second contact pad at or near the first surface to the first electrical contact and one or more second lateral conductive portions extending laterally outward from the second longitudinal conductive portion, wherein the second longitudinal conductive portion defines a second resistive electrical path and the one or more second lateral conductive portions define a second capacitive electrical path in parallel with the second resistive electrical path. The one or more lateral conductive portions and the one or more second lateral conductive portions may be interleaved with one another and separated by an intervening dielectric material. One of the interconnect structure and the second interconnect structure may be configured to connect to a power source, and the other of the interconnect structure and the second interconnect structure may be configured to connect to an electrical ground. The passive electronic component may comprise a plurality of alternating conductive and dielectric features disposed between opposing first and second surfaces of the passive electronic component. The passive electronic component can include a first electrode directly bonded to the element on a first surface of the passive electronic component, a second electrode on a second outer surface of the passive electronic component, and an intervening dielectric material, where the first electrode is patterned into a plurality of bond pads with the intervening dielectric. The second electrode can include a noble metal. The noble metal can include platinum or ruthenium. The intervening dielectric material can include a high-K dielectric. The intervening dielectric material can include a complex oxide. The intervening dielectric material can include titanates (BaxSr1-xTiO3, Bi4Ti3O12, PbZrxTi1-xO3), niobates (LiNbO3), and / or zirconates (BaZrO3, CaZrO3).

[0135] In another embodiment, a bonding structure is disclosed that can include an element having one or more active devices at or near an active surface of the element, and a passive electronic component bonded to the element, the passive electronic component comprising a sheet having a lateral width at least three times a thickness of the passive electronic component, the sheet covering a majority of the active surface of the element.

[0136] In some embodiments, the passive electronic component may comprise a capacitive sheet. The passive electronic component may be bonded directly to the element without the use of an intervening adhesive.

[0137] In another embodiment, a method of forming a bonding structure is disclosed. The method can include providing an element having one or more active devices. The method can include directly bonding a passive electronic component to the element without an intervening adhesive.

[0138] In some embodiments, the method can include forming three or more metal layers separated by multiple dielectric layers in a passive electronic component. The passive electronic component can comprise a sheet having a lateral width at least three times the thickness of the passive electronic component, and the method can include covering a majority of an active surface of the element with the sheet. The method can include forming the passive electronic component to include a first electrode comprising a refractory metal, a second electrode, and an intervening dielectric layer having a dielectric constant greater than 10. The method can include patterning the second electrode to define multiple portions of the second electrode. The method can include forming the passive electronic component in a first facility and forming the element in a second facility different from the first facility.

[0139] For purposes of summarizing the disclosed embodiments and the advantages achieved over the prior art, certain objects and advantages have been described herein. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment. Thus, for example, those skilled in the art will recognize that the disclosed implementations may be embodied or performed in a manner that achieves or optimizes one advantage or group of advantages as taught or suggested herein, without necessarily achieving other objects or advantages that may be taught or suggested herein.

[0140] All of these embodiments are intended to be within the scope of the present disclosure. These and other embodiments will be readily apparent to those skilled in the art from the following detailed description of the embodiments, taken in conjunction with the accompanying drawings, and the claims are not limited to any particular embodiment disclosed. While this specific embodiment and example is disclosed herein, it will be understood by those skilled in the art that the disclosed implementations extend beyond the specifically disclosed embodiments to other alternative embodiments and / or uses thereof, as well as obvious modifications and equivalents. In addition, while some variations have been shown and described in detail, other variations will be apparent to those skilled in the art based on this disclosure. It is also contemplated that various combinations or subcombinations of specific features and aspects of the embodiments may be made and still fall within the scope. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another to form varying modes of the disclosed implementations. Accordingly, it is intended that the scope of the disclosed subject matter herein should not be limited by the specific disclosed embodiments described above, but should be determined solely by a fair reading of the following claims.

Claims

1. 1. A microelectronic device comprising: a first insulating substrate; a capacitor having a first surface and a second surface opposite the first surface, the first surface of the capacitor being mechanically coupled to the first insulating substrate; a second insulating substrate, the second surface of the capacitor mechanically coupled to the second insulating substrate such that the capacitor is disposed between the first insulating substrate and the second insulating substrate; an insulating element disposed between the first insulating substrate and the second insulating substrate; a first interconnect extending through the first insulating substrate to electrically connect to a first terminal of the capacitor.

2. The microelectronic device of claim 1 , wherein the first surface of the capacitor is mechanically coupled to the first insulating substrate by a first adhesive.

3. 3. The microelectronic device of claim 2, wherein the second surface of the capacitor is mechanically coupled to the second insulating substrate by a second adhesive, the insulating element further comprising the second adhesive.

4. The microelectronic device of claim 2 , wherein the first adhesive material comprises a solder.

5. The microelectronic device of claim 1 , wherein the insulating element comprises a molding compound disposed around a portion of the capacitor.

6. The microelectronic device of claim 1 , wherein the insulating element comprises a third intermediate insulating substrate disposed around the capacitor between the first insulating substrate and the second insulating substrate.

7. 10. The microelectronic device of claim 1, wherein one or more of the first insulating substrate and the second insulating substrate have a coefficient of thermal expansion (CTE) of 5 ppm / [deg.]C or less.

8. 10. The microelectronic device of claim 1, wherein the microelectronic device has an overall effective coefficient of thermal expansion (CTE) of 7 ppm / [deg.]C or less.

9. 10. The microelectronic device of claim 1, further comprising a second interconnect extending through the first insulating substrate, the first interconnect connected to a first terminal of the capacitor on a first side of the capacitor, and the second interconnect connected to a second terminal on the first side, the first terminal being of a different type than the second terminal.

10. 10. The microelectronic device of claim 9, further comprising a third terminal on the second side of the capacitor and a fourth terminal on the second side, the third terminal being of a different type than the fourth terminal.

11. A bonded structure comprising the microelectronic device of claim 1 and an element, wherein the element is bonded directly to the microelectronic device without the use of an intervening adhesive.

12. 1. A microelectronic device comprising: an insulating material having a first surface and a second surface opposite the first surface; a capacitor at least partially embedded within the insulating material between the first surface and the second surface; an interconnect layer disposed on the first surface and configured to electrically couple one or more terminals of the capacitor to one or more interconnects at or extending through the first surface of the insulating material.

13. The microelectronic device of claim 12 , wherein the capacitor is completely embedded within the insulating material.

14. 13. The microelectronic device of claim 12, further comprising a first insulating substrate, wherein a first surface of the capacitor is mechanically coupled to the first insulating substrate by a first adhesive, and wherein the insulating material comprises the first adhesive.

15. 15. The microelectronic device of claim 14, further comprising a second insulating substrate, the second surface of the capacitor being mechanically coupled to the second insulating substrate by a second adhesive, the insulating material further comprising the second adhesive.

16. 13. The microelectronic device of claim 12, further comprising a molding compound disposed around portions of the capacitor, the insulating material further comprising the molding compound.

17. A joint structure, elements, a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface, the passive electronic component having a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element, the first anode terminal and the first cathode terminal being disposed on the first surface of the passive electronic component.

18. 20. The bonded structure of claim 17, wherein the passive electronic component is bonded directly to the element without the use of an intervening adhesive.

19. The bonded structure of claim 17 , wherein the passive electronic component comprises a capacitor.

20. 20. The bonded structure of claim 19, wherein the capacitor dielectric material comprises a high-K dielectric.

21. 20. The bonded structure of claim 19, wherein the capacitor comprises a serpentine pattern extending through the passive electronic component.

22. 20. The junction structure of claim 19, wherein the passive electronic component comprises a feedthrough signal conductor extending through the passive electronic component.

23. A joint structure, elements, a passive electronic component bonded directly to the element without the use of an intervening adhesive.

24. 24. The bonded structure of claim 23, wherein the passive electronic component comprises a capacitor.

25. 25. The bonded structure of claim 24, wherein the capacitor comprises three or more metal layers separated by multiple dielectric layers.

26. 24. The bonded structure of claim 23, wherein the passive electronic component comprises a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode, the dielectric material comprising a high-K dielectric.

27. The high-K dielectric is a titanate (BaxSr 1 -xTiO 3 , Bi 4 Ti 3 O 12 , PbZrxTi 1 -xO 3 ), niobate (LiNbO3) and / or zirconate (BaZrO 3 , CaZrO 3 27. The bonded structure of claim 26, comprising:

28. 24. The junction structure of claim 23, wherein the passive electronic component comprises a feedthrough signal conductor extending through the passive electronic component.

Images