Inspection method of semiconductor device

Abstract

To provide an inspection method of a semiconductor device capable of preventing degradation of characteristics of a semiconductor device due to a BPD.SOLUTION: An embodiment includes the following steps of: preparing a semiconductor substrate including silicon carbide; generating image data of a transmission polarization image of the semiconductor substrate by a transmission polarization image acquisition device; and performing an image processing of the image data by the transmission polarization image processing device to determine and store defect coordinates. After an epitaxial layer is formed on the semiconductor substrate and a plurality of semiconductor elements are formed, the plurality of semiconductor elements is sequentially electrically inspected by an electrical characteristic evaluation apparatus. In the inspection by the electrical characteristic evaluation apparatus, the semiconductor element corresponding to the defect coordinates is not inspected, and a process indicating a defect is performed.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiments relate to a method for inspecting a semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) substrates contain numerous basal plane dislocations (BPDs), some of which are known to propagate into the epitaxial layer after epitaxial growth and expand into stacking faults due to electron and hole injection.

[0003] When BPDs expand into stacking faults, they cause degradation of semiconductor device characteristics. There is a demand for removing BPDs to prevent degradation of semiconductor device characteristics due to BPDs. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2017 / 078127 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the embodiments is to provide a semiconductor device inspection method that can prevent the characteristics of the semiconductor device from being degraded due to BPD. [Means for solving the problem]

[0006] The semiconductor device inspection method according to the embodiment includes the following steps. A semiconductor substrate including silicon carbide is prepared. A transmission polarization image acquisition device captures a transmission polarization image of the semiconductor substrate and converts it into first image data in a predetermined format. A transmission polarization image processing device sets coordinates representing the positions on the substrate of multiple semiconductor elements formed on the semiconductor substrate in the first image data. The transmission polarization image processing device processes the first image data, and if the brightness at any of the multiple coordinates is higher than a first brightness or if the brightness at any of the multiple coordinates is lower than a second brightness, the coordinate is determined to be a first defect coordinate and stored. An epitaxial layer is formed on the semiconductor substrate. Multiple semiconductor elements are formed on the semiconductor substrate with the epitaxial layer formed on it. After the multiple semiconductor elements are formed, an electrical characteristic evaluation device sequentially performs electrical testing on one of the remaining semiconductor elements of the multiple semiconductor elements corresponding to the remaining coordinates other than the first defect coordinates based on preset electrical testing conditions. The semiconductor element corresponding to the first defect coordinates is subjected to a process of identifying it as defective without performing the electrical test using the electrical characteristic evaluation device, and if the electrical test determines that it is defective, a process of identifying that one semiconductor element of the remaining semiconductor elements is defective is performed, and if the electrical test determines that it is within specifications, the one semiconductor element of the remaining semiconductor elements is moved to the next process. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic block diagram illustrating an inspection system for a semiconductor device. [Figure 2] 1 is a flowchart illustrating a method for inspecting a semiconductor device according to an embodiment. [Figure 3] Figure 3(a) is an example of image data of a SiC substrate before forming an epitaxial layer, captured using a transmission polarization inspection device. Figure 3(b) is an X-ray topography image of part A in Figure 3(a). Figure 3(c) is an X-ray topography image of part B in Figure 3(a). [Figure 4]FIG. 1 is a schematic cross-sectional view showing the expansion of BPD after growing an epitaxial layer on a SiC substrate. [Figure 5] 10 is a flowchart illustrating a method for inspecting a semiconductor device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In the present specification and the drawings, elements similar to those already explained are given the same reference numerals and detailed explanations will be omitted as appropriate. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0009] FIG. 1 is a schematic block diagram illustrating an inspection system for a semiconductor device. 1, the inspection system 100 includes a transmission polarization inspection apparatus 10, an electrical characteristic evaluation apparatus 40, a control apparatus 50, and a storage apparatus 60. The inspection system 100 may further include a defect inspection apparatus 30, as in the specific example of FIG.

[0010] In the inspection system 100, the transmission polarization inspection device 10, the defect inspection device 30, and the electrical characteristic evaluation device 40 are each communicatively connected to a control device 50, for example, via a control network. The transmission polarization inspection device 10, the defect inspection device 30, and the electrical characteristic evaluation device 40 communicate with the control device 50 to exchange various control signals, data, and the like.

[0011] The transmission polarization inspection device 10 includes a transmission polarization image acquisition device 12 and a transmission polarization image processing device 14 . The transmission polarization image acquisition device 12 captures a transmission polarization image, which is an image obtained by transmission polarization of a silicon carbide (SiC) substrate (hereinafter referred to as a bulk wafer) before an epitaxial layer is formed. The transmission polarization image acquisition device 12 includes, for example, a light source (not shown) and an imaging unit. The light source is configured, for example, by a light emitting diode that emits ultraviolet light. The light source is disposed on one side of the bulk wafer via a polarizing plate. The imaging unit is disposed on the other side of the bulk wafer. Light from the light source is irradiated onto the bulk wafer via the polarizing plate, and the imaging unit captures a transmission polarization image of the bulk wafer irradiated with light from the light source.

[0012] The transmission polarization image acquisition device 12 converts the captured transmission polarization image into image data (first image data) in a predetermined format, and outputs the image data to the transmission polarization image processing device 14 based on a command from the control device 50, for example.

[0013] The transmission polarization image processing device 14 processes the image data of the transmission polarization image acquired by the transmission polarization image acquisition device 12, determines a defect area (first defect area) of the bulk wafer on the image data, and extracts coordinates (first defect coordinates) included in the defect area. In the image processing, the image data is converted into, for example, brightness data at each coordinate of the image data.

[0014] A bulk wafer is assigned a wafer number in advance to distinguish it from other bulk wafers. For example, the wafer number of the bulk wafer is set and managed by the control device 50 and the storage device 60. The image data acquired by the transmission polarization inspection device 10 is associated with the wafer number.

[0015] In the inspection system 100, for example, coordinates are set for each bulk wafer. The set bulk wafer coordinates include multiple coordinates that identify the respective positions of multiple semiconductor elements formed on the bulk wafer. The coordinates set for each bulk wafer are stored in the storage device 60, for example, in association with the wafer number. In the transmission polarization image processing device 14, coordinates are set in the image data so as to correspond to the coordinates on the bulk wafer. In other words, the multiple coordinates of the image data correspond to the multiple coordinates of the bulk wafer, i.e., the positions of the formed semiconductor elements. Note that the coordinates of the bulk wafer and the image data may be absolute coordinates set for each semiconductor element, or may be relative coordinates from a reference position.

[0016] The transmission polarization image processing device 14 determines a defect area (first defect area) based on the brightness of the image data of the bulk wafer that has been subjected to image processing.

[0017] The transmission polarization image processing device 14 determines a defective area, for example, as follows: That is, the transmission polarization image processing device 14 compares the brightness data of each coordinate in the image data with a preset brightness threshold value (first brightness). The transmission polarization image processing device 14 extracts coordinates whose brightness data is higher than the brightness threshold value. The transmission polarization image processing device 14 further extracts adjacent extracted coordinates. The transmission polarization image processing device 14 calculates the area of ​​the area including the extracted adjacent coordinates, and if the area is larger than a preset area threshold value (first area predetermined value), determines that area to be a defective area.

[0018] The area threshold may be set in advance, or may be set for each wafer number and associated with the wafer number.

[0019] The brightness threshold may be set for each wafer number in association with the wafer number of the bulk wafer. The brightness threshold may also be set for each image data of the bulk wafer. When the brightness threshold is set for each bulk wafer, it can be calculated by processing the brightness data of the bulk wafer using a statistical method. For example, brightness data for each coordinate may be obtained from the image data of the bulk wafer, the average brightness Lav and standard deviation σ may be calculated, and Lav + nσ may be set as the brightness threshold. n is an arbitrary natural number, and an appropriate value may be set, for example, through experiments, etc. Another statistical method is to calculate the median LM and quartile Q4 of the luminance, and use LM+nQ4 as the luminance threshold. n is an arbitrary natural number, and an appropriate value is set, for example, through experiments. In addition to these, the luminance threshold may be set by using an appropriate statistical method for outliers in the luminance data.

[0020] In determining the defective area, the defective area may be defined as an area including a plurality of adjacent coordinates having brightness data lower than a predetermined brightness threshold (second brightness). In this case, if there are adjacent coordinates having brightness lower than the brightness threshold, the transmission polarization image processing device 14 calculates the area of ​​the area based on the distance between the coordinates.

[0021] The transmission polarization image processing device 14 associates a plurality of coordinates included in the area determined to be a defective area with the wafer number and outputs the associated coordinates to the control device 50. The control device 50 stores the wafer number and the plurality of coordinates included in the defective area associated with the wafer number in the storage device 60.

[0022] The defect inspection device 30 inspects a SiC substrate (hereinafter referred to as an epitaxial wafer) having an epitaxial layer formed on a bulk wafer for defects in the epitaxial layer and / or the bulk wafer. The defect inspection device 30 is, for example, a photoluminescence image inspection device, and inspects the surface and internal defects of the epitaxial wafer for defects. Defects on the surface of the epitaxial wafer include, for example, surface scratches, triangular defects, linear defects, etc., and internal defects include BPDs, stacking faults, etc.

[0023] The defect inspection device 30 acquires, for example, image data (second image data) as data related to defects acquired by the defect inspection device 30. The defect inspection device 30 determines a defect area (second defect area) based on the photoluminescence intensity of each coordinate of the image data. The defect area consists of a plurality of adjacent coordinates having intensity data higher than a preset threshold value of photoluminescence intensity.

[0024] For example, if the area of ​​an area including adjacent coordinates is larger than a preset threshold, the defect inspection device 30 sets the area as a defective area. The defect inspection device 30 determines a defective area for each wafer number and extracts multiple coordinates (second defect coordinates) included in the defective area. The defect inspection device 30 associates the extracted multiple coordinates with the wafer number and outputs them to the control device 50. The control device 50 adds the multiple coordinates included in the defective area to the multiple coordinates associated with the corresponding wafer number, and updates the data in the storage device 60.

[0025] The coordinates extracted by the defect inspection device 30 are stored separately from the coordinates extracted by the transmission polarization inspection device 10. However, this is not limiting, and they may be stored without distinction. In this embodiment, the following description will be given assuming that they are stored in association with the wafer number without distinction.

[0026] The electrical characteristic evaluation device 40 performs electrical testing of an SiC substrate (hereinafter referred to as an element-formed wafer) in which semiconductor elements are formed on an epitaxial wafer. The electrical characteristic evaluation device 40 performs electrical testing, such as current-voltage characteristics by probing, for each semiconductor element formed on the element-formed wafer, and performs processing to distinguish between good and bad semiconductor elements.

[0027] For example, data for electrical inspection for each wafer number is stored in the storage device 60. Coordinates for identifying the position of a semiconductor element for each wafer number are stored in the storage device 60. Furthermore, for each wafer number, the storage device 60 stores a plurality of coordinates included in the defect area determined by the transmission polarization inspection device 10 and the defect inspection device 30.

[0028] The control device 50 outputs data for electrical testing for each wafer number to the electrical characteristic evaluation device 40. The electrical characteristic evaluation device 40 sets the data for electrical testing. Note that the data for electrical testing may be set for each lot number that includes multiple wafer numbers, or for each product number that includes multiple lots. For simplicity, the following description will be given assuming that the data for electrical testing is set for each wafer number.

[0029] The control device 50 outputs coordinates that identify the position of the semiconductor element on the bulk wafer and a plurality of coordinates included in the defect area to the electrical characteristic evaluation device 40. The electrical characteristic evaluation device 40 sets these coordinates.

[0030] The electrical characteristic evaluation device 40 inspects the wafer on which devices have been formed based on the data for the electrical inspection and the data on the coordinates of the defective area. The electrical inspection data includes electrical characteristic items, measurement conditions for each electrical characteristic item, and standard values ​​for each electrical characteristic. Examples of electrical characteristics include leakage current, gate threshold voltage, and forward voltage drop of semiconductor devices.

[0031] For example, the electrical characteristic evaluation device 40 receives input of coordinates specifying the positions of semiconductor elements, and sequentially electrically tests the semiconductor elements corresponding to the input coordinates. Note that the coordinate data specifying the positions of the semiconductor elements does not have to be input sequentially, and may be preset in the electrical characteristic evaluation device 40.

[0032] If the electrical characteristic evaluation device 40 determines that the inspected semiconductor element does not meet the electrical test data standards, it performs a process to identify the semiconductor element as defective. The process to identify the defective product is, for example, a process of applying a mark using ink or the like to the surface of the semiconductor element.

[0033] When the electrical characteristic evaluation device 40 inputs one of the multiple coordinates contained in the defective area, it does not perform an electrical inspection on the semiconductor element corresponding to the coordinates, but instead marks the surface of the semiconductor element as a process to identify the defective product.

[0034] The marked semiconductor element is judged as a defective element by an image or the like in the subsequent assembly process into a package, and is excluded from the assembly. Alternatively, when one of the coordinates included in a defective area is input, the electrical characteristic evaluation device 40 may perform an electrical test on the semiconductor element corresponding to the coordinate, and if the semiconductor element is determined to be non-defective, may not affix a mark to the surface of the semiconductor element, because there may be cases where the electrical characteristics of a semiconductor element formed in a defective area are good.

[0035] FIG. 2 is a flowchart illustrating a method for inspecting a semiconductor device according to the embodiment. The above series of operations will be explained using the flowchart in FIG. 2, a bulk wafer is prepared in step S1. The prepared bulk wafer corresponds to a wafer number and is distinguished from other bulk wafers.

[0036] In step S2, the transmission polarization image acquisition device 12 acquires image data of the transmission polarization image of the bulk wafer, and outputs the acquired image data to the transmission polarization image processing device 14 in association with the wafer number.

[0037] In step S3, the transmission polarization image processing device 14 processes the input image data to determine a defect area (first defect area) and extracts multiple coordinates (first defect coordinates) included in the defect area. The transmission polarization image processing device 14 associates the extracted multiple coordinates with the wafer number and outputs them to the control device 50. The control device 50 stores the wafer number and the multiple coordinates associated with the wafer number in the storage device 60.

[0038] In step S4, the bulk wafer that has undergone the transmission polarization inspection is sent to a process for forming an epitaxial layer. To form an epitaxial layer on the bulk wafer, for example, a chemical vapor deposition (CVD) apparatus is used.

[0039] In step S5, the defect inspection device 30 acquires data, such as image data, relating to defects on the surface and inside of the epitaxial wafer.

[0040] In step S6, the defect inspection device 30 processes the image data of the surface and the interior to determine a defect area (second defect area). The defect inspection device 30 extracts a plurality of coordinates (second defect coordinates) contained in the defect area, associates them with the wafer number, and outputs them to the control device 50. The control device 50 adds the plurality of coordinates contained in the defect area so as to associate them with the corresponding wafer number, and updates the data in the storage device 60.

[0041] In step S7, the epitaxial wafer that has been inspected by the defect inspection device 30 is input into the semiconductor element formation process, in which semiconductor layers, insulating films, conductive layers, electrodes, etc. are formed according to the configuration of the semiconductor element.

[0042] In step S8, the control device 50 extracts data for electrical inspection associated with the wafer number, coordinates for identifying the position of the semiconductor element, and multiple coordinates included in the defect area from the storage device 60. The control device 50 outputs the extracted data for electrical inspection, coordinates for identifying the position of the semiconductor element, and multiple coordinates included in the defect area to the electrical characteristic evaluation device 40. The electrical characteristic evaluation device 40 sets the data and coordinates output from the control device 50.

[0043] In step S9, the electrical characteristic evaluation device 40 sequentially inputs coordinates that identify the semiconductor elements, and performs an electrical inspection of the semiconductor elements formed on the wafer on which elements have been formed, based on the data for the electrical inspection (electrical inspection conditions) output from the control device 50. Through the electrical inspection, for example, the electrical characteristic evaluation device 40 measures the current-voltage characteristics of the semiconductor elements formed on the wafer based on the preset electrical inspection conditions. The electrical characteristic evaluation device 40 performs a process of identifying the semiconductor element as a defective product, that is, attaches a mark or the like to the semiconductor element that has been determined to be a defective product.

[0044] When one of a plurality of coordinates included in a defective area is input, the electrical characteristic evaluation device 40 performs a defective product identification process on the semiconductor element corresponding to the coordinates. Alternatively, when one of a plurality of coordinates included in a defective area is input, the electrical characteristic evaluation device 40 may perform an electrical inspection of the semiconductor element corresponding to the coordinates. Then, only if the result of the electrical inspection is a failure, the electrical characteristic evaluation device 40 may perform a defective product identification process on the semiconductor element corresponding to the coordinates.

[0045] In step S10, the wafer on which elements have been formed and which has completed inspection by the electrical characteristic evaluation device 40 is sent to a package assembly process. In the package assembly process, semiconductor elements are packaged, excluding those semiconductor elements that have been subjected to a defective product identification process, to form a semiconductor device.

[0046] The operation and effects of the semiconductor device inspection method according to the embodiment will be described. Fig. 3(a) is an example of image data of a SiC substrate before forming an epitaxial layer, captured by the transmission polarization image acquisition device 12. Fig. 3(b) is an X-ray topography image of part A in Fig. 3(a). Fig. 3(c) is an X-ray topography image of part B in Fig. 3(a). As shown in FIG. 3(a), image data P1 acquired by the transmission polarization image acquisition device 12 has differences in brightness depending on the area. In Figures 3(b) and 3(c), the BPD is shown as a black curve.

[0047] 3(b) and 3(c), BPDs are more densely concentrated in areas with high brightness than in areas with low brightness in the image data P1 acquired by the transmission polarization image acquisition device 12. In other words, the transmission polarization image acquisition device 12 acquires the image data P1 and performs image processing on the image data P1 to detect areas with higher brightness than other areas, thereby making it possible to detect areas with a high concentration of BPDs.

[0048] FIG. 4 is a schematic cross-sectional view showing the expansion of the BPD after growing an epitaxial layer on a SiC substrate. 4, a layer of a bulk SiC substrate is shown as an n-type substrate 1, and an n-type buffer layer 2 is provided on the n-type substrate 1. An n-type drift layer 3 is provided on the n-type drift layer 3. A p-type layer 4 is provided on the n-type drift layer 3.

[0049] The n-type buffer layer 2 and the n-type drift layer 3 are epitaxial layers formed by epitaxial growth using CVD or the like. The concentration of n-type impurities in the n-type drift layer 3 is lower than the concentrations of n-type impurities in the n-type substrate 1 and the n-type buffer layer 2. The p-type layer 4 is a layer containing p-type impurities formed by, for example, ion implantation or the like.

[0050] By applying a higher voltage to the p-type layer 4 than to the n-type substrate 1, holes, which are minority carriers, are injected from the p-type layer 4 into the n-type drift layer 3. Electrons are supplied from the n-type substrate 1, causing a current to flow across the pn junction. This current can cause BPDs to expand into stacking faults.

[0051] 4, a plurality of BPDs d1 to d5 are formed on the n-type substrate 1. These are generated during the manufacturing of the SiC substrate, and are initially difficult to remove.

[0052] By forming the n-type buffer layer 2 on the n-type substrate 1, some of the BPDs are converted into threading edge dislocations (TEDs). TEDs do not expand into stacking faults and are formed in the stacking direction, so they are considered harmless dislocations that have little effect on the performance of the semiconductor device. By providing the n-type buffer layer 2 on the n-type substrate 1, it also functions as a recombination layer where holes injected from the p-type layer 4 recombine with electrons before reaching the n-type substrate 1.

[0053] In the example of Figure 4, of BPDs d1 to d5 initially formed on the n-type substrate 1, BPDs d1, d3, and d4 are converted to TEDs d1a, d3a, and d4a, respectively, during the process of forming the n-type buffer layer 2 by epitaxial growth. On the other hand, BPDs d2 and d5 are not converted to TEDs and may remain in each layer and grow to upper layers. In addition, dislocations occur during the epitaxial growth process, and there may be a small number of cases where TEDs, like TEDs d6, are converted to BPDs d6b during the epitaxial growth process.

[0054] If the semiconductor device is, for example, a metal oxide semiconductor field effect transistor (MOSFET), BPDs do not expand into stacking faults under normal operation because MOSFETs are unipolar devices in which either electrons or holes contribute to conduction. In the case of a vertical-structure MOSFET, the p-type layer in FIG. 4 serves as a p-type base layer and forms a p-n junction together with the n-type drift layer, and this p-n junction can function as a diode connected in antiparallel to the MOSFET. Under conditions in which this diode operates, holes are injected from the p-type base layer into the n-type drift layer, causing BPDs to expand into stacking faults.

[0055] The stacking fault, for example, is a single Shockley stacking fault, which extends in a triangular shape along the C-plane of the SiC crystal. Stacking faults are defects that span multiple semiconductor layers and impede the movement of majority carriers through those layers. Therefore, as shown in image data P1, as the total area of ​​stacking faults increases, the on-resistance of the MOSFET and the forward voltage drop of the diode increase, resulting in a deterioration in performance.

[0056] In other words, because the degradation of semiconductor device characteristics due to BPD does not become apparent until the semiconductor device is in operation, it is difficult to discover it in the early stages and remove it as a defect. Also, although it is technically possible to detect the degradation of characteristics by operating the semiconductor device and remove the detected ones as defects, this would require energization screening of all the devices, making it difficult to realize.

[0057] Although efforts are being made to suppress the occurrence of BPDs in the manufacturing process of SiC substrates, it is difficult to achieve stable suppression of their occurrence. Also, while the etch pit method and X-ray topography method are known as methods for detecting the presence of BPDs, the former is a destructive test, and the latter requires a long measurement time, making it difficult to inspect all products, and the equipment is large, making it even more difficult to introduce into mass production facilities.

[0058] As explained in relation to Figure 4, BPDs are converted into harmless dislocations during the formation of the epitaxial layer. BPDs that are not converted into harmless dislocations and remain can expand into stacking faults during use after the semiconductor device is formed. However, even if BPDs expand into stacking faults, the degradation in performance of the semiconductor device is minimal if the area of ​​the BPD is sufficiently small compared to the area through which current flows in the semiconductor device.

[0059] In an SiC substrate before the formation of an epitaxial layer, in areas with a higher BPD density than other areas, the density of BPDs remaining in that area after the epitaxial layer formation process is high. Therefore, in areas with a high BPD density, the probability that BPDs will expand into stacking faults is also high. Furthermore, if the area of ​​a high BPD density area is large, the probability that the remaining BPDs will degrade the performance of the semiconductor device if they expand into stacking faults is also high. Therefore, in an embodiment of a semiconductor device inspection method, an area with a high density of BPDs that is larger than a predetermined value is detected as a defective area in an SiC substrate before the formation of an epitaxial layer. By determining the semiconductor elements included in the detected defective area as defective in advance, it is possible to remove in advance semiconductor devices whose performance may degrade after the BPDs are energized after the semiconductor device is formed.

[0060] 3, the transmission polarization inspection device 10 can detect BPDs densely packed in a SiC substrate before the formation of an epitaxial layer as a change in brightness of a transmission polarization image. Therefore, in the semiconductor device inspection method according to the embodiment, image data of the transmission polarization image of the SiC substrate is processed to identify areas of dense BPDs as defective areas.

[0061] The electrical characteristic evaluation device 40 has coordinates representing the positions of multiple semiconductor elements formed on a SiC substrate, each assigned a wafer number. In the semiconductor device inspection method according to the embodiment, the coordinates of the semiconductor elements included in the defect area identified in the image data acquired by the transmission polarization inspection device 10 are associated with the wafer number, thereby expanding the defect to include stacking faults and identifying semiconductor elements that are likely to experience a deterioration in characteristics after current is applied.

[0062] In the semiconductor device inspection method according to the embodiment, semiconductor elements with a high density of BPDs are identified and determined to be defective in advance, thereby improving the yield of the final semiconductor device after packaging.

[0063] In the semiconductor device inspection method according to the embodiment, photoluminescence can be used in combination with transmission polarization inspection to perform defect inspection using photoluminescence. By using transmission polarization inspection and photoluminescence inspection together, the accuracy of BPD detection can be improved. Furthermore, in SiC substrates, in addition to stacking faults due to BPDs, dislocations such as threading screw dislocations that degrade the performance of semiconductor devices may occur. In the semiconductor device inspection method according to the embodiment, defect inspection using photoluminescence can be performed after the formation of an epitaxial layer.

[0064] In the photoluminescence inspection method, as in the case of transmission polarization inspection, the image data is processed to identify the defective area, and the coordinates of the semiconductor elements included in the defective area are extracted and stored. In this case, the semiconductor elements corresponding to the coordinates are excluded from the judgment of non-defective products in the wafer inspection, thereby improving the yield after semiconductor element formation.

[0065] (Variation) FIG. 5 is a flowchart illustrating a method for inspecting a semiconductor device according to a modified example of the embodiment. In this modification, by passing a current through the pn junction, BPDs remaining after the formation of the epitaxial layer are expanded into stacking faults, and the influence of the expanded stacking faults on the characteristics of the semiconductor element is removed by electrical screening. This makes it possible to remove in advance semiconductor elements whose characteristics may be degraded by electrical screening after assembly into a package, thereby improving the reliability of the manufactured semiconductor device.

[0066] The flowchart in Fig. 5 differs from the example shown in Fig. 2 in that steps S3a and S9a are applied instead of steps S3 and S9 in Fig. 2. The flowchart in Fig. 5 also differs from the example shown in Fig. 2 in that step S21 is executed after step S9 in Fig. 2, and then step S10 is executed. Below, the differences will be described in detail, and explanations of the same points will be omitted as appropriate.

[0067] 5, in step S3a, the transmission polarization image processing device 14 performs image processing on the image data of the transmission polarization image of the bulk wafer acquired by the transmission polarization image acquisition device 12 in step S2 to determine a defective area. In determining a defective area, it is preferable to use a luminance change over a wider range as a judgment condition than in the example of FIG. 2, such as setting the luminance threshold to Lav+(n-1)σ. As in the example of FIG. 2, if the area of ​​an area including adjacent coordinates having luminance higher than the threshold is larger than a preset area threshold, the transmission polarization image processing device 14 determines the area including those coordinates to be a defective area.

[0068] Furthermore, when associating multiple coordinates included in a defect area with a wafer number, the transmission polarization image processing device 14 associates the multiple coordinates included in the defect area with the wafer number, distinguishing them from the coordinates specifying the position of the semiconductor element stored in the storage device 60. For example, the transmission polarization image processing device 14 attaches a flag indicating that energization screening will be performed, and then associates the wafer number with the multiple coordinates included in the defect area.

[0069] In step S6, the transmission polarization image processing device 14 associates the plurality of coordinates included in the defect area with the wafer number without attaching a flag.

[0070] In step S9a, the electrical characteristic evaluation device 40 performs an electrical inspection of the semiconductor elements formed on the element-formed wafer based on the data for the electrical inspection output from the control device 50. The electrical characteristic evaluation device 40 performs a defective product identification process, for example, attaching a mark, to the semiconductor elements determined to be defective.

[0071] When the electrical characteristic evaluation device 40 receives input of one of the multiple coordinates contained in the defective area determined by the image data of the transmitted polarization image, it does not inspect the semiconductor element corresponding to the coordinate, nor does it perform the process of identifying defective products, and skips the process.

[0072] When the electrical characteristic evaluation device 40 receives input of one of a plurality of coordinates contained in a defective area determined by the image data of a photoluminescence image, it performs a defective product identification process on the semiconductor element corresponding to the coordinates.

[0073] In step S21, the electrical characteristic evaluation device 40 performs electrical screening on each of the semiconductor elements corresponding to the coordinates included in the defect area determined from the image data of the transmission polarization image. In the electrical screening, a current is continuously passed through the pn junction of the semiconductor element under predetermined conditions, and an electrical inspection is performed after a predetermined time has elapsed. The electrical characteristic evaluation device 40 then performs a defect identification process on the semiconductor elements determined to be defective.

[0074] In this modification, defective semiconductor elements corresponding to the coordinates included in the defective area determined from the image data of the transmission polarization image are subjected to energization screening before packaging, thereby eliminating the waste of packaging defective elements.

[0075] This modification can be applied in combination with the semiconductor device inspection method according to the embodiment described in relation to Fig. 2. That is, for example, in steps S3 and S3a, the brightness threshold value of the defective area determined by the transmission polarization image processing device 14 may be set to two levels, and electrical screening may be applied to semiconductor elements corresponding to coordinates included in a low-brightness defective area, and electrical screening may not be applied to semiconductor elements corresponding to coordinates included in a high-brightness area, and the defective product identification process may be performed.

[0076] 1 is merely an example, and is not limited to this configuration as long as the semiconductor device inspection methods according to the embodiments and their modifications can be applied. For example, the storage device 60 may be connected to a control network, or each device may exchange data offline using a storage medium or the like. Furthermore, the image processing device may be an element that constitutes part of a transmission polarization inspection device, and the defect inspection device may have a separate image processing unit as part of the defect inspection device.

[0077] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other.

[0078] The embodiments include the following aspects.

[0079] (Appendix 1) providing a semiconductor substrate comprising silicon carbide; capturing a transmission polarization image of the semiconductor substrate using a transmission polarization image acquisition device and converting it into first image data in a predetermined format; a transmission polarization image processing device sets coordinates representing positions on the semiconductor substrate of each of a plurality of semiconductor elements formed on the semiconductor substrate in the first image data; performing image processing on the first image data using the transmission polarization image processing device, and determining and storing any one of the coordinates as a first defect coordinate when the brightness at any one of the plurality of coordinates is higher than a first brightness or when the brightness at any one of the plurality of coordinates is lower than a second brightness; forming an epitaxial layer on the semiconductor substrate; forming a plurality of semiconductor elements on the semiconductor substrate on which the epitaxial layer is formed; After forming the plurality of semiconductor elements, an electrical characteristic evaluation device is used to sequentially perform an electrical test on one of the remaining semiconductor elements corresponding to the remaining coordinates other than the first defect coordinates, based on predetermined electrical test conditions; a process for identifying a semiconductor element corresponding to the first defect coordinates as defective without performing the electrical test by the electrical characteristic evaluation device; If the electrical test determines that the semiconductor element is defective, a process is performed to identify the semiconductor element among the remaining semiconductor elements as defective, and if the electrical test determines that the semiconductor element is within specifications, the semiconductor element among the remaining semiconductor elements is moved to a next process. A method for inspecting a semiconductor device.

[0080] (Appendix 2) After forming the epitaxial layer on the semiconductor substrate and before forming the plurality of semiconductor elements, a photoluminescence image of the epitaxial substrate is captured by a defect inspection device and converted into second image data in a predetermined format; setting the plurality of coordinates in the second image data by the defect inspection device; image processing the second image data based on the photoluminescence intensities at the plurality of coordinates, and if an area on the substrate where the photoluminescence intensities at adjacent coordinates among the plurality of coordinates are all higher than a third predetermined value has an area larger than a fourth predetermined value, determining the area as a second defect area, and storing a plurality of coordinates among the plurality of coordinates included in the second defect area as second defect coordinates; A semiconductor device inspection method according to claim 1, wherein after forming the plurality of semiconductor elements, electrical testing using the electrical characteristic evaluation device is performed to identify the semiconductor elements corresponding to the plurality of second defect coordinates as defective without performing electrical testing.

[0081] (Appendix 3) 3. The semiconductor device inspection method according to claim 1, wherein the first luminance and the second luminance are calculated by processing the luminances at the plurality of coordinates using a statistical method.

[0082] (Appendix 4) providing a semiconductor substrate comprising silicon carbide; capturing a transmission polarization image of the semiconductor substrate using a transmission polarization image acquisition device and converting it into first image data in a predetermined format; using the transmission polarization image processing device to set a plurality of coordinates representing the positions of a plurality of semiconductor elements formed on the semiconductor substrate in the first image data; the transmitted polarization image processing device performs image processing on the first image data, and when an area on the substrate where the brightness at adjacent coordinates among the plurality of coordinates is all higher than a first predetermined value and the area is larger than a second predetermined value, or when an area on the substrate where the brightness at adjacent coordinates is all lower than the first predetermined value and the area is larger than the second predetermined value, the area on the substrate is determined to be a first defect area including a plurality of first defect coordinates, and the plurality of first defect coordinates are stored; forming an epitaxial layer on the semiconductor substrate; capturing a photoluminescence image of the epitaxial substrate using a defect inspection device and converting the image into second image data in a predetermined format; setting the plurality of coordinates in the second image data by the defect inspection device; image processing the second image data, and image processing the first image data based on the photoluminescence intensities at the plurality of coordinates, and if an area on the substrate where the photoluminescence intensities at adjacent coordinates among the plurality of coordinates are all higher than a third predetermined value has an area larger than a fourth predetermined value, determining the area as a second defect area, and storing a plurality of coordinates among the plurality of coordinates included in the second defect area as second defect coordinates; forming a plurality of semiconductor elements on the semiconductor substrate on which the epitaxial layer is formed; sequentially performing electrical testing on semiconductor elements other than the semiconductor element corresponding to the first defect coordinates or the second defect coordinates among the plurality of semiconductor elements by an electrical characteristic evaluation device based on preset electrical testing conditions; determining a semiconductor element corresponding to the second defect coordinates among the plurality of semiconductor elements as defective without performing the electrical inspection; for a semiconductor element among the plurality of semiconductor elements corresponding to the first defect coordinates, performing an electrical screening in which a current is continuously passed through a pn junction of the semiconductor element corresponding to the first defect coordinates, and then performing an electrical inspection using the electrical characteristic evaluation device to determine whether the semiconductor element is within specifications or defective; If the semiconductor element is determined to be defective, a process is performed to identify that the semiconductor element corresponding to the first defect coordinates is defective; If it is determined that the defect is within the standard, the semiconductor element corresponding to the first defect coordinates is moved to a next process. A method for inspecting a semiconductor device. [Explanation of symbols]

[0083] 10...Transmission polarization inspection device, 20...image processing device, 30...defect inspection equipment, 40...Electrical characteristic evaluation equipment, 50...control device, 60...Storage device, 100...Inspection system

Claims

1. providing a semiconductor substrate comprising silicon carbide; capturing a transmission polarization image of the semiconductor substrate using a transmission polarization image acquisition device and converting the image into first image data in a predetermined format; a transmission polarization image processing device is used to set coordinates representing positions on the semiconductor substrate of each of a plurality of semiconductor elements formed on the semiconductor substrate in the first image data; performing image processing on the first image data using the transmission polarization image processing device, and determining and storing any one of the coordinates as a first defect coordinate when the luminance at any one of the plurality of coordinates is higher than a first luminance or when the luminance at any one of the plurality of coordinates is lower than a second luminance; forming an epitaxial layer on the semiconductor substrate; forming a plurality of semiconductor elements on the semiconductor substrate on which the epitaxial layer is formed; After forming the plurality of semiconductor elements, an electrical characteristic evaluation device is used to sequentially perform an electrical test on one of the remaining semiconductor elements corresponding to the remaining coordinates other than the first defect coordinates, based on predetermined electrical test conditions; a process for identifying a semiconductor element corresponding to the first defect coordinates as defective without performing the electrical test by the electrical characteristic evaluation device; If the electrical test determines that the semiconductor element is defective, a process is performed to identify the semiconductor element among the remaining semiconductor elements as defective, and if the electrical test determines that the semiconductor element is within specifications, the semiconductor element among the remaining semiconductor elements is moved to a next process. A method for inspecting a semiconductor device.

2. After forming the epitaxial layer on the semiconductor substrate and before forming the plurality of semiconductor elements, a photoluminescence image of the epitaxial substrate is captured by a defect inspection device and converted into second image data in a predetermined format; setting the plurality of coordinates in the second image data by the defect inspection device; image processing the second image data based on the photoluminescence intensities at the plurality of coordinates, and if an area on the substrate where the photoluminescence intensities at adjacent coordinates among the plurality of coordinates are all higher than a third predetermined value has an area larger than a fourth predetermined value, determining the area as a second defect area, and storing a plurality of coordinates among the plurality of coordinates included in the second defect area as second defect coordinates; 2. A semiconductor device inspection method according to claim 1, wherein, after forming the plurality of semiconductor elements, electrical testing using the electrical characteristic evaluation device involves processing to identify the semiconductor elements corresponding to the plurality of second defect coordinates as defective without performing electrical testing.

3. 3. The semiconductor device inspection method according to claim 1, wherein the first luminance and the second luminance are calculated by processing the luminances at the plurality of coordinates using a statistical method.

4. providing a semiconductor substrate comprising silicon carbide; capturing a transmission polarization image of the semiconductor substrate using a transmission polarization image acquisition device and converting the image into first image data in a predetermined format; a plurality of coordinates representing positions of a plurality of semiconductor elements formed on the semiconductor substrate are set in the first image data by the transmission polarization image processing device; the transmitted polarization image processing device performs image processing on the first image data, and when an area on the substrate where the brightness at adjacent coordinates among the plurality of coordinates is all higher than a first predetermined value and the area is larger than a second predetermined value, or when an area on the substrate where the brightness at adjacent coordinates is all lower than the first predetermined value and the area is larger than the second predetermined value, the area on the substrate is determined to be a first defect area including a plurality of first defect coordinates, and the plurality of first defect coordinates are stored; forming an epitaxial layer on the semiconductor substrate; capturing a photoluminescence image of the epitaxial substrate using a defect inspection device and converting the image into second image data in a predetermined format; setting the plurality of coordinates in the second image data by the defect inspection device; image processing the second image data, and image processing the first image data based on the photoluminescence intensities at the plurality of coordinates, and if an area on the substrate where the photoluminescence intensities at adjacent coordinates among the plurality of coordinates are all higher than a third predetermined value has an area larger than a fourth predetermined value, determining the area as a second defect area, and storing a plurality of coordinates among the plurality of coordinates included in the second defect area as second defect coordinates; forming a plurality of semiconductor elements on the semiconductor substrate on which the epitaxial layer is formed; sequentially performing electrical inspections on semiconductor elements other than the semiconductor element corresponding to the first defect coordinates or the second defect coordinates among the plurality of semiconductor elements by an electrical characteristic evaluation device based on preset electrical inspection conditions; determining a semiconductor element corresponding to the second defect coordinates among the plurality of semiconductor elements as defective without performing the electrical inspection; for a semiconductor element among the plurality of semiconductor elements corresponding to the first defect coordinates, performing an electrical screening in which a current is continuously passed through a pn junction of the semiconductor element corresponding to the first defect coordinates, and then performing an electrical inspection using the electrical characteristic evaluation device to determine whether the semiconductor element is within specifications or defective; If the semiconductor element is determined to be defective, a process is performed to identify that the semiconductor element corresponding to the first defect coordinates is defective; If it is determined that the defect is within the standard, the semiconductor element corresponding to the first defect coordinates is moved to a next process. A method for inspecting a semiconductor device.

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