Neural network-based identification of poses of cameras

Abstract

To provide apparatuses, systems and techniques to identify a pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras.SOLUTION: In at least one embodiment, a pose of a camera for an image of a sequence of images is identified using one or more neural networks, based, at least in part, on one or more identified poses of the camera for one or more previous images of the sequence.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] At least one embodiment relates to processing resources used to implement and facilitate artificial intelligence for identifying camera poses. For example, at least one embodiment relates to a processor or computing system that uses a neural network to identify a camera pose based on one or more different poses of the camera. [Background technology]

[0002] Identifying the camera pose can use significant memory, time, or computing resources, and the camera pose identification can be inaccurate. Summary of the Invention [Problem to be solved by the invention]

[0003] The amount of memory, time, or computing resources used to identify the camera pose may be reduced, and the accuracy of the camera pose identification may be improved. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 is a logical block diagram of a camera pose classifier that implements neural network-based identification of camera pose, according to at least one embodiment. [Figure 2] FIG. 1 is a logical block diagram of a sequence of images in which camera poses are identified by one or more neural networks, according to at least one embodiment. [Figure 3] FIG. 1 is a diagram of a method for performing neural network-based identification of camera pose, according to at least one embodiment. [Figure 4] FIG. 1 is a diagram of a method for performing neural network-based identification of camera pose for a sequence of images, according to at least one embodiment. [Figure 5A] FIG. 1 illustrates logic according to at least one embodiment. [Figure 5B] FIG. 1 illustrates logic according to at least one embodiment. [Figure 6] FIG. 1 illustrates training and deployment of a neural network, according to at least one embodiment. [Figure 7] FIG. 1 illustrates an example data center system, according to at least one embodiment. [Figure 8A] FIG. 1 illustrates an example of an autonomous vehicle, according to at least one embodiment. [Figure 8B] 8B illustrates example camera locations and fields of view for the autonomous vehicle of FIG. 8A, according to at least one embodiment. [Figure 8C] FIG. 8B is a block diagram illustrating an example system architecture of the autonomous vehicle of FIG. 8A, according to at least one embodiment. [Figure 8D] FIG. 8B illustrates a system for communication between a cloud-based server and the autonomous vehicle of FIG. 8A, according to at least one embodiment. [Figure 9] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 10] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 11] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 12] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 13A] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 13B] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 13C] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 13D] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 13E]FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 13F] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 14] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 15A] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor according to at least one embodiment. [Figure 15B] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor according to at least one embodiment. [Figure 16A] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 16B] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 17] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 18A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 18B] FIG. 1 illustrates a partition unit, according to at least one embodiment. [Figure 18C] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 18D] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 19] FIG. 1 illustrates a multi-graphics processing unit (GPU) system according to at least one embodiment. [Figure 20] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 21] FIG. 1 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment. [Figure 22]FIG. 1 illustrates a deep learning application processor, according to at least one embodiment. [Figure 23] FIG. 1 is a block diagram illustrating an example neuromorphic processor, according to at least one embodiment. [Figure 24] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 25] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 26] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 27] FIG. 1 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment. [Figure 28] FIG. 1 is a block diagram of at least a portion of a graphics processor core, according to at least one embodiment. [Figure 29A] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 29B] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 30] FIG. 1 illustrates a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 31] FIG. 1 illustrates a general processing cluster (“GPC”), according to at least one embodiment. [Figure 32] FIG. 1 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 33] FIG. 1 illustrates a streaming multiprocessor, according to at least one embodiment. [Figure 34]FIG. 1 is an example data flow diagram for an advanced computing pipeline, according to at least one embodiment. [Figure 35] FIG. 1 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment. [Figure 36] A diagram including an example of an advanced computing pipeline 3510A for processing imaging data, according to at least one embodiment. [Figure 37A] FIG. 10 includes an example data flow diagram of a virtual instrument supporting an ultrasound device, according to at least one embodiment. [Figure 37B] FIG. 10 includes an example data flow diagram of a virtual instrument supporting a CT scanner, according to at least one embodiment. [Figure 38A] FIG. 1 is a data flow diagram of a process for training a machine learning model, according to at least one embodiment. [Figure 38B] FIG. 1 illustrates an example client-server architecture for extending annotation tools with pre-trained annotation models, according to at least one embodiment. [Figure 39] FIG. 1 is a diagram of components of a system for accessing large language models, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0005] 1 is a logical block diagram of a camera pose identifier that implements neural network-based identification of camera pose, according to at least one embodiment. In at least one embodiment, the camera pose identifier 100 can receive a sequence of images 102 and identify camera poses for different images in the sequence. In at least one embodiment, the sequence of images 102 can be received via a programmatic interface, such as an application programming interface (API). In at least one embodiment, the camera pose identifier 100 can implement another type of interface that can receive the sequence of images 102. In at least one embodiment, camera pose identifier 100 may include a current pose identifier 104. In at least one embodiment, current pose identifier 104 may receive as input a camera pose for one or more previous images (image 1 through image N-1) in a sequence of images 102 and, based at least in part on the input, identify a camera pose for image N 106 (the current image in the sequence of images 102). In at least one embodiment, in addition to the camera pose for one or more previous images in the sequence, current pose identifier 104 may also receive as input image N itself (the current image in the sequence of images 102) and identify a camera pose for image N 106. In at least one embodiment, in addition to the camera pose for one or more previous images (image 1 through image N-1) and / or current image N in a sequence, current pose identifier 104 may also receive as input any number of one or more previous images (image 1 through image N-1) and identify a camera pose for image N 106. For example, in at least one embodiment, current pose identifier 104 may also receive image 1 through image N-1 as input and identify the camera pose for image N 106. In at least one embodiment, current pose identifier 104 may receive the first image (image 1) in the sequence of images as input and identify the camera pose for image 1 (because there are no previous images in the sequence of images, there are no identified camera poses for the previous images to use as input for current pose identifier 104). In at least one embodiment, to identify the camera pose for an image, current pose identifier 104 may predict the camera pose using one or more neural networks.

[0006] In at least one embodiment, camera pose classifier 100 can identify a camera pose for different images in a sequence of images. For example, in at least one embodiment, camera pose classifier 100 can identify a camera pose trajectory representing different camera poses over time according to a sequence of images captured by a camera over time and received by camera pose classifier 100. For example, in at least one embodiment, camera pose classifier 100 can identify a camera pose trajectory from a given input video. For example, in at least one embodiment, camera pose classifier 100 receives a sequence of images (video frames) as input, and for each frame, camera pose classifier 100 can identify a transformation of the camera pose relative to the previous input image. In at least one embodiment, one or more neural networks implemented or used as part of camera pose classifier 100 are autoregressive, predicting the pose for a current frame (N) according to the pose predictions for previous frames (1 to N-1) as input feedback to the one or more neural networks. In at least one embodiment, one or more neural networks implemented or used as part of camera pose identifier 100 predict the pose of a current frame (N) of a video based on at least pose predictions of any number of previous frames (1 to N-1) and / or comparing the current frame (N) input to the one or more neural networks with any number of previous frames (1 to N-1) input to the one or more neural networks. In at least one embodiment, the one or more neural networks can be trained on a large corpus of video datasets, where each video in the video dataset is annotated with a ground truth camera pose label.

[0007] In at least one embodiment, current pose identifier 104 may generate as an output an identified camera pose for image N 106. In at least one embodiment, camera pose identifier 100 may store the camera pose for image N 106 as part of a data store of identified camera poses 108 for different images in sequence of images 102, such as a persistent data store using a block-based or other non-volatile storage device, or a non-persistent data store such as memory or other byte-addressable, volatile storage. In at least one embodiment, identified camera pose 108 stores the camera pose for each image in sequence of images 102 after current pose identifier 104 identifies each image.

[0008] In at least one embodiment, identifying a camera pose for an image in the sequence of images 102 may be repeated for any number of images in the sequence of images 102 to identify any number of corresponding camera poses. For example, in at least one embodiment, current pose identifier 104 may receive as input the camera poses for images 1 through N and identify the camera pose for image N+1 (the next image in the sequence of images 102). In at least one embodiment, camera pose identifier 100 may then store the camera pose for image N+1 as part of a data store of identified camera poses 108. In at least one embodiment, identifying the camera pose for a camera may be performed based on images provided by one or more other cameras for any number of cameras.

[0009] In at least one embodiment, the camera pose for an image can include information indicating the orientation and / or position of the camera that captured the image. In at least one embodiment, the camera pose for an image can include any number of values ​​that represent the orientation and / or position of the camera in three-dimensional space that captured the image. In at least one embodiment, the camera pose for an image can include any number of values ​​that represent the orientation and position of the camera that captured the image according to a coordinate system that maps to a three-dimensional space or volume that contains the camera, such as a world coordinate system.

[0010] In at least one embodiment, current pose identifier 104 may use or implement one or more machine learning models (e.g., one or more neural networks) that receive as input different camera poses for one or more previous images in a sequence of images (e.g., the camera pose for image 1 through the camera pose for image N-1) and apply generative artificial intelligence techniques to generate a camera pose for the current image (the camera pose for image N). In at least one embodiment, current pose identifier 104 may use or implement one or more machine learning models (e.g., one or more neural networks) that receive as input the camera poses for one or more previous images in a sequence, as well as the current image itself (image N), and apply artificial intelligence techniques to predict a camera pose for the current image relative to one or more previous camera poses predicted for the one or more previous images.

[0011] In at least one embodiment, current pose identifier 104 may include one or more of the techniques discussed in detail below with respect to FIGS. 2, 3, and 4 to identify the camera pose for an image. In at least one embodiment, for example, current pose identifier 104 may implement an autoregressive neural network and receive as input one or more prior predictions generated by the autoregressive neural network, allowing the autoregressive neural network to use a feed-forward technique to predict future values ​​based on past values. In at least one embodiment, the autoregressive neural network may be trained to apply one or more linear regression analyses to predict the camera pose for the current image according to the past camera pose predictions. In at least one embodiment, by using different camera poses of the camera for different images as input, the neural network may significantly increase the speed at which additional camera poses are identified for additional images while reducing computing resource utilization for identifying the additional camera poses.

[0012] 2 is a logical block diagram of a sequence of images for which camera poses are identified by one or more neural networks, according to at least one embodiment. In at least one embodiment, current pose identifier 104 may receive a sequence of images including image 1 202, image 2 204, and image 3 206. In at least one embodiment, current pose identifier 104 may identify a camera pose for each image in the sequence of images including image 1 202, image 2 204, and image 3 206. In at least one embodiment, current pose identifier 104 may include one or more neural networks used to identify a camera pose for each image in the sequence. In at least one embodiment, the sequence of images may include any number of images before image 1 202 and / or any number of images after image 3 206.

[0013] In at least one embodiment, current pose identifier 104 may identify a pose of one or more cameras based, at least in part, on any number of different poses of one or more cameras. For example, in at least one embodiment, current pose identifier 104 may identify a pose of the camera that captured image 3 206 based on previous identification of one or more different poses of the camera by current pose identifier 104. For example, in at least one embodiment, current pose identifier 104 may receive a pose for image 1 that was previously identified by current pose identifier 104, and current pose identifier 104 may receive another pose for image 2 that was previously identified by current pose identifier 104.

[0014] In at least one embodiment, the current pose identifier 104 can identify different poses of the camera for image 1 202, image 2 204, and image 3 206. For example, in at least one embodiment, the camera may be higher off the ground, tilted more forward, and tilted more to the right for image 2 204 compared to image 1 202. Similarly, the camera may be higher off the ground, tilted more forward, and tilted more to the right for image 3 206 compared to image 2 204. In at least one embodiment, changes in the location of objects between each of the images, such as changes in the location of the tent and the mountain, can be attributed to changes in the camera pose between each of the images.

[0015] In at least one embodiment, an input video (a sequence of images or video frames) may exhibit both large movements and / or dynamics of various objects in the scene of the input video and / or large movements of the camera that captured the input video. For example, in at least one embodiment, an input video including image 1 202, image 2 204, and image 3 206 may exhibit both large movements and / or dynamics of birds or other animals in the scene of the input video and / or large movements of the camera that captured the input video. In at least one embodiment, the one or more neural networks of current pose identifier 104 may be trained from a distribution of any number or types of video datasets, including real-world and / or "real-world" video datasets. In at least one embodiment, current pose identifier 104 may identify different camera poses for a scene of the input video without identifying the three-dimensional structure of the scene of the input video.

[0016] In at least one embodiment, the one or more neural networks of the current pose identifier 104 also label the current video frame or current image to indicate the identified pose of one or more cameras for the current video frame or current image. This may be performed for any number of video frames or images in the sequence of images or video frames received by the camera pose identifier 100 and / or the current pose identifier 104. In at least one embodiment, the labeled video frames or labeled images generated by the current pose identifier 104 may be used by the camera pose identifier 100 as training data for training one or more larger-scale foundation models (video-based models). In at least one embodiment, the labeled video frames or labeled images generated by the current pose identifier 104 may be sent to another system or endpoint where they may be used as training data for training one or more larger-scale foundation models (video-based models).

[0017] In at least one embodiment, an autonomous agent (e.g., an embodied AI such as a robot or vehicle) can use the identified camera pose to reliably localize itself in a dynamic, moving environment. For example, the autonomous agent may have one or more cameras and, in at least one embodiment, may include a system implementing camera pose identifier 100 to identify and provide poses for the one or more cameras. In at least one embodiment, the identified poses of the one or more cameras provided by camera pose identifier 100 for images captured by the one or more cameras may be more accurate, thereby improving the performance of many different image or video editing or generation techniques, including view synthesis of dynamic video capture.

[0018] Figure 3 is a diagram of a method for performing neural network-based identification of camera pose, according to at least one embodiment. In at least one embodiment, the method shown in Figure 3 can be implemented as part of the current pose identifier 104 described above with respect to Figure 1 and / or as various of the various embodiments of the systems, applications, services, or devices described below with respect to Figures 5A through 39. In at least one embodiment, as shown at 310, one or more different poses of one or more cameras can be obtained (received by one or more neural networks of the current pose identifier 104).

[0019] In at least one embodiment, one or more neural networks of current pose identifier 104 can be used to identify a pose of one or more cameras based, at least in part, on one or more different poses of one or more cameras, as shown at 320. In at least one embodiment, the one or more neural networks identify a pose of a given camera for an image captured by the given camera based, at least in part, on one or more different poses of the camera for one or more different images captured by the given camera. In at least one embodiment, one or more camera poses can be provided (provided by one or more neural networks of current pose identifier 104), as shown at 330.

[0020] Figure 4 is a diagram of a method for performing neural network-based identification of camera pose for a sequence of images, according to at least one embodiment. In at least one embodiment, the method shown in Figure 4 can be implemented as part of current pose identifier 104 or camera pose identifier 100 described above with respect to Figure 1 and / or as various of the various embodiments of systems, applications, services, or devices described below with respect to Figures 5A through 39.

[0021] In at least one embodiment, the one or more neural networks receive one or more poses of the camera previously identified by the one or more neural networks for one or more previous images of the sequence of images, as shown at 410. In at least one embodiment, the one or more neural networks identify a pose of the camera for a current image of the sequence based, at least in part, on the one or more poses of the camera previously identified by the one or more neural networks for one or more previous images of the sequence of images, as shown at 420.

[0022] In at least one embodiment, the one or more neural networks provide a camera pose for a current image in the sequence of images, as shown at 430. In at least one embodiment, the camera pose identifier 100 determines whether there is another image in the sequence of images to process. If there is another image to process, the process returns to 410, as shown at 440. If there is not another image to process, the identification of the camera pose for the sequence of images is complete, as shown at 450.

[0023] logic FIG. 5A illustrates logic 515, described in connection with elsewhere herein, that may be used in one or more devices to perform operations as discussed herein, according to at least one embodiment. In at least one embodiment, logic 515 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 515 is inference and / or training logic. More details regarding logic 515 are provided below in conjunction with FIG. 5A and / or FIG. 5B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide the functionality or operations described herein, and logic may be embodied, collectively or individually, as circuitry that forms part of a larger system, such as an integrated circuit (IC), a system-on-chip (SoC), or one or more processors (e.g., CPU, GPU).

[0024] In at least one embodiment, logic 515 may include, without limitation, code and / or data storage 501 for storing forward and / or output weights, and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used to infer in one or more embodiments. In at least one embodiment, logic 515 may include or be coupled to code and / or data storage 501 for storing graph code or other software for controlling the timing and / or sequence of logic loaded with weights and / or other parameter information, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code such as graph code loads weights or other parameter information into processor ALUs based on the architecture of the neural network to which such code corresponds. In at least one embodiment, code and / or data storage 501 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of the input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 501 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache, or system memory.

[0025] In at least one embodiment, any portion of code and / or data storage 501 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 501 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or code and / or data storage 501 is internal or external to a processor, for example, or whether it includes DRAM, SRAM, flash, or some other type of storage, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in neural network inference and / or training, or any combination of these factors.

[0026] In at least one embodiment, logic 515 may include, without limitation, code and / or data storage 505 for storing back and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, code and / or data storage 505 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments while backpropagating the input / output data and / or weight parameters during training and / or inference using one or more embodiments. In at least one embodiment, logic 515 may include or be coupled to code and / or data storage 505 for storing graph code or other software for controlling the timing and / or order into which weights and / or other parameter information are loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).

[0027] In at least one embodiment, code, such as graph code, loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 505 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 505 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 505 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 505 is internal or external to the processor, for example, or whether it includes DRAM, SRAM, flash memory, or some other type of storage, may depend on the storage available on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inferring and / or training the neural network, or any combination of these factors.

[0028] In at least one embodiment, code and / or data storage 501 and code and / or data storage 505 may be separate storage structures. In at least one embodiment, code and / or data storage 501 and code and / or data storage 505 may be combined storage structures. In at least one embodiment, code and / or data storage 501 and code and / or data storage 505 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data storage 501 and code and / or data storage 505 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0029] In at least one embodiment, logic 515 may include one or more arithmetic logic units (“ALUs”) 510, including, without limitation, integer and / or floating point units, for performing logical and / or arithmetic operations based at least in part on or indicated by training and / or inference code (e.g., graph code), the results of which may generate activations (e.g., output values ​​from layers or neurons in a neural network) stored in activation storage 520, which are functions of input / output and / or weight parameter data stored in code and / or data storage 501 and / or code and / or data storage 505. In at least one embodiment, the activations stored in activation storage 520 are generated according to linear algebra and / or matrix-based calculations performed by ALU 510 in response to executing instructions or other code, where weight values ​​stored in code and / or data storage 505 and / or data storage 501 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 505, code and / or data storage 501, and / or separate storage on-chip or off-chip.

[0030] In at least one embodiment, ALU 510 is included within one or more processors or other hardware logic devices or circuits, while in other embodiments, ALU 510 may be external to the processors or other hardware logic devices or circuits that use them (e.g., a coprocessor). In at least one embodiment, ALU 510 may be included within an execution unit of a processor, or within a bank of ALUs that are otherwise accessible by execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 501, code and / or data storage 505, and activation storage 520 may share processors or other hardware logic devices or circuits, while in other embodiments, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same processor or other hardware logic devices or circuits and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 520 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry, and may be fetched and / or processed using the processor's fetch, decode, schedule, execute, retire, and / or other logic.

[0031] In at least one embodiment, activation storage 520 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 520 may be completely or partially internal to or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 520 is internal or external to a processor, for example, or whether it includes DRAM, SRAM, flash memory, or some other type of storage, may depend on available on-chip versus off-chip storage, latency requirements of the training and / or inference functions being performed, batch sizes of data used in inference and / or training of the neural network, or any combination of these factors.

[0032] In at least one embodiment, the logic 515 shown in Figure 5A may be used in conjunction with an application-specific integrated circuit ("ASIC"), such as Google's TensorFlow® processing unit, Graphcore™'s inference processing unit (IPU), or Intel Corp.'s Nervana® (e.g., "Lake Crest") processor. In at least one embodiment, the logic 515 shown in Figure 5A may also be used in conjunction with other hardware, such as central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or a field programmable gate array ("FPGA").

[0033] FIG. 5B illustrates logic 515, according to at least one embodiment. In at least one embodiment, logic 515 is inference and / or training logic. In at least one embodiment, logic 515 may include, without limitation, hardware logic in which computational resources are dedicated to, or otherwise used only in conjunction with, weight values ​​or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, logic 515 shown in FIG. 5B may be used in conjunction with an application-specific integrated circuit (ASIC), such as Google's TensorFlow® processing unit, Graphcore™'s inference processing unit (IPU), or Intel Corp.'s Nervana® (e.g., "Lake Crest") processor. In at least one embodiment, logic 515 shown in FIG. 5B may be used in conjunction with other hardware, such as central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or field-programmable gate arrays (FPGAs). In at least one embodiment, logic 515 includes, without limitation, code and / or data storage 501 and code and / or data storage 505, which may be used to store code (e.g., graph code), weight and / or bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment illustrated in FIG. 5B , each of code and / or data storage 501 and code and / or data storage 505 is associated with dedicated computational resources, such as computation hardware 502 and computation hardware 506, respectively. In at least one embodiment, computation hardware 502 and computation hardware 506 each include one or more ALUs that perform mathematical functions, such as linear algebraic functions, solely on the information stored in code and / or data storage 501 and code and / or data storage 505, respectively, with the results stored in activation storage 520.

[0034] In at least one embodiment, each of code and / or data storage 501 and 505 and corresponding computational hardware 502 and 506 corresponds to a different layer of a neural network, such that activations resulting from one storage / computation pair 501 / 502, between code and / or data storage 501 and computational hardware 502, are provided as input to a storage / computation pair 505 / 506, between the next code and / or data storage 505 and computational hardware 506, to reflect the conceptual organization of the neural network. In at least one embodiment, each of storage / computation pairs 501 / 502 and 505 / 506 may correspond to two or more layers of the neural network. In at least one embodiment, additional storage / computation pairs (not shown) may be included in logic 515 after or in parallel with storage / computation pairs 501 / 502 and 505 / 506.

[0035] Neural network training and deployment FIG. 6 illustrates the training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an untrained neural network 606 is trained using a training dataset 602. In at least one embodiment, the training framework 604 is the PyTorch framework, while in other embodiments, the training framework 604 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 604 trains the untrained neural network 606 and enables it to be trained using processing resources described herein to generate a trained neural network 608. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training may be performed in a supervised, semi-supervised, or unsupervised manner.

[0036] In at least one embodiment, the untrained neural network 606 is trained using supervised learning, where the training dataset 602 includes inputs paired with desired outputs, or the training dataset 602 includes inputs with known outputs, and the outputs of the neural network 606 are manually scored. In at least one embodiment, the untrained neural network 606 is trained in a supervised manner, processing inputs from the training dataset 602 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through the untrained neural network 606. In at least one embodiment, the training framework 604 adjusts the weights that control the untrained neural network 606. In at least one embodiment, the training framework 604 includes tools to monitor how well the untrained neural network 606 is converging toward a model, such as the trained neural network 608, that is suitable for generating correct answers, such as in the results 614, based on input data, such as the new dataset 612. In at least one embodiment, the training framework 604 iteratively trains the untrained neural network 606 while adjusting weights to refine the output of the untrained neural network 606 using a loss function and a tuning algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 604 trains the untrained neural network 606 until the untrained neural network 606 reaches a desired accuracy. In at least one embodiment, the trained neural network 608 can then be deployed to implement any number of machine learning operations.

[0037] In at least one embodiment, the untrained neural network 606 is trained using unsupervised learning, where the untrained neural network 606 attempts to train itself using unlabeled data. In at least one embodiment, the training dataset 602 for unsupervised learning includes input data without any associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 606 can learn groupings within the training dataset 602 and determine how individual inputs relate to the untrained dataset 602. In at least one embodiment, unsupervised training can be used within the trained neural network 608 to generate self-organizing maps, which can perform operations useful for reducing the dimensionality of the new dataset 612. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the new dataset 612 that deviate from the normal patterns of the new dataset 612.

[0038] In at least one embodiment, semi-supervised learning may be used, which is a technique in which the training dataset 602 includes a mixture of labeled and unlabeled data. In at least one embodiment, the training framework 604 may be used to perform incremental learning, such as by transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 608 to adapt to a new dataset 612 without forgetting knowledge instilled in the trained neural network 608 during initial training.

[0039] In at least one embodiment, training framework 604 is a framework operated in conjunction with a software development toolkit, such as the OpenVINO (Open Visual Inference and Neural network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit, such as a toolkit developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes or uses logic 515 to perform the operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0040] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications, particularly neural network applications, for a variety of tasks and operations, such as human vision emulation, speech recognition, natural language processing, suggestion systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports a variety of software libraries, such as OpenCV, OpenCL, and / or variations thereof.

[0041] In at least one embodiment, OpenVINO supports neural network models for a variety of tasks and operations, including classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., human and / or object), monocular depth estimation, image inpainting, style transfer, action recognition, colorization, and / or transformations thereof.

[0042] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of neural network models. In at least one embodiment, the model optimizer optimizes neural network models for execution on various devices and / or processing units, such as GPUs, CPUs, PPUs, GPGPUs, and / or variations thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers of the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying inputs to the model (e.g., resizing inputs to the model), modifying the size of inputs to the model (e.g., modifying the batch size of the model), modifying the model structure (e.g., modifying the layers of the model), normalizing, standardizing, quantizing (e.g., converting model weights from a first representation, such as a decimal point, to a second representation, such as an integer), and / or transforming thereof.

[0043] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or a library in any suitable programming language. In at least one embodiment, the inference engine is utilized to infer input data. In at least one embodiment, the inference engine implements various classes to infer the input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process the intermediate representation, set input and / or output formats, and / or execute the model on one or more devices.

[0044] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems utilizing one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions for executing a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions for executing a program and / or portions of a program on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, for executing a first portion of code on a CPU and a second portion of the code on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions for executing one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).

[0045] In at least one embodiment, OpenVINO includes various functionality similar to functionality associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variants thereof. In at least one embodiment, one or more CUDA programming model operations are executed using OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0046] Data Center 7 illustrates an example data center 700 in which at least one embodiment may be used. In at least one embodiment, the data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0047] 7, in at least one embodiment, data center infrastructure layer 710 may include a resource orchestrator 712, grouped computing resources 714, and node computing resources (“node CRs”) 716(1) through 716(N), where “N” represents a positive integer (although “N” may be a different integer than that used in other figures). In at least one embodiment, node CRs 716(1) through 716(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 718(1) through 718(N) (e.g., dynamic read-only memory, solid-state storage drives, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules. In at least one embodiment, one or more of nodes CR 716(1)-716(N) may be a server having one or more of the computing resources described above.

[0048] In at least one embodiment, grouped computing resources 714 may include separate groups of node CRs housed within one or more racks (not shown), or multiple racks housed in a data center at various geographic locations (also not shown). In at least one embodiment, separate groups of node CRs within grouped computing resources 714 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power supply modules, cooling modules, and network switches in any combination.

[0049] In at least one embodiment, resource orchestrator 712 may configure or otherwise control one or more nodes CR 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource orchestrator 712 may include a software design infrastructure (“SDI”) management entity for data center 700. In at least one embodiment, resource orchestrator 512 may include hardware, software, or some combination thereof.

[0050] As shown in FIG. 7 , in at least one embodiment, framework layer 720 includes job scheduler 722, configuration manager 724, resource manager 726, and distributed file system 728. In at least one embodiment, framework layer 720 may include frameworks to support software 732 in software layer 730 and / or one or more applications 742 in application layer 740. In at least one embodiment, software 732 or applications 742 may each include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 720 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark® (hereinafter “Spark”), which can use distributed file system 728 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 722 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 700. In at least one embodiment, configuration manager 724 may be capable of configuring different tiers, such as software tier 730, as well as framework tier 720, which includes Spark and distributed file system 728 to support large-scale data processing. In at least one embodiment, resource manager 726 may be capable of managing clustered or grouped computing resources that are mapped or allocated to support distributed file system 728 and job scheduler 722. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 714 in data center infrastructure tier 710.In at least one embodiment, resource manager 726 may manage these mappings or allocated computing resources in conjunction with resource orchestrator 712.

[0051] In at least one embodiment, software 732 included in software layer 730 may include software used by nodes CR 716(1)-716(N), grouped computing resources 714, and / or at least a portion of distributed file system 728 of framework layer 720. In at least one embodiment, the one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0052] In at least one embodiment, the applications 742 included in the application layer 740 may include one or more types of applications used by at least a portion of the nodes CR 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 728 of the framework layer 720. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute, and applications including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), and machine learning applications, or other machine learning applications used in conjunction with one or more embodiments.

[0053] In at least one embodiment, any of configuration manager 724, resource manager 726, and resource orchestrator 712 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may prevent data center operators of data center 700 from making potentially bad configuration decisions and from potentially avoiding underutilized and / or poorly performing portions of the data center.

[0054] In at least one embodiment, data center 700 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, machine learning models may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 700. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 700 by using weight parameters calculated by one or more techniques described herein.

[0055] In at least one embodiment, the data center may use a CPU, application specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Additionally, one or more of the software and / or hardware resources described above may be configured as a service to enable a user to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0056] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, logic 515 may be used in data center 700 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0057] In at least one embodiment, at least one embodiment of Figures 5A, 5B, 6, and / or 7 may include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify a pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to Figures 1-4.

[0058] Autonomous Vehicles 8A illustrates an example of an autonomous vehicle 800 according to at least one embodiment. In at least one embodiment, autonomous vehicle 800 (alternatively referred to herein as "vehicle 800") may be a passenger vehicle, such as, without limitation, a car, truck, bus, and / or another type of vehicle that accommodates one or more occupants. In at least one embodiment, vehicle 800 may be a semi-tractor trailer truck used for hauling cargo. In at least one embodiment, vehicle 800 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0059] Autonomous vehicles may be described in terms of levels of automation as defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, issued June 15, 2018, Standard No. J3016-201609, issued September 30, 2016, and previous and new versions of this standard). In at least one embodiment, vehicle 800 may be capable of functionality according to one or more of Levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 800 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0060] In at least one embodiment, vehicle 800 may include components such as, without limitation, a chassis, a vehicle body, wheels (2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 800 may include a propulsion system 850 such as, without limitation, an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 850 may be coupled to a drive train of vehicle 800, which may include, without limitation, a transmission to enable propulsion of vehicle 800. In at least one embodiment, propulsion system 850 may be controlled in response to receiving a signal from throttle / accelerator 852.

[0061] In at least one embodiment, steering system 854, which may include without limitation a steering wheel, is used to steer vehicle 800 (e.g., along a desired path or route) when propulsion system 850 is operating (e.g., when vehicle 800 is moving). In at least one embodiment, steering system 854 may receive signals from steering actuator 856. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 846 may be used to operate vehicle brakes in response to receiving signals from brake actuator 848 and / or brake sensor.

[0062] In at least one embodiment, controller 836, which may include, without limitation, one or more systems on a chip (“SoC”) (not shown in FIG. 8A ) and / or graphics processing units (“GPUs”), provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 800. For example, in at least one embodiment, controller 836 may send signals to operate vehicle brakes via brake actuator 848, to operate steering system 854 via steering actuator 856, and to operate propulsion system 850 via throttle / accelerator 852. In at least one embodiment, controller 836 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 800. In at least one embodiment, controller 836 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functionalities, two or more controllers may handle a single functionality, and / or some combination thereof.

[0063] In at least one embodiment, controller 836 provides signals to control one or more components and / or systems of vehicle 800 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, sensor data may be received from, for example, without limitation, global navigation satellite system (“GNSS”) sensors 858 (e.g., global positioning system sensors), RADAR sensors 860, ultrasonic sensors 862, LIDAR sensors 864, inertial measurement unit (“IMU”) sensors 866 (e.g., accelerometers, gyroscopes, magnetic compasses, magnetometers, etc.), microphones 896, stereo cameras 868, wide-angle cameras 870 (e.g., fisheye cameras), infrared cameras 872, ambient cameras 874 (e.g., 360-degree cameras), long-range cameras (not shown in FIG. 8A ), mid-range cameras (not shown in FIG. 8A ), speed sensors 844 (e.g., for measuring the speed of vehicle 800), vibration sensors 842, steering sensors 840, brake sensors (e.g., as part of brake sensor system 846), and / or other types of sensors.

[0064] In at least one embodiment, one or more of controllers 836 may receive input (e.g., represented by input data) from instrument cluster 832 of vehicle 800 and provide output (e.g., represented by output data, display data, etc.) via human-machine interface (“HMI”) display 834, audible annunciators, loudspeakers, and / or via other components of vehicle 800. In at least one embodiment, the output may include vehicle speed, velocity, time, map data (e.g., a high-resolution map (not shown in FIG. 8A )), position data (e.g., the position of vehicle 800 on a map, etc.), direction, the positions of other vehicles (e.g., occupancy grid), information about objects and object statuses perceived by controller 836, etc. For example, in at least one embodiment, HMI display 834 may display information regarding the presence of one or more objects (e.g., road signs, caution signs, changing traffic signals, etc.) and / or information regarding a driving maneuver that the vehicle has performed, is performing, or will perform (e.g., changing lanes now, taking exit 34B in 2 miles).

[0065] In at least one embodiment, vehicle 800 further includes a network interface 824, which may use a wireless antenna 826 and / or a modem for communicating over one or more networks. For example, in at least one embodiment, network interface 824 may be capable of communicating over a Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") network, etc. In at least one embodiment, the wireless antenna 826 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area network protocols such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee, etc., and / or low power wide-area network (“LPWAN”) protocols such as LoRaWAN, SigFox, etc.

[0066] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, logic 515 may be used in vehicle 800 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0067] In at least one embodiment, the embodiment of FIG. 8A can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify the pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0068] 8B illustrates example camera locations and fields of view for autonomous vehicle 800 of FIG. 8A according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are an example example and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be positioned at different locations on vehicle 800.

[0069] In at least one embodiment, the camera type may include, but is not limited to, a digital camera that may be adapted for use with components and / or systems of vehicle 800. In at least one embodiment, the camera may operate at Automotive Safety Integrity Level (“ASIL”) B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor ("RGGB") color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a clear pixel camera may be used, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, to increase light sensitivity.

[0070] In at least one embodiment, one or more of the cameras may be used to perform advanced driver assistance systems ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all of the cameras) may simultaneously record and provide image data (e.g., video).

[0071] In at least one embodiment, one or more cameras may be mounted on a mounting assembly, such as a custom-designed (e.g., three-dimensionally (“3D”) printed) assembly, to eliminate stray light and reflections from inside the vehicle 800 (e.g., reflections reflected from the dashboard onto the windshield mirror) that may interfere with the camera's image data capture capabilities. With reference to door mirror mounting assemblies, in at least one embodiment, the door mirror assembly may be custom 3D printed so that the camera mounting plate matches the shape of the door mirror. In at least one embodiment, the camera may be integral with the door mirror. In at least one embodiment, for side view cameras, the cameras may also be integrated into the four pillars at each corner of the cabin.

[0072] In at least one embodiment, a camera (e.g., a front-facing camera) having a field of view that includes a portion of the environment ahead of vehicle 800 may be used for a surroundings view to facilitate identification of the forward path and obstacles, and may be used in conjunction with controller 836 and / or one or more of the control SoCs to assist in providing information essential for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the front-facing camera may be used to perform many ADAS functions similar to LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front-facing camera may also be used for ADAS features and systems, including, without limitation, other features such as lane departure warnings ("LDW"), autonomous cruise control ("ACC"), and / or traffic sign recognition.

[0073] In at least one embodiment, various cameras may be used in a front-facing configuration, including, for example, a monocular camera platform including a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 870 may be used to sense objects (e.g., pedestrians, cross traffic, or bicycles) coming into view from the periphery. While only one wide-angle camera 870 is shown in FIG. 8B , in other embodiments, there may be any number (including zero) of wide-angle cameras on the vehicle 800. In at least one embodiment, any number of long-range cameras 898 (e.g., a pair of long-view stereo cameras) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range cameras 898 may also be used for object detection and classification, as well as basic object tracking.

[0074] In at least one embodiment, any number of stereo cameras 868 may also be included in a front-facing configuration. In at least one embodiment, one or more stereo cameras 868 may include an integrated control unit with a scalable processing unit, which may provide a programmable gate array ("FPGA") and a multi-core microprocessor with an integrated controller area network ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 800 environment, including distance estimates for all points in the image. In at least one embodiment, one or more of the stereo cameras 868 may include, without limitation, a compact stereo vision sensor, which may include, without limitation, two camera lenses (one on each side) and an image processing chip that can measure the distance from the vehicle 800 to target objects and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning features. In at least one embodiment, other types of stereo cameras 868 may be used in addition to or instead of those described herein.

[0075] In at least one embodiment, cameras having a field of view that includes a portion of the environment to the sides of vehicle 800 (e.g., side view cameras) may be used for the surroundings view to provide information used to create and update the occupancy grid and generate side collision warnings. For example, in at least one embodiment, surrounding cameras 874 (e.g., four surrounding cameras as shown in FIG. 8B ) may be disposed on vehicle 800. In at least one embodiment, surrounding cameras 874 may include, without limitation, any number and combination of wide-angle cameras, fisheye cameras, 360-degree cameras, and / or the like. For example, in at least one embodiment, four fisheye cameras may be disposed in front, behind, and on the sides of vehicle 800. In at least one embodiment, vehicle 800 may use three surrounding cameras 874 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a front camera) as a fourth surrounding camera.

[0076] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind vehicle 800 (e.g., a rear view camera) may be used for parking assistance, surrounding view, rear collision warning, and to create and update the occupancy grid. In at least one embodiment, a variety of cameras may be used, including, but not limited to, cameras that are also suitable as front cameras described herein (e.g., long-range camera 898 and / or mid-range camera 876, stereo camera 868, infrared camera 872, etc.).

[0077] In at least one embodiment, at least one embodiment of FIG. 8B can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify the pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0078] FIG. 8C is a block diagram illustrating an example system architecture of the autonomous vehicle 800 of FIG. 8A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 800 of FIG. 8C is illustrated as being connected via a bus 802. In at least one embodiment, the bus 802 may include, without limitation, a CAN data interface (alternatively referred to herein as a “CAN bus”). In at least one embodiment, the CAN may be a network within the vehicle 800 used to assist in controlling various features and functionality of the vehicle 800, such as brake application, acceleration, braking, steering, wipers, etc. In at least one embodiment, the bus 802 may be configured to have tens or hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 802 may be read to determine steering wheel angle, ground speed, engine revolutions per minute (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 802 may be an ASIL B compliant CAN bus.

[0079] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, there may be any number of buses forming bus 802, including, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or to provide redundancy. For example, a first bus may be used for collision avoidance functions and a second bus may be used for actuation control. In at least one embodiment, each bus of bus 802 may communicate with one of the components of vehicle 800, and two or more of buses of bus 802 may communicate with corresponding components. In at least one embodiment, each of any number of systems-on-chip (“SoC”) 804 (e.g., SoC 804(A) and SoC 804(B)), each of controllers 836, and / or each computer in the vehicle may have access to the same input data (e.g., input from sensors in vehicle 800) and may be connected to a common bus, such as a CAN bus.

[0080] In at least one embodiment, vehicle 800 may include one or more controllers 836, such as those described herein with respect to FIG. 8A . In at least one embodiment, controller 836 may be used for a variety of functions. In at least one embodiment, controller 836 may be coupled to any of a variety of other components and systems of vehicle 800 and may be used to control vehicle 800, artificial intelligence of vehicle 800, infotainment and / or other functions of vehicle 800.

[0081] In at least one embodiment, vehicle 800 may include any number of SoCs 804. In at least one embodiment, each of SoCs 804 may include, without limitation, a central processing unit ("CPU") 806, a graphics processing unit ("GPU") 808, a processor 810, a cache 812, an accelerator 814, a data store 816, and / or other components and features not shown. In at least one embodiment, SoCs 804 may be used to control vehicle 800 in a variety of platforms and systems. For example, in at least one embodiment, SoC 804 may be incorporated into a system (e.g., that of vehicle 800) having a high definition ("HD") map 822 that can obtain map refreshes and / or updates via a network interface 824 from one or more servers (not shown in FIG. 8C ).

[0082] In at least one embodiment, CPU 806 may include a CPU cluster, or CPU complex (also referred to herein as a "CCPLEX"). In at least one embodiment, CPU 806 may include multiple cores and / or level 2 ("L2") caches. For example, in at least one embodiment, CPU 806 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU 806 may include four dual-core clusters, where each cluster has a dedicated L2 cache (e.g., 2 megabytes (MB) of L2 cache). In at least one embodiment, CPU 806 (e.g., a CCPLEX) may be configured to support simultaneous cluster operation, allowing any combination of clusters of CPUs 806 to be active at any given time.

[0083] In at least one embodiment, one or more of the CPUs 806 may implement power management functionality, including, without limitation, one or more of the following features: individual hardware blocks may be automatically clock gated when idle to save dynamic power; each core clock may be gated when such core is not actively executing instructions due to execution of a Wait for Interrupt ("WFI") / Wait for Event ("WFE") instruction; each core may be independently power gated; when all cores are clock gated or power gated, each core cluster may be independently clock gated; and / or when all cores are power gated, each core cluster may be independently power gated. In at least one embodiment, the CPUs 806 may further implement an advanced algorithm for managing power states, where, given allowed power states and expected wake-up times, hardware / microcode determines what the best power state for cores, clusters, and CCPLEXes to enter is. In at least one embodiment, a processing core may support in software a simple sequence of entering power states, with work offloaded to microcode.

[0084] In at least one embodiment, GPU 808 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU 808 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU 808 may use an extended tensor instruction set. In at least one embodiment, GPU 808 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 (“L1”) cache (e.g., an L1 cache having at least 96 KB of storage capacity) and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512 KB of storage capacity). In at least one embodiment, GPU 808 may include at least eight streaming microprocessors. In at least one embodiment, GPU 808 may use a compute application programming interface (API). In at least one embodiment, GPU 808 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0085] In at least one embodiment, one or more of the GPUs 808 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, the GPUs 808 may be fabricated on Fin field-effect transistor ("FinFET") circuitry. In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, without limitation, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix operations, a level-zero ("L0") instruction cache, a scheduler (e.g., warp scheduler) or sequencer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to achieve efficient execution of workloads by mixing computational and addressing calculations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling to enable finer-grained synchronization and coordination between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0086] In at least one embodiment, one or more of the GPUs 808 may include high bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem, providing, in some instances, a peak memory bandwidth of approximately 900 GB / s. In at least one embodiment, synchronous graphics random-access memory (“SGRAM”), such as graphics double data rate type five (“GDDR5”), may be used in addition to or in place of the HBM memory.

[0087] In at least one embodiment, GPU 808 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow GPU 808 to directly access the page tables of CPU 806. In at least one embodiment, when the GPU 808 memory management unit ("MMU") experiences a GPU miss, an address translation request may be sent to CPU 806. In at least one embodiment, in response, two of CPUs 806 may look up the virtual-to-physical address mapping in their own page tables and send the translation back to GPU 808. In at least one embodiment, unified memory technology may enable a single, unified virtual address space for both CPU 806 and GPU 808 memory, thereby simplifying programming of GPU 808 and porting applications to GPU 808.

[0088] In at least one embodiment, GPU 808 may include any number of access counters that can record the frequency of GPU 808's accesses to the memory of other processors. In at least one embodiment, the access counters may help ensure that memory pages are moved to the physical memory of the processor that is accessing the pages most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0089] In at least one embodiment, one or more of the SoCs 804 may include any number of caches 812, including those described herein. For example, in at least one embodiment, the caches 812 may include a level 3 (“L3”) cache available to both the CPU 806 and the GPU 808 (e.g., connected to the CPU 806 and the GPU 808). In at least one embodiment, the caches 812 may include a write-back cache that can record line state by using a cache coherence protocol or the like (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB of memory or more, depending on the embodiment, although smaller cache sizes may also be used.

[0090] In at least one embodiment, one or more of the SoCs 804 may include one or more accelerators 814 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoCs 804 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4 MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to complement the GPU 808 and offload some of the GPU 808's tasks (e.g., freeing up more cycles for the GPU 808 to perform other tasks). In at least one embodiment, the accelerators 814 may be used for targeted workloads that are stable enough to accept acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, the CNN may include a region-based, i.e., regional convolutional neural network (“RCNN”), and Faster RCNN (e.g., used for object detection), or other types of CNN.

[0091] In at least one embodiment, accelerator 814 (e.g., a hardware-accelerated cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, the DLAs may include, without limitation, one or more tensor processing units (“TPUs”), which may be further configured to provide tens of trillions of operations per second for deep learning applications and inference. In at least one embodiment, the TPUs may be accelerators configured and optimized to perform image processing functions (e.g., CNN, RCNN, etc.). In at least one embodiment, the DLAs may be further optimized for a specific set of neural network types and floating-point operations, as well as for inference. In at least one embodiment, the design of the DLAs allows for improved performance per millimeter over typical general-purpose GPUs, and typically greatly exceeds the performance of CPUs. In at least one embodiment, the TPU may perform several functions, including, for example, single-instance convolution functions supporting INT8, INT16, and FP16 data types for both features and weights, as well as post-processor functions. In at least one embodiment, the DLA may quickly and efficiently run neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, without limitation, CNNs for object identification and detection using data from a camera sensor, CNNs for distance estimation using data from a camera sensor, CNNs for emergency vehicle detection and identification using data from a microphone, CNNs for face recognition and vehicle owner identification using data from a camera sensor, and / or CNNs for security and / or safety events.

[0092] In at least one embodiment, the DLA may perform any function of the GPU 808, and a designer may target either the DLA or the GPU 808 for any function, for example, by using an inference accelerator. For example, in at least one embodiment, a designer may centralize CNN and floating-point processing in the DLA and offload other functions to the GPU 808 and / or accelerator 814.

[0093] In at least one embodiment, accelerator 814 may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 838, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVA may provide a balance between performance and versatility. For example, in at least one embodiment, each PVA may include, by way of example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”) processors, and / or any number of vector processors.

[0094] In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a number of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0095] In at least one embodiment, the DMA may allow components of the PVA to access system memory independent of the CPU 806. In at least one embodiment, the DMA may support any number of features used to provide optimizations to the PVA, including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0096] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripheral devices. In at least one embodiment, the vector processing subsystem may operate as the primary processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core may include a digital signal processor, such as a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0097] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of the vector processors may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance the overall security of the system.

[0098] In at least one embodiment, the accelerator 814 may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the accelerator 814. In at least one embodiment, the on-chip memory may include, for example, without limitation, at least 4 MB of SRAM including eight field-configurable memory blocks, which may be accessible by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory through a backbone that provides the PVA and DLA with high-speed access to the memory. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using the APB).

[0099] In at least one embodiment, the on-chip computer vision network may include an interface that determines whether both the PVA and DLA provide ready and enable signals before transmitting any control signals, addresses, or data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals, addresses, and data, as well as burst-based communication for continuous data transfer. In at least one embodiment, the interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0100] In at least one embodiment, one or more of the SoCs 804 may include a real-time ray tracing hardware accelerator that may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, sound propagation synthesis and / or analysis, SONAR system simulation, general waveform propagation simulation, comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0101] In at least one embodiment, accelerator 814 can have diverse uses for autonomous driving. In at least one embodiment, PVAs can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, PVA performance is well suited to algorithm domains that require low-power, low-latency, and predictable processing. In other words, PVAs perform well even with small data sets for semi-dense or dense regular computations that may require low-latency, low-power, and predictable runtimes. In at least one embodiment, PVAs can be designed to run classic computer vision algorithms, such as in vehicle 800, because they can be effective for object detection and integer arithmetic.

[0102] For example, according to at least one embodiment of the technology, computer stereo vision may be performed using the PVA. In at least one embodiment, algorithms based on semi-global matching may be used in some instances, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereo vision functions on input from two monocular cameras.

[0103] In at least one embodiment, the PVA may be used to perform dense optical flow. For example, in at least one embodiment, the PVA may process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA may be used for time-of-flight depth processing, e.g., by processing raw time-of-flight data to provide processed time-of-flight data.

[0104] In at least one embodiment, the DLA may be used to implement any type of network for enhancing control and driving safety, including, for example, without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be expressed or interpreted as the probability of each detection compared to other detections or as providing its relative “weight.” In at least one embodiment, the confidence measure may further enable the system to make decisions regarding which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system may set a threshold for confidence and consider only detections above the threshold to be true positive detections. In embodiments where an automatic emergency braking (“AEB”) system is used, a false positive detection may cause the vehicle to automatically apply emergency braking, which is clearly undesirable. In at least one embodiment, a highly confident detection may be considered an AEB trigger. In at least one embodiment, the DLA may implement a neural network to regress the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground surface estimate obtained (e.g., from another subsystem), an output from an IMU sensor 866 that correlates with the orientation of the vehicle 800, distance, and a 3D location estimate of the object obtained from the neural network and / or other sensors (e.g., a LIDAR sensor 864 or a RADAR sensor 860), among others.

[0105] In at least one embodiment, one or more of the SoCs 804 may include a data store 816 (e.g., memory). In at least one embodiment, the data store 816 may be on-chip memory of the SoCs 804, which may store neural networks running on the GPUs 808 and / or DLAs. In at least one embodiment, the capacity of the data store 816 may be large enough to store multiple instances of the neural networks for redundancy and safety. In at least one embodiment, the data store 816 may comprise an L2 or L3 cache.

[0106] In at least one embodiment, one or more of the SoCs 804 may include any number of processors 810 (e.g., embedded processors). In at least one embodiment, the processors 810 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC 804 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in transitioning the system to a low power state, manage the thermal and temperature sensors of the SoC 804, and / or manage the power state of the SoC 804. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC 804 may use the ring oscillator to detect the temperature of the CPU 806, the GPU 808, and / or the accelerator 814. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine, place the SoC 804 in a low power state, and / or place the vehicle 800 in a driver-safety shutdown mode (e.g., bring the vehicle 800 to a safety shutdown).

[0107] In at least one embodiment, processor 810 may further include a set of embedded processors capable of acting as an audio processing engine, which may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces and a wide variety of flexible audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0108] In at least one embodiment, processor 810 may further include an always-on processor engine capable of providing the hardware features necessary to support low-power sensor management and bring-up use cases. In at least one embodiment, the always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0109] In at least one embodiment, the processor 810 may further include a safety cluster engine, which may include, without limitation, a processor subsystem dedicated to addressing safety management for automotive applications. In at least one embodiment, the safety cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, in at least one embodiment, two or more cores may operate in lockstep mode and function as a single core with comparison logic to detect any differences between their operation. In at least one embodiment, the processor 810 may further include a real-time camera engine, which may include, without limitation, a processor subsystem dedicated to addressing real-time camera management. In at least one embodiment, the processor 810 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0110] In at least one embodiment, processor 810 may include a video image composer, which may be a processing block (e.g., implemented in a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image in a playback device window. In at least one embodiment, the video image composer may perform lens distortion correction for wide-angle camera 870, surrounding camera 874, and / or in-cabin surveillance camera sensors. In at least one embodiment, the in-cabin surveillance camera sensors are preferably monitored by a neural network running on a separate instance of SoC 804 that is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform lip reading to, without limitation, activate cellular service, make phone calls, write emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, and provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are unavailable at other times.

[0111] In at least one embodiment, the video image combiner may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in the video, the noise reduction appropriately weights spatial information and downweights information provided by adjacent frames. In at least one embodiment, when an image or portion of an image does not contain motion, the temporal noise reduction performed by the video image combiner may use information from previous images to reduce noise in the current image.

[0112] In at least one embodiment, the video image compositor may also be configured to perform stereo correction on the input stereo lens frames. In at least one embodiment, the video image compositor may also be used for user interface compositing when the operating system desktop is in use, eliminating the need for the GPU 808 to continually render new surfaces. In at least one embodiment, the video image compositor may be used to offload the GPU 808 when it is powered on and actively performing 3D rendering, improving performance and responsiveness.

[0113] In at least one embodiment, one or more of the SoCs 804 may further include a mobile industry processor interface ("MIPI") camera serial interface for receiving input from video and cameras, a high-speed interface, and / or a video input block that may be used for camera and associated pixel input functions. In at least one embodiment, one or more of the SoCs 804 may further include an input / output controller, which may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0114] In at least one embodiment, one or more of the SoCs 804 may further include peripherals, audio encoders / decoders ("codecs"), power management, and / or a wide range of peripheral interfaces to enable communication with other devices. In at least one embodiment, the SoC 804 may be used to process data from cameras (e.g., connected via a gigabit multimedia serial link and an Ethernet channel), sensors (e.g., LIDAR sensor 864, RADAR sensor 860, etc., which may be connected via an Ethernet channel), data from bus 802 (e.g., vehicle 800 speed, steering wheel position, etc.), data from GNSS sensor 858 (e.g., connected via an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more of the SoCs 804 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to offload routine data management tasks from the CPU 806.

[0115] In at least one embodiment, the SoC 804 may be an end-to-end platform with a flexible architecture spanning levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently utilizes computer vision and ADAS techniques for diversity and redundancy, and providing a flexible and reliable driving software stack platform along with deep learning tools. In at least one embodiment, the SoC 804 may be faster, more reliable, and more energy- and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator 814, when combined with the CPU 806, GPU 808, and data store 816, may provide a fast and efficient platform for levels 3-5 of autonomous vehicles.

[0116] In at least one embodiment, computer vision algorithms may run on a CPU, which may be configured using a high-level programming language such as C to perform various processing algorithms across various visual data. However, in at least one embodiment, CPUs often cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to run complex object detection algorithms used in in-vehicle ADAS applications and realistic Level 3-5 autonomous vehicles in real time.

[0117] Embodiments described herein may enable multiple neural networks to run simultaneously and / or sequentially, with the results combined together to enable Levels 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN running on the DLA or a separate GPU (e.g., GPU 820) may include text and word recognition, allowing the neural network to read and understand traffic signs, including signs for which it was not specifically trained. In at least one embodiment, the DLA may further include a neural network capable of identifying and interpreting signs and providing a semantic understanding of the signs, which can then be passed to a route planning module running on the CPU complex.

[0118] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks may be running simultaneously. For example, in at least one embodiment, a warning sign displaying "Caution: Flashing Icy Conditions" in conjunction with an electric light may be interpreted separately or collectively by several neural networks. In at least one embodiment, the warning sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the words "Flashing Icy Conditions" may be interpreted by a second deployed neural network, which, if the flashing light is detected, notifies the vehicle's route planning software (preferably running on the CPU complex) that an icy condition exists. In at least one embodiment, the flashing light may be identified by running a third deployed neural network over multiple frames, and the presence (or absence) of the flashing light is notified to the vehicle's route planning software. In at least one embodiment, all three neural networks may be running simultaneously, such as within the DLA and / or on the GPU 808.

[0119] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from a camera sensor to identify the presence of an authorized driver and / or owner of vehicle 800. In at least one embodiment, an always-on sensor processing engine may be used to unlock a vehicle and turn on lights when an owner approaches the driver's door, and to disable such vehicle in security mode when the owner leaves such vehicle. In this way, SoC 804 provides security against theft and / or carjacking.

[0120] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphone 896 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC 804 uses a CNN to classify environmental and urban sounds as well as visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative speed at which an emergency vehicle is approaching (e.g., by using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the region in which the vehicle is operating, as identified by GNSS sensor 858. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when operating in North America, the CNN attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, a control program for executing an emergency vehicle safety routine may be used to slow the vehicle, pull over, stop the vehicle, and / or allow a vehicle assisted by ultrasonic sensor 862 to idle until the emergency vehicle has passed.

[0121] In at least one embodiment, vehicle 800 may include a CPU 818 (e.g., a discrete CPU or dCPU), which may be coupled to SoC 804 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU 818 may include, for example, an X86 processor. CPU 818 may be used to perform any of a variety of functions, including, for example, reconciling potentially inconsistent results between ADAS sensors and SoC 804 and / or monitoring the status and health of controller 836 and / or infotainment system on a chip ("infotainment SoC") 830. In at least one embodiment, SoC 804 includes one or more interconnects, which may include Peripheral Component Interconnect Express (PCIe).

[0122] In at least one embodiment, vehicle 800 may include GPU 820 (e.g., a discrete GPU or dGPU), which may be coupled to SoC 804 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, GPU 820 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors in vehicle 800.

[0123] In at least one embodiment, vehicle 800 may further include a network interface 824, which may include, without limitation, a wireless antenna 826 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 824 may be used to enable wireless connections to Internet cloud services (e.g., servers and / or other network devices) with other vehicles and / or computing devices (e.g., occupant client devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 800 and the other vehicles and / or an indirect link (e.g., across a network and via the Internet) may be established. In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 800 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 800). In at least one embodiment, these aforementioned features may be part of a cooperative adaptive cruise control feature of the vehicle 800.

[0124] In at least one embodiment, the network interface 824 may include an SoC that provides modulation and demodulation functionality and enables the controller 836 to communicate over a wireless network. In at least one embodiment, the network interface 824 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, the frequency conversion may be performed in any technically feasible manner. For example, the frequency conversion may be performed by well-known processes and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0125] In at least one embodiment, vehicle 800 may further include a data store 828, which may include, without limitation, off-chip (e.g., not on SoC 804) storage. In at least one embodiment, data store 828 may include one or more storage elements, including, without limitation, RAM, SRAM, dynamic random access memory (“DRAM”), video random-access memory (“VRAM”), flash memory, a hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0126] In at least one embodiment, vehicle 800 may further include GNSS sensors 858 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 858 may be used, including, for example, without limitation, a GPS using a USB connector with an Ethernet to serial (e.g., RS-232) bridge.

[0127] In at least one embodiment, vehicle 800 may further include a RADAR sensor 860. In at least one embodiment, RADAR sensor 860 may be used by vehicle 800 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, RADAR sensor 860 may use a CAN bus and / or bus 802 for control (e.g., to transmit data generated by RADAR sensor 860) and to access object tracking data, and in some examples, may have access to an Ethernet channel to access raw data. In at least one embodiment, various types of RADAR sensors may be used. For example, without limitation, RADAR sensor 860 may be suitable for forward, rearward, and side RADAR use. In at least one embodiment, one or more of RADAR sensors 860 are pulse-Doppler RADAR sensors.

[0128] In at least one embodiment, the RADAR sensor 860 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, and short-range with side coverage. In at least one embodiment, the long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system may provide a wide field of view, such as within a 250 m (meter) range, achieved by two or more independent scans. In at least one embodiment, the RADAR sensor 860 may help distinguish between static and moving objects and may be used by the ADAS system 838 to provide emergency braking assistance and forward collision warning. In at least one embodiment, the sensors 860 included in the long-range RADAR system may include, without limitation, multiple (e.g., six or more) fixed RADAR antennas, as well as monostatic multi-mode RADAR with high-speed CAN and FlexRay interfaces. In at least one embodiment, where there are six antennas, the center four antennas may generate a focused beam pattern designed to record the surroundings of vehicle 800 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the other two antennas may extend the field of view, allowing for quick detection of vehicles entering or exiting the lane of vehicle 800.

[0129] In at least one embodiment, the medium-range RADAR system may include, by way of example, a range of up to 160 meters (forward) or 80 meters (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, the short-range RADAR system may include, without limitation, any number of RADAR sensors 860 designed to be mounted on either end of the rear bumper. When mounted on either end of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that constantly monitor blind spots behind and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 838 to provide blind spot detection and / or lane change assistance.

[0130] In at least one embodiment, vehicle 800 may further include ultrasonic sensors 862. In at least one embodiment, ultrasonic sensors 862 may be located at front, rear, and / or side locations of vehicle 800 and may be used for parking assistance and / or to generate and update an occupancy grid. In at least one embodiment, multiple ultrasonic sensors 862 may be used, and different ultrasonic sensors 862 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensors 862 may operate at functional safety level ASIL B.

[0131] In at least one embodiment, vehicle 800 may include a LIDAR sensor 864. In at least one embodiment, LIDAR sensor 864 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor 864 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 800 may include multiple LIDAR sensors 864 (e.g., two, four, six, etc.), which may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0132] In at least one embodiment, the LIDAR sensor 864 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, a commercially available LIDAR sensor 864 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2 cm to 3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor 864 may include a small device that can be integrated into the front, rear, side, and / or corner positions of the vehicle 800. In at least one embodiment, the LIDAR sensor 864 of such an embodiment may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, with a range of 200 meters, even for low-reflectivity objects. In at least one embodiment, a front-mounted LIDAR sensor 864 may be configured for a horizontal field of view of 45 degrees to 135 degrees.

[0133] In at least one embodiment, LIDAR technology such as 3D flash LIDAR may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 800 up to approximately 200 meters. In at least one embodiment, the flash LIDAR unit includes, without limitation, a receptor that records the transit time of the laser pulse and the reflected light at each pixel, which corresponds to the range from the vehicle 800 to the object. In at least one embodiment, flash LIDAR may enable a highly accurate, undistorted image of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of the vehicle 800. In at least one embodiment, the 3D flash LIDAR system includes, without limitation, a solid-state 3D staring array LIDAR camera (e.g., a non-scanning LIDAR device) with no moving parts other than a fan. In at least one embodiment, the flash LIDAR device may use 5 nanosecond Class I (eye-safe) laser pulses per frame and may capture reflected laser light as a 3D range point cloud and co-registered intensity data.

[0134] In at least one embodiment, vehicle 800 may further include an IMU sensor 866. In at least one embodiment, IMU sensor 866 may be positioned at the center of a rear axle of vehicle 800. In at least one embodiment, IMU sensor 866 may include, for example, without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, multiple magnetic compasses, and / or other types of sensors. In at least one embodiment, such as in a 6-axis application, IMU sensor 866 may include, without limitation, an accelerometer and a gyroscope. In at least one embodiment, such as in a 9-axis application, IMU sensor 866 may include, without limitation, an accelerometer, a gyroscope, and a magnetometer.

[0135] In at least one embodiment, IMU sensor 866 may be implemented as a compact, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical systems ("MEMS") inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, IMU sensor 866 enables vehicle 800 to estimate its heading by directly observing velocity changes and correlating them from GPS to IMU sensor 866 without requiring input from a magnetic sensor. In at least one embodiment, IMU sensor 866 and GNSS sensor 858 may be combined into a single integrated unit.

[0136] In at least one embodiment, vehicle 800 may include microphones 896 located in and / or around vehicle 800. In at least one embodiment, microphones 896 may be used for, among other things, emergency vehicle detection and identification.

[0137] In at least one embodiment, vehicle 800 may further include any number of camera types, including stereo camera 868, wide-angle camera 870, infrared camera 872, perimeter camera 874, long-range camera 898, mid-range camera 876, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire perimeter of vehicle 800. In at least one embodiment, the types of cameras used vary depending on vehicle 800. In at least one embodiment, any combination of camera types may be used to provide the required coverage around vehicle 800. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 800 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example and not limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communications. In at least one embodiment, each camera may be as described in more detail herein above with respect to Figures 8A and 8B.

[0138] In at least one embodiment, vehicle 800 may further include a vibration sensor 842. In at least one embodiment, vibration sensor 842 may measure vibrations of components of vehicle 800, such as an axle. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, if two or more vibration sensors 842 are used, the difference in vibration may be used to determine the amount of friction or slippage of the road surface (e.g., if there is a vibration difference between a powered axle and a free-spinning axle).

[0139] In at least one embodiment, vehicle 800 may include an ADAS system 838. In at least one embodiment, ADAS system 838 may include, in some examples, without limitation, an SoC. In at least one embodiment, the ADAS systems 838 may include, without limitation, any number and combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0140] In at least one embodiment, the ACC system may use a RADAR sensor 860, a LIDAR sensor 864, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle directly in front of the vehicle 800 and automatically adjusts the speed of the vehicle 800 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system enforces distance maintenance and notifies the vehicle 800 to change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0141] In at least one embodiment, the CACC system uses information from other vehicles, which may be received by network interface 824 and / or wireless antenna 826 from other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, a vehicle-to-vehicle ("V2V") communication link may provide a direct link, while an infrastructure-to-vehicle ("I2V") communication link may provide an indirect link. Generally, V2V communication provides information about the immediate preceding vehicle (e.g., a vehicle immediately in front of vehicle 800 and in the same lane), while I2V communication provides information about traffic ahead of that. In at least one embodiment, the CACC system may include either or both I2V and V2V information sources. In at least one embodiment, information about vehicles in front of vehicle 800 may make the CACC system more reliable, potentially allowing for smoother traffic flow and reducing congestion on the roads.

[0142] In at least one embodiment, the FCW system is designed to alert drivers to hazards so that they can take corrective action. In at least one embodiment, the FCW system uses a front-facing camera and / or RADAR sensor 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide a warning, such as in the form of an audible, visual warning, vibration, and / or quick brake pulse.

[0143] In at least one embodiment, the AEB system may detect an imminent frontal collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use a front-facing camera and / or RADAR sensor 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first advises the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the severity of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-collision braking.

[0144] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as vibration of the steering wheel or seat, to advise the driver when the vehicle 800 crosses a lane marker. In at least one embodiment, the LDW system does not engage if the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, the LKA system provides steering input or brake control to correct the vehicle 800 if the vehicle 800 begins to stray from its lane.

[0145] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver. In at least one embodiment, the BSW system may provide visual, audible, and / or haptic alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may use a rearview camera and / or RADAR sensor 860 coupled to dedicated processors, DSPs, FPGAs, and / or ASICs, which are electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0146] In at least one embodiment, the RCTW system may provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear camera when reversing the vehicle 800. In at least one embodiment, the RCTW system includes an AEB system to ensure vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear RADAR sensors 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration components.

[0147] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting to the driver, but are typically not a major concern because conventional ADAS systems advise the driver and allow the driver to determine whether a safety condition truly exists and respond accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 800 itself determines whether to follow the results from the primary computer or the secondary computer (e.g., the first controller or the second controller of the controller 836). For example, in at least one embodiment, the ADAS system 838 may be a backup and / or secondary computer to provide perception information to a rationality module of the backup computer. In at least one embodiment, the rationality monitor of the backup computer may run redundant software on hardware components to detect perceptual errors and dynamic driving tasks. In at least one embodiment, output from the ADAS system 838 may be provided to a supervisory MCU. In at least one embodiment, in the event of conflicting outputs from the primary computer and the secondary computer, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0148] In at least one embodiment, the primary computer may be configured to provide the monitor MCU with a reliability score indicating the reliability of the primary computer's selected result. In at least one embodiment, if the reliability score exceeds a threshold, the monitor MCU may follow the primary computer's instructions regardless of whether the secondary computers are providing conflicting or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold and the primary and secondary computers provide different (e.g., conflicting) results, the monitor MCU may arbitrate between the computers to determine the appropriate result.

[0149] In at least one embodiment, the monitoring MCU may be configured to execute a neural network trained and configured to determine conditions under which the secondary computer will provide a false alarm based at least in part on outputs from the primary computer and the secondary computer. In at least one embodiment, the neural network of the monitoring MCU may learn when the output of the secondary computer may be trusted and when it may not be trusted. For example, in at least one embodiment, if the secondary computer is a RADAR-based FCW system, the neural network of the monitoring MCU may learn when the FCW system identifies a metal object that is not actually a hazard, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, if the secondary computer is a camera-based LDW system, the neural network of the monitoring MCU may learn to disable LDW when a bicyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the monitoring MCU may include at least one of a DLA or a GPU suitable for executing the neural network along with associated memory. In at least one embodiment, the supervisory MCU may comprise and / or be included as a component of the SoC 804.

[0150] In at least one embodiment, the ADAS system 838 may include a secondary computer that performs ADAS functions using traditional rules of computer vision. In at least one embodiment, the secondary computer may use classical computer vision rules (if-then rules), and a neural network may reside in the supervisory MCU, improving reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the overall system more error-tolerant, particularly to errors caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a software bug or error in the software running on the primary computer and non-identical software code running on the secondary computer provides overall consistent results, the supervisory MCU may have greater confidence that the overall results are correct and that a software or hardware bug on the primary computer did not cause a critical error.

[0151] In at least one embodiment, the output of the ADAS system 838 may be provided to a perception block of the primary computer and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 838 indicates a frontal collision warning due to an immediately preceding object, the perception block may use this information when identifying the object. In at least one embodiment, the secondary computer may have its own neural network pre-trained, as described herein, thus reducing the risk of false positives.

[0152] In at least one embodiment, vehicle 800 may further include an infotainment SoC 830 (e.g., an in-vehicle infotainment system (IVI)). While infotainment system 830 is shown and described as an SoC, in at least one embodiment, it may not be an SoC and may include, without limitation, two or more separate components. In at least one embodiment, infotainment SoC 830 may include, without limitation, a combination of hardware and software that may be used to provide vehicle 800 with audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephony (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation system, rear park assist, wireless data system, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door opening / closing, air filter information, etc.). For example, infotainment SoC 830 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, a car computer, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a heads-up display (“HUD”), an HMI display 834, telematics devices, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 830 may also be used to provide information (e.g., visual and / or auditory) to a user of vehicle 800, such as information from ADAS system 838, autonomous driving information such as vehicle maneuver plans, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0153] In at least one embodiment, infotainment SoC 830 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 830 may communicate with other devices, systems, and / or components of vehicle 800 via bus 802. In at least one embodiment, infotainment SoC 830 may be coupled to a supervisory MCU such that the infotainment system's GPU may perform some self-driving functions when primary controller 836 (e.g., vehicle 800's primary and / or backup computers) fails. In at least one embodiment, infotainment SoC 830 may place vehicle 800 in a driver-safety shutdown mode, as described herein.

[0154] In at least one embodiment, vehicle 800 may further include an instrument cluster 832 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, instrument cluster 832 may include, without limitation, a controller and / or a supercomputer (e.g., a separate controller or supercomputer). In at least one embodiment, instrument cluster 832 may include any number and combination of instrument sets, such as, without limitation, a speedometer, fuel level, oil pressure, a tachometer, an odometer, turn signals, a shift lever position indicator, a seat belt warning light, a parking brake warning light, an engine malfunction light, supplemental restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some instances, information may be displayed and / or shared between infotainment SoC 830 and instrument cluster 832. In at least one embodiment, instrument cluster 832 may be included as part of infotainment SoC 830, or vice versa.

[0155] In at least one embodiment, at least one embodiment of FIG. 8C can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify the pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0156] 8D is a diagram of a system for communicating between a cloud-based server and the autonomous vehicle 800 of FIG. 8A , according to at least one embodiment. In at least one embodiment, the system may include any number and type of vehicles, including, without limitation, a server 878, a network 890, and a vehicle 800. In at least one embodiment, the server 878 may include, without limitation, multiple GPUs 884(A)-884(H) (collectively referred to herein as GPUs 884), PCIe switches 882(A)-882(D) (collectively referred to herein as PCIe switches 882), and / or CPUs 880(A)-880(B) (collectively referred to herein as CPUs 880). In at least one embodiment, the GPUs 884, CPUs 880, and PCIe switches 882 may be interconnected by a high-speed interconnect, such as, for example, without limitation, an NVLink interface 888 developed by NVIDIA, and / or a PCIe connection 886. In at least one embodiment, the GPUs 884 are connected to each other via NVLink and / or NVS switch SoCs, and the GPUs 884 and PCIe switch 882 are connected via PCIe interconnects. While eight GPUs 884, two CPUs 880, and four PCIe switches 882 are shown, this is not intended to be limiting. In at least one embodiment, each of the servers 878 may include any number of GPUs 884, CPUs 880, and / or PCIe switches 882 in any combination, including, but not limited to, 8 GPUs 884, 16 CPUs 880, and / or PCIe switches 882. For example, in at least one embodiment, the servers 878 may each include 8, 16, 32, and / or more GPUs 884.

[0157] In at least one embodiment, server 878 may receive image data from a vehicle over network 890 representing images showing unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, server 878 may transmit updated or unupdated neural network 892 and / or map information 894, including, without limitation, information regarding traffic and road conditions, to the vehicle over network 890. In at least one embodiment, updates to map information 894 may include, without limitation, updates to HD map 822, such as information regarding construction sites, potholes, detours, floods, and / or other obstacles. In at least one embodiment, neural network 892 and / or map information 894 may be derived from new training and / or experience represented in data received from any number of vehicles in the environment and / or may be derived based at least in part on training performed at a data center (e.g., using server 878 and / or other servers).

[0158] In at least one embodiment, server 878 may be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data may be tagged and / or otherwise preprocessed (e.g., if the associated neural network benefits from supervised learning). In at least one embodiment, any amount of the training data may not be tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, it may be used by the vehicle (e.g., sent to the vehicle via network 890) and / or used by server 878 to remotely monitor the vehicle.

[0159] In at least one embodiment, server 878 may receive data from vehicles and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, server 878 may include a deep learning supercomputer and / or dedicated AI computer powered by GPU 884, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server 878 may also include a deep learning infrastructure using a CPU-powered data center.

[0160] In at least one embodiment, the deep learning infrastructure of server 878 may be capable of fast, real-time inference and may use that capability to assess and verify the health of the processor, software, and / or associated hardware of vehicle 800. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 800, such as a series of images and / or objects that vehicle 800 has located in the series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by vehicle 800; if the results do not match and the deep learning infrastructure concludes that the AI ​​of vehicle 800 has failed, server 878 may send a signal to vehicle 800 instructing a fail-safe computer in vehicle 800 to take control, notify the occupants, and complete a safe stopping maneuver.

[0161] In at least one embodiment, server 878 may include a GPU 884 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT3 devices). In at least one embodiment, the combination of a GPU-powered server and inference acceleration can enable real-time response. In at least one embodiment, servers powered by CPUs, FPGAs, and other processors may be used for inference, such as when performance is less critical. In at least one embodiment, a hardware structure 515 is used to execute one or more embodiments. Details regarding hardware structure 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B.

[0162] In at least one embodiment, at least one embodiment of FIG. 8D can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify a pose of one or more cameras based, at least in part, on one or more different poses of one or more cameras, and / or based on any other embodiment discussed above with respect to FIGS. 1-4, and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0163] Computer Systems 9 is a block diagram illustrating an exemplary computer system, which may be a system having interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof, formed with a processor that may include an execution unit for executing instructions, according to at least one embodiment. In at least one embodiment, computer system 900 may include components such as, without limitation, a processor 902 for using an execution unit that includes logic for executing algorithms for processing data in accordance with the present disclosure, such as in the embodiments described herein. In at least one embodiment, computer system 900 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 900 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may also be used.

[0164] Embodiments may be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors ("DSPs"), systems-on-chips, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0165] In at least one embodiment, computer system 900 may include, without limitation, a processor 902, which may include one or more execution units 908 for performing training and / or inference of machine learning models according to the techniques described herein. In at least one embodiment, computer system 900 is a single-processor desktop or server system, while in other embodiments, computer system 900 may be a multiprocessor system. In at least one embodiment, processor 902 may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 902 may be coupled to a processor bus 910, which may transmit digital signals between processor 902 and other components within computer system 900.

[0166] In at least one embodiment, processor 902 may include, without limitation, level 1 ("L1") internal cache memory ("cache") 904. In at least one embodiment, processor 902 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 902. Other embodiments may include a combination of both internal and external cache, depending on the particular implementation and needs. In at least one embodiment, register file 906 may store different types of data in various registers, including, without limitation, integer registers, floating-point registers, status registers, and an instruction pointer register.

[0167] In at least one embodiment, processor 902 also includes an execution unit 908, including, without limitation, logic for performing integer and floating-point operations. In at least one embodiment, processor 902 may also include microcode (“u-code”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 908 may include logic for a packed instruction set 909. In at least one embodiment, including packed instruction set 909, along with associated circuitry for executing the instructions, in a general-purpose processor's instruction set allows operations used by many multimedia applications to be performed using packed data in processor 902. In at least one embodiment, performing operations on packed data using the full width of the processor's data bus can speed up and more efficiently execute many multimedia applications, eliminating the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0168] In at least one embodiment, execution unit 908 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 900 may include, without limitation, memory 920. In at least one embodiment, memory 920 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 920 may store instructions 919 and / or data 921 represented by data signals that may be executed by processor 902.

[0169] In at least one embodiment, a system logic chip may be coupled to the processor bus 910 and the memory 920. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”) 916, and the processor 902 may communicate with the MCH 916 via the processor bus 910. In at least one embodiment, the MCH 916 may provide a high-bandwidth memory path 918 to the memory 920 for instruction and data storage, and for storing graphics commands, data, and textures. In at least one embodiment, the MCH 916 may route data signals between the processor 902, the memory 920, and other components of the computer system 900, and may bridge data signals between the processor bus 910, the memory 920, and a system I / O interface 922. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 916 may be coupled to memory 920 via a high-bandwidth memory path 918, and the graphics / video card 912 may be coupled to the MCH 916 via an Accelerated Graphics Port (“AGP”) interconnect 914.

[0170] In at least one embodiment, computer system 900 may use system I / O interface 922 as a proprietary hub interface bus to couple MCH 916 to I / O controller hub (“ICH”) 930. In at least one embodiment, ICH 930 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 920, a chipset, and processor 902. Examples may include, without limitation, an audio controller 929, a firmware hub (“flash BIOS”) 928, a wireless transceiver 926, data storage 924, a legacy I / O controller 923 including a user input and keyboard interface 925, a serial expansion port 927 such as a Universal Serial Bus (“USB”) port, and a network controller 934. In at least one embodiment, data storage 924 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0171] In at least one embodiment, Figure 9 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, Figure 9 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in Figure 9 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 900 may be interconnected using a compute express link (CXL) interconnect.

[0172] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, logic 515 may be used in computer system 900 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0173] In at least one embodiment, at least one embodiment of FIG. 9 can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify a pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0174] 10 is a block diagram illustrating an electronic device 1000 for utilizing a processor 1010, according to at least one embodiment. In at least one embodiment, electronic device 1000 may be, for example, without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0175] In at least one embodiment, electronic device 1000 may include, without limitation, a processor 1010 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. 2The devices may be coupled using a bus or interface such as a C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 10 depicts a system including interconnected hardware devices or “chips,” although in other embodiments, FIG. 10 may depict an exemplary SoC. In at least one embodiment, the devices depicted in FIG. 10 may be interconnected using a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 10 may be interconnected using a Compute Express Link (CXL) interconnect.

[0176] In at least one embodiment, FIG. 10 illustrates a display 1024, a touch screen 1025, a touch pad 1030, a Near Field Communications unit ("NFC") 1045, a sensor hub 1040, a thermal sensor 1046, an Express Chipset ("EC") 1035, a Trusted Platform Module ("TPM") 1038, a BIOS / firmware / flash memory ("BIOS,FW flash") 1022, a DSP 1060, a drive 1020, such as a solid state disk ("SSD") or hard disk drive ("HDD"), a wireless local area network unit ("WLAN") 1050, a Bluetooth unit 1052, a wireless wide area network unit ("WWAN") 1054, a Bluetooth module 1056, a Bluetooth-enabled device ("Device") 1058 ... The memory may include a memory card (RAM) 1056, a Global Positioning System (GPS) unit 1055, a camera such as a USB 3.0 camera ("USB 3.0 Camera") 1054, and / or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") 1015, implemented, for example, to the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0177] In at least one embodiment, other components may be communicatively coupled to the processor 1010 via the components described herein. In at least one embodiment, an accelerometer 1041, an ambient light sensor (“ALS”) 1042, a compass 1043, and a gyroscope 1044 may be communicatively coupled to the sensor hub 1040. In at least one embodiment, a thermal sensor 1039, a fan 1037, a keyboard 1036, and a touchpad 1030 may be communicatively coupled to the EC 1035. In at least one embodiment, a speaker 1063, headphones 1064, and a microphone (“mic”) 1065 may be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 1062, which may be communicatively coupled to the DSP 1060. In at least one embodiment, audio unit 1062 may include, for example, without limitation, an audio coder / decoder ("codec") and a Class D amplifier. In at least one embodiment, SIM card ("SIM") 1057 may be communicatively coupled to WWAN unit 1056. In at least one embodiment, components such as WLAN unit 1050 and Bluetooth unit 1052, as well as WWAN unit 1056, may be implemented in a Next Generation Form Factor ("NGFF").

[0178] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, logic 515 may be used in electronic device 1000 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0179] In at least one embodiment, at least one embodiment of FIG. 10 can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify a pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0180] 11 illustrates a computer system 1100, according to at least one embodiment. In at least one embodiment, the computer system 1100 is configured to implement the various processes and methods described throughout this disclosure.

[0181] In at least one embodiment, computer system 1100 includes at least one central processing unit ("CPU") 1102 connected to a communication bus 1110 implemented using any suitable protocol, such as, without limitation, PCI (Peripheral Component Interconnect), Peripheral Component Interconnect Express ("PCI-Express"), AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1100 includes main memory 1104 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1104, which may be in the form of random access memory ("RAM"). In at least one embodiment, network interface subsystem (“network interface”) 1122 provides an interface with other computing devices and networks to receive data from other systems comprising computer system 1100 and to transmit data to other systems comprising computer system 1100.

[0182] In at least one embodiment, computer system 1100 includes, without limitation, input device(s) 1108, parallel processing system 1112, and display device 1106, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode ("LED") display, plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device(s) 1108, such as a keyboard, mouse, touch pad, microphone, or the like. In at least one embodiment, each of the modules described herein may be located on a single semiconductor platform to form a processing system.

[0183] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, logic 515 may be used in computer system 1100 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0184] In at least one embodiment, at least one embodiment of FIG. 11 can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify a pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0185] 12 illustrates a computer system 1200, according to at least one embodiment. In at least one embodiment, computer system 1200 may include, without limitation, a computer 1210 and a USB stick 1220. In at least one embodiment, computer 1210 may include, without limitation, any number and type of processor (not shown) and memory (not shown). In at least one embodiment, computer 1210 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0186] In at least one embodiment, USB stick 1220 includes, without limitation, a processing unit 1230, a USB interface 1240, and USB interface logic 1250. In at least one embodiment, processing unit 1230 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1230 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1230 comprises an application specific integrated circuit (“ASIC”) optimized to perform any quantity and type of operations associated with machine learning. For example, in at least one embodiment, processing unit 1230 is a tensor processing unit (“TPC”) optimized to perform machine vision and machine learning inference operations. In at least one embodiment, processing unit 1230 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0187] In at least one embodiment, USB interface 1240 may be any type of USB connector or socket. For example, in at least one embodiment, USB interface 1240 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1240 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1250 may include any amount and type of logic that enables processing unit 1230 to interface with a device (e.g., computer 1210) via USB connector 1240.

[0188] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, logic 515 may be used in computer system 1200 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0189] In at least one embodiment, at least one embodiment of FIG. 12 can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify a pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0190] FIG. 13A illustrates an exemplary architecture in which multiple GPUs 1310(1)-1310(N) are communicatively coupled to multiple multi-core processors 1305(1)-1305(M) via high-speed links 1340(1)-1340(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1340(1)-1340(N) support communication throughputs of 4 GB / s, 30 GB / s, 80 GB / s, or more. In at least one embodiment, various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure. 16A and 16B, one or more of the plurality of GPUs 1310(1)-1310(N) includes one or more graphics cores (also referred to simply as "cores") 1600. In at least one embodiment, one or more graphics cores 1600 may also be referred to as streaming multiprocessors ("SM"), stream processors ("SP"), stream processing units ("SPU"), compute units ("CU"), execution units ("EU"), and / or slices, and in this context, a slice may refer to a portion of the processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or a scheduler).

[0191] Additionally, in at least one embodiment, two or more of the GPUs 1310 are interconnected via high-speed links 1329(1)-1329(2), which may be implemented using similar or different protocols / links as used for high-speed links 1340(1)-1340(N). Similarly, two or more of the multi-core processors 1305 may be connected via high-speed link 1328, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, all communications between the various system components shown in FIG. 13A may be achieved using similar protocols / links (e.g., via a common interconnect fabric).

[0192] In at least one embodiment, each multi-core processor 1305 is communicatively coupled to processor memory 1301(1)-1301(M) via memory interconnect 1326(1)-1326(M), respectively, and each GPU 1310(1)-1310(N) is communicatively coupled to GPU memory 1320(1)-1320(N) via GPU memory interconnect 1350(1)-1350(N), respectively. In at least one embodiment, memory interconnects 1326 and 1350 may utilize similar or different memory access technologies. By way of example, and not limitation, processor memory 1301(1)-1301(M) and GPU memory 1320 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of processor memory 1301 may be volatile memory and other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0193] As described herein, various multi-core processors 1305 and GPUs 1310 may each be physically coupled to specific memories 1301, 1320, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as "effective address" space) is distributed among various physical memories. For example, processor memories 1301(1) through 1301(M) may each have 64 GB of system memory address space, and GPU memories 1320(1) through 1320(N) may each have 32 GB of system memory address space, resulting in a total of 256 GB of addressable memory when M=2 and N=4. Other values ​​for N and M are possible.

[0194] 13B illustrates further details of the interconnection between multi-core processor 1307 and graphics acceleration module 1346 according to one example embodiment. In at least one embodiment, graphics acceleration module 1346 may include one or more GPU chips integrated on a line card that is coupled to processor 1307 via high-speed link 1340 (e.g., PCIe bus, NVLink, etc.). Alternatively, in at least one embodiment, graphics acceleration module 1346 may be integrated into the package or chip with processor 1307.

[0195] In at least one embodiment, the processor 1307 includes multiple cores 1360A-1360D (which may also be referred to as "execution units"), each having a translation lookaside buffer (TLB) 1361A-1361D and one or more caches 1362A-1362D. In at least one embodiment, the cores 1360A-1360D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, the caches 1362A-1362D may comprise a level 1 (L1) and a level 2 (L2) cache. Additionally, one or more shared caches 1356 may be included in the caches 1362A-1362D and shared by the set of cores 1360A-1360D. For example, one embodiment of processor 1307 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more of the L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, processor 1307 and graphics acceleration module 1346 are coupled to system memory 1314, which may include processor memories 1301(1)-1301(M) of FIG. 13A.

[0196] In at least one embodiment, coherence is maintained for data and instructions stored in the various caches 1362A-1362D, 1356, and system memory 1314 through inter-core communication via coherence bus 1364. In at least one embodiment, for example, each cache may have cache coherence logic / circuitry associated therewith for communicating via coherence bus 1364 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via coherence bus 1364 to monitor cache accesses.

[0197] In at least one embodiment, proxy circuit 1325 communicatively couples graphics acceleration module 1346 to coherence bus 1364 to enable graphics acceleration module 1346 to participate in cache coherence protocols as a peer of cores 1360A-1360D. In particular, in at least one embodiment, interface 1335 provides a connection to proxy circuit 1325 over high-speed link 1340, and interface 1337 connects graphics acceleration module 1346 to high-speed link 1340.

[0198] In at least one embodiment, the accelerator integrated circuit 1336 provides cache management, memory access, content management, and interrupt management services on behalf of the multiple graphics processing engines 1331(1)-1331(N) of the graphics acceleration module 1346. In at least one embodiment, the graphics processing engines 1331(1)-1331(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, the multiple graphics processing engines 1331(1)-1331(N) of the graphics acceleration module 1346 include one or more graphics cores 1600, as discussed in connection with FIGs. 16A and 16B. Alternatively, in at least one embodiment, the graphics processing engines 1331(1)-1331(N) may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1346 may be a GPU having multiple graphics processing engines 1331(1)-1331(N), or the graphics processing engines 1331(1)-1331(N) may be individual GPUs integrated into a common package, line card, or chip.

[0199] In at least one embodiment, accelerator integrated circuitry 1336 includes a memory management unit (MMU) 1339 for performing various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation), and a memory access protocol for accessing system memory 1314. In at least one embodiment, MMU 1339 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 1338 may store commands and data for efficient access by graphics processing engines 1331(1)-1331(N). In at least one embodiment, data stored in cache 1338 and graphics memory 1333(1)-1333(M) is kept coherent with core caches 1362A-1362D, 1356, and system memory 1314, possibly using fetch unit 1344. As noted, this may be accomplished via proxy circuitry 1325 (e.g., sending updates to cache 1338 and receiving updates from cache 1338 regarding modifications / accesses of cache lines in processor caches 1362A-1362D, 1356) on behalf of cache 1338 and memory 1333(1)-1333(M).

[0200] In at least one embodiment, a set of registers 1345 stores context data for threads executed by graphics processing engines 1331(1)-1331(N), and a context management circuit 1348 manages thread contexts. For example, the context management circuit 1348 may perform save and restore operations to save and restore the context of various threads during a context switch (e.g., where a first thread is saved and a second thread is saved so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 1348 may store current register values ​​in a designated area of ​​memory (e.g., identified by a context pointer). Then, when returning to the context, the context management circuit 1348 may restore the register values. In at least one embodiment, the interrupt management circuit 1347 receives and processes interrupts received from system devices.

[0201] In at least one embodiment, virtual / effective addresses from the graphics processing engine 1331 are translated to real / physical addresses in the system memory 1314 by the MMU 1339. In at least one embodiment, the accelerator integration circuit 1336 supports multiple (e.g., four, eight, or sixteen) graphics accelerator modules 1346 and / or other accelerator devices. In at least one embodiment, the graphics accelerator modules 1346 may be dedicated to a single application running on the processor 1307 or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment exists in which the resources of the graphics processing engines 1331(1)-1331(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0202] In at least one embodiment, the accelerator integrated circuitry 1336 performs as a bridge to the system for the graphics acceleration module 1346, providing address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuitry 1336 may provide a virtualization facility for a host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1331(1)-1331(N).

[0203] In at least one embodiment, the hardware resources of graphics processing engines 1331(1)-1331(N) are explicitly mapped into the real address space seen by host processor 1307, so that any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuitry 1336 is to physically separate graphics processing engines 1331(1)-1331(N) so that they appear to the system as independent units.

[0204] In at least one embodiment, one or more graphics memories 1333(1)-1333(M) are respectively coupled to each of the graphics processing engines 1331(1)-1331(N), where N=M. In at least one embodiment, the graphics memories 1333(1)-1333(M) store instructions and data being processed by each of the graphics processing engines 1331(1)-1331(N). In at least one embodiment, the graphics memories 1333(1)-1333(M) may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory such as 3D XPoint or Nano-Ram.

[0205] In at least one embodiment, to reduce data traffic over high-speed link 1340, biasing techniques can be used to ensure that the data stored in graphics memory 1333(1)-1333(M) is data that will be used most frequently by graphics processing engines 1331(1)-1331(N), and preferably is data that is not used (or at least not frequently) by cores 1360A-1360D. Similarly, in at least one embodiment, biasing mechanisms attempt to keep data needed by the cores (and thus preferably not by graphics processing engines 1331(1)-1331(N)) in caches 1362A-1362D, 1356, and system memory 1314.

[0206] 13C illustrates another exemplary embodiment in which the accelerator integration circuitry 1336 is integrated within the processor 1307. In this embodiment, the graphics processing engines 1331(1)-1331(N) communicate directly with the accelerator integration circuitry 1336 via high-speed link 1340 (which again may be any form of bus or interface protocol) via interface 1337 and interface 1335. In at least one embodiment, the accelerator integration circuitry 1336 may perform operations similar to those described with respect to FIG. 13B, but potentially at a higher throughput given its proximity to the coherence bus 1364 and caches 1362A-1362D, 1356. In at least one embodiment, the accelerator integrated circuitry supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuitry 1336 and a programming model controlled by the graphics acceleration module 1346.

[0207] In at least one embodiment, graphics processing engines 1331(1)-1331(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can route other application requests to graphics processing engines 1331(1)-1331(N), achieving virtualization within a VM / partition.

[0208] In at least one embodiment, graphics processing engines 1331(1)-1331(N) may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a system hypervisor to virtualize graphics processing engines 1331(1)-1331(N) to allow access by each operating system. In at least one embodiment, in a single-partition system without a hypervisor, graphics processing engines 1331(1)-1331(N) are owned by the operating system. In at least one embodiment, the operating system may virtualize graphics processing engines 1331(1)-1331(N) to provide access to each process or application.

[0209] In at least one embodiment, the graphics acceleration module 1346 or an individual graphics processing engine 1331(1)-1331(N) selects a process element using a process handle. In at least one embodiment, the process element is stored in system memory 1314 and is addressable using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to a host process when registering the host process's context with the graphics processing engine 1331(1)-1331(N) (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the low-order 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0210] FIG. 13D illustrates an exemplary accelerator integration slice 1390. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of accelerator integration circuitry 1336. In at least one embodiment, application effective address space 1382 in system memory 1314 stores process element 1383. In at least one embodiment, process element 1383 is stored in response to a GPU call 1381 from an application 1380 executing on processor 1307. In at least one embodiment, process element 1383 contains the process state of the corresponding application 1380. In at least one embodiment, work descriptor (WD) 1384 contained in process element 1383 can be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1384 is a pointer to a job request queue in application effective address space 1382.

[0211] In at least one embodiment, graphics acceleration module 1346 and / or individual graphics processing engines 1331(1)-1331(N) may be shared by all or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process state and sending WD 1384 to graphics acceleration module 1346 to start a job in a virtualized environment.

[0212] In at least one embodiment, the dedicated process programming model is implementation specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1346 or an individual graphics processing engine 1331. In at least one embodiment, when the graphics acceleration module 1346 is owned by a single process, the hypervisor initializes the accelerator integration circuitry 1336 for the owning partition when the graphics acceleration module 1346 is allocated, and the operating system initializes the accelerator integration circuitry 1336 for the owning process.

[0213] In at least one embodiment, in operation, WD fetch unit 1391 in accelerator integrated slice 1390 fetches the next WD 1384, which contains an indication of work to be performed by one or more graphics processing engines of graphics acceleration module 1346. In at least one embodiment, as shown, data from WD 1384 may be stored in register 1345 and used by MMU 1339, interrupt management circuit 1347, and / or context management circuit 1348. For example, one embodiment of MMU 1339 includes segment / page walk circuitry for accessing segment / page table 1386 within OS virtual address space 1385. In at least one embodiment, interrupt management circuit 1347 may process interrupt events 1392 received from graphics acceleration module 1346. In at least one embodiment, when performing graphics operations, effective addresses 1393 generated by graphics processing engines 1331(1)-1331(N) are translated into real addresses by MMU 1339.

[0214] In at least one embodiment, registers 1345 may be replicated for each graphics processing engine 1331(1)-1331(N) and / or graphics acceleration module 1346 and initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers may be included in accelerator integration slice 1390. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. [Table 1]

[0215] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 2]

[0216] In at least one embodiment, each WD 1384 is specific to a particular graphics acceleration module 1346 and / or graphics processing engine 1331(1)-1331(N). In at least one embodiment, WD 1484 may contain all the information that graphics processing engine 1331(1)-1331(N) needs to do its work, or may be a pointer to a memory location where an application has set up a command queue for work to be completed.

[0217] 13E illustrates further details of an exemplary embodiment of the sharing model. This embodiment includes a hypervisor real address space 1398 in which a process element list 1399 is stored. In at least one embodiment, the hypervisor real address space 1398 is accessible through a hypervisor 1396 that virtualizes the graphics acceleration module engine of the operating system 1395.

[0218] In at least one embodiment, a shared programming model allows all or a subset of processes from all or a subset of partitions in a system to use the graphics acceleration module 1346. In at least one embodiment, there are two programming models in which the graphics acceleration module 1346 is shared by multiple processes and partitions: timeslice shared and graphics-directed shared.

[0219] In at least one embodiment, in this model, system hypervisor 1396 owns graphics acceleration module 1346 and makes its functionality available to all operating systems 1395. In at least one embodiment, in order for graphics acceleration module 1346 to support virtualization by system hypervisor 1396, graphics acceleration module 1346 may comply with several requirements, such as: (1) application job requests must be autonomous (i.e., no state needs to be maintained between jobs) or graphics acceleration module 1346 must provide a mechanism for saving and restoring context; (2) application job requests must be guaranteed by graphics acceleration module 1346 to complete in a specified amount of time, including any translation errors, or graphics acceleration module 1346 must provide the ability to preempt job processing; and (3) graphics acceleration module 1346 must ensure fairness between processes when operating in a specified shared programming model.

[0220] In at least one embodiment, application 1380 must make a system call to operating system 1395 with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the acceleration function targeted by the system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value. In at least one embodiment, the WD is formatted specifically for graphics acceleration module 1346 and may be in the form of graphics acceleration module 1346 commands, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure for describing the work to be performed by graphics acceleration module 1346.

[0221] In at least one embodiment, the AMR value is the AMR state to use for the current process. In at least one embodiment, the value passed to the operating system is the same as the application setting the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1336 (not shown) and the graphics acceleration module 1346 does not support a User Authorization Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR to the hypervisor call. In at least one embodiment, the hypervisor 1396 may optionally apply the current Authorization Mask Override Register (AMOR) value before placing the AMR in the process element 1383. In at least one embodiment, the CSRP is one of the registers 1345 that contains the effective address of an area in the application's effective address space 1382 for the graphics acceleration module 1346 to save and restore context state. In at least one embodiment, this pointer is optional if no state needs to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be pinned system memory.

[0222] Upon receiving the system call, the operating system 1395 may verify that the application 1380 is registered and authorized to use the graphics acceleration module 1346. In at least one embodiment, the operating system 1395 then calls the hypervisor 1396 with the information shown in Table 3. [Table 3]

[0223] In at least one embodiment, upon receiving the hypervisor call, the hypervisor 1396 verifies that the operating system 1395 is registered and authorized to use the graphics acceleration module 1346. In at least one embodiment, the hypervisor 1396 then places the process element 1383 into a process element linked list of the corresponding graphics acceleration module 1346 type. In at least one embodiment, the process element may include the information shown in Table 4. [Table 4]

[0224] In at least one embodiment, the hypervisor initializes registers 1345 of multiple accelerator integrated slices 1390.

[0225] As shown in FIG. 13F, at least one embodiment uses unified memory that is addressable via a common virtual memory address space used to access physical processor memory 1301(1)-1301(N) and GPU memory 1320(1)-1320(N). In this implementation, operations performed on GPUs 1310(1)-1310(N) utilize the same virtual / effective memory address space as those used to access processor memory 1301(1)-1301(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1301(1), a second portion is allocated to second processor memory 1301(N), a third portion is allocated to GPU memory 1320(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes called the effective address space) is thereby distributed across each of the processor memory 1301 and GPU memory 1320, allowing any processor or GPU to access any physical memory, with virtual addresses mapped to physical memory.

[0226] In at least one embodiment, bias / coherence management circuits 1394A-1394E in one or more of MMUs 1339A-1339E ensure cache coherence between caches of one or more host processors (e.g., 1305) and caches of GPU 1310 and implement biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, multiple instances of bias / coherence management circuits 1394A-1394E are illustrated in FIG. 13F, although bias / coherence circuits may be implemented within the MMUs of one or more host processors 1305 and / or within accelerator integration circuit 1336.

[0227] One embodiment enables GPU memory 1320 to be mapped as part of system memory and accessible using shared virtual memory (SVM) techniques, but without the performance penalty associated with full system cache coherence. In at least one embodiment, having GPU memory 1320 accessible as system memory without cumbersome cache coherence overhead provides a beneficial operating environment for GPU offload. In at least one embodiment, this configuration enables host processor 1305 software to set up operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies require driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, being able to access GPU memory 1320 without cache coherence overhead can be essential to the execution time of offloaded computations. In at least one embodiment, for example, in the presence of significant streaming write memory traffic, cache coherence overhead may significantly reduce the effective write bandwidth seen by the GPU 1310. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation may be useful in determining the effectiveness of GPU offloading.

[0228] In at least one embodiment, the selection of the GPU bias and the host processor bias is determined by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page-granular structure containing one or two bits per GPU-attached memory page (e.g., controlled at memory page granularity). In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU memories 1320, with or without a bias cache in the GPU 1310 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the bias table may be maintained entirely within the GPU.

[0229] In at least one embodiment, a bias table entry associated with each access to GPU-biased memory 1320 is accessed prior to the actual access to the GPU memory, resulting in the following actions: In at least one embodiment, a local request from the GPU 1310 to find its page in the GPU bias is forwarded directly to the corresponding GPU memory 1320. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to the processor 1305 (e.g., via the high-speed link described above). In at least one embodiment, a request from the processor 1305 to find the requested page in the host processor bias completes the request similar to a normal memory read. Alternatively, a request directed to a GPU-biased page may be forwarded to the GPU 1310. In at least one embodiment, the GPU may then migrate the page to the host processor bias if it is not currently using the page. In at least one embodiment, the bias state of a page can be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, simply a hardware-based mechanism.

[0230] In at least one embodiment, one mechanism for changing the bias state utilizes an API call (e.g., OpenCL) that calls the GPU's device driver, which sends a message (or queues a command descriptor) to the GPU to change the bias state and, for some transitions, directs the GPU to perform a cache flushing operation in the host. In at least one embodiment, a cache flushing operation is used for transitions from host processor 1305 bias to GPU bias, but not for transitions in the opposite direction.

[0231] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages uncacheable by the host processor 1305. In at least one embodiment, to access these pages, the processor 1305 may request access from the GPU 1310, which may or may not immediately grant the access. Thus, in at least one embodiment, to reduce communication between the processor 1305 and the GPU 1310, it is beneficial to ensure that GPU-biased pages are requested by the GPU but not by the host processor 1305, or vice versa.

[0232] To implement one or more embodiments, a hardware structure 515 is used, details regarding the hardware structure 515 may be provided herein in conjunction with Figures 5A and / or 5B.

[0233] 14 illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral device interface controllers, or general-purpose processor cores.

[0234] 14 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1400 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 1400 includes one or more application processors 1405 (e.g., CPUs), at least one graphics processor 1410, and may further include an image processor 1415 and / or a video processor 1420, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1400 includes a USB controller 1425, a UART controller 1430, an SPI / SDIO controller 1435, and an I / O controller 1440. 2 2S / I 2The integrated circuit 1400 includes peripheral or bus logic including a HDMI™ controller 1440. In at least one embodiment, the integrated circuit 1400 may include a display device 1445 coupled to one or more of a High-Definition Multimedia Interface (HDMI™) controller 1450 and a Mobile Industry Processor Interface (MIPI) display interface 1455. In at least one embodiment, storage may be provided by a flash memory subsystem 1460 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1465 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits further include an embedded security engine 1470.

[0235] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, logic 515 may be used in integrated circuit 1400 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0236] In at least one embodiment, at least one embodiment of FIG. 14 can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify a pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0237] 15A-15B illustrate an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral device interface controllers, or general-purpose processor cores.

[0238] 15A-15B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 15A illustrates an exemplary graphics processor 1510 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores, according to at least one embodiment. FIG. 15B illustrates a further exemplary graphics processor 1540 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the graphics processor 1510 of FIG. 15A is a low-power graphics processor core. In at least one embodiment, the graphics processor 1540 of FIG. 15B is a high-performance graphics processor core. In at least one embodiment, each of the graphics processors 1510, 1540 can be a variation of the graphics processor 1410 of FIG. 14.

[0239] In at least one embodiment, graphics processor 1510 includes vertex processor 1505 and one or more fragment processors 1515A-1515N (e.g., 1515A, 1515B, 1515C, 1515D-1515N-1, and 1515N). In at least one embodiment, graphics processor 1510 can execute different shader programs through separate logic, such that vertex processor 1505 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1515A-1515N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1505 executes the vertex processing stage of a 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, fragment processors 1515A-1515N use the primitive and vertex data generated by vertex processor 1505 to generate a frame buffer that is displayed on a display device. In at least one embodiment, fragment processors 1515A-1515N are optimized to execute fragment shader programs provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0240] In at least one embodiment, graphics processor 1510 further includes one or more memory management units (MMUs) 1520A-1520B, caches 1525A-1525B, and circuit interconnects 1530A-1530B. In at least one embodiment, one or more MMUs 1520A-1520B provide virtual-to-physical address mapping for graphics processor 1510, including vertex processor 1505 and / or fragment processors 1515A-1515N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1525A-1525B. In at least one embodiment, one or more MMUs 1520A-1520B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1405, image processor 1415, and / or video processor 1420 of Figure 14, allowing each processor 1405-1420 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1530A-1530B allow graphics processor 1510 to interface with other IP cores in the SoC via the SoC's internal bus or via a direct connection.

[0241] 15B, graphics processor 1540 includes one or more shader cores 1555A-1555N (e.g., 1555A, 1555B, 1555C, 1555D, 1555E, 1555F-1555N-1, and 1555N), where a single core, or type, or cores provide a unified shader core architecture capable of executing all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, graphics processor 1540 includes an inter-core task manager 1545 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1555A-1555N, and a tiling unit 1558 for accelerating tiling operations for tile-based rendering, where rendering operations of a scene are subdivided in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0242] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, logic 515 may be used in graphics processors 1510 and 1540 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0243] In at least one embodiment, at least one embodiment of FIG. 15A and / or FIG. 15B can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify the pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0244] 16A-16B illustrate further exemplary graphics processor logic according to embodiments described herein. In at least one embodiment, the components illustrated and described in connection with FIGS. 16A-16B are integrated into a single system, such as a graphics processing unit (GPU), SoC, or other type of processor. FIG. 16A illustrates a graphics core 1600, which, in at least one embodiment, may be included in the graphics processor 1410 of FIG. 14 or, in at least one embodiment, may be integrated shader cores 1555A-1555N, as in FIG. 15B. FIG. 16B illustrates a highly parallel general-purpose graphics processing unit ("GPGPU," which may also be referred to as a "graphics processing unit") 1630 suitable for deployment in a multi-chip module in at least one embodiment. In at least one embodiment, the graphics processing unit 1630 is a GPGPU that includes a graphics processor. In at least one embodiment, integrated circuit 1400 includes graphics core 1600, e.g., forming an integrated circuit, and / or such integrated circuit and / or SoC forming an SoC that performs the operations described herein.

[0245] In at least one embodiment, graphics core 1600 includes a shared instruction cache 1602, a texture unit 1618, and cache / shared memory 1620 (e.g., including L1, L2, L3, last level cache, or other caches) that are common to execution resources within graphics core 1600. In at least one embodiment, graphics core 1600 may include multiple slices 1601A-1601N, or partitions per core, and a graphics processor may include multiple instances of graphics core 1600. In at least one embodiment, each slice 1601A-1601N refers to graphics core 1600. In at least one embodiment, slices 1601A-1601N have sub-slices that are part of slices 1601A-1601N. In at least one embodiment, slices 1601A-1601N may be independent of other slices or may be dependent on other slices. In at least one embodiment, slices 1601A-1601N may include support logic including local instruction caches 1604A-1604N, thread schedulers (sequencers) 1606A-1606N, thread dispatchers 1608A-1608N, and sets of registers 1610A-1610N. In at least one embodiment, slices 1601A-1601N may include a set of additional functional units (AFUs 1612A-1612N), floating-point units (FPUs 1614A-1614N), integer arithmetic logic units (ALUs 1616A-1616N), address calculation units (ACUs 1613A-1613N), double-precision floating-point units (DPFPUs 1615A-1615N), and matrix processing units (MPUs 1617A-1617N). In at least one embodiment, MPUs 1617A-1617N are referred to as matrix engines.

[0246] In at least one embodiment, each slice 1601A-1601N includes one or more engines for floating-point and integer vector operations, as well as one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large dataset workloads. In at least one embodiment, one or more slices 1601A-1601N include one or more vector engines for computing vectors (e.g., computing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16-bit floating point (also referred to as "FP16"), 32-bit floating point (also referred to as "FP32"), or 64-bit floating point (also referred to as "FP64"). In at least one embodiment, one or more slices 1601A-1601N include 16 vector engines paired with 16 matrix math units for computing matrix / tensor operations, where the vector engines and math units are exposed via matrix expansion. In at least one embodiment, a slice is a designated portion of a processing unit's processing resources, e.g., 16 cores and a ray tracing unit, or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for the processor. In at least one embodiment, graphics core 1600 includes one or more matrix engines for computing matrix operations, e.g., when computing tensor operations.

[0247] In at least one embodiment, one or more slices 1601A-1601N include one or more ray tracing units (e.g., 16 ray tracing units per slice 1601A-1601N) for computing ray tracing operations. In at least one embodiment, the ray tracing units compute ray traversal, triangle intersection, bounding box intersection, or other ray tracing operations.

[0248] In at least one embodiment, one or more slices 1601A-1601N comprise media slices that encode, decode, and / or transcode data; scale and / or format convert data; and / or perform video quality operations on video data.

[0249] In at least one embodiment, one or more slices 1601A-1601N are linked to an L2 cache and memory fabric, link connectors, a high-bandwidth memory (HBM) (e.g., HBM2e, HDM3) stack, and a media engine. In at least one embodiment, one or more slices 1601A-1601N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1601A-1601N have one or more L1 caches. In at least one embodiment, one or more slices 1601A-1601N include: one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data, e.g., data corresponding to instructions; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometries for performing operations in a geometry pipeline and / or applying geometric transforms to vertices or polygons; one or more rasterizers for describing images in a vector graphics format (e.g., shapes) and converting them into raster images (e.g., a series of pixels, dots, or lines that, when displayed together, create the image represented by the shapes); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, slices 1601A-1601N include a memory fabric, such as an L2 cache.

[0250] In at least one embodiment, the FPUs 1614A-1614N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 1615A-1615N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1616A-1616N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1617A-1617N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPUs 1617A-1617N can perform various matrix operations to accelerate machine learning application frameworks, including being able to support acceleration of general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1612A-1612N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0251] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B. In at least one embodiment, logic 515 may be used in graphics core 1600 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0252] In at least one embodiment, the graphics core 1600 includes an interconnect and link fabric sublayer attached to a switch, and a GPU-GPU bridge that allows multiple graphics processors 1600 (e.g., 8) to be inter-linked using load / store units (LSUs), data transfer units, and synchronization semantics without gluing across the multiple graphics processors 1600. In at least one embodiment, the interconnect includes a standard interconnect (e.g., PCIe) or some combination thereof.

[0253] In at least one embodiment, graphics core 1600 includes multiple tiles. In at least one embodiment, tiles are individual dies or one or more dies where the individual dies may be connected by an interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, graphics core 1600 includes compute tiles, memory tiles (e.g., where memory tiles may be exclusively accessed by different tiles or different chipsets, such as Rambo tiles), substrate tiles, base tiles, HMB tiles, link tiles, and EMIB tiles, all packaged together within graphics core 1600 as part of a GPU. In at least one embodiment, graphics core 1600 may include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a compute tile may include eight graphics cores 1600 and an L1 cache. The base tile can have host interfaces such as PCIe 5.0, HBM2e, MDFI, and EMIB, and the link tile can have eight links and eight ports with an embedded switch. In at least one embodiment, the tiles are connected through fine-pitch, 36-micron microbumps (e.g., copper pillars) with face-to-face (F2F) chip-on-chip bonding. In at least one embodiment, the graphics core 1600 includes a memory fabric, which includes memory and is accessible by multiple tiles. In at least one embodiment, the graphics core 1600 stores, accesses, or loads its own hardware context from memory, where the hardware context is a set of data loaded from registers before a process resumes, and the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0254] In at least one embodiment, graphics core 1600 includes serializer / deserializer (SERDES) circuitry that converts serial data streams to parallel data streams or converts parallel data streams to serial data streams.

[0255] In at least one embodiment, graphics core 1600 includes a high-speed, coherent integrated fabric (GPU-to-GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected through an embedded switch, where the GPU-GPU bridges are controlled by a controller.

[0256] In at least one embodiment, graphics core 1600 executes an API that abstracts the hardware of graphics core 1600 and uses instructions to access libraries to perform mathematical operations (e.g., math kernel libraries), deep neural network operations (e.g., deep neural network libraries), vector operations, collective communication, thread building blocks, video processing, data analytics libraries, and / or ray tracing operations.

[0257] In at least one embodiment, at least one embodiment of FIG. 16A can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify the pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0258] FIG. 16B illustrates a GPGPU 1630, which, in at least one embodiment, can be configured to enable highly parallel computational operations by an array of graphics processing units. In at least one embodiment, the GPGPU 1630 can be directly linked to other instances of the GPGPU 1630 to create multiple GPU clusters to improve the training speed of deep neural networks. In at least one embodiment, the GPGPU 1630 includes a host interface 1632 to enable connection with a host processor. In at least one embodiment, the host interface 1632 is a PCI Express interface. In at least one embodiment, the host interface 1632 can be a vendor-specific communications interface or fabric. In at least one embodiment, the GPGPU 1630 receives commands from the host processor and uses a global scheduler 1634 (which may also be referred to as a thread sequencer and / or asynchronous compute engine) to distribute execution threads associated with those commands to a set of compute clusters 1636A-1636H. In at least one embodiment, compute clusters 1636A-1636H share cache memory 1638. In at least one embodiment, cache memory 1638 can act as a higher-level cache for cache memories within compute clusters 1636A-1636H. In at least one embodiment, compute clusters 1636A-1636H include slices or are referred to as "slices." In at least one embodiment, GPGPU 1630 is part of an SoC, such as part of integrated circuit 1400 (FIG. 14).

[0259] In at least one embodiment, GPGPU 1630 includes memory 1644A-1644B coupled to compute clusters 1636A-1636H via a set of memory controllers 1642A-1642B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 1644A-1644B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as graphics double data rate (GDDR) memory, and synchronous graphics random access memory (SGRAM).

[0260] In at least one embodiment, compute clusters 1636A-1636H each include a set of graphics cores, such as graphics core 1600 of FIG. 16A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 1636A-1636H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0261] In at least one embodiment, multiple instances of GPGPU 1630 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 1636A-1636H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU 1630 communicate through host interface 1632. In at least one embodiment, GPGPU 1630 includes I / O hub 1639, which couples GPGPU 1630 to GPU link 1640, which enables direct connection to other instances of GPGPU 1630. In at least one embodiment, GPU link 1640 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 1630. In at least one embodiment, GPU link 1640 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1630 are located in separate data processing systems and communicate via a network device accessible via host interface 1632. In at least one embodiment, GPU link 1640 can be configured to allow connection to a host processor in addition to, or instead of, host interface 1632.

[0262] In at least one embodiment, the GPGPU 1630 can be configured to train a neural network. In at least one embodiment, the GPGPU 1630 can be used within an inference platform. In at least one embodiment, when the GPGPU 1630 is used for inference, the GPGPU 1630 may include fewer compute clusters 1636A-1636H than when the GPGPU 1630 is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 1644A-1644B may differ between the inference configuration and the training configuration, with higher-bandwidth memory technology being devoted to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1630 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can support one or more 8-bit integer dot-product instructions, which may be used during inference operations of a deployed neural network.

[0263] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, logic 515 may be used in GPGPU 1630 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0264] In at least one embodiment, at least one embodiment of FIG. 16B can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify the pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0265] 17 is a block diagram illustrating a computing system 1700 according to at least one embodiment. In at least one embodiment, computing system 1700 includes a processing subsystem 1701 having one or more processors 1702 and system memory 1704 that communicate via an interconnection path that may include a memory hub 1705. In at least one embodiment, memory hub 1705 may be a separate component within a chipset component or may be integrated within one or more processors 1702. In at least one embodiment, memory hub 1705 is coupled to an I / O subsystem 1711 via communication link 1706. In at least one embodiment, I / O subsystem 1711 includes an I / O hub 1707 that can enable computing system 1700 to receive input from one or more input devices 1708. In at least one embodiment, I / O hub 1707 can enable a display controller, which may be included in one or more processors 1702 and provide output to one or more display devices 1710A. In at least one embodiment, the one or more display devices 1710A coupled to I / O hub 1707 can include local, internal, or embedded display devices.

[0266] In at least one embodiment, processing subsystem 1701 includes one or more parallel processors 1712 coupled to memory hub 1705 via a bus or other communication link 1713. In at least one embodiment, communication link 1713 may use one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In at least one embodiment, one or more parallel processors 1712 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, some or all of parallel processors 1712 form a graphics processing subsystem that can output pixels to one of one or more display devices 1710A coupled via I / O hub 1707. In at least one embodiment, parallel processor 1712 also includes a display controller and display interface (not shown) that enables direct connection to one or more display devices 1710B. In at least one embodiment, parallel processor 1712 includes one or more cores, such as graphics core 1600 discussed herein.

[0267] In at least one embodiment, system storage unit 1714 may be connected to I / O hub 1707 to provide a storage mechanism for computing system 1700. In at least one embodiment, I / O switch 1716 may be used to provide an interface mechanism to enable communication between I / O hub 1707 and other components, such as network adapter 1718 and / or wireless network adapter 1719, which may be integrated into the platform, as well as various other devices that may be added via one or more add-in devices 1720. In at least one embodiment, network adapter 1718 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1719 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0268] In at least one embodiment, computing system 1700 may include other components not shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1707. In at least one embodiment, the communication paths interconnecting the various components of FIG. 17 may be implemented using any suitable protocol, such as a Peripheral Component Interconnect (PCI)-based protocol (e.g., PCI-Express), or other bus or point-to-point communication interface and / or protocol, such as the NV-Link high-speed interconnect, or interconnection protocol.

[0269] In at least one embodiment, parallel processor 1712 incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry, forming a graphics processing unit (GPU), e.g., parallel processor 1712 includes graphics core 1600. In at least one embodiment, parallel processor 1712 incorporates circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 1700 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processor 1712, memory hub 1705, processor 1702, and I / O hub 1707 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, components of computing system 1700 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1700 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0270] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, logic 515 may be used in computing system 1700 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0271] In at least one embodiment, at least one embodiment of FIG. 17 can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify the pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0272] Processor 18A illustrates a parallel processor 1800 according to at least one embodiment. In at least one embodiment, various components of parallel processor 1800 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 1800 is a variation of one or more parallel processors 1712 shown in FIG. 17 according to an example embodiment. In at least one embodiment, parallel processor 1800 includes one or more graphics cores 1600.

[0273] In at least one embodiment, parallel processor 1800 includes parallel processing units 1802. In at least one embodiment, parallel processing units 1802 include I / O units 1804 that enable communication with other devices, including other instances of parallel processing units 1802. In at least one embodiment, I / O units 1804 may be directly connected to other devices. In at least one embodiment, I / O units 1804 are connected to other devices through the use of a hub or switch interface, such as memory hub 1805. In at least one embodiment, the connection between memory hub 1805 and I / O units 1804 forms communication link 1813. In at least one embodiment, I / O units 1804 are connected to host interface 1806 and memory crossbar 1816, where host interface 1806 receives commands directed to the execution of processing operations and memory crossbar 1816 receives commands directed to the execution of memory operations.

[0274] In at least one embodiment, when host interface 1806 receives command buffers via I / O unit 1804, host interface 1806 can direct work operations to execute these commands to front end 1808. In at least one embodiment, front end 1808 is coupled to scheduler 1810 (which may also be referred to as a sequencer), which is configured to distribute commands or other work items to processing cluster array 1812. In at least one embodiment, scheduler 1810 ensures that processing cluster array 1812 is properly configured and in a valid state before tasks are distributed to clusters in processing cluster array 1812. In at least one embodiment, scheduler 1810 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1810 is configurable to perform complex scheduling and work distribution operations at both coarse and fine granularities, enabling rapid preemption and context switching of threads executing in the processing array 1812. In at least one embodiment, host software can direct scheduling workloads in the processing cluster array 1812 through one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed across the processing array clusters 1812 by scheduler 1810 logic in the microcontroller that includes the scheduler 1810.

[0275] In at least one embodiment, processing cluster array 1812 can include up to “N” processing clusters (e.g., cluster 1814A, cluster 1814B through cluster 1814N), where “N” represents a positive integer (although “N” may be a different integer than used in other figures). In at least one embodiment, each cluster 1814A through 1814N of processing cluster array 1812 can execute a large number of concurrent threads. In at least one embodiment, scheduler 1810 can allocate work to clusters 1814A through 1814N of processing cluster array 1812 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 1810 or may be partially assisted by compiler logic during compilation of program logic configured to be executed by processing cluster array 1812. In at least one embodiment, different clusters 1814A-1814N of processing cluster array 1812 may be allocated to process different types of programs or perform different types of calculations.

[0276] In at least one embodiment, processing cluster array 1812 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 1812 may be configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 1812 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0277] In at least one embodiment, the processing cluster array 1812 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 1812 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as mosaic logic and other vertex processing logic. In at least one embodiment, the processing cluster array 1812 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, mosaic shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 1802 may transfer data from system memory via the I / O unit 1804 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1822) during processing and then written back to system memory.

[0278] In at least one embodiment, when graphics processing is performed using parallel processing unit 1802, scheduler 1810 can be configured to divide the processing workload into roughly equal-sized tasks to better distribute graphics processing operations among multiple clusters 1814A-1814N of processing cluster array 1812. In at least one embodiment, portions of processing cluster array 1812 can be configured to perform different types of processing. For example, in at least one embodiment, to generate and display a rendered image, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform mosaic and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data generated by one or more of clusters 1814A-1814N may be stored in a buffer so that the intermediate data can be transmitted between clusters 1814A-1814N for further processing.

[0279] In at least one embodiment, the processing cluster array 1812 can receive processing tasks to be performed via a scheduler 1810, which receives commands defining the processing tasks from the front end 1808. In at least one embodiment, a processing task can include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., which program to execute). In at least one embodiment, the scheduler 1810 can be configured to fetch the index corresponding to the task or can receive the index from the front end 1808. In at least one embodiment, the front end 1808 can be configured to ensure that the processing cluster array 1812 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0280] In at least one embodiment, each of one or more instances of parallel processing unit 1802 can be coupled to parallel processor memory 1822. In at least one embodiment, parallel processor memory 1822 can be accessed via memory crossbar 1816, which can receive memory requests from processing cluster array 1812 as well as I / O unit 1804. In at least one embodiment, memory crossbar 1816 can access parallel processor memory 1822 via memory interface 1818. In at least one embodiment, memory interface 1818 can include multiple partition units (e.g., partition unit 1820A, partition unit 1820B through partition unit 1820N), each of which can be coupled to a portion (e.g., a memory unit) of parallel processor memory 1822. In at least one embodiment, the number of partition units 1820A-1820N is configured to be equal to the number of memory units, such that a first partition unit 1820A has a corresponding first memory unit 1824A, a second partition unit 1820B has a corresponding memory unit 1824B, and an Nth partition unit 1820N has a corresponding Nth memory unit 1824N. In at least one embodiment, the number of partition units 1820A-1820N does not have to be equal to the number of memory units.

[0281] In at least one embodiment, memory units 1824A-1824N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1824A-1824N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM), HBM2e, or HDM3. In at least one embodiment, to efficiently use the available bandwidth of parallel processor memory 1822, render targets, such as frame buffers or texture maps, may be stored across memory units 1824A-1824N, allowing partition units 1820A-1820N to write portions of each render target in parallel. In at least one embodiment, the local instance of parallel processor memory 1822 may be omitted in favor of a unified memory design that uses both system memory and local cache memory.

[0282] In at least one embodiment, any one of the clusters 1814A-1814N in the processing cluster array 1812 can process data that is to be written to any one of the memory units 1824A-1824N in the parallel processor memory 1822. In at least one embodiment, the memory crossbar 1816 can be configured to forward the output of each cluster 1814A-1814N to any partition unit 1820A-1820N or to another cluster 1814A-1814N that can perform further processing operations on the output. In at least one embodiment, each cluster 1814A-1814N can communicate with a memory interface 1818 through the memory crossbar 1816 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 1816 has connections to memory interface 1818 for communicating with I / O unit 1804, as well as connections to local instances of parallel processor memory 1822, allowing processing units in different processing clusters 1814A-1814N to communicate with system memory or other memory not local to parallel processing unit 1802. In at least one embodiment, memory crossbar 1816 can use virtual channels to separate traffic streams between clusters 1814A-1814N and partition units 1820A-1820N.

[0283] In at least one embodiment, multiple instances of parallel processing unit 1802 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 1802 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other different configurations. For example, in at least one embodiment, some instances of parallel processing unit 1802 may include higher precision floating-point units than other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 1802 or parallel processor 1800 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or portable personal computers, servers, workstations, game consoles, and / or embedded systems.

[0284] FIG. 18B is a block diagram of a partition unit 1820 according to at least one embodiment. In at least one embodiment, partition unit 1820 is an instance of one of partition units 1820A-1820N of FIG. 18A. In at least one embodiment, partition unit 1820 includes an L2 cache 1821, a frame buffer interface 1825, and a raster operations unit (ROP) 1826. In at least one embodiment, L2 cache 1821 is a read / write cache configured to execute load and store operations received from memory crossbar 1816 and ROP 1826. In at least one embodiment, read misses and urgent writeback requests are output by L2 cache 1821 to frame buffer interface 1825 for processing. In at least one embodiment, updates can also be sent to the frame buffer via frame buffer interface 1825 for processing. In at least one embodiment, frame buffer interface 1825 interfaces with one of the memory units of a parallel processor memory, such as memory units 1824A-1824N (e.g., in parallel processor memory 1822) of FIG. 18A.

[0285] In at least one embodiment, ROP1826 is a processing unit that performs raster operations such as stencil, z-test, and blending. In at least one embodiment, ROP1826 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, ROP1826 includes compression logic for compressing depth or color data being written to memory and decompressing depth or color data being read from memory. In at least one embodiment, the compression logic may be lossless compression logic that utilizes one or more of a number of compression algorithms. In at least one embodiment, the type of compression performed by ROP1826 may be varied based on statistical characteristics of the data being compressed. For example, in at least one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

[0286] In at least one embodiment, ROP 1826 is included within each processing cluster (e.g., clusters 1814A-1814N of FIG. 18A ) instead of within partition unit 1820. In at least one embodiment, read and write requests for pixel data, instead of pixel fragment data, are transmitted through memory crossbar 1816. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 1710 of FIG. 17 , routed for further processing by processor 1702, or routed for further processing by one of the processing entities in parallel processor 1800 of FIG. 18A .

[0287] FIG. 18C is a block diagram of a processing cluster 1814 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of the processing clusters 1814A-1814N of FIG. 18A. In at least one embodiment, the processing cluster 1814 may be configured to execute multiple threads in parallel, where a "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0288] In at least one embodiment, operation of the processing clusters 1814 may be controlled via a pipeline manager 1832, which distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 1832 receives instructions from the scheduler 1810 of FIG. 18A and manages the execution of those instructions via the graphics multiprocessor 1834 and / or the texture unit 1836. In at least one embodiment, the graphics multiprocessor 1834 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing clusters 1814. In at least one embodiment, one or more instances of the graphics multiprocessor 1834 may be included within the processing clusters 1814. In at least one embodiment, the graphics multiprocessor 1834 may process data, and a data crossbar 1840 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 1832 can facilitate distribution of the processed data by specifying destinations for the processed data to be distributed through the data crossbar 1840.

[0289] In at least one embodiment, each graphics multiprocessor 1834 in a processing cluster 1814 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, allowing new instructions to be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0290] In at least one embodiment, instructions sent to a processing cluster 1814 constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, the thread groups execute a common program on different input data. In at least one embodiment, each thread in a thread group can be assigned to a different processing engine in the graphics multiprocessor 1834. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in the graphics multiprocessor 1834. In at least one embodiment, if a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in the graphics multiprocessor 1834. In at least one embodiment, if a thread group includes more threads than the number of processing engines in the graphics multiprocessor 1834, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on the graphics multiprocessor 1834.

[0291] In at least one embodiment, the graphics multiprocessor 1834 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1834 can forgo the internal cache and use cache memory (e.g., L1 cache 1848) within the processing cluster 1814. In at least one embodiment, each graphics multiprocessor 1834 can also access an L2 cache within a partition unit (e.g., partition units 1820A-1820N in FIG. 18A ), which may be shared among all processing clusters 1814 and used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 1834 can also access off-chip global memory, which may include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing units 1802 may be used as global memory. In at least one embodiment, processing cluster 1814 may include multiple instances of graphics multiprocessor 1834 and share common instructions and data, which may be stored in L1 cache 1848.

[0292] In at least one embodiment, each processing cluster 1814 may include an MMU 1845 (memory management unit) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1845 may reside within memory interface 1818 of FIG. 18A . In at least one embodiment, MMU 1845 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses of tiles and optionally cache line indexes. In at least one embodiment, MMU 1845 may include an address translation lookaside buffer (TLB) or cache, which may reside within graphics multiprocessor 1834 or L1 1848 cache, or processing cluster 1814. In at least one embodiment, physical addresses are processed to locally distribute surface data accesses, allowing efficient interleaving of requests across partition units. In at least one embodiment, the cache line index may be used to determine whether a cache line request is a hit or a miss.

[0293] In at least one embodiment, processing cluster 1814 may be configured such that each graphics multiprocessor 1834 is coupled to a texture unit 1836 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 1834 and, as needed, fetched from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1834 outputs processed tasks to data crossbar 1840 to provide the processed tasks to another processing cluster 1814 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 1816. In at least one embodiment, a pre-ROP 1842 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 1834 and direct the data to the ROP units, which may be located in partition units (e.g., partition units 1820A-1820N in FIG. 18A ) as described herein. In at least one embodiment, the pre-ROP 1842 unit can perform color blending optimizations, organize pixel color data, and perform address translation.

[0294] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B. In at least one embodiment, logic 515 may be used in graphics processing cluster 1814 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0295] In at least one embodiment, at least one embodiment of Figures 18A, 18B, and / or 18C may include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify a pose of one or more cameras based, at least in part, on one or more different poses of one or more cameras and / or based on any other embodiment discussed above with respect to Figures 1-4.

[0296] FIG. 18D illustrates a graphics multiprocessor 1834 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 1834 couples with a pipeline manager 1832 of a processing cluster 1814. In at least one embodiment, the graphics multiprocessor 1834 has an execution pipeline including, but not limited to, an instruction cache 1852, an instruction unit 1854, an address mapping unit 1856, a register file 1858, one or more general-purpose graphics processing unit (GPGPU) cores 1862, and one or more load / store units 1866, where the one or more load / store units 1866 can perform load / store operations to load / store instructions corresponding to execution of the operations. In at least one embodiment, the GPGPU cores 1862 and the load / store units 1866 are coupled to a cache memory 1872 and a shared memory 1870 via a memory and cache interconnect 1868. In at least one embodiment, GPGPU core 1862 is part of an SoC, such as part of integrated circuit 1400 of FIG.

[0297] In at least one embodiment, instruction cache 1852 receives a stream of instructions to execute from pipeline manager 1832. In at least one embodiment, instructions are cached in instruction cache 1852 and dispatched for execution by instruction unit 1854. In at least one embodiment, instruction unit 1854 can dispatch instructions as thread groups (e.g., warps, wavefronts, waves), with each thread of a thread group assigned to a different execution unit within GPGPU core 1862. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying addresses in the unified address space. In at least one embodiment, address mapping unit 1856 can be used to translate addresses in the unified address space into individual memory addresses accessible by load / store unit 1866.

[0298] In at least one embodiment, register file 1858 provides a set of registers to the functional units of graphics multiprocessor 1834. In at least one embodiment, register file 1858 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 1862, load / store unit 1866) of graphics multiprocessor 1834. In at least one embodiment, register file 1858 is partitioned among the respective functional units, with each functional unit allocated a dedicated portion of register file 1858. In at least one embodiment, register file 1858 is partitioned among the different warps (which may also be referred to as wavefronts and / or waves) being executed by graphics multiprocessor 1834.

[0299] In at least one embodiment, GPGPU cores 1862 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions for graphics multiprocessor 1834. In at least one embodiment, GPGPU cores 1862 may have similar or different architectures. In at least one embodiment, a first portion of GPGPU core 1862 includes a single-precision FPU and an integer ALU, and a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement IEEE 754-2008 standard floating-point arithmetic or may enable variable-precision floating-point arithmetic. In at least one embodiment, graphics multiprocessor 1834 may further include one or more fixed-function or special-function units for performing specific functions, such as rectangle copy or pixel blending operations. In at least one embodiment, one or more of GPGPU cores 1862 may also include fixed or special-function logic.

[0300] In at least one embodiment, GPGPU core 1862 includes SIMD logic capable of executing a single instruction on multiple data sets. In at least one embodiment, GPGPU core 1862 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for the GPGPU core may be generated at compile time by a shader compiler or may be generated automatically when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may execute via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may execute in parallel via a single SIMD8 logical unit.

[0301] In at least one embodiment, memory and cache interconnect 1868 is an interconnect network connecting each functional unit of graphics multiprocessor 1834 to register file 1858 and shared memory 1870. In at least one embodiment, memory and cache interconnect 1868 is a crossbar interconnect that allows load / store unit 1866 to implement load and store operations between shared memory 1870 and register file 1858. In at least one embodiment, register file 1858 can operate at the same frequency as GPGPU cores 1862, and therefore data transfers between GPGPU cores 1862 and register file 1858 can have very low latency. In at least one embodiment, shared memory 1870 can be used to enable communication between threads executing in functional units within graphics multiprocessor 1834. In at least one embodiment, cache memory 1872 can be used, for example, as a data cache to cache texture data communicated between functional units and texture unit 1836. In at least one embodiment, shared memory 1870 can also be used as a program-managed cache. In at least one embodiment, threads running on GPGPU cores 1862 can programmatically store data in the shared memory in addition to automatically caching data stored in cache memory 1872.

[0302] In at least one embodiment, a parallel processor or GPGPU described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, a GPU may be communicatively coupled to a host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, an SoC includes a parallel processor or GPGPU described herein, and the parallel processor or GPGPU executes on the SoC. In at least one embodiment, a GPU may be integrated into a package or chip as a core, or may be communicatively coupled to a core via an internal processor bus / interconnect within the package or chip. In at least one embodiment, regardless of how the GPU is connected, a processor core may allocate work to such a GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0303] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B. In at least one embodiment, logic 515 may be used in graphics multiprocessor 1834 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0304] In at least one embodiment, at least one embodiment of FIG. 18D can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify the pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0305] FIG. 19 illustrates a multi-GPU computing system 1900, according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 1900 may include a processor 1902 coupled to multiple general-purpose graphics processing units (GPGPUs) 1906A-D via a host interface switch 1904. In at least one embodiment, the host interface switch 1904 is a PCI Express switch device that couples the processor 1902 to a PCI Express bus, via which the processor 1902 can communicate with the GPGPUs 1906A-D. In at least one embodiment, the GPGPUs 1906A-D may be interconnected via a set of high-speed, point-to-point GPU-to-GPU links 1916. In at least one embodiment, the GPU-to-GPU links 1916 are connected to each of the GPGPUs 1906A-D via dedicated GPU links. In at least one embodiment, P2P GPU link 1916 allows direct communication between each of GPGPUs 1906A-D without requiring communication through host interface bus 1904 to which processor 1902 is connected. In at least one embodiment, GPU-to-GPU traffic directed to P2P GPU link 1916 keeps host interface bus 1904 available for access to system memory or for communication with other instances of multi-GPU computing system 1900, for example, via one or more network devices. While in at least one embodiment, GPGPUs 1906A-D connect to processor 1902 through host interface switch 1904, in at least one embodiment, processor 1902 includes direct support for P2P GPU link 1916 and can connect directly to GPGPUs 1906A-D. In at least one embodiment, GPGPUs 1906A-D are part of an SoC, such as part of integrated circuit 1400 of FIG. 14, and GPGPUs 1906A-D perform the operations described herein.

[0306] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, logic 515 may be used in multi-GPU computing system 1900 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0307] In at least one embodiment, the multi-GPU computing system 1900 includes one or more graphics cores 1600.

[0308] In at least one embodiment, at least one embodiment of FIG. 19 can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify the pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0309] FIG. 20 is a block diagram of a graphics processor 2000 according to at least one embodiment. In at least one embodiment, the graphics processor 2000 includes a ring interconnect 2002, a pipeline front end 2004, a media engine 2037, and graphics cores 2080A-2080N. In at least one embodiment, the ring interconnect 2002 couples the graphics processor 2000 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2000 is one of multiple processors integrated within a multi-core processing system. In at least one embodiment, the graphics processor 2000 includes the graphics core 1600.

[0310] In at least one embodiment, graphics processor 2000 receives batches of commands via ring interconnect 2002. In at least one embodiment, the incoming commands are interpreted by command streamer 2003 of pipeline front end 2004. In at least one embodiment, graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2080A-2080N. In at least one embodiment, for 3D geometry processing commands, command streamer 2003 supplies the commands to geometry pipeline 2036. In at least one embodiment, for at least some media processing commands, command streamer 2003 supplies the commands to video front end 2034, which is coupled to media engine 2037. In at least one embodiment, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing and a multi-format encode / decode (MFX) 2033 engine that provides hardware-accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2036 and the media engine 2037 each spawn execution threads for thread execution resources provided by at least one graphics core 2080.

[0311] In at least one embodiment, graphics processor 2000 includes scalable thread execution resources characterized by graphics cores 2080A-2080N (which may be modular and sometimes referred to as core slices), each of which has multiple sub-cores 2050A-2050N, 2060A-2060N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2000 can have any number of graphics cores 2080A. In at least one embodiment, graphics processor 2000 includes a graphics core 2080A having at least a first sub-core 2050A and a second sub-core 2060A. In at least one embodiment, graphics processor 2000 is a low-power processor having a single sub-core (e.g., 2050A). In at least one embodiment, graphics processor 2000 includes multiple graphics cores 2080A-2080N, each including a set of first sub-cores 2050A-2050N and a set of second sub-cores 2060A-2060N. In at least one embodiment, each of first sub-cores 2050A-2050N includes at least a first set of execution units 2052A-2052N and media / texture samplers 2054A-2054N. In at least one embodiment, each of second sub-cores 2060A-2060N includes at least a second set of execution units 2062A-2062N and samplers 2064A-2064N. In at least one embodiment, each sub-core 2050A-2050N, 2060A-2060N shares a set of shared resources 2070A-2070N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic. In at least one embodiment, graphics processor 2000 includes a load / store unit in pipeline front end 2004.

[0312] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, logic 515 may be used in graphics processor 2000 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0313] In at least one embodiment, at least one embodiment of FIG. 20 can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify the pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0314] FIG. 21 is a block diagram illustrating the micro-architecture of a processor 2100 that may include logic circuitry for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2100 can execute instructions including x86 instructions, ARM instructions, instructions specialized for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2100 may include registers for storing packed data, such as 64-bit wide MMX registers of a microprocessor that supports MMX™ technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available for both integer and floating-point types, can operate using packed data elements associated with Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extension (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, the processor 2100 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0315] In at least one embodiment, processor 2100 includes an in-order front end (“front end”) 2101 that fetches instructions to be executed and prepares the instructions for later use in the processor pipeline. In at least one embodiment, front end 2101 may include several units. In at least one embodiment, an instruction prefetcher 2126 fetches instructions from memory and provides the instructions to an instruction decoder 2128, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2128 decodes received instructions into one or more operations, called “microinstructions” or “micro-operations” (also called “micro-ops” or “uops” or “μ-ops”), that the machine can execute. In at least one embodiment, instruction decoder 2128 parses instructions into opcodes and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, trace cache 2130 may assemble the decoded uops into program-order sequences, or traces, for execution in uop queue 2134. In at least one embodiment, when trace cache 2130 encounters a complex instruction, microcode ROM 2132 provides the uops necessary to complete the operation.

[0316] In at least one embodiment, some instructions can be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if an instruction requires more than four micro-ops to complete, the instruction decoder 2128 may access the microcode ROM 2132 to execute the instruction. In at least one embodiment, the instruction may be decoded into a smaller number of micro-ops for processing in the instruction decoder 2128. In at least one embodiment, if a large number of micro-ops are required to complete such an operation, the instruction may be stored in the microcode ROM 2132. In at least one embodiment, the trace cache 2130 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer to read the microcode sequence from to complete one or more instructions from the microcode ROM 2132, in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 2132 finishes sequencing micro-ops for an instruction, the machine front end 2101 may resume fetching micro-ops from the trace cache 2130.

[0317] In at least one embodiment, out-of-order execution engine ("out-of-order engine") 2103 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the flow of instructions to optimize performance as instructions are scheduled for execution down the pipeline. In at least one embodiment, out-of-order execution engine 2103 includes, without limitation, allocator / register renamer 2140, memory uop queue 2142, integer / floating point uop queue 2144, memory scheduler 2146, fast scheduler 2102, slow / general purpose floating point scheduler ("slow / general purpose FP scheduler") 2104, and simple floating point scheduler ("simple FP scheduler") 2106. In at least one embodiment, fast scheduler 2102, slow / general purpose floating point scheduler 2104, and simple floating point scheduler 2106 are also collectively referred to herein as "uop schedulers 2102, 2104, 2106." In at least one embodiment, allocator / register renamer 2140 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, allocator / register renamer 2140 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 2140 also allocates each uop's entry to one of two uop queues—memory uop queue 2142 for memory operations and integer / floating point uop queue 2144 for non-memory operations—before memory scheduler 2146 and uop schedulers 2102, 2104, 2106. In at least one embodiment, uop schedulers 2102, 2104, 2106 determine when uops are ready to execute based on the readiness of the sources of their dependent input register operands and the availability of the execution resources required by the uop to complete their operations.In at least one embodiment, the fast scheduler 2102 may schedule every half of the main clock cycle, and the slow / general purpose floating point scheduler 2104 and simple floating point scheduler 2106 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2102, 2104, 2106 arbitrate for dispatch ports to schedule uops for execution.

[0318] In at least one embodiment, execution block 2111 includes, without limitation, integer register file / bypass network 2108, floating point register file / bypass network (“FP register file / bypass network”) 2110, address generation units (“AGUs”) 2112 and 2114, fast arithmetic logic units (ALUs) (“fast ALUs”) 2116 and 2118, slower arithmetic logic unit (“slower ALU”) 2120, floating point ALU (“FP”) 2122, and floating point move unit (“FP move”) 2124. In at least one embodiment, integer register file / bypass network 2108 and floating point register file / bypass network 2110 are also referred to herein as “register files 2108, 2110.” In at least one embodiment, AGUS 2112 and 2114, fast ALUs 2116 and 2118, slow ALU 2120, floating-point ALU 2122, and floating-point move unit 2124 are also referred to herein as "execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124." In at least one embodiment, execution block 2111 may include any number and type of register files (including zero), bypass networks, address generation units, and execution units, in any combination, without limitation.

[0319] In at least one embodiment, register networks 2108, 2110 may be disposed between uop schedulers 2102, 2104, 2106 and execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124. In at least one embodiment, integer register file / bypass network 2108 performs integer operations. In at least one embodiment, floating point register file / bypass network 2110 performs floating point operations. In at least one embodiment, each of register networks 2108, 2110 may include, without limitation, a bypass network, which may bypass or forward recently completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, register networks 2108, 2110 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2108 may include, without limitation, two separate register files: one register file for the lower 32-bit data and a second register file for the higher 32-bit data. In at least one embodiment, floating-point instructions typically have operands that are 64-128 bits wide, so floating-point register file / bypass network 2110 may include, without limitation, 128-bit wide entries.

[0320] In at least one embodiment, execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124 may execute instructions. In at least one embodiment, register networks 2108 and 2110 store integer and floating-point data operand values ​​required by microinstructions to execute. In at least one embodiment, processor 2100 may include any number and combination of execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124, without limitation. In at least one embodiment, floating-point ALU 2122 and floating-point move unit 2124 may perform floating-point, MMX, SIMD, AVX, and SSE, or other operations, including special machine learning instructions. In at least one embodiment, the floating-point ALU 2122 may include, without limitation, a 64-bit floating-point divider to perform division, square root, and remaining micro-ops. In at least one embodiment, instructions involving floating-point values ​​may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the high-speed ALUs 2116, 2118. In at least one embodiment, the high-speed ALUs 2116, 2118 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the low-speed ALU 2120 may include, without limitation, integer execution hardware for long-latency type operations such as multipliers, shifts, flag logic, and branching, with most complex integer operations proceeding to the low-speed ALU 2120. In at least one embodiment, memory load / store operations may be performed by the AGUs 2112, 2114. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 may be implemented to support a variety of data bit sizes, including 16, 32, 128, 256, etc.In at least one embodiment, floating-point ALU 2122 and floating-point move unit 2124 may be implemented to support a range of operands having various bit widths, such as 128-bit wide packed data operands, in conjunction with SIMD and multimedia instructions.

[0321] In at least one embodiment, the uop schedulers 2102, 2104, 2106 dispatch dependent operations before the parent load finishes execution. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 2100, the processor 2100 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline past the scheduler that have temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the incorrect data. In at least one embodiment, the dependent operations may need to be replayed, and the independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of a processor may also be designed to capture instruction sequences for text string comparison operations.

[0322] In at least one embodiment, a "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, or perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0323] In at least one embodiment, processor 2100, or each core of processor 2100, includes one or more prefetchers, one or more fetchers, one or more predecoders, one or more decoders for decoding data (e.g., instructions), one or more instruction queues for processing instructions (e.g., corresponding to operations or API calls), one or more micro-op caches for storing micro-ops (uops), one or more micro-op (uop) queues, an in-order execution engine, one or more load buffers, one or more store buffers, one or more reorder buffers, one or more fill buffers, an out-of-order execution engine, one or more ports, one or more shift and / or shifter units, one or more fused multiply-add (FMA) ... processor 2100 may include one or more load-store units ("LSUs") for performing load store operations corresponding to loading / storing data (e.g., instructions) to perform operations (e.g., executing an API, API call), one or more matrix multiply accumulate (MMA) units, and / or one or more shuffle units for performing any of the functions further described herein for said processor 2100. In at least one embodiment, processor 2100 may access, use, implement, or execute instructions corresponding to calling an API.

[0324] In at least one embodiment, processor 2100 includes one or more Ultra Path Interconnects (UPIs), e.g., point-to-point processor interconnects; one or more PCIe interfaces; one or more accelerators for accelerating calculations or operations; and / or one or more memory controllers. In at least one embodiment, processor 2100 includes a shared last level cache (LLC) coupled to the one or more memory controllers, which enables shared memory access across processor cores.

[0325] In at least one embodiment, the processor 2100 or cores of the processor 2100 have a mesh architecture in which the processor cores, on-chip caches, memory controllers, and I / O controllers are organized into rows and columns, connected at each intersection using wires and switches to enable turns. In at least one embodiment, the processor 2100 has one or more high-bandwidth memory modules (HMBs, e.g., HMBe) that store or cache data, for example, in Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM). In at least one embodiment, one or more components of the processor 2100 are interconnected using a Compute Express Link (CXL) interconnect. In at least one embodiment, the memory controller uses a "least recently used" (LRU) approach to determine what has been stored in the cache. In at least one embodiment, the processor 2100 includes one or more PCIe (e.g., PCIe 5.0) interfaces.

[0326] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B . In at least one embodiment, some or all of logic 515 may be incorporated into execution block 2111 and other memory or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs shown in execution block 2111. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution block 2111 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0327] In at least one embodiment, at least one embodiment of FIG. 21 can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify the pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0328] 22 illustrates a deep learning application processor 2200 according to at least one embodiment. In at least one embodiment, the deep learning application processor 2200 uses instructions that, when executed by the deep learning application processor 2200, cause the deep learning application processor 2200 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2200 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 2200 performs matrix multiplication operations, all of which are "hardwired" into hardware, as a result of executing one or more instructions or both. In at least one embodiment, deep learning application processor 2200 includes, without limitation, processing clusters 2210(1)-2210(12), inter-chip links (“ICLs”) 2220(1)-2220(12), inter-chip controllers (“ICCs”) 2230(1)-2230(2), high-bandwidth memory second generation (“HBM2”) 2240(1)-2240(4), memory controllers (“Mem Ctrlrs”) 2242(1)-2242(4), high-bandwidth memory physical layers (“HBM PHYs”) 2244(1)-2244(4), management-controller central processing unit (“management-controller CPU”) 2250, serial peripheral interfaces, inter-integrated circuit, and general-purpose input / output blocks (“SPIs”). 2 22. The peripheral component interconnect express controller and direct memory access block ("PCIe Controller and DMA") 2270 includes a 16-lane peripheral component interconnect express port ("PCI Express x16") 2280.

[0329] In at least one embodiment, processing cluster 2210 may perform deep learning operations, including inference or prediction operations, based on weight parameters calculated using one or more training techniques, including the techniques described herein. In at least one embodiment, each processing cluster 2210 may include any number and type of processors, without limitation. In at least one embodiment, deep learning application processor 2200 may include any number and type of processing clusters 2200. In at least one embodiment, inter-chip link 2220 is bidirectional. In at least one embodiment, inter-chip link 2220 and inter-chip controller 2230 enable multiple deep learning application processors 2200 to exchange information, including activation information resulting from running one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2200 may include any number and type (including zero) of ICLs 2220 and ICCs 2230.

[0330] In at least one embodiment, the HBM2 2240 provides a total of 32 Gigabytes (GB) of memory. In at least one embodiment, an HBM2 2240(i) is associated with both a memory controller 2242(i) and an HBM PHY 2244(i), where "i" is any integer. In at least one embodiment, any number of HBM2s 2240 may provide any type and total amount of high-bandwidth memory and may be associated with any number and type of memory controllers 2242 and HBM PHYs 2244 (including zero). In at least one embodiment, the SPI, I 2 C, GPIO 2260, PCIe controller and DMA 2270, and / or PCIe 2280 may be replaced with any number and types of blocks enabling any number and types of communication standards in any technically feasible manner.

[0331] Logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B. In at least one embodiment, the deep learning application processor 2200 is used to train a machine learning model, such as a neural network, to predict or infer information provided to the deep learning application processor 2200. In at least one embodiment, the deep learning application processor 2200 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2200. In at least one embodiment, the processor 2200 may be used to perform one or more neural network use cases described herein.

[0332] In at least one embodiment, at least one embodiment of FIG. 22 can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify the pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0333] FIG. 23 is a block diagram of a neuromorphic processor 2300, according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2300 may receive one or more inputs from sources external to the neuromorphic processor 2300. In at least one embodiment, these inputs may be sent to one or more neurons 2302 within the neuromorphic processor 2300. In at least one embodiment, the neurons 2302 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2300 may include, without limitation, thousands or millions of instances of neurons 2302, although any suitable number of neurons 2302 may be used. In at least one embodiment, each instance of a neuron 2302 may include a neuron input 2304 and a neuron output 2306. In at least one embodiment, neuron 2302 may generate an output, which may be sent to an input of another instance of neuron 2302. For example, in at least one embodiment, neuron input 2304 and neuron output 2306 may be interconnected via synapse 2308.

[0334] In at least one embodiment, neurons 2302 and synapses 2308 may be interconnected such that neuromorphic processor 2300 operates to process or analyze information received by neuromorphic processor 2300. In at least one embodiment, neuron 2302 may send an output pulse (or "fire" or "spike") when input received via neuron input 2304 exceeds a threshold. In at least one embodiment, neuron 2302 may sum or integrate signals received at neuron input 2304. For example, in at least one embodiment, neuron 2302 may be implemented as a leaky integrate-and-fire neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, neuron 2302 may generate an output (or "fire") using a transfer function such as a sigmoid function or a threshold function. In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron input 2304 into a membrane potential and may apply a decay factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire if multiple input signals are received at neuron input 2304 quickly enough to exceed a threshold (i.e., before the membrane potential decays too little to cause firing). In at least one embodiment, neuron 2302 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Further, in at least one embodiment, neuron 2302 may include, without limitation, comparator circuitry or logic that generates an output spike at neuron output 2306 when the result of applying the transfer function to neuron input 2304 exceeds a threshold. In at least one embodiment, neuron 2302 may ignore previously received input information when firing, for example, by resetting the membrane potential to 0 or another suitable default value.In at least one embodiment, once the membrane potential is reset to zero, neuron 2302 may resume normal operation after a suitable period (or refractory period).

[0335] In at least one embodiment, neurons 2302 may be interconnected through synapses 2308. In at least one embodiment, synapses 2308 may operate to transmit a signal from an output of a first neuron 2302 to an input of a second neuron 2302. In at least one embodiment, neurons 2302 may transmit information through two or more instances of synapses 2308. In at least one embodiment, one or more instances of neuron outputs 2306 may be connected to instances of neuron inputs 2304 of the same neuron 2302 through instances of synapses 2308. In at least one embodiment, an instance of neuron 2302 that generates an output to be transmitted through an instance of synapse 2308 may be referred to as a “pre-synaptic neuron” with respect to that instance of synapse 2308. In at least one embodiment, an instance of neuron 2302 that receives an input to be transmitted through an instance of synapse 2308 may be referred to as a “post-synaptic neuron” with respect to that instance of synapse 2308. In at least one embodiment, an instance of neuron 2302 may receive input from one or more instances of synapse 2308 and may send output through one or more instances of synapse 2308, so that a single instance of neuron 2302 may therefore be both a “pre-synaptic neuron” and a “post-synaptic neuron” with respect to various instances of synapse 2308.

[0336] In at least one embodiment, neurons 2302 may be organized into one or more layers. In at least one embodiment, each instance of a neuron 2302 may have one neuron output 2306 that can fan out to one or more neuron inputs 2304 through one or more synapses 2308. In at least one embodiment, a neuron output 2306 of a neuron 2302 in a first layer 2310 may be connected to a neuron input 2304 of a neuron 2302 in a second layer 2312. In at least one embodiment, layer 2310 may be referred to as a "feed-forward layer." In at least one embodiment, each instance of a neuron 2302 in an instance of a first layer 2310 may fan out to each instance of a neuron 2302 in a second layer 2312. In at least one embodiment, first layer 2310 may be referred to as a "fully connected feed-forward layer." In at least one embodiment, each instance of neuron 2302 in the second layer 2312 may fan out to fewer than all instances of neuron 2302 in the third layer 2314. In at least one embodiment, the second layer 2312 may be referred to as a "sparsely connected feed-forward layer." In at least one embodiment, the neurons 2302 in the second layer 2312 may fan out to neurons 2302 in multiple other layers, including the neurons 2302 in the second layer 2312. In at least one embodiment, the second layer 2312 may be referred to as a "recurrent layer." In at least one embodiment, the neuromorphic processor 2300 may include, without limitation, any suitable combination of recurrent and feed-forward layers, including, without limitation, both sparsely connected feed-forward layers and fully connected feed-forward layers.

[0337] In at least one embodiment, neuromorphic processor 2300 may include, without limitation, a reconfigurable interconnect architecture or dedicated hardwired interconnects for connecting synapses 2308 to neurons 2302. In at least one embodiment, neuromorphic processor 2300 may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons 2302 as needed based on the neural network topology and the fan-in / fan-out of the neurons. For example, in at least one embodiment, synapses 2308 may be connected to neurons 2302 using an interconnect fabric, such as a network-on-chip, or using dedicated connections. In at least one embodiment, synaptic interconnects and their components may be implemented using circuitry or logic.

[0338] In at least one embodiment, at least one embodiment of FIG. 23 can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify the pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0339] 24 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 2400 includes one or more processors 2402 and one or more graphics processors 2408 and may be a single-processor desktop system, a multiprocessor workstation system, or a server system having multiple processors 2402 or processor cores 2407. In at least one embodiment, system 2400 is a processing platform integrated into a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device. In at least one embodiment, one or more graphics processors 2408 include one or more graphics cores 1600.

[0340] In at least one embodiment, system 2400 may include or be incorporated into a server-based gaming platform, a game console including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, system 2400 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, processing system 2400 may also include, be coupled to, or be integrated into a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 2400 is a television or set-top box device having one or more processors 2402 and a graphical interface generated by one or more graphics processors 2408.

[0341] In at least one embodiment, the one or more processors 2402 each include one or more processor cores 2407 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2407 is configured to process a particular instruction sequence 2409. In at least one embodiment, the instruction sequence 2409 may facilitate computing via complex instruction set computing (CISC), reduced instruction set computing (RISC), or very long instruction word (VLIW). In at least one embodiment, each processor core 2407 may process a different instruction sequence 2409, which may include instructions that facilitate emulation of other instruction sequences. In at least one embodiment, the processor cores 2407 may also include other processing devices, such as a digital signal processor (DSP).

[0342] In at least one embodiment, processor 2402 includes cache memory 2404. In at least one embodiment, processor 2402 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 2402. In at least one embodiment, processor 2402 also uses an external cache (e.g., a level 3 (L3) cache or last level cache (LLC)) (not shown), which may be shared among processor cores 2407 using known cache coherence techniques. In at least one embodiment, processor 2402 further includes register file 2406, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2406 may include general-purpose registers or other registers.

[0343] In at least one embodiment, the one or more processors 2402 are coupled to one or more interface buses 2410 to transmit communication signals, such as address, data, or control signals, between the processors 2402 and other components in the system 2400. In at least one embodiment, the interface bus 2410 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 2410 is not limited to a DMI bus, but may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2402 includes an integrated memory controller 2416 and a platform controller hub 2430. In at least one embodiment, the memory controller 2416 facilitates communication between memory devices and other components of the system 2400, while the platform controller hub (PCH) 2430 provides connectivity to I / O devices via a local I / O bus.

[0344] In at least one embodiment, memory device 2420 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or any other memory device with performance suitable for serving as process memory. In at least one embodiment, memory device 2420 may operate as system memory for system 2400, storing data 2422 and instructions 2421 for use by one or more processors 2402 when executing applications or processes. In at least one embodiment, memory controller 2416 also couples to an optional external graphics processor 2412, which may communicate with one or more graphics processors 2408 within processor 2402 to perform graphics and media operations. In at least one embodiment, a display device 2411 may be connected to processor 2402. In at least one embodiment, display device 2411 may include one or more of an internal display device, such as a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., a display port, etc.). In at least one embodiment, display device 2411 may include a head-mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0345] In at least one embodiment, platform controller hub 2430 allows peripherals to be connected to memory device 2420 and processor 2402 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 2446, a network controller 2434, a firmware interface 2428, a wireless transceiver 2426, a touch sensor 2425, and a data storage device 2424 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device 2424 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a Peripheral Component Interconnect bus (e.g., PCI, PCI Express). In at least one embodiment, touch sensor 2425 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, wireless transceiver 2426 may be a WiFi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2428 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2434 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples to interface bus 2410. In at least one embodiment, audio controller 2446 is a multi-channel high-definition audio controller. In at least one embodiment, system 2400 includes an optional legacy I / O controller 2440 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to system 2400.In at least one embodiment, platform controller hub 2430 can also connect to one or more universal serial bus (USB) controller 2442 connected input devices, such as a keyboard and mouse 2443 combination, a camera 2444, or other USB input devices.

[0346] In at least one embodiment, instances of memory controller 2416 and platform controller hub 2430 may be integrated into a separate external graphics processor, such as external graphics processor 2412. In at least one embodiment, platform controller hub 2430 and / or memory controller 2416 may be external to one or more processors 2402. For example, in at least one embodiment, system 2400 may include external memory controller 2416 and platform controller hub 2430, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset that communicates with processor 2402.

[0347] Logic 515 is used to perform the inference and / or training operations associated with one or more embodiments. More details regarding logic 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B . In at least one embodiment, some or all of logic 515 may be incorporated into graphics processor 2408. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs embodied in the 3D pipeline. Furthermore, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that shown in FIG. 5A or FIG. 5B . In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of graphics processor 2408 for executing one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0348] In at least one embodiment, at least one embodiment of FIG. 24 can include or cause one or more processors, circuits, or systems to cause one or more neural networks to identify the pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras and / or based on any other embodiment discussed above with respect to FIGS. 1-4.

[0349] FIG. 25 is a block diagram of a processor 2500 having one or more processor cores 2502A-2502N, an integrated memory controller 2514, and an integrated graphics processor 2508, according to at least one embodiment. In at least one embodiment, the processor 2500 may include a number of additional cores, including additional core 2502N, represented by a dashed box. In at least one embodiment, each of the processor cores 2502A-2502N includes one or more internal cache units 2504A-2504N. In at least one embodiment, each processor core also has access to one or more shared cache units 2506. In at least one embodiment, the graphics processor 2508 includes one or more graphics cores 1600.

[0350] In at least one embodiment, internal cache units 2504A-2504N and shared cache unit 2506 represent a cache memory hierarchy within processor 2500. In at least one embodiment, cache memory units 2504A-2504N may include at least one level of instruction and data cache within each processor core, as well as one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherency between the various cache units 2506 and 2504A-2504N.

[0351] In at least one embodiment, processor 2500 may also include a set of one or more bus controller units 2516 and a system agent core 2510. In at least one embodiment, bus controller unit 2516 manages a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, system agent core 2510 provides management functions for various processor components. In at least one embodiment, system agent core 2510 includes one or more integrated memory controllers 2514 for managing access to various external memory devices (not shown).

[0352] In at least one embodiment, one or more of the processor cores 2502A-2502N include support for simultaneous multithreading. In at least one embodiment, the system agent core 2510 includes components for coordinating and operating the cores 2502A-2502N during multithreaded processing. In at least one embodiment, the system agent core 2510 may further include a power control unit (PCU), which includes logic and components for coordinating the power state of one or more of the processor cores 2502A-2502N and the graphics processor 2508.

[0353] In at least one embodiment, processor 2500 further includes a graphics processor 2508 for performing graphics processing operations. In at least one embodiment, graphics processor 2508 couples to a shared cache unit 2506 and to a system agent core 2510 that includes one or more integrated memory controllers 2514. In at least one embodiment, system agent core 2510 also includes a display controller 2511 for driving output of the graphics processor to one or more coupled displays. In at least one embodiment, display controller 2511 may also be a separate module coupled to graphics processor 2508 via at least one interconnect or may be integrated within graphics processor 2508.

[0354] In at least one embodiment, a ring-based interconnect unit 2512 is used to couple the internal components of processor 2500. In at least one embodiment, alternative interconnect units such as point-to-point interconnects, switched interconnects, or other techniques may be used. In at least one embodiment, graphics processor 2508 couples to ring interconnect 2512 via I / O link 2513.

[0355] In at least one embodiment, I / O link 2513 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2518, such as an eDRAM module. In at least one embodiment, each of processor cores 2502A-2502N and graphics processor 2508 use embedded memory module 2518 as a shared last-level cache.

[0356] In at least one embodiment, processor cores 2502A-2502N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, processor cores 2502A-2502N are ...

Claims

1. 1. A processor comprising: one or more circuits that use one or more neural networks to identify a pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras.

2. 2. The processor of claim 1, wherein the one or more different poses of the one or more cameras are based on prior identification, by the one or more neural networks, of the one or more different poses of the one or more cameras.

3. 3. The processor of claim 2, wherein the prior identification by the one or more neural networks of the one or more different poses of the one or more cameras is based on receipt by the one or more neural networks of one or more prior images of a sequence of images captured by the one or more cameras.

4. 4. The processor of claim 3, wherein the one or more circuits further use the one or more neural networks to identify the pose of the one or more cameras based, at least in part, on receipt by the one or more neural networks of a current image in the sequence of images captured by the one or more cameras.

5. The processor of claim 4 , wherein the sequence of images comprises a sequence of video frames of a video captured by the one or more cameras, and the current image comprises a current video frame of the video.

6. 6. The processor of claim 5, wherein the one or more circuits further use the one or more neural networks to label the current video frame to indicate the identified pose of the one or more cameras.

7. 2. The processor of claim 1, wherein at least one orientation or one position of the one or more cameras according to the identified pose of the one or more cameras is different from at least one other orientation or another position of the one or more cameras according to the one or more different poses of the one or more cameras.

8. using one or more neural networks to identify a pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras; A method comprising:

9. 9. The method of claim 8, wherein the one or more different poses of the one or more cameras are based on prior identification, by the one or more neural networks, of the one or more different poses of the one or more cameras.

10. 10. The method of claim 9, wherein the prior identification, by the one or more neural networks, of the one or more different poses of the one or more cameras is based on receipt, by the one or more neural networks, of one or more prior images of a sequence of images captured by the one or more cameras.

11. 11. The method of claim 10, further comprising: using the one or more neural networks to identify the pose of the one or more cameras based, at least in part, on receipt by the one or more neural networks of a current image in the sequence of images captured by the one or more cameras.

12. The method of claim 11 , wherein the sequence of images comprises a sequence of video frames of a video captured by the one or more cameras, and the current image comprises a current video frame of the video.

13. The method of claim 12 , further comprising labeling the current video frame to indicate the identified pose of the one or more cameras.

14. 9. The method of claim 8, wherein at least one orientation or one position of the one or more cameras according to the identified pose of the one or more cameras is different from at least one other orientation or one other position of the one or more cameras according to the one or more different poses of the one or more cameras.

15. one or more processors for identifying a pose of one or more cameras based, at least in part, on one or more different poses of the one or more cameras using one or more neural networks; one or more memories for storing parameters associated with one or more neural networks; A system comprising:

16. 16. The system of claim 15, wherein the one or more different poses of the one or more cameras are based on prior identification, by the one or more neural networks, of the one or more different poses of the one or more cameras.

17. 17. The system of claim 16, wherein the prior identification by the one or more neural networks of the one or more different poses of the one or more cameras is based on receipt by the one or more neural networks of one or more prior images of a sequence of images captured by the one or more cameras.

18. 20. The system of claim 17, wherein the one or more processors further use the one or more neural networks to identify the pose of the one or more cameras based, at least in part, on receipt by the one or more neural networks of a current image in the sequence of images captured by the one or more cameras.

19. 20. The system of claim 18, wherein the sequence of images comprises a sequence of video frames of a video captured by the one or more cameras, and the current image comprises a current video frame of the video.

20. 20. The system of claim 19, wherein the one or more processors further use the one or more neural networks to label the current video frame to indicate the identified pose of the one or more cameras.

Images