Measurement of stitching error using split targets

Abstract

To provide improved methods and systems for metrology of patterned semiconductor wafers.SOLUTION: A method of semiconductor metrology includes patterning film layers 22, 38 on a semiconductor substrate 24 to define a first field on the semiconductor substrate 24 with a first pattern comprising at least a first target feature within a first margin along a first edge of the first field and to define a second field, which abuts the first field, with a second pattern comprising at least a second target feature within a second margin along a second edge of the second field, such that the second edge of the second field adjoins the first edge of the first field. The first target feature in the first margin is adjacent to the second target feature in the second margin without overlapping the second target feature.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates generally to semiconductor device manufacturing, and more particularly to methods and target features for semiconductor circuit metrology. [Background technology]

[0002] Semiconductor circuits are commonly fabricated using photolithographic methods. In photolithographic processes, a thin layer of photosensitive polymer (photoresist) is deposited over a semiconductor substrate. The photoresist is patterned by an exposure system, typically including a scanner or stepper, that projects an image of a mask (also called a "photomask" or "reticle") onto the photoresist, typically using ultraviolet radiation. The extent of the reticle image defines an exposure field on the substrate. Multiple fields are typically exposed on a single semiconductor substrate for optimal substrate utilization. After patterning, the substrate is modified by methods such as etching and ion bombardment to change the material properties and / or topography of the substrate, while leaving the portions of the substrate covered by the photoresist unaffected.

[0003] The exposure field of a scanner typically includes one or more dies, each of which will be used to produce a corresponding integrated circuit. However, in some applications, a single circuit may require dimensions larger than a single exposure field. In this case, a single die may include two or more adjacent exposure fields, with patterned circuit features connecting neighboring fields within the die. Patterning a semiconductor substrate to connect circuit features in adjacent fields is commonly referred to as "field stitching" or simply "stitching."

[0004] Several methods have been proposed for measuring misalignment between neighboring fields. For example, U.S. Patent Application Publication No. 2021 / 0200105 describes a metrology system including a controller that receives a first metrology data set related to a first set of metrology target features on a specimen, including a first feature from a first exposure field on a first specimen layer and a second feature from a second exposure field on a second specimen layer, where the second exposure field partially overlaps with the first exposure field. The controller may further receive a second metrology data set related to a second set of metrology target features, including a third feature from a third exposure field on the second layer that overlaps with the first exposure field and a fourth feature formed from a fourth exposure field on the first layer of the specimen that overlaps with the second exposure field. The controller can further determine a manufacturing error based on the first metrology data set and the second metrology data set and can generate a correctable value for adjusting the lithography apparatus based on the manufacturing error. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0200105 Summary of the Invention [Problem to be solved by the invention]

[0006] Embodiments of the present invention described hereinafter provide improved methods and systems for metrology of patterned semiconductor wafers, and targets for use in such methods. [Means for solving the problem]

[0007] Therefore, according to an embodiment of the invention, there is provided a method of semiconductor metrology, the method comprising patterning a film layer on a semiconductor substrate to define a first field on the semiconductor substrate with a first pattern including at least first target features within a first margin along a first edge of the first field. The film layer on the semiconductor substrate is patterned to define a second field bordering the first field with a second pattern including at least second target features within a second margin along a second edge of the second field, such that a second edge of the second field abuts the first edge of the first field and the first target features within the first margin abuts the second target features within the second margin without overlapping the second target features. An image is captured of an area of ​​the patterned film layer including at least the first and second target features. The image is processed to detect misalignment between the first and second fields.

[0008] In a disclosed embodiment, processing the image includes finding a first center of symmetry and a second center of symmetry of the first target feature and the second target feature, respectively, measuring a displacement between the first center of symmetry and the second center of symmetry, and detecting misalignment by comparing the measured displacement with a nominal displacement.

[0009] In some embodiments, the first target feature and the second target feature comprise first and second linear gratings, respectively, oriented along a common grating direction. In one such embodiment, the first and second linear gratings are oriented along the first grating direction, and patterning the film layer comprises forming third and fourth target features along a first edge of the first field and a second edge of the second field, respectively, in margins on opposing first and second sides of the field, and the third and fourth target features comprise third and fourth linear gratings, respectively, oriented along a second direction that is non-parallel to the first direction.

[0010] Additionally or alternatively, patterning the film layer includes forming at least a further instance of the first target feature in the first field proximate the first target feature, and processing the image includes calculating an alignment calibration function using the at least a further instance of the first target feature and applying the alignment calibration function in measuring misalignment between the first field and the second field. In disclosed embodiments, the at least a further instance of the first target feature includes a copy of the first target feature adjacent to the first target feature, and calculating the alignment calibration function includes measuring a relationship in the image between the copy of the first target feature and the first target feature. Alternatively, the at least a further instance of the first target feature includes copies of both the first target feature and the second target feature.

[0011] In a disclosed embodiment, patterning the film layer includes defining a third field bordering the second field, the third field having a third pattern including at least third target features in a third margin along a third edge of the third field, such that a third edge of the third field is adjacent to a fourth edge of the second field, and the second field includes a fourth target feature in the second margin adjacent to the third target feature on the third margin without overlapping the third target feature. The method includes capturing a further image including at least the third target feature and the fourth target feature, and processing the further image to detect further misalignment between the second field and the third field.

[0012] Additionally or alternatively, the method includes measuring angular misalignment of the semiconductor substrate, and processing the image includes correcting for the angular misalignment when estimating the misalignment between the first field and the second field.

[0013] Further, additionally or alternatively, the first target feature and the second target feature are used in measuring overlay error between successive film layers on a semiconductor substrate.

[0014] According to an embodiment of the invention, there is further provided an article of manufacture, the article including a semiconductor substrate and a film layer disposed on the substrate, the film layer being patterned to define a first field on the semiconductor substrate having a first pattern including at least first target features in a first margin along a first edge of the first field, and a second pattern including at least second target features in a second margin along a second edge of the second field such that a second edge of the second field is adjacent to the first edge of the first field and the first target features in the first margin are adjacent to second target features in the second margin without overlapping the second target features.

[0015] According to an embodiment of the invention, there is further provided an apparatus for semiconductor metrology, the apparatus including an imaging assembly configured to capture an image of a semiconductor substrate having a film layer disposed thereon. The film layer is patterned to define a first field on the semiconductor substrate having a first pattern including at least first target features within a first margin along a first edge of the first field, and a second pattern including at least second target features within a second margin along a second edge of the second field such that a second edge of the second field is adjacent to the first edge of the first field and the first target features within the first margin are adjacent to second target features within the second margin without overlapping the second target features. A processor is configured to process the image to detect misalignment between the first field and the second field. The present invention will be more fully understood from the following detailed description of embodiments of the invention taken in conjunction with the drawings. [Brief explanation of the drawings]

[0016] [Figure 1]1 is a schematic side view of an exposure system for patterning a photoresist layer on a semiconductor substrate, according to an embodiment of the invention. [Figure 2] 1 is a schematic top view of a patterned semiconductor substrate according to an embodiment of the invention. [Figure 3] FIG. 2 is a schematic top view of an exposure field, according to an embodiment of the invention. [Figure 4] FIG. 2 is a schematic top view of four adjacent exposure fields, according to an embodiment of the invention. [Figure 5] 1 is a schematic side view of an imaging and measurement device, according to an embodiment of the invention; [Figure 6] 5 is a schematic top view of the four exposure fields of FIG. 4 showing areas of interest for stitching error measurement, according to an embodiment of the invention. [Figure 7A] 1A-1C are schematic top views of two exposure fields each with a calibration target, according to two embodiments of the invention; [Figure 7B] 1A-1C are schematic top views of two exposure fields each with a calibration target, according to two embodiments of the invention; [Figure 8] FIG. 1 is a schematic top view of an angularly misaligned metrology target, in accordance with an embodiment of the invention. [Figure 9] 1 is a flow chart that schematically illustrates a method for patterning multiple fields on a semiconductor substrate and for measuring stitching errors between adjacent fields, in accordance with an embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION

[0017] overview For semiconductor circuits in which two or more adjacent exposure fields define a single die, stitching errors between the fields, i.e., misalignment between the fields, can result in fatal circuit defects. Stitching errors can occur, for example, due to optical aberrations and scanner motion errors. It is important to detect and correct stitching errors early in the process to avoid yield loss.

[0018] However, overlay metrology targets are typically patterned with one target feature in an underlying process layer and another target feature in a photoresist layer, and for stitching error measurement, both features are patterned in the photoresist layer: one target feature is patterned when exposing one field, and the other feature is patterned when exposing a neighboring field. In overlay metrology targets, target features in the photoresist layer typically overlap with corresponding target features in the underlying process layer. Emulating this model in stitching targets, however, requires that the margins of neighboring fields overlap each other. This overlap necessitates a complex double exposure process.

[0019] The embodiments described hereinafter address this issue by patterning adjacent fields that abut each other without substantial overlap, with measurement target features in the margins of the fields adjacent to the respective field edges. To measure stitching errors, each target includes two "half targets" on opposite sides of the boundary between a pair of abutting fields. The half targets have respective target features, such as linear gratings, that abut each other without overlapping. The half targets are non-overlapping in the sense that there is no overlapping area between the smallest bounding boxes containing the respective target features of the two half targets.

[0020] This type of half target (for use in overlay metrology) is described in U.S. patent application Ser. No. 63 / 299,010, filed Jan. 13, 2022, the disclosure of which is incorporated herein by reference.

[0021] For example, a target containing two target features in the form of linear gratings oriented in the same grating direction may be patterned with one target feature at the edge of one field and the other at the edge of a neighboring field, with the features adjacent to each other across the boundary between the two fields. By employing two half targets with gratings that are orthogonal to each other and adjacent the boundary, the stitching error between these two fields may be measured in two orthogonal directions.

[0022] Thus, in the disclosed example, a film layer on a semiconductor substrate is patterned to define multiple fields, including at least a first field and a second field that abut each other. The pattern of the first field includes at least first target features within a margin of the first field along the edge of the first field. (The term "margin" refers to a narrow band, typically on the order of 10 μm in width, along the field edge, although narrower or wider margins may be used depending on the size of the target features.) The pattern of the second field includes at least second target features within a margin of the second field along the edge of the second field adjacent to the edge of the first field. The target features are defined such that a first target feature within the margin of the first field is adjacent to a second target feature within the margin of the second field without overlapping the second target feature.

[0023] The imaging assembly captures an image of an area of ​​the patterned film layer including the stitching metrology target, i.e., an image including at least a first target feature and a second target feature, and the processor processes the image to detect misalignment between the first field and the second field.

[0024] The patterns in the first and second fields may be different or identical, as long as the patterns contain target features in appropriate adjacent locations within the field margins. In some embodiments, as described hereinafter, this technique is extended to measure stitching errors between three or more neighboring fields.

[0025] Patterning 1 is a schematic side view of an exposure system 20 for patterning a photoresist layer 22 on a semiconductor substrate 24, such as a silicon wafer, in accordance with an embodiment of the invention. Exposure system 20 is shown as an example, and other types of exposure systems may be used instead.

[0026] The exposure system 20, which represents a scanner or stepper in a simplified manner, includes an exposure source 26, a mask stage 28, projection optics 30, a wafer stage 32, and an exposure system controller 34. A mask 36 defining a pattern for a photoresist layer 22 is mounted on the mask stage 28. The mask 36 includes target features in margins along one or more edges of the pattern for the purpose of measuring stitching errors as described further hereinafter. A semiconductor substrate 24 having one or more process layers 38 and a photoresist layer 22 deposited thereon is mounted on the wafer stage 32. The orientation of the exposure system 20, as well as the orientation of items in the figures hereinafter, refers to a Cartesian coordinate system 40.

[0027] Exposure source 26 emits radiation, indicated by arrow 42, to illuminate mask 36. The radiation typically includes wavelengths in the ultraviolet (UV) or extreme ultraviolet (EUV) regions of the spectrum. Although the emitted radiation is shown as uniform and collimated radiation, it may alternatively include radiation having other spatial and / or angular distributions.

[0028] The mask stage 28 comprises actuators controlled by the exposure system controller 34 that can move the stage (and thus the mask 36) linearly in the x-, y-, and z-directions, as well as rotate the stage about the z-axis and tilt the stage about the x- and y-axes. The mask 36 typically comprises a substrate, such as quartz, that is transparent to the radiation emitted by the exposure source 26, and has a pattern formed in a thin film of a suitable material on the substrate that modulates the amplitude and / or phase of the radiation transmitted by the mask.

[0029] The projection optics 30 is shown for simplicity as a single lens, but typically comprises multiple lenses and / or mirrors, the positions and orientations of which may be controlled by the exposure system controller 34 for optimum optical performance.

[0030] The wafer stage 32 includes actuators controlled by the exposure system controller 34 that can move the stage (and thus the semiconductor substrate 24) linearly in the x-, y-, and z-directions, as well as rotate the stage about the z-axis.

[0031] An exposure system controller 34 is coupled to the light source 26, the mask stage 28, the projection optics 30, and the wafer stage 32. The controller 34 typically comprises a programmable processor that is programmed in software and / or firmware to perform the functions described herein, along with suitable digital and / or analog interfaces for connection to other elements of the exposure system 20. Alternatively or additionally, the controller 34 comprises hardwired and / or programmable hardware logic circuitry that performs at least some of the functions of the controller. Although the controller 34 is shown in FIG. 1 as a single, monolithic functional block for simplicity, in practice the controller may comprise multiple interconnected control units with suitable interfaces for receiving and outputting the signals shown in the figures and described herein.

[0032] To pattern the photoresist layer 22, the exposure system controller 34 moves the wafer stage 32 under the projection optics 30 so that the photoresist layer 22 on the semiconductor substrate 24 is at a desired position and orientation relative to the optics. The exposure light source 26 emits radiation to illuminate the mask 36. The radiation that strikes the mask 36 is transmitted and / or diffracted by the mask and projected toward the projection optics 30, which focuses the radiation onto the photoresist layer 22 and exposes the photoresist. The area to be exposed, referred to as the "exposure field" or "field," is defined by an image of the mask 36 on the semiconductor substrate 24. As previously noted, each field includes target features within margins along one or more edges of the field for the purpose of stitching error measurement. After exposure of one field, the controller 34 moves the wafer stage 32 in the xy-plane so that the next field can be exposed, as described in more detail in FIG. 2 . When a different pattern is required for the next field, for example when producing a die containing multiple fields with different circuit patterns in each field, mask 36 is replaced by another appropriate mask before exposure.

[0033] Once all the required fields have been exposed, the photoresist layer is developed. After the development step, the stitching error of the patterning between adjacent fields is measured using target features in the margins, as described hereinafter. As long as the stitching error complies with a preset tolerance, the process layer 38 is modified by methods such as etching and ion irradiation to change the material properties and / or topography of the process layer, while the portions of the process layer covered by the remaining portions of the photoresist layer 22 are unaffected.

[0034] In addition to measuring stitching errors between adjacent fields, the target features in the margins may also be used to measure overlay errors between successive film layers on the substrate 24, such as the photoresist layer 22 and the process layer 38, by providing corresponding target features in the margins of the process layers. Furthermore, the target features in the margins of the process layer 38 may be used to measure stitching errors between adjacent fields in the process layer.

[0035] FIG. 2 is a schematic top view of a patterned semiconductor substrate 24, according to an embodiment of the invention.

[0036] The semiconductor substrate 24 includes exposure fields 50 that have been exposed by the exposure system 20 as described hereinabove. The fields 50 are exposed so that the fields abut one another with adjacent edges that touch but do not substantially overlap. In the depicted example, each die 52 includes a pair of adjacent fields 50. For example, fields 50a and 50b form die 52a, shown by shading. (In alternative embodiments, two or more fields 50 may form a single die 52.) This combination of multiple fields 50 to form a single die 52 allows for the formation of circuits that are larger than a single field of the exposure system 20.

[0037] For the circuitry within a given die 52 to be functional, i.e., to have functional connections across the common boundary between the two fields that form the die, the fields must be aligned with one another with high precision (typically to within the order of 10 nm). To ensure this alignment, target features are patterned in the margins along adjacent edges of fields 50a and 50b in the patterning step described above. Alternatively, target features may be patterned along two, three, or all four edges of each field, as will be described hereinafter.

[0038] FIG. 3 is a schematic top view of an exposure field 50, according to an embodiment of the invention.

[0039] Field 50 includes a circuit area 60 that extends across the field to its edges to allow coupling of multiple circuits within the circuit area to one or more of the neighboring fields. (For brevity, details of the electronic circuitry within circuit area 60 are not shown in the current figure, and the reference numeral for circuit area 60 is omitted from the remaining figures.) Field margin 61 includes a frame-like area between outer edge 63 and inner edge 65 of field 50. Field 50 additionally includes x-metrology target features 62, 64, 66, and 68 and y-metrology target features 72, 74, 76, and 78, with all target features located within margin 61 adjacent outer edge 63.

[0040] In the depicted example, each target feature comprises a linear grating containing four parallel, equally spaced bars. Target features 62, 64, 66, and 68 are oriented in the y-direction, and target features 72, 74, 76, and 78 are oriented in the x-direction. Alternatively, target features 72, 74, 76, and 78 may be oriented at one or more different angles, as long as they are not parallel to target features 62, 64, 66, and 68.

[0041] In alternative embodiments, other target features may be used that allow determining the location of the center of symmetry of the feature in either the x- or y-direction.

[0042] Due to the requirement that circuit features within circuit area 60 of field 50 connect to at least one neighboring field, the circuit area extends into white space 61, thus sharing white space with the target features.

[0043] For clarity, the dimensions of target features 62, 64, 66, 68, 72, 74, 76 and 78 and margins 61 are exaggerated relative to the dimensions of field 50. Typical fields have dimensions in the range of tens of millimeters, while target features typically have a size of 5 μm×5 μm or 10 μm×10 μm.

[0044] The target features are placed within the field 50 in such a way that when patterning several adjacent fields, each target feature is nominally aligned with a similar target feature in the adjacent field, as will be explained in more detail hereinafter. The term "nominal aligned" means that when the stitching error is measured using a pair of adjacent target features each belonging to adjacent fields 50, this error is zero when patterned by an ideal exposure system 20.

[0045] Because field 50 is patterned by exposure system 20 using mask 36, all fields patterned on semiconductor substrate 24 using this mask include the same pattern of circuitry in circuit area 60 and x-metrology target features 62, 64, 66, and 68 and y-metrology target features 72, 74, 76, and 78, respectively, in the margins. When different masks are used to pattern different circuit features in different fields, each mask may still have the same pattern of metrology target features to enable stitching errors to be measured as described in this embodiment.

[0046] FIG. 4 is a schematic top view of four adjacent exposure fields 100a, 100b, 100c and 100d, according to an embodiment of the invention.

[0047] Each of the four fields includes four x- and four y-metrology target features as shown in FIG. 3 for field 50. In accordance with the labeling of the metrology target features in FIG. 3, x-metrology target features 66a and 66d form x-metrology target 102, which allows for measuring the x-stitching error, i.e., misalignment in the x-direction, between fields 100a and 100d. (Measuring stitching errors will be explained in detail later in this specification.) Similarly, y-misalignment structures 76a and 76d form y-metrology target 104, which allows for measuring the y-stitching error between fields 100a and 100d. To measure the x- and y-stitching errors between fields 100c and 100d, x-metrology target 106 is formed by x-metrology target features 68c and 68d, and y-metrology target 108 is formed by y-metrology target features 78c and 78d. To measure the stitching error between fields 100a and 100b and between fields 100b and 100c, measurement targets are similarly formed from the associated target features. Stitching error measurement between four fields is shown here merely as an example, and the method may be limited to only two or three neighboring fields, or may be extended to any number of adjacent fields.

[0048] Because each metrology target is formed by two target features in adjacent fields, no overlap of the fields is necessary, thus simplifying the patterning of each field, particularly for all circuit patterns within margin 61. Rather, the smallest bounding box containing any given target feature (i.e., the smallest rectangular area containing all target features) has no overlapping area with the smallest bounding boxes of any other target features within the same metrology target.

[0049] Metrology targets, such as targets 102, 104, 106, and 108 in Figure 4, are one-dimensional half targets. As used herein, "one-dimensional" refers to the fact that one-dimensional half targets allow for measurement of stitching error in only one dimension. The term "half target" refers to the fact that these stitching error measurements do not need to be calibrated by 0° / 180° rotation, in contrast to "full targets" that include multiple target features with 180° symmetry about the normal to the substrate 24 (e.g., AIM™ targets by KLA Corporation, Milpitas, CA, USA).

[0050] In the following description, metrology targets such as targets 102 and 108 in which the bars of each target feature are placed side by side along a direction perpendicular to the grating direction will be referred to hereinafter as "side-by-side targets." Metrology targets such as targets 104 and 106 in which the bars of each target feature are placed head-to-head along the grating direction will be referred to as "head-to-head targets." The principles of the present invention, however, are not limited to such targets. In alternative embodiments, for example, target cells may be placed at angles that are not orthogonal to each other, and in some designs, targets may include diagonal bars.

[0051] Stitching Error Measurement 5 is a schematic side view of an imaging metrology device 200, in accordance with an embodiment of the invention. Device 200 is shown as an example to illustrate a method of metrology and calibration, in accordance with an embodiment of the present invention. Alternatively, other types of metrology systems may be used.

[0052] The imaging metrology device 200 includes an imaging assembly 202, an illumination assembly 204, a metrology processor 206, and a table 208 on which a semiconductor substrate 24 is mounted. The imaging assembly 202 includes an objective lens 210, a cube beam splitter 212, and an imaging lens 214. The imaging assembly 202 further includes a two-dimensional sensor array 216 including, for example, a complementary metal-oxide semiconductor (CMOS) detector having a two-dimensional array of pixels 218. The imaging lens 214 images the top surface of the semiconductor substrate 24 onto the sensor array 216.

[0053] The illumination assembly 204 includes a light source 220 that emits radiation and a lens 222. A table 208 is located adjacent to the objective lens 210 and is controlled by the metrology processor 206, and includes actuators that can linearly move the table in the x-, y-, and z-directions, as well as rotate the table about the z-axis.

[0054] A semiconductor substrate 24 having a process layer 38 and a photoresist layer 22 deposited thereon is placed on a table 208. The photoresist layer 22 has been patterned as described herein above.

[0055] The measurement processor 206 is coupled to the sensor array 216 and the table 208. The measurement processor 206 typically comprises a programmable processor with suitable digital and / or analog interfaces for connection to other elements of the device 200, which is programmed in software and / or firmware to perform the functions described herein. Alternatively or additionally, the processor 206 comprises hardwired and / or programmable hardware logic circuitry that performs at least some of the functions of the controller. Although the processor 206 is shown in FIG. 5 as a single monolithic functional block for simplicity, in practice the controller may comprise multiple interconnected control units with suitable interfaces for receiving and outputting the signals shown in the figure and described herein. Program code or instructions for the measurement processor 206 to implement the various methods and functions disclosed herein may be stored in a readable storage medium, such as memory within the measurement processor 206 or other memory.

[0056] To capture an image of the metrology target in the photoresist layer 22, the semiconductor substrate 24 is placed on a table 208 and the table is moved so that the target is within the field of view (FOV) of an objective lens 210. A light source 220 projects a beam of radiation onto a lens 222, which further projects the beam onto a cube beam splitter 212. The beam splitter 212 reflects the beam to the objective lens 210, which projects the beam onto the semiconductor substrate 24 to illuminate the metrology target. The radiation that strikes the semiconductor substrate 24 is reflected back to the objective lens 210 and further focused by a lens 214 onto a sensor array 216. A metrology processor 206 captures the image and processes the image to measure stitching errors, as described in more detail hereinafter.

[0057] FIG. 6 is a schematic top view of the four exposure fields shown in FIG. 4 showing the areas of interest for stitching error measurement, according to an embodiment of the invention.

[0058] To measure the x-stitching error and y-stitching error between fields 100a and 100d and between fields 100c and 100d, metrology processor 206 moves table 208 so that each metrology target 102, 104, 106, and 108 is, in turn, positioned under objective lens 210 and imaged onto sensor array 216 (FIG. 5). For each metrology target 102, 104, 106, and 108, processor 206 defines a region of interest (ROI) over the target features forming the respective metrology target. (In FIG. 6, the ROIs are drawn to encompass the entire target feature. Alternatively, each ROI may include only the interior portion of the respective target feature, thus excluding, for example, potentially anomalous ends of bars.) The designation of the ROIs is shown in Table 1.

[0059] [Table 1]

[0060] For each ROI, the metrology processor 206 processes a portion of the image within the respective ROI and calculates the location of the center of symmetry of each target feature. Based on the location of the center of symmetry, the processor 206 calculates the x-stitching error (STE) x ) and y-stitching error (STE y ) Because the metrology targets 102, 104, 106 and 108 differ from one another in both structure and orientation, these calculations are explained in more detail hereinafter:

[0061] The metrology target 102-processor 206 calculates the centers of symmetry of each of the target features within the ROIs 162d and 166a, as well as the displacement Δ between the two centers of symmetry in the x-direction.x (The displacement between the two centers of symmetry in the y-direction is determined by the positions of the two ROIs and is not related to the x-stitching error.) For the side-by-side target features 62d and 66a, the displacement Δ x is the displacement D nominal,x and stitching error STE x Here, D nominal,x is the nominal displacement between the centers of symmetry of the target features within ROIs 162d and 166a. x is Δ x =D nominal,x +STE x and the stitching error is the sum of the measured displacement Δ x From D nominal,x It is calculated by subtracting: STE x =Δ x -D nominal,x Nominal x-displacement D nominal,x is determined by processor 206 from the design dimensions of mask 36 as projected onto semiconductor substrate 24 in exposure system 20 and imaged onto sensor 216 in metrology system 200. In other words, D nominal,x depends on the nominal position of each target feature on the mask, the optical magnification of the exposure system 20 and the nominal optical magnification of the metrology tool 200.

[0062] The metrology target 104-processor 206 determines the centers of symmetry of each of the target features within the ROIs 172d and 176a, as well as the displacement Δ between the centers of symmetry in the y-direction. y (The displacement between the two centers of symmetry in the x-direction is determined by the positions of the two ROIs and is not related to the y-stitching error.) The head-to-head target features 72d and 76a are nominally aligned with respect to each other in the y-direction, and therefore the displacement Δ y y-stitching error STE y Given: STE y =Δ y is.

[0063] The metrology target 106-processor 206 calculates the centers of symmetry of each of the target features within the ROIs 164d and 168c, as well as the displacement Δ between the two centers of symmetry in the x-direction. x (The displacement between the two centers of symmetry in the y-direction is determined by the positions of the two ROIs and is not related to the x-stitching error.) Like the metrology target 104, the head-to-head target features 64d and 68c are nominally aligned with respect to each other in the x-direction, and therefore the displacement Δ x x-stitching error STE x Given: STE x =Δ x Alternatively, using other target designs, such as diagonally oriented targets, a given target may simultaneously introduce both x-stitching and y-stitching errors.

[0064] The metrology target 108-processor 206 calculates the centers of symmetry of each of the target features within the ROIs 174d and 178c, as well as the displacement Δ between the two centers of symmetry in the y-direction. y (The displacement between the two centers of symmetry in the x-direction is determined by the positions of the two ROIs and is not related to the y-stitching error.) For side-to-side target features 74d and 78c, the displacement Δ y is the nominal y-displacement D between the centers of symmetry of ROIs 174d and 178c. nominal,y and stitching error STE y and is the sum of: Δ y =D nominal,y +STE y Therefore, the stitching error is the sum of the measured displacement Δ y From D nominal,y It is calculated by subtracting: STE y =Δ y -D nominal,y The nominal y-displacement D nominal,y is D as described herein above nominal,xSimilarly, it is determined by the processor 206 from the design dimensions of the mask 36 .

[0065] The stitching error between fields 100a and 100b and between fields 100b and 100c is measured in a similar manner.

[0066] Figures 7A and 7B are schematic top views of two exposure fields each with a calibration target, according to two embodiments of the invention. In the embodiment shown in Figure 7A, the calibration target is integrated with the metrology target, whereas in the embodiment shown in Figure 7B, the calibration target is separate from the metrology target.

[0067] The stitching error STE as measured by the overlay metrology tool 200 x and STE y may have measurement errors due to optical aberrations in the imaging assembly 202 of the device, as well as due to magnification errors ΔM relative to the nominal optical magnification M of an ideal imaging assembly. As explained herein above (with reference to FIG. 6 ), the nominal displacement D between the centers of symmetry of the ROIs of side-by-side measurement targets (such as targets 102 and 108) nominal,x and D nominal,y However, stitching error STE x and STE y The magnification error of ΔM is used to calculate the measured stitching error STE x and STE y (ΔM / M)×D nominal,x and (ΔM / M) × D nominal,y For example, a relative error of 0.1% ΔM / M and D nominal,x The nominal value of 5 μm for STE x This results in an error of 5 nm, which is significant compared to a typical total stitching error budget of 5-10 nm.

[0068] Another source of error in stitching error measurements is angular misalignment of the target features with respect to Cartesian coordinates 40, as explained in more detail later in this specification in Figure 8. Because of these error sources, it is desirable to calibrate the stitching error measurements. Two alternative methods for calibration are shown in Figures 7A and 7B.

[0069] 7A shows two exposure fields 300a and 300b. Exposure field 300a includes target features 302a, 304a, 306a, and 308a for x-misalignment measurement, and target features 312a, 314a, 316a, and 318a for y-misalignment measurement. Exposure field 300b includes similar target features identified by the letter "b" in its reference number. Exposure field 300a includes calibration target features 320a and 322a, with similar calibration target features 320b and 322b added to field 300b.

[0070] The calibration procedure is described hereinafter, by way of example, with respect to metrology targets 330 and 332. Metrology target 330 includes target features 302b and 306a for measuring the x-stitching error between fields 300a and 300b, and metrology target 332 includes target features 312b and 316a for measuring the y-stitching error between these two fields.

[0071] Calibration target feature 320a, used to calibrate the x-misalignment measurements, is a copy of target feature 306a and is placed adjacent to target feature 306a with a shift in the x-direction, so that these two target features together form metrology target 334, which is completely contained within field 300a. The displacement in the x-direction between the centers of symmetry of target features 306a and 320a is the same as the nominal displacement between the centers of symmetry of target features 302b and 306a. To calibrate the x-misalignment measured by metrology system 200 using target 330, the system also measures the x-misalignment of target 334. Because the entire target 334 is patterned within one field (field 300a), its x-stitching error is known to be zero. Any non-zero x-misalignment of target 334 is due to the error sources described above (optical aberrations and magnification errors of apparatus 200 and angular misalignment of target features), hence the x-misalignment calibration. Because this error manifests itself in the x-stitching error measurement of target 330, this measurement, including the magnification error, may be corrected using the x-misalignment calibration value measured using target 334.

[0072] Calibration target feature 322b, used to calibrate the y-misalignment measurements, is a copy of target feature 312b and is placed adjacent to target feature 312b with a shift in the x-direction, so that these two target features together form metrology target 336. To calibrate the y-misalignment measured by metrology system 200 using target 332, the system also measures the y-misalignment of target 336. As with target 334, target 336 is known to have zero y-stitching error. Any non-zero misalignment of target 336 is again due to the error sources described above (optical aberrations of system 200 and angular misalignment of target features; magnification error is not relevant for head-to-head metrology target 332) to perform the y-misalignment calibration. Since this error manifests itself similarly in the y-stitching error measurement of target 332, this measurement may be corrected using a y-misalignment calibration value measured using target 336.

[0073] For simplicity, only calibration target features shifted in the x-direction are shown for each field in Figure 7A. Other calibration target features similar to the x-shifted calibration features but shifted in the y-direction may be added adjacent to other measurement target features for misalignment calibration.

[0074] 7B shows two exposure fields 400a and 400b. Exposure field 400a includes target features 402a, 404a, 406a, and 408a for x-misalignment measurement and target features 412a, 414a, 416a, and 418a for y-misalignment measurement. Exposure field 400b includes similar target features identified by the letter "b" in its reference numeral. Exposure field 400a includes calibration target features 420a, 422a, 424a, and 426a, with similar target features 420b, 422b, 424b, and 426b added to field 400b.

[0075] The calibration procedure will be described with respect to example metrology targets 430 and 432. Metrology target 430 includes target features 402b and 406a for measuring the x-stitching error between fields 400a and 400b, and metrology target 432 includes target features 412b and 416a for measuring the y-stitching error between these two fields.

[0076] Calibration target features 420a and 422a are positioned in field 400a to form calibration target 434a, which is nominally identical to metrology target 430, including the displacement between the centers of symmetry of the target features. Calibration target 434a may therefore be used to calibrate x-misalignment measurements using metrology target 430, similar to the use of target 334 to measure x-misalignment calibration values ​​and to calibrate x-misalignment measurements using target 330 (FIG. 7A).

[0077] Similarly, calibration target features 424a and 426a are placed in field 400a to form calibration target 436a, which is nominally identical to metrology target 432. Calibration target 436a may therefore be used to calibrate y-misalignment measurements using target 432, similar to the use of target 336 to measure y-misalignment calibration values ​​and to calibrate y-misalignment measurements using target 332 (FIG. 7A).

[0078] 7B, the target features are shifted in the x-direction relative to each other. Other calibration target features similar to the x-shifted calibration features but shifted in the y-direction may be added adjacent to other measurement target features for misalignment calibration.

[0079] When the gratings of the two target features forming the metrology target have unequal pitches, a calibration step may be performed prior to that shown in Figure 7A or 7B. This step involves measuring the stitching error using the target at two orientations separated by a 180° rotation about the z-axis, and then calibrating the STE for the two orientations. x,0° and STE x,180° x-stitching error and STE for two orientations y,0° and STE y,180° In the first calibration step, the calibrated x-stitching error and y-stitching error are calculated by STE x,CAL1 =(STE x,0° -STE x,180° ) / 2 and STE y,CAL1 =(STE y,0° -STE y,180° ) / 2. A second calibration step is then performed using the method described above.

[0080] When multiple metrology targets are utilized to measure the same stitching error, for example, the x-misalignment between fields 300a and 300b (FIG. 7A) or between fields 400a and 400b (FIG. 7B), the respective x-misalignment calibration value may be used for all of these targets.

[0081] FIG. 8 is a schematic top view of an angularly misaligned metrology target 500, in accordance with an embodiment of the invention.

[0082] Although the angular misalignment of the metrology targets may be calibrated as described herein above, further local angular misalignments may be introduced when measuring stitching errors using each metrology target with apparatus 200. Table 208 moves semiconductor substrate 24 in the xy-plane to sequentially bring each target under objective lens 210, and during this movement may introduce angular misalignments, i.e., yaw errors. These local yaw errors of table 208 may be measured, for example, by using interferometric measurements of the table's yaw angle. Once the yaw angle is known, it may be used for further calibration of stitching error measurements, as described hereinafter.

[0083] The metrology target 500 is a head-to-head one-dimensional half target containing six parallel, equally spaced bars in two target features, 502 and 504, to measure the x-stitching error. The target 500 is rotated by a yaw angle α with respect to the Cartesian coordinate system 40. The measured x-stitching error STE x For purposes of illustrating the error, target 500 has zero x-misalignment, i.e., is a non-rotated target, and target features 502 and 504 should be aligned with one another with zero shift in the x-direction. xis measured by metrology device 200 using target 500. To that end, metrology processor 206 defines ROIs 506 and 508 covering respective target features 502 and 504, and finds respective centers of symmetry 510 and 512 of the target features, as described herein above. D between centers of symmetry 510 and 512 ROI,y With respect to the displacement of , the rotation of α causes the displacement between the centers of symmetry in the x-direction to be Δ angular,x = α × D ROI,y where the small-angle approximation is used. For example, α=1 mrad and D ROI,y For = 5 μm, Δ angular,x = 5 nm. This error is measured from a target such as target 500, where x-misalignment measurement STE x This proves itself directly, and Δ angular,x However, the measured x-stitching error STE x For side-by-side targets such as target 104 (FIG. 4), the typical yaw angle of table 208 has negligible error.

[0084] FIG. 9 is a flow chart 600 that schematically illustrates a method for patterning multiple fields on a semiconductor substrate and measuring stitching errors between adjacent fields, according to an embodiment of the invention.

[0085] In a deposition step 602, a photoresist layer 22 (FIG. 1) is deposited over a semiconductor substrate 24. In a patterning step 604, adjacent but non-overlapping fields are patterned on the substrate 24 using a mask 36 in an exposure system 20. In a development step 606, the photoresist layer 22 is developed to produce features defined by the mask 36, including metrology target features.

[0086] In a stitching error measurement step 608, the x-stitching error and the y-stitching error are measured by the imaging metrology device 200 (FIG. 5) using the measurement target features. In a calibration step 610, the measured stitching error is calibrated using the methods described herein above with reference to FIGS. 7A-7B and 8. In a correctable value calculation step 612, the metrology processor 206 calculates from the measured stitching error correction values ​​(sometimes referred to as "correctable values") for application in the exposure system 20 to reduce the stitching errors produced in the patterning process. In a correction step 614, the calculated correction values ​​are sent to the exposure system 20.

[0087] The calibrated stitching error is compared to a preset stitching error tolerance in decision step 616. If the stitching error is not within the preset tolerance, the photoresist layer 22 is removed from the substrate 24 in a strip step 618, and the substrate is sent back to step 602. If the stitching error meets the tolerance, the semiconductor substrate 24 continues to the next process step 620, and the patterning process continues to step 602 via next substrate step 622.

[0088] The above-described embodiments are cited by way of example, and it will be appreciated that the present invention is not limited to what has been particularly shown and described herein above. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described herein above, as well as variations and modifications of the present invention which would occur to those skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.

Claims

1. 1. A method of semiconductor metrology, comprising: patterning a film layer on a semiconductor substrate to define a first field on the semiconductor substrate with a first pattern including at least a first target feature within a first margin along a first edge of the first field; patterning the film layer on the semiconductor substrate to define a second field bordering the first field, the second field having a second pattern including at least the second target features in the second margin along the second edge of the second field, such that a second edge of the second field is adjacent to the first edge of the first field and the first target features in the first margin are adjacent to the second target features in the second margin without overlapping the second target features; capturing an image of an area of ​​the patterned film layer including at least the first target feature and the second target feature; processing the image to detect misalignment between the first field and the second field; Including, The method, wherein the first target feature and the second target feature each comprise linear gratings that are adjacent to each other without overlapping and perpendicular to each other, and wherein there is no overlapping area between smallest bounding boxes containing the linear gratings.

2. 2. The method of claim 1, wherein processing the image comprises finding a first center of symmetry and a second center of symmetry of the first target feature and the second target feature, respectively; measuring a displacement between the first center of symmetry and the second center of symmetry; and detecting the misalignment by comparing the measured displacement with a nominal displacement.

3. 10. The method of claim 1, wherein the first target feature and the second target feature comprise first and second linear gratings, respectively, oriented along a common grating direction.

4. 4. The method of claim 3, wherein the first linear grating and the second linear grating are oriented along a first grating direction, and patterning the film layer includes forming third and fourth target features along the first edge of the first field and the second edge of the second field, respectively, in margins on opposing first and second sides of the field, the third and fourth target features comprising third and fourth linear gratings, respectively, oriented along a second grating direction that is non-parallel to the first grating direction.

5. 2. The method of claim 1, wherein patterning the film layer includes forming at least a further instance of the first target feature in the first field proximate to the first target feature, and processing the image includes calculating an alignment calibration function using at least the further instance of the first target feature, and applying the alignment calibration function when measuring the misalignment between the first field and the second field.

6. 6. The method of claim 5, wherein the further instance of at least the first target feature includes a copy of the first target feature adjacent to the first target feature, and wherein calculating the alignment calibration function includes measuring a relationship in the image between the copy of the first target feature and the first target feature.

7. 6. The method of claim 5, wherein the further instances of at least the first target feature include copies of both the first target feature and the second target feature.

8. 2. The method of claim 1, wherein patterning the film layer includes defining a third field bordering the second field, the third field having a third pattern including at least the third target features in a third margin along the third edge of the third field, such that a third edge of the third field is adjacent to a fourth edge of the second field, and the second field includes a fourth target feature in the second margin adjacent to the third target feature on the third margin without overlapping the third target feature; The method further comprising capturing a further image including at least the third target feature and the fourth target feature, and processing the further image to detect further misalignment between the second field and the third field.

9. 10. The method of claim 1, further comprising measuring angular misalignment of the semiconductor substrate, and wherein processing the image comprises correcting for the angular misalignment when estimating the misalignment between the first field and the second field.

10. 10. The method of claim 1, further comprising applying the first target feature and the second target feature in measuring an overlay error between successive film layers on the semiconductor substrate.

11. a semiconductor substrate; a film layer disposed on the substrate, a first field on the semiconductor substrate having a first pattern including at least a first target feature within a first margin along a first edge of the first field; and a second field bordering the first field, the second field having a second pattern including at least the second target features in the second margin along the second edge of the second field such that a second edge of the second field is adjacent to the first edge of the first field and the first target features in the first margin are adjacent to the second target features in the second margin without overlapping the second target features; the first target feature and the second target feature are patterned to define a film layer applied to detect misalignment between the first field and the second field; wherein the first target feature and the second target feature each comprise linear gratings that are adjacent to each other without overlapping and perpendicular to each other, and wherein there is no overlapping area between smallest bounding boxes that contain the linear gratings.

12. 12. The article of manufacture of claim 11, wherein the first target feature and the second target feature comprise first and second linear gratings, respectively, oriented along a common grating direction.

13. 13. The article of manufacture of claim 12, wherein the first linear grating and the second linear grating are oriented along a first grating direction, and the film layer is patterned to form third and fourth target features along the first edge of the first field and the second edge of the second field, respectively, in margins on opposing first and second sides of the fields, the third and fourth target features comprising third and fourth linear gratings, respectively, oriented along a second grating direction that is non-parallel to the first grating direction.

14. 12. The article of manufacture of claim 11, wherein the film layer is patterned to form at least additional instances of the first target feature within the first field adjacent to the first target feature.

15. 15. The article of manufacture of claim 14, wherein the further instances of at least the first target feature include copies of the first target feature that are adjacent to the first target feature.

16. 16. The article of manufacture of claim 15, wherein the further instance of at least the first target feature includes a copy of both the first target feature and the second target feature.

17. 12. The article of manufacture of claim 11, wherein the film layer is patterned to define a third field that borders but does not overlap the second field, the third pattern including at least the third target feature in the third margin along the third edge of the third field, such that a third edge of the third field is adjacent to a fourth edge of the second field, and the second field includes a fourth target feature in the second margin adjacent to the third target feature on the third margin without overlapping the third target feature.

18. In an apparatus for semiconductor measurement, 1. An imaging assembly configured to capture an image of a semiconductor substrate having a film layer disposed thereon, the film layer comprising: a first field on the semiconductor substrate having a first pattern including at least a first target feature within a first margin along a first edge of the first field; and a second field that borders but does not overlap the first field, the second field having a second pattern including at least the second target features in the second margin along the second edge of the second field such that a second edge of the second field is adjacent to the first edge of the first field and the first target features in the first margin are adjacent to the second target features in the second margin without overlapping the second target features; an imaging assembly that is patterned to define a processor configured to process the image to detect misalignment between the first field and the second field; and wherein the first target feature and the second target feature each comprise linear gratings that are adjacent to each other without overlapping and perpendicular to each other, and wherein smallest bounding boxes containing the linear gratings have no overlapping area between them.

19. 20. The apparatus of claim 18, wherein the processor is configured to find first and second centers of symmetry of the first and second target features, respectively, measure a displacement between the first and second centers of symmetry, and detect the misalignment by comparing the measured displacement with a nominal displacement.

20. 20. The apparatus of claim 18, wherein the film layer is patterned to form at least a further instance of the first target feature in the first field proximate to the first target feature, and the processor is configured to calculate an alignment calibration function using at least the further instance of the first target feature and to apply the alignment calibration function when measuring the misalignment between the first field and the second field.

21. 21. The apparatus of claim 20, wherein the further instance of at least the first target feature includes a copy of the first target feature adjacent to the first target feature, and the processor is configured to measure a relationship in the image between the copy of the first target feature and the first target feature and to apply the relationship when measuring the misalignment.

22. 20. The apparatus of claim 18, wherein the processor is configured to measure angular misalignment of the semiconductor substrate and to correct for the angular misalignment when estimating the misalignment between the first field and the second field.

Images