Semiconductor device

Abstract

To provide a semiconductor device that can suppress changes in the responsiveness of a switching element even when the driving capability for driving the switching element is changed.SOLUTION: A semiconductor device 1 according to an embodiment includes an IGBT 121, a state detection unit 113 that detects the operating state of the IGBT 121, a switching time adjustment unit 111 that adjusts the switching time of the IGBT 121 in accordance with the operating state detected by the state detection unit 113, and a drive current adjustment unit 112 that adjusts the drive current Idv that drives the IGBT 121 in accordance with the operating state detected by the state detection unit 113.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including a switching element. [Background technology]

[0002] Patent Documents 1 to 3 disclose techniques for changing the driving capacity for driving a switching element in accordance with the load current that the switching element supplies to a load when the switching element is turned on or off. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-158361 [Patent Document 2] Japanese Patent Publication No. 2020-136874 [Patent Document 3] International Publication No. 2017 / 150036 Summary of the Invention [Problem to be solved by the invention]

[0004] When the driving capability of a switching element is changed in response to a load current, the driving capability of the switching element is set to be higher as the load current increases, which increases the voltage change rate (dv / dt) of the switching element when it is turned on or off. In this way, changing the driving capability of a switching element in response to a load current changes the responsiveness of the switching element, which increases the possibility of unstable operation of a device that includes the switching element.

[0005] An object of the present invention is to provide a semiconductor device that can suppress changes in the responsiveness of a switching element even when the driving capability for driving the switching element is changed. [Means for solving the problem]

[0006] In order to achieve the above object, a semiconductor device according to one aspect of the present invention comprises a switching element, a state detection unit that detects the operating state of the switching element, a switching time adjustment unit that adjusts the switching time of the switching element in accordance with the operating state detected by the state detection unit, and a drive current adjustment unit that adjusts the drive current that drives the switching element in accordance with the operating state detected by the state detection unit. [Effects of the Invention]

[0007] According to each aspect of the present invention, even if the driving capability for driving a switching element is changed, it is possible to suppress changes in the responsiveness of the switching element. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram showing an example of a schematic configuration of a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 1 is a diagram showing the relationship between the load current and the voltage change rate of a switching element in the prior art. [Figure 3] FIG. 1 is a diagram showing the relationship between the load current and the turn-on time of a switching element in the prior art. [Figure 4] 1 is a diagram for explaining the semiconductor device according to the first embodiment of the present invention, and is a timing chart schematically showing an example of an operating waveform when a switching element is turned on. FIG. [Figure 5] FIG. 10 is a block diagram (part 1) showing an example of a schematic configuration of a semiconductor device according to a second embodiment of the present invention. [Figure 6] FIG. 10 is a block diagram (part 2) showing an example of a schematic configuration of a semiconductor device according to a second embodiment of the present invention. [Figure 7] FIG. 10 is a diagram for explaining a semiconductor device according to a second embodiment of the present invention, and is a timing chart schematically showing an example of an operating waveform when a switching element is turned on. [Figure 8] FIG. 10 is a block diagram showing an example of a schematic configuration of a semiconductor device according to a third embodiment of the present invention. [Figure 9] FIG. 10 is a block diagram (part 1) showing an example of a schematic configuration of a semiconductor device according to a fourth embodiment of the present invention. [Figure 10] FIG. 10 is a block diagram (part 2) showing an example of a schematic configuration of a semiconductor device according to a fourth embodiment of the present invention. [Figure 11] FIG. 10 is a diagram for explaining a semiconductor device according to a fourth embodiment of the present invention, and is a timing chart schematically showing an input signal and an output signal output from a switching time adjustment section. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments of the present invention are merely examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components to be described below. The technical idea of ​​the present invention can be modified in various ways within the technical scope defined by the claims.

[0010] [First embodiment] A semiconductor device according to a first embodiment of the present invention will be described with reference to Figures 1 to 4. The semiconductor device according to this embodiment and each of the embodiments described below can be applied to, for example, an intelligent power module (IPM) in which a semiconductor chip having a power semiconductor element (e.g., an insulated gate bipolar transistor) for power conversion and an integrated circuit for driving and protecting the semiconductor chip are integrated into a single package. Hereinafter, "insulated gate bipolar transistor" may be abbreviated as "IGBT" (Insulated Gate Bipolar Transistor).

[0011] 1-1.Configuration of semiconductor device: The schematic configuration of the semiconductor device according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the schematic configuration of a semiconductor device 1 according to this embodiment.

[0012] 1, the semiconductor device 1 includes a semiconductor control circuit 11 and a semiconductor element 12. The semiconductor element 12 includes an IGBT 121 and a state detection element 122. The semiconductor element 12 may include a free wheel diode connected in anti-parallel to the IGBT 121. The semiconductor element 12 is configured, for example, by a semiconductor chip on which the IGBT 121 and the state detection element 122 are formed.

[0013] As described above, the semiconductor device 1 includes the IGBT 121 (an example of a switching element). The operating state of the IGBT 121 is, for example, how much current the IGBT 121 is supplying to a load device (not shown) to be driven, or the temperature at which the IGBT 121 is operating. Therefore, the state detection element 122 may be, for example, a current detection element that detects the current flowing through the IGBT 121 or a temperature detection element that detects the temperature of the IGBT 121.

[0014] The load device is connected to the emitter of the IGBT 121 when the semiconductor device 1 is, for example, a power converter and the IGBT 121 forms the upper arm of the power converter. On the other hand, the load device is connected to the emitter of the IGBT 121 when the IGBT 121 forms the lower arm of the power converter. The gate of the IGBT 121 is connected to a gate input terminal Tgi provided in the semiconductor element 12. The output terminal of the state detection element 122 is connected to a detection terminal Tdo provided in the semiconductor element 12.

[0015] 1, the semiconductor control circuit 11 has a switching time adjustment unit 111, a drive current adjustment unit 112, and a state detection unit 113. Therefore, the semiconductor device 1 includes the switching time adjustment unit 111, the drive current adjustment unit 112, and the state detection unit 113. The semiconductor control circuit 11 is an integrated circuit for driving and protecting the IGBT 121.

[0016] An input terminal of the state detection unit 113 is connected to a detection signal input terminal Tdi provided in the semiconductor control circuit 11. The detection signal input terminal Tdi is connected to a detection terminal Tdo provided in the semiconductor element 12. Therefore, the state detection unit 113 detects the operating state of the IGBT 121, for example, using a detection signal Sos input from the state detection element 122. The state detection unit 113 outputs a state detection signal Sosd detected using the detection signal Sos.

[0017] The switching time adjustment unit 111 has two input terminals, one of which is connected to a signal input terminal Tic provided in the semiconductor control circuit 11, and the other of which is connected to an output terminal of the state detection unit 113. The switching time adjustment unit 111 adjusts the switching time of the IGBT 121 in accordance with the operating state of the IGBT 121 detected by the state detection unit 113. The switching time adjustment unit 111 adjusts the switching time in accordance with the signal level of a state detection signal Sosd input from the state detection unit 113. As will be described in detail later, when the state detection unit 113 detects that the IGBT 121 is in a predetermined operating state, the switching time adjustment unit 111 delays the input signal Sin input via the signal input terminal Tic by a predetermined time and outputs the delayed signal. As a result, the semiconductor device 1 can maintain approximately the same switching time regardless of the operating state of the IGBT 121 by having the switching time adjustment unit 111 delay the input signal Sin by the predetermined time.

[0018] The drive current adjuster 112 has two input terminals, one of which is connected to the output terminal of the switching time adjuster 111, and the other of which is connected to the output terminal of the state detector 113. The drive current adjuster 112 adjusts the drive current Idv that drives the IGBT 121 in accordance with the operating state of the IGBT 121 detected by the state detector 113. The drive current adjuster 112 adjusts the drive current Idv in accordance with the signal level of a state detection signal Sosd input from the state detector 113. The drive current adjuster 112 adjusts the amount of the drive current Idv so that it becomes larger, for example, when the IGBT 121 is in an operating state in which the input signal Sin is delayed by a predetermined time in the switching time adjuster 111. This allows the semiconductor device 1 to suppress changes in the responsiveness of the IGBT 121 regardless of the amount of load current supplied by the IGBT 121 to the load device.

[0019] 1-2. Operation of semiconductor device: The operation of the semiconductor device 1 according to this embodiment will be described with reference to Fig. 1 and Fig. 2 to Fig. 4. Problems with the prior art will also be described in the description of the operation of the semiconductor device 1. Fig. 2 to Fig. 4 explain the operation state of the IGBT by taking as an example the amount of current flowing through the IGBT (i.e., the load current supplied by the IGBT to the load).

[0020] 2 is a graph showing an example of the relationship between the load current and the voltage change rate when an IGBT is turned on. The horizontal axis of the graph shown in FIG. 2 represents the load current, and the vertical axis of the graph represents the voltage change rate (dv / dt).

[0021] When the load current is low, for example, 15% or less of the rated current Icr, the IGBT is driven with a lower driving capability than when the load current is normal, for example, greater than 15% but less than 100% of the rated current Icr. In this case, as shown in Figure 2, the voltage change rate of the IGBT is reduced at low currents compared to normal currents.

[0022] 3 is a graph showing an example of the relationship between the load current and the turn-on time in an IGBT, where the horizontal axis of the graph shown in FIG. 3 represents the load current, and the vertical axis of the graph represents the turn-on time.

[0023] When the load current is low, for example, 15% or less of the rated current Icr, the IGBT is driven with a lower driving capability than when the load current is normal, for example, greater than 15% but less than 100% of the rated current Icr. In this case, as shown in Figure 3, the turn-on time of the IGBT is longer when the load current is low than when the load current is normal.

[0024] Although not shown, if an IGBT is driven at the same drive capacity at low currents as at normal currents, the voltage change rate of the IGBT increases rapidly as the load current decreases at low currents. Therefore, if the IGBT is driven at the same drive capacity at low currents as at normal currents, the IGBT's tolerance to noise signals will decrease, increasing the likelihood of malfunction. Therefore, as shown in Figure 2, the IGBT is driven at a drive capacity lower than at normal currents, thereby reducing the likelihood of malfunction.

[0025] However, as explained with reference to Figure 3, when an IGBT is driven with its driving capability reduced at a lower current than at a normal current, its turn-on time becomes longer at the lower current than at the normal current. If the turn-on time of an IGBT changes depending on the load current, the responsiveness of the IGBT also changes, increasing the possibility of unstable operation of a device including the IGBT. Therefore, it is difficult to simultaneously suppress malfunctions caused by a decrease in the IGBT's tolerance to noise signals and reduce operational instability caused by changes in the IGBT's responsiveness.

[0026] FIG. 4 is a timing chart schematically showing a portion of the operating waveforms of the IGBT 121 provided in the semiconductor device 1 according to this embodiment and the conventional IGBT when they are turned on. The upper part of FIG. 4 shows the operating waveforms of the IGBT 121 and the conventional IGBT. The middle part of FIG. 4 shows the operating waveforms of the conventional IGBT. The lower part of FIG. 4 shows the operating waveforms of the IGBT 121. "Sin" in FIG. 4 indicates the input signal input to the semiconductor control circuit 11 or the conventional semiconductor control circuit. "Ic" in FIG. 4 indicates the collector current of the IGBT 121 or the conventional IGBT (i.e., the load current supplied to the load device). "Sdy" in FIG. 4 indicates a delayed signal obtained by delaying the input signal.

[0027] The upper part of FIG. 4 shows operational waveforms when the IGBT 121 or the conventional IGBT is driven with the drive current during low current operation described in FIGS. 2 and 3. The middle part of FIG. 4 shows operational waveforms when the conventional IGBT is driven with the drive current during normal operation described in FIGS. 2 and 3. The lower part of FIG. 4 shows operational waveforms when the switching time is adjusted and the IGBT 121 is driven with the drive current during normal operation described in FIGS. 2 and 3. The operational waveforms shown from the upper to lower parts of FIG. 4 share the same DC voltage applied to the IGBT 121 or the conventional IGBT, the emitter-collector voltage when the IGBT 121 or the IGBT is in the off state, the inductance value of the load, and the load current supplied to the load. The operational waveforms shown in the lower part of FIG. 4 show the IGBT 121 driven with a drive current twice as large as that shown in the upper part of FIG. 4.

[0028] As shown in the upper and middle sections of Figure 4, when a conventional IGBT is turned on, the switching time ton1 at normal current is, for example, 90% of the switching time ton0 at low current. The peak current during collector current Ic overshoot is larger at normal current than at low current because the switching time is shorter. This means that the conventional IGBT has lower noise signal tolerance at normal current than at low current. In Figure 4, the switching time of IGBT 121 or the conventional IGBT is the time from when the input signal Sin is input until the collector current Ic reaches 90% of its target value.

[0029] In the semiconductor device 1 according to this embodiment, the switching time adjustment unit 111 (see FIG. 1) outputs the input signal Sin to the drive current adjustment unit 112 without delay, for example, during low current. Therefore, as shown in the upper part of FIG. 4, the switching time of the IGBT 121 according to this embodiment is the switching time ton0, similar to that of a conventional IGBT.

[0030] On the other hand, in the semiconductor device 1 according to this embodiment, the switching time adjustment unit 111 delays the input signal Sin during normal current, for example, and outputs the delayed signal to the drive current adjustment unit 112. Therefore, as shown in the lower part of FIG. 4 , the IGBT 121 according to this embodiment has a switching time ton1, which is approximately the same length as the switching time of a conventional IGBT, when the input timing of the delay signal Sdy, which triggers the start of supply of the drive current Idv, is used as a reference. However, the delay signal Sdy is a signal obtained by delaying the input signal Sin by the delay time Tdy in the switching time adjustment unit 111. Therefore, the switching time ton3 of the IGBT 121 during normal current is approximately the same length as the switching time ton0 of the IGBT 121 during low current.

[0031] In this way, in the semiconductor device 1, the voltage change rate of the IGBT 121 is larger during low current than during normal operation, thereby shortening the rise time from when the supply of the drive current Idv begins until the collector current Ic of the IGBT 121 reaches a target value. By adjusting the delay time of the input signal Sin in accordance with the voltage change rate for each load current of the IGBT 121, the semiconductor device 1 can offset the shortened rise time, thereby improving the tolerance of the input signal Sin to noise signals and suppressing a decrease in the responsiveness of the IGBT 121.

[0032] Incidentally, the higher the operating temperature of the IGBT 121, the slower the switching time becomes. For this reason, when the operating state of the IGBT 121 is at the operating temperature, the switching time adjustment unit is configured to adjust the switching time so that the delay time becomes shorter as the operating temperature increases.

[0033] As described above, the semiconductor device 1 according to this embodiment includes the IGBT 121, a state detection unit 113 that detects the operating state of the IGBT 121, a switching time adjustment unit 111 that adjusts the switching time of the IGBT 121 in accordance with the operating state detected by the state detection unit 113, and a drive current adjustment unit 112 that adjusts the drive current Idv that drives the IGBT 121 in accordance with the operating state detected by the state detection unit 113.

[0034] With this configuration, the semiconductor device 1 can suppress changes in the responsiveness of the switching element even when the driving capability for driving the switching element is changed.

[0035] Second Embodiment A semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS.

[0036] 2-1.Configuration of semiconductor device: The schematic configuration of the semiconductor device 2 according to the present embodiment will be described with reference to FIGS. 5 and 6. FIGS. 5 and 6 are block diagrams showing an example of the schematic configuration of the semiconductor device 2 according to the present embodiment. In FIG. 5, the specific configuration of the drive current adjustment unit 212 provided in the semiconductor device 2 is omitted. In FIG. 6, the specific configuration of the delay time adjustment circuit 211AC provided in the semiconductor device 2 is omitted. In the semiconductor device 2 according to the present embodiment, components that have the same actions and functions as the components of the semiconductor device 1 according to the first embodiment are denoted by the same reference numerals, and their description will be omitted.

[0037] 5 and 6, the semiconductor device 2 according to this embodiment includes a semiconductor control circuit 21 and a semiconductor element 22. The semiconductor element 22 includes an IGBT 221 and a current detection element 222. Therefore, the semiconductor device 2 includes the IGBT 221 (an example of a switching element) and the current detection element 222. The current detection element 222 detects a detection current Is for detecting a load current IL supplied by the IGBT 221 to a load. The semiconductor element 22 may include a free wheel diode connected in anti-parallel to the IGBT 221. The semiconductor element 22 is configured, for example, by a semiconductor chip on which the IGBT 221 and the current detection element 222 are formed.

[0038] The semiconductor control circuit 21 provided in the semiconductor device 2 has a switching time adjustment unit 211, a drive current adjustment unit 212, and a state detection unit 213. The semiconductor control circuit 21 is an integrated circuit for driving and protecting the IGBT 221.

[0039] The state detection unit 213 detects the operating state of the IGBT 221. The state detection unit 213 has a current detection unit 213ID that detects the magnitude of a load current IL corresponding to a detection current Is detected by the current detection element 222 as the operating state of the IGBT 221. The current detection unit 213ID has a current-voltage conversion circuit 213a (an example of a conversion circuit) that converts the detection current Is into a detection voltage Vs, and a buffer circuit 213b that outputs the detection voltage Vs output from the current-voltage conversion circuit 213a as a current detection signal Ss having a signal level according to the magnitude of the load current IL.

[0040] The current-voltage conversion circuit 213a has a resistor element R213. One terminal of the resistor element R213 is connected to the detection signal input terminal Tdi. The other terminal of the resistor element R213 is connected to a reference potential terminal (e.g., a ground terminal) of the semiconductor control circuit 21. The current-voltage conversion circuit 213a outputs a voltage generated between one terminal and the other terminal of the resistor element R213 as a detection voltage Vs to the buffer circuit 213b when a detection current Is input from the current detection element 222 flows. The buffer circuit 213b is configured, for example, with an operational amplifier. One terminal of the resistor element R213 is connected to a non-inverting input terminal (+) of the buffer circuit 213b. The inverting input (-) of the buffer circuit 213b is connected to the output terminal of the buffer circuit 213b. Therefore, the buffer circuit 213b functions as a voltage follower circuit and outputs a current detection signal Ss having the same voltage level as the detection voltage Vs.

[0041] The switching time adjustment unit 211 includes a NOT gate 211a, a transistor 215b, a delay time adjustment circuit 211AC, a buffer circuit 211e, and a NOT gate 211f. An input terminal of the NOT gate 211a is connected to a signal input terminal Tic provided in the semiconductor control circuit 21. An output terminal of the NOT gate 211a is connected to a transistor 211b. The transistor 211b is configured, for example, by an N-type MOSFET (metal oxide semiconductor field effect transistor). An output terminal of the NOT gate 211a is connected to a gate of the transistor 211b. A source of the transistor 211b is connected to a reference potential terminal (for example, a ground terminal) of the semiconductor control circuit 21. A drain of the transistor 211b is connected to a delay time adjustment circuit 211AC.

[0042] The input terminal of the NOT gate 211f is connected to the output terminal of the buffer circuit 213b. The output terminal of the NOT gate 211f is connected to the delay time adjustment circuit 211AC. The NOT gate 211f inverts the signal level of the current detection signal Ss input from the buffer circuit 213b and outputs the inverted signal to the delay time adjustment circuit 211AC.

[0043] The delay time adjustment circuit 211AC adjusts the delay time of the input signal Sin input from the outside (for example, a control device (not shown) that controls the semiconductor control circuit 21) in accordance with the signal level of the current detection signal Ss input from the current detection unit 213ID. The delay time adjustment circuit 211AC has a variable constant current source 211c, a delay time changing unit 211d, and a buffer circuit 211e.

[0044] The variable constant current source 211c is powered by a power supply that drives the delay time adjustment circuit 211AC. The output terminal of the NOT gate 211f is connected to a current control terminal of the variable constant current source 211c. The variable constant current source 211c outputs a constant current of a different current value depending on the signal level (e.g., voltage level) of the current detection signal Ss input from the buffer circuit 213b. More specifically, the variable constant current source 211c outputs a constant current of a different current value depending on the signal level (e.g., voltage level) of the current detection signal Ss input from the buffer circuit 213b and inverted by the NOT gate 211f. The variable constant current source 211c has a configuration similar to that of the variable constant current source 212VC provided in the drive current adjustment unit 212, which will be described later. The lower the signal level of the inverted signal input from the NOT gate 211f (i.e., the higher the signal level of the current detection signal Ss), the smaller the constant current value that the variable constant current source 211c outputs. Moreover, the higher the signal level of the inverted signal input from the NOT gate 211f (ie, the lower the signal level of the current detection signal Ss), the larger the constant current value that the variable constant current source 211c outputs.

[0045] The output terminal of the variable constant current source 211c is connected to the drain of the transistor 211b and the delay time changer 211d. The delay time changer 211d includes a resistor R211d and a capacitor C211d. The delay time adjustment circuit 211AC adjusts the delay time of the input signal Sin based on a time constant determined by the amount of current input from the variable constant current source 211c to the delay time changer 211d and the resistance value of the resistor R211d and the capacitance value of the capacitor C211d. Because the time constant is a fixed value, the delay time adjustment circuit 211AC outputs a delayed signal Sdy obtained by delaying the input signal Sin in accordance with the current value of the output current Iout output from the variable constant current source 211c.

[0046] One terminal of a resistor R211d provided in the delay time changer 211d is connected to the output terminal of the variable constant current source 211c and the drain of the transistor 211b. The other terminal of the resistor R211d is connected to one electrode of a capacitor C211d. The other electrode of the capacitor C211d is connected to a reference potential terminal (e.g., a ground terminal) of the semiconductor control circuit 21. An input terminal of a buffer circuit 211e is connected to the output terminal of the delay time changer 211d (the connection between the other terminal of the resistor R211d and one electrode of the capacitor C211d). Like the buffer circuit 213b, the buffer circuit 211e configures, for example, a voltage follower circuit. An output terminal of the buffer circuit 211e is connected to the input terminal of the drive current adjuster 212. As a result, the buffer circuit 211e outputs the delay signal Sdy input from the delay time changer 211d to the drive current adjuster 212 without changing the signal level.

[0047] The variable constant current source 211c outputs an output current Iout with a smaller current value as the signal level (i.e., voltage level) of the current detection signal Ss input from the current detection unit 213ID increases. On the other hand, the variable constant current source 211c outputs an output current Iout with a larger current value as the signal level (i.e., voltage level) of the current detection signal Ss input from the current detection unit 213ID decreases. In other words, the variable constant current source 211c outputs an output current Iout with a larger current value as the current value of the load current IL supplied to the load device by the IGBT 221 decreases. On the other hand, the variable constant current source 211c outputs an output current Iout with a smaller current value as the current value of the load current IL supplied to the load device by the IGBT 221 increases.

[0048] When the signal level of the input signal Sin switches from low to high, the transistor 211b transitions from an on state to an off state, disconnecting the output terminal of the variable constant current source 211c from the reference potential terminal. As a result, the output current Iout output from the variable constant current source 211c flows to the delay time changer 211d, causing the delay signal Sdy output from the delay time changer 211d to rise. The rise time of the delay signal Sdy depends on the current value of the output current Iout output from the variable constant current source 211c, and becomes shorter as the current value increases.

[0049] Furthermore, when the signal level of the input signal Sin switches from high to low, the transistor 211b transitions from an off state to an on state, connecting the output terminal of the variable constant current source 211c to the reference potential terminal. This causes the output current Iout output from the variable constant current source 211c to flow to the reference potential terminal. Furthermore, the capacitor C211d provided in the delay time changer 211d discharges, causing the delay signal Sdy output from the delay time changer 211d to fall. The charge stored in the capacitor C211d is drawn more quickly the greater the amount of output current Iout flowing from the variable constant current source 211c to the reference potential terminal, shortening the discharge time of the capacitor C211d. Therefore, the greater the amount of current, the shorter the fall time of the delay signal Sdy. The delay time changer 211d not only generates the delay signal Sdy delayed relative to the input signal Sin, but also suppresses ringing that occurs in the output current Iout output from the variable constant current source 211c.

[0050] The timing at which the signal level of the input signal Sin switches is the input timing of the input signal Sin. The drive current adjustment unit 212 generates the drive current Idv by receiving the delay signal Sdy. Therefore, the delay time is the time from when the input signal Sin is input to the switching time adjustment unit 211, when the delay signal Sdy is output to the drive current adjustment unit 212, and when the drive current Idv starts to be supplied to the IGBT 221. The timing at which the drive current Idv starts to be supplied to the IGBT 221 is, for example, the time when the current value of the collector current (i.e., the load current IL) flowing through the IGBT 221 reaches 10% of the target value.

[0051] In this way, the switching time adjustment unit 211 delays the input signal Sin according to the magnitude of the load current IL detected by the current detection unit 213ID. As a result, the switching time adjustment unit 211 adjusts the switching time of the IGBT 221 according to the magnitude of the load current IL detected by the current detection unit 213ID as the operating state of the IGBT 221. Furthermore, the variable constant current source 211c provided in the delay time adjustment circuit 211AC can continuously change the amount of the output current Iout according to continuous changes in the signal level (i.e., voltage level) of the current detection signal Ss input from the current detection unit 213ID. Therefore, the switching time adjustment unit 211 continuously adjusts the switching time according to fluctuations in the detection current Is.

[0052] 6, the drive current adjuster 212 includes an operational amplifier 212a, transistors 212b, 212c, 212e, 212f, and 212g, and a resistor 212d. The transistor 212c is configured, for example, by an N-type MOSFET, and the transistors 212b, 212e, 212f, and 212g are configured, for example, by a P-type MOSFET.

[0053] The transistor 212e and the transistor 212f form a current mirror circuit 212CM. The source of the transistor 212e is connected to a power supply terminal to which power for driving the gate drive circuit 212DC is supplied. The drain of the transistor 212e is connected to the gates of the transistors 212e and 212f and the drain of the transistor 212c.

[0054] The source of the transistor 212f is connected to a power supply terminal to which power for driving the gate drive circuit 212DC is supplied. The drain of the transistor 212f is connected to the source of the transistor 212g. The drain of the transistor 212g is connected to a reference potential terminal (for example, a ground terminal) of the semiconductor control circuit 21. The gate of the transistor 212g is connected to an output terminal of the switching time adjustment unit 211 (specifically, the output terminal of the buffer circuit 211e). The connection point between the source of the transistor 212f and the drain of the transistor 212g is connected to the current output terminal Toc. The connection point between the source of the transistor 212f and the drain of the transistor 212g becomes the output terminal of the drive current adjustment unit 212.

[0055] The operational amplifier 212a, the transistors 212b and 212c, and the resistor element 212d constitute a variable constant current source 212VC. The non-inverting input terminal (+) of the operational amplifier 212a, which serves as a current control terminal of the variable constant current source 212VC, is connected to the output terminal of the current detection unit 213ID. The inverting input terminal (-) of the operational amplifier 212a is connected to the source of the transistor 212c and one terminal of the resistor element 212d. The output terminal of the operational amplifier 212a is connected to the gate of the transistor 212c and the source of the transistor 212b. The drain of the transistor 212b is connected to a reference potential terminal (e.g., a ground terminal) of the semiconductor control circuit 21. The gate of the transistor 212b is connected to an output terminal of the switching time adjustment unit 211 (specifically, the output terminal of the buffer circuit 211e). The other terminal of the resistor element 212d is connected to a reference potential terminal (e.g., a ground terminal) of the semiconductor control circuit 21.

[0056] The variable constant current source 212VC controls the transistor 212c so that a constant current corresponding to the voltage level of the current detection signal Ss input to the non-inverting input terminal (+) of the operational amplifier 212a flows from the current mirror circuit 212CM.

[0057] When the signal level of the delay signal Sdy input from the switching time adjustment unit 211 becomes high, the transistor 212b becomes off, and the variable constant current source 212VC operates to pass a constant current corresponding to the voltage level of the current detection signal Ss to the transistor 212c. Furthermore, when the signal level of the delay signal Sdy input from the switching time adjustment unit 211 becomes high, the transistor 212g becomes off, and the current mirror circuit 212CM outputs a current corresponding to the current passed by the variable constant current source 212VC to the gate of the IGBT 221 as the drive current Idv (i.e., gate current).

[0058] The output voltage of the operational amplifier 212a fluctuates in accordance with fluctuations in the voltage level of the current detection signal Ss. Therefore, the drive current Idv fluctuates in accordance with fluctuations in the voltage level of the current detection signal Ss. The current detection signal Ss is a signal obtained by current-voltage conversion of the detection current Is detected by the current detection element 222, and therefore fluctuates in accordance with fluctuations in the detection current Is. The detection current Is is a current that changes continuously. Therefore, the drive current adjustment unit 212 continuously adjusts the drive current Idv in accordance with fluctuations in the detection current Is.

[0059] The voltage level of the current detection signal Ss output from the current detection unit 213ID is based on the magnitude of the load current IL supplied to the load device by the IGBT 221. Therefore, the drive current adjustment unit 212 can supply to the gate of the IGBT 221 a drive current Idv that corresponds to the magnitude of the load current IL supplied to the load device by the IGBT 221. In this way, the drive current adjustment unit 212 adjusts the drive current Idv that drives the IGBT 221 according to the magnitude of the load current IL detected by the current detection unit 213ID as the operating state of the IGBT 221.

[0060] Furthermore, when the delay signal Sdy is input from the switching time adjustment circuit 211, the drive current adjustment unit 212 starts supplying the drive current Idv to the IGBT 221. Therefore, the drive current adjustment unit 212 supplies the IGBT 221 with the drive current Idv that is delayed according to the current value of the load current IL that the IGBT 221 supplies to the load device, relative to the input timing of the input signal Sin. In this way, the drive current adjustment unit 212 has a gate drive circuit 212DC (an example of a drive circuit) that drives the IGBT 221 with the drive current Idv of a current amount according to the signal level of the current detection signal Ss when the delay signal Sdy, which is obtained by delaying the input signal Sin, is input from the delay time adjustment circuit 211AC.

[0061] 2-2. Operation of semiconductor device: The operation of the semiconductor device 2 according to this embodiment will be described using FIG. 7 with reference to FIGS. 5 and 6. FIG. 7 is a timing chart schematically showing a portion of the operating waveform of the semiconductor device 2. "Sin" in FIG. 7 indicates an input signal input to the switching time adjustment unit 211. "Sinv" in FIG. 7 indicates an inverted signal output from the NOT gate 211a provided in the switching time adjustment unit 211. "Sdy" in FIG. 7 indicates a delayed signal output from the delay time adjustment circuit 211AC. "IL" in FIG. 7 indicates a load current supplied to the load device by the IGBT 221.

[0062] 7, when the input signal Sin rises, the inverted signal Sinv falls. When the voltage level of the inverted signal Sinv becomes lower than the threshold voltage of the transistor 211b, the transistor 211b turns off, and the output current Iout output from the variable constant current source 211c flows to the delay time changer 211d. This causes the signal level of the delay signal Sdy to rise.

[0063] When the load current IL supplied from the IGBT 221 to the load device is the smallest within its supplyable range (i.e., when its target value is the smallest), the signal level of the current detection signal Ss becomes the lowest within its variable range. Therefore, the amount of the output current Iout output from the variable constant current source 211c provided in the delay time adjustment circuit 211AC becomes the largest within its variable range. As a result, as shown by the waveform Sdyn in FIG. 7, the delay signal Sdy rises the earliest within its variable range and becomes a signal delayed by the delay time Tdyn relative to the input signal Sin. When the voltage level of the delay signal Sdy becomes higher than the threshold voltages of the transistors 212b and 212g, the transistors 212b and 212g are turned off, causing the drive current Idv to flow to the gate of the IGBT 221.

[0064] At this time, the signal level of current detection signal Ss is the lowest within its variable range, so the current passed to transistor 212c by variable constant current source 212VC provided in gate drive circuit 212DC of drive current adjuster 212 is also the smallest within its variable range. Therefore, the current supply capability of drive current adjuster 212 is the lowest, and the rise time of load current IL is the longest within its variable range, as shown by waveform ILn in the lower part of Figure 7. As a result, the switching time of IGBT 221 at low currents is switching time SWT.

[0065] As the load current IL of the IGBT 221 increases, the signal level of the current detection signal Ss increases, and as a result, the delay signal Sdy rises the latest within its variable range, and is delayed by a delay time Tdyx relative to the input signal Sin, as shown by the waveform Sdyx in Figure 7. The delay time Tdyx is the longest time within the fluctuation range of the delay signal Sdy.

[0066] At this time, the signal level of current detection signal Ss is the highest within its variable range, so the current passed to transistor 212c by variable constant current source 212VC provided in gate drive circuit 212DC of drive current adjustment unit 212 is the largest within its variable range. Therefore, the current supply capability of drive current adjustment unit 212 is the highest, and the rise time of load current IL is the shortest within its variable range, as shown by waveform ILx in the lower part of Figure 7. As a result, the switching time of IGBT 221 during normal operation is switching time SWT, the same as when the current is low.

[0067] 7, the rise time of the delay signal Sdy changes continuously in accordance with the continuous change in the load current IL (i.e., the continuous change in the signal level of the current detection signal Ss). Therefore, the switching time of the IGBT 221 also changes continuously in accordance with the continuous change in the load current IL (i.e., the continuous change in the signal level of the current detection signal Ss).

[0068] As described above, the semiconductor device 2 according to this embodiment includes the IGBT 221, a state detection unit 213 that detects the operating state of the IGBT 221, a switching time adjustment unit 211 that adjusts the switching time of the IGBT 221 in accordance with the operating state detected by the state detection unit 213, and a drive current adjustment unit 212 that adjusts the drive current Idv that drives the IGBT 221 in accordance with the operating state detected by the state detection unit 213.

[0069] With this configuration, the semiconductor device 2 can suppress changes in the responsiveness of the switching element even when the driving capability for driving the switching element is changed.

[0070] Third Embodiment A semiconductor device according to a third embodiment of the present invention will be described with reference to Fig. 8. Fig. 8 is a block diagram showing an example of a schematic configuration of a semiconductor device 3 according to this embodiment. In the semiconductor device 3 according to this embodiment, components that have the same actions and functions as those of the semiconductor device 2 according to the second embodiment described above are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0071] 3-1. Structure of semiconductor device: 8, the semiconductor device 3 according to this embodiment includes a semiconductor control circuit 31 and a semiconductor element 22. The semiconductor control circuit 31 includes a switching time adjustment unit 311, a drive current adjustment unit 312, and a state detection unit 313.

[0072] The state detection unit 313 has a current detection unit 313ID that detects the magnitude of the load current IL corresponding to the detection current Is detected by the current detection element 222 as the operating state of the IGBT 221.

[0073] The current detection unit 313ID includes a current-voltage conversion circuit 313a (an example of a conversion circuit) that converts the detection current Is into a detection voltage Vs, and a comparator 313b that outputs a current detection signal Ss having a signal level based on a comparison result between the detection voltage Vs output from the current-voltage conversion circuit 313a and a reference voltage Vr. The current detection unit 313ID further includes a reference voltage generation circuit 313c that generates the reference voltage Vr.

[0074] The current-voltage conversion circuit 313a has a resistor element R313. The current-voltage conversion circuit 313a outputs a voltage generated across both terminals of the resistor element R313 as a detection voltage Vs to a comparator 313b when a detection current Is input from the current detection element 222 flows. The current-voltage conversion circuit 313a has a similar configuration to the current-voltage conversion circuit 213a in the second embodiment, except that the detection voltage Vs is output to the comparator 313b.

[0075] The reference voltage generating circuit 313c is configured by, for example, a DC voltage source. The positive electrode of the reference voltage generating circuit 313c is connected to the input terminal of the comparator 313b, and the negative electrode of the reference voltage generating circuit 313c is connected to a reference potential terminal (for example, a ground terminal) of the semiconductor control circuit 31.

[0076] The comparator 313b is configured with, for example, an operational amplifier. The non-inverting input terminal (+) of the comparator 313b is connected to the output terminal of the current-voltage conversion circuit 313a (specifically, one terminal of the resistor element R313). The inverting input terminal (-) of the comparator 313b is connected to the positive side of the reference voltage generation circuit 313c. When the detection voltage Vs is lower than the reference voltage Vr, the comparator 313b outputs a current detection signal Ss whose signal level is low. On the other hand, when the detection voltage Vs is higher than the reference voltage Vr, the comparator 313b outputs a current detection signal Ss whose signal level is high.

[0077] The detection voltage Vs increases as the detection current Is increases. The detection current Is increases as the load current IL increases. Therefore, the comparator 313b outputs a current detection signal Ss with a low signal level when the load current IL is smaller than the current corresponding to the reference voltage Vr. The comparator 313b outputs a current detection signal Ss with a low signal level when the load current IL is larger than the current corresponding to the reference voltage Vr. The current corresponding to the reference voltage Vr is a current that serves as a boundary between the current during low current and the current during normal operation, as described in the first embodiment. For example, the current corresponding to the reference voltage Vr is a current with an amount that is 15% of the rated current of the IGBT 221.

[0078] The switching time adjustment unit 311 includes an AND gate 311a and a delay time adjustment circuit 311b. One input terminal of the AND gate 311a is connected to a signal input terminal Tic provided in the semiconductor control circuit 31, and the other input terminal of the AND gate 311a is connected to an output terminal (more specifically, the output terminal of the comparator 313b) of the state detection unit 313. The AND gate 311a outputs a calculation signal obtained by performing a logical AND operation on the signal level of the input signal Sin input via the signal input terminal Tic and the signal level of the current detection signal Ss output from the comparator 313b to the delay time adjustment circuit 311b.

[0079] The delay time adjustment circuit 311b provided in the switching time adjustment unit 311 adjusts the delay time of the input signal Sin input from the outside (for example, a control device (not shown) that controls the semiconductor control circuit 31) according to the signal level of the current detection signal Ss input from the comparator 313b.

[0080] The AND gate 311a outputs a constant low-level calculation signal to the delay time adjustment circuit 311b when the signal level of the current detection signal Ss is low, and outputs an input signal Sin to the delay time adjustment circuit 311b when the signal level of the current detection signal Ss is high. The signal level of the current detection signal Ss output from the comparator 313b becomes high when the load current IL is large (when the target value of the load current IL is the normal current value as described in the first embodiment). Therefore, the input signal Sin is input to the delay time adjustment circuit 311b when the load current IL is large. On the other hand, when the load current IL is small (when the target value of the load current IL is the current value during low current as described in the first embodiment), a signal with a constant low-level signal level is input to the delay time adjustment circuit 311b. Therefore, the delay time adjustment circuit 311b outputs a delayed signal Sdy obtained by delaying the input signal Sin when the load current IL is large, and outputs a constant low-level calculation signal as is when the load current IL is small.

[0081] The drive current adjustment unit 312 has a gate drive circuit 312DC. When a delayed signal Sdy, which is obtained by delaying the input signal Sin, is input from the delay time adjustment circuit 311b, the gate drive circuit 312DC (an example of a drive circuit) drives the IGBT 221 with a drive current Idv having a current amount corresponding to the signal level of the current detection signal Ss. The gate drive circuit 312DC has a plurality of current supply units (a first current supply unit 312a and a second current supply unit 312b) that selectively supply the drive current Idv to the IGBT 221 according to the signal level of the current detection signal Ss.

[0082] 8 , the first current supply unit 312-1 provided in the gate drive circuit 312DC is selected at least when the current detection signal Ss has a signal level indicating that the detection voltage Vs is lower than the reference voltage Vr to supply the drive current Idv1 to the IGBT 221. In this embodiment, the input signal Sin is input to the first current supply unit 312-1, but the current detection signal Ss is not input. Therefore, the first current supply unit 312-1 starts supplying the drive current Idv1 to the IGBT 221 when the input signal Sin is input. Meanwhile, the first current supply unit 312-1 supplies the drive current Idv1 to the IGBT 221 not only when the current detection signal Ss has a signal level indicating that the detection voltage Vs is lower than the reference voltage Vr, but also when the current detection signal Ss has a signal level indicating that the detection voltage Vs is higher than the reference voltage Vr.

[0083] The second current supply unit 312-2 is selected when the current detection signal Ss has a signal level indicating that the detection voltage Vs is higher than the reference voltage Vr, and supplies the drive current Idv2 to the IGBT 221. More specifically, when the current detection signal Ss has a signal level indicating that the detection voltage Vs is higher than the reference voltage Vr, the IGBT 221 supplies a load current IL of a large target value (the load current during normal operation described in the first embodiment) to the load device. Therefore, the second current supply unit 312-2 outputs the drive current Idv2 to the gate of the IGBT 221 so that the IGBT 221 can supply the load current IL of a large target value to the load device.

[0084] When the input signal Sin is input, the first current supply unit 312-1 supplies a drive current Idv1 to the gate of the IGBT 221. When the delay signal Sdy is input, the second current supply unit 312-2 supplies a drive current Idv2 to the gate of the IGBT 221. A drive current Idv that is the sum of the drive currents Idv1 and Idv2 is supplied to the gate of the IGBT 221.

[0085] In this embodiment, for example, the second current supply unit 312-2 supplies the IGBT 221 with a drive current Idv2 having a larger current value than the first current supply unit 312-1. Therefore, the turn-on time of the IGBT 221 is shorter when the drive current Idv2 is supplied than when the drive current Idv1 is supplied. The first current supply unit 312-1 supplies the drive current Idv1 to the IGBT 221 based on the input of the input signal Sin. In contrast, the second current supply unit 312-2 supplies the drive current Idv2 to the IGBT 221 based on the input of the delay signal Sdy, the delay time of which has been adjusted by the delay time adjustment circuit 311b of the switching time adjustment unit 311. Therefore, the timing at which the IGBT 221 starts to turn on is later when the drive current Idv2 is supplied than when the drive current Idv1 is supplied. As a result, the switching time of the IGBT 221 is approximately the same when the drive current Idv1 is supplied as the drive current Idv to the gate of the IGBT 221 and when the drive current Idv, which is the sum of the drive currents Idv1 and Idv2, is supplied to the gate of the IGBT 221. This allows the semiconductor device 3 to suppress changes in the responsiveness of the IGBT 221 when the drive capability for driving the IGBT 221 is only the drive current Idv1 and when the drive currents Idv1 and Idv2 are combined.

[0086] 3-2. Operation of semiconductor device: The operation of the semiconductor device 3 according to this embodiment will be described with reference to Figures 4 and 8. Hereinafter, the operation of the semiconductor device 3 according to this embodiment will be described by taking as an example the time when the IGBT 221 is turned on.

[0087] When the IGBT 221 supplies a load current IL of a small target value (the load current at the time of low current described in the first embodiment) to a load device, the detection voltage Vs is lower than the reference voltage Vr. Therefore, when the input signal Sin is input to the semiconductor control circuit 31, the first current supply unit 312-1 supplies the drive current Idv1 to the gate of the IGBT 221, whereas the second current supply unit 312-2 does not supply the drive current Idv2 to the gate of the IGBT 221. As a result, as shown in the upper part of FIG. 4, the switching time of the IGBT 221 becomes the switching time ton0.

[0088] When the IGBT 221 supplies a load current IL having a large target value (the load current during normal operation described in the first embodiment) to a load device, the detection voltage Vs becomes higher than the reference voltage Vr. Therefore, when an input signal Sin is input to the semiconductor control circuit 31, a delay signal Sdy is output from the delay time adjustment circuit 311b to the second current supply unit 312-2. Therefore, the first current supply unit 312-1 supplies a drive current Idv1 to the gate of the IGBT 221, and the second current supply unit 312-2 supplies a drive current Idv2 to the gate of the IGBT 221. As a result, as shown in the lower part of FIG. 4, the turn-on time of the IGBT 221 is shortened, but the timing at which the load current IL (i.e., the collector current of the IGBT 221) starts to flow is delayed by the delay time Tdy of the delay signal Sdy relative to the input signal Sin, and the switching time of the IGBT 221 becomes switching time ton0.

[0089] In this way, the semiconductor device 3 can suppress a change in the responsiveness of the IGBT 221 due to the amount of the load current IL of the IGBT 221.

[0090] As described above, the semiconductor device 3 according to this embodiment includes the IGBT 221, a state detection unit 313 that detects the operating state of the IGBT 221, a switching time adjustment unit 311 that adjusts the switching time of the IGBT 221 in accordance with the operating state detected by the state detection unit 313, and a drive current adjustment unit 312 that adjusts the drive current Idv that drives the IGBT 221 in accordance with the operating state detected by the state detection unit 313.

[0091] With this configuration, the semiconductor device 3 can suppress changes in the responsiveness of the switching element even when the driving capability for driving the switching element is changed.

[0092] [Fourth embodiment] A semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. 9 to 11. FIGS. 9 and 10 are block diagrams showing an example of a schematic configuration of a semiconductor device 4 according to this embodiment. In FIG. 9, the specific configuration of the drive current adjustment unit 412 is not shown, and in FIG. 10, the specific configuration of the delay time adjustment circuit 411AC is not shown. In the semiconductor device 4 according to this embodiment, components that have the same actions and functions as the components of the semiconductor devices 1, 2, and 3 according to the first to third embodiments are given the same reference numerals, and their description will be omitted.

[0093] 4-1. Structure of semiconductor device: 9 and 10, the semiconductor device 4 according to the present embodiment includes a semiconductor control circuit 41 and a semiconductor element 22. The semiconductor control circuit 41 includes a switching time adjustment unit 411, a drive current adjustment unit 412, and a state detection unit 313. The state detection unit 313 includes a current detection unit 313ID. The state detection unit 313 and the current detection unit 313ID in the present embodiment have the same configurations as the state detection unit 313 and the current detection unit 313ID in the third embodiment. The voltage value of the reference voltage Vr in the present embodiment may be set to the same value as the voltage value of the reference voltage Vr in the third embodiment, or may be set to a different value.

[0094] The switching time adjustment unit 411 includes a NOT gate 211a, a transistor 211b, a delay time adjustment circuit 411AC, and a buffer circuit 211e. The delay time adjustment circuit 411AC includes a constant current source 411a and delay time change units 211d and 411b.

[0095] The delay time change unit 411b has a transistor 411b-1 and a capacitor C411b. The transistor 411b-1 is configured, for example, by an N-type MOSFET. The gate of the transistor 411b-1 is connected to the output terminal of a comparator 313b provided in the current detection unit 313ID. As a result, the on / off state of the transistor 411b-1 is controlled by the signal level of a current detection signal Ss input from the comparator 313b.

[0096] The delay time changer 411b is connected between the delay time changer 211d and the buffer circuit 211e. The capacitor C411b is arranged in parallel with the capacitor C211d downstream of the delay time changer 211d. When the transistor 411b-1 is in the off state, the capacitor C411b is disconnected from the wiring between the capacitor C211d and the buffer circuit 211e. On the other hand, when the transistor 411b-1 is in the on state, the capacitor C411b is connected in parallel with the capacitor C211d. As a result, when the transistor 411b-1 is in the on state, the capacitance of the capacitor formed between the wiring from the output terminal of the constant current source 411a to the buffer circuit 211e and the reference potential terminal (e.g., ground terminal) of the semiconductor control circuit 41 increases by the capacitance of the capacitor C411b.

[0097] The constant current source 411a operates with a power supply that drives the delay time adjustment circuit 411AC. The output terminal of the constant current source 411a is connected to the drain of the transistor 211b and the delay time changer 211d. Therefore, when the signal level of the input signal Sin is low, the output current Iout output by the constant current source 411a flows to the reference potential terminal (e.g., the ground terminal) of the semiconductor control circuit 41 and hardly flows to the delay time changer 211d. On the other hand, when the signal level of the input signal Sin is high, the output current Iout output by the constant current source 411a hardly flows to the reference potential terminal of the semiconductor control circuit 41 and flows to the delay time changer 211d.

[0098] In the semiconductor device 4, unlike the semiconductor device 2 according to the second embodiment, the amount of output current Iout output from the constant current source 411a is constant. Therefore, the rise time of the delay signal Sdy is delayed by the capacitance of the capacitor C411b when the transistor 411b-1 is on compared to when it is off. The on / off state of the transistor 411b-1 is controlled by the current detection signal Ss. In other words, the on / off state of the transistor 411b-1 is controlled according to fluctuations in the detection current Is. When the transistor 411b-1 is off, the capacitor C211d is charged with the output current Iout output from the constant current source 411a. On the other hand, when the transistor 411b-1 is on, the capacitors C211d and C411b are charged with the output current Iout output from the constant current source 411a. Therefore, the delay signal Sdy rises more slowly when the transistor 411b-1 is on compared to when it is off, resulting in a longer delay time.

[0099] In this way, the delay time adjustment circuit 411AC controls the transistor 411b-1 from an off state to an on state or vice versa in accordance with fluctuations in the detection current Is, thereby changing the delay time of the delay signal Sdy in a stepwise manner. Therefore, the switching time adjustment unit 411 adjusts the switching time of the IGBT 221 in a stepwise manner in accordance with fluctuations in the detection current Is.

[0100] The on / off state is controlled according to the amount of load current IL supplied to a load device (not shown) by the IGBT 221. Therefore, the delay time changing unit 411b can selectively output a delay signal Sdy obtained by delaying the input signal Sin by different delay times according to the amount of load current IL.

[0101] In this way, the delay time adjustment circuit 411AC adjusts the delay time of the input signal Sin input from the outside (for example, a control device (not shown) that controls the semiconductor control circuit 41) according to the signal level of the current detection signal Ss input from the comparator 313b.

[0102] 10, the drive current adjustment unit 412 has a gate drive circuit 412DC. The gate drive circuit 412DC has a constant current source 412CC, a current mirror circuit 412CM, a first current supply unit 412-1, and a second current supply unit 412-2. In this way, the gate drive circuit 412DC has a plurality of current supply units, and the plurality of current supply units have the first current supply unit 412-1 and the second current supply unit 412-2.

[0103] The constant current source 412CC includes an operational amplifier 212a, a transistor 212b, a transistor 212c, a resistor 212d, and a DC voltage generator 412a. Thus, unlike the variable constant current source 212VC in the second embodiment, the constant current source 412CC includes a DC voltage generator 412a. The DC voltage generator 412a is configured, for example, as a DC voltage source, and its positive terminal is connected to the non-inverting input terminal (+) of the operational amplifier 212a. Therefore, the operational amplifier 212a outputs an output voltage having substantially the same voltage value as the voltage generated by the DC voltage generator 412a to the gate of the transistor 212c. This allows the constant current source 412CC to pass a constant current corresponding to the voltage value of the output voltage of the operational amplifier 212a through the transistor 212e of the current mirror circuit 412CM.

[0104] The current mirror circuit 412CM has a transistor 212e, a transistor 212f, and a transistor 412b. In the semiconductor device 4, the transistors 212f and 412b have different transistor sizes so that the transistor 412b can pass a larger amount of current than the transistor 212f. The transistor 212f is also a transistor that constitutes the first current supply unit 412-1, and the transistor 412b is also a transistor that constitutes the second current supply unit 412-2.

[0105] The first current supply unit 412-1 has a transistor 212f and a transistor 212g. The transistors 212f and 212g in this embodiment operate in the same manner as the transistors 212f and 212g in the second embodiment. Therefore, when a delay signal Sdy having a high signal level is input from the switching time adjustment unit 411 to the transistor 212g, the first current supply unit 412-1 supplies the drive current Idv1 to the gate of the IGBT 221. On the other hand, when a delay signal Sdy having a low signal level is input from the switching time adjustment unit 411 to the transistor 212g, the first current supply unit 412-1 flows the drive current Idv1 to a reference potential terminal (e.g., a ground terminal) of the semiconductor control circuit 41 without supplying it to the gate of the IGBT 221.

[0106] Whether or not the first current supply unit 412-1 supplies the drive current Idv1 to the gate of the IGBT 221 is controlled by the signal level of the delay signal Sdy (i.e., the signal level of the input signal Sin), and is not controlled by the signal level of the current detection signal Ss. The first current supply unit 412-1 is selected at least when the current detection signal Ss has a signal level indicating that the detection voltage Vs is lower than the reference voltage Vr, and supplies the drive current Idv1 to the IGBT 221. The first current supply unit 412-1 also supplies the drive current Idv1 to the IGBT 221 when the current detection signal Ss has a signal level indicating that the detection voltage Vs is higher than the reference voltage Vr. A low signal level of the current detection signal Ss indicates that the detection voltage Vs is lower than the reference voltage Vr, and a high signal level indicates that the detection voltage Vs is higher than the reference voltage Vr.

[0107] The second current supply unit 412-2 has a transistor 412b and a transistor 412c. The transistor 412b is configured, for example, by a P-type MOSFET, and the transistor 412c is configured, for example, by an N-type MOSFET. The transistors 412b and 412c are connected in series between a power supply terminal to which power for driving the gate drive circuit 412DC is supplied and a current output terminal Toc provided in the semiconductor control circuit 41. The source of the transistor 412c is connected to the current output terminal Toc and the connection point of the transistors 212f and 212g (i.e., the output terminal of the drive current Idv1). The gate of the transistor 412c is connected to the output terminal of the comparator 313b.

[0108] Therefore, when a current detection signal Ss having a high signal level is input to the transistor 412c from the current detection unit 313ID, the second current supply unit 412-2 supplies the drive current Idv2 to the gate of the IGBT 221. On the other hand, when a current detection signal Ss having a low signal level is input to the transistor 412c from the current detection unit 313ID, the second current supply unit 412-2 does not supply the drive current Idv2 to the gate of the IGBT 221, but instead passes the drive current Idv2 to a reference potential terminal (for example, a ground terminal) of the semiconductor control circuit 41.

[0109] In this way, the on / off state of the second current supply unit 412-2 is controlled by the signal level of the current detection signal Ss. Therefore, the second current supply unit 412-2 is selected to supply the drive current Idv2 to the IGBT 221 when the current detection signal Ss has a signal level indicating that the detection voltage Vs is higher than the reference voltage Vr.

[0110] The first current supply unit 412-1 supplies the drive current Idv1 to the IGBT 221 regardless of the level of the reference voltage Vr and the detection voltage Vs, whereas the second current supply unit 412-2 supplies the drive current Idv2 to the IGBT 221 only when the detection voltage Vs is higher than the reference voltage Vr. That is, the gate drive circuit 412DC selects only the first current supply unit 412-1 when the detection voltage Vs is lower than the reference voltage Vr (when the signal level of the current detection signal Ss is low). On the other hand, the gate drive circuit 412DC selects both the first current supply unit 412-1 and the second current supply unit 412-2 when the detection voltage Vs is higher than the reference voltage Vr (when the signal level of the current detection signal Ss is high). The gate drive circuit 412DC supplies the combined current of the drive current Idv1 and the drive current Idv2 to the gate of the IGBT 221 as the drive current Idv. For this reason, the gate drive circuit 412DC has a plurality of current supply units (i.e., a first current supply unit 412-1 and a second current supply unit 412-2) that selectively supply the drive current Idv to the IGBT 221 in accordance with the signal level of the current detection signal Ss.

[0111] The drive current adjusting unit 412 supplies the drive current Idv to the gate of the IGBT 221 using only the first current supply unit 412-1, or supplies the drive current Idv to the gate of the IGBT 221 using both the first current supply unit 412-1 and the second current supply unit 412-2, depending on the fluctuations in the reference voltage Vr and the detection voltage Vs, i.e., the fluctuations in the detection current Is. Therefore, the drive current adjusting unit 412 adjusts the drive current Idv in stages depending on the fluctuations in the detection current.

[0112] In the present embodiment, for example, the second current supply unit 412-2 supplies a driving current Idv2 having a larger current value than the first current supply unit 412-1 to the IGBT 221. Therefore, the turn-on time of the IGBT 221 is shorter when the driving current Idv2 is supplied to the IGBT 221 than when the driving current Idv1 is supplied to the IGBT 221.

[0113] As described above, the drive current adjustment unit 412 has a gate drive circuit 412DC that drives the IGBT 221 with a drive current Idv of a current amount corresponding to the signal level of the current detection signal Ss when the delay signal Sdy, which is obtained by delaying the input signal Sin, is input from the delay time adjustment circuit 411AC. The delay signal Sdy has a longer delay time relative to the input signal Sin when the signal level of the current detection signal Ss is high than when it is low. Therefore, the delay time of the delay signal Sdy input to the gate drive circuit 412DC is longer when the drive current Idv is supplied to the IGBT 221 by the first current supply unit 412-1 and the second current supply unit 412-2 than when the drive current Idv is supplied to the IGBT 221 by only the first current supply unit 412-1.

[0114] As a result, the switching time of the IGBT 221 is approximately the same when the drive current Idv1 is supplied to the gate of the IGBT 221 as the drive current Idv and when the drive current Idv, which is the sum of the drive currents Idv1 and Idv2, is supplied to the gate of the IGBT 221. Therefore, the semiconductor device 4 can suppress a change in the responsiveness of the IGBT 221 when the drive capability for driving the IGBT 221 is only the drive current Idv1 and when the drive currents Idv1 and Idv2 are combined.

[0115] 4-2. Operation of semiconductor device: The operation of the semiconductor device 4 according to this embodiment will be described using FIG. 11 with reference to FIGS. 9 and 10. FIG. 11 is a timing chart schematically showing a portion of the operating waveform of the semiconductor device 4. "Sdy" in FIG. 11 indicates the delay signal output from the delay time adjustment circuit 411AC. "Sin" in FIG. 11 indicates the input signal input to the switching time adjustment unit 411. "IL" in FIG. 11 indicates the load current supplied by the IGBT 221 to the load device.

[0116] When the IGBT 221 supplies a load current IL of a small target value (the load current at the time of low current described in the first embodiment) to a load device, the detection voltage Vs is lower than the reference voltage Vr. Therefore, when a delayed signal Sdy, which is delayed by a delay time Tdy1 with respect to the input signal Sin, is input to the drive current adjustment unit 412, the first current supply unit 412-1 supplies the drive current Idv1 to the gate of the IGBT 221, while the second current supply unit 412-2 does not supply the drive current Idv2 to the gate of the IGBT 221. As a result, as shown in the upper part of FIG. 11, the switching time of the IGBT 221 becomes the switching time ton0.

[0117] When the IGBT 221 supplies a load current IL (the normal load current described in the first embodiment) with a large target value to the load device, the detection voltage Vs becomes higher than the reference voltage Vr. Therefore, when a delayed signal Sdy, which is delayed by a delay time Tdy2 longer than that during low current with respect to the input signal Sin, is input to the drive current adjustment unit 412, the first current supply unit 412-1 starts supplying the drive current Idv1 to the IGBT 221 at a later timing than during low current. Furthermore, when the detection voltage Vs becomes higher than the reference voltage Vr, the transistor 412c is turned on, and the second current supply unit 412-2 also starts supplying the drive current Idv2. Therefore, the turn-on time of the IGBT 221 is shorter than during low current. As a result, as shown in the lower part of FIG. 11, the switching time of the IGBT 221 is the switching time ton0, similar to during low current.

[0118] In this way, the semiconductor device 4 can suppress a change in the responsiveness of the IGBT 221 due to the amount of the load current IL of the IGBT 221.

[0119] As described above, the semiconductor device 4 according to this embodiment includes the IGBT 221, a state detection unit 313 that detects the operating state of the IGBT 221, a switching time adjustment unit 411 that adjusts the switching time of the IGBT 221 in accordance with the operating state detected by the state detection unit 313, and a drive current adjustment unit 412 that adjusts the drive current Idv that drives the IGBT 221 in accordance with the operating state detected by the state detection unit 313.

[0120] With this configuration, the semiconductor device 4 can suppress changes in the responsiveness of the switching element even when the driving capability for driving the switching element is changed.

[0121] The present invention is not limited to the above-described embodiment, and various modifications are possible. Although the semiconductor devices 1, 2, 3, and 4 according to the first to fourth embodiments have been described using an example in which an IGBT is turned on, the present invention is not limited to this. The semiconductor devices 1, 2, 3, and 4 can also achieve the same effect when the IGBT is turned off.

[0122] The semiconductor devices 3 and 4 according to the third and fourth embodiments can change the drive current Idv supplied to the gate of the IGBT 221 in two stages, but by providing a predetermined number of current detection units and current supply units, it can be changed in three or more stages.

[0123] In the semiconductor devices 3 and 4 according to the third and fourth embodiments, the first current supply unit 312-1 and 412-1 are configured to supply the drive current Idv1 to the gate of the IGBT 221 even during normal operation, but the present invention is not limited to this. The first current supply unit 312-1 and 412-1 may be configured not to supply a current to the gate of the IGBT 221 during normal operation. In this case, the second current supply unit 312-2 and 412-2 need to be configured to supply the drive current Idv2, which has a larger current amount than the first current supply unit 312-1 and 412-1, to the gate of the IGBT 221.

[0124] The technical scope of the present invention is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to the object of the present invention. Furthermore, the technical scope of the present invention is not limited to the combination of inventive features defined by the claims, but can be defined by any desired combination of specific features from among all the respective disclosed features. [Explanation of symbols]

[0125] 1,2,3,4 Semiconductor devices 11, 21, 31, 41 Semiconductor control circuit 12,22 Semiconductor elements 111,211,311,411 Switching time adjustment section 112,212,312,412 Drive current adjustment section 113,213,313,413 Status detection unit 121,221 IGBT 122 Status detection element 211AC, 311b, 411AC delay time adjustment circuit 211c, 212VC variable constant current source 211d, 411b Delay time change section 211e, 213b Buffer circuit 212CM, 412CM current mirror circuit 212DC, 312DC, 412DC gate drive circuit 213a, 313a Current-voltage conversion circuit 213ID, 313ID Current detection section 222 Current sensing element 311a AND Gate 312-1,312a,412-1 First current supply section 312-2, 312b, 412-2 Second current supply section 313b Comparator 313c Reference voltage generation circuit Idv, Idv1, Idv2 drive current IL load current Is detection current Sin input signal SOS detection signal Sosd status detection signal Ss Current detection signal Vr Reference voltage Vs detection voltage

Claims

1. A switching element; a state detection unit that detects an operating state of the switching element; a switching time adjusting unit that adjusts the switching time of the switching element in accordance with the operating state detected by the state detecting unit; a drive current adjusting unit that adjusts a drive current for driving the switching element in accordance with the operating state detected by the state detecting unit; A semiconductor device comprising:

2. a current detection element for detecting a load current supplied by the switching element to a load; the state detection unit includes a current detection unit that detects, as the operating state, a magnitude of the load current corresponding to the detected current detected by the current detection element; the switching time adjustment unit adjusts the switching time of the switching element in accordance with the magnitude of the load current detected by the current detection unit as the operating state; The drive current adjusting unit adjusts the drive current for driving the switching element in accordance with the magnitude of the load current detected by the current detecting unit as the operating state. The semiconductor device according to claim 1 .

3. the switching time adjusting unit continuously adjusts the switching time in accordance with fluctuations in the detected current; The drive current adjusting unit continuously adjusts the drive current according to fluctuations in the detected current. The semiconductor device according to claim 2 .

4. The current detection unit a conversion circuit for converting the sensed current into a sensed voltage; a buffer circuit that outputs the detection voltage output from the conversion circuit as a current detection signal having a signal level corresponding to the magnitude of the load current; and the switching time adjustment unit has a delay time adjustment circuit that adjusts a delay time of an input signal input from outside in accordance with a signal level of the current detection signal input from the current detection unit, The drive current adjustment unit has a drive circuit that drives the switching element with the drive current of a current amount corresponding to the signal level of the current detection signal when a delay signal obtained by delaying the input signal is input from the delay time adjustment circuit.

4. The semiconductor device according to claim 2 or 3.

5. the switching time adjustment unit adjusts the switching time in stages according to fluctuations in the detected current; The drive current adjusting unit adjusts the drive current stepwise in accordance with fluctuations in the detected current. The semiconductor device according to claim 2 .

6. The current detection unit a conversion circuit for converting the sensed current into a sensed voltage; a comparator that compares the detected voltage output from the conversion circuit with a reference voltage and outputs a current detection signal having a signal level based on the comparison result; and the switching time adjustment unit includes a delay time adjustment circuit that adjusts a delay time of an input signal input from an external device in accordance with a signal level of the current detection signal input from the comparator, The drive current adjustment unit has a drive circuit that drives the switching element with the drive current of a current amount corresponding to the signal level of the current detection signal when a delay signal obtained by delaying the input signal is input from the delay time adjustment circuit. The semiconductor device according to claim 2 or 5.

7. The drive circuit has a plurality of current supply units that selectively supply the drive current to the switching element in accordance with the signal level of the current detection signal. The semiconductor device according to claim 6.

8. The plurality of current supply units include: a first current supply unit that is selected at least when the current detection signal has a signal level indicating that the detection voltage is lower than the reference voltage and that supplies the drive current to the switching element; a second current supply unit that is selected when the current detection signal has a signal level indicating that the detection voltage is higher than the reference voltage and that supplies the driving current to the switching element; have The semiconductor device according to claim 7 .

9. The first current supply unit supplies the drive current to the switching element even when the current detection signal has a signal level indicating that the detection voltage is higher than the reference voltage. The semiconductor device according to claim 8 .

10. The second current supply unit supplies the driving current to the switching element with a current value larger than that of the first current supply unit. The semiconductor device according to claim 9 .

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