Method for manufacturing a semiconductor device package having insulation - Patents.com

Abstract

A method includes placing a semiconductor device package having a first portion of leads of a package substrate extending from a mold compound and a second portion of leads insulated from the first portion extending from the mold compound, on a test handler; contacting the first portion with first and second conductive slugs (713); contacting the second portion with third and fourth conductive slugs (715); contacting a first surface of the mold compound with a first plunger having a conductive plate and an insulated tip (717); contacting an opposing second surface of the mold compound with a second plunger having a conductive plate and an insulated tip (719); applying a high voltage to the first conductive slug (721); applying approximately half of the high voltage to the conductive plate of the first plunger (721); and applying a ground voltage to the third conductive slug (721).

Description

[Technical field]

[0001] This application relates generally to manufacturing semiconductor devices, and more particularly to manufacturing semiconductor device packages with integrated insulation for the semiconductor die, including testing of the completed semiconductor device packages. [Background technology]

[0002] For integrated devices with internal isolation in a semiconductor device package, the semiconductor die is separated from the high voltage signal by an isolation barrier. For example, a semiconductor die with an integrated Hall element configured as a current sensor may be mounted to a package substrate, such as a lead frame, by a dielectric material. A high voltage input signal, with a maximum voltage of several hundred volts, one kilovolt, or several kilovolts, may be coupled to the lead frame. The semiconductor die remains electrically isolated from the high voltage while a Hall current sensor in the semiconductor die outputs a signal that varies in response to a magnetic field caused by a current flowing through a portion of the lead frame. The package substrate may include additional leads that are also isolated from the high voltage. The additional leads may be coupled to the semiconductor die to provide power, control, and output signals for the semiconductor die. Other types of semiconductor devices that require electrical isolation may also be mounted in a semiconductor device package. For example, a pair of semiconductor dies may form a transformer with an inductor having coils spaced apart by an insulating dielectric layer, and this arrangement may allow power to be transferred through isolated components without direct connections between components of different voltages.

[0003] When manufacturing a semiconductor device package with isolation, testing is performed to ensure that the isolation is robust enough for the application. The completed semiconductor device package may be placed into a test handler capable of handling high voltages. One portion of the test handler supplies a high voltage to package leads that are positioned to receive the high voltage. Another portion of the test handler is coupled to the package leads that are insulated from the high voltage, and a measurement is taken to determine if the high voltage is isolated from the insulated leads. The measurement includes applying the high voltage to the packaged device and determining if the isolation is effective.

[0004] High voltages input to a semiconductor device package can generate high electric fields. Dielectric materials such as die attach and mold compounds can fail in high electric fields, resulting in defects, arcing, and short circuits. Arcs and short circuits in the test handler can cause current from the electric field arcing in the air to flow around the device under test, and can result in inaccurate test results indicating insulation failure if the arcing current shows up as a current flow in the test handler. To provide a robust semiconductor device package that can handle being coupled to high voltages in the kilovolt range, the semiconductor device package must be designed to accommodate high voltages at the input and withstand the resulting electric fields without damage to the semiconductor device package or semiconductor die. During high voltage insulation testing, the electric fields that are generated in the test handler when high voltages are applied must be managed to prevent inaccurate test results due to excessive electric field concentrations in the tester and damage from arcing currents to otherwise good semiconductor devices and packages. Summary of the Invention

[0005] In one described example, a method for testing insulation in a semiconductor device package includes placing a semiconductor device package in a test handler, the semiconductor device package having a first lead on a first portion of a package substrate extending from a mold compound forming a package body of the semiconductor device package and a second lead on a second portion of the package substrate extending from the mold compound, the first portion being electrically isolated from the second portion; contacting the first lead of the first portion with a first conductive slug and a second conductive slug of the test handler; and contacting the second lead of the second portion with a third conductive slug and a fourth conductive slug of the test handler, the third conductive slug and the fourth conductive slug being electrically isolated from the first conductive slug. contacting a first surface of the mold compound with a first plunger having a conductive plate and an insulating tip, the insulating tip contacting the first surface of the mold compound; contacting a second surface of the mold compound opposite the first surface of the mold compound with a second plunger, the second plunger having a conductive plate and an insulating tip, the insulating tip contacting the second surface of the mold compound; and applying a high voltage to the first conductive slug and the second conductive slug while applying approximately half of the high voltage to the conductive plate of the first plunger and the conductive plate of the second plunger and applying a ground voltage to the third conductive slug and the fourth conductive slug.

[0006] In another illustrated example, another method includes forming semiconductor dies on a semiconductor wafer; forming a package substrate including a first portion and a second portion spaced apart and electrically insulated from the first portion, the package substrate including a conductive lead frame, the first portion having a device side surface and an opposing surface; mounting a first surface of a spacer dielectric having a first surface and a second surface opposite the first surface to the device side surface of the first portion of the package substrate, the spacer dielectric being partially covered by the first portion and extending beyond the first portion; mounting one of the semiconductor dies to the second surface of the spacer dielectric, the one of the semiconductor dies having bond pads formed on a surface of the semiconductor die that is partially covered by the spacer dielectric and extending beyond the spacer dielectric; bonding the bond pads of the semiconductor die by making electrical connections from the bond pads to leads formed by the second portion of the lead frame; and mounting the semiconductor die, the electrical connections, the spacer dielectric, and the leads in a molding compound. forming a semiconductor device package by partially covering a first portion of the frame and partially covering a second portion of the lead frame; shaping a first lead of the first portion extending from the molding compound and shaping a second lead of the second portion extending from the molding compound; contacting a first conductive slug and a second conductive slug of the test handler with the first lead of the first portion; contacting a third conductive slug and a fourth conductive slug of the test handler with the second lead of the second portion; and contacting a conductive plate and an insulating tip. contacting a first plunger having a conductive plate and an insulating tip with a first surface of the mold compound of the semiconductor device package, the first plunger being located between the first slug and a third slug of the test handler; and contacting a second plunger having a conductive plate and an insulating tip with a second surface of the mold compound of the semiconductor device package opposite the first surface of the mold compound, the second plunger being located opposite the first plunger and between the second slug and a fourth slug of the test handler.applying a high voltage to the first lead of the first portion, a voltage approximately half the high voltage to the conductive plate of the first plunger and the conductive plate of the second plunger, and a ground voltage to the second lead of the second portion.

[0007] In a further described example, a test handler for performing a high voltage insulation test on a semiconductor device package includes a first conductive slug and a second conductive slug configured to contact a first lead of a first portion of a package substrate of the semiconductor device package, the first conductive slug and the second conductive slug configured to be coupled to a high voltage, a third conductive slug and a fourth conductive slug configured to contact a second lead of a second portion of the package substrate of the semiconductor device package, the third conductive slug and the fourth conductive slug configured to be coupled to a ground voltage, and a semiconductor device package. a first plunger configured to contact a first surface of a mold compound forming a body of the device package, the first plunger including a conductive plate and an insulating tip disposed in contact with the first surface of the mold compound, the conductive plate configured to be coupled to a voltage that is approximately half of the high voltage; and a second plunger configured to contact a second surface of the mold compound opposite the first surface of the mold compound, the second plunger including a conductive plate and an insulating tip disposed in contact with the second surface of the mold compound, the conductive plate configured to be coupled to a voltage that is approximately half of the high voltage. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 illustrates a circuit block diagram of a Hall current sensing device with isolation for use in an arrangement.

[0009] [Figure 2A]1 illustrates a semiconductor device package in a perspective view for a Hall current sensor, including a semiconductor die in the semiconductor device package; [Figure 2B] 1 illustrates a semiconductor device package, including a semiconductor die in the semiconductor device package, for a Hall current sensor, in a partial isometric view. [Figure 2C] 1 illustrates a semiconductor device package in plan view for a Hall current sensor, including a semiconductor die in the semiconductor device package. [Figure 2D] 1 is a cross section of a semiconductor device package.

[0010] [Figure 3A] A semiconductor wafer having rows and columns of semiconductor dies is illustrated in perspective view. [Figure 3B] 2 illustrates, in enlarged view, an individual semiconductor die that may be used with the arrangement of FIG.

[0011] [Figure 4A] 1 illustrates, in cross-sectional view, selected steps in forming a semiconductor device package that may be used in one arrangement; [Figure 4B] 1 illustrates, in cross-sectional view, selected steps in forming a semiconductor device package that may be used in one arrangement; [Figure 4C] 1 illustrates, in cross-sectional view, selected steps in forming a semiconductor device package that may be used in one arrangement; [Figure 4D] 1 illustrates, in cross-sectional view, selected steps in forming a semiconductor device package that may be used in one arrangement; [Figure 4E] 1 illustrates, in cross-sectional view, selected steps in forming a semiconductor device package that may be used in one arrangement; [Figure 4F] 1 illustrates, in cross-sectional view, selected steps in forming a semiconductor device package that may be used in one arrangement; [Figure 4G] A completed semiconductor device package formed by the steps of FIGS. 4A-4F is illustrated in perspective view.

[0012] [Figure 5A] 1 illustrates, in perspective view, a layout for a test handler to perform high voltage insulation tests on semiconductor device packages having insulation. [Figure 5B] 1 illustrates, in perspective view, a layout for a test handler to perform high voltage insulation tests on semiconductor device packages having insulation. [Figure 5C] 1 illustrates, in perspective view, a layout for a test handler to perform high voltage insulation tests on semiconductor device packages having insulation. [Figure 5D] FIG. 2 illustrates a circuit diagram for applying voltages to the arrangement of FIG. 1; [Figure 5E] Additional details of certain arrangements are illustrated in cross-section.

[0013] [Figure 6A] 13 shows a graph of stress volume results for a simulation illustrating high voltage tests performed without the arrangement of FIG. 1 and comparing the results obtained for stress volume for tests performed with different arrangements. [Figure 6B] The stress volume results of a simulation illustrating high voltage tests performed without the arrangement of FIG. 1 are plotted with a corresponding table of values ​​obtained at certain points on the graph to compare the results obtained for the stress volume for tests performed with the different arrangements.

[0014] [Figure 7A] 1 illustrates the steps of a method arrangement in a flow chart. [Figure 7B] 1 illustrates the steps of a method arrangement in a flow chart. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Corresponding numbers and symbols in the different figures generally refer to corresponding parts unless otherwise noted. The figures are not necessarily drawn to scale.

[0016] In this specification, elements are described as being "coupled." As used in this specification, the term "coupled" includes not only elements that are directly connected, but also elements that are electrically connected through intervening elements or wires.

[0017] In this specification, the term "semiconductor die" is used. As used herein, a semiconductor die can be an integrated circuit with individual semiconductor devices such as bipolar transistors, several individual devices such as a pair of power FET switches fabricated together on a single semiconductor die, or multiple semiconductor devices such as multiple capacitors in an A / D converter. A semiconductor die can include passive devices such as resistors, inductors, filters, and active devices such as transistors. A semiconductor die can be an integrated circuit with hundreds or thousands of transistors that are combined to form a functional circuit such as a microprocessor or memory device. Semiconductor dies for power applications useful in these configurations include intelligent power devices that include individual power transistors, gate drivers to operate these power transistors, passive components such as capacitors, inductors, and resistors required to implement the power circuit elements, and protection sensors such as inrush current sensors that add reliability and control to the system. In some applications, these devices can be individual semiconductor dies that can be fabricated with different semiconductor materials and mounted in a single device package. In an exemplary configuration, the semiconductor die includes a Hall element configured as a current sensor.

[0018] The term "semiconductor device package" is used herein. The semiconductor device package has at least one semiconductor die electronically coupled to the terminals and a package body that protects and covers the semiconductor die. In some arrangements, multiple semiconductor dies may be packaged together. For example, a power metal oxide semiconductor (MOS) field effect transistor (FET) semiconductor die and a second semiconductor die (such as a gate driver die or a controller device die) may be packaged together to form a single packaged electronic device. Additional components, such as passive components, may be included in the packaged electronic device. The semiconductor die is mounted to a package substrate that provides conductive leads, some of which form terminals for the packaged electronic device. The semiconductor die may be mounted to the package substrate such that a front surface of the active device faces toward the package substrate and a back surface of the active device faces away from the package substrate. The semiconductor device package may have a package body that is formed by a thermosetting epoxy resin in a molding process or by using an epoxy, plastic, or resin that is liquid at room temperature and subsequently hardened. The package body may provide a hermetic package for the packaged electronic device. The package body may be formed in a mold using an encapsulation process, but some of the leads of the substrate are not covered during encapsulation, and these exposed lead portions provide exposed terminals for the semiconductor device package.

[0019] The term "package substrate" is used herein. The package substrate is a substrate that is arranged to receive and support a semiconductor die in a completed semiconductor device package. The package substrate includes a conductive lead frame that may be formed from copper, aluminum, stainless steel, steel, and alloys such as alloy 42. The lead frame may include die pads for mounting the semiconductor die and conductive leads spaced apart from the die pads for electrical connection using wire bonds, ribbon bonds, or other conductors to bond pads on the semiconductor die. The lead frame may be provided in a strip or array. The die may be arranged on the strip or array, the die may be placed on the die pads for each packaged device, and the die may be mounted to the die pads of the lead frame using die attach or die adhesive. The bond pads on the semiconductor die may be bonded to the leads of the lead frame by wire bonding. After the wire bonds are in place, a portion of the substrate, the die, and at least a portion of the die pads may be covered with a protective material such as a mold compound. The completed devices may then be detached from one another by cutting the molding compound and packaging substrate between the mounted semiconductor dies.

[0020] Leadframes may include plated, stamped, and partially etched leadframes. In partially etched leadframes, two levels of metal are formed from a sheet of material by etching a pattern from one side of the metal leadframe and then the other to form full thickness and partial thickness sections, and in some areas, all of the metal may be etched away to form openings in the partially etched leadframe. Repeated plating and patterning may form multiple layers of conductors separated by dielectrics and conductive vias connecting the conductor layers through the dielectrics, which may be mold compound. Package substrates may also be tape and film-based substrates carrying conductors, ceramic substrates, laminate substrates with multiple layers of conductors and insulator layers, ceramic, fiberglass, or resin printed circuit boards, and glass-reinforced epoxy substrates such as flame retardant 4 (FR4).

[0021] Leaded packages may be used with configurations in which the leads extend away from the package body and are shaped to form portions for soldering to a substrate. Dual in-line packages, or "DIPs," may be used with such configurations. Thin DIP packages with surface mount lead configurations that meet certain size specifications are sometimes referred to as small outline integrated circuit or "SOIC" packages.

[0022] The term "spacer dielectric" is used herein. The spacer dielectric is in an insulating layer that provides electrical insulation between devices mounted thereon. Spacer dielectrics used in the above arrangement include printed circuit board materials such as flame retardant 4 (FR4), glass reinforced epoxy or fiber substrates, bismaleimide triazine (BT) resins, ceramics, other epoxies, resins, tapes, and films. The spacer dielectric may be a stack of layered dielectric materials.

[0023] In this specification, the term "test handler" is used. In the above arrangement, the test handler is a tester that can receive a semiconductor device package, transport the semiconductor device package to a test area, perform a high voltage test, and transport the semiconductor device package out of the tester. The above arrangement constitutes the elements of a test handler for managing electric field concentrations around a semiconductor device package during high voltage testing.

[0024] In the above arrangement, the semiconductor device package includes a package substrate having a first portion spaced apart and electrically isolated from a second portion. The package substrate may be a conductive leadframe. The first portion of the conductive leadframe includes a first lead (or a first group of leads) coupled to a first node and a second lead (or a second group of leads) coupled to a second node. The first portion includes a conductive path for carrying a current between the first node and the second node. A spacer dielectric is mounted on a device side surface of the first portion of the leadframe, the first portion having an opposing surface opposite the device side surface. A semiconductor die including a current sensor is mounted on the spacer dielectric such that the semiconductor die is electrically isolated from the first portion of the leadframe. The semiconductor die is positioned to be located within a magnetic field generated by a current flowing through the current carrying portion of the first portion of the leadframe. In one example, the semiconductor die includes a Hall element configured as the current sensor. An electrical connection is made between a bond pad on the semiconductor die and a third lead on the second portion of the leadframe. A mold compound covers the first and second portions of the leadframe, the spacer dielectric, and at least a portion of the semiconductor die, and the first, second, and third leads include portions exposed from the mold compound to form package terminals. The first portion of the leadframe including the terminals formed from the conductive leads outside the mold compound within the semiconductor device package is electrically insulated from the semiconductor die and the second portion of the leadframe including the terminals formed from the conductive leads.

[0025] In the test handler, a high voltage, e.g., a voltage in the hundreds of volts or kilovolt range, is applied to a first portion of the lead frame while a second portion of the lead frame is held at a reference potential. To test the insulation of the semiconductor device package, when the high voltage is applied to the first portion of the lead frame, current measurements are taken to verify that the current flowing between the first and second portions of the lead frame is less than a predetermined amount, thereby confirming electrical insulation.

[0026] In the above arrangement, a structure is formed to reduce electric field concentrations that occur when a high voltage, for example, greater than several hundred volts, is coupled to the first portion of the lead frame in the test handler. In an exemplary test, a high voltage of greater than 300 volts, or even higher voltages such as 1 kV or up to several kilovolts, is coupled to the first portion of the lead frame by using a conductive slug. A pair of plungers, which are positioned to contact the mold compound that forms the body of the semiconductor device package, are positioned on either side of the semiconductor device package, and the plungers contact and hold the semiconductor device package. In one arrangement, the plungers include a conductive plate or blade with an insulating tip that contacts the mold compound of the semiconductor device package, for example, the plungers can be a copper plate or blade with a polymeric tip. During high voltage testing, a pair of conductive slugs, which are positioned to contact either side of the terminals formed by the leads of the first portion of the lead frame, are placed at a high voltage. The conductive blade of the plunger is placed at a voltage equivalent to approximately half the high voltage while another pair of slugs contact terminals of the semiconductor device package formed by leads of a second portion of the lead frame that are at a ground or reference potential lower than the high voltage. By subjecting the conductive portion of the plunger to a voltage equal to or approximately equal to half the high voltage applied across the terminals of the semiconductor device package, the electric field within the test handler is managed and electric field concentrations around and within the semiconductor device package are distributed to reduce or prevent high electric field concentrations and prevent arcing due to dielectric breakdown in the air surrounding the semiconductor device package when high voltage testing is performed. Arcing can carry currents that can cause erroneous test results and can damage the semiconductor device package.

[0027] FIG. 1 is a circuit block diagram of a semiconductor device package 100, which is an example semiconductor device package that can be used in an arrangement. The example semiconductor device package 100 is a Hall current sensor. Other circuits can be used in the above arrangement, such as for devices that use transformers with isolation. In addition to current sensing with high voltage signals, additional response examples of isolation in a semiconductor device package include power transfer across voltage regimes at separate ground potentials, and communication, such as in isolated signaling between transceiver devices operating at different voltage potentials. Power supply circuitry including alternating current (AC) isolation, DC-DC converters, and load protection circuitry can be used with the above arrangement. The above arrangement provides high voltage testing to verify isolation in a semiconductor device package and can be used with many devices that include electrical isolation.

[0028] 1, an input IN+ may be coupled to a first node to receive a signal carrying a current labeled "I", for example, the IN+ node may be coupled to a high voltage signal or voltage source, and an output IN- may be coupled to a second node, the output IN- outputs a current I. A semiconductor die 103 in a semiconductor device package 100 includes a Hall element 101. Circuitry required to control and monitor the Hall element 101 is provided, including a Hall element bias circuit 107, a temperature compensation and offset cancellation circuit 113, a precision amplifier 109, and an output amplifier 111.

[0029] In operation, the output amplifier 111 drives an output VOUT that corresponds to the magnitude of the current I or changes with changes in the current I. The magnetic field caused by the current I is sensed by the Hall element 101, and a voltage VOUT corresponding to the magnitude of the magnetic field is output by the semiconductor die 103. In some systems, a calibration scheme may be used to determine the value of the current I from the voltage appearing at the output VOUT. An isolation barrier 112 is shown, which is formed by using a packaging substrate with isolated portions to mount the semiconductor die 103 in the magnetic field caused by the current I, while keeping the semiconductor die electrically isolated from the input IN+ and output IN- to which the current I is supplied. The semiconductor die 103 may be a material that cannot withstand the high voltage applied to the terminal IN+, and may be made of silicon and may operate at a low voltage, such as 5 volts or less. This reduces the cost of the current sensor and allows the semiconductor die 103 to be formed using conventional semiconductor processing.

[0030] FIG. 2A shows a semiconductor device package 200 in a perspective view for use with an arrangement. A package substrate 231, here a conductive lead frame, is shown to include a first portion 227 having a number of leads and a second portion 229 having a number of leads, the first portion 227 and the second portion 229 being spaced apart and electrically isolated from each other. A semiconductor die 203, which may include a Hall element, similar to the semiconductor die 103 of FIG. 1, is mounted to a spacer dielectric 205, which is mounted to the first portion 227 of the package substrate 231. In this manner, the semiconductor die 203 is proximate to the first portion 227 of the package substrate 231 but is electrically isolated from the first portion 227. The second portion 229 of the package substrate 231 is electrically connected to the semiconductor die 203 by an electrical connection between the leads of the semiconductor die 203 and the second portion 229, as shown in FIG. 2A. In this example, the electrical connection is a bond wire 235, although in other arrangements ribbon bonding may be used. The semiconductor die 203, spacer dielectric 205, bond wires 235, and a portion of the package substrate 231 are covered with a mold compound 221 forming a package body. The spacer dielectric 205 has a portion that extends beyond the leadframe first portion 227, and the semiconductor die 203 has a portion that includes the bond pads that extends beyond the spacer dielectric 205.

[0031] The first portion 227 of the package substrate 231 is insulated from the semiconductor die 203 by the spacer dielectric 205, which is an insulator, a die attach material used to mount the spacer dielectric 205 to the first portion 227, and a die attach material used to mount the semiconductor die 203 to the spacer dielectric 205. The package substrate may be a conductive metal lead frame, useful examples include copper, gold, alloy 42, aluminum, stainless steel, steel, and alloys thereof. In some examples, a copper lead frame may be used and may have a thickness of about 0.1 to 0.4 millimeters. The conductive lead frame may be formed by stamping or etching a sheet of conductive material to form solid parts for conductive leads, die pads, and low resistance conductive paths, and to add strength, dimples, holes, openings, and slots that form mold compound stops and enhance adhesion of the mold compound to the lead frame features.

[0032] FIG. 2B illustrates the features of FIG. 2A in more detail in another perspective, partial view. In FIG. 2B, a first portion 227 of a package substrate 231 has a first lead or first group of leads 224 coupled to receive a current I, for example, the leads 224 may be coupled to a high voltage signal or source, greater than several hundred volts, one kilovolt, or several kilovolts. A second set of leads 226 is configured to output the current I to a second node. The current I flows through a current sense portion 239 of the first portion 227, and the current I is carried over a portion of the semiconductor die 203. A spacer dielectric 205 is mounted to the first portion 227 of the package substrate 231 on a device side surface. The semiconductor die is mounted to the spacer dielectric 205 opposite the first portion 227. The first portion 227 of the lead frame has a current sense portion 239 coupled to carry the current I between the first lead 224 and the second lead 226. A portion of the semiconductor die 203 underlies the current sensing portion 239 and is disposed within a magnetic field generated by a current I in the current sensing portion 239. The spacer dielectric 205, the die attach material connecting the spacer dielectric 205 to the first portion 227 of the package substrate 231, and the die attach connecting the semiconductor die 203 to the spacer dielectric 205 together provide electrical isolation between the semiconductor die 203 and the first portion 227. The second portion 229 of the package substrate 231 is electrically connected to the semiconductor die 203 by bond wires 235. The bond pads of the semiconductor die 203 are exposed from the spacer dielectric 205 by mounting the semiconductor die 203 such that the bond pads are exposed from the spacer dielectric 205 such that only a portion of the semiconductor die 203 is covered by the spacer dielectric 205.

[0033] Current sensing portion 239 of first portion 227 is shown above spacer dielectric 205, and semiconductor die 203 has a portion (not shown in FIG. 2B ) that is aligned with current sensing portion 239 so that semiconductor die 203 is exposed to a magnetic field caused by current I flowing through current sensing portion 239. Current sensing portion 239 is a conductor that carries current I across semiconductor die 203. In the above configuration, semiconductor die 203 may be positioned to place a Hall element within the semiconductor die within the magnetic field to sense the magnetic field due to current I.

[0034] FIG. 2C shows the semiconductor device package 200 in a plan view to better illustrate certain aspects. In FIG. 2C, the lead frame first portion 227 includes a first lead or first group of leads 224 and a second lead or second group of leads 226. The first lead 224 receives a current I from a first node, which may be a high voltage signal of more than several hundred volts, more than 1 kV, but up to several kilovolts, and the second lead or group of leads 226 is arranged to couple to a second node and output the current I. The current sensing portion 239 is coupled between the first lead 224 and the second lead 226 and is arranged on the spacer dielectric 205 and on a portion of the semiconductor die 203. The portion of the semiconductor die 203 is aligned with the current sensing portion 239 such that a magnetic field due to the current I flowing through the lead frame first portion 227 reaches a Hall element current sensor in the semiconductor die 203. A second portion 229 of the leadframe is coupled to a bond pad on the semiconductor die by a bond wire 235. Mold compound 221 covers semiconductor die 203, spacer dielectric 205, and bond wire 235 and partially covers the leadframe including first portion 227 and second portion 229, while the leads of the leadframe are exposed from mold compound 221.

[0035] 2D shows a cross-sectional view of a semiconductor device package 200 comprising a mold compound 221 forming a package body, a first portion 227 including leads extending from the mold compound 221, and a second portion 229 of a package substrate including leads extending from the mold compound 221. A spacer dielectric 205 spaces the semiconductor die 203 from the first portion 227. The semiconductor die 203 includes bond pads 208, and bond wires 235 couple the bond pads 208 to leads on the second portion 229 of the package substrate. The second portion 229 and the semiconductor die 203 are electrically insulated from the first portion 227 of the package substrate, which may be a metal lead frame of copper, aluminum, steel, stainless steel, or an alloy such as alloy 42. The spacer dielectric 205 and the mold compound 221 are used to form an insulating barrier between the first portion 227 and the semiconductor die 203.

[0036] 3A-3B show a semiconductor wafer 301 with rows and columns of semiconductor dies 303 formed thereon in projection views, with the individual semiconductor dies 303 after being separated from the semiconductor wafer. In FIG. 3A, the semiconductor dies 303 are formed on the semiconductor wafer 301. Scribe lanes 306 and 307 run across the wafer 301 between the semiconductor dies 303, with the scribe lines orthogonal to each other in parallel groups. The semiconductor dies 303 can be separated from each other by mechanically sawing along the scribe lanes 306, 307, or by using a laser to score the wafer at the scribe lanes and break the semiconductor wafer 301 along the scribed lines. FIG. 3B illustrates an enlarged view of the semiconductor die 303 that may be used in one arrangement. Bond pads 308 are formed on the device surface of the semiconductor die 303. The bond pads 308 are electrically coupled to circuit elements (not shown) formed in the semiconductor die 303.

[0037] Figures 4A-4F illustrate a series of cross-sectional views of a process for forming semiconductor dies for use in one arrangement. In Figure 4A, a semiconductor wafer 401 is shown in cross-section with semiconductor dies 403 formed thereon and scribe lanes 406 shown between the semiconductor dies 403. As shown in Figures 3A-3B, the semiconductor dies may be removed from the wafer by singulating along the scribe lanes between the dies, such as 406.

[0038] 4B illustrates in another cross-sectional view package substrate 431, which may be a conductive leadframe, having first portion 427 and second portion 429. First portion 427 and second portion 429 include conductive leads (leads not visible in this cross-sectional view) that will form terminals for the completed semiconductor device package.

[0039] Figure 4C is another cross-sectional view illustrating the package substrate 431 of Figure 4B after additional processing steps. In Figure 4C, a spacer dielectric 405 is mounted on the device side surface of the first portion 427 of the package substrate 431. The spacer dielectric 405 is an insulator and can be a printed circuit board material such as FR4 or BT resin. In additional alternative arrangements, the spacer dielectric 405 can be glass, plastic, fiberglass, resin, epoxy, semiconductor substrate, or other insulating material.

[0040] FIG 4D is another cross-section illustrating the arrangement of FIG 4C after additional processing steps. The semiconductor die 403 from the semiconductor wafer 401 of FIG 4A is shown mounted to the spacer dielectric 405 on a surface opposite the surface of the spacer dielectric mounted to the first portion 427, such that the spacer dielectric is disposed between the first portion 427, the package substrate 431, and the semiconductor die 403. The semiconductor die 403 is electrically insulated from the conductive first portion 427 of the package substrate 431 by the spacer dielectric 405. The semiconductor die 403 is mounted using a die attach material, which may be a non-conductive die attach film, tape, paste, or epoxy. The semiconductor die 403 is positioned such that the bond pads 408 on the device side surface of the semiconductor die 403 are over the space between the first portion 427 and the second portion 429, such that the semiconductor die 403 is cantilevered over the space. Semiconductor die 403 is mounted “front” side and may be referred to as a “flip chip” mounted to spacer dielectric 405. Bond pad 408 is disposed in the space between first portion 427 and second portion 429.

[0041] FIG. 4E illustrates the package substrate 431 of FIG. 4D in another cross-sectional view after additional processing steps. In FIG. 4E, the elements are shown inverted after the process of FIG. 4D to better illustrate the wire bonding. A bond wire 435 extends from a bond ball on the bond pad 408 to a stitch bond on a second portion 429 of the package substrate 431. The bond wire 435 extends through a space between the first portion 427 and the second portion 429 of the package substrate 431. The bond wire 435 electrically couples the semiconductor die 403 to the second portion 429 of the package substrate 431, which may be a conductive lead frame. In an exemplary process, a wire bonding tool has a capillary through which the bond wire passes. A ball is formed at the end of the wire extending from the capillary by applying a flame or other heat to the exposed end of the bond wire. The ball is placed on a bond pad 408 of the semiconductor die 403 and a ball bond is formed using ultrasonic, mechanical or thermal energy, or a combination thereof. As the capillary is moved away from the bond pad, the wire extends to form an arc or curved shape. The bond wire is placed against a conductive land or lead on the lead frame at the second portion 429 and a stitch bond is formed using mechanical pressure, thermal energy, ultrasonic energy, or a combination thereof. The bond wire is then broken or melted to complete the wire bond, and the process is repeated. In the semiconductor device package 400, the semiconductor die 403 is electrically isolated from the first portion 427, while the semiconductor die 403 is positioned such that a magnetic field generated by a current flowing through the first portion 427 can be sensed by a Hall element formed in the semiconductor die 403.

[0042] FIG. 4F illustrates the elements shown in FIG. 4E in another cross section after the molding process. In FIG. 4F, the mold compound 421 covers the semiconductor die 403, the bond wires 435, the spacer dielectric 405, and a portion of the first portion 427 and a portion of the second portion 429 of the package substrate 431. The first portion 427 and a portion of the second portion 429 are not covered and form terminals for the semiconductor device package 400. The mold compound 421 may be a thermosetting epoxy resin mold compound. The mold compound 421 may be a plastic, epoxy, or resin. The mold compound 421 may be formed by a block molding operation or may be formed by unit molding by a transfer molding process. In an exemplary process, a pack or powder of solid molded thermosetting mold compound is heated to a liquid state and then transferred by pressure through a runner into a mold where the package substrate 431 is placed. The liquid molding compound fills the mold, covering the semiconductor die 403, the bond wires 435, the spacer dielectric 405, and portions of the leads that form the first portion 427 and the second portion 429 of the package substrate 431. The molding compound is allowed to cool and harden, forming the solid body of the semiconductor device package 400. Room temperature molding compounds or dielectrics such as resins or liquid epoxies can be used. In one fabrication example, a strip or array of unitary leadframes are molded simultaneously, and then the individual devices are separated from one another by cutting the package substrate along sawing paths between the molded devices.

[0043] FIG. 4G illustrates in perspective the semiconductor device package 400 of FIG. 4F after processing has been completed with trim and form operations. A first portion 427 of the package substrate includes leads 424 and 426, which may be grouped to form an input IN+ and an output IN−, for example as shown in FIG. 1. The leads 424 and 426 are trimmed to remove any support tie bars connecting the leads for support during the above-described process, and the leads 424 and 426 are shaped to form terminals for surface mounting the semiconductor device package 400. A “trim and form” tool may be used to perform these steps. Mold compound 421 forms a package body that protects the semiconductor die 403 and spacer dielectric 405 (see FIG. 4F).

[0044] U.S. Patent Publication No. 2021 / 0231729A1, entitled "High-Voltage Integrated Circuit Test Interface Assembly," which is incorporated herein by reference in its entirety, discloses a test assembly for performing high-voltage tests on semiconductor device packages. In the above arrangement, a test handler is arranged for performing high-voltage tests on the semiconductor device packages. [Patent Document 1] U.S. Patent Publication No. 2021 / 0231729A1

[0045] 5A-5C illustrate in perspective views a portion of a test handler and a semiconductor device package mounted thereon, showing different configuration features. In FIG. 5A, a semiconductor device package 400 has a body of mold compound 421, a first portion 427 of a package substrate including leads extending from the mold compound 421 to form terminals, and a second portion 429 of a package substrate including leads extending from the mold compound 421 to form additional terminals. A first conductive slug 531 and a second conductive slug 532 are positioned to abut opposite sides of the leads of the first portion 427, and a third conductive slug 533 and a fourth conductive slug 534 are positioned to abut opposite sides of the leads of the second portion 429. A first plunger 541 has a conductive blade 542 and a tip 543, where the blade 542 is a conductive material such as copper or aluminum, and the tip 543 is an insulator. In an exemplary arrangement, tip 543 may be a low dielectric constant polymer, including polyetherimide, polyimide, silicone rubber, and / or foams thereof. In an exemplary arrangement, a plastic foam with a dielectric constant of 1.0 is used for tip 543 with a thickness of 100 microns and a height of approximately 1 millimeter. Blade 542 may be a metal plate of a conductive metal, such as copper, aluminum, steel, stainless steel, or alloys thereof.

[0046] A second plunger 551 is shown below the semiconductor device package 400 and includes a blade 552 and a tip 553. The first plunger 541 and the second plunger 551 are positioned to movably contact the mold compound 421 of the semiconductor device package 400 on opposite sides of the semiconductor device package, such as the top and bottom surfaces of the semiconductor device package 400.

[0047] In operation, conductive slug 531 and conductive slug 532 are coupled to a conductor that applies a high voltage of greater than 300 volts at the lead of first portion 427 of semiconductor device package 400. In an exemplary test, the high voltage is 4 kVrms, but other voltages may be used. The high voltage used in a test arrangement is selected to exceed the rated voltage of the device by a safety margin, with the rated voltage corresponding to the voltage used in the field. Blade 542 of first plunger 541 and blade 552 of second plunger 551 are placed at approximately one-half the high voltage, for example 2 kVrms. Third conductive slug 533 and fourth conductive slug 534 are grounded. The conductive blades 542, 552 are at an intermediate voltage between high voltage and ground, and because the conductive blades 542, 552 are intermediate the semiconductor device package 400 and between the first and second conductive slugs 531, 532 and the third and fourth conductive slugs 533, 534, the electric field concentrations due to the high voltage at the first and second conductive slugs are distributed, reducing or eliminating the high electric field concentrations and preventing arcing in the air surrounding the semiconductor device package during high voltage testing. The high voltage testing is used to ensure that the first portion 427 of the semiconductor device package 400 and the second portion 429 of the semiconductor device package 400 are electrically isolated at the voltage for which the semiconductor device package is rated.

[0048] The above arrangement can be used to prevent air arcing due to high electric field concentrations between the high voltage conductive slugs 531, 532 and the grounded conductive slugs 533, 534. When performing high voltage testing, a good semiconductor device package will not pass current between the first portion 427 of the package substrate and the second portion 429 of the package substrate, which can be confirmed by measuring the current between the conductive slugs. If a current is detected at a predetermined high voltage greater than the rated voltage of the device, the insulation of the device under test is insufficient, i.e., the device fails the high voltage test. Typically, the high voltage is 1.3 to 1.5 times greater than the desired rated voltage. In one particular example, a test voltage of 4 kVrms is used in the high voltage test. If arcing occurs between the slugs in the high voltage test handler during testing, the arc current may erroneously appear as a current flow between the isolated portions of the semiconductor device package, resulting in improper test results. The above arrangement can be used to prevent or reduce arcing due to high electric field concentrations in the tester and in the semiconductor device package. In one example, the polymeric tips 543, 553 of Figure 5A are plastic foam with a dielectric constant of about 1.0. In an additional example arrangement, the polymeric tips 543, 553 are silicone rubber with a dielectric constant of about 3.2.

[0049] 5B illustrates in perspective an alternative arrangement for testing an insulated semiconductor device package. In FIG. 5B, semiconductor device package 400 is shown with mold compound 421 forming the body and with leads of first portion 427 and second portion 429 of the package substrate extending from mold compound 421. First and second conductive slugs 531 and 532 contact the leads of first portion 427, and third and fourth slugs 533 and 534 contact the leads of second portion 429. Plunger 561 contacts the top of semiconductor device package 400, and plunger 571 contacts the bottom of the semiconductor device package, with plungers 561 and 571 positioned in the openings between slugs 531, 532 and slugs 533, 534. Plunger 561, which abuts the top of semiconductor device package 400 (orientation in FIG. 5B), includes several conductive plates or blades, each with a polymeric tip that abuts mold compound 421, which in the illustrated arrangement are made of plastic foam. In additional useful examples, the polymeric tips can be made of low dielectric constant materials, including polyetherimide, polyimide, silicone rubber, and / or foams thereof. In the arrangement illustrated in FIG. 5B, plunger 571 abuts the bottom of mold compound 421 of semiconductor device package 400 and also has four tips 573 and four corresponding blades or plates of conductive material 572 that are bonded together. Plungers 561 and 571 can have blades of copper, copper alloy, steel, stainless steel, aluminum, or alloys thereof. These tips can be, for example, about 100 microns thick and about 1 millimeter high. The plunger abuts the mold compound. The plunger may have a variety of dimensions, in some instances the height and width of the plunger may be several millimeters, and the thickness may be about 100 microns or more. The plunger may have a variety of dimensions, in some instances the height and width of the plunger may be several millimeters, and the thickness may be about 100 microns or more. A slot or notch in the blade may hold the polymeric tip of the plunger.

[0050] 5C illustrates in perspective view another alternative arrangement for testing an insulated semiconductor device package. In FIG. 5C, semiconductor device package 400 is again shown with mold compound 421 forming the body and with leads of first portion 427 and second portion 429 of the package substrate extending from mold compound 421. First and second conductive slugs 531 and 532 contact the leads of first portion 427, and third and fourth slugs 533 and 534 contact the leads of second portion 429. Plunger 581 contacts the top of semiconductor device package 400 and plunger 591 contacts the bottom of the semiconductor device package, with plungers 581 and 591 positioned in the openings between slugs 531, 532 and slugs 533, 534. A plunger 581 that abuts the top of the semiconductor device package 400 (in the orientation in FIG. 5B ) includes several conductive plates or blades with polymeric tips that abut the mold compound 421, and in an exemplary arrangement, the polymeric tips are made of plastic foam. The polymeric tips also include conductive tips 584. In additional useful examples, the polymeric tips can be made of low dielectric constant materials, including polyetherimide, polyimide, silicone rubber, and / or foams thereof. In the arrangement illustrated in FIG. 5C , a plunger 591 abuts the bottom of the mold compound 421 of the semiconductor device package 400 and also has four tips 593 and corresponding blades or plates of conductive material 572 that are bonded together. The plunger 592 also has conductive tips 594, which can be made of copper, aluminum, or other conductors. The conductive tips can be, for example, about 100 microns thick and about 1 millimeter high. The tip of the plunger contacts the mold compound.

[0051] In one high voltage insulation test, a high voltage of greater than 300 volts is applied to the first slug 531 and the second slug 532 while the slugs are in contact with the leads of the first portion 427. During the high voltage test, the third and fourth slugs 533, 534 in contact with the leads of the second portion 429 of the semiconductor device package 400 are grounded and the conductive blades or plates 582, 592 of the plungers 581, 591 are placed at approximately half the high voltage. By applying approximately half the high voltage to the plungers in contact with the semiconductor device package during the high voltage insulation test, the electric field is distributed around the semiconductor device package 400 in the test handler, avoiding high electric field concentrations. Potential arcing between the slugs at high voltage and ground due to dielectric breakdown is prevented.

[0052] FIG. 5D illustrates in electrical schematic form one circuit for the test handler arrangement. In FIG. 5D, first conductive slug 531 and second conductive slug 532 are coupled to high voltage HV+, which may be coupled to a high voltage of 300 volts or more, such as 1 kV, 2 kV, etc. In the exemplary test, a high voltage of 4 kVrms is used. Third conductive slug 533 and fourth conductive slug 534 are coupled to ground.

[0053] In the above arrangement, a voltage of HV+ / 2, i.e., approximately half of the high voltage, is applied to plunger 541, which is disposed against the top surface of the semiconductor device package as shown in FIGS. 5A-5C, and plunger 551, which is disposed against the bottom surface of the semiconductor device package as shown in FIGS. 5A-5C. In the illustrated example, the voltage is divided using a capacitive voltage divider. Plunger 541 is coupled to a first capacitor C1 and a second capacitor C2, and plunger 551 is coupled to a third capacitor C3 and a fourth capacitor C4. By making the capacitance of each of the capacitors C1-C4 the same, the high voltage HV+ is divided in half at the node between the capacitors to which plungers 541, 551 are coupled. Additional arrangements can be made using other circuit elements that provide a voltage to the plungers that corresponds to half of the high voltage HV+.

[0054] 5E illustrates an example arrangement of a voltage divider adapted for use in a test handler to provide a voltage HV+ / 2 to plungers 541, 551. A first conductive slug 531 and a second conductive slug 532 are coupled to a high voltage input labeled HV+ for receiving a high voltage during testing. A semiconductor device package 400 is shown in the test handler with the first conductive slug 531 and the second conductive slug 532 contacting leads of a first portion 427 of a lead frame of the semiconductor device package 400. A third conductive slug 533 and a fourth conductive slug 524 contact leads of a second portion 429 of a lead frame of the semiconductor device package 400, the third conductive slug 533 and the fourth conductive slug 524 being coupled to inputs that can be coupled to ground or a voltage reference. A first frame 535 carries a capacitor C1 coupled between the first conductive slug 531 and a conductive plate 542 of the first plunger 541. A second frame 537 carries a second capacitor C2 coupled between conductive plate 542 of first plunger 541 and third conductive slug 533. A third frame 536 carries a capacitor C3 coupled between second conductive slug 532 and conductive plate 552 of second plunger 551. A fourth frame 538 carries a fourth capacitor C4 coupled between conductive plate 552 of second plunger 551 and fourth conductive slug 534. Capacitors C1 and C2 divide the voltage at first conductive slug 531 in half and this voltage (approximately HV+ / 2) is coupled to first plunger 541. First frame 535 and second frame 537 carry capacitors C1, C2, first conductive slug 531, third conductive slug 533, and first plunger 541 and may be moved together to move semiconductor device package 400 into and out of a test handler. Third frame 536 and fourth frame 538 carry capacitors C3, C4, second conductive slug 532, fourth conductive slug 534, and second plunger 551 and these frames and other elements mounted thereon may be moved together to move semiconductor device package 400 into and out of a test handler.Capacitors C3 and C4 divide the voltage HV+ at second conductive slug 532 in half, and this voltage (approximately HV+ / 2) is coupled to second plunger 551. Frames 535, 537, 536, 538 can be made of a conductive metal such as copper or stainless steel and can couple the capacitors as described above, or wires can be used to couple the capacitors as described above, and the frames can be made of any material of sufficient strength. The test handler frame can be moved so that semiconductor device package 400 can be loaded between the conductive slugs, which can then be positioned against the leads of the lead frame with tips 543 and 553 of first plunger 541 and second plunger 552 in contact with mold compound 421, as shown. During high voltage testing, a voltage HV+ / 2 is coupled to the conductive plates 542, 552 of the plunger to distribute the electric field across the semiconductor device package 400 and avoid high electric field concentrations and arcing that could otherwise occur when the electric field breaks down in the air between the elements.

[0055] Figure 6A shows the resulting cubic meters [m 3 ] in units of stress volume S V 6A illustrates simulation results from a finite element analysis simulator showing the stress volume S V6 is a graph of the electric field E, with the horizontal scale shown in volts per micron [V / μm]. The plot labeled "Conventional Approach" corresponds to a test handler without the above arrangement, Case 1 plot corresponds to a single-blade plunger with a silicone rubber insulated tip (such as in FIG. 5A), Case 2 plot corresponds to a single-blade plunger with a polymeric foam tip (such as in FIG. 5A), Case 3 corresponds to a four-blade plunger with an insulated tip (such as in FIG. 5B), and Case 4 corresponds to four insulated blades and a metal blade (such as in FIG. 5C). The arrow indicates the point on the horizontal axis where the electric field E is 3 V / μm. The data obtained at this point is shown in the table of FIG. 6B.

[0056] In FIG. 6B, the table shows the stress volume Sv of the plot of FIG. 6A at the point where the electric field E is 3 V / μm (see the downward arrow in FIG. 6A). In the first row, labeled "Conventional Approach," without the above arrangement, the conventional approach test handler produced a stress volume Sv of 75.59. VIn the table, the second row, labeled "Case 1 - Single Blade, Dielectric Constant 3.2," illustrates the configuration of FIG. 5A using a silicone rubber tip material with a stress volume Sv of 9.43, an improvement over the conventional approach. The third row, labeled "Case 2 Single Blade with Polymer, Dielectric Constant 1.0," illustrates configurations such as that of FIG. 5A with a single blade insulating tip made of a low dielectric constant plastic foam. The resulting stress volume Sv was 2.94, the best performing configuration. The remaining rows, Cases 3 and 4, illustrate the performance of the configuration of FIG. 5B, which is multiple tips on multiple blades, and the configuration of FIG. 5C, which is multiple blades with tips of dielectric constant 2.1 and conductive tips contacting the mold compound of a semiconductor package. These configurations improved the stress volume Sv over the conventional approach, but to a lesser extent than the single blade configurations of Cases 1 and 2. The arrangement of Figure 5A with a single blade and a single polymer tip of plastic foam with a dielectric constant of about 1.0 is the preferred arrangement of the examples shown, and shows a significant performance improvement over the conventional approach, with a reduction of about 96%, as shown in the table of Figure 6B, although each example shown shows an improvement over the conventional approach.

[0057] 7A-7B illustrate in a flow chart a method arrangement for manufacturing a semiconductor device. In step 701, a package substrate, which may be a conductive leadframe, is formed having spaced apart and electrically isolated first and second portions, the leadframe having a first device side surface and an opposing side surface (see first portion 427 and second portion 429 in FIG. 4B).

[0058] In step 703, a first surface of a spacer dielectric is mounted to the device side surface of the first portion, the spacer dielectric having a second surface opposite the first surface, the spacer dielectric being partially covered by and extending beyond the first portion (see spacer dielectric 405 in FIG. 4C ).

[0059] In step 705, a semiconductor die is mounted to the second surface of the spacer dielectric, a portion of the semiconductor die being covered by the spacer dielectric, and the semiconductor die having bond pads exposed from the spacer dielectric (see semiconductor die 403 in FIG. 4D with bond pads 408).

[0060] At step 707, electrical connections are made between the bond pads of the semiconductor die and the second portion of the lead frame (see bond wires 435 in FIG. 4E). Alternative electrical connections include ribbon bonding.

[0061] In step 709, a mold compound is used to cover the semiconductor die, the spacer dielectric, and partially cover the first portion of the leadframe and the second portion of the leadframe to form a semiconductor device package (see mold compound 421 in FIG. 4F and semiconductor device package 400 in FIG. 4G).

[0062] In step 711, the leads of the first portion and the leads of the second portion are shaped and any connecting material is removed to complete the semiconductor device package (see semiconductor device package 400 in FIG. 4G).

[0063] The method continues in Figure 7B. The steps shown in Figure 7A may be performed asynchronously with the test method steps of Figure 7B, and the semiconductor device package may be manufactured at any time and place, and then the test method of Figure 7B may be performed to complete this method arrangement.

[0064] In step 713, a first conductive slug and a second conductive slug of the test handler are brought into contact with leads of a first portion of a lead frame of a semiconductor device package having insulation (see, for example, conductive slugs 531, 532 in FIG. 5E).

[0065] A third conductive slug and a fourth conductive slug of the test handler are contacted with the leads of the second portion of the lead frame in step 715. Although for ease of explanation these are described as separate, successive steps, the test handler may perform these steps simultaneously, as well as steps 717 and 719 below.

[0066] In step 717, a first plunger having a conductive plate and an insulating tip is contacted with a first surface of the molding compound of the semiconductor device package. The first plunger is between the first slug and the third slug in the space between the conductive slugs of the test handler. In the example shown in FIG. 5E, first plunger 542 contacts the top surface of mold compound 421 and is positioned midway between conductive slugs 531 and 533.

[0067] At step 719, a second plunger having a conductive plate and an insulating tip is brought into contact with a second surface of the mold compound of the semiconductor device package, the second plunger being positioned between the second slug and the fourth slug of the test handler. In the example shown in FIG. 5E, the second plunger is positioned opposite the first plunger, underneath the semiconductor device package, and in contact with the bottom surface of the mold compound 421.

[0068] In step 721, a high voltage is placed on the leads of the first portion, a voltage approximately half the high voltage is placed on the conductive plates of the first and second plungers, and the leads of the second portion are placed at ground voltage. In step 723, a test is performed by measuring the current between the leads of the first portion where the first and second slugs are in contact with the leads at high voltage and the leads of the second portion where the third and fourth conductive slugs are in contact with the leads at ground voltage. If the current is below a predetermined threshold, set at a low or zero current level, it indicates that the insulation within the semiconductor device package is sufficient and that the semiconductor device package has passed the high voltage insulation test. Conversely, if the current flowing exceeds a predetermined level, it indicates that the insulation of the semiconductor device package is not sufficient and that the semiconductor device package has failed the high voltage insulation test. The failed devices should be identified and either discarded or repaired.

[0069] In an exemplary arrangement, a semiconductor device is manufactured, including a semiconductor device package with an insulated portion in a package substrate, such as a lead frame. The electrical insulation is then tested. A high voltage, greater than 300 volts and up to several kilovolts, is placed on a first portion of the lead frame in a test handler. A plunger having a conductive plate and an insulated tip is placed in contact with the mold compound of the semiconductor device package. In such an arrangement, the plunger is split from the high voltage and placed at a voltage that is approximately half of the high voltage on the first portion. A ground voltage is placed on the lead of the second portion of the lead frame. Using such an arrangement and the split voltage on the plunger in contact with the mold compound of the semiconductor device package distributes the electric field in the test handler due to the high voltage, preventing arcing in the air and reducing current due to arcing that may otherwise occur. Various structures are used in the test handler to reduce the concentration of electric fields in the insulated device package. In an exemplary arrangement, a capacitor splitting structure is used to split the high voltage into a divided voltage of half the high voltage, which is coupled to the conductive plate of the plunger. The use of such a structure in a test handler for performing high voltage insulation testing of semiconductor device packages reduces electric field concentrations that occur when a first portion of a lead frame is coupled to a high voltage.

[0070] Modifications in the described arrangements are possible, and other alternative arrangements are possible, within the scope of the claims.

Claims

1. 1. A method for testing insulation in a semiconductor device package, comprising: placing a semiconductor device package in a test handler, the semiconductor device package including a first lead on a first portion of a package substrate extending from a molding compound forming a package body of the semiconductor device package and a second lead on a second portion of the package substrate extending from the molding compound, the first portion being electrically isolated from the second portion; contacting a first lead of the first portion with a first conductive slug and a second conductive slug of the test handler; contacting a second lead of the second portion with a third conductive slug and a fourth conductive slug of the test handler, the third conductive slug and the fourth conductive slug being spaced apart from the first conductive slug and the second conductive slug; contacting a first surface of the mold compound with a first plunger including a conductive plate and an insulating tip, the insulating tip contacting the first surface of the mold compound; contacting a second surface of the mold compound opposite the first surface of the mold compound with a second plunger, the second plunger including a conductive plate and an insulating tip, the insulating tip contacting the second surface of the mold compound; applying a high voltage to the first conductive slug and the second conductive slug, while applying approximately half of the high voltage to the first plunger conductive plate and the second plunger conductive plate, while applying a ground voltage to the third conductive slug and the fourth conductive slug; A method comprising:

2. 10. The method of claim 1, applying approximately half of the high voltage to a conductive plate of the first plunger; coupling a first capacitor having a first capacitance between a first conductive slug of the test handler and a conductive plate of the first plunger; coupling a second capacitor having the first capacitance between a conductive plate of the first plunger and a third conductive slug of the test handler; A method comprising:

3. 10. The method of claim 1, The method further includes measuring a current between the first conductive slug and the third conductive slug while the high voltage is coupled to the first conductive slug.

4. 4. The method of claim 3, The method further includes indicating that the semiconductor device package failed a high voltage insulation test in response to the current being determined to be greater than a predetermined threshold.

5. 4. The method of claim 3, The method further includes indicating that the semiconductor device package has passed a high voltage insulation test in response to the current being determined to be less than a predetermined threshold.

6. 1. A method of forming a semiconductor device, comprising: forming a semiconductor die on a semiconductor wafer; forming a package substrate including a first portion having a device-side surface and an opposite surface, a second portion spaced apart and electrically isolated from the first portion, and a conductive lead frame; mounting a first surface of a spacer dielectric, the first surface having a first surface and a second surface opposite the first surface, on a device side surface of a first portion of the package substrate, the spacer dielectric being partially covered by and extending beyond the first portion; mounting one of the semiconductor dies to a second surface of the spacer dielectric, the one of the semiconductor dies being partially covered by the spacer dielectric and having bond pads formed on a surface of the semiconductor die that extend beyond the spacer dielectric; coupling the bond pads of the semiconductor die by making electrical connections from the bond pads to leads formed by a second portion of the lead frame; encasing the semiconductor die, the electrical connections, and the spacer dielectric in a molding compound, and partially encasing the first portion of the leadframe and the second portion of the leadframe; forming a semiconductor device package by shaping a first lead of the first portion extending from the molding compound and shaping a second lead of the second portion extending from the molding compound; contacting a first conductive slug and a second conductive slug of a test handler to a first lead of the first portion; contacting a third conductive slug and a fourth conductive slug of the test handler to a second lead of the second portion; contacting a first plunger including a conductive plate and an insulating tip with a first surface of a mold compound of the semiconductor device package, the first plunger being positioned between a first slug and a third slug of the test handler; contacting a second plunger including a conductive plate and an insulating tip with a second surface of the molding compound of the semiconductor device package opposite the first surface of the molding compound, the second plunger being opposite the first plunger and positioned between a second slug and a fourth slug of the test handler; applying a high voltage to a first lead of the first portion, a voltage approximately half of the high voltage to a conductive plate of the first plunger and a conductive plate of the second plunger, and a ground voltage to a second lead of the second portion; A method comprising:

7. 7. The method of claim 6, The method further includes measuring a current between a first portion and a second portion of the package substrate.

8. 8. The method of claim 7, indicating that the semiconductor device failed a high voltage insulation test in response to determining that the current is greater than a predetermined threshold; and indicating that the semiconductor device package has passed a high voltage insulation test in response to the current being determined to be less than the predetermined threshold; and The method further comprises:

9. 7. The method of claim 6, applying a voltage of approximately half of the high voltage to the conductive plate of the first plunger; coupling a first capacitor having a first capacitance in series between a first conductive slug of the test handler and a conductive plate of the first plunger; coupling a second capacitor having the first capacitance in series between a conductive plate of the first plunger and a third conductive slug of the test handler; A method comprising:

10. 10. The method of claim 9, coupling a third capacitor having the first capacitance in series between a second conductive slug of the test handler and a conductive plate of the second plunger; coupling a fourth capacitor having the first capacitance in series between a conductive plate of the second plunger and a fourth conductive slug of the test handler; The method further comprises:

11. 7. The method of claim 6, The method wherein the high voltage is greater than 300 volts.

12. 7. The method of claim 6, The method wherein the high voltage is greater than 1 kilovolt.

13. 7. The method of claim 6, contacting the conductive plate and a first plunger having an insulated tip with a first surface of the mold compound; contacting a first surface of the molding compound with a first plunger comprising a conductive plate of copper, aluminum, steel, stainless steel, or an alloy thereof and an insulating tip comprising polyetherimide, polyimide, silicone rubber, plastic, or a foam of one of these.

14. 14. The method of claim 13, contacting a first plunger including the conductive plate and an insulating tip with a first surface of the mold compound; The method includes contacting a plurality of insulating tips of a first plunger, the first plunger including several conductive plates with insulating tips connected in parallel, with a first surface of the mold compound.

15. 15. The method of claim 14, contacting a first plunger including several conductive plates with parallel insulating tips with a first surface of the molding compound; The method includes contacting a first plunger including several conductive plates with parallel insulating tips and conductive tips parallel to the insulating tips with a first surface of the mold compound.

16. 7. The method of claim 6, The method, wherein forming the semiconductor die includes forming a semiconductor die including a Hall element.

17. 17. The method of claim 16, The method, wherein forming a semiconductor die including the Hall element includes forming a semiconductor die including circuitry configured to sense current using the Hall element.

18. 7. The method of claim 6, mounting the semiconductor die to the spacer dielectric; 1. The method of claim 1, wherein the semiconductor die is electrically isolated from the first portion of the lead frame while being exposed to a magnetic field corresponding to a current flowing through the first portion of the lead frame.

19. 1. A test handler for performing a high voltage insulation test on a semiconductor device package, comprising: a first conductive slug and a second conductive slug configured to contact a first lead of a first portion of a package substrate of the semiconductor device package, the first conductive slug and the second conductive slug configured to be coupled to a high voltage; a third conductive slug and a fourth conductive slug configured to contact a second lead of a second portion of a package substrate of the semiconductor device package, the third conductive slug and the fourth conductive slug configured to be coupled to a ground voltage; a first plunger configured to contact a first surface of a molding compound forming a body of the semiconductor device package, the first plunger including a conductive plate and an insulating tip positioned to contact the first surface of the molding compound, the conductive plate configured to be coupled to a voltage that is approximately half of the high voltage; a second plunger configured to contact a second surface of the mold compound opposite the first surface of the mold compound, the second plunger including a conductive plate and an insulated tip positioned to contact the second surface of the mold compound, the conductive plate configured to couple to approximately half of the high voltage; Test handlers, including:

20. 20. The test handler of claim 19, a first capacitor connected in series between the first conductive slug and the conductive plate of the first plunger; a second capacitor coupled in series between the conductive plate of the first plunger and a third conductive slug of the test handler; a third capacitor coupled in series between a second conductive slug of the test handler and a conductive plate of the second plunger; a fourth capacitor coupled in series between the conductive plate of the second plunger and a fourth conductive slug of the test handler; Including, The first, second, third and fourth capacitors have the same capacitance.

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