Fault injection attack countermeasures

Abstract

The method includes programming (410) a first value and a second value and a first compare enable command into respective first operand, second operand, and first compare enable command registers in a hardware comparator circuit. The method includes determining (440, 450) that there is a first match corresponding to the first and second values, programming a third value into the first operand register, a fourth value into the second operand register, and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit. In response to determining that there is a second match corresponding to the third and fourth values, the method includes asserting a success interrupt signal, programming (472) a fifth value into the first operand register, a sixth value into the second operand register, and programming the second compare enable command into the second compare enable command register in the hardware comparator circuit.

Description

[Technical field]

[0001] A fault injection attack is a tool that allows an attacker to access resources (e.g., memory, interfaces, etc.) in a device. An attacker may gain unauthorized access to resources by causing unpredictable system behavior and security violations. Some techniques for injecting faults into a system may include voltage glitch injection, clock glitch injection, and electromagnetic fault injection (EMFI). A fault injection attack may corrupt instructions, cause instructions to be skipped during execution, corrupt arguments for instructions, cause improper execution flow, etc. For example, a fault injection attack may bypass authentication mechanisms that protect access to a particular resource, thereby exposing access to the resource to the public. Although some software coding implementations may improve the overall security for protecting access to resources, such implementations may not provide strong enough resilience against well-synchronized fault injection attacks. Summary of the Invention

[0002] In one example, a method includes programming a first value and a second value and a first compare enable command into respective first operand, second operand, and first compare enable command registers in a hardware comparator circuit. The method includes determining that a first match exists corresponding to the first value and the second value, programming a third value into the first operand register and a fourth value into the second operand register, and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit. In response to determining that a second match exists corresponding to the third and fourth values, the method includes asserting a success interrupt signal, programming a fifth value into the first operand register and a sixth value into the second operand register, and programming the second compare enable command into the second compare enable command register in the hardware comparator circuit.

[0003] In another example, an integrated circuit (IC) includes a computer resource, a hardware comparator circuit, and a microcontroller unit (MCU) coupled to the hardware comparator circuit. The hardware comparator circuit includes a first operand register, a second operand register, a first compare enable command register, a second compare enable command register, a third compare enable command register, and a scratchpad register. The MCU is configured to write a first value to the first operand register, a second value to the second operand register, a first compare enable command to the first compare enable command register, and a scratchpad value to the scratchpad register, the scratchpad value identifying the computer resource. The MCU is further configured to determine that a first match exists corresponding to the first and second values, and to write a third value to the first operand register, a fourth value to the second operand register, and a second compare enable command to the second compare enable command register. In response to receiving a success interrupt signal from the hardware comparator circuit indicating that there is a second match corresponding to the third and fourth values, the MCU is configured to write a fifth value to the first operand register, a sixth value to the second operand register, and write a second compare enable command to the second compare enable command register. [Brief description of the drawings]

[0004] For a detailed description of various examples, reference will now be made to the accompanying drawings.

[0005] [Figure 1] 1 is a block diagram of a system that implements improved countermeasures against fault injection attacks in accordance with one or more embodiments.

[0006] [Diagram 2] FIG. 2 is a block diagram of a hardware comparator circuit that may be utilized in one or more embodiments to provide additional defense against fault injection attacks.

[0007] [Diagram 3] 1 is a flowchart illustrating a process for reducing the likelihood of resource access via a fault injection attack in one or more embodiments.

[0008] In the drawings, the same reference numbers are used for the same or similar features (either of function and / or structure). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In some software techniques, access to a resource (e.g., memory, interface, etc.) may involve computing an access parameter, such as a digital signature, and comparing the newly computed access parameter with a previously stored access parameter. If the access parameters match, access to the resource is granted. If the access parameters do not match, access to the resource is denied. A relatively small number of instructions are required to determine whether the access parameters match. For example, most coding languages ​​have some form of "If-then" instructions where a condition is checked for being "true" or "false". If the condition (e.g., whether the access parameters match) is true, access to the resource is enabled. Such software instructions can be skipped by a fault injection attack.

[0010] The fault injection countermeasure system described herein separates the function of checking the conditions necessary to enable access to a resource from the function of actually enabling the resource. In one embodiment, one or more comparisons of an operand (e.g., an access parameter unique to the target resource, such as a digital signature, a password, etc.) are performed in a hardware comparator which, if the comparison is successful, triggers a hardware interrupt to complete the process of enabling access to the resource. Additional checks can be performed by an interrupt service (ISR) routine to further ensure that an authorized attempt to access the resource is being made.

[0011] FIG 1 is a block diagram of a system 100 according to one or more embodiments. In one or more embodiments, the system 100 is implemented as an integrated circuit (IC). In one example, the IC is a system on a chip (SoC). As shown in the example of FIG 1, the system 100 includes a microcontroller unit (MCU) 211, a hardware comparator circuit (HW CMP) 213, a random access memory (RAM) 215, a read only memory (ROM) 217, and a flash memory 219. The MCU 211 is coupled to the RAM 215, the ROM 217, the flash memory 219, and the HW CMP 213 via one or more buses 218.

[0012] Executable instructions may be stored in any of RAM 215, ROM 217, and / or flash memory 219 and executed by MCU 211. In the illustrated example, firmware 221, success interrupt service routine (ISR) 222, and failure ISR 223 are stored in ROM 217. ROM 217 (as well as RAM 215 and flash memory 219) are non-transitory computer-readable media. Instructions (e.g., firmware 221, success ISR 222, and failure ISR 223) may be retrieved from ROM 217 and executed by MCU 211 as described herein. References herein to firmware 221, success ISR 222, or failure ISR 223 performing a function include MCU 211 performing such function upon execution of the corresponding executing firmware 221, success ISR 222, or failure ISR 223.

[0013] System 100 also includes one or more computer resources 250, access of which is restricted only to authorized entities. Computer resources 250 may include interfaces to system 100, such as a Joint Test Action Group (JTAG) interface, memory (e.g., one or more of RAM 215, ROM 217, and / or flash memory 219, or a subset of their contents), resources within MCU 211, etc. As described herein, a combination of MCU 211 executing firmware, interrupt service routines (ISRs), and HW CMP 213 are used to enable access to computer resources 250. In one embodiment, MCU 211 executes firmware 221 to calculate access parameters, such as a digital signature or other type of control value (required to grant access to a given computer resource), and programs registers in HW CMP 213 with the newly calculated signature and a pre-stored signature. The HW CMP 213 then performs one or more comparisons of the two signatures (each comparison is performed as the MCU 211 programs registers in the HW CMP 213). If the signatures match, a success interrupt (SI) 230 is asserted by the HW CMP to the MCU 211, which responds by executing a success ISR 223 to enable the target computer resource via an enable signal 209. In another embodiment, the HW CMP 213 enables the target computer resource via an enable signal 207. If none of the comparisons performed by the HW COMP 213 match, the HW CMP 213 asserts a FI 280 to the MCU 211, which responds by executing a failure ISR 223. In the latter case, the target computer resource 250 is not enabled.

[0014] 2 is a block diagram of HW CMP 213 in one example. In this example, HW CMP 213 includes bus interface 310, configuration and control registers 320, controller 335, digital comparator 330, timer 350, latches 360A, 360B, and 360C, AND gates 370A and 370B, event generator 380, and signal generator 390. Bus interface 310 provides access between MCU 211 and HW CMP 213 via bus 218. Through bus interface 310, MCU 211 can write (or read) one or more of the registers in configuration and control registers 320. The registers include a clear register 321, a first compare enable command register 322, a second compare enable command register 323, a third compare enable command register 324, an operand A register 325, an operand B register 326, a scratch pad register 327, a timeout register 328, and a status register 329. A controller 335 accesses the registers and responds as described below. A signal connection 353 between the controller 335 and the configuration and control registers 320 may include one or more signals. The signal connection 353 may allow the controller 335 to read and / or write one or more of the registers.

[0015] Digital comparator 330 is an m-bit comparator and has inputs 332 and 334. The digital comparator compares the m-bit value on input 332 with the m-bit value on input 334. The comparison is a bit-wise comparison (e.g., bit 0 of operand A register 325 is compared with bit 0 of operand B register 326, bit 1 of register 325 is compared with bit 1 of register 326, etc.). In one embodiment, m is 256 bits, although m may include any suitable number of bits. Digital comparator 330 compares operand A and operand B from registers 325 and 326, respectively, and outputs comparator output signal 336 accordingly. In one example, comparator output signal 336 is a single digital signal that is asserted logic high if all bits of operand A match the corresponding bits of operand B; otherwise, comparator output signal 336 is logic low indicating a mismatch in any one or more bits between operands A and B. In the example of FIG. 2, the bubbles on input 334 indicate that the digital comparator inverts each bit of operand B before comparing the inverse of operand B with operand A. In such an embodiment, MCU 211 (via firmware 221) writes operand A register 325 to include the inverse of a value to be compared with the value that the MCU writes to operand B register 326. For example, if MCU 211 intends for HW CMP 213 to compare a newly calculated signature to an existing signature, MCU 211 may invert the bits of the newly calculated signature, write those bits to operand A register 325, and write the non-inverted bits of the existing signature to the operand B register. Alternatively, the MCU can write the non-inverted bits of the newly computed signature to operand A register 325, invert the bits of the existing signature, and write those (inverted) bits to operand B register. In yet another embodiment, digital comparator 330 compares the bits of registers 325 and 326 without inverting either of its inputs and without performing an inversion operation.

[0016] The output of the digital comparator 330 is coupled to the inputs of latches 360A, 360B, and 360C. Each latch 360A-C has an enable (EN) input. The EN input of latch 360A is controlled by controller 335 (via enable first comparison signal 341). One input of AND gate 370A is coupled to the output of latch 360A, and the other input of AND gate 370A is coupled to controller 335 (and receives enable second comparison signal 342). The output of AND gate 370A is coupled to the EN input of latch 360B. One input of AND gate 370B is coupled to the output of latch 360B, and the other input of AND gate 370B is coupled to controller 335 (and receives enable third comparison signal 343). The output of AND gate 370B is coupled to the EN input of latch 360C. As described below, a sequence of comparisons of the contents of the Operand A and Operand B registers is performed with controller 335 enabling latch 360A, which then latches a first successful comparison of Operands A and B by latch 360A, thereby enabling latch 360B upon assertion of an enabled second compare signal 342 by controller 335. A second successful comparison of the Operand A and B registers is then latched via latch 360B, which then latches a third successful comparison of the Operand A and B registers by assertion of an enabled third compare signal 343 by controller 335. Although three latches are shown in the example of FIG. 2, any number of latches may be included.

[0017] The event generator 380 receives the first result output signal 362 of the latch 360A and the second result output signal 364 of the latch 360B. The first and second results correspond to a logic high if operand A matches operand B during the respective comparisons by the digital comparator 330. If either or both of the first and second result signals indicate a mismatch, the event generator 380 asserts the FI signal 280 to the MCU 211. If both the first and second result signals indicate a successful match of operands A and B, the event generator asserts the SI signal 230 to the MCU 211. The MCU 211 executes the ISR (success ISR 222 or failure ISR 223) that corresponds to the particular interrupt that is asserted. In one embodiment, the controller 335 is implemented as a finite state machine. Thus, the states of the controller 335 are predefined, and each state is entered only from certain other states and with predefined signaling. If the controller detects any other set of conditions, signals, states, etc., the controller asserts a fault signal 345 to the event generator 380. The asserted fault signal 345 causes the event generator to assert the FI signal 280.

[0018] The MCU 211 can also write a time value to the timeout register 328. The time value can be a value long enough to allow the MCU 211 to write values ​​to the configuration and control registers 320 (e.g., 10% longer than the amount of time required to update the registers). If the timer 350 expires before the MCU has completely updated all of the configuration and control registers 320, the timer 350 asserts a timeout signal 352 to the event generator 380, which responds by asserting a fail interrupt 280, and the process is blocked. In some embodiments, the size of the value to be written to the register is larger than the width of the bus 218. Thus, multiple write cycles are performed to completely write the value to the configuration and control registers 320. The controller 335 reads the timeout register 328 and programs the timer 350 to begin counting for a time corresponding to the timeout register value. The controller 335 stops the timer 350 once the MCU 211 has finished loading a new set of values ​​into the configuration and control registers 320. In one example, MCU 211 may send a packet to controller 335 indicating the end of the register update process. In another example, configuration and control registers 320 assert a signal (in signal connection 353) to controller 335 indicating that the register update is complete. If timer 350 expires before register 320 is fully updated, the timer asserts timeout signal 352, which causes event generator 380 to assert failure interrupt 280. Assertion of failure interrupt 280 prevents target resource 250 from being enabled. Thus, event generator 380 asserts failure interrupt signal 280 if any comparison of operands A and B fails, if abnormal behavior is detected, or if a timeout occurs.

[0019] 2, the output of latch 360C is third result signal 366, which is provided to an input of signal generator 390. Third result signal 366 also asserts a read enable bit (or read enable bits) 373 in scratch pad 327, thereby making scratch pad 327 readable by MCU 211. Otherwise, scratch memory register 327 would not be readable by MCU 211, as described below.

[0020] In one embodiment (described below), the MCU responds to the assertion of the SI signal 230 by executing a success ISR 222 that causes the MCU 211 to perform one or more operations before the target computer resource 250 is enabled. If such operations are successful, the MCU 211 asserts an enable signal 209 to enable the target computer resource. In another embodiment, the success ISR may reprogram registers in the HW CMP 213 to perform a further comparison of the operands, which, if successful, causes a signal generator 390 in the HW CMP 213 to assert an enable signal 207 to the target computer resource 250.

[0021] The status register 329 can be read by the MCU 211 and provides status information regarding the operation and state of the HW CMP. In one example, the controller 335 updates the status register 329 with the success / failure result of each of the operand comparison operations described herein. The clear register 321 can be used to reset the HW CMP to an initial state, including disabling the scratchpad register 327. The MCU 211 can write to the clear register 321 at any time to reset the HW CMP 213. For example, after the MCU 211 completes an authentication process and enables the target computer resource 250, it can write to the clear register 321 to reset the HW CMP 213, so that the scratchpad register 327 is not readable at the start of the next process to enable the computer resource 250.

[0022] 3 illustrates a method for enabling access to a target computer resource. At the end of a previous attempt to enable computer resource 250, MCU 211 (in firmware execution) writes to clear register 321 in HW CMP 213, which in part updates the read enable capability of scratch pad register 327 to disallow reading. At that point, scratch pad register 327 can be written to but cannot be read from.

[0023] At step 410, the method includes receiving access parameters for the target resource 250 from an input source. The access parameters may be a newly calculated digital signature (e.g., calculated by the MCU 211), a password, a PIN, etc. In one embodiment, the access parameters are unique to the target resource. In one embodiment, step 410 is performed by the MCU 211 executing firmware that is not part of an interrupt service routine.

[0024] At 430, the method includes implementing a random (or pseudo-random time) delay. Any suitable software or hardware implemented delay function may be used to implement the random delay. In one example, the delay may be between 10 and 200 milliseconds. The introduction of the random delay at steps 430 and 480 (described below) helps minimize the risk of a synchronous fault injection attack by exposing access to resources.

[0025] At 440, the method includes performing a comparison between the received access parameters (from step 410) and pre-configured access parameters. The pre-configured access parameters may be pre-calculated and are known valid parameters for the target resource. The pre-configured access parameters may be stored in any of the memory devices (RAM 215, ROM 217, and flash memory 219) and may be retrieved therefrom by MCU 211.

[0026] In one embodiment, step 440 is performed by MCU 211 executing firmware that is not part of the interrupt service routine. In one example, MCU 211 writes the access parameters to operand registers 325 and 326. For example, MCU 211 may perform a bitwise inversion of the newly calculated access parameters and then write the inverted newly calculated access parameters to operand A register 325. MCU 211 may also write a pre-set access parameter (non-inverted) to operand B register 326. As part of step 440, MCU 211 may also write a value to first compare enable command register 322 to trigger controller 335 of HW CMP 213 to enable latch 360A to latch the result of the first comparison, and write a value to scratchpad register 327. The value written to scratchpad register 327 may identify a target computer resource to be enabled. MCU 211 may also write a time value to timeout register 328. At this point, the MCU 211 does not write to the second and third compare enable command registers 323 and 324 .

[0027] As described above, the controller 335 is implemented as a finite state machine (e.g., a combination of logic gates, counters, flip-flops, etc.), and at this point in the process flow, the controller 335 is in a state in which it expects the first compare enable command register to be written to enable a first compare operation. If the second or third compare enable command registers are written to enable their respective commands, the controller 335 responds by asserting the FI signal 280. However, if only the first compare enable command register 322 is written with a value indicating a comparison to be performed, the controller 335 asserts the enable first compare signal 341 to a logic state (e.g., logic high) upon the occurrence of a clock edge to latch 360A (not shown) to enable latch 360A. The digital comparator 330 compares the values ​​in the operand A and B registers 325 and 326 (in some embodiments, flipping a bit of operand B) and outputs a signal 336 indicating whether the comparison was successful or unsuccessful (step 450). If all of the corresponding bits match, digital comparator 330 asserts signal 336 to a first logic state (e.g., logic high), but if any of the corresponding bits do not match, digital comparator 330 asserts signal 336 to a second logic state (e.g., logic low) to indicate that the operands did not match (the "no" branch).

[0028] The "no" branch from decision step 450 results from the comparator output signal 336 being in a logic low state (operand mismatch). In this case, the event generator 380 asserts FI 280 to the MCU 211, which responds by implementing the failure ISR 223 corresponding to the failure event. In the flowchart of FIG. 3, the failure ISR (implemented by the MCU 211) implements, for example, steps 490 and 492. In step 490, the failure interrupt service routine identifies the newly calculated access parameters received in step 410 as part of a potential fault injection attack. The identified access parameters may be stored anywhere in memory within the system 100. In step 492, the failure ISR implements a security access response, which may include, for example, sending a message or signal to the input source that initiated the request to access the target resource 250. The message or signal may, for example, indicate that the input source has been listed on a "deny list," which prevents the system 100 from responding to future resource access requests from the same input source. The input source may be identified by any suitable type of identifier, such as a Globally Unique Identifier (GUID), a serial number, an Internet Protocol (IP) address (or other type of address), etc.

[0029] However, the operands may match as detected by digital comparator 330. MCU 211 reads status register 329 updated by controller 335 to indicate success of the first comparison operation. If MCU 211 determines that the first comparison was successful ("Yes" branch from decision step 450), the method includes, at step 430, MCU 211 implementing a random delay, which may be the same or a different length as the delay.

[0030] In step 482, the method includes performing a comparison between two values. One value may be the received access parameter (from step 410) and the other value may be a pre-set access parameter (hence the same two access parameters compared in step 440). However, the value compared in step 482 may be a different value than the value compared in step 440.

[0031] In one embodiment, step 482 is performed by MCU 211 executing firmware that is not part of the interrupt service routine. In one example, MCU 211 writes values ​​to be compared for the second compare operation to operand registers 325 and 326 (e.g., overwriting the access parameters written therein in step 440). As described above, MCU 211 may bitwise invert the value to be written to operand A register 325 before writing the inverted value to the register. MCU 211 may also write the other value (not inverted) to operand B register 326. As part of step 482, MCU 211 may also write a value to second compare enable command register 323 to trigger controller 335 of HW CMP 213 to perform the second compare operation.

[0032] At this point in the process flow, the controller 335 is in a state where it expects the second compare enable command register to be written to enable a second comparison operation. If the first or third compare enable command registers are written to enable their respective commands, the controller 335 responds by asserting the fail interrupt signal 280. However, if only the second compare enable command register 323 is written with a value indicating a comparison to be performed, the controller 335 asserts the enable second compare signal 342 to a logic state (e.g., logic high) to enable latch 360B via AND gate 370B, as described further below. As described above, the digital comparator 330 compares the values ​​in the operand A and B registers 325 and 326 (in some embodiments, inverting the bit of operand B) and outputs a signal 336 indicating whether this second comparison was successful or unsuccessful. If all of the corresponding bits match, digital comparator 330 asserts signal 336 to a first logic state (e.g., logic high), but if any of the corresponding bits do not match, digital comparator 330 asserts signal 336 to a second logic state (e.g., logic low) to indicate that the operands did not match.

[0033] If the first comparison is successful, comparator output signal 336 will be a logic one, which is latched via latch 360A in response to assertion by controller 335 of enabled first compare signal 341. In response to second compare enable command register 323 containing a value indicating a second comparison to be performed, the controller asserts enabled second compare signal 342. At that point, both inputs to AND gate 370A are logic high, and latch 360B latches the output signal 336 of digital comparator 330 (which will be a logic one if operands A and B match).

[0034] Control proceeds to step 455, where the method determines whether the second comparison was successful or unsuccessful (the first comparison was made at decision step 450). If the second comparison was unsuccessful (e.g., operands A and B did not match), the event generator 380 asserts the failure interrupt signal 280 and the failure ISR is executed by the MCU 211 (steps 490 and 492, as described above). If the second comparison was successful, the event generator 380 asserts the success interrupt signal 230 to the MCU 211, which responds by executing the success ISR 222.

[0035] 3, the Success ISR (executed by MCU 211) in one embodiment performs steps 470 through 476. In step 470, the Success ISR performs a random delay as described above.

[0036] In step 472, the success ISR enables the third comparison to be performed. This step may be performed by the success ISR programming the third compare enable command register 324 and the operand A and B registers 325 and 326, as described above. The values ​​programmed into the operand registers may be the same values ​​as in the first and / or second compare operations, or may be different values. As described above, one value may be an inverted version of a value. The value written to the third compare enable command register 324 indicates to the controller 335 that a third compare operation should be performed. If the first two compare operations are done in order and both comparisons are successful, the controller 335 is in a state where it expects the third compare to be started. If the controller 335 is not in that state when the third compare enable command register is written with a value to initiate a comparison, the controller 335 asserts a failure signal 345 to the event generator 380, which asserts a failure interrupt signal 280, as described above, to terminate the success ISR and instantiate execution of the failure ISR.

[0037] Assuming the first two comparison operations are successful, the second result output signal 364 from latch 360B will be a logic high. Controller 335 also responds to the value written to third compare enable command register 324 by asserting enable third compare signal 343, so both inputs to AND gate 370B will be a logic high. Latch 360C is then enabled and comparator output signal 336 is latched by latch 360C as third result signal 366. Third result signal 366 will be a logic high if the two values ​​compared by digital comparator 330 were the same (taking into account possible inversions as discussed above). If the two values ​​are different, the third result signal will be a logic low.

[0038] The third result signal 366 is coupled to a read enable bit 373 in the scratch pad register 327. The scratch pad register 327 could not be read if the MCU initially cleared the state of the HW CMP 213 before the first comparison was performed. If the third result signal 366 is a logic high, the scratch pad register 327 is enabled to be read, otherwise the scratch pad register is not enabled to be read. The third result signal 366 may also be provided as an input to a signal generator 390.

[0039] In step 474, the success ISR attempts to read the scratchpad register 327. If the third comparison fails, the scratchpad register is not readable, thereby preventing access to the target resource 250. If the third comparison succeeds, the scratchpad register 327 is readable and the success ISR reads the value of the scratchpad register. The value in the scratchpad register 327 may be an identifier of the resource 250 to be enabled. In step 476, the success ISR enables the target resource, for example, by asserting a corresponding enable signal 209 (FIG. 1).

[0040] In an alternative embodiment, rather than the success ISR (MCU 211) reading the scratchpad register 327 and asserting the enable signal 209 to the target resource 250, the success ISR programs the third compare enable command and operand registers 323-326 as described above, and a signal generator 390 in the HW CMP 213 asserts the correct enable signal 207. Multiple enable signals 207 are shown in FIG. 3, with each enable signal enabling a different resource. In this embodiment, a logic high assertion (compare success) of the third result signal 366 enables the scratchpad register 327 to be read, thereby providing the value in the scratchpad register to the signal generator 390. The signal generator 390 then asserts the enable signal 207 corresponding to the value from the scratchpad register.

[0041] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, (A) in a first example, device A is coupled to device B by a direct connection, where device A generates a signal that controls device B to perform an action, or (b) in a second example, device A is coupled to device B via an intervening component C, where intervening component C does not change the functional relationship between device A and device B, and device B is controlled by device A via a control signal generated by device A.

[0042] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by a manufacturer to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through the firmware and / or software programming of the device, through the configuration and / or layout of the hardware components, through the device's interconnections, or through a combination thereof.

[0043] Modifications may be made to the illustrative embodiments described, and other embodiments are possible, within the scope of the claims of the invention.

Claims

1. A method comprising: obtaining a first value and a second value, both associated with accessing a computer resource; performing a first comparison of the first value with the second value; performing a second comparison of the first value with the second value based on the first comparison indicating that the first value matches the second value, and determining whether to generate a signal to trigger a first interrupt service routine (ISR) or a second interrupt service routine (ISR) based on the second comparison indicating whether the first value matches the second value; A method comprising:

2. A method according to claim 1, The method further comprising implementing a delay lasting a random amount of time before performing the first comparison.

3. A method according to claim 1, The method further comprising implementing a delay lasting a random amount of time before performing the second comparison.

4. The method of claim 1, The method further includes determining to generate a signal to trigger the first ISR based on the second comparison indicating that the first value matches the second value.

5. The method according to claim 4, The method further comprising enabling, by the first ISR, a third comparison of the first value with the second value.

6. The method according to claim 5, The method further comprising accessing, by the first ISR, a register to determine whether to enable access to the computer resource.

7. The method of claim 6, accessing a register by the first ISR is permitted based on the third comparison indicating that the first value matches the second value.

8. The method of claim 1, determining to generate the signal to trigger the second ISR based on the second comparison indicating that the first value does not match the second value.

9. The method according to claim 8, The method further comprising disabling access to the computer resource by the second ISR.

10. The method of claim 1, The method, wherein the first value comprises a digital signature associated with access to the computer resource, and the second value comprises a previously validated digital signature associated with access to the computer resource.

11. A system comprising:

1. A comparator circuit comprising: obtaining a first value and a second value, both associated with access to a computer resource; performing a first comparison of the first value with the second value; performing a second comparison of the first value with the second value based on the first comparison indicating that the first value matches the second value, and determining whether to trigger a first interrupt service routine (ISR) or a second interrupt service routine (ISR) based on the second comparison indicating whether the first value matches the second value. a comparator circuit configured to:

12. The system of claim 11, The system, wherein the comparator circuit is further configured to perform the first comparison after a delay.

13. The system of claim 11, The system, wherein the comparator circuit is further configured to perform the second comparison after a delay.

14. The system of claim 11, The system, wherein the comparator circuit is further configured to determine to trigger the first ISR based on the second comparison indicating that the first value matches the second value.

15. The system of claim 14, The system further includes a microcontroller configured to service the first ISR to enable a third comparison of the first value with the second value.

16. The system of claim 15, The system, wherein the comparator circuit is further configured to perform a third comparison of the first value with the second value.

17. The system of claim 16, the comparator circuit is further configured to determine whether to allow the first ISR access to the register based on whether the third comparison indicates that the first value matches the second value.

18. The system of claim 17, The system, wherein the microcontroller is further configured to enable access to the computer resource based on the first ISR being permitted to access the register.

19. The system of claim 11, The system, wherein the comparator circuit is further configured to determine to trigger the second ISR based on the second comparison indicating that the first value does not match the second value.

20. The system of claim 19, The system further includes a microcontroller configured to service the second ISR to disable access to the computer resource.

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