COMMUNICATION METHOD FOR A VEHICLE COMMUNICATION NETWORK AND COMMUNICATION NETWORK - Patent application

Abstract

An apparatus and method are provided that are adapted to overcome each of the above-mentioned shortcomings of the prior art. A communication method for a vehicle communication network (14), comprising: a master data processing unit 10; a slave data processing unit 11 connected to the master data processing unit 10 via a synchronous serial communication interface; Including, the slave data processing unit 11 is connected to the master data processing unit 10 via a slave select line SS for indicating that data 17 are to be sent from the master data processing unit 10 to the slave data processing unit 11; The data 17 transmitted from the master data processing unit 10 to the slave data processing unit 11 and / or from the slave data processing unit 11 to the master data processing unit 10 is surrounded by a start bit S and a stop bit E of the transmitted data 17 .

Description

[Technical field]

[0001] The present disclosure relates to a communication method for a vehicle and a communication system configured to at least partially perform said method.A partially automated vehicle may be provided that includes a communication network. [Background technology]

[0002] A System on Chip or Chip or System on a Chip (SoC) is a highly advanced microcontroller with limited ports that uses the SPI (Serial Peripheral Interface) protocol for communication for high priority tasks.

[0003] One problem with the prior art is that when these ports are used for heartbeat monitoring, other tasks with higher priority may not be able to be executed using these ports or the CPU (Central Processing Unit) may be heavily loaded. That is, one problem with the prior art is that when using a communication protocol such as SPI, monitoring different slave SoCs through one monitoring SoC requires multiple monitoring ports in the monitoring SoC. This places more load on the CPU in the monitoring SoC and may cause data processing and / or cross communication between ports or even short circuits between physical pins / ports of the monitoring SoC. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 4,816,996 Summary of the Invention [Problem to be solved by the invention]

[0005] In view of the prior art, it is an object of the present disclosure to provide an apparatus and method adapted to overcome at least each of the above-mentioned shortcomings of the prior art. [Means for solving the problem]

[0006] The object is solved by the features of the independent claims. The dependent claims have as their subject matter further preferred embodiments of the present disclosure.

[0007] More specifically, the problem is solved by a communication method for a vehicle communication network, the network including a master data processing unit and a slave data processing unit connected to the master data processing unit via a synchronous serial communication interface, the slave data processing unit being connectable to the master data processing unit via a slave select line for indicating that data is to be transmitted from the master data processing unit to the slave data processing unit.

[0008] The master data processing unit and / or the slave data processing unit may be or include an SoC. An SoC is an integrated circuit (also known as a "chip") that integrates all or most of the components of a computer or other electronic system. These components may include a central processing unit (CPU), memory, input / output ports and secondary storage, and optionally other components such as a graphic processing unit (GPU), all on a single substrate or microchip. An SoC may include digital signal processor functionality, analog signal processor functionality, mixed signal processor functionality, and / or radio frequency signal processor functionality. An SoC differs from the typical traditional motherboard-based PC architecture, which separates components based on functionality and connects them by a central interface circuit board. While a motherboard houses and connects removable or replaceable components, an SoC integrates all these components into a single integrated circuit.

[0009] According to the method, data transmitted from the master data processing unit to the slave data processing unit and from the slave data processing unit to the master data processing unit are surrounded by a start bit as the first bit of the transmitted data and a stop bit as the last bit, where the data transmitted during one cycle (frame) can have a certain length, for example 8 bits (i.e. 1 byte), 10 bits, 12 bits or 16 bits.

[0010] More specifically, the master data-handling unit and the slave data-handling unit may be SPI devices, SPI being a synchronous serial communication interface specification used primarily for short distance communication in embedded systems. SPI devices can communicate in full duplex mode using a master-slave architecture, usually with a single master. The master (controller / data-handling) device generates the read and write frames. Multiple slave devices can be supported by selection via individual chip select (CS) or slave select (SS) lines. In an independent slave configuration, there is an independent chip select line for each slave. The master asserts only one chip select at a time. Some products that implement SPI can be connected in a daisy-chain configuration, with the output of a first slave connected to the input of a second slave, and so on. The SPI port of each slave is configured to transmit an exact copy of the data received during the first group of clock pulses during the second group of clock pulses. The whole chain acts as a communication shift register, and the daisy-chain is often done by shift registers to provide a bank of inputs or outputs by SPI. Each slave copies the input to its output on the next clock cycle until the active-low SS line goes high. Such a feature simply requires a single SS line from the master rather than separate SS lines to each slave. Both configurations are possible here.

[0011] As a synchronous serial communication interface, SPI does not use start and stop bits to indicate the beginning and end of transmitted data, but uses a slave select line to select the connection of one slave to the master respectively. However, start and stop bits are used when using Universal Asynchronous Receiver / Transmitter (UART), a computer hardware for asynchronous serial communication interface with configurable data format and transmission speed. UART transmits data bits one by one from least significant bit to most significant bit, surrounded (framed) by start and stop bits so that precise timing is handled by the communication channel. Here, related devices, namely Universal Synchronous Receiver / Transmitter and Universal Asynchronous Receiver / Transmitter (USART), which support synchronous operation, can also be provided.

[0012] However, it is possible to provide interoperability between devices using asynchronous communication (e.g. UART) and master and slave data processing devices by adding a start bit and a stop bit to each data (frame or packet) transmitted using synchronous communication (e.g. SPI).

[0013] More specifically, a UART typically receives bytes of data and transmits individual bits sequentially. At the destination, a second UART reassembles the bits into a complete byte. Each UART contains a shift register, which is the basic method of conversion between serial and parallel formats. Serial transmission of digital information (bits) over a single wire or other medium is less expensive than parallel transmission over multiple wires. Communication can be unidirectional (one-way only, with no ability for the receiving device to send information back to the transmitting device), full duplex (both devices transmit and receive at the same time) or half duplex (devices transmit and receive alternately). In a UART, the idle, no data state is when a high voltage or power is applied. Each character / data packet is framed (framed) with a logic low start bit, data bits, possibly a parity bit, and one or more stop bits. The start bit informs the receiving device that a new character is coming. The next optional 5 to 9 bits represent the character depending on the code set employed. If a parity bit is used, it is placed after every data bit. The next one or two bits are always in a mark (logic high or "1") state and are called the stop bits. These bits tell the receiving device that the character is complete. Because the start bit is a logic low (or "0") and the stop bit is a logic high (or "1"), there are always at least two guaranteed signal transitions between characters.

[0014] In this case, the sending device is not a UART but an SPI device that simulates start and stop bits so that the UART can identify the beginning and end of transmitted data, therefore the start and stop bits can be called dummy bits.

[0015] UART has the advantage of requiring only one wire for single data transmission and two wires (plus ground) for dual data transmission, whereas SPI requires four wires, thus reducing the number of wires and therefore the number of pins required at the receiving device.

[0016] In the following, the above mentioned method will be explained in more detail.

[0017] The slave data processing unit can be connected to the master data processing unit via a serial clock line for synchronizing the sampling time of the master data processing unit with the sampling time of the slave data processing unit and a master-out-slave-in data line for data output from the master data processing unit to the slave data processing unit.

[0018] Here, sampling is the reduction of the continuous-time signal received at each device (i.e., data transmitted over MOSI and / or MSIO) to a discrete-time signal. The sampling time is the point in time at which a sample is obtained from the continuous-time signal at the receiving device. The original (continuous-time) signal can be extracted from the series of samples up to the Nyquist limit by passing the series of samples through a low-pass filter called the reconstruction filter.

[0019] The method may include indicating that data is to be transmitted from the master data handling unit to the slave data handling unit using a slave select line, for example by pulling the slave select line from high to low.

[0020] The method may include synchronizing a sampling time of the master data processing unit with a sampling time of the slave data processing unit using the serial clock line after and / or during an indication that data is to be transmitted from the master data processing unit to the slave data processing unit.

[0021] The method may include transmitting data from the master data processing unit to the slave data processing unit using a Master-Out-Slave-In data line (i.e. MOSI) after and / or during synchronisation of a sampling time of the master data processing unit with a sampling time of the slave data processing unit.

[0022] The slave data processing units can be connected to the master data processing unit via a master-in-slave-out data line (i.e., MISO) for data output from the slave data processing units to the master data processing unit.

[0023] The method may include transmitting data from the slave data processing unit to the master data processing unit using the master-in-slave-out data line after and / or during synchronisation of a sampling time of the master data processing unit with a sampling time of the slave data processing unit.

[0024] More specifically, in the case of SPI, to start communication, the (bus) master sets the clock with a frequency supported by the slave device, typically up to a few MHz. The master then selects the slave device with a logic level 0 on the select line, as described above. If a wait period is required, such as an analog-to-digital conversion, the master can wait this period before generating a clock cycle.

[0025] During each SPI clock cycle, full-duplex data transmission can occur: the master can transmit a bit on the MOSI line and the slave can read it, while the slave can transmit a bit on the MISO line and the master can read it. This sequence is maintained even when unidirectional data transmission is intended.

[0026] Typically, a transmission using SPI involves two shift registers, one in the master and one in the slave, of some predefined word size, such as 8 bits, connected in a virtual ring topology. Typically, data is shifted out most significant bit first. On a clock edge, both the master and slave can shift out a bit and output it to the other on the transmission lines (i.e., MISO and MOSI). On the next clock edge, at each receiving device, a bit can be sampled from the transmission line and set as the new least significant bit of each shift register. After all register bits have been shifted out and in, the master and slave have exchanged register values. If more data needs to be exchanged, the shift registers can be reloaded and the process repeated. In this case, each shift register is optionally loaded with a start bit as the most significant bit and a stop bit as the least significant bit on each cycle. The transmission can continue for any number of clock cycles. Once complete, the master stops toggling the clock signal and typically deselects the slave using the slave select line.

[0027] The network may include a supervisory data processing unit including an asynchronous serial communication interface, the supervisory data processing unit being connectable to the master data processing unit and the slave data processing unit via the asynchronous serial communication interface.

[0028] According to this method, the monitoring device recognizes the start of the transmission data using the start bit, and recognizes the end of the transmission data using the stop bit.

[0029] That is, the monitoring device may include a UART that acts as a (second) receiving device for signals transmitted from the master to the slave and / or vice versa.

[0030] More specifically, the supervisory data processing unit can be connected to a master-out slave-in data line.

[0031] According to the method, the monitoring device can use the start bit to recognize the start of data transmitted from the master data processing unit to the slave data processing unit via the master-out-slave-in data line, and can use the stop bit to recognize the end of data transmitted from the master data processing unit to the slave data processing unit via the master-out-slave-in data line.

[0032] Additionally or alternatively, the supervisory data processing unit may be connected to the master-in-slave-out data line.

[0033] According to the method, the monitoring device can use the start bit to recognize the start of data transmitted from the slave data processing unit to the master data processing unit via the master-in-slave-out data line, and can use the stop bit to recognize the end of data transmitted from the slave data processing unit to the master data processing unit via the master-in-slave-out data line.

[0034] More specifically, and with regard to UARTs, all operations of the UART hardware can be controlled by an internal clock signal that runs at a multiple of the data rate used for data transmission, typically 8 or 16 times the bit rate. The receiving device, here a monitor, can test the state of the received signal at each clock pulse looking for the onset of a start bit. If an apparent (apparent) start bit lasts at least 1 / 2 a bit time, it can be valid and indicate the start of a new character. Otherwise it can be considered a spurious pulse and ignored. After waiting a further bit time, the state of the line can be sampled again and the resulting level can be clocked into a shift register. After the number of bit periods required for the character length (typically 5-8 bits as mentioned above) the contents of the shift register can be made available (in parallel) to the receiving system. The UART can set a flag to indicate that new data is available and can also generate a processor interrupt to request that the host processor transmit the received data.

[0035] Communicating UARTs do not share a timing system separate from the communication signal. Typically, a UART resynchronizes its internal clock at every data line change that is not considered a spurious pulse. With timing information obtained in this way, the UART will receive reliably when the transmitting device is transmitting at a slightly different speed than it should. Very simple UARTs do not do this, instead resynchronizing only on the falling edge of the start bit and reading the center of each expected data bit, and the system works if the broadcast data rate is accurate enough to sample the stop bit reliably. Here, both options are possible.

[0036] However, since the UART does not derive a clock signal from the master data processing unit, the UART needs to know the bit rates used by the master and slave so as to sample the data correctly, i.e. the UARTs of the master, slave and monitoring system need to have substantially identical sampling rates.

[0037] The monitoring device is capable of sampling data at the same sampling time as the master data processing unit and the slave data processing unit.

[0038] The monitoring device can perform an automatic bit rate recognition (ABR) function. ABR refers to the process whereby the receiving device (here the monitoring device) determines the speed, code level, start bit, and stop bit of the received data by examining the first character on the UART connection, usually a preselected sign-on character (sync word). ABR allows the receiving device to accept data from a variety of transmitting devices operating at different speeds without having to specify the data rate in advance.

[0039] Additionally, the monitor can store the most recent character while receiving the next character. This "double buffering" gives the receiving computer the entire character transmission time to retrieve the character being received. The monitor can have a small first-in-first-out (FIFO) buffer memory between the receiver shift register and the host system interface. This allows the host processor additional time to process interrupts from the UART and prevents loss of received data at high rates.

[0040] The supervisor may be referred to as a security device. The supervisor and the master data processing unit may be in the same or different SoCs.

[0041] The above method, in other words and with respect to its more specific implementation, can be summarized as follows.

[0042] The background of the disclosure is the creation of a monitoring system using UART (Universal Asynchronous Transmitter-Receiver) communication protocol instead of SPI (Serial Peripheral Interface) protocol to ensure the safety integrity of safety-critical systems such as System-on-Chip (SoC), e.g., in heartbeat monitoring.

[0043] Safety integrity can be defined using Automotive Safety Levels (ASILs), a standardized risk classification scheme defined by ISO 26262-Functional Safety for Road Vehicles. It is an application of the Safety Integrity Levels (SILs) used in IEC 61508 for the automotive industry. The classification helps define the safety requirements necessary to meet the ISO 26262 standard. The ASILs are set by performing a risk analysis of potential hazards, considering the severity, exposure, and controllability of the vehicle's operating situation (scenario). The safety goals for the hazards in turn have ASIL requirements. There are four ASILs identified by the standard: ASIL A, ASIL B, ASIL C, and ASIL D. ASIL D defines the highest integrity requirements for the apparatus / method, and ASIL A defines the lowest integrity requirements. Hazards identified as QM do not define any safety requirements.

[0044] The present disclosure contemplates that there may be multiple slave SoCs that may be monitored by one master SoC and / or one separate supervisory / security SoC.

[0045] The master / safety SoC can be developed according to the ASIL and can provide different monitoring mechanisms like CRC, timeout and heartbeat monitoring to ensure high availability.

[0046] According to the state of the art, a secure SoC monitors the heartbeat of a slave using a SPI (Serial Peripheral Interface) communication protocol on a given port. However, according to the present disclosure, the secure SoC can use a UART (Universal Asynchronous Transmitter / Receiver) communication protocol.

[0047] The UART protocol is an asynchronous serial communications protocol with configurable speed. Asynchronous means that there is no clock signal to synchronize the output bits from the transmitting device to the receiving end of the UART. Therefore, data is sent serially from the transmitting UART to the receiving UART.

[0048] A secure SoC may have only one UART port per slave, and the port may be configured only for receiving information from the respective slave transmit port.

[0049] The UART communication protocol can be modified to ensure a data packet capability similar to that of the SPI communication protocol.

[0050] The SPI communication protocol can be modified to generate UART packets with a start bit, a data frame, and a stop bit. Here, it is possible to configure the UART packet such that the start bit is low (i.e., 0) and the stop bit and bus idle are high (i.e., 1). The stop bits can contain 1, 1.5, or more bits. A parity bit before the stop bit may or may not be used.

[0051] The secure SoC may also be a grandmaster with multiple SoCs in a master and slave SoC configuration.

[0052] The master and slave SoCs can communicate with each other using "MOSI" and "MISO". The grandmaster SoC can monitor the heartbeat at ASIL using UART "RX" which directly reads "MOSI" and "MISO" of the master and slave SoCs.

[0053] The communication between the Master SC and Slave SC and to the Grandmaster secure SoC can be protected with end-to-end (E2E) protection, such as a Cyclic Redundancy Check (CRC), to ensure that no corruption of the data frames of the data packets occurs.

[0054] It is possible to ensure that the reading of the bits in the UART data frame has the same frequency / baud rate as the SPI protocol, i.e. the same sampling time can be used.

[0055] Further provided is a communication network for a vehicle, the communication network being capable of being configured to at least partially perform the method described above.

[0056] The network includes a master data processing unit and slave data processing units connected to the master data processing unit via a synchronous serial communications interface.

[0057] The slave data-handling unit is connected to the master data-handling unit via a slave select line to indicate that data is to be transmitted from the master data-handling unit to the slave data-handling unit.

[0058] The master data processing unit is arranged so that data transmitted from the master data processing unit to the slave data processing unit is surrounded by a start bit as the first bit of the transmitted data and a stop bit as the last bit.

[0059] Additionally or alternatively, the slave data processing unit is configured to surround data transmitted from the slave data processing unit to the master data processing unit with a start bit as the first bit and a stop bit as the last bit of the transmitted data.

[0060] In the following, the above mentioned communication networks are described in more detail.

[0061] The slave data processing unit can be connected to the master data processing unit via a serial clock line for synchronizing the sampling time of the master data processing unit with the sampling time of the slave data processing unit and a master-out-slave-in data line for data output from the master data processing unit to the slave data processing unit.

[0062] The master data handling unit can be configured to use the slave select line to indicate that data is to be transmitted from the master data handling unit to the slave data handling unit.

[0063] The master data processing unit can be configured to use the serial clock line to synchronize the sampling time of the master data processing unit (i.e. the time at which each unit samples / reads the signal received via the data line) with the sampling time of the slave data processing unit after and / or during the indication that data is to be transmitted from the master data processing unit to the slave data processing unit.

[0064] The master data processing unit may be configured to transmit data from the master data processing unit to the slave data processing unit using the master-out-slave-in data line after and / or during synchronization of the sampling time of the master data processing unit with the sampling time of the slave data processing unit.

[0065] Additionally or alternatively, the slave data processing unit may be connected to the master data processing unit via a master-in-slave-out data line for data output from the slave data processing unit to the master data processing unit.

[0066] The slave data processing unit may be configured to transmit data from the slave data processing unit to the master data processing unit using the master-in-slave-out data line after and / or during synchronization of the sampling time of the master data processing unit with the sampling time of the slave data processing unit.

[0067] The network may include a supervisory data processing unit including an asynchronous serial communication interface, the supervisory data processing unit being connected to the master data processing unit and the slave data processing unit via the asynchronous serial communication interface.

[0068] The monitoring device can recognize the start of the transmission data using the start bit, and can recognize the end of the transmission data using the stop bit.

[0069] The monitoring data processing unit can be connected to the master-out slave-in data line.

[0070] The monitoring device can be configured to use the start bit to recognize the start of data transmitted from the master data processing unit to the slave data processing unit via the master-out-slave-in data line and to use the stop bit to recognize the end of data transmitted from the master data processing unit to the slave data processing unit via the master-out-slave-in data line.

[0071] Additionally or alternatively, the supervisory data processing unit may be connected to the master-in-slave-out data line.

[0072] The monitoring device can be configured to use the start bit to recognize the start of data transmitted from the slave data processing unit to the master data processing unit via the master-in-slave-out data line, and to use the stop bit to recognize the end of data transmitted from the slave data processing unit to the master data processing unit via the master-in-slave-out data line.

[0073] The monitoring device can be configured to sample data at the same sampling times as the master data processing unit and the slave data processing unit.

[0074] The communication network may include electronic control units (ECUs) and / or SoCs for the vehicle as master data processing units, slave data processing units and / or supervisory data processing units. The data processing units may optionally be (intelligent) processor control units that can communicate with other modules, optionally via a central gateway (CGW). The data processing units, optionally together with a telematics control unit, may form part of the vehicle's on-board network, including field buses such as CAN bus, LIN bus, MOST bus, FlexRay or automotive Ethernet. The data processing units may be configured to control functions related to the driving behavior of the vehicle, such as engine control systems, power transmission, braking systems and / or tire pressure control systems. In addition, some or all of the driver assist systems, such as parking assist, adaptive cruise control, lane departure warning, lane change assist, traffic sign recognition, signal light recognition, approach assist, night vision assist, intersection assist and / or many others, may be controlled by the data processing units.

[0075] Moreover, the above description of the method applies mutatis mutandis to the network and vice versa.

[0076] Further provided is a vehicle, the vehicle including a data communication network as described above.

[0077] The vehicle may be a motor vehicle, e.g. a passenger car. The vehicle may be automated. The automated vehicle may be designed to take over lateral and / or longitudinal guiding (driving) at least partially and / or temporarily during automated driving of the automated vehicle. Thus, inter alia, sensor / camera data of the above-mentioned sensor systems / cameras may be used. The control unit may be configured to at least partially control the automated driving.

[0078] Automated driving may be such that the driving of the vehicle is (nearly) autonomous. The vehicle may be an autonomous level 1 vehicle, i.e. it may have certain driver assistance systems, e.g. adaptive cruise control (ACC), that support the driver in operating the vehicle.

[0079] The vehicle may be an autonomous level 2 vehicle, i.e. capable of being partially automated such that functions such as automatic parking, lane keeping or lateral guidance, general longitudinal guidance, acceleration and / or braking are performed by driver assistance systems.

[0080] The vehicle may be an autonomous level 3 vehicle, i.e., capable of being automated such that the driver does not need to continually monitor the system vehicle. The vehicle automatically performs functions such as turn signal activation, lane changing and / or lane keeping. The driver can attend to other matters but is instructed by the system to take over control within a warning period if necessary.

[0081] The vehicle may be an autonomous level 4 vehicle, i.e., the driving of the vehicle may be so highly automated that the driver is permanently taken over by the system vehicle may be requested to take over control when the driving task is no longer handled by the system.

[0082] The vehicle may be an autonomous level 5 vehicle, i.e., fully automated such that a driver is not required to complete the driving task. No human intervention is required other than setting the destination and activating the system. The vehicle can operate without a steering wheel or pedals.

[0083] Furthermore, the above description of the method and network applies mutatis mutandis to the vehicle and vice versa.

[0084] Furthermore, the computer program contains instructions (commands) which, when the program is executed by a computer, optionally a data processing unit, cause the computer to at least partly carry out the above-mentioned method.

[0085] The program may comprise program code, in particular code suitable for a control system of a vehicle. The above descriptions for the method, the control unit and the vehicle apply mutatis mutandis to the computer program and vice versa.

[0086] Additionally, the computer readable medium includes instructions that, when executed by a computer, cause the computer to perform at least part of the method described above.

[0087] The computer readable medium may be any digital data storage device, such as a USB flash drive, a hard disk, a CD-ROM, an SD card, or an SSD card. The above-mentioned computer program can be stored in a computer readable medium. However, the computer program does not necessarily have to be stored in such a computer readable medium, and can also be obtained via the Internet.

[0088] Furthermore, the above descriptions for the method, the control unit, the vehicle and the computer program apply mutatis mutandis to the computer-readable (storage) medium and vice versa.

[0089] Hereinafter, an embodiment will be described with reference to FIGS. [Brief description of the drawings]

[0090] [Figure 1] FIG. 1 is a schematic diagram of an SPI network including a master data processing unit connected to a slave data processing unit and a supervisory data processing unit according to the prior art; [Diagram 2] FIG. 1 shows a schematic diagram of a communication network including a master data processing unit connected to a slave data processing unit and a supervisory data processing unit according to the present disclosure; [Diagram 3] FIG. 3 shows a schematic diagram of a communication protocol used for communication between a master data processing unit and a monitored data processing unit in the network of FIG. 2; [Figure 4] FIG. 3 shows a flowchart of a communication method for use in the communication network of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0091] An embodiment is described below with reference to Figures 1 to 4, where the same reference numerals are used for the same objects throughout the description of the figures, and the embodiment is merely one example for implementing the present disclosure and does not limit the scope of the present disclosure as defined by the claims.

[0092] The flowchart of FIG. 4 should not be construed as indicating a strict order for steps S1-S3, and steps S1-S3 can be performed in any order that is technically reasonable (e.g., at least partially simultaneously).

[0093] The '1999 patent shows and describes a network 14' having a Serial Peripheral Interface (SPI), which is illustrated in Figure 1 and in which the SPI is used, which can be described as a synchronous four-wire serial interface.

[0094] A master device / data processing unit 10' such as a microcomputer (MCU) or system on chip (SoC) and a slave device / data processing unit 11' such as an analog to digital converter or similar peripheral device or system on chip (SoC) communicate using their respective SPI interfaces.

[0095] In master device 10', the SPI interface includes a master shift register 12' and a clock generator 13'. The least significant bit of shift register 12' has an input connected to a pin labeled MISO (master in / slave out or master-in-slave-out) and the most significant bit of shift register 12' has an output connected to a pin labeled MOSI (master out / slave in or master-out-slave-in) of master device 10'. The output of clock generator 13' is connected to the clock input of shift register 12' of master device 10 and to a pin labeled (for slave clock) of master device 10'.

[0096] The SPI interface of slave device 11' (there can be more than one slave device 11' associated with one master device 10') includes a slave shift register 15'. The least significant bit of slave shift register 15' has an input connected to a pin labeled MOSI and the most significant bit of shift register 15' has an output connected to a pin labeled MISO of slave device 11'. The clock input of slave shift register 15' is connected to a pin labeled SCK of slave device 11' which is connected to a pin labeled SCK of master device 10'.

[0097] The MOSI, MISO and SCK of the master device 10' and the slave device 11' are connected to each other. In addition, one or more slave / chip select lines SS are provided for transmitting one or more chip select signals from the master device 10' to the slave device 11' to enable selection of the (respective) slave device 11'. Both the master device 10' and the slave device 11' have data paths for inputting data to be transmitted to the respective shift registers 12', 15' and for reading data received from the respective shift registers 12', 15'.

[0098] Furthermore, a monitoring device 16', optionally an SoC, is provided, which includes the above-mentioned SPI interface of the slave device 11', including the MOSI port / pin, MISO port / pin and SCK port / pin connected to the MOSI port, MISO port and SCK port of the master device 10' and the slave device 11', and also a shift register 161' for the MOSI data line and a shift register 162' for the MSIO data line, connected to the SCK port of the master device 10'. The monitoring device 16' is also connected to the chip select line, labeled SS, of each slave device 11'. The monitoring device 16' performs a liveness monitoring of the master device 10' and the slave device 11' using the SPI interface, i.e. checks whether data is exchanged periodically between the master device 10' and the slave device 11' and / or whether the exchanged data is correct and / or valid.

[0099] The main drawback of the SPI interface as described above when used in health monitoring is that a relatively large number of pins / ports are required in the monitoring device 16', i.e. at least three, four or more pins, to perform health monitoring for one slave device 11'.

[0100] Thus, as can be seen from Figures 2 to 4, a new communication method for a vehicle communication network 14 (not shown) is provided, with Figure 2 showing the communication network 14 in a schematic manner and Figure 3 showing data packets exchanged in the network 14 of Figure 2 using the method shown in Figure 4. The network includes master devices 10, slave devices 11 and monitoring devices 16, as in network 14' of Figure 1, and corresponding parts of network 14 are indicated by the same reference numerals as in network 14' of Figure 1, but without apostrophes. The above description of Figure 1 also applies to network 14 shown in Figure 2, unless otherwise stated.

[0101] The network 14 includes a master data processing unit 10 and a slave data processing unit 11 connected to the master data processing unit 10 via its SPI.

[0102] More specifically, the slave data processing unit 11 is connected to the master data processing unit via a slave select line labelled by SS for indicating that data is to be sent from the master data processing unit 10 to the slave data processing unit 11, a serial clock line labelled by SCK for synchronising the sampling time of the master data processing unit 10 with the sampling time of the slave data processing unit 11, a master-out-slave-in data line labelled by MOSI for data output from the master data processing unit 10 to the slave data processing unit 11 and a master-in-slave-out data line labelled by MISO for data output from the slave data processing unit 11 to the master data processing unit 10.

[0103] The network 14 includes a supervisor / supervised data processing unit 16 connected to the master data processing unit 10 and the slave data processing unit 11. The supervisory data processing unit 16 therefore includes an asynchronous serial communication interface.

[0104] More specifically, the asynchronous serial communication interface of the monitoring device 16 includes two input ports, each labeled UART Rx, and two shift registers 161, 162, each connected at its input side to one of the input ports of the monitoring device 16. One of the input ports labeled UART Rx is connected to the master-out-slave-in data line labeled MOSI, and the other input port labeled UART Rx is connected to the master-in-slave-out data line labeled MISO. Data transmitted from the master device 10 (via MOSI) to the slave device 11 and from the slave device 11 to the master device 10 (via MISO) are received in the monitoring device 16 via the two input ports and written into one of the shift registers 161, 162 of the monitoring device 16, respectively. The asynchronous serial communications interface of the monitoring device 16 also includes a clock generator 163 (similar to the clock generator 13 of the master device 10) connected to the clock inputs of both shift registers 161, 162 of the monitoring device 16. Both shift registers 161, 162 of the monitoring device 16 have a data path for reading out the received data from each shift register 161, 162.

[0105] The network 14 described above is used in carrying out the method of FIG. 4 as follows:

[0106] In a first step S1 of the method, the master device 10 indicates the start of a communication cycle including the transmission of data from the master device 10 to the slave device 11 and vice versa, by, for example, pulling the slave select line, labeled SS, from an idle / high state (i.e., "1") to a low state (i.e., "0").

[0107] In a second step of the method, the master device 10 and the slave device 11 start transmitting the loaded (optionally preloaded) data packets 17 into their respective shift registers 12, 15 via the master-out-slave-in data line labeled MOSI and the master-in-slave-out data line labeled MISO (so-called duplex communication mode). More specifically, in a second step S2, the transmission of data from the master data processing unit 10 to the slave data processing unit 11 is performed using the master-out-slave-in data line labeled MOSI and the transmission of data from the slave data processing unit 11 to the master data processing unit 10 is performed using the master-in-slave-out data line labeled MISO.

[0108] The data packet 17 is shown in detail in Fig. 3 and includes a start bit (e.g. low / zero) labeled by data S and a stop bit (e.g. by / 1) labeled by E, surrounding (framing) / containing a data byte labeled by F with 8 data bits (it can be more or less than 8, but a data packet should contain a set / predefined number of data bits) labeled by F1 to F8 in between. That is to say, the data (packet) 17 transmitted from the master data processing unit 10 to the slave data processing unit 11 and the data (packet) 17 transmitted from the slave data processing unit 11 to the master data processing unit 10 are surrounded by a start bit labeled by S as the first bit and a stop bit labeled by E as the last bit of the transmitted data (packet) 17.

[0109] Master device 10 and slave device 11 each transmit a data packet 17 beginning with a start bit labeled with S, followed by data bits labeled with F1 through F8, and finally a stop bit labeled with E.

[0110] Both the shift register 12 of the master device 10 and the shift register 15 of the slave device 11 receive the same clock signal from the clock generator 13 of the master device 10 via the serial clock line labelled SCK, at least during the transmission and reception of the data packets 17 in the second step S2 of the method, i.e. by using the same clock signal the sampling times of the master device 10 and the slave device 11 are synchronized with each other.

[0111] More specifically, to start communication in a second step S2, the bus device 10 configures its clock generator 13 with a frequency supported by the slave device 11, typically up to a few MHz, and with a frequency supported by the monitoring device 16, where predefined frequencies can be used. The master device 10 then selects the slave device 11 with a logic level 0 on the select line labelled by SS. If a waiting period such as an analog-to-digital conversion is required, the master device 10 waits at least this period before generating clock cycles using its clock generator 13 and the serial clock line labelled by SCK.

[0112] During each SPI clock cycle, full-duplex data transmission occurs: master device 10 transmits bits on the master-out-slave-in data line labeled MOSI, which is read by slave device 11, while slave device 11 transmits bits on the master-in-slave-out data line labeled MISO, which is read by master device 10. This sequence can be maintained even when unidirectional data transmission is intended.

[0113] Data transmission between the master device 10 and the slave device 11 involves two shift registers 12, 15 in the master device 10 and the slave device 11, both with some predefined word length, such as 10 bits, connected in a virtual ring topology by a master-out-slave-in data line labeled MOSI and a master-in-slave-out data line labeled MISO. Data is shifted out first with the most significant bit, here a start bit labeled S. On a clock edge, both the master device 10 and the slave device 11 shift out a bit and output it to the other on their respective data (transmission) lines (i.e. MISO and MOSI). On the next clock edge, in each receiving device 10, 11, the bit is sampled (extracted) from the transmission line and set as the new least significant bit of each shift register 12, 15. After all register bits have been shifted out and in, the master device 10 and the slave device 11 have exchanged register values. If more data needs to be exchanged, the shift registers 12, 15 are reloaded and the process is repeated. The transmission can continue for any number of clock cycles. Once complete, master device 10 stops toggling the clock signal and typically deselects slave device 11 using the slave select line labeled SS.

[0114] In addition to setting the clock frequency, the master device 10 also configures the clock polarity and clock phase for the data. In SPI, there are two commonly available options: CPOL and CPHA (for clock polarity and clock phase).

[0115] The timing is described below and applies to both the master device 10 and the slave device 11.

[0116] CPOL defines the polarity of the clock. The polarity can be changed by an inverter. CPOL=0 idles at 0 and each cycle consists of a pulse of 1, i.e. the leading edge is a rising edge and the trailing edge is a falling edge. CPOL=1 idles at 1 and each cycle consists of a pulse of 0, i.e. the leading edge is a falling edge and the trailing edge is a rising edge. CPHA defines the timing (i.e. phase) of the data bits with respect to the clock pulse. For CPHA=0, the "out" side changes data at the trailing edge of the previous clock cycle, while the "in" side captures data at (or just after) the leading edge of the clock cycle. The "out" side holds the data valid until the trailing edge of the current clock cycle. For the first cycle, the first bit must be on the MOSI line before the leading edge. An alternative way of considering is that a CPHA=0 cycle consists of a half cycle with an idle clock followed by a half cycle with an asserted (active) clock. For CPHA=1, the "out" side changes data at the leading edge of the current clock cycle, while the "in" side captures data at (or just after) the trailing edge of the clock cycle. The "out" side holds the data valid until the leading edge of the following clock cycle. For the last cycle, the slave holds the MISO line valid until the slave select is deactivated. An alternative way of considering is that a CPHA=1 cycle consists of a half cycle with an asserted clock followed by a half cycle with an idle clock. Normally, the MOSI and MISO signals are stable (at their reception point) for a half cycle until the next clock transition. The SPI master device 11 and the slave device 11 can sample the data well at different points in the half cycle. This allows for more flexibility in the communication channel between the master device 10 and the slave device 11.

[0117] However, regardless of which clock polarity and clock phase are used, the above ensures that master device 10 and slave device 11 sample the received data signal at the correct instant in time, i.e., that master device 10 and slave device 11 use synchronized sampling times (as indicated by the arrows in FIG. 3).

[0118] Monitoring device 16, which may be considered a man-in-the-middle device, also receives the bits labeled S, F1-F8, and E transmitted at its respective input ports labeled UART Rx via the master-in-slave-out data line labeled MISO and the master-out-slave-in data line labeled MOSI. Because monitoring device 16 includes a UART interface (asynchronous communication interface), monitoring device 16 is not connected to the serial clock line labeled SCK and therefore does not receive a clock signal from master device 10. Additionally, monitoring device 16 is not connected to the slave select line labeled SS and therefore does not receive a slave / chip select signal from master device 10.

[0119] However, since each data packet transmitted from the master device 10 to the slave device 11 and vice versa contains a start bit labeled S, the monitoring device 16 is able to recognize the start of the above-mentioned transmission cycle without obtaining a chip select signal. The same applies to the end of the transmission cycle, which can be recognized by the monitoring device 16 using a stop bit labeled E. That is, the monitoring device 16 recognizes the start of the transmitted data using the start bit labeled S and the end of the transmitted data using the stop bit labeled E. So, in a third step of the method, the monitoring device 16 recognizes the start of the data transmitted from the master data processing unit 10 to the slave data processing unit 11 via the master-out-slave-in data line labeled MOSI using the start bit labeled S and recognizes the end of the data transmitted from the master data processing unit 10 to the slave data processing unit 11 via the master-out-slave-in data line labeled MOSI using the stop bit labeled E. The monitoring device 16 uses the start bit labeled S to recognize the beginning of the data transmitted from the slave data processing unit 11 to the master data processing unit 10 via the master-in-slave-out data line labeled MISO, and uses the stop bit labeled E to recognize the end of the data transmitted from the slave data processing unit 11 to the master data processing unit 10 via the master-in-slave-out data line labeled MISO.

[0120] Furthermore, the monitoring device 16 samples data at the same sampling times as the master data processing unit 10 and the slave data processing unit 11 (i.e. samples received data during the same time slots as the slave data processing unit 11 for data transmitted over MOSI and / or samples received data during the same time slots as the master data processing unit 10 for data transmitted over MISO). This is done by sampling data in the monitoring device 16 using a clock generator 163 of the monitoring device 16, which may have the same clock frequency as the clock generator 13 of the master device 10, and optionally according to predefined clock polarity and clock phase used by the master device 10 and the slave device 11. Thus, the monitoring device 16 is not only able to recognize the start and end of a transmission cycle, but also able to accurately read / recognize the data bits labeled with F1 to F8 contained in each data packet labeled with F. [Explanation of symbols]

[0121] 10' Master device (conventional technology) 11' Slave device (conventional technology) 12' Master Shift Register (Prior Art) 13' Master device clock generator (prior art) 14' Communication Network (Prior Art) 15' Slave Shift Register (Conventional Technology) 16' Safety / Monitoring Devices (Conventional Technology) 161' MISO shift register for monitoring device (prior art) 162' MOSI shift register in monitoring device (prior art) 10 Master Device 11 Slave Device 12 Master Shift Register 13 Master device clock generator 14. Communications Networks 15 Slave Shift Register 16 Safety / Monitoring Equipment 161 MISO shift register of monitoring device 162 MOSI shift register of monitoring device 163 Clock generator for monitoring equipment 17 Data Packets MSIO Master-in-slave-out data line MOSI Master-out slave-in data line SS Slave / Chip Select Line SCK Slave Clock Line S Start bit E stop bit F Data Byte F1~F8 data bits S1~S3 Method steps

Claims

1. A communication method for a vehicle communication network (14), comprising: a master data processing unit (10), a slave data processing unit (11) connected to said master data processing unit (10) via a synchronous serial communication interface; Including, - the slave data processing unit (11) is connected to the master data processing unit (10) via a slave select line (SS) for indicating that data (17) is to be sent from the master data processing unit (10) to the slave data processing unit (11), - a method characterized in that the data (17) transmitted from the master data processing unit (10) to the slave data processing unit (11) and / or the data (17) transmitted from the slave data processing unit (11) to the master data processing unit (10) are surrounded by a start bit (S) as the first bit and a stop bit (E) as the last bit of the transmitted data (17).

2. said slave data processing unit (11) a serial clock line (SCK) for synchronizing the sampling times of the master data processing unit (10) and the slave data processing unit (11); a Master Out Slave In data line (MOSI) for data output from the master data processing unit to the slave data processing unit; connected to the master data processing unit (10) via - indicating, using the slave select line (SS), that data (17) is to be sent from the master data processing unit (10) to the slave data processing unit (11); - synchronizing the sampling time of the master data processing unit (10) with the sampling time of the slave data processing unit (11) using the serial clock line (SCK) after and / or during the indication that data (17) is to be sent from the master data processing unit (10) to the slave data processing unit (11); and - transmitting data (17) from the master data processing unit (10) to the slave data processing unit (11) using the Master Out Slave In Data Line (MOSI) after and / or during the synchronization of the sampling time of the master data processing unit (10) with the sampling time of the slave data processing unit (11); 2. The method of claim 1, comprising:

3. - said slave data processing unit (11) is connected to said master data processing unit (10) via a master-in-slave-out data line (MISO) for data output from said slave data processing unit (11) to said master data processing unit (10); transmitting data (17) from the slave data processing unit (10) to the master data processing unit (10) using the master-in-slave-out data line (MISO) after and / or during the synchronization of the sampling time of the master data processing unit (10) with the sampling time of the slave data processing unit (11); 3. The method of claim 2.

4. The network (14) - a supervisory data processing unit (16) including an asynchronous serial communication interface, the supervisory data processing unit (16) is connected to the master data processing unit (10) and the slave data processing unit (11) via the asynchronous serial communication interface, The monitoring data processing unit (16) recognizes the start of the transmission data (17) using the start bit (S) and the end of the transmission data (17) using the stop bit (E). The method according to any one of claims 1 to 3.

5. - said supervisory data processing unit (16) is connected to said Master-Out-Slave-In data line (MOSI); The monitor data processing unit (16) uses the start bit (S) to recognize the start of data (17) transmitted from the master data processing unit (10) to the slave data processing unit (11) via the master-out-slave-in data line (MOSI), and uses the stop bit (E) to recognize the end of data (17) transmitted from the master data processing unit (10) to the slave data processing unit (11) via the master-out-slave-in data line (MOSI).

5. The method according to claim 4, which is dependent on claim 2.

6. - said supervisory data processing unit (16) is connected to said Master-In-Slave-Out data line (MISO); The monitor data processing unit (16) uses the start bit (S) to recognize the start of data (17) transmitted from the slave data processing unit (11) to the master data processing unit (10) via the master-in-slave-out data line (MISO), and uses the stop bit (E) to recognize the end of data (17) transmitted from the slave data processing unit (11) to the master data processing unit (10) via the master-in-slave-out data line (MISO).

5. The method according to claim 4, which is dependent on claim 3.

7. 5. The method according to claim 4, wherein the monitoring data processing unit (16) samples the received data (17) at the same sampling time as the master data processing unit (10) and the slave data processing unit (11).

8. A communication network (14) for a vehicle, the network comprising: a master data processing unit (10), a slave data processing unit (11) connected to said master data processing unit (10) via a synchronous serial communication interface; Including, - in the network, wherein the slave data processing unit (11) is connected to the master data processing unit (10) via a slave select line (SS) for indicating that data (17) is to be sent from the master data processing unit (10) to the slave data processing unit (11), the master data processing unit (10) is configured to surround the data (17) transmitted from it to the slave data processing unit (11) with a start bit (S) as the first bit and a stop bit (E) as the last bit of the transmitted data (17); and / or The slave data processing unit (11) is configured to surround the data (17) transmitted from the slave data processing unit (11) to the master data processing unit (10) with a start bit (S) as the first bit of the transmitted data (17) and a stop bit (E) as the last bit. A network characterized by:

9. said slave data processing unit (11) a serial clock line (SCK) for synchronizing the sampling times of the master data processing unit (10) and the slave data processing unit (11); a Master Out Slave In data line (MOSI) for the data (17) output from said master data processing unit to said slave data processing unit (11); connected to the master data processing unit (10) via the master data processing unit (10) is configured to indicate, using the slave select line (SS), that data (17) is to be sent from the master data processing unit (10) to the slave data processing unit (11); the master data processing unit (10) is configured to synchronize the sampling time of the master data processing unit (10) with the sampling time of the slave data processing unit (11) using the serial clock line (SCK) after and / or while indicating that data (17) is to be transmitted from the master data processing unit (10) to the slave data processing unit (11); and the master data processing unit (10) is configured to transmit data (17) from the master data processing unit (10) to the slave data processing unit (11) using the Master-Out-Slave-In Data Line (MOSI) after and / or during synchronization of the sampling time of the master data processing unit (10) with the sampling time of the slave data processing unit (11); 9. The network (14) according to claim 8, characterized in that

10. - said slave data processing unit (11) is connected to said master data processing unit (10) via a master-in-slave-out data line (MISO) for data output from said slave data processing unit (11) to said master data processing unit (10); the slave data processing unit (11) is configured to transmit data (17) from the slave data processing unit (10) to the master data processing unit (10) using the master-in-slave-out data line (MISO) after and / or during the synchronization of the sampling time of the master data processing unit (10) with the sampling time of the slave data processing unit (11); 10. The network (14) according to claim 9.

11. The network - a supervisory data processing unit (16) including an asynchronous serial communication interface, the supervisory data processing unit (16) is connected to the master data processing unit (10) and the slave data processing unit (11) via the asynchronous serial communication interface, The monitoring data processing unit (16) is configured to recognize the start of transmission data using the start bit (S) and the end of transmission data using the stop bit (E). A network (14) according to any one of claims 8 to 10.

12. - said supervisory data processing unit (16) is connected to said Master-Out-Slave-In data line (MOSI); The monitor data processing unit (16) is configured to recognize, using the start bit (S), the start of data (17) transmitted from the master data processing unit (10) to the slave data processing unit (11) via the master-out-slave-in data line (MOSI), and to recognize, using the stop bit (E), the end of data transmitted from the master data processing unit (10) to the slave data processing unit (11) via the master-out-slave-in data line (MOSI). Network (14) according to claim 11, which is dependent on claim 9.

13. - said supervisory data processing unit (16) is connected to said Master-In-Slave-Out data line (MISO); The monitor data processing unit (16) is configured to recognize, using the start bit (S), the start of data (17) transmitted from the slave data processing unit (11) to the master data processing unit (10) via the master-in-slave-out data line (MISO), and to recognize, using the stop bit (E), the end of data transmitted from the slave data processing unit (11) to the master data processing unit (10) via the master-in-slave-out data line (MISO). A network (14) according to claim 11, which is dependent on claim 10.

14. The network (14) according to claim 9 or 10, characterized in that the monitoring data processing unit (16) is configured to sample the received data (17) at the same sampling time as the master data processing unit (10) and the slave data processing unit (11).

15. A vehicle, characterized in that it includes a network (14) according to any one of claims 8 to 10.

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