Display device and manufacturing method thereof

Abstract

The display device includes a power supply wiring, a passivation layer disposed on the power supply wiring and having an undercut shape, a first connection electrode disposed inside the undercut shape, a second connection electrode electrically connecting the power supply wiring and the first connection electrode, and a common electrode electrically connected to the power supply wiring by at least one of the first connection electrode and the second connection electrode.

Description

[Technical field]

[0001] The present invention relates to a display device and a method for manufacturing the display device. [Background technology]

[0002] A display device includes a light emitting element, and the light emitting element includes a common electrode formed of a plate electrode. As the size of the display device increases, the size of the common electrode also increases. Also, as the thickness of the display device decreases, the thickness of the common electrode also decreases. For this reason, a structure for preventing a voltage drop of a common voltage provided to the common electrode has been developed. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present invention is to provide a display device.

[0004] Another object of the present invention is to provide a method for manufacturing the display device.

[0005] However, the object of the present invention is not limited to the above object, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Means for solving the problem]

[0006] In order to achieve the above-mentioned object of the present invention, a display device according to one embodiment of the present invention is characterized in including a power supply wiring arranged on a substrate, a passivation layer arranged on the power supply wiring and having an undercut shape, a first connection electrode arranged on the power supply wiring and arranged inside the undercut shape, a second connection electrode arranged on the power supply wiring and electrically connecting the power supply wiring and the first connection electrode, and a common electrode arranged on the second connection electrode and electrically connected to the power supply wiring by at least one of the first connection electrode and the second connection electrode.

[0007] The common electrode overlaps the first connection electrode and the second connection electrode, and is in contact with the first connection electrode and the second connection electrode.

[0008] The common electrode does not contact the power supply wiring.

[0009] The first connection electrode is in contact with the second connection electrode.

[0010] The second connection electrode is in contact with the power supply wiring, the first connection electrode, and the common electrode.

[0011] The display device further includes a light-emitting layer that is interrupted by the undercut feature.

[0012] The light emitting layer is disposed between the second connection electrode and the common electrode.

[0013] The common electrode covers a side surface of the light emitting layer.

[0014] The display device further includes a data wiring arranged in the same layer as the power supply wiring, a first gate electrode arranged in the same layer as the first connection electrode, a cap electrode arranged on the first gate electrode, and a pixel electrode arranged in the same layer as the second connection electrode and in contact with the cap electrode.

[0015] In order to achieve another object of the present invention as described above, a manufacturing method of a display device according to one embodiment of the present invention is characterized in that it includes the steps of forming a power wiring on a substrate, forming a first connection electrode and an etching electrode on the power wiring, forming a preliminary passivation layer on the etching electrode so as to cover the etching electrode, forming a passivation layer so as to expose a side of the etching electrode, removing the etching electrode so that the passivation layer has an undercut shape, forming a second connection electrode electrically connecting the power wiring and the first connection electrode, and forming a common electrode on the second connection electrode, the common electrode being electrically connected to the power wiring by at least one of the first connection electrode and the second connection electrode.

[0016] The etching electrode reacts with a first etchant through the exposed side surface.

[0017] The step of forming the second connection electrode includes a step of forming a spare second connection electrode and a step of etching the spare second connection electrode with a second etchant, the first etchant containing the same material as the second etchant.

[0018] The etching electrode includes copper (Cu), and the spare second connection electrode includes silver (Ag) and indium tin oxide (ITO).

[0019] The first connection electrode contains titanium (Ti).

[0020] The manufacturing method further includes the steps of forming a data wiring together with the power wiring on the substrate, forming a first gate electrode together with the first connection electrode, and forming a cap electrode on the first gate electrode, wherein the passivation layer exposes an upper surface of the cap electrode.

[0021] The etching electrode reacts with a first etchant through the exposed side surface, the second connection electrode reacts with a second etchant, and the cap electrode does not react with the first etchant or the second etchant.

[0022] The first gate electrode comprises titanium, the etch electrode comprises copper, and the cap electrode comprises indium tin oxide (ITO).

[0023] The method further includes forming a light emitting layer such that the light emitting layer is interrupted by the undercut feature.

[0024] The first angle at which the light emitting layer is deposited is greater than the second angle at which the common electrode is deposited. Effect of the Invention

[0025] The display device according to the present invention includes a power supply wiring, a first connection electrode, a second connection electrode, and the common electrode. The common electrode is electrically connected to the power supply wiring via at least one of the first connection electrode and the second connection electrode. This makes it possible to prevent a voltage drop of a common voltage provided to the common electrode.

[0026] In addition, an undercut shape in which the first connection electrode is disposed is formed in the passivation layer overlapping the power wiring. The undercut shape interrupts the light-emitting layer so that the common electrode is electrically connected to the power wiring. The undercut shape is formed by removing an etching electrode, and the etching electrode is etched with the same etchant as that used to etch the pixel electrode. This improves the economic efficiency of the process of forming the undercut shape.

[0027] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Brief description of the drawings]

[0028] [Figure 1] FIG. 1 is a perspective view illustrating a display device according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a block diagram for explaining the display device of FIG. [Diagram 3] FIG. 3 is a circuit diagram illustrating a pixel included in the display device of FIG. [Figure 4] FIG. 4 is a perspective view illustrating a lower structure included in the display device of FIG. [Diagram 5] FIG. 5 is a cross-sectional view illustrating a lower structure included in the display device of FIG. [Figure 6] FIG. 6 is a cross-sectional view illustrating an upper structure included in the display device of FIG. [Figure 7] 7A to 7C are cross-sectional views for explaining a method for manufacturing the lower structure of FIG. [Figure 8] 8A to 8C are cross-sectional views for explaining a method for manufacturing the lower structure of FIG. [Figure 9] 9A to 9C are cross-sectional views for explaining a method for manufacturing the lower structure of FIG. [Figure 10] 10A to 10C are cross-sectional views for explaining a method for manufacturing the lower structure of FIG. [Figure 11] FIG. 11 is a cross-sectional view for explaining a method for manufacturing the lower structure of FIG. [Figure 12] 12A to 12C are cross-sectional views for explaining a method for manufacturing the lower structure of FIG. [Figure 13] FIG. 13 is a cross-sectional view for explaining a method for manufacturing the lower structure of FIG. [Figure 14] FIG. 14 is a cross-sectional view for explaining a method for manufacturing the lower structure of FIG. [Figure 15] FIG. 15 is a cross-sectional view for explaining a method for manufacturing the lower structure of FIG. [Figure 16] 16A to 16C are cross-sectional views for explaining a method for manufacturing the lower structure of FIG. [Figure 17]FIG. 17 is a cross-sectional view for explaining a method for manufacturing the lower structure of FIG. [Figure 18] FIG. 18 is a cross-sectional view for explaining a method for manufacturing the lower structure of FIG. [Figure 19] FIG. 19 is a cross-sectional view illustrating a display device according to another embodiment of the present invention. [Figure 20] FIG. 20 is an enlarged view of region E in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used to refer to the same elements in the drawings, and duplicated descriptions of the same elements will be omitted.

[0030] FIG. 1 is a perspective view illustrating a display device according to an embodiment of the present invention.

[0031] As shown in FIG. 1, a display device DD according to an embodiment of the present invention includes a lower structure LRS and an upper structure UPS.

[0032] The substructure LRS includes at least one light emitting element and is also called a light emitting substrate, and emits light having a predetermined color.

[0033] The upper structure UPS is disposed on the lower structure LRS. The upper structure UPS includes at least one color conversion pattern, and is also called a color conversion substrate. The upper structure UPS converts the color of the light emitted by the lower structure LRS.

[0034] FIG. 2 is a block diagram for explaining the display device of FIG.

[0035] As shown in FIG. 2, the display device DD includes a display panel PNL, a data driver DDV, a gate driver GDV, a control unit CON, and a voltage supply unit VP.

[0036] The display panel PNL includes at least one pixel PX.

[0037] The pixel PX is provided with a first gate signal SC via the first gate line GL1 and a second gate signal SS via the second gate line GL2. The pixel PX is also provided with a data voltage DATA via the data line DL and an initialization voltage VINT via the initialization voltage line VTL. The data voltage DATA is written to the pixel PX in response to the first gate signal SC, and the initialization voltage VINT is written to the pixel PX in response to the second gate signal SS.

[0038] The data driver DDV generates a data voltage DATA based on the output image data ODAT and a data control signal DCTRL provided by the controller CON. For example, the data driver DDV generates a data voltage DATA corresponding to the output image data ODAT and outputs the data voltage DATA in response to the data control signal DCTRL. The data control signal DCTRL includes an output data enable signal, a horizontal start signal, and a load signal.

[0039] The gate driver GDV generates first and second gate signals SC and SS according to a gate control signal GCTRL. For example, the first and second gate signals SC and SS each include a gate-on voltage for turning on a transistor and a gate-off voltage for turning off a transistor. The gate control signal GCTRL includes a vertical start signal, a clock signal, etc.

[0040] The control unit CON (e.g., a timing controller T-CON) receives input image data IDAT and a control signal CTRL from an external host processor (e.g., a GPU). For example, the input image data IDAT is RGB data including red image data, green image data, and blue image data. The control signal CTRL includes a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, and the like. The control unit CON generates a gate control signal GCTRL, a data control signal DCTRL, and an output image data ODAT based on the input image data IDAT and the control signal CTRL.

[0041] The voltage supply unit VP provides the pixels PX with a driving voltage ELVDD, a common voltage ELVSS, and an initialization voltage VINT. The driving voltage ELVDD is provided to the pixels PX via the driving wiring PL. The common voltage ELVSS is provided to the pixels PX via the power supply wiring VL and a common electrode (for example, the common electrode CTE in FIG. 4).

[0042] FIG. 3 is a circuit diagram for explaining a pixel included in the display device of FIG.

[0043] 3, the pixel PX includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor CST. The pixel PX is electrically connected to a light-emitting element LED.

[0044] The first transistor T1 includes a first terminal, a second terminal, and a gate terminal. The first terminal is provided with a driving voltage ELVDD. The second terminal is connected to the light-emitting element LED. The gate terminal disposed between the first terminal and the second terminal is connected to the second transistor T2. The first transistor T1 generates a driving current for the light-emitting element LED according to the driving voltage ELVDD and the data voltage DATA.

[0045] The second transistor T2 includes a first terminal, a second terminal, and a gate terminal. The first terminal is provided with a data voltage DATA. The second terminal is connected to the first transistor T1. The gate terminal disposed between the first terminal and the second terminal is provided with a first gate signal SC. The second transistor T2 transmits the data voltage DATA to the gate terminal of the first transistor T1 in response to the first gate signal SC.

[0046] The third transistor T3 includes a first terminal, a second terminal, and a gate terminal. The first terminal is connected to the second terminal of the first transistor T1. The second terminal is provided with an initialization voltage VINT. The gate terminal disposed between the first terminal and the second terminal is provided with a second gate signal SS. The third transistor T3 transmits the initialization voltage VINT to the second terminal of the first transistor T1 in response to the second gate signal SS.

[0047] The capacitance capacitor CST includes a first terminal and a second terminal. The first terminal is connected to the gate terminal of the first transistor T1 and the second terminal of the second transistor T2. The second terminal is connected to the first terminal of the third transistor T3, the second terminal of the first transistor T1, and the light emitting element LED. The capacitance capacitor CST maintains the voltage level of the gate terminal of the first transistor T1 during the inactive period of the first gate signal SC.

[0048] The light emitting element LED includes a first terminal and a second terminal. The first terminal is connected to the second terminal of the first transistor T1. The second terminal is provided with a common voltage ELVSS. The light emitting element LED emits light having a brightness corresponding to a driving current. The light emitting element LED includes an organic light emitting element using an organic material as a light emitting layer, an inorganic light emitting element using an inorganic material as a light emitting layer, and the like.

[0049] FIG. 4 is a perspective view illustrating a lower structure included in the display device of FIG.

[0050] As shown in FIG. 4, the lower structure LRS included in the display device DD includes a substrate SUB1, a power supply wiring VL, and a common electrode CTE.

[0051] The substrate SUB1 is parallel to a plane formed by a first direction D1 (e.g., the X direction) and a second direction D2 (e.g., the Y direction) intersecting the first direction D1, and has a thickness in a third direction D3 (e.g., the Z direction) perpendicular to the plane.

[0052] The substrate SUB1 includes a transparent or opaque material. In one embodiment, materials used as the substrate SUB1 include glass, quartz, plastic, etc. These may be used alone or in combination with each other.

[0053] The power supply wiring VL is disposed on the substrate SUB1. In one embodiment, the power supply wiring VL extends in the second direction D2 and is spaced apart in the first direction D1. The power supply wiring VL transmits a common voltage ELVSS to the common electrode CTE. The power supply wiring VL can prevent a voltage drop of the common voltage ELVSS.

[0054] In another embodiment, the power supply wiring VL extends in a first direction D1 and is spaced apart in a second direction D2. In another embodiment, the power supply wiring VL includes a first power supply wiring and a second power supply wiring disposed on the first power supply wiring. The first and second power supply wirings cross each other.

[0055] The common electrode CTE is disposed on the power supply line VL. In one embodiment, the common electrode CTE is formed of a plate electrode. The common electrode CTE is provided with a common voltage ELVSS from the power supply line VL. For example, the common electrode CTE corresponds to the second terminal of the light-emitting element LED described in FIG. 3.

[0056] FIG. 5 is a cross-sectional view illustrating a lower structure included in the display device of FIG.

[0057] As shown in FIG. 5, the lower structure LRS includes a substrate SUB1, a lower electrode BML, a data wiring DL, a buffer layer BFR, a first active pattern ACT1, a second active pattern ACT2, a gate insulation pattern GI, a first gate electrode GAT1, a second gate electrode GAT2, a first cap electrode CPE1, a third gate electrode GAT3, a fourth gate electrode GAT4, a second cap electrode CPE2, a first connection electrode CE1, a passivation layer PVX, a via insulation layer VIA, a pixel electrode PE, a first connection wiring CL1, a second connection wiring CL2, a second connection electrode CE2, a pixel definition film PDL, a light emitting layer EL, and a common electrode CTE.

[0058] In one embodiment, the lower electrode BML, the data wiring DL, and the power supply wiring VL are disposed on a substrate SUB1. For example, the lower electrode BML, the data wiring DL, and the power supply wiring VL are formed together. In other words, the lower electrode BML, the data wiring DL, and the power supply wiring VL are disposed in the same layer.

[0059] In one embodiment, the bottom electrode BML, the data line DL, and the power line VL are formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. Materials used for the bottom electrode BML, the data line DL, and the power line VL include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These can be used alone or in combination with each other. In addition, each of the bottom electrode BML, the data line DL, and the power line VL is formed of a single layer or a multilayer.

[0060] In one embodiment, a driving voltage ELVDD is provided to the bottom electrode BML, a data voltage DATA is provided to the data line DL, and a common voltage ELVSS is provided to the power line VL.

[0061] The buffer layer BFR is disposed on the lower electrode BML, the data line DL, and the power line VL. In one embodiment, the buffer layer BFR is made of an insulating material. Examples of insulating materials used as the buffer layer BFR include silicon oxide, silicon nitride, and silicon oxynitride. These materials can be used alone or in combination with each other. The buffer layer BFR can be configured as a single layer or multiple layers.

[0062] The first active pattern ACT1 and the second active pattern ACT2 are disposed on the buffer layer BFR, for example, the first active pattern ACT1 and the second active pattern ACT2 are formed together.

[0063] In an embodiment, the first active pattern ACT1 and the second active pattern ACT2 are formed of a silicon semiconductor material or an oxide semiconductor material. Examples of the silicon semiconductor material used for the first active pattern ACT1 and the second active pattern ACT2 include amorphous silicon and polycrystalline silicon. Examples of the oxide semiconductor material used for the first active pattern ACT1 and the second active pattern ACT2 include IGZO (InGaZnO) and ITZO (InSnZnO). The oxide semiconductor material may further include indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). These may be used alone or in combination with each other.

[0064] In one embodiment, the first active pattern ACT1 is disposed on the bottom electrode BML, overlaps the bottom electrode BML, and is electrically connected to the bottom electrode BML by a first connection wiring CL1. For example, the first active pattern ACT1 corresponds to the first terminal and the second terminal of the first transistor T1.

[0065] In one embodiment, the second active pattern ACT2 is electrically connected to the data line DL by a second connection line CL2 For example, the second active pattern ACT2 corresponds to the first terminal and the second terminal of the second transistor T2.

[0066] The gate insulation pattern GI is disposed directly on the first active pattern ACT1, the second active pattern ACT2, and the buffer layer BFR. In one embodiment, the gate insulation pattern GI is made of an insulating material. The insulating material used for the gate insulation pattern GI can be silicon oxide, silicon nitride, silicon oxynitride, etc., which can be used alone or in combination with each other. The gate insulation pattern GI can be formed of a single layer or multiple layers.

[0067] The first gate electrode GAT1, the third gate electrode GAT3, and the first connection electrode CE1 are each disposed on the gate insulation pattern GI. For example, the first gate electrode GAT1, the third gate electrode GAT3, and the first connection electrode CE1 are formed together. In other words, the first gate electrode GAT1, the third gate electrode GAT3, and the first connection electrode CE1 are disposed in the same layer.

[0068] In one embodiment, each of the first gate electrode GAT1, the third gate electrode GAT3, and the first connection electrode CE1 is formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. Materials used for the first gate electrode GAT1, the third gate electrode GAT3, and the first connection electrode CE1 include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. For example, the first gate electrode GAT1, the third gate electrode GAT3, and the first connection electrode (CE1) are formed of titanium (Ti).

[0069] The first gate electrode GAT1 overlaps the bottom electrode BML and the first active pattern ACT1, and the third gate electrode GAT3 overlaps the second active pattern ACT2.

[0070] The first connection electrode CE1 is electrically connected to the power supply wiring VL. In another embodiment, the first connection electrode CE1 overlaps the power supply wiring VL and does not contact the power supply wiring VL. In another embodiment, the first connection electrode CE1 does not overlap the power supply wiring VL.

[0071] The second gate electrode GAT2 is disposed on the first gate electrode GAT1, and the fourth gate electrode GAT4 is disposed on the third gate electrode GAT3. For example, the second gate electrode GAT2 and the fourth gate electrode GAT4 are formed together. In other words, the second gate electrode GAT2 and the fourth gate electrode GAT4 are disposed in the same layer.

[0072] In one embodiment, the second gate electrode GAT2 and the fourth gate electrode GAT4 are formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. Materials used for the second gate electrode GAT2 and the fourth gate electrode GAT4 include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. For example, the second gate electrode GAT2 and the fourth gate electrode GAT4 are formed of copper (Cu).

[0073] The first cap electrode CPE1 is disposed on the second gate electrode GAT2, and the second cap electrode CPE2 is disposed on the fourth gate electrode GAT4. For example, the first cap electrode CPE1 and the second cap electrode CPE2 are formed together. In other words, the first cap electrode CPE1 and the second cap electrode CPE2 are disposed in the same layer.

[0074] In one embodiment, the first cap electrode CPE1 and the second cap electrode CPE2 are formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. Materials used for the first cap electrode CPE1 and the second cap electrode CPE2 include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0075] In one embodiment, each of the first cap electrode CPE1 and the second cap electrode CPE2 has a Ti / Cu structure. In another embodiment, each of the first cap electrode CPE1 and the second cap electrode CPE2 is made of indium tin oxide (ITO).

[0076] The first cap electrode CPE1 overlaps the bottom electrode BML and the first active pattern ACT1, and is in contact with the second gate electrode GAT2. The second cap electrode CPE2 overlaps the second active pattern ACT2, and is in contact with the fourth gate electrode GAT4.

[0077] In one embodiment, the first gate electrode GAT1, the second gate electrode GAT2, and the first cap electrode CPE1 configure the gate electrode GAT In other words, the gate electrode GAT has a multi-layer structure.

[0078] The passivation layer PVX is disposed on the buffer layer BFR. The passivation layer PVX covers the first gate electrode GAT1, the second gate electrode GAT2, and the first cap electrode CPE1, and covers the third gate electrode GAT3, the fourth gate electrode GAT4, and the second cap electrode CPE2.

[0079] In one embodiment, the passivation layer PVX has an undercut shape UC overlapping the first connection electrode CE1. In other words, the passivation layer PVX has an undercut shape UC, and the first connection electrode CE1 is disposed inside the undercut shape UC. As a result, the upper surface of the first connection electrode CE1 and the passivation layer PVX do not contact each other. Although not shown, an organic material is filled between the upper surface of the first connection electrode CE1 and the passivation layer PVX.

[0080] In one embodiment, the passivation layer PVX is made of an insulating material. The insulating material used for the passivation layer PVX includes silicon oxide, silicon nitride, silicon oxynitride, etc. These can be used alone or in combination with each other. The passivation layer PVX can be composed of a single layer or multiple layers.

[0081] The via insulating layer VIA is disposed on the passivation layer PVX. In one embodiment, the via insulating layer VIA is made of an insulating material. The insulating material used as the via insulating layer VIA includes photoresist, polyacrylic resin, polyimide resin, acrylic resin, etc. These can be used alone or in combination with each other.

[0082] The pixel electrode PE, the first connection line CL1, and the second connection line CL2 are disposed on the via insulating layer VIA. The second connection electrode CE2 is disposed on the via insulating layer VIA and is interrupted by an undercut shape UC. For example, the pixel electrode PE, the first connection line CL1, the second connection line CL2, and the second connection electrode CE2 are formed together.

[0083] In one embodiment, the pixel electrode PE, the first connection line CL1, the second connection line CL2, and the second connection electrode CE2 are formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. Materials used for the pixel electrode PE, the first connection line CL1, the second connection line CL2, and the second connection electrode CE2 include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. For example, each of the pixel electrode PE, the first connection line CL1, the second connection line CL2, and the second connection electrode CE2 has an ITO / Ag / ITO structure.

[0084] In one embodiment, the pixel electrode PE contacts the bottom electrode BML and the first active pattern ACT1. The pixel electrode PE is electrically connected to the bottom electrode BML through a first contact hole penetrating the passivation layer PVX and the buffer layer BFR, and is electrically connected to the first active pattern ACT1 through a second contact hole penetrating the passivation layer PVX. The pixel electrode PE also corresponds to a first terminal of the light emitting element LED.

[0085] In one embodiment, the first connection wiring CL1 contacts the first cap electrode CPE1 and the second active pattern ACT2. The first connection wiring CL1 electrically connects the first cap electrode CPE1 and the second active pattern ACT2.

[0086] In one embodiment, the second connection wiring CL2 contacts the data wiring DL and the second active pattern ACT2 through a contact hole penetrating the passivation layer PVX. The second connection wiring CL2 is electrically connected to the data wiring DL through a third contact hole penetrating the passivation layer PVX and the buffer layer BFR, and electrically connects the second active pattern ACT2 through a fourth contact hole penetrating the passivation layer PVX.

[0087] In one embodiment, the second connection electrode CE2 is interrupted by an undercut shape UC. The second connection electrode CE2 contacts the power supply wiring VL and the first connection electrode CE1. As a result, the second connection electrode CE2 electrically connects the power supply wiring VL and the first connection electrode CE1.

[0088] The pixel defining layer PDL is disposed on the via insulating layer VIA. In one embodiment, the pixel defining layer PDL is formed of an insulating material. Examples of insulating materials used as the pixel defining layer PDL include photoresist, polyacrylic resin, polyimide resin, acrylic resin, etc. These may be used alone or in combination with each other. In one embodiment, the pixel defining layer PDL is formed with a first opening exposing an upper surface of the pixel electrode PE and a second opening overlapping the second connection electrode CE2.

[0089] The light emitting layer EL is disposed on the pixel electrode PE, the pixel defining layer PDL, and the second connecting electrode CE2. In other words, the light emitting layer EL is formed on the whole surface of the lower structure LRS. In one embodiment, the light emitting layer EL is interrupted by an undercut shape UC.

[0090] The common electrode CTE is disposed on the light-emitting layer EL. In one embodiment, the common electrode CTE is formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. Materials used as the common electrode CTE include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), and the like. These materials can be used alone or in combination with each other. In addition, the common electrode CTE is composed of a single layer and a multilayer.

[0091] In one embodiment, the common electrode CTE is interrupted by an undercut shape UC. Thus, the light-emitting layer EL is disposed between the second connection electrode CE2 and the common electrode CTE. In one embodiment, the common electrode CTE covers the side surface of the light-emitting layer EL.

[0092] In one embodiment, the first connection electrode CE1, the second connection electrode CE2, and the common electrode CTE are formed inside the undercut shape UC. The common electrode CTE contacts the first connection electrode CE1 and the second connection electrode CE2. This allows the common electrode CTE to be electrically connected to the power supply line VL. In this case, the common electrode CTE does not directly contact the power supply line VL.

[0093] FIG. 6 is a cross-sectional view illustrating an upper structure included in the display device of FIG.

[0094] As shown in FIG. 6, the upper structure UPS includes an upper substrate SUB2, a first color filter CF1, a second color filter CF2, a third color filter CF3, a refractive layer LR, a refractive cap layer LRC, a bank layer BK, a first color conversion pattern CVL1, a second color conversion pattern CVL2, a third color conversion pattern CVL3, and a color conversion cap layer QDC.

[0095] The upper substrate SUB2 includes a transparent or opaque material. In one embodiment, materials used as the upper substrate SUB2 include glass, quartz, plastic, etc. These may be used alone or in combination with each other.

[0096] The first color filter CF1, the second color filter CF2, and the third color filter CF3 are disposed under the upper substrate SUB2. In one embodiment, the first color filter CF1 transmits light having a wavelength corresponding to red light, the second color filter CF2 transmits light having a wavelength corresponding to green light, and the third color filter CF3 transmits light having a wavelength corresponding to blue light. The area where the first color filter CF1, the second color filter CF2, and the third color filter CF3 overlap functions as a light blocking layer.

[0097] The refractive layer LR is disposed under the first to third color filters CF1, CF2, and CF3. The refractive layer LR has a predetermined refractive index. This improves the light efficiency of the display device DD. In another embodiment, the refractive layer LR is disposed under the first to third color conversion patterns CVL1, CVL2, and CVL3. In another embodiment, the refractive layer LR includes first and second refractive layers, the first refractive layer being disposed on the first to third color conversion patterns CVL1, CVL2, and CVL3, and the second refractive layer being disposed under the first to third color conversion patterns CVL1, CVL2, and CVL3.

[0098] The refractive cap layer LRC is disposed below the refractive layer LR. The refractive cap layer LRC protects the refractive layer LR. In another embodiment, the cap layer is disposed above the refractive layer LR. In another embodiment, a first cap layer is disposed below the refractive layer LR and a second cap layer is disposed above the refractive layer LR.

[0099] The bank layer BK is disposed below the refractive cap layer LRC. The bank layer BK is made of a light-shielding material and blocks light emitted from below. The bank layer BK has an opening formed therein to expose the refractive cap layer LRC.

[0100] The first color conversion pattern CVL1 is disposed under the first color filter CF1 and overlaps the first pixel electrode 4110. The first color conversion pattern CVL1 converts the wavelength of light emitted from the light emitting layer EL. For example, the first color conversion pattern CVL1 includes a phosphor, a scattering material, a quantum dot, etc. When the light emitted from the light emitting layer EL passes through the first color conversion pattern CVL1, red light is emitted.

[0101] The second color conversion pattern CVL2 is disposed under the second color filter CF2 and overlaps the second pixel electrode 4120. The second color conversion pattern CVL2 converts the wavelength of light emitted from the light emitting layer EL. For example, the second color conversion pattern CVL2 includes a phosphor, a scattering material, a quantum dot, etc. When the light emitted from the light emitting layer EL passes through the second color conversion pattern CVL2, green light is emitted.

[0102] The third color conversion pattern CVL3 is disposed under the third color filter CF3 and overlaps the third pixel electrode 4130. The third color conversion pattern CVL3 scatters the wavelengths of light emitted from the light emitting layer EL. For example, the third color conversion pattern CVL3 includes a phosphor, a scatterer, a quantum dot, etc. When the light emitted from the light emitting layer EL passes through the third color conversion pattern CVL3, blue light is emitted.

[0103] In one embodiment, each of the first to third color conversion patterns CVL1, CVL2, and CVL3 has a concave cross-sectional shape.

[0104] The color converting cap layer QDC is disposed under the first to third color conversion patterns CVL1, CVL2, and CVL3. The color converting cap layer QDC protects the first to third color conversion patterns CVL1, CVL2, and CVL3.

[0105] Figures 7 to 18 are cross-sectional views for explaining a method for manufacturing the lower structure of Figure 5. For example, Figure 10 is an enlarged view of region A of Figure 9, Figure 12 is an enlarged view of region B of Figure 11, Figure 16 is an enlarged view of region C of Figure 15, and Figure 18 is an enlarged view of region D of Figure 17.

[0106] 7, a bottom electrode BML, a data line DL, and a power line VL are formed on a substrate SUB1. A buffer layer BFR is formed to cover the bottom electrode BML, the data line DL, and the power line VL. A first active pattern ACT1 and a second active pattern ACT2 are formed on the buffer layer BFR.

[0107] A gate insulating layer is formed on the first active pattern ACT1 and the second active pattern ACT2, and a gate electrode layer is formed on the gate insulating layer. Then, the gate insulating layer and the gate electrode layer are patterned together to form a gate insulating pattern GI, a first gate electrode GAT1, a second gate electrode GAT2, a first cap electrode CPE1, a third gate electrode GAT3, a fourth gate electrode GAT4, a second cap electrode CPE2, a first connection electrode CE1, an etching electrode ECE, and a third cap electrode CPE3.

[0108] Specifically, the first gate electrode GAT1, the third gate electrode GAT3, and the first connection electrode CE1 are all formed of the same material. In one embodiment, the first gate electrode GAT1, the third gate electrode GAT3, and the first connection electrode CE1 are formed of titanium (Ti).

[0109] The second gate electrode GAT2, the fourth gate electrode GAT4, and the etching electrode ECE are all formed of the same material. In one embodiment, the second gate electrode GAT2, the fourth gate electrode GAT4, and the etching electrode ECE are formed of copper (Cu).

[0110] The first cap electrode CPE1, the second cap electrode CPE2, and the third cap electrode CPE3 are all formed of the same material. In one embodiment, the first cap electrode CPE1, the second cap electrode CPE2, and the third cap electrode CPE3 each have a Ti / Cu structure. In another embodiment, the first cap electrode CPE1, the second cap electrode CPE2, and the third cap electrode CPE3 are formed of ITO.

[0111] However, the metals forming the first gate electrode GAT1, the second gate electrode GAT2, the first cap electrode CPE1, the third gate electrode GAT3, the fourth gate electrode GAT4, the second cap electrode CPE2, the first connection electrode CE1, the etching electrode ECE, and the third cap electrode CPE3 are not limited to these, and various metals can be selected taking into consideration hardness, electrical conductivity, etching selectivity, etc.

[0112] 8, the preliminary passivation layer PVX' is formed on the buffer layer BFR. The preliminary passivation layer PVX' covers the first gate electrode GAT1, the second gate electrode GAT2, and the first cap electrode CPE1, covers the third gate electrode GAT3, the fourth gate electrode GAT4, and the second cap electrode CPE2, and covers the first connection electrode CE1, the etching electrode ECE, and the third cap electrode CPE3.

[0113] A via insulating layer VIA is disposed on the preliminary passivation layer PVX'. A via contact hole VCNT is formed in the via insulating layer VIA. The via contact hole VCNT penetrates the via insulating layer VIA. In one embodiment, the via contact hole VCNT includes a first via contact hole VCNT1 overlapping the first cap electrode CPE1 and a second via contact hole VCNT2 overlapping the third cap electrode CPE3. The first via contact hole VCNT1 exposes the preliminary passivation layer PVX' overlapping the first cap electrode CPE1, and the second via contact hole VCNT2 exposes the preliminary passivation layer PVX' overlapping the third cap electrode CPE3.

[0114] As shown in FIG. 9 and FIG. 10, a contact hole CNT is formed in the preliminary passivation layer PVX'. The contact hole CNT penetrates the preliminary passivation layer PVX', thereby forming the passivation layer PVX. The contact hole CNT includes a first contact hole CNT1 connected to the first via contact hole VCNT1 and a second contact hole CNT2 connected to the second via contact hole VCNT2. The first contact hole CNT1 exposes the first cap electrode CPE1. As shown in FIG. 10, the second contact hole CNT2 exposes the side surface SSF of the etching electrode ECE and the upper surface of the power supply wiring VL.

[0115] 11 and 12, the etching electrode ECE and the third cap electrode CPE3 are removed. In one embodiment, the etching electrode ECE and the third cap electrode CPE3 are removed by reacting with the first etchant ECT1. This forms an undercut shape UC in the passivation layer PVX. Also, the first connection electrode CE1 is disposed inside the undercut shape UC.

[0116] Specifically, as shown in FIG. 12, the first etchant ECT1 contacts the exposed side surface SSF of the etching electrode ECE. In other words, the etching electrode ECE reacts with the first etchant ECT1 through the exposed side surface SSF. As a result, the etching electrode ECE is etched and removed. In addition, the third cap electrode CPE3 is removed together with the etching electrode ECE.

[0117] 11, the first etchant ECT1 contacts the upper surface of the first cap electrode CPE1. In this case, the first cap electrode CPE1 is a metal that does not react with the first etchant ECT1. Therefore, the first cap electrode CPE1 can protect the second gate electrode GAT2 from being removed by the first etchant ECT1.

[0118] In other words, the first etchant ECT1 is an etchant that does not react with the first cap electrode CPE1 and the third cap electrode CPE3, but reacts with the etching electrode ECE.

[0119] As shown in FIG. 13, a spare second connection electrode CE2' is formed on the via insulating layer VIA. The spare second connection electrode CE2' is formed on the entire surface of the lower structure LRS. The spare second connection electrode CE2' contacts the first cap electrode CPE1 through the first contact hole CNT1, and contacts the first connection electrode CE1 and the power supply wiring VL through the second contact hole CNT2. In addition, the spare second connection electrode CE2' contacts the lower electrode BML, the first active pattern ACT1, the second active pattern ACT2, and the data wiring DL through the contact holes CNT.

[0120] 14, the spare second connection electrode CE2' is patterned. In one embodiment, the spare second connection electrode CE2' is reacted with the second etchant ECT2 and etched, thereby forming the second connection electrode CE2.

[0121] In one embodiment, the second etchant ECT2 contains the same material as the first etchant ECT1. In other words, the etching electrode ECE and the second connection electrode CE2 are metals that react with the same etchant. For example, the etching electrode ECE is made of copper (Cu), and the second connection electrode CE2 contains silver (Ag) and indium tin oxide (ITO). Also, the first connection electrode CE1 does not react with the first etchant ECT1 and the second etchant ECT2. As a result, the first connection electrode CE1 remains inside the undercut shape UC.

[0122] In other embodiments, the second etchant ECT2 may also include a different material than the first etchant ECT1, in other words, the etching electrode ECE and the second connection electrode CE2 may react with different etchants.

[0123] 15 and 16, a pixel defining film PDL is formed on the second connecting electrode CE2. An opening is formed in the pixel defining film PDL, and an emission layer EL is formed on the pixel defining film PDL. The emission layer EL is formed on the entire surface of the lower structure LRS, and is interrupted by an undercut shape UC.

[0124] The light-emitting layer EL is formed on the second connection electrode CE2, as shown in Figure 16. In one embodiment, the light-emitting layer EL is deposited at a first angle DG1.

[0125] 17 and 18, a common electrode CTE is formed on the light emitting layer EL. The common electrode CTE is formed on the entire surface of the lower structure LRS and is interrupted by an undercut shape UC.

[0126] As shown in FIG. 18, the common electrode CTE is formed on the light-emitting layer EL. In one embodiment, the common electrode CTE is deposited at a second angle DG2. For example, the first angle DG1 is greater than the second angle DG2. This allows the common electrode CTE to cover the side surface of the light-emitting layer EL inside the undercut shape UC. Also, the common electrode CTE contacts the side surface of the second connection electrode CE2 and the upper surface of the first connection electrode CE1. Thus, the common electrode CTE is electrically connected to the power supply line VL.

[0127] The display device DD includes a power supply line VL, a first connection electrode CE1, a second connection electrode CE2, and a common electrode CTE. The common electrode CTE is electrically connected to the power supply line VL by at least one of the first connection electrode CE1 and the second connection electrode CE2. This prevents a voltage drop of the common voltage ELVSS provided by the common electrode CTE.

[0128] An undercut shape UC in which the first connection electrode CE1 is disposed is formed in the passivation layer PVX overlapping the power supply wiring VL. The undercut shape UC is formed by removing the etching electrode ECE, and the etching electrode ECE is etched with the same etchant as that used to etch the pixel electrode PE. This improves the economy of the process of forming the undercut shape UC.

[0129] FIG. 19 is a cross-sectional view for explaining a display device according to another embodiment of the present invention, and FIG. 20 is an enlarged view of a region E in FIG.

[0130] 19, a display device DD1 according to another embodiment of the present invention includes an emitting layer EL′ and a common electrode CTE′. However, the display device DD1 is similar to the display device DD described in FIG. 5 except for the emitting layer EL′ and the common electrode CTE′.

[0131] 20, the light-emitting layer EL' is formed on the entire surface of the lower structure LRS and is interrupted by the undercut shape UC. Inside the undercut shape UC, the light-emitting layer EL' covers the side surface of the second connection electrode CE2. For example, the deposition angle of the light-emitting layer EL' is reduced. As a result, the light-emitting layer EL' comes into contact with the side surface of the second connection electrode CE2 and the upper surface of the second connection electrode CE2.

[0132] The common electrode CTE' is formed on the light-emitting layer EL'. The common electrode CTE' is formed on the entire surface of the lower structure LRS and is interrupted by the undercut shape UC. Within the undercut shape UC, the common electrode CTE' is in contact with the upper surface of the light-emitting layer EL', the side surface of the light-emitting layer EL', and the upper surface of the first connection electrode CE1.

[0133] As mentioned above, the present invention has been described with reference to exemplary embodiments. However, those having ordinary skill in the art will appreciate that the present invention can be modified and changed in various ways without departing from the spirit and scope of the present invention as set forth in the following claims. [Industrial Applicability]

[0134] The present invention is applicable to display devices and electronic devices including the same, such as high-resolution smartphones, mobile phones, smart pads, smart watches, tablet PCs, vehicle navigation systems, televisions, computer monitors, and notebook computers.

Claims

1. A power supply wiring disposed on the substrate; a passivation layer disposed on the power supply wiring and having an undercut shape; a first connection electrode that is disposed on the power supply wiring and within the undercut shape; a second connection electrode disposed on the power supply wiring and electrically connecting the power supply wiring and the first connection electrode; a common electrode disposed on the second connection electrode and electrically connected to the power supply wiring by at least one of the first connection electrode and the second connection electrode; A display device comprising:

2. The display device according to claim 1 , wherein the common electrode is in contact with the first connection electrode and the second connection electrode.

3. The display device according to claim 1 , wherein the common electrode is not in contact with the power supply wiring.

4. The display device according to claim 1 , wherein the first connection electrode is in contact with the second connection electrode.

5. The display device according to claim 1 , wherein the second connection electrode is in contact with the power supply wiring, the first connection electrode, and the common electrode.

6. The display device of claim 1 , further comprising a light emitting layer interrupted by the undercut shape.

7. The display device according to claim 6 , wherein the light-emitting layer is disposed between the second connection electrode and the common electrode.

8. The display device according to claim 7 , wherein the common electrode covers a side surface of the light-emitting layer.

9. A data line disposed in the same layer as the power supply line; a first gate electrode disposed in the same layer as the first connection electrode; a cap electrode disposed on the first gate electrode; The display device according to claim 1 , further comprising: a pixel electrode disposed in the same layer as the second connection electrode.

10. forming a power supply wiring on a substrate; forming a first connection electrode and an etching electrode on the power supply wiring; forming a pre-passivation layer on the etching electrode so as to cover the etching electrode; patterning the passivation layer so as to expose a side surface of the etching electrode; removing the etching electrode such that the passivation layer has an undercut profile; forming a second connection electrode that electrically connects the power supply wiring and the first connection electrode; forming a common electrode on the second connection electrode, the common electrode being electrically connected to the power supply wiring by at least one of the first connection electrode and the second connection electrode; A method for manufacturing a display device comprising the steps of:

11. The method of claim 10, wherein the etching electrode reacts with the first etchant through the exposed side surface.

12. The step of forming the second connection electrode includes: forming a spare second connection electrode; Etching the spare second connection electrode with a second etchant; The method of claim 11, wherein the first etchant contains the same material as the second etchant.

13. The etching electrode includes copper (Cu), The method of claim 12, wherein the spare second connection electrodes contain silver (Ag) and indium tin oxide (ITO).

14. The method for manufacturing a display device according to claim 10 , wherein the first connection electrode contains titanium (Ti).

15. forming data wiring together with the power wiring on the substrate; forming a first gate electrode together with the first connection electrode; forming a cap electrode on the first gate electrode; The method of claim 10 , wherein the passivation layer exposes an upper surface of the cap electrode.

16. the etching electrode reacts with a first etchant through the exposed side surface; The second connection electrode reacts with a second etchant; The method of claim 15, wherein the cap electrode does not react with the first etchant and the second etchant.

17. the first gate electrode comprises titanium; the etching electrode comprises copper; The method for manufacturing a display device according to claim 16 , wherein the cap electrode contains titanium.

18. the first gate electrode comprises titanium; the etching electrode comprises copper; 17. The method of claim 16, wherein the cap electrode comprises indium tin oxide (ITO).

19. The method of claim 10, further comprising forming a light emitting layer so as to be interrupted by the undercut shape.

20. The method of claim 19, wherein a first angle at which the light emitting layer is deposited is greater than a second angle at which the common electrode is deposited.

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