Driving method and display device

Abstract

The present disclosure provides a driving method related to the display technology field. The driving method drives a pixel array, and includes an operation (S210) and an operation (S220). In the operation (S210), a timing of a gate driving signal (Gate) is set according to an effective time difference between a data signal (Vdata) and an effective signal of the gate driving signal (Gate), and in the operation (S220), the pixel array is driven by the gate driving signal (Gate). The present disclosure further provides a display device (600).

Description

[Technical field]

[0001] The present disclosure relates to the field of display technology, and in particular to a driving method and a display device. [Background technology]

[0002] A display device (e.g., an OLED display) includes a display panel, a gate driver, a data driver, and a timing controller. The display panel includes a pixel array of a plurality of pixels, where the gate driver generates gate drive signals and supplies the pixel rows with data voltages, and the data driver supplies the pixels with data voltages.

[0003] However, the change in the data signal causes a fluctuation in the power supply voltage, which causes a crosstalk phenomenon when displaying an image on the display panel, thereby affecting the display effect of the display panel. Summary of the Invention

[0004] The present disclosure provides a driving method and a display device.

[0005] According to a first aspect, the present disclosure provides a driving method, setting timing of a gate drive signal based on an effective time difference between a data signal and an effective signal of the gate drive signal, and driving a pixel array with the gate drive signal.

[0006] For example, the effective time difference includes a first time difference between the application time of the data signal and the start time of the effective level of the gate drive signal, and setting the timing of the gate drive signal based on the effective time difference includes setting the timing of the gate drive signal such that the first time difference between the application time of the data signal and the start time of the effective level of the gate drive signal is greater than 0.5 times the effective time difference and less than the effective time difference, while the duration of the effective levels of the data signal and the gate drive signal remains unchanged.

[0007] For example, the ratio of the effective time difference to the scanning period of the gate drive signal ranges from 35% to 45%.

[0008] For example, the ratio of the effective time difference to the scanning period of the gate drive signal is 39%.

[0009] For example, the range of the ratio between the first time difference and the scanning period of the gate driving signal is 22-37%.

[0010] For example, the scanning period of the gate driving signal is 8.7 μs, and the range of the first time difference is 1.9 μs-3.2 μs.

[0011] For example, the first time difference is greater than a jump time of the power supply voltage.

[0012] For example, the driving method further includes setting the duration of the latch input period based on the effective time difference such that the time difference between the end of the latch input period and the start of the effective level of the gate drive signal of the next scanning period is greater than 0.5 times the effective time difference and less than the effective time difference.

[0013] For example, the method according to the embodiment of the present disclosure further includes a first driving mode, where the first time difference is A1, and a second driving mode, where the first time difference is A2, where A1 is greater than A2.

[0014] According to a second aspect, the present disclosure provides a display device, comprising a pixel array, a timing controller, a source driver configured to generate a data signal under control of the timing controller, and a gate driver configured to generate a gate drive signal under control of the timing controller, wherein the timing controller is configured to set a timing of the gate drive signal based on an effective time difference between the data signal and an effective signal of the gate drive signal, and to drive the pixel array with the gate drive signal.

[0015] For example, the effective time difference includes a first time difference between the application time of the data signal and the start time of the effective level of the gate drive signal, and the timing controller is further configured to set the timing of the gate drive signal such that the first time difference between the application time of the data signal and the start time of the effective level of the gate drive signal is greater than 0.5 times the effective time difference and less than the effective time difference, while the effective level durations of the data signal and the gate drive signal remain unchanged.

[0016] For example, the ratio of the effective time difference to the scanning period of the gate drive signal ranges from 35% to 45%.

[0017] For example, the ratio of the effective time difference to the scanning period of the gate drive signal is 39%.

[0018] For example, the range of the ratio of the first time difference to the scanning period of the gate driving signal is 22-37%.

[0019] For example, the scanning period of the gate driving signal is 8.7 μs, and the range of the first time difference is 1.9 μs-3.2 μs.

[0020] For example, the first time difference is greater than a jump time of the power supply voltage.

[0021] For example, the timing controller is further configured to set the duration of the latch input period based on the effective time difference such that the time difference between the end of the latch input period and the start of the effective level of the gate drive signal of the next scan period is greater than 0.5 times the effective time difference and less than the effective time difference.

[0022] For example, the display device according to the embodiment of the present disclosure further includes an external power supply installed between the voltage source of the source driver and the pixel array.

[0023] For example, the display device according to the embodiment of the present disclosure further includes a resistor disposed between the voltage source of the source driver and the pixel array.

[0024] For example, the timing controller is further configured such that a first driving mode is provided, the first time difference being A1, and a second driving mode is provided, the first time difference being A2, where A1 is greater than A2. [Brief description of the drawings]

[0025] [Figure 1A] FIG. 1A is a timing diagram of signals driving a display panel according to one example. [Figure 1B] FIG. 1B is a schematic diagram showing an abnormal display on a screen when the display device is driven according to the signal timing diagram of FIG. 1A. [Diagram 2] FIG. 2 is a flowchart of a driving method according to an embodiment of the present disclosure. [Diagram 3] FIG. 3 is a signal timing diagram according to one embodiment of the present disclosure. [Figure 4] FIG. 4 is a signal timing diagram according to another embodiment of the present disclosure. [Figure 5A] FIG. 5A is a structural schematic diagram of a pixel circuit according to an embodiment of the present disclosure. [Figure 5B] FIG. 5B is a signal timing diagram of the pixel circuit in FIG. 5A. [Figure 6] FIG. 6 is a block diagram of a display device according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a block diagram of a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, and not all of the embodiments. Based on the described embodiments of the present disclosure, a person skilled in the art can easily obtain all other embodiments without creative effort, which are within the scope of protection of the present disclosure. In addition, in each drawing, the same elements are given the same or similar symbols. In the following description, some specific embodiments are only for the purpose of explanation, and should not be understood as limiting the present disclosure in any way, but are merely examples of the embodiments of the present disclosure. If there is a possibility of confusing the understanding of the present disclosure, common structures or configurations are omitted. The shapes and dimensions of each member in the drawings do not reflect the actual size and ratio, but only show the contents of the embodiments of the present disclosure.

[0027] Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure have the ordinary meanings understood by those skilled in the art. The terms "first", "second" and similar terms used in the embodiments of the present disclosure do not denote any order, quantity or importance, but are intended to distinguish different components.

[0028] In addition, in describing the embodiments of the present disclosure, the terms "coupled" or "connected" may mean that two components are directly connected to each other, or that the two components are connected to each other via one or more other components. Furthermore, the two components may be coupled or connected to each other by wire or wirelessly.

[0029] In the description of the embodiments of the present disclosure, the symbol Vdata may indicate a data signal or the level of the data signal. Similarly, the symbol Gate may indicate a gate drive signal or the level of the gate drive signal, the symbol VINT may indicate a predetermined initial voltage end or the voltage of the initial signal, and the symbol ELVDD may indicate a power supply or the power supply voltage supplied by the power supply. The following embodiments are the same as the above, and the description will be omitted.

[0030] Fig. 1A is a signal timing diagram for driving a display panel according to an example, and Fig. 1B is a schematic diagram showing a display device displaying an abnormal screen when driven according to the signal timing diagram of Fig. 1A.

[0031] As shown in Fig. 1A, when the data signal Vdata is applied, the change in the reference voltage AVDD of the data signal Vdata causes a jump in the power supply voltage VDD. Period a is a period in which the start point of the gate driving signal Gate's effective level is delayed from the application point of the data signal Vdata, and period b is a period in which the end point of the gate driving signal Gate's effective level is earlier than the end application point of the data signal Vdata. If the noise caused by the jump in the power supply voltage VDD is not eliminated at the start point of the gate driving signal Gate's effective level, i.e., at the period a, a crosstalk phenomenon will occur on the display screen of the display panel, which will affect the display effect of the display panel.

[0032] As shown in FIG. 1B, the display panel includes pixel units 110, 120 and 130. In the display process, the gate driving signal Gate scans the pixel units row by row. The applied data signal Vdata makes the pixel unit 110 display a black image, and the pixel unit 120 and the pixel unit 130 display a white image. Due to the noise caused by the jump of the power supply voltage VDD, the pixel unit 120 and the pixel unit 130 are affected by the crosstalk of the pixel unit 110, and the pixel unit 120 and the pixel unit 130 are actually displayed as a gray image, which affects the display effect of the display panel.

[0033] The present disclosure provides a driving method for driving a pixel array, including setting timing of a gate drive signal based on an effective time difference between a data signal and an effective signal of the gate drive signal, and driving the pixel array with the gate drive signal.

[0034] FIG. 2 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0035] As shown in FIG. 2, the driving method may include operations S210 to S220.

[0036] In operation S210, the timing of the gate driving signal is set based on an effective time difference between the data signal and an effective signal of the gate driving signal.

[0037] For example, the data signal is longer than the duration of the effective level of the gate drive signal, which can avoid the data signal not being written when the drive transistor is turned on. In one scanning period, the application time point of the data signal is located before the start time of the effective level of the gate drive signal, and the end application time point of the data signal is located after the end time of the effective level of the gate drive signal. The ratio of the effective time difference to the scanning period of the gate drive signal ranges from 35% to 45%. The effective time difference between the data signal and the effective signal of the gate drive signal shown in FIG. 1A includes a period a and a period b. The scanning period of the gate drive signal is 1H, for example, the scanning period of the gate drive signal is the time required to scan one row of the pixel array.

[0038] For example, the effective time difference may be constant for any pixel array. By setting the timing of the gate driving signal according to the effective time difference, the noise caused by the jump of the power supply voltage VDD before the start time of the effective level of the gate driving signal can be completely eliminated, and the crosstalk phenomenon occurring in the display panel can be mitigated.

[0039] In operation 220, the pixel array is driven with gate drive signals.

[0040] For example, if a display panel includes a pixel array, and the gate drive signals are timed according to the disclosed embodiments, the gate drive signals can drive the pixel array to mitigate crosstalk phenomena appearing in the display panel.

[0041] According to the embodiment of the present disclosure, it is possible to completely eliminate noise caused by a jump in the power supply voltage VDD before the start of the effective level of the gate driving signal, and to mitigate the crosstalk phenomenon appearing in the display panel.

[0042] The present disclosure provides an embodiment for setting the timing of a gate drive signal, the effective time difference including a first time difference between an application time of a data signal and a start time of an effective level of the gate drive signal.

[0043] Operation S210: setting the timing of the gate driving signal according to an effective time difference between the data signal and the effective signal of the gate driving signal includes: setting the timing of the gate driving signal such that the first time difference is greater than 0.5 times the effective time difference and less than the effective time difference while the effective level durations of the data signal and the gate driving signal remain unchanged, and the ratio of the first time difference to the scanning period of the gate driving signal is in the range of 22% to 37%.

[0044] FIG. 3 is a signal timing diagram according to an embodiment of the present disclosure. As shown in FIG. 3, the low level of the gate driving signal is an effective level. In the example of FIG. 3, Gate(N) indicates the gate signal of the pixel in the Nth row, and Gate(N+1) indicates the gate signal of the pixel in the N+1th row, where N is an integer equal to or greater than 1. The first time difference is a period a, and the first time difference is greater than 0.5 times the effective time difference and less than the effective time difference. The effective time difference further includes a second time difference between the end time of the effective level of the gate driving signal and the end application time of the data signal. The second time difference is a period b. The second time difference b is less than 0.5 times the effective time difference and greater than 0.

[0045] For example, for the normal timing of the gate drive signal, the first time difference and the second time difference may both be equal to 0.5 times the effective time difference. For example, for the default timing of the gate drive signal, when the duration of the effective level of the gate drive signal and the effective time difference of the data signal are 3.4 μs, the first time difference and the second time difference are both 1.7 μs. In this case, the default value of the first time difference and the second time difference may be 0.5 times the effective time difference, for example, 1.7 μs. The first time difference can be increased by delaying the start time of the effective level of the gate drive signal while keeping the effective level duration of the gate drive signal unchanged, so that the first time difference is greater than 0.5 times the effective time difference and less than the effective time difference.

[0046] The first time may be greater than the duration of the jump of the power supply voltage. If the first time difference is large enough, the noise caused by the jump of the power supply voltage VDD is completely eliminated before the start time of the effective level of the gate driving signal, and the crosstalk phenomenon appearing in the display panel can be mitigated.

[0047] Optionally, the first time difference is 1.2 times -2.4 times the jump time of the power supply voltage VDD, so as to better ensure that the noise caused by the jump of the power supply voltage VDD is completely eliminated before the effective level of the gate driving signal starts. For example, the first time difference is 2.4-3.2 μs, which is greater than the duration of the jump of the power supply voltage, 2.0 μs.

[0048] Since the duration of the effective levels of the data signal and the gate drive signal does not change, it is considered that the effective time difference (period a and period b) does not change. If the first time difference (period a) becomes larger than the default value (the first time difference is 0.5 times the effective time difference), the second time difference (period b) becomes smaller accordingly. Also, the first time difference must be smaller than the effective time difference. If the first time difference is increased indefinitely, the second time difference will not exist, that is, the end application time point of the data signal will be before the end time point of the effective level of the gate drive signal, and the data signal will not be written when the drive transistor is turned on.

[0049] The present disclosure provides a driving method of another embodiment, which, in addition to operation S210 to operation S220, further includes: setting a duration of the latch input period according to an effective time difference, such that a time difference between an end time of the latch input period and an effective level start time of the gate driving signal of the next scanning period is greater than 0.5 times the effective time difference and less than the effective time difference.

[0050] The interval between two adjacent data signals is the latch input period Latch Input. Changing the latch input period Latch Input changes the frequency of the data signal, and the application time point of the data signal in the next scanning period changes. For example, decreasing the latch input period Latch Input advances the application time point of the data signal in the next scanning period. At the same time, the change in the latch input period Latch Input changes the data signal reference voltage AVDD, which in turn changes the jump time point of the power supply voltage signal VDD.

[0051] FIG. 4 is a signal timing diagram according to another embodiment of the present disclosure. In the example of FIG. 4, Gate(N) indicates the gate signal of the pixel in the Nth row, Gate(N+1) indicates the gate signal of the pixel in the N+1th row, and Gate(N+2) indicates the gate signal of the pixel in the N+2th row. As shown in FIG. 4, the duration of the first latch input period of the normal timing of the data signal is Latch input1. For example, the signal timing diagram shown in FIG. 4 is obtained by first setting the timing of the gate drive signal, and then setting the duration of the latch input period, while the effective level duration of the gate drive signal remains unchanged. By first setting the timing of the gate drive signal, the first time difference (period a) is greater than 0.5 times the effective time difference and smaller than the effective time difference. The duration of the second latch input period is Latch input2, and the duration of the second latch input period Latch input2 is shorter than the duration of the first latch input period Latch input1, so that the first time difference (period a') between the start time of application of the data signal to the pixels in the N+1th row and the start time of the effective level of the gate drive signal Gate(N+1) of the next row is longer than the first time difference (period a) between the start time of application of the data signal to the pixels in the Nth row and the start time of the effective level of the gate drive signal Gate(N) of the Nth row. The second time difference a' is also greater than 0.5 times the effective time difference and smaller than the effective time difference.

[0052] 4 shows that the first time difference changes with the change of the duration of the latch input period Latch input. Optionally, in practical driving application, after the duration of the latch input period is set, the duration of the latch input period does not change. For example, in the embodiment of the present disclosure, the duration of the latch input period at the timing of setting the data signal is Latch input2.

[0053] For example, the driving method may be as follows: Without changing the default timing of the gate drive signal, the duration of the latch input period is set so that the time difference between the end of the latch input period and the start of the effective level of the gate drive signal in the next scan period is greater than 0.5 times the effective time difference and smaller than the effective time difference.

[0054] For example, in the above normal timing of the data signal, the duration of the latch input period may be 1.5 μs. By shortening the duration of the latch input period and increasing the first time difference while keeping the application duration of the data signal and the normal timing of the gate drive signal unchanged, the first time difference can be made to be greater than 0.5 times the effective time difference and less than the effective time difference. The duration of the latch input period can be 1.2 μs-0.3 μs.

[0055] Alternatively, the duration of the latch input period may be set to 0.4 μs.

[0056] Optionally, the overlap length between the data signal application duration and the on duration of the gate drive signal can be kept constant, thus ensuring that the loaded valid data signal time is approximately the same when the gate drive signal is output to each row.

[0057] Fig. 5A is a structural schematic diagram of a pixel circuit according to an embodiment of the present disclosure, and Fig. 5B is a signal timing diagram of the pixel circuit in Fig. 5A.

[0058] 5A and 5B, in the example of Fig. 5A, the transistors T1-T7 may be P-type transistors. In the initialization stage, the low level of the reset signal Reste1 is an active level.

[0059] The transistor T1 is turned on under the control of the reset signal Reste1. The initialization signal VINT initializes the gate of the drive transistor T3 to initialize the gate voltage of the drive transistor T3 to VINT and charges the storage capacitor CST.

[0060] In the data writing stage, the low level of the gate driving signal Gate and the low level of the reset signal Reste2 are effective levels. Under the control of the gate driving signal Gate, the transistors T2 and T4 are turned on. The driving transistor T3 is turned on by driving the voltage signal stored in the storage capacitor CST. The data signal Vdata is written from the data signal end to the node N1 via the transistors T4, T3 and T2. Under the control of the reset signal Reste2, the transistor T7 is turned on, and the initialization signal VINT is written to the anode of the light-emitting element EL along the initialization path from a predetermined initial voltage end to the light-emitting element EL, and the anode voltage of the light-emitting element EL is initialized to VINT.

[0061] It is understood that the voltage difference (VINT-ELVSS) between the initial signal terminal VINT and the second power terminal ELVSS should be smaller than the threshold voltage Voled of the light emitting element EL, where ELVSS is the voltage of the second terminal of the light emitting element OLED and Voled is the light emitting threshold voltage of the light emitting element EL, thereby ensuring that the light emitting element EL does not emit light during the data writing stage.

[0062] In the light emission stage, the low level of the light emission control signal EM is an effective level. Under the control of the light emission control signal EM, the transistors T5 and T6 are turned on. The driving transistor T3 is turned on by driving the voltage signal stored in the storage capacitor CST. When the transistors T5 and T6 are turned on, a driving current is applied to the light emitting element EL along the light emission path from the power source via the transistor T5, the driving transistor T3, and the transistor T6 to the light emitting element EL, causing the light emitting element EL to emit light.

[0063] Of course, other pixel circuits are also possible: for example, transistors T1-T2 may be N-type transistors and T3-T7 may be P-type transistors.

[0064] For example, a crosstalk test is performed on a display panel including the pixel circuit shown in Fig. 5A. In one example, the display scanning frame frequency is 60Hz, and the resolution row of the display panel is 1915 rows, so that the scanning period of the gate driving signal Gate is 1H=8.7μs, the effective time difference a+b=3.4μs, and the default values ​​of the first time difference a and the second time difference b are 1.7μs. At this time, the ratio of the effective time difference to the scanning period of the gate driving signal is 39%.

[0065] Alternatively, the scanning period H of the gate driving signal Gate can be determined by the scanning frame rate and the number of resolution lines of the display panel. For example, the scanning frame frequency is 60Hz, and the resolution lines of the display panel are 1915 lines. In addition, the resolution lines of the display panel may include real lines and virtual lines. For example, the real lines are 1888 lines, and the virtual lines are 27 lines. The gate driving signal first scans the virtual lines, and then scans the real lines again. The scanning period 1H of the gate driving signal Gate is 1H=1 / F=1 / (60*1915)=8.7μs, where F=driving frequency*number of resolution lines.

[0066] Of course, in some embodiments, other driving frequencies or resolutions are applied. Optionally, the display panel may have other resolutions, such as 10-30 Hz or 90 Hz-120 Hz, and may have other resolutions, such as 2360 lines of resolution.

[0067] Optionally, the value of the first time difference a and the second time difference b is changed by setting the timing of the gate driving signal and / or the duration of the latch input period. For example, the first time difference a is about 22-37% of 1 / F, where F=driving frequency*number of resolution rows. In the embodiment of the present disclosure, the ratio of the first time difference a and the second time difference b is changed by setting the timing of the gate driving signal and / or the duration of the latch input period. In order to test the crosstalk phenomenon when setting different ratios a / b, a crosstalk test is performed on a display panel including the pixel circuit shown in FIG. 5A using the driving method according to the embodiment of the present disclosure, and the test results are shown in Table 1. In the test, the range of the ratio a / b of the first time difference and the second time difference is 0.0625 to 16. The lower the crosstalk level, the more serious the crosstalk phenomenon.

[0068] [Table 1]

[0069] As shown in Table 1, from the default value a=b=1.7us, with the increase of the ratio a / b, the crosstalk phenomenon is gradually reduced. When a / b=16, a=3.2us, the crosstalk level is the highest. As the ratio a / b becomes smaller, the crosstalk level decreases and the crosstalk phenomenon becomes more serious. When a / b=0.0625, a=0.2us, the crosstalk level is the highest.

[0070] When the scanning period H of the gate driving signal is 8.7 μs, in order to ensure the mitigation of the crosstalk phenomenon, the range of the ratio a / b between the first time difference and the second time difference may be 1.27-16, and the range of the first time difference may be set to 1.9 μs-3.2 μs.

[0071] For example, in a display panel including the pixel circuit shown in FIG. 5A, four test points are arbitrarily selected in the display area, and a crosstalk test is performed on the test points. The horizontal and vertical crosstalk test values ​​of each test point are tested by setting the timing of the gate driving signal and the duration of the latch input period. For the same display panel, under the same test conditions, in one comparative scheme, the crosstalk test values ​​of the four test points are shown in Table 2, and in the technical scheme of the embodiment of the present disclosure, the crosstalk test values ​​of the four test points are shown in Table 3. In the above comparative scheme, the duration of the latch input period is 1.5 μs, and the range of the ratio a / b between the first time difference and the second time difference is 1, for example, the first time difference and the second time difference may both be set to a default value of 1.7 μs. In the technical solution of the embodiment of the present disclosure, the duration of the latch input period is 0.4 μs, the ratio a / b between the first time difference and the second time difference is in the range of 1.27-16, and the ratio between the first time difference and the duration of the latch input period is in the range of 4.75-8, for example, the first time difference is 3.2, the second time difference is 0.2, and the ratio between the first time difference and the duration of the latch input period is 8.

[0072] [Table 2]

[0073] [Table 3]

[0074] As shown in Table 2, according to the above-mentioned comparative solution, the crosstalk test value in the horizontal direction H of the test point 2 is 2.35%, which shows that the test point 2 has a serious crosstalk phenomenon in the horizontal direction. As shown in Table 3, according to the technical solution of the embodiment of the present disclosure, the horizontal and vertical crosstalk test values ​​of the four test points are all less than 2.00%, which shows that the crosstalk phenomenon is almost not generated in all the test points according to the technical solution of the embodiment of the present disclosure. Here, the crosstalk test value in the horizontal direction H of the test point 2 is 0.95%, which shows that the test point 2 has almost no crosstalk phenomenon in the horizontal direction. Thus, it can be verified that the crosstalk phenomenon of the display panel is mitigated after improving the crosstalk phenomenon by the method of setting the timing of the gate driving signal and the method of setting the duration of the latch input period, and increasing the ratio a / b between the first time difference and the second time difference.

[0075] The present disclosure performs crosstalk testing and improvement on a display panel in multiple operation modes. For example, the operation modes include high frequency driving and low frequency driving. For example, in a first driving mode, the first time difference is A1, for example A1=2.6μs-3μs, and in a second driving mode, the first time difference is A2, for example A1=2.0μs-2.4μs, where the first time difference A1 is greater than A2. Optionally, the first driving mode is high frequency driving (for example, 60HZ-240HZ) and the second driving mode is low frequency driving (for example, 10HZ-50HZ), of course, the second driving mode can be high frequency driving (for example, 60HZ-240HZ) and the first driving mode is low frequency driving (for example, 10HZ-50HZ). In one embodiment, in order to mitigate the crosstalk phenomenon of the display panel, the first time difference in the high frequency driving mode (120 Hz) is smaller than the first time difference in the low frequency driving mode (30 Hz).

[0076] According to an embodiment of the present disclosure, the timing of the gate driving signal and / or the duration of the latch input period are set so that the first time difference and the second time difference have a ratio greater than 1. When the first time difference is greater than 0.5 times the effective time difference, the power supply voltage ELVDD jumps away from the effective level of the gate driving signal, and the noise caused by the power supply voltage ELVDD jump may be eliminated before the start time of the effective level of the gate driving signal Gate. When the start time of the effective level of the gate driving signal Gate is reached, the jumped power supply voltage ELVDD basically returns to the normal power supply voltage ELVDD, which avoids the noise interference from being written into the storage capacitor CST and improves the crosstalk phenomenon.

[0077] In the embodiment of the present disclosure, the timing of the light emission control signal EM may be set according to the timing of the gate driving signal. Since the start point of the effective level of the gate driving signal is delayed from the start point of the effective level in the normal timing, the reset signal Reste1 can be set so that the start point of the effective level of the reset signal Reste1 is delayed by the same width according to the start point of the effective level of the gate driving signal while the effective level duration of the reset signal Reste1 remains unchanged. In this way, by setting the timing of the light emission control signal, the effective level duration of the light emission control signal in the previous scanning period can be extended from the default duration of the effective level of the light emission control signal. By lengthening the effective level duration of the light emission control signal, the average current density can be reduced and the life of the light emitting element EL can be extended.

[0078] 6 is a block diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 6, the display device 600 may include a pixel array 610, a timing controller 620, a source driver 630, and a gate driver 640.

[0079] The pixel array 610 includes a plurality of pixels, which are located at the intersections of a plurality of scan lines S, a plurality of data lines DL, and a plurality of light emission control lines EM.

[0080] The source driver 630 is configured to generate a data signal under the control of the timing controller 620. The gate driver 640 is configured to generate a gate drive signal under the control of the timing controller 620.

[0081] The timing controller 620 is configured to set the timing of the gate drive signals based on an effective time difference between the data signal and an effective signal of the gate drive signals to drive the pixel array with the gate drive signals.

[0082] The timing controller 620, the source driver 630 and the gate driver 640 are configured to perform the driving method of the above-mentioned embodiment to drive the pixel array 610. The timing controller 620 is configured to perform the above-mentioned operation S210, and the description thereof will be omitted here.

[0083] For example, the effective time difference includes a first time difference between the application time point of the data signal and the start time of the effective level of the gate drive signal, and the timing controller 620 is further configured to set the timing of the gate drive signal such that the first time difference between the application time point of the data signal and the start time of the effective level of the gate drive signal is greater than 0.5 times the effective time difference and less than the effective time difference, while the effective level durations of the data signal and the gate drive signal remain unchanged.

[0084] For example, the ratio of the effective time difference to the scanning period of the gate drive signal ranges from 35% to 45%.

[0085] For example, the ratio of the effective time difference to the scanning period of the gate drive signal is 39%.

[0086] For example, the range of the ratio of the first time difference to the scanning period of the gate driving signal is 22-37%.

[0087] For example, the scanning period of the gate driving signal is 8.7 μs, and the range of the first time difference is 1.9 μs-3.2 μs.

[0088] For example, the first time difference is greater than a jump time of the power supply voltage, the jump time of the power supply voltage being related to a reference voltage of the data signal.

[0089] For example, the timing controller 620 is further configured to set the duration of the latch input period according to the effective time difference, such that the time difference between the end of the latch input period and the start of the effective level of the gate drive signal of the next scan period is smaller than the effective time difference.

[0090] FIG. 7 is a block diagram of a display device according to another embodiment of the present disclosure.

[0091] The display device 700 may include a pixel array 710, a timing controller 720, a source driver 730, a gate driver 740, a power supply chip Power IC 750, and a gamma correction chip GAM IC 760.

[0092] The pixel array 710, the timing controller 720, the source driver 730 and the gate driver 740 have the same functions as the pixel array 610, the timing controller 620, the source driver 630 and the gate driver 640 of the display device shown in Figure 6. For the sake of brevity, this disclosure will not be described in detail.

[0093] The power supply chip Power IC 750 inputs the data signal reference voltage AVDD to the gamma correction chip GAM IC 760, which performs gamma correction on the data signal reference voltage AVDD and inputs the corrected data signal reference voltage AVDD to the pixel array 610. The power supply chip Power IC 750 is further configured to input an initialization signal VINT to the pixel array 610.

[0094] In an embodiment of the present disclosure, by installing external devices, such as an external power supply, a constant voltage capacitor, or a filter resistor, at points N, P, and Q as shown in FIG. 7, a water ripple phenomenon test and a crosstalk test can be performed on the display panel.

[0095] For example, to test the moire phenomenon and crosstalk phenomenon of a display panel under different hardware conditions, a moire test and a crosstalk test are performed on a display panel including a pixel circuit shown in FIG. 5A. The hardware conditions of the test include providing relevant external devices at points N, P, and Q on the path for inputting the reference voltage of the data signal as shown in FIG. 7, modifying the operation mode of the Power IC 750, and changing the Power IC 750 to the Power IC2. The duration of the latch input period input to the data line during the test includes 0.4 μs and 1.5 μs. The test results are shown in Table 4. N indicates that the phenomenon shown in the table does not exist, and Y indicates that the phenomenon shown in the table exists. When an external device is provided at point Q, the moire phenomenon is improved in either case, so Table 4 does not show the test results of providing relevant external devices at point Q.

[0096] [Table 4]

[0097] As shown in Table 4, when the duration of the latch input period is 1.5 μs, the display panel of the display device shown in Table 4 has a crosstalk phenomenon. When the duration of the latch input period is 0.4 μs, it can be considered that the crosstalk phenomenon does not occur. When the duration of the latch input period is 0.4 μs, it can be considered that the moire phenomenon does not occur when an external power supply is installed at point N or point P, it can be considered that the moire phenomenon does not occur if a filter resistor is installed at point N, it can be considered that the moire phenomenon does not occur if the Power IC 750 adopts a normal operation mode instead of a power saving mode, and it can be considered that the moire phenomenon does not occur when the Power IC 750 is replaced with another power supply chip.

[0098] According to the embodiment of the present disclosure, the reference voltage of the data signal can be optimized and the moire problem can be improved by providing an external power supply or filter resistor between the power supply chip Power IC 750 and the gamma correction chip GAM IC 760. An external power supply or filter resistor may be provided between the power supply chip Power IC 750 and the pixel array 710 to optimize the reference voltage of the data signal and mitigate the moire problem.

[0099] The flowcharts and block diagrams in the drawings illustrate possible system architectures, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, a program fragment or a portion of code that includes one or more executable instructions for implementing a certain logical function. It should be noted that in alternative implementations, the functions described in the blocks may be performed in a different order than the order described in the drawings. For example, two successively shown blocks may actually be essentially executed in parallel, or they may be executed in the reverse order, as determined by such functionality. It should be noted that each block in the block diagrams or flowcharts, and combinations of blocks in the block diagrams or flowcharts, may be implemented in a system with dedicated hardware that performs a certain function or operation, or may be implemented in a combination of dedicated hardware and computer instructions.

[0100] As can be understood by those skilled in the art, the features described in each embodiment and / or claims of the present disclosure may be combined and / or combined in multiple combinations even if not explicitly described in the present disclosure. In particular, the features described in each embodiment and / or claims of the present disclosure may be combined and / or combined in various ways without departing from the spirit and teachings of the present disclosure. All such combinations and / or combinations are within the scope of the present disclosure.

[0101] The above describes the embodiments of the present disclosure. However, these embodiments are merely illustrative and do not limit the scope of the present disclosure. Although the above describes each embodiment, it does not mean that the measures in each embodiment cannot be advantageously used together. The scope of the present disclosure is limited by the appended claims and their equivalents. A person skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all of these substitutions and modifications are included in the scope of the present disclosure.

Claims

1. Drives the pixel array; setting a timing of the gate drive signal based on an effective time difference between a data signal and an effective signal of the gate drive signal; driving the pixel array with the gate drive signals. A driving method comprising:

2. the effective time difference includes a first time difference between an application time of the data signal and a start time of an effective level of the gate drive signal; setting timing of the gate drive signals based on the effective time difference timing the gate drive signals such that the first time difference is greater than 0.5 times the effective time difference and less than the effective time difference, while the durations of the effective levels of the data signals and the gate drive signals remain unchanged. The method of claim 1.

3. The ratio of the effective time difference to the scanning period of the gate driving signal is in the range of 35-45%. The method of claim 2.

4. The ratio of the effective time difference to the scanning period of the gate driving signal is 39%. The method according to claim 3.

5. The ratio of the first time difference to the scanning period of the gate driving signal ranges from 22% to 37%. The method of claim 2.

6. The scanning period of the gate driving signal is 8.7 μs, and the first time difference ranges from 1.9 μs to 3.2 μs.

6. The method according to any one of claims 3 to 5.

7. The first time difference is greater than a jump time of the power supply voltage. The method of claim 2.

8. and setting a duration of the latch input period based on the effective time difference such that a time difference between an end point of the latch input period and a start point of an effective level of the gate drive signal of the next scanning period is greater than 0.5 times the effective time difference and less than the effective time difference. The method of claim 2.

9. The method further includes a first driving mode, in which the first time difference is A1, and a second driving mode, in which the first time difference is A2, and the A1 is greater than A2. The method of claim 2.

10. A pixel array; A timing controller; A source driver configured to generate a data signal under the control of the timing controller; A gate driver configured to generate a gate drive signal under the control of the timing controller; The timing controller includes: configured to set a timing of the gate drive signal based on an effective time difference between the data signal and an effective time of the gate drive signal, and to drive the pixel array with the gate drive signal. Display device.

11. the effective time difference includes a first time difference between an application time of the data signal and a start time of an effective level of the gate drive signal; The timing controller further comprises: and setting the timing of the gate drive signal such that, while the effective level durations of the data signal and the gate drive signal remain unchanged, a first time difference between an application time point of the data signal and a start time point of an effective level of the gate drive signal is greater than 0.5 times the effective time difference and less than the effective time difference. The display device according to claim 10.

12. The ratio of the effective time difference to the scanning period of the gate driving signal is in the range of 35-45%. The display device according to claim 11.

13. The ratio of the effective time difference to the scanning period of the gate driving signal is 39%. The display device according to claim 11.

14. The ratio of the first time difference to the scanning period of the gate driving signal ranges from 22% to 37%. The display device according to claim 11.

15. The scanning period of the gate driving signal is 8.7 μs, and the first time difference ranges from 1.9 μs to 3.2 μs. The display device according to any one of claims 12 to 14.

16. The first time difference is greater than a jump time of a power supply voltage. The display device according to claim 11.

17. The timing controller further comprises: The duration of the latch input period is set based on the effective time difference so that the time difference between the end of the latch input period and the start of the effective level of the gate drive signal in the next scanning period is greater than 0.5 times the effective time difference and less than the effective time difference. The display device according to claim 10.

18. The pixel array further includes an external power supply disposed between the voltage source of the source driver and the pixel array. The display device according to claim 10.

19. The source driver further includes a resistor disposed between a voltage source of the source driver and the pixel array. The display device according to claim 10.

20. The timing controller further comprises: A first driving mode in which the first time difference is A1 and a second driving mode in which the first time difference is A2 are provided; The A1 is greater than A2 The display device according to claim 11.

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