Single-photon avalanche diode macropixel and image, proximity or time-of-flight sensor comprising same

Abstract

A macropixel is disclosed. The macropixel comprises a plurality of pixels, each pixel comprising a single photon avalanche diode (SPAD). The macropixel also comprises a memory configured to store a plurality of counts, each count associated with one pixel of the plurality of pixels, and a plurality of saturation bits, each saturation bit associated with one count of the plurality of counts. The macropixel also comprises a saturation detection circuit configured to gate recharging of each SPAD based on a state of each saturation bit.

Description

[Technical field]

[0001] The present disclosure is in the field of SPAD-based pixels, and in particular, relates to macro-pixels comprising multiple SPAD-based pixels for use in image sensors. [Background technology]

[0002] Single-photon avalanche detector (SPAD)-based sensors can typically be implemented in a variety of applications including, for example, LIDAR, time-of-flight (ToF), and 3D imaging applications.

[0003] The characteristics and operation of a SPAD may also be affected by the underlying semiconductor technology used to implement the SPAD, as well as by associated circuitry for controlling and sensing SPAD operation and recording SPAD events, e.g., photon strikes. For example, the dynamic range, spatial resolution, signal-to-noise ratio and / or bit count of a SPAD-based device may depend, at least in part, on the underlying semiconductor technology node on which the SPAD is fabricated and / or the associated measurement and storage circuitry.

[0004] In some examples, the circuitry required to read and / or store the state of a SPAD can significantly affect the size, cost, power consumption, and general performance of a SPAD-based device.

[0005] These characteristics of SPAD-based pixels and their operation have somewhat limited the use of SPAD-based pixels in applications such as image sensing.

[0006] For example, implementation of a cost-effective image sensor using SPAD-based pixels, where the SPAD-based image sensor had performance comparable to known megapixel CMOS image sensors, would require implementation of a SPAD-based pixel that exhibits a high photon count dynamic range, yet has sufficiently low power consumption and a footprint small enough to ensure commercial viability, which may be largely related to megapixel count in the format of standard optical lenses for cameras integrated into a low z-height suitable for mobile battery-powered applications.

[0007] Semiconductor technology nodes, such as sub-30 nanometer nodes, that may be required to implement circuits that meet such stringent size, power, and performance requirements may be prohibitively expensive. Thus, the design of a SPAD-based image sensor implementation may require suboptimal compromises with respect to spatial resolution, temporal resolution, bit count, power requirements, and / or signal-to-noise ratio.

[0008] In particular, the implementation of the counter for counting SPAD events can significantly affect the size, power, and performance of a SPAD-based photon-counting image sensor.

[0009] Known counter solutions can include either digital or analog bit counters.

[0010] Digital bit counters generally use N flip-flops for an N-bit counter, and despite process scaling to advanced CMOS manufacturing nodes, e.g., sub-30 nanometer nodes, such counters still occupy a significant area due to their large transistor count, thereby potentially limiting the pitch and therefore the resolution of any image array implemented using such digital bit counters.

[0011] Another approach is the use of analog counters, which can advantageously reduce pixel pitch and power, but such analog counters can be prone to current leakage, mismatch errors, and manufacturing process variations, and are not easily portable across different CMOS technology nodes.

[0012] It is therefore desirable to provide a highly integrated SPAD-based sensor suitable for implementation in megapixel image sensing applications. It is further desirable that such a SPAD-based sensor be suitable for manufacturing in cost-effective semiconductor process nodes, yet still provide sufficient dynamic range, spatial resolution, and signal-to-noise ratio to compete with known CMOS megapixel image sensors. It is desirable that such a SPAD-based sensor be implemented primarily using digital circuitry to avoid the above-mentioned shortcomings of analog solutions. Furthermore, it is highly desirable that such a SPAD-based sensor meet stringent low power requirements.

[0013] It is therefore an object of at least one embodiment of at least one aspect of the present disclosure to obviate or at least mitigate at least one of the above identified disadvantages of the prior art. Summary of the Invention [Problem to be solved by the invention]

[0014] The present disclosure is in the field of SPAD-based pixels, and in particular, relates to macro-pixels comprising multiple SPAD-based pixels for use in image sensors. [Means for solving the problem]

[0015] According to a first aspect of the present disclosure, a macropixel is provided that includes a plurality of pixels, each pixel including a single photon avalanche diode (SPAD). The macropixel also includes a memory configured to store a plurality of counts, each count associated with one pixel of the plurality of pixels, and a plurality of saturation bits, each saturation bit associated with one count of the plurality of counts. The macropixel also includes a saturation detection circuit configured to gate recharging of each SPAD based on a state of the respective saturation bit.

[0016] The term "macropixel" is understood to refer to an optical device comprising a plurality of pixels, for example two or more pixels.

[0017] The term "pixel" is understood to refer to a SPAD-based pixel, e.g., a SPAD with circuitry associated with the SPAD, which may include, for example, circuitry for sampling and holding voltage levels, circuitry for resetting the SPAD, circuitry for quenching the SPAD, etc., as described in more detail below.

[0018] The term "single-photon avalanche diode" is understood to refer only to the physical SPAD device itself, and excludes additional circuitry that may collectively form a SPAD-based pixel as described above.

[0019] The term "count" is understood to refer to a value, e.g., a value that can be used with an associated counter circuit to implement a counter. The count may be a value that is incremented, decremented, or otherwise advanced by the associated circuit to a next known state. In a further example, as described in more detail below, the count may be a value that is sequentially incremented, decremented, or adjusted to one of a number of defined known states.

[0020] In a non-limiting example, the count may correspond to words stored in memory.

[0021] Advantageously, the use of memory, e.g., SRAM or DRAM memory cells, can reduce the overall footprint and power consumption of the macropixel compared to a hardware counter, e.g., a flip-flop-based binary counter, as may be implemented in prior art pixels. That is, the overall transistor count of a memory-based macropixel can be significantly less than that associated with a hardware counter-based macropixel, thereby contributing to reduced power consumption and size. In further examples, other RAM types, such as Phase Change RAM (PCRAM), Synchronous Dynamic RAM (SDRAM), Spin Torque Transfer Magnetic RAM (STT-MRAM), etc., may be implemented.

[0022] Advantageously, by gating the recharging of each SPAD based on the state of its respective saturation bit, power consumption of the macropixel can be significantly reduced, as will be explained in more detail below.

[0023] Advantageously, the memory and saturation detection circuitry is fully digital and suitable for implementation in a compact macropixel, with the digital circuitry optimally stacked beneath the SPAD of the pixel.

[0024] Advantageously, a fully digital solution, described in more detail below, allows for the implementation of a macropixel without the need for analog-to-digital circuitry, as may be implemented in prior art pixels.

[0025] Advantageously, the disclosed macropixels enable light sensing over a high dynamic range using a low power digital pixel with a compact size suitable for implementation in low cost semiconductor manufacturing technology nodes, i.e., the disclosed macropixels avoid the need to move to increasingly advanced semiconductor manufacturing technology nodes to implement pixels that meet stringent low power and performance requirements, thereby minimizing cost and design cycle time.

[0026] The saturation detection circuitry may be configured to gate the recharging of each SPAD when the respective saturation bit indicates that the associated count has saturated.

[0027] The saturation detection circuitry may be configured to gate the recharging of each SPAD when the respective saturation bit indicates that the associated count has reached a threshold.

[0028] Advantageously, power consumption may be reduced by gating the recharging of each SPAD after the count associated with the SPAD saturates or reaches a threshold.

[0029] In an embodiment, saturation of the count may correspond to the value of the count reaching a maximum value.

[0030] In an embodiment, saturation of the count may correspond to the value at which the count rolls over or returns to the initial value.

[0031] In an embodiment, saturation of the count may correspond to the value that the count has cycled through all possible states.

[0032] In an embodiment, the threshold may be user programmable.

[0033] While recharging of one or more SPADs in one or more of the plurality of pixels is gated, the associated one or more counts can be used to indicate the time since a respective saturation bit indicated that the count has saturated and / or reached a threshold.

[0034] That is, embodiments may count the number of refresh cycles, e.g., the cycles that the SPAD would have been recharged had it not been saturated. Advantageously, as described in more detail below, such extended counting of refresh cycles, even after gating the recharge of the SPAD, may be used to effectively extend the dynamic range of the pixel.

[0035] While the recharging of one or more SPADs in one or more of the pixels is not gated, the associated one or more counts can be used to indicate the number of photons detected.

[0036] Advantageously, each count may correspond to the photon count of the associated pixel. It will be appreciated that the "number of detected photons" may correspond to the number of SPAD events, e.g. the number of avalanche current trigger events, rather than the exact number of photons incident on the SPAD.

[0037] Access to the memory by each pixel may be done in a time multiplexed manner.

[0038] Each SPAD may be recharged in a time multiplexed manner during which the recharging of the SPADs is not gated.

[0039] Advantageously, by implementing time multiplexing, power consumption can be significantly reduced, and further, the amount of logic, e.g., transistor count, can be minimized, as will be explained in more detail below with reference to the accompanying drawings.

[0040] In an embodiment, a high gain mode for each SPAD, e.g., a mode that recharges the SPAD to a Geiger mode suitable for detecting photon hits, is used with a relatively low duty cycle, but for the minimum duration required to achieve the required signal-to-noise ratio.

[0041] The time multiplexing method may be a round robin method.

[0042] That is, during use, each SPAD can be recharged and / or each count stored in memory can be accessed in a substantially equal amount of time on average.

[0043] Gating the recharge of each SPAD can include configuring at least one transistor in the respective pixel to hold the SPAD in sub-Geiger mode.

[0044] Sub-Geiger mode will be understood to be the mode in which each SPAD is biased below its reverse bias breakdown voltage.

[0045] Advantageously, by keeping the SPAD at a voltage insufficient for Geiger-mode breakdown, e.g., below its reverse bias breakdown voltage, the power consumption of the SPAD can be reduced and the lifetime of the SPAD can be increased. For example, the power consumption of a SPAD can be relatively high compared to a pinned photodiode because a relatively large amount of charge can be consumed by the avalanche multiplication process following a photon strike. By keeping the SPAD below the reverse bias breakdown voltage, the avalanche multiplication process can be avoided.

[0046] Each pixel can include at least one transistor configurable to hold the respective SPAD in a high impedance state while the SPAD is biased in Geiger mode.

[0047] In an embodiment, each SPAD may be periodically reset, and after reset, the SPAD may remain in Geiger mode while in a high impedance state, thereby advantageously reducing overall power consumption.

[0048] The macropixel may be configured such that when a photon triggers the SPAD, the SPAD discharges its internal capacitance, thereby bringing the excess bias voltage of the SPAD below its breakdown voltage.

[0049] Advantageously, upon a photon strike that triggers an avalanche event, e.g., a photon is absorbed generating an electron-hole pair that triggers an avalanche event, each SPAD can discharge its own capacitance, thereby overbiasing below the breakdown level, e.g., into sub-Geiger mode, effectively achieving self-quenching.

[0050] Each pixel may include a recharge transistor configurable to recharge the respective SPAD into Geiger mode.

[0051] Each pixel may include a sample and hold circuit for sampling and holding a voltage corresponding to the state of its respective SPAD.

[0052] Advantageously, in embodiments, the above-described pixel, which can implement both transistors configurable to hold each SPAD in a high impedance state while the SPADs are biased in Geiger mode, and sample-and-hold circuitry for sampling and holding a voltage corresponding to the state of each SPAD, can effectively realize a dynamic D-type sampler in a compact area.

[0053] The macropixel may comprise a shared memory increment or decrement circuit.The macropixel may comprise a time-multiplexed memory increment or decrement circuit.The macropixel may comprise a shared time-multiplexed memory increment or decrement circuit configured to respectively increment or decrement each count of the plurality of counts.

[0054] That is, the shared increment or decrement circuitry can be configured to selectively increment or decrement or otherwise advance each stored count in a time multiplexed manner, as described in more detail below. Advantageously, the effective area per SPAD of circuitry associated with incrementing / decrementing / advancing the counts and any associated saturation detection can be significantly minimized depending on the degree of sharing between the counts, e.g., the amount of counts that share the memory increment or decrement circuitry.

[0055] Furthermore, time multiplexing of the shared circuitry can also help to reduce power consumption, i.e., the shared circuitry may be associated with each count of the multiple counts in a time multiplexed manner, e.g., with a dedicated time slot for each count, thereby avoiding duplication of the circuitry.

[0056] In an exemplary embodiment, such time multiplexing may be in a round robin manner, however, this disclosure is not limited to such embodiments and other scheduling methods may be implemented.

[0057] Each count may correspond to a value of a binary counter.

[0058] That is, in one example, the shared increment or decrement circuitry may be configured to selectively increment or decrement each stored count using binary arithmetic, as described in more detail below with reference to the disclosed embodiments.

[0059] In an exemplary embodiment, such a shared increment or decrement circuit may be implemented as a chain of full adder circuits.

[0060] Each count can correspond to a value that represents the state of a Linear Feedback Shift Register (LFSR).

[0061] That is, in one example, the shared increment or decrement circuitry may be configured to selectively advance each stored count to the next state of the LFSR, as described in more detail below with reference to the disclosed embodiments.

[0062] In an embodiment, each LFSR may require XOR feedback and shift operations, which allows for an arbitrary LFSR-to-binary decode circuit implementation to reduce the overall transistor count compared to a binary counter implementation.

[0063] Advantageously, an LFSR can be significantly smaller than a binary counter and can consume less power and / or circuit area.

[0064] Additionally, LFSRs can reduce the need for higher levels of time-multiplexed sharing of access to memory, allowing greater availability of memory to each SPAD, thereby advantageously increasing the dynamic range of the macropixel.

[0065] Although examples of binary counters and LFSRs are described herein, it will be understood that the disclosure is not limited to such specific embodiments, and embodiments implementing alternative or additional circuitry capable of incrementing and / or decrementing a count and / or advancing a code or state may be practiced.

[0066] The macropixel may include processing circuitry configured to read out each count and each associated saturation bit at the end of a frame time.

[0067] In an embodiment, readout may be accomplished by a "rolling shutter" technique, for example by reading the memory line by line.

[0068] The processing circuitry may be configured to read out each count by clocking each pixel for at least a number of cycles corresponding to the number of memory cells associated with the pixel, while holding the pixel in a reset state.

[0069] Advantageously, this allows each count and saturation bit in the memory to be read, for example for each row in the memory, while also resetting the memory.

[0070] The processing circuitry may be further configured to read a saturation bit associated with each count.

[0071] Advantageously, the processing circuitry may implement an extended count dynamic range extension scheme using a saturation bit.

[0072] That is, in an exemplary embodiment based on an LFSR implementation, the saturation detection circuitry can detect counts where the LFSR code associated with a pixel is in an all-zero state, thereby indicating that the LFSR code has counted through all possible states and is about to "wrap around", e.g., saturate.

[0073] Similarly, in an exemplary embodiment based on binary counting, a saturation detection circuit may detect counts where the binary code associated with a pixel is in the all-ones state, thereby indicating that the binary count has counted through all possible states and is about to “wrap around”, e.g., saturate.

[0074] When this occurs, a saturation bit can be set in the respective pixel to indicate that the respective SPAD has reached saturation of its LFSR or binary counter.

[0075] As mentioned above, the saturation bit may be used to gate the recharging of the respective SPAD so that the respective SPAD is not reset to low again and can therefore remain in a high state, e.g. a triggered state.

[0076] This results in a further increment or decrement of the stored count, eg, a binary count or LFSR code, with every refresh cycle.

[0077] However, the processing circuitry can use the saturation bit to determine that the count stored since the saturation bit was set represents the "time since saturation," and therefore the dynamic range of the pixel can also be increased without a significant degradation in the signal-to-noise ratio.

[0078] That is, once the saturation bit associated with each count is set and recharging of the associated SPAD is gated, the processing circuitry can be configured to use the respective count as an indication of the round robin refresh cycle since the saturation bit was set.

[0079] The memory may comprise an array of static random access memory (SRAM) cells.

[0080] Advantageously, an SRAM-based implementation may be a compromise between relatively high density memory compared to flip-flop or logic-based counter implementations and low power consumption without the refresh cycles that may be associated with, for example, DRAM.

[0081] The memory may comprise an array of dynamic random access memory (DRAM) cells.

[0082] Advantageously, DRAM can be a very dense memory, for example with as few as three transistors per memory cell, thereby enabling very compact and integrated macropixel implementations.

[0083] The macropixel may include a refresh circuit for refreshing the DRAM cells.

[0084] Advantageously, the DRAM can be refreshed without affecting the stored count.

[0085] The refresh circuitry may be configured to increment the count by 0 if the respective SPAD is not triggered.

[0086] The refresh circuitry may be configured to add a predetermined number of extra refresh cycles to the count for subsequent subtraction by the processing circuitry.

[0087] Advantageously, the DRAM may be refreshed by affecting the stored count in a known manner.

[0088] The macropixel may be formed as a monolithic device.

[0089] In an example, the macropixel may be formed in a CMOS process.

[0090] A memory may be formed within the region of the substrate. A plurality of pixels may be formed directly above the memory. A plurality of SPADs may be formed directly above the memory.

[0091] Advantageously, the macropixels described above, and in particular the memory and / or circuitry of the macropixels described above, may be sufficiently compact such that a SPAD array, or an array of SPAD-based pixels, may be formed directly on top of the memory and / or circuitry.

[0092] According to a second aspect of the present disclosure, there is provided an image sensor comprising an array of macropixels according to the first aspect.

[0093] Advantageously, implementing an image sensor using a SPAD, instead of a pinned photodiode as may commonly be used in CMOS image sensors, can result in a sensor that exhibits very high dynamic range and sensitivity.

[0094] In an embodiment, an array of macropixels may be used to implement a "megapixel array", for example an array with hundreds of thousands or millions of pixels.

[0095] According to a third aspect of the present disclosure, there is provided a proximity or time-of-flight sensor comprising at least one macropixel according to the first aspect.

[0096] Advantageously, the time multiplexed mode of operation described above, in which, for example, each SPAD may be reset in a round robin fashion, may enable distance measurements to be performed.

[0097] For example, in one embodiment of a macropixel with N×SPADs, assuming that each SPAD is held in a reset state for 1 / N of a cycle, a return laser pulse that falls in the reset window of the i-th SPAD can be assumed to be free of signal from distances between i / N and i+1 / N of the distance range, and thus the processing circuitry can perform an indirect time-of-flight distance calculation.

[0098] The above summary is intended to be merely illustrative and non-limiting. The present disclosure includes one or more corresponding aspects, embodiments or features, either alone or in various combinations, whether or not they are specifically mentioned (including those claimed) in combination or alone. It should be understood that the features defined above according to any aspect of the present disclosure, or the features defined below with respect to any specific embodiment of the present disclosure, can be used alone or in combination with any other defined features in any other aspect or embodiment, or to form further aspects or embodiments of the present disclosure.

[0099] These and other aspects of the present disclosure will now be described, by way of example only, with reference to the accompanying drawings, in which: [Brief description of the drawings]

[0100] [Figure 1] FIG. 2 shows a block diagram of a macropixel according to one embodiment of the present disclosure. [Diagram 2] 4 shows a block diagram of a macropixel according to a further embodiment of the present disclosure; [Diagram 3] 13 shows a circuit diagram of a macropixel implemented using an LFSR and DRAM according to a further embodiment of the present disclosure. [Figure 4] 13 shows a circuit diagram of a macropixel implemented using a binary increment circuit and DRAM according to a further embodiment of the present disclosure. [Diagram 5] 13 shows a circuit diagram of a macropixel implemented using an LFSR and an SRAM according to a further embodiment of the present disclosure. [Figure 6] 13 shows a circuit diagram of a macropixel implemented using a binary increment circuit and an SRAM according to a further embodiment of the present disclosure. [Figure 7] 1 illustrates a pixel for use in a macropixel according to one embodiment of the present disclosure, and an associated timing diagram. [Figure 8] 8 shows a timing diagram of a macropixel based on the pixels of FIG. 7; [Figure 9a] 1 illustrates a sensor comprising a plurality of macropixels, according to one embodiment of the present disclosure. [Figure 9b] 9b shows a cross-sectional view of the sensor of FIG. 9a. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0101] FIG. 1 illustrates a block diagram of a macropixel 100 according to one embodiment of the present disclosure.

[0102] The exemplary macropixel 100 comprises multiple pixels: a first pixel 105a, a second pixel 105b, and a third pixel 105c. For purposes of example, only three pixels 105a, 105b, 105c are shown, although it will be understood that in embodiments of the present disclosure, as few as two or more than three pixels may be implemented in a macropixel.

[0103] Each pixel 105a, 105b, 105c includes a SPAD and associated circuitry, as described in more detail below with reference to the examples of Figures 2 to 7. For example, such associated circuitry may include circuitry for sampling and holding voltage levels, circuitry for resetting the SPAD, circuitry for quenching the SPAD, etc., as described below with reference to pixel 305 of Figure 3.

[0104] The macropixel 100 also includes a memory 110. In the exemplary macropixel described with reference to Figures 1-6, the memory 100 is an SRAM or a DRAM. It will be appreciated that such memory implementations are provided for illustrative purposes only, and that in other examples, the memory 100 may be implemented as another memory type, such as, for example, a Phase Change RAM (PCRAM), a Synchronous Dynamic RAM (SDRAM), a Spin Torque Transfer RAM (STTRAM), etc.

[0105] The memory 110 is configured to store a plurality of counts, e.g., values ​​that can be used in an associated counter circuit to implement a counter. Such counts may be stored in the memory 110 as words. In this example, the memory 110 is configured to store a first count 115a associated with a first pixel 105a, a second count 115b associated with a second pixel 115b, and a third count 115c associated with a third pixel 105c.

[0106] In some embodiments, each count 115a, 115b, 115b may correspond to a value of a binary counter, as described in more detail below with reference to the examples of FIGS.

[0107] In some embodiments, each count 115a, 115b, 115b may correspond to a value or code representing a state of a linear feedback shift register (LFSR), as described in more detail below with reference to examples in Figures 2, 3, and 5.

[0108] The memory 110 is also configured to store a number of saturation bits. In this example, the memory 110 is configured to store a first saturation bit 120a associated with the first count 115a, a second saturation bit 120b associated with the second count 115b, and a third saturation bit 120c associated with the third count 115c.

[0109] The macropixel 100 also includes a saturation detection circuit 125 configured to gate the recharging of each SPAD in each pixel 105a, 105b, 105c based on the state of the respective saturation bit 120a, 120b, 120c, i.e., signals 125a, 125b, 125c are provided by the saturation detection circuit 125 to each pixel 105a, 105b, 105c based on the state of the respective saturation bit 120a, 120b, 120c to control the operation of each pixel 105a, 105b, 105c.

[0110] The macropixel 100 also includes a processing circuit 130. Although the processing circuit 130 is illustrated in Figure 1 as a feature of the macropixel 100, in other examples, the macropixel 100 may be directly coupled to the processing circuit 130 that is not a feature of the macropixel 100. For example, two or more macropixels 100 may be coupled to a common processing circuit 130.

[0111] In an example, the processing circuit 130 may be configured to read out each count 115a, 115b, 115c and each associated saturation bit 120a, 120b, 120c at the end of a frame time.

[0112] In an example, the processing circuitry may be configured to read each count 115a, 115b, 115b by clocking each pixel 105a, 105b, 105c for at least a number of cycles corresponding to the number of memory cells associated with the pixel 105a, 105b, 105c while holding each pixel 105a, 105b, 105c in a reset state.

[0113] In the example, the processing circuit 130 may be further configured to read a saturation bit 120a, 120b, 120c associated with each count 115a, 115b, 115b.

[0114] The macropixel 100 may be configured such that access to the memory 100 by each pixel 105a, 105b, 105c may be in a time multiplexed manner, such as in a round robin manner, as will be described in more detail below.

[0115] The operation of the macropixel 100 will now be described in more detail with reference to corresponding specific embodiments of FIGS.

[0116] FIG. 2 shows a block diagram of a macropixel 200 according to a further embodiment of the present disclosure.

[0117] Macropixel 200 comprises a number of pixels 205 labeled "Nx High-Z SPAD Front-ends."

[0118] The term "SPAD front-end" is understood to refer to a SPAD-based pixel, e.g., a SPAD with circuitry associated with that SPAD. For example, such associated circuitry may include circuitry for sampling and holding voltage levels, circuitry for resetting the SPAD, circuitry for quenching the SPAD, etc., as described in more detail below. The high impedance "High-Z" state of each pixel is described below with reference to FIG. 3.

[0119] The exemplary macropixel 200 comprises a DRAM memory 210. The memory 210 is configured to store N×counts, e.g., values ​​that can be used by an associated counter circuit 235 to implement a counter, each count having M bits. Thus, the memory 210 is denoted as an “N×Mbit Memory.”

[0120] The memory 210 is also configured to store N×saturation bits 220, a saturation bit 220 associated with each count.

[0121] Each count stored in memory 210 corresponds to a value representing a state of a linear feedback shift register (LFSR). An exemplary counter circuit 235 includes LFSR logic, e.g., logic to perform XOR feedback and shift operations, and counter circuit 235 is provided to update the counts.

[0122] As noted above, an LFSR is implemented for illustrative purposes only, and alternative or additional circuitry may be implemented, i.e., the photon counting increment circuit may be implemented as a binary counter, an LFSR, or another circuit configured to increment, decrement, or otherwise advance or sequence defined states.

[0123] The macropixel 100 also includes a saturation detection circuit 225 configured to detect whether any of the N× counts have saturated, set a respective saturation bit 220, and further gate the recharging of each SPAD of each of the N× pixels 205 based on the state of the respective saturation bit 220.

[0124] That is, a signal (not shown in FIG. 2) is provided by saturation detection circuit 225 to each of N× pixels 205 to control the operation of each of N× pixels 205 based on the state of respective saturation bit 220 .

[0125] Also shown in FIG. 2 is an N× read-write precharge control circuit 250 for controlling access by the N× pixels 205 to the N×M memory 210, as will be described in more detail with reference to FIG.

[0126] The N× read-write precharge control circuit 250 provides precharge, read, and write signals to the memory 210 to synchronize the signals received from each of the N× pixels 205, <n-1:0>" to enable updating of the count stored in memory 210 upon receipt of a signal "Rst" to hold the SPAD of each of the N× pixels 205 in a reset state, as described below with reference to the more detailed embodiment of FIGS. <n-1:0>" is also shown.

[0127] 3, there is shown a circuit diagram of a macropixel 300 implemented using an LFSR and DRAM. The circuit diagram of the macropixel 300 generally corresponds to the exemplary macropixel 200 of FIG.

[0128] Macropixel 300 comprises N× pixels, but for purposes of illustration only a single pixel 305 is shown. Pixel 305 corresponds to one of the “N× High-Z SPAD Front-ends” of macropixel 200 of FIG.

[0129] The exemplary macropixel 300 comprises a DRAM memory 310. The memory 310 is configured to store N×counts, e.g., values ​​that can be used in an associated counter circuit 335 to implement a counter, each count having M bits. Thus, the memory 310 comprises an N×M configuration of memory cells for storing N×counts, each count having M bits.

[0130] In the example of FIG. 3, each memory cell is implemented as a three-transistor (3T) cell. It will be appreciated that in other embodiments, each DRAM cell may be implemented as, for example, either a two-, three-, or four-transistor configuration. Additionally, in embodiments, the cells may be implemented as either NMOS or PMOS gain cells. Additionally, other high density memory types may be implemented, for example, 1T1C trench DRAM memory cells.

[0131] In the exemplary N×M configuration of memory cells of Figure 3, each memory cell includes a first transistor, a second transistor, and a third transistor, where the first and second transistors are connected in series to a bit line bi<1:k-1>, the third transistor is connected between an input line bi<0:k-2> and the gate of the first transistor, and the first transistor effectively functions as a storage node.

[0132] A read signal Rd<0:n-1> supplies a control signal to the gate of each second transistor, and a write signal Wr<0:n-1> supplies a control signal to the gate of each third transistor.

[0133] When reading data from a cell having bits 0 to n, a read signal Rd<0:n-1> is asserted, and the data can be read via the corresponding bit line bi<1:k-1>.

[0134] When a count is to be incremented, e.g., written, write signal Wr<0:n-1l> is asserted and data from input lines bi<0:k-2> can be written to the corresponding memory cells. Each count can be maintained by periodic refresh operations of the DRAM memory cells until a new count is written.

[0135] Each count stored in memory 310 corresponds to a value representing a state of a Linear Feedback Shift Register (LFSR). Counter circuit 335 includes XOR feedback logic to implement the LFSR to sequentially update the counts stored in memory 310. As shown in Figure 3, each bit line "bi" is provided to an XOR gate as a feedback signal to increment the LFSR.

[0136] The memory 310 also comprises memory cells configured to store N×saturation bits 320, a saturation bit 320 associated with each count.

[0137] The first and second transistors of each saturation bit are connected in series to the saturation signal "sat", and the third transistor of each saturation bit is connected between the input line "nextSatb" and the gate of the respective first transistor of each saturation bit, with the first transistor effectively functioning as a storage node.

[0138] A read signal Rd<0:n-1> provides a control signal to the gate of each second transistor of the saturation bit 320 , and a write signal Wr<0:n-1> provides a control signal to the gate of each third transistor of the saturation bit 320 .

[0139] The “nextSatb” signal is generated by a saturation detection circuit 325 configured to detect whether any of the N× counts have saturated, set a respective saturation bit 320, and further gate the recharging of each SPAD of each of the N× pixels 305 based on the state of the respective saturation bit 320.

[0140] FIG. 3 also illustrates a memory access control circuit 340 for generating read signals Rd<0:n-1> and write signals Wr<0:n-1> to perform count increment / decrement and refresh operations according to some embodiments of the present disclosure.

[0141] The exemplary pixel 305 comprises a SPAD 350. As is known in the art, operation of the SPAD 350 is based on the pn junction of the SPAD 350 being biased beyond its breakdown region, known as operation in the "Geiger" region. A high reverse bias voltage creates an electric field large enough that a single charge carrier brought into the depletion layer of the SPAD 350 by impact ionization due to one or more incident photons can induce the generation of a self-sustaining avalanche current. In use, the avalanche can be "quenched" by a quench circuit to reset the SPAD 350, thereby allowing further photon detection.

[0142] In the exemplary pixel 305, the cathode of the SPAD 350 is coupled to a high voltage supply rail designated VHV. The anode of the SPAD is coupled to a recharge transistor 355, configurable by a signal Vcas coupled to the gate of the recharge transistor 355 to recharge the SPAD 350.

[0143] The exemplary pixel 305 also includes a transmission gate 360. The transmission gate 360 ​​includes a pair of transistors configurable by a sample signal "Smp" to couple the voltage VSPAD generated by the SPAD 350 at the recharge transistor 355 to a capacitor 365. The transmission gate 360 ​​and the capacitor 365 effectively function as a sample and hold circuit. The pixel 305 also includes a sample and hold reset transistor 370 to reset the voltage on the capacitor 365.

[0144] Recharge transistor 355 is gated by a series arrangement of quench transistor 375 and gating transistor 380. The gate of quench transistor 375 is controlled by the "NextSatb" signal described above. The gate of gating transistor 380 is controlled by the "Wrint " signal.

[0145] Clamp diode 385 is provided to limit excessive bias voltage developed across SPAD 350 and prevent damage to SPAD 350 during use.

[0146] In use, pixel 305 may be operated in a mode known as "high impedance quenching", where after SPAD 350 powers up, e.g., after a photon impact event occurs, pixel 305 is configured to hold the previous voltage on its own parasitic capacitance until transmission gate 360 ​​is configured to allow the SPAD voltage to be transferred to capacitor 365. That is, quenching transistor 375 and gating transistor 380 may be configured to effectively block the quenching path to ground. Thus, pixel 305 may be configured to hold the state, e.g., high impedance quenching, after SPAD 350 powers up high until SPAD 350 is subsequently reset.

[0147] That is, pixel 350 is configured as a "high-Z SPAD quench and sample-and-hold pixel," effectively implementing a dynamic D-type sampler in a compact area.

[0148] For illustrative purposes, several alternative embodiments of the macropixel are also disclosed.

[0149] FIG. 4 shows a circuit diagram of a macropixel 400 implemented using a binary increment circuit and DRAM according to a further embodiment of the present disclosure.

[0150] The features of macropixel 400 generally correspond to those of macropixel 300 of FIG. 3 and therefore will not be described in detail for the sake of brevity.

[0151] 3, the counter circuit 435 of the macropixel 400 comprises binary increment or decrement logic instead of logic for implementing an LFSR. Thus, each count stored in the memory can be incremented or decremented by the counter circuit 435. That is, each bit line "bi" is provided to the binary increment or decrement logic as a feedback signal to increment or decrement each count stored in the memory.

[0152] 3, the saturation detection circuit 425 is also different: in the macropixel 400, the "nextSatb" signal is generated by a saturation detection circuit 425 configured to detect whether any of the N× counts have saturated, set a respective saturation bit 420, and further gate the recharging of each respective SPAD of the N× pixel 405 based on the state of the respective saturation bit 420. The detection of saturation is based on detecting the most significant bit (MSB) carry bit being set, indicating that the respective count has reached a maximum (or minimum, in the case of decrementing) value.

[0153] The selection of an LFSR implementation as shown in FIG. 3 or a binary increment / decrement implementation as shown in macrocell 400 may be based on a range of factors.

[0154] As mentioned above, the LFSR requires the implementation of XOR feedback logic, which in one example may be implemented in about 16 transistors (16T) along with logic for the shift operation. This allows the overall transistor count of the macropixel to be reduced compared to a binary increment / decrement implementation. However, the LFSR may require the implementation of an LFSR-binary decode circuit. Such an LFSR-binary decode circuit may be implemented outside the pixel area of ​​the macrocell.

[0155] Similarly, binary increment / decrement can be implemented with a chain of full adder circuits, which may present the drawback of a relatively large area overhead compared to an LFSR implementation. An exemplary implementation of a binary increment / decrement circuit may have approximately 44 transistors per count, i.e., N×44T, and may further exhibit carry chain settling delays.

[0156] The area per SPAD of the associated circuitry for incrementing / decrementing the counts and implementing saturation detection can be arbitrarily reduced by the degree of sharing between the counts, e.g., by the size of N. However, a high N may also incur greater time multiplexing and thus a lower maximum SPAD count rate and dynamic range.

[0157] Therefore, design tradeoffs between binary and LFSR implementations may be made based on the particular application requirements and the particular CMOS technology node.

[0158] 5 and 6 correspond generally to FIGS. 3 and 4, respectively, with the memory implemented as SRAM rather than DRAM.

[0159] 5 shows a circuit diagram of a macropixel 500 implemented using an LFSR and an SRAM, according to a further embodiment of the present disclosure. Each SRAM cell is implemented as a six-transistor (6T) SRAM cell. FIG. 6 shows a circuit diagram of a macropixel 600 implemented using a binary increment / decrement circuit and an SRAM, according to a further embodiment of the present disclosure. Each SRAM cell is implemented as a 6T SRAM cell.

[0160] The choice between an SRAM and a DRAM implementation may depend, for example, on the particular CMOS technology node in which the device is fabricated, and the power requirements of a particular application. In either case, an implementation of the counter circuit and the count stored in an SRAM or DRAM memory may be significantly more area efficient than a logical counter, e.g., a D-type flip-flop-based counter implementation.

[0161] For example, the area of ​​one bit of a high density SRAM implemented in CMOS can be about 1 / 20 of that of a single counter D-type flip-flop, the area of ​​one bit of a 3T gain cell DRAM implemented in CMOS can be about 1 / 40 of that of a single counter D-type flip-flop, and the area of ​​one bit of a 1T1C trench DRAM implemented in CMOS can be about 1 / 100 of that of a single counter D-type flip-flop.

[0162] A more detailed comparison of a logical counter based solution rather than the disclosed count stored using memory cells with associated increment / decrement circuitry follows.

[0163] A logical counter might require 20T per bit using standard logic. The readout circuitry might require another 4T per bit. So for an N-bit counter with an extra saturation bit, the area per pixel is:

[0164] Area per pixel = (20+4)(N+1)T+AFE

[0165] Here, "AFE" is the area reserved for the analog front end of the pixel, e.g., a SPAD device.

[0166] In contrast, for the disclosed shared memory based macropixel implementation in which the memory is configured to store M×counts, with each count having N bits and an associated saturation bit, the area per pixel can be expressed as follows:

[0167] Area per pixel = (((N+1) x memory bit size x M) + ((N+1) x memory increment logic) + M x (address logic) (LFSR, state detection and read tristate)) / M

[0168] Assuming that the LFSR, state detection and read tristates comprise 12T+12T+4T=28T, and assuming that the address logic, e.g., memory access control circuit 340, is 2NAND+2NOR=16T per pixel, the area per pixel can be expressed as:

[0169] Area per pixel = (N+1)T / 20+16T+(16N+1)T / M+28T / M+AFE for SRAM

[0170] Applying this to each of the memory types mentioned above, eg, high density SRAM, 3T Gain Cell DRAM, and 1T1C DRAM, the area per pixel can be expressed as follows:

[0171] The area per pixel is (N+1)T / 20+16T+(9N+1)T / M+28T / M+AFE for high density SRAM.

[0172] For a 3T gain cell DRAM, area per pixel = (N+1)T / 40+16T+(9N+1)T / M+28T / M+AFE.

[0173] In the case of 1T1C DRAM+AFE, the area per pixel is (N+1)T / 100+16T+(9N+1)T / M+28T / M+AFE.

[0174] As an exemplary configuration for a macropixel, each count may contain 12 bits (N=12) and memory may be shared 16 ways, e.g., 16 counts (M=16) stored in a macrocell. Based on this exemplary configuration, excluding the AFE of each pixel, the total area contribution per pixel is 312T for the logic counter, 31.4T for the SRAM-based embodiment of FIG. 5, 24.8T for the 3T gain cell DRAM-based embodiment of FIG. 3, and 23.9T for the 1T1C DRAM-based embodiment.

[0175] It can thus be seen that the disclosed embodiments using shared access to a memory array by pixels can require approximately 10 times less area per pixel than a logical counter-based solution, and therefore can reach areas with 10 times higher resolution due to increased pixel density.

[0176] The operation of the macropixels 300, 400, 500, and 600 is as follows.

[0177] The disclosed macropixels 300, 400, 500, 600 are directed to implementing SPAD photon counting with digital circuitry in an extremely compact, e.g., low die size, low power consumption manner. Thus, the disclosed macropixels 300, 400, 500, 600 can take advantage of wafer-scale 3D integration of back-illuminated SPADs located above the digital circuitry, as described in more detail below with reference to FIG. 9b.

[0178] The power consumption of a SPAD-array based image sensor may be higher than that of a pinned photodiode CMOS image sensor because a relatively large charge may be consumed by each SPAD for each detected photon that triggers an avalanche event. This charge may flow through a relatively high bias voltage, thereby correspondingly increasing the power.

[0179] The power consumption of the SPAD can be addressed by keeping the SPAD below its reverse bias breakdown voltage. Thus, embodiments of the present disclosure can utilize a high gain mode, e.g., operation in the Geiger region, with a relatively low duty cycle selected to provide a minimum duration of high gain mode to achieve a desired signal-to-noise ratio (SNR).

[0180] For the exemplary macropixels 300, 400, 500, 600, a target SNR (related to the number of photons and therefore the counting bit depth) can be selected by design and detection of photons can be inhibited when this target count is reached.

[0181] This can be achieved using high impedance quenching and clocked recharging. The SPAD in each pixel may be repeatedly reset with a clock pulse, so that the SPAD is left in a high impedance state, above breakdown, e.g., in Geiger mode. When a photon triggers the avalanche effect in the SPAD, the SPAD discharges its own capacitance, thereby becoming overbiased below breakdown, e.g., in sub-Geiger mode, thus achieving self-quenching.

[0182] The proposed pixel structures, such as pixel 305, achieve single photon counting simultaneously with a relatively high level of compactness and relatively low power consumption.

[0183] The disclosed embodiment relies on the principle of time-multiplexed sharing of counts stored in memory cells, eg, counts 115a, 115b, 115c, and clocked recharging of a time-multiplexed SPAD.

[0184] That is, compared to prior art SPAD-based sensors, better pixel compactness can be achieved by using three mutually complementary elements: The first element is a high-density memory that holds the photon-counting state of multiple pixels, such as the DRAM of the embodiment of Figures 3 and 4, the SRAM of the embodiment of Figures 5 and 6, or advanced memories such as STT-MRAM, PCRAM, etc.

[0185] The second element is the time-multiplexed sharing of memory access and increment logic among multiple SPADs.

[0186] The third element is the increment logic, which is implemented with very low logic overhead, such as the LFSR mentioned above.

[0187] In the disclosed embodiment, the time-multiplexed incrementing of accesses to the shared memory is advantageously combined with a time-multiplexed clocked recharging of the SPADs, which provides a technical advantage over a synchronized global recharging of the SPAD matrix in reducing the peak power consumption from the high voltage supply of each SPAD.

[0188] Referring again to the exemplary embodiment of FIG. 3, the N×SPADs 305 are configured to share access to the N×M bit memory 310 in a round-robin time-multiplexed manner.

[0189] As mentioned above, each SPAD 305 has an individual recharge transistor 355 and a sample and hold circuit provided by a transmission gate 360 ​​and a capacitor 365 .

[0190] During operation, the state of each SPAD305 is monitored, e.g. <n-1:0>" is sampled and held by a sample-and-hold circuit, which is controlled by a round-robin control signal "Smp <n-1:0>" is controlled by.

[0191] Immediately after each SPAD state is sampled, each SPAD is recharged.

[0192] The recharge signal is generated by a saturation bit 320 stored for each detector in memory that indicates whether the stored SPAD count has reached saturation. <n-1:0>That is, the saturation detection circuitry is configured to gate the recharging of each SPAD 305 based on the state of its respective saturation bit 320.

[0193] The memory access control circuit 340, which controls the read, write, and precharge operations for accessing the memory 310, operates based on the signal “Photon <n-1:0>The sampled state, denoted by "," is used to select a single row i of memory 310 that corresponds to the round-robin selected SPAD 305 for increment or decrement.

[0194] Each “Photon” The " signal gates the global ExtRdb and ExtWrb clocks to the memory row specific Rd which respectively reads and writes the incremented / decremented state of the photon count of the ith SPAD. and Wr The increment block, e.g., a counter circuit 335, can be used to generate a signal based on the photon count b It receives the read status of row i and increments its count so that it can be written to row i of memory.

[0195] As mentioned above, in some embodiments, the counter circuit 335 may implement an LFSR, and in some embodiments, the counter circuit 435 may comprise binary increment (or decrement) logic.

[0196] As described, some features of each macropixel 300, 400, 500, 600 may be replicated for each pixel, and some features of each macropixel 300, 400, 500, 600 may be shared by each pixel. For example, each pixel may have an associated m-bit memory for storing an associated count. The use of high density memory cell structures, such as 3T DRAM memory cells, may reduce the area impact of such non-shared features.

[0197] Similarly, each pixel 305 has its own recharge and sample circuitry. As mentioned above, each pixel 305 may be implemented with as few as six transistors: a recharge transistor 355, two transistors to form a transmission gate 360, a sample hold reset transistor 370 controlled by Rdb, a quench transistor 375, and a gating transistor 380.

[0198] Other features that are replicated for each pixel 305 include the memory access control circuit 340. To mitigate the area impact of the memory access control circuit 340, an area efficient circuit is shown in the embodiment of Figures 3-7. For example, for the DRAM-based macrocells 300, 400, the memory access control circuit 340 comprises a NOR gate pair and a NAND gate pair that can be implemented with only 16 transistors per SPAD. For the disclosed SRAM-based macrocells 500, 600, the memory access control circuit comprises only a single NAND and a pair of NORs per SPAD.

[0199] In an exemplary embodiment, saturation detection may be implemented by detecting the final state of the m-bit count.

[0200] In macropixels 300, 400 where LFSR codes are used, an m-input NOR can be used to test if the initial state of the m-bit count is reoccurring.

[0201] In macropixels 500, 600 where binary counting is used, it may be sufficient to test the most significant bit (MSB) carry bit from the counter circuitry, which is stored in an additional memory bit as the saturation bit for each SPAD and can be read out as an indication of the saturation condition.

[0202] Therefore, each SPAD has a memory bit that indicates whether the photon count has reached saturation. If this bit is set, the SPAD is inhibited from being reset and will remain in Sub-Geiger mode, consuming very little power. This is done via the Write This is achieved by a series connection of the nextsatb signal with a nextsatb signal that is generated by detecting saturation of the photon count of the ith SPAD. Advantageously, this series connection implements a conditional open-drain high-Z recharge of the SPAD without additional logic.

[0203] That is, the count saturated SPAD is therefore maintained in a high off state biased below the breakdown voltage, thus saving power for pixels with high detection rates.

[0204] The pixel power consumption is calculated by ExtRdb and ExtWrb as well as Smp <n-1:0>The rates of the signals can be set to a minimum frequency relative to the DRAM leakage, or a maximum frequency relative to the DRAM refresh time 1 / (N*(TRd+TWr)).

[0205] If the saturation bit sat is set, then the state of the SPADs is always sampled to a high level indicating that the SPADs have been fired. This causes the SPAD count to be incremented for every subsequent round robin cycle until the end of the frame, when the saturation bits of all SPADs are reset. The counter state thus indicates the number of round robin refresh cycles from the time of saturation of the individual SPADs to the end of the frame. From this information, i.e. the saturation bit of SPAD i and the counter value of SPAD i, a photon count with a higher dynamic range can be constructed without affecting the signal-to-noise ratio. In an embodiment, the saturation bit set to 1 can indicate that the count should not be interpreted as the number of photon impact events but as the number of recharge cycles until the end of the frame.

[0206] That is, while the recharging of one or more SPADs in one or more of the pixels is gated, the associated one or more counts can be used to indicate the time since the respective saturation bit indicated that the counts have saturated.

[0207] If the saturation bit of SPAD i is not set, the counter value of SPAD i represents the number of detected photons. A SPAD with a high count rate will reach saturation faster and be inhibited sooner, saving the most power.

[0208] At the end of the frame, all the bits from memory 310 can be read out by addressing each memory row in turn. In the LFSR implementation of Figures 3 and 4, this can be achieved by simply clocking each pixel 305 with Rst=1 m times for each row of memory cells, and reading the bit from Dout on an output column wire shared by all pixels 305 on the column. This advantageously has the effect of resetting each row of memory cells simultaneously. The saturation bit Dsat associated with each count is also read out.

[0209] A binary implementation may require adding a tri-state gate for each. Readout can be achieved by a rolling shutter, for example a line-by-line readout of the memory.

[0210] The macropixel may comprise processing circuitry configured to read out each count and each associated saturation bit at the end of a frame time, for example circuitry for reading out each count by addressing each memory row in sequence and clocking each pixel for at least a number of cycles corresponding to the number of memory cells associated with the pixel while holding each pixel in a reset state.

[0211] The DRAM-based macropixel 300, 400 requires a refresh operation. In an embodiment, this may be implemented with additional logic that can increment by 0 if the SPAD 305 does not fire, or add / subtract a predefined number of extra periodic refresh cycles that increment / decrement the memory by a fixed offset to the output code, and then reveal the output code after readout.

[0212] FIG. 7 illustrates a pixel 705 for use in a macropixel according to one embodiment of the present disclosure, and an associated timing diagram.

[0213] In the exemplary pixel 705, the cathode of the SPAD 750 is coupled to a high voltage supply rail designated VHV. The anode of the SPAD is coupled to a recharge transistor 755, configurable by a signal Vcas coupled to the gate of the recharge transistor 755 to recharge the SPAD 750.

[0214] The exemplary pixel 705 also includes a transmission gate 760. The transmission gate 760 couples the voltage VSPAD generated by the SPAD 750 to the recharge transistor 755. The sample signal "Smp ". The transmission gate 760 and the capacitor 765 effectively function as a sample and hold circuit. The pixel 705 also includes a sample and hold reset transistor 770 for resetting the voltage on the capacitor 765.

[0215] Pixel 705 generally corresponds to pixel 305 of FIG. 3, but rather than having separate quenching transistor 375 and gating transistor 380, for simplicity of illustration only a single quenching transistor 775 is shown. The quenching transistor 775 is connected to a signal "SPADRst " controlled by SPADRst =「WrInt &NextSatb".

[0216] The recharge transistor 755 is gated by a quench transistor 775 .

[0217] Clamp diode 785 is provided to limit excessive bias voltage developed across SPAD 750 and prevent damage to SPAD 750 during use.

[0218] In use, pixel 705 can be operated in a mode known as “high impedance quenching”, where after SPAD 750 is actuated, e.g., after a photon strike event occurs, pixel 705 operates such that transmission gate 760 supplies a SPAD voltage V , i.e., configured to allow the SPAD 750 to transfer its charge to the capacitor 765. That is, the quench transistor 775 may be configured to effectively block the quenching path to ground. Thus, the pixel 705 may be configured such that after the SPAD 750 powers up high, the pixel 705 holds that state, e.g., high impedance quenching, until the SPAD 750 is subsequently reset. That is, the pixel 750 is configured as a "high Z SPAD quench and sample and hold pixel," effectively realizing a dynamic D-type sampler in a compact area.

[0219] That is, a macropixel using the disclosed pixel 705 may be configured such that when a photon triggers the SPAD, the SPAD discharges its internal capacitance, thereby bringing the excess bias voltage of the SPAD below the breakdown voltage.

[0220] The operation of pixel 750 is illustrated in the accompanying timing diagram. is periodically negated with a relatively low duty cycle and the sample and hold transmission gate 760 is periodically clocked at the same rate, so that the state of the SPAD, e.g., the voltage VSPAD, can be periodically sampled and it is seen that the pixel remains in the high Z quench state when not sampled.

[0221] In use, signal Photon (As described above, the global RdInt and WrInt clocks are gated to generate the memory row specific Rd Signal and Wr (which may be used to generate a signal) is Smp is held low during the low state of

[0222] In particular, the capacitance of the capacitor Cp is significantly larger than the capacitance of the capacitor 765, so that The charge distribution at the rising edge of maintains the reset SPAD state.

[0223] Signal SPADRst It can be seen that when VSPAD is high, the SPAD 750 is quenched and the voltage VSPAD, which may go high due to, for example, a photon strike event, is reset to a low voltage.

[0224] signal smp If VSPAD is high when is high, the signal Photon It can be seen that is asserted, indicating a photon collision event.

[0225] FIG. 8 shows a timing diagram of an example of a macropixel comprising four pixels, each of which operates according to the pixel description of FIG.

[0226] In particular, the round-robin time multiplexing of pixels is clearly shown, with each pixel's SPADRst Signal and smp The signals are asserted in turn, which causes the VSPAD <0> , V.S.P.A.D. <1> , V.S.P.A.D. <2> , and VSPAD <3> This allows round-robin sampling of the

[0227] Furthermore, the disclosed macropixel configuration allows for the generation of time-resolved information.

[0228] For example, one can assume that each SPAD in a macropixel is held reset for 1 / N of the cycle time due to N-way SPAD sharing. This means that a return laser pulse (e.g. from a VSEL) that falls in the reset window of the i-th SPAD will not generate a signal from distances between i / N and i+1 / N of the distance range. This therefore enables indirect time-of-flight (iToF) type distance calculations.

[0229] This can enable either full resolution intensity mode imaging or macropixel-based distance imaging that can interpret distance. In some examples, it may be possible to achieve both full resolution intensity mode imaging and macropixel-based distance imaging that can interpret distance, since the background light is not affected by the reset-only time-correlated light.

[0230] An exemplary embodiment of 4x4 macropixels (e.g., 16 pixels) effectively allows for a 16-bin histogram. Distance can be interpreted by the pixel with the lowest signal, e.g., the smallest count, that does not integrate the return pulse compared to other pixels that integrate the return pulse 15 / 16 of the time.

[0231] Figure 9a shows a plan view of an example of a sensor 900 comprising a number of macropixels 905-1 through 905-9, according to one embodiment of the present disclosure, and Figure 9b shows a cross-sectional view of the sensor 900 along line AA.

[0232] The sensor 900 may be configured as an image sensor, however, as described above, such a sensor may be capable of determining time-resolved information and therefore may additionally or alternatively be configurable to operate as a time-of-flight sensor.

[0233] In an exemplary embodiment, the sensor 900 includes only nine macropixels 905-1 through 905-9, each of which may be a macropixel 300, 400, 500, or 600 as described above.

[0234] The macropixels 905-1 to 905-9 are formed on a substrate 910. In this example, the macropixels 905-1 to 905-9 are arranged as a regular array of macropixels. Each macropixel 905-1 to 905-9 comprises a plurality of pixels. By way of example only, each macropixel may comprise an array of 4×4 pixels.

[0235] In other embodiments, an array of macropixels may be used to implement a "megapixel array," e.g., an array with hundreds of thousands or millions of pixels with a significant number of macropixels.

[0236] Processing circuitry 915, which may be configured to read out the memory array of each macropixel 905-1 through 905-9 of sensor 900, is also shown.

[0237] Macropixel 900 is formed as a monolithic device, eg, fabricated on a single substrate, rather than being formed by combining multiple discrete devices.

[0238] Due to the compactness of macrocells 905-1 to 905-9, i.e., because the macrocells correspond to the new macrocells 300, 400, 500, 600, the SPAD pitch, and therefore capacitance, can be reduced, thereby reducing the power consumption of the SPAD in each macrocell compared to prior art SPAD arrays.

[0239] 9b, it can be seen that the circuitry for each macropixel 905-1, 905-2, 905-3, e.g., at least the memory arrays 920-1, 920-2, 920-3, is formed within the substrate 910, and that the pixels 925-1, 925-2, 925-3 (or at least the SPADs for those pixels) associated with each macropixel 905-1, 905-2, 905-3 are formed above the respective memory arrays 920-1, 920-2, 920-3. The memory arrays 920-1, 920-2, 920-3 are formed within an area of ​​the substrate 910, and a plurality of pixels 925-1, 925-2, 925-3 are formed directly above the memory arrays 920-1, 920-2, 920-3.

[0240] That is, because the dimensions of the circuitry within each macropixel 905-1, 905-2, 905-3 are very compact, the disclosed macropixels 905-1, 905-2, 905-3 can leverage wafer-scale 3D integration of back-illuminated SPADs located above the digital circuitry, as shown in FIG. 9b.

[0241] As described above, the present disclosure has been described with respect to preferred embodiments, but it should be understood that these embodiments are merely examples and the claims are not limited to these embodiments. Those skilled in the art may make modifications and substitutions in light of the present disclosure, which are considered to fall within the scope of the appended claims. Each feature disclosed or exemplified herein may be incorporated into any embodiment alone or in any suitable combination with any other feature disclosed or exemplified herein. [Explanation of symbols]

[0242] 100 Macropixels 105a 1st pixel 105b Second pixel 105c The third pixel 110 Memory 115a First Count 115b Second Count 115c Third Count 120a First saturation bit 120b Second saturation bit 120c 3rd saturation bit 125 Saturation detection circuit 125a signal 125b signal 125c signal 130 Processing circuit 200 Macropixels 205 N×pixels 210 Memory 235 Counter Circuit 220 N x saturation bits 225 Saturation detection circuit 250 Read-write precharge control circuit 300 Macropixels 305 pixels 310 Memory 335 Counter Circuit 320 saturation bits 325 Saturation detection circuit 340 Memory access control circuit 350 SPAD 355 Rechargeable Transistor 360 Transmission Gate 365 Capacitor 370 Sample Hold Reset Transistor 375 Quench Transistor 380 Gating Transistor 385 Clamp Diode 400 Macropixels 425 Saturation detection circuit 435 Counter Circuit 500 Macropixels 600 Macropixels 705 pixels 750 SPAD 755 Recharge Transistor 760 Transmission Gate 765 Capacitor 770 Sample Hold Reset Transistor 775 Quench Transistor 785 Clamp Diode 900 Sensors 905-1 Macropixel 905-2 Macropixel 905-3 Macropixel 905-4 Macropixel 905-5 Macropixel 905-6 Macropixel 905-7 Macropixel 905-8 Macropixel 905-9 Macropixel 910 Substrate 915 Processing Circuit 920-1 Memory Array 920-2 Memory Array 920-3 Memory Array 925-1 pixels 925-2 pixels 925-3 pixels

Claims

1. A macropixel, a plurality of pixels, each pixel comprising a single photon avalanche diode (SPAD); a memory storing a plurality of counts, each count associated with one pixel of the plurality of pixels; a plurality of saturation bits, each saturation bit being associated with one count of said plurality of counts; a memory configured to store a saturation detection circuit configured to gate recharging of each SPAD based on the state of the respective saturation bit; A macropixel comprising:

2. 2. The macropixel of claim 1, wherein the saturation detection circuitry is configured to gate recharging of a respective SPAD when the respective saturation bit indicates that the associated count has saturated.

3. 2. The macropixel of claim 1, wherein while the recharging of one or more SPADs in one or more pixels of the plurality of pixels is gated, the associated one or more counts are used to indicate a time since the respective saturation bit indicated that the count has saturated.

4. 4. The macropixel of claim 3, wherein the associated one or more counts are used to indicate a number of detected photons while the recharging of one or more SPADs in one or more pixels of the plurality of pixels is not gated.

5. The macropixel of claim 1 , wherein access to the memory by each pixel is provided in a time-multiplexed manner.

6. The macropixel of claim 1 , wherein each SPAD is recharged in a time-multiplexed manner while recharging of the SPADs is not gated.

7. The macropixel of claim 5 , wherein the time multiplexing scheme is a round-robin scheme.

8. 10. The macropixel of claim 1, wherein gating the recharging of each SPAD comprises configuring at least one transistor in the respective pixel to hold the SPAD in sub-Geiger mode.

9. 10. The macropixel of claim 1, wherein each pixel comprises at least one transistor configurable to hold the respective SPAD in a high impedance state while the SPAD is biased in Geiger mode.

10. The macropixel of claim 1 , wherein when a photon triggers a SPAD, the SPAD is configured to discharge its internal capacitance, thereby bringing an excess bias voltage of the SPAD below a breakdown voltage.

11. Each pixel is a recharge transistor configurable to recharge the respective SPAD into the Geiger mode; a sample-and-hold circuit for sampling and holding a voltage corresponding to the state of each of the SPADs; The macropixel of claim 9 , comprising:

12. The macropixel of claim 1 , comprising a shared time-multiplexed memory increment or decrement circuit configured to increment or decrement each count of the plurality of counts.

13. The macropixel of claim 1 , wherein each count corresponds to a value of a binary counter.

14. The macropixel of claim 1 , wherein each count corresponds to a value representing a state of a linear feedback shift register (LFSR).

15. The macropixel of claim 1 , comprising processing circuitry configured to read out each count and each associated saturation bit at the end of a frame time.

16. 16. The macropixel of claim 15, wherein the processing circuitry is configured to read out each count by clocking each pixel for at least a number of cycles corresponding to a number of memory cells associated with the pixel while holding the pixel in a reset state.

17. The macropixel of claim 16 , wherein the processing circuitry is further configured to read the saturation bit associated with each count.

18. 16. The macropixel of claim 15, wherein when the saturation bit associated with a respective count is set and recharging of the associated SPAD is gated, the processing circuitry is configured to use the respective count as an indication of a round-robin refresh cycle since the saturation bit was set.

19. The macropixel of claim 1 , wherein the memory comprises an array of static random access memory (SRAM) cells.

20. The macropixel of claim 1 , wherein the memory comprises an array of dynamic random access memory (DRAM) cells.

21. a refresh circuit for refreshing the DRAM cells, the refresh circuit comprising: If the respective SPAD has not been triggered, incrementing the count by 0; or 21. The macropixel of claim 20, configured to add a predetermined number of extra refresh cycles to the count for subsequent subtraction by processing circuitry.

22. The macropixel of claim 1 formed as a monolithic device.

23. the memory is formed within a region of a substrate; the plurality of pixels are formed directly above the memory; The macropixel of claim 1 .

24. An image sensor comprising an array of macropixels according to any one of claims 1 to 23.

25. A proximity or time-of-flight sensor comprising at least one macropixel according to any one of claims 1 to 23.

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