Display substrate and display device

Abstract

The display substrate 91 includes a base substrate 100, a plurality of pixel circuits, a plurality of first light-emitting elements 13, a plurality of second light-emitting elements 14, and at least one first signal line 21 extending along a first direction X. The base substrate 100 includes a first display region A1 and at least one second display region A2a, A2b. The first display region A1 at least partially surrounds the second display regions A2a, A2b. The first signal line 21 is located in the first display region A1 and is electrically connected to a plurality of pixel circuits in the first display region A1. The first signal line 21 is partitioned into at least two first sub-signal lines 211, 212, 213 by at least one second display region A2a, A2b. Adjacent first sub-signal lines of the at least two first sub-signal lines 211, 212, 213 are electrically connected via a first transfer line 41. At least some of the line segments of the first transfer line 41 are located between the plurality of first pixel circuits 11.

Description

[Technical field]

[0001] The present specification relates to the field of display technology, but is not limited thereto, and in particular to a display substrate and a display device. [Background technology]

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices, which have the advantages of autonomous light emission, wide viewing angle, high contrast ratio, low power consumption, extremely fast response speed, lightweight, bendable, and low cost. Under-display camera technology is a completely new technology proposed to improve the screen occupancy rate of display devices. Summary of the Invention

[0003] The following is a summary of the subject matter described herein. This summary is not intended to limit the scope of protection of the claims.

[0004] An embodiment of the present disclosure provides a display substrate and a display device.

[0005] In one aspect, an embodiment of the present disclosure provides a display substrate including a base substrate, a plurality of pixel circuits, a plurality of first light-emitting elements, a plurality of second light-emitting elements, and at least one first signal line extending in a first direction. The base substrate includes a first display region and at least one second display region, the first display region at least partially surrounding the at least one second display region. The plurality of pixel circuits and the plurality of first light-emitting elements are located in the first display region. The plurality of pixel circuits include a plurality of first pixel circuits and a plurality of second pixel circuits, the plurality of second pixel circuits include a plurality of second effective pixel circuits and a plurality of ineffective pixel circuits. The plurality of second light-emitting elements are located in the at least one second display region. At least one first pixel circuit of the plurality of first pixel circuits is electrically connected to at least one first light-emitting element of the plurality of first light-emitting elements, and the at least one first pixel circuit is configured to drive the emission of the at least one first light-emitting element. At least one second effective pixel circuit among the plurality of second effective pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements, and the at least one second effective pixel circuit is configured to drive emission of the at least one second light-emitting element. At least one first signal line extending in a first direction is located in the first display area and is electrically connected to the plurality of pixel circuits in the first display area, and the first signal line is partitioned into at least two first sub-signal lines by the at least one second display area. Adjacent first sub-signal lines among the at least two first sub-signal lines are electrically connected via a first transfer line, and at least a portion of the first transfer line is located between the plurality of first pixel circuits.

[0006] In some exemplary embodiments, the orthogonal projection of the first transfer line on the base substrate comprises: an overlapping portion exists between an orthogonal projection of the first transfer line on the base substrate and an orthogonal projection of at least one ineffective pixel circuit of the first display area on the base substrate; a positive projection of the first transfer line on the base substrate is located between the first pixel circuits and the second pixel circuits; The orthogonal projection of the first transfer line on the base substrate is located in a peripheral region of the at least one second display region.

[0007] In some exemplary embodiments, the first transfer line includes at least a first line segment, a second line segment, and a third line segment that are connected in sequence, the extension directions of the first line segment and the third line segment are the same, and the extension direction of the second line segment intersects with the extension direction of the first line segment.

[0008] There is an overlapping portion between the orthogonal projections of the first line segment and the third line segment on the base substrate and the orthogonal projections of the multiple invalid pixel circuits of the first display area on the base substrate, and the orthogonal projection of the second line segment on the base substrate is located between the multiple pixel circuits, or there is an overlapping portion between the orthogonal projections of the first line segment, the second line segment, and the third line segment on the base substrate and the orthogonal projections of the multiple invalid pixel circuits of the first display area on the base substrate.

[0009] In some exemplary embodiments, the first line segment, the second line segment, and the third line segment are in the same layer structure, or the first line segment and the third line segment are in the same layer structure and the first line segment and the second line segment are located in different conductive layers.

[0010] In some exemplary embodiments, in a direction perpendicular to the display substrate, the pixel circuit includes at least an active layer, a first gate metal layer, a second gate metal layer, and a first source-drain metal layer provided on the base substrate, and the active layer, the first gate metal layer, and the second gate metal layer of the invalid pixel circuit are all provided intermittently. An orthogonal projection of a second segment of the first transfer line on the base substrate is located in an area where the invalid pixel circuit is located, and there is no overlapping portion between the orthogonal projection of the second segment on the base substrate and the orthogonal projection of the active layer, the first gate metal layer, and the second gate metal layer of the invalid pixel circuit on the base substrate.

[0011] In some exemplary embodiments, a first source-drain metal layer of a disable pixel circuit where there is an overlapping portion with a positive projection of the first line segment or the third line segment of the first transfer line on the base substrate is not electrically connected to an active layer, a first gate metal layer and a second gate metal layer of the disable pixel circuit.

[0012] In some illustrative embodiments, the first line segment and the third line segment of the first transfer line are located on a side of the first source-drain metal layer away from the base substrate, and the second line segment and the first gate metal layer or the second gate metal layer have a same layer structure.

[0013] In some illustrative embodiments, when the orthogonal projection of the first transfer line on the base substrate is located in the edge region of the second display region, a shield wiring is provided in the edge region of the second display region, and the orthogonal projection of the shield wiring on the base substrate covers the orthogonal projection of the first transfer line on the base substrate.

[0014] In some exemplary embodiments, the at least one first signal line includes at least one of a light emission control line, a first reset control line, a second reset control line, a scan line, a first initial signal line, and a second initial signal line.

[0015] In some exemplary embodiments, the display substrate further includes at least one second signal line located in the first display area and extending in a second direction, the second direction intersecting the first direction, the second signal line being divided into at least two second sub-signal lines by the at least one second display area, and adjacent second sub-signal lines of the at least two second sub-signal lines are electrically connected via a second transfer line.

[0016] In some exemplary embodiments, the at least one second signal line includes a data line.

[0017] In some exemplary embodiments, in a direction perpendicular to the display substrate, the second transfer line is located on a side of the second signal line closer to the base substrate.

[0018] In some exemplary embodiments, the first transfer line is located on a side of the second transfer line away from the second display area.

[0019] In some exemplary embodiments, an orthogonal projection of the second transfer line on the base substrate is located in an edge region of the second display area, a shield wiring is provided in the edge region of the second display area, and the orthogonal projection of the shield wiring on the base substrate covers the orthogonal projection of the second transfer line on the base substrate.

[0020] In some exemplary embodiments, the shield wire is electrically connected to a first power wire.

[0021] In some exemplary embodiments, the multiple first signal lines are divided into two groups, the second display area has opposing first and second sides in a second direction, the first signal lines of the first group bypass the second display area from a first side thereof via the first transfer lines, and the first signal lines of the second group bypass the second display area from a second side thereof via the first transfer lines, and the second direction intersects with the first direction.

[0022] In some exemplary embodiments, the base substrate includes two second display areas, and the second display areas are aligned in the first direction.

[0023] In some exemplary embodiments, the first signal line is partitioned into three first sub-signal lines by the two second display areas, the first first sub-signal line and the second first sub-signal line are electrically connected via a first first transfer line, and the second first sub-signal line and the third first sub-signal line are electrically connected via a second first transfer line. The first first transfer line bypasses a first second display area, and the second first transfer line bypasses a second second display area.

[0024] In some exemplary embodiments, the first first transfer line and the second first transfer line are located on the same side of the two second display areas in a second direction, and the second direction intersects with the first direction.

[0025] In another aspect, an embodiment of the present disclosure provides a display device comprising the display substrate described above.

[0026] Other aspects may be understood after reading and understanding the drawings and detailed description. [Brief description of the drawings]

[0027] [Figure 1] FIG. 2 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Diagram 2] FIG. 2 is an equivalent circuit diagram of a pixel circuit in accordance with at least one embodiment of the present disclosure. [Diagram 3] 3 is an operation timing chart of the pixel circuit shown in FIG. 2. [Figure 4] FIG. 2 is a schematic diagram of local wiring in a first display area in accordance with at least one embodiment of the present disclosure. [Diagram 5] 2 is a schematic diagram of a pixel circuit layout in a first display region according to at least one embodiment of the present disclosure. [Figure 6] FIG. 2 is a schematic diagram of a first signal line arrangement according to at least one embodiment of the present disclosure. [Figure 7] FIG. 2 is another schematic diagram of a first signal line according to at least one embodiment of the present disclosure. [Figure 8] 8 is a partial plan view of the display substrate in region P1 of FIG. 7. [Figure 9] 9 is a schematic local cross-sectional view taken along the R-R' direction in FIG. 8. FIG. [Figure 10A] 9 is a partial schematic plan view of the display substrate after the semiconductor layer in FIG. 8 is formed. [Figure 10B] 9 is a partial schematic plan view of the display substrate after the first conductive layer in FIG. 8 has been formed. [Figure 10C] 9 is a partial schematic plan view of the display substrate after the second conductive layer in FIG. 8 has been formed. [Figure 10D]9 is a partial schematic plan view of the display substrate after the third insulating layer in FIG. 8 has been formed. FIG. [Figure 10E] 9 is a partial schematic plan view of the display substrate after the third conductive layer in FIG. 8 has been formed. FIG. [Figure 10F] 9 is a partial schematic plan view of the display substrate after a fourth insulating layer is formed in FIG. 8. FIG. [Figure 11] FIG. 2 is a schematic diagram of a second signal line arrangement in at least one embodiment of the present disclosure. [Figure 12] FIG. 2 is another schematic diagram of a second signal line according to at least one embodiment of the present disclosure. [Figure 13] 13 is a partial schematic plan view of the display substrate in region P2 of FIG. 12. FIG. [Figure 14] 14 is a partial schematic plan view of the display substrate after the third conductive layer in FIG. 13 has been formed. FIG. [Figure 15] FIG. 2 is a schematic diagram illustrating the layout of a first initial signal line and a second initial signal line in at least one embodiment of the present disclosure. [Figure 16] FIG. 2 is another schematic diagram of a pixel circuit of a first display area according to at least one embodiment of the present disclosure. [Figure 17] FIG. 2 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 18] 18 is a schematic diagram of the wiring of the transparent conductive lines in region P3 of FIG. 17. [Figure 19] FIG. 2 is another schematic diagram of a wiring layout of a first signal line in accordance with at least one embodiment of the present disclosure. [Figure 20] FIG. 2 is a partial plan view of a display substrate in accordance with at least one embodiment of the present disclosure. [Figure 21] FIG. 2 is another partial plan view of a display substrate in accordance with at least one embodiment of the present disclosure. [Figure 22] 2 is a partially enlarged schematic diagram of a connection position between a first line segment and a second line segment of a first transfer line in at least one embodiment of the present disclosure. FIG. [Figure 23] FIG. 2 is another schematic diagram of a first signal line according to at least one embodiment of the present disclosure. [Figure 24] FIG. 2 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Diagram 25]25 is a schematic diagram of a first signal line in FIG. 24. [Figure 26] FIG. 2 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 27] FIG. 27 is a schematic diagram of the second signal line in FIG. 26. [Figure 28] FIG. 2 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 29] 1 is a schematic diagram of a display device in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The drawings are for better understanding of the technical solution of the present disclosure, and constitute a part of the specification, and are used to explain the technical solution of the present disclosure together with the embodiments of the present application, and are not intended to limit the technical solution of the present disclosure. The shape and size of one or more components in the drawings are for the purpose of merely providing a schematic description of the present disclosure and do not reflect the true ratio.

[0029] The following is a detailed description of the embodiments of the present disclosure with reference to the drawings. The embodiments can be implemented in a number of different forms. Those skilled in the art can easily understand that the method and content can be converted into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to only those described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined unless they conflict.

[0030] In the drawings, the size, thickness or area of ​​one or more components may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the dimensions, and the shape and size of one or more parts in the drawings do not reflect the true ratio. In addition, the drawings are schematic illustrations of ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, etc. shown in the drawings.

[0031] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion of components and are not intended to limit the quantity. In this disclosure, "plurality" means a number of two or more.

[0032] In this specification, for convenience, the positional relationship of components is described with reference to the drawings using words and phrases indicating orientation or positional relationship such as "center", "top", "bottom", "front", "back", "vertical", "horizontal", "upper", "bottom", "inner", "outer", etc., but this is merely to facilitate and simplify the description of this specification, and does not indicate or imply that the device or element referred to has a specific orientation, is configured in a specific orientation, and must operate, so it is not considered to limit the present disclosure. The positional relationship of components is appropriately changed depending on the direction of the described components. Therefore, it is not limited to the words and phrases described in the description, and can be appropriately changed depending on the situation.

[0033] In this specification, unless otherwise clearly specified and limited, the terms "attached", "connected" and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection, or it may be a mechanical connection or connection. It may be a direct connection, an indirect connection via middleware, or communication inside two elements. For those skilled in the art, the meaning of the above terms in this disclosure can be understood according to the situation.

[0034] In this specification, "electrical connection" includes cases where components are connected via an element having some electrical action. The "element having some electrical action" is not particularly limited as long as it allows transmission of an electrical signal between the components to be connected. Examples of the "element having some electrical action" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.

[0035] In this specification, a transistor refers to an element that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and a current can flow through the drain, the channel region, and the source. In this specification, a channel region refers to a region through which a current mainly flows.

[0036] In this specification, the first pole may be the drain and the second pole may be the source, or the first pole may be the source and the second pole may be the drain. The functions of "source" and "drain" may be interchanged, such as when using transistors with reversed polarity or when the direction of current flow during circuit operation is changed. Thus, in this specification, "source" and "drain" may be interchanged. The gate may also be referred to as the control pole.

[0037] In this specification, "parallel" refers to a state in which the angle between two lines is between -10° and 10°, inclusive, including a state in which the angle is between -5° and 5°, inclusive. "Perpendicular" refers to a state in which the angle between two lines is between 80° and 100°, inclusive, including a state in which the angle is between 85° and 95°, inclusive.

[0038] The shapes such as triangles, rectangles, trapezoids, pentagons, and hexagons in this specification are not strictly defined, and may be approximate triangles, rectangles, trapezoids, pentagons, and hexagons, and may have some small deformations due to tolerances, and may have chamfers, arc edges, deformations, and the like.

[0039] In this disclosure, "light transmittance" refers to the ability of light to pass through a medium, and is the ratio of the luminous flux transmitted through a transparent or semitransparent body to the luminous flux incident thereon.

[0040] In this disclosure, the terms "about" and "approximately" refer to cases where the limits are not strictly defined but are within the allowable range of process and measurement errors. In this disclosure, "almost the same" refers to cases where the difference in values ​​is within 10%.

[0041] An embodiment of the present disclosure provides a display substrate including a base substrate, a plurality of pixel circuits, a plurality of first light-emitting elements, a plurality of second light-emitting elements, and at least one first signal line. The base substrate includes a first display region and at least one second display region, the first display region at least partially surrounding the at least one second display region. The plurality of pixel circuits and the plurality of first light-emitting elements are located in the first display region. The plurality of pixel circuits include a plurality of first pixel circuits and a plurality of second pixel circuits, the plurality of second pixel circuits include a plurality of second effective pixel circuits and a plurality of ineffective pixel circuits. The plurality of second light-emitting elements are located in the at least one second display region. At least one of the plurality of first pixel circuits is electrically connected to at least one of the first light-emitting elements, the at least one first pixel circuit being configured to drive the emission of the at least one first light-emitting element. At least one second effective pixel circuit among the plurality of second light-emitting elements is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements, and the at least one second effective pixel circuit is configured to drive emission of the at least one second light-emitting element. At least one first signal line extending in a first direction is located in a first display area and electrically connected to the plurality of pixel circuits in the first display area, and the first signal line is partitioned into at least two first sub-signal lines by at least one second display area. Adjacent first sub-signal lines among the at least two first sub-signal lines are electrically connected via a first transfer line, and at least a portion of the first transfer line is located between the plurality of first pixel circuits.

[0042] In the display substrate according to the present embodiment, the first sub-signal lines adjacent to the first signal line are connected by the first transfer line, thereby ensuring signal transmission of the first signal line, for example, supporting bilateral driving. At least some of the line segments of the first transfer line are located between the first pixel circuits, for example, in the region where the ineffective pixel circuits are located, in the space between the pixel circuits, or in the edge region of the second display area, thereby enabling the space to be reasonably arranged and ensuring the size of the second display area.

[0043] In some exemplary embodiments, the orthogonal projection of the first transfer line on the base substrate is: an overlapping portion exists between an orthogonal projection of the first transfer line on the base substrate and an orthogonal projection of at least one ineffective pixel circuit of the first display area on the base substrate; The orthogonal projection of the first transfer line on the base substrate is located between the plurality of first pixel circuits and the plurality of second pixel circuits; The orthogonal projection of the first transfer line on the base substrate can be located in a peripheral region of at least one second display region.

[0044] In some examples, there may be an overlapping portion between the orthogonal projection of the at least one first transfer line on the base substrate and the orthogonal projection of the at least one invalid pixel circuit on the base substrate. In another example, the orthogonal projection of the at least one first transfer line on the base substrate may be located between adjacent pixel circuits. In another example, there may be an overlapping portion between the orthogonal projection of a portion of the at least one first transfer line on the base substrate and the orthogonal projection of the at least one invalid pixel circuit on the base substrate, and the orthogonal projection of the other portion of the base substrate may be located between adjacent pixel circuits. In another example, there may be an overlapping portion between the orthogonal projection of a portion of the at least one first transfer line on the base substrate and the orthogonal projection of the at least one invalid pixel circuit on the base substrate, and the orthogonal projection of the other portion of the base substrate may be located in the edge region of the second display region. In another example, there may be an overlapping portion between the orthogonal projection of a portion of the at least one first transfer line on the base substrate and the orthogonal projection of the at least one invalid pixel circuit on the base substrate, and the orthogonal projection of the other portion of the base substrate may be located in the edge region of the second display region. In some examples, the edge region of the second display region may refer to a region around the light-emitting elements of the second display region where no pixel circuits are provided.

[0045] In some examples, the number of the second display areas may be one, two, or more, but this embodiment is not limited thereto.

[0046] In some examples, by setting an overlap between the orthogonal projection of the first transfer line on the base substrate and the orthogonal projection of at least one ineffective pixel circuit on the base substrate, the first transfer line does not need to occupy the space for arranging the effective pixel circuit and the space of the second display area, thereby ensuring both the supply of drive signals to the pixel circuits and the size of the second display area.

[0047] In some exemplary embodiments, the first transfer line may include at least a first line segment, a second line segment, and a third line segment that are connected in sequence. The first line segment and the third line segment may extend in the same direction, and the second line segment may extend in a direction that intersects with the first line segment. For example, the second line segment may extend perpendicular to the first line segment.

[0048] In some exemplary embodiments, there may be an overlapping portion between the orthogonal projection of the first and third line segments of the first transfer line on the base substrate and the orthogonal projection of the multiple invalid pixel circuits of the first display area on the base substrate, and the orthogonal projection of the second line segment on the base substrate is located between the multiple pixel circuits. Alternatively, there is an overlapping portion between the orthogonal projection of the first, second, and third line segments on the base substrate and the orthogonal projection of the multiple invalid pixel circuits of the first display area on the base substrate. For example, the first and third line segments may have the same layer structure, and the second line segment may be located on the side of the first line segment closer to the base substrate. However, this embodiment is not limited thereto.

[0049] In some exemplary embodiments, the first line segment, the second line segment, and the third line segment of the first transfer line may be located on a side of the first signal line away from the base substrate. For example, the first line segment, the second line segment, and the third line segment of the first transfer line may have a same layer structure. In other words, the first transfer line may have an integral structure. However, this embodiment is not limited thereto.

[0050] In some exemplary embodiments, in a direction perpendicular to the display substrate, the pixel circuit may include an active layer, a first gate metal layer, a second gate metal layer, and a first source-drain metal layer provided on the base substrate. The active layer, the first gate metal layer, and the second gate metal layer of the invalid pixel circuit may all be provided discontinuously. The active layer of the invalid pixel circuit may be discontinuous, the first gate metal layer may be discontinuous, and the second gate metal layer may be discontinuous. The orthogonal projection of the second segment of the first transfer line on the base substrate may be located in a region where the invalid pixel circuit is located, and there may be no overlap between the orthogonal projection of the second segment of the first transfer line on the base substrate and the active layer, the first gate metal layer, and the second gate metal layer of the invalid pixel circuit on the base substrate. In some examples, the first gate metal layer may include a gate of a transistor of the pixel circuit and a first capacitor plate of a storage capacitor, the second gate metal layer may include a second capacitor plate of the storage capacitor of the pixel circuit, and the first source-drain metal layer may include a plurality of connection electrodes. In this example, by removing a portion of the film layer structure of the ineffective pixel circuit, it is possible to provide a space for arranging the second line segment, and the capacitance of the second line segment can be reduced.

[0051] In some exemplary embodiments, the first source-drain metal layer of the inactive pixel circuit, which has a portion overlapping with the orthogonal projection of the first line segment or the third line segment of the first transfer line on the base substrate, may not be electrically connected to the active layer, the first gate metal layer, and the second gate metal layer of the inactive pixel circuit. In this example, by removing a portion of the film layer structure of the inactive pixel circuit, it is possible to provide a placement space for the first line segment and reduce the capacitance of the first line segment.

[0052] In some exemplary embodiments, the first and third segments of the first transfer line may be located on the side of the first source-drain metal layer away from the base substrate, and the second segment and the first or second gate metal layer may have the same layer structure, but this embodiment is not limited thereto.

[0053] In some exemplary embodiments, the at least one first signal line may include at least one of an emission control line, a first reset control line, a second reset control line, a scan line, a first initial signal line, and a second initial signal line. For example, the first signal line may include an emission control line and a first reset control line.

[0054] In some exemplary embodiments, the orthogonal projection of the first transfer line on the base substrate may be located in the edge region of the second display region. A shielding wiring may be provided in the edge region of the second display region, and the orthogonal projection of the shielding wiring on the base substrate may cover the orthogonal projection of the first transfer line on the base substrate. In this example, the first signal line can be realized as a winding in the edge region of the second display region, the load of the first signal line can be reduced, and the display uniformity can be improved. In addition, by shielding the first transfer line in the edge region of the second display region via the shielding wiring, the interference situation due to the gap between the multiple first transfer lines can be improved.

[0055] In some exemplary embodiments, the display substrate may further include at least one second signal line located in the first display region and extending in a second direction. The second direction may cross the first direction. The second signal line may be divided into at least two second sub-signal lines by the at least one second display region. Adjacent second sub-signal lines of the at least two second sub-signal lines may be electrically connected via a second transfer line. In this example, the second transfer line allows the second signal line to bypass the second display region and avoid occupying space in the second display region.

[0056] In some exemplary embodiments, at least one second signal line may include a data line. However, this embodiment is not limited thereto. In other examples, the second signal line may include an initial signal line (e.g., a first initial signal line, a second initial signal line).

[0057] In some exemplary embodiments, in a direction perpendicular to the base substrate, the second transfer line may be located on a side of the second signal line closer to the base substrate. However, this embodiment is not limited thereto. For example, the second transfer line may be located on a side of the second signal line farther from the base substrate.

[0058] In some exemplary embodiments, the first transfer line may be located on the side of the second transfer line that is farther away from the second display area, which can effectively avoid wiring crossing.

[0059] In some exemplary embodiments, the orthogonal projection of the second transfer line on the base substrate may be located in the edge region of the second display region. A shielding wiring may be provided in the edge region of the second display region. The orthogonal projection of the shielding wiring on the base substrate may cover the orthogonal projection of the second transfer line on the base substrate. In this example, the second signal line can be realized as a winding in the edge region of the second display region, the load of the second signal line can be reduced, and the uniformity of the display can be improved. In addition, by shielding the second transfer line in the edge region of the second display region via the shielding wiring, the interference situation due to the gap between the multiple second transfer lines can be improved.

[0060] In some exemplary embodiments, the shielding wire may be electrically connected to the first power supply wire. However, this embodiment is not limited thereto. For example, the shielding wire may be electrically connected to another wire that transmits a DC voltage signal.

[0061] In some exemplary embodiments, the plurality of first signal lines may be divided into two groups, and the second display area has a first side and a second side opposite to each other in the second direction. The first signal lines of the first group may bypass the second display area from a first side of the second display area via a first transfer line, and the first signal lines of the second group bypass the second display area from a second side of the second display area via a first transfer line. The second direction intersects with the first direction. In some examples, by setting the plurality of first signal lines to bypass the second display area from both the top and bottom sides of the second display area, it is advantageous to the arrangement of the plurality of first signal lines and the first transfer lines, and the adverse effect of wiring overcrowding is avoided.

[0062] In some exemplary embodiments, the base substrate may include two second display areas, and the second display areas may be aligned in the first direction. However, this embodiment is not limited thereto. For example, the two second display areas may be sequentially arranged along the first direction, and may have a slight misalignment in the second direction.

[0063] The scheme of this embodiment will be described below with some examples.

[0064] FIG. 1 is a schematic diagram of a display substrate in at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in FIG. 1, the display substrate may include a display area AA and a peripheral area BB surrounding the periphery of the display area AA. The display area AA of the display substrate may include a first display area A1 and two second display areas (e.g., second display areas A2a, A2b). The first display area A1 may be located on at least one side of the two second display areas A2a, A2b. For example, the first display area A1 may surround the periphery of the two second display areas A2a, A2b. However, this embodiment is not limited thereto. For example, the first display area A1 may surround the periphery of the second display area A2a and partially surround the second display area A2b, or the first display area A1 may partially surround the second display area A2a and partially surround the second display area A2b.

[0065] In some exemplary embodiments, as shown in FIG. 1, the display area AA may be a rectangle, such as a rectangle with rounded corners. The second display areas A2a and A2b may be a rectangle, such as a rectangle with rounded corners. However, this embodiment is not limited thereto. For example, the display area AA may be other shapes, such as a circle, an ellipse, or a pentagon. Also, for example, the second display area may be other shapes, such as a circle, an ellipse, a semicircle, or a pentagon.

[0066] In some exemplary embodiments, as shown in FIG. 1, the two second display areas A2a, A2b may be arranged sequentially along the first direction X. For example, the two second display areas A2a, A2b may have the same shape and size, may be aligned in the first direction X, and may not be misaligned in the second direction Y. For example, the distance from the upper edge of the second display areas A2a, A2b to the upper edge of the display area AA may be the same. In some examples, the first direction X and the second direction Y may intersect, for example, the first direction X may be perpendicular to the second direction Y. However, this embodiment is not limited thereto. For example, the shapes or sizes of the two second display areas A2a, A2b may be different. Also, for example, the two second display areas A2a, A2b may be misaligned in the second direction Y, for example, the distance from the upper edge of the second display area A2a to the upper edge of the display area AA may be equal to or less than the distance from the upper edge of the second display area A2b to the upper edge of the display area AA.

[0067] In some exemplary embodiments, as shown in FIG. 1, the two second display areas A2a, A2b may be light-transmitting display areas and may be referred to as under-display camera (UDC) areas, and the first display area A1 may be a non-light-transmitting display area and may be referred to as a normal display area. For example, the orthogonal projection of a photosensitive sensor (e.g., hardware such as a camera) on a display substrate may be located within the second display areas A2a, A2b of the display substrate. In some examples, as shown in FIG. 1, the second display area A2a may be a rectangle (e.g., a rounded rectangle), and the size of the orthogonal projection of the photosensitive sensor on the display substrate may be equal to or smaller than the size of the inscribed circle of the second display area A2a. However, this embodiment is not limited thereto. In other examples, the second display area may be a circle, and the size of the orthogonal projection of the photosensitive sensor on the display substrate may be equal to or smaller than the size of the second display area.

[0068] In some exemplary embodiments, as shown in FIG. 1, the two second display areas A2a, A2b may be located in the middle of the upper part of the display area AA. The first display area A1 may surround the periphery of the second display areas A2a, A2b. However, this embodiment is not limited thereto. For example, the two second display areas A2a, A2b may be located in other positions, such as the upper left corner or the upper right corner of the display area AA. For example, the first display area A1 may surround at least one side of the second display area A2a, and the first display area A1 may surround at least one side of the second display area A2b.

[0069] In some exemplary embodiments, a plurality of sub-pixels may be provided in the display area AA. At least one of the sub-pixels may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the light-emitting element connected thereto. For example, the pixel circuit may be configured to provide a driving current for driving the light-emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor, for example, the pixel circuit may have a 3T1C (i.e., three transistors and one capacitor) structure, a 7T1C (i.e., seven transistors and one capacitor) structure, a 5T1C (i.e., five transistors and one capacitor) structure, an 8T1C (i.e., eight transistors and one capacitor) structure, or an 8T2C (i.e., eight transistors and two capacitors) structure, etc. In some examples, the light-emitting element may be an organic light-emitting diode (OLED), and the light-emitting element emits red light, green light, blue light, white light, etc. under the driving of the corresponding pixel circuit. The color emitted by the light-emitting element is determined as required. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit, but this embodiment is not limited thereto.

[0070] In some exemplary embodiments, one pixel unit in the display area AA may include three sub-pixels, and the three sub-pixels may be red, green, and blue sub-pixels, respectively. However, this embodiment is not limited thereto. In some examples, one pixel unit may include four sub-pixels, and the four sub-pixels may be red, green, blue, and white sub-pixels, respectively.

[0071] In some exemplary embodiments, the shape of the light-emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon. When one pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or square manner, and when one pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or square manner. However, this embodiment is not limited thereto.

[0072] 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. FIG. 3 is an operation timing chart of the pixel circuit according to FIG. 2. The pixel circuit according to this exemplary embodiment is described using a 7T1C structure as an example. However, this embodiment is not limited thereto.

[0073] 2, the pixel circuit of this example may include six switching transistors (T1, T2, T4 to T7), one driving transistor T3, and one storage capacitor Cst. The six switching transistors are a data writing transistor T4, a threshold compensation transistor T2, a first emission control transistor T5, a second emission control transistor T6, a first reset transistor T1, and a second reset transistor T7. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0074] In some exemplary embodiments, the driving transistor and the six switching transistors may be P-type transistors or N-type transistors. By adopting the same type of transistors in the pixel circuit, the process flow can be simplified, the process difficulty of the display substrate can be reduced, and the product yield can be improved. In some possible embodiments, the driving transistor and the six switching transistors may include P-type transistors and N-type transistors.

[0075] In some exemplary embodiments, the driving transistor and the six switching transistors can be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin-film transistor uses an oxide semiconductor (Oxide). The low-temperature polysilicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. By integrating the low-temperature polysilicon thin-film transistor and the oxide thin-film transistor on one display substrate to form a low-temperature polycrystalline oxide (LTPO, Low Temperature Polycrystalline Oxide) display substrate, the advantages of both can be utilized, low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

[0076] In some exemplary embodiments, as shown in Fig. 2, the display substrate may include a scan line GL, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In some examples, the first power line PL1 may be configured to supply a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 may be configured to supply a constant second voltage signal VSS to the pixel circuit, where the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GL may be configured to supply a scan signal SCAN to the pixel circuit, the data line DL may be configured to supply a data signal DATA to the pixel circuit, the emission control line EML may be configured to supply an emission control signal EM to the pixel circuit, the first reset control line RST1 may be configured to supply a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 may be configured to supply a second reset control signal RESET2 to the pixel circuit. In some examples, in the pixel circuit of the nth row, the first reset control line RST1 may be electrically connected to the scan line GL of the pixel circuit of the n-1th row so that the scan signal SCAN(n-1) is input, i.e., the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). The second reset control line RST2 may be electrically connected to the scan line GL of the pixel circuit of the nth row so that the scan signal SCAN(n) is input, i.e., the second reset control signal RESET2(n) is the same as the scan signal SCAN(n). In some examples, the second reset control line RST2 electrically connected to the pixel circuits in the nth row and the first reset control line RST1 electrically connected to the pixel circuits in the n+1th row may be integrally formed. Here, n is an integer greater than 0. This allows the number of signal lines on the display substrate to be reduced, and a narrow frame design for the display substrate to be realized. However, this embodiment is not limited to this.

[0077] In some exemplary embodiments, the first initial signal line INIT1 may be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 may be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first initial signal and the second initial signal may be constant voltage signals, the magnitude of which is, for example, but not limited to, between the first voltage signal VDD and the second voltage signal VSS. In other examples, the first initial signal and the second initial signal may be the same, and only the first initial signal line may be provided to provide the first initial signal.

[0078] In some exemplary embodiments, as shown in FIG. 2, the driving transistor T3 is electrically connected to the light-emitting element EL, and outputs a driving current to drive the light-emitting element EL to emit light under the control of signals such as a scan signal SCAN, a data signal DATA, a first voltage signal VDD, and a second voltage signal VSS. The gate of the data write transistor T4 is electrically connected to the scan line GL, the first pole of the data write transistor T4 is electrically connected to the data line DL, and the second pole of the data write transistor T4 is electrically connected to the first pole of the driving transistor T3. The gate of the threshold compensation transistor T2 is electrically connected to the scan line GL, the first pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second pole of the threshold compensation transistor T2 is electrically connected to the second pole of the driving transistor T3. The gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control line EML, the first pole of the first light-emitting control transistor T5 is electrically connected to the first power line PL1, and the second pole of the first light-emitting control transistor T5 is electrically connected to the first pole of the driving transistor T3. The gate of the second emission control transistor T6 is electrically connected to the emission control line EML, the first electrode of the second emission control transistor T6 is electrically connected to the second electrode of the driving transistor T3, and the second electrode of the second emission control transistor T6 is electrically connected to the anode of the light-emitting element EL. The first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and configured to reset the gate of the driving transistor T3, and the second reset transistor T7 is electrically connected to the anode of the light-emitting element EL and configured to reset the anode of the light-emitting element EL. The gate of the first reset transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first reset transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the second reset transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the second reset transistor T7 is electrically connected to the anode of the light-emitting element EL.A first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and a second capacitor plate of the storage capacitor Cst is electrically connected to the first power line PL1.

[0079] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3, and the threshold compensation transistor T2, the second node N2 is the connection point of the first light-emitting control transistor T5, the data write transistor T4, and the driving transistor T3, the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2, and the second light-emitting control transistor T6, and the fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7, and the light-emitting element EL.

[0080] Next, an operation process of the pixel circuit shown in Fig. 2 will be described with reference to Fig. 3. An example will be described in which all of the multiple transistors included in the pixel circuit shown in Fig. 2 are P-type transistors.

[0081] In some exemplary embodiments, as shown in FIG. 3, in one frame display period, the operation process of the pixel circuit may include a first stage S1, a second stage S2, and a third stage S3.

[0082] The first stage S1 is called a reset stage. The first reset control signal RESET1 supplied from the first reset control line RST1 is a low level signal, which turns on the first reset transistor T1, and the first initial signal supplied from the first initial signal line INIT1 is supplied to the first node N1, which initializes the first node N1 and clears the original data voltage of the storage capacitor Cst. The scan signal SCAN supplied from the scan line GL is a high level signal, and the emission control signal EM supplied from the emission control line EML is a high level signal, which turns off the data write transistor T4, the threshold compensation transistor T2, the first emission control transistor T5, the second emission control transistor T6 and the second reset transistor T7. In this stage, the light emitting element EL does not emit light.

[0083] The second stage S2 is called a data write stage or threshold compensation stage. The scan signal SCAN supplied from the scan line GL is a low level signal, the first reset control signal RESET1 supplied from the first reset control line RST1 and the light emission control signal EM supplied from the light emission control line EML are both high level signals, and the data line DL outputs a data signal DATA. In this stage, the first capacitor plate of the storage capacitor Cst is at a low level, so the driving transistor T3 is turned on. The scan signal SCAN is a low level signal, which turns on the threshold compensation transistor T2, the data write transistor T4 and the second reset transistor T7. By turning on the threshold compensation transistor T2 and the data write transistor T4, the data voltage Vdata output by the data line DL is supplied to the first node N1 via the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the driving transistor T3 is charged to the storage capacitor Cst, and the voltage of the first capacitor plate (i.e., the first node N1) of the storage capacitor Cst is Vdata-|Vth|, where Vdata is the data signal DATA output by the data line DL, and Vth is the threshold voltage of the driving transistor T3. The second reset transistor T7 is turned on, and the second initial signal supplied from the second initial signal line INIT2 is supplied to the anode of the light-emitting element EL to initialize (reset) the anode of the light-emitting element EL, clearing the internal pre-stored voltage to complete the initialization, and ensuring that the light-emitting element EL does not emit light. The first reset control signal RESET1 supplied from the first reset control line RST1 is a high level signal, and turns off the first reset transistor T1. The light emission control signal EM supplied from the light emission control signal line EML is a high level signal, which turns off the first light emission control transistor T5 and the second light emission control transistor T6.

[0084] The third stage S3 is called a light-emitting stage. The light-emitting control signal EM supplied from the light-emitting control signal line EML is a low-level signal, and the scan signal SCAN supplied from the scan line GL and the first reset control signal RESET1 supplied from the first reset control line RST1 are high-level signals. The light-emitting control signal EM supplied from the light-emitting control signal line EML is a low-level signal, which turns on the first light-emitting control transistor T5 and the second light-emitting control transistor T6, and the first voltage signal VDD output from the first power line PL1 supplies a driving voltage to the anode of the light-emitting element EL via the first light-emitting control transistor T5, the driving transistor T3, and the second light-emitting control transistor T6 that are turned on, thereby driving the light-emitting element EL to emit light.

[0085] In the driving process of the pixel circuit, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first pole. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is given by the following formula:

[0086] I = K × (Vgs - Vth) 2 =K × [(VDD - Vdata + |Vth|) - Vth] 2 =K × [VDD-Vdata] 2 .

[0087] Here, I is the driving current flowing through the driving transistor T3, i.e., the driving current that drives the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0088] From the above formula, it can be seen that the current flowing through the light emitting element EL is independent of the threshold voltage of the driving transistor T3, so the pixel circuit of this embodiment can satisfactorily compensate for the threshold voltage of the driving transistor T3.

[0089] In some exemplary embodiments, as shown in FIG. 1, a plurality of first light-emitting elements 13 and a plurality of pixel circuits may be provided in the first display area A1, and a plurality of second light-emitting elements 14 may be provided in the second display areas A2a and A2b. The plurality of pixel circuits in the first display area A1 may include a plurality of first pixel circuits 11 and a plurality of second pixel circuits. The plurality of second pixel circuits may include a plurality of second effective pixel circuits 12 and a plurality of ineffective pixel circuits. At least one first pixel circuit 11 in the first display area A1 is electrically connected to at least one first light-emitting element 13, and the at least one first pixel circuit 11 is configured to drive the emission of the at least one first light-emitting element 13. An orthogonal projection of the at least one first pixel circuit 11 in the first display area A1 on the base substrate at least partially overlaps with an orthogonal projection of the at least one first light-emitting element 13 on the base substrate. For example, the first pixel circuit 11 may have a one-to-one correspondence with the first light-emitting element 13. At least one second effective pixel circuit 12 in the first display area A1 and at least one second light-emitting element 14 in the second display area A2a or A2b may be electrically connected via a transparent conductive line L, and the at least one second effective pixel circuit 12 is configured to drive the emission of the at least one second light-emitting element 14. The ineffective pixel circuit may be advantageous for improving the uniformity of components of multiple film layers in an etching process. For example, the ineffective pixel circuit may have the same structure as the first pixel circuit 11 and the second effective pixel circuit 12 in the row or column in which it is located, but it is not connected to any light-emitting element.

[0090] In some exemplary embodiments, as shown in FIG. 1, one end of the transparent conductive line L may be electrically connected to the second effective pixel circuit 12, and the other end may be electrically connected to the second light-emitting element 14. The transparent conductive line L may extend from the first display area A1 to the second display area A2a, or from the first display area A1 to the second display area A2b. For example, the transparent conductive line L may extend from the first display area A1 to the second display area A2a along the first direction X, or the transparent conductive line L may first extend in the first display area A1 along the second direction Y, and then extend to the second display area A2a along the first direction X. The transparent conductive line L may use a transparent conductive material, such as indium tin oxide (ITO). However, this embodiment is not limited thereto. A plurality of transparent conductive lines L may be arranged in one transparent conductive layer, or a plurality of transparent conductive lines L may be arranged in two or three transparent conductive layers. For example, each transparent conductive line L can connect one second effective pixel circuit 12 and one second light-emitting element 14. Also, for example, one second effective pixel circuit 12 and one second light-emitting element 14 can be electrically connected by a plurality of transparent conductive lines L that are connected in sequence.

[0091] In some exemplary embodiments, the light transmittance of the first display region A1 may be smaller than that of the second display regions A2a and A2b. By providing pixel circuits only in the first display region A1 and not providing pixel circuits in the second display regions A2a and A2b, the light transmittance of the second display regions A2a and A2b can be improved.

[0092] In some exemplary embodiments, in order to improve the display effect, the density of the second light-emitting elements 14 in the second display area A2a, A2b may be equal to or lower than the density of the first light-emitting elements 13 in the first display area A1. However, this embodiment is not limited thereto.

[0093] In some exemplary embodiments, the resolution of the first display area A1 may be equal to or less than the resolution of the second display areas A2a and A2b, but this embodiment is not limited thereto.

[0094] FIG. 4 is a schematic diagram of local wiring in the first display area of ​​at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in FIG. 1 and FIG. 4, the first display area A1 of the display substrate may be provided with a plurality of first signal lines 21 and a plurality of third signal lines 22 extending along the first direction X, and a plurality of second signal lines 31 and a plurality of fourth signal lines 32 extending along the second direction Y. The first signal lines 21 and the third signal lines 22 may be electrically connected to a plurality of pixel circuits arranged sequentially in the first direction X. The second signal line 31 is partitioned by the second display area A2a or A2b in the second direction Y. The fourth signal line 32 may be electrically connected to a plurality of first pixel circuits 11 arranged sequentially in the second direction Y, or may be electrically connected to a plurality of ineffective pixel circuits. The first signal line 21 may be divided into three first sub-signal lines by the second display areas A2a and A2b in the first direction X, and adjacent first sub-signal lines may be electrically connected by the first transfer line 41. In some examples, the first signal line 21 and the third signal line 22 may include a scanning line and a light emission control line, and the second signal line 31 and the fourth signal line 32 may include a data line. One end of the third signal line 22 may be electrically connected to a gate driving circuit in a left peripheral area of ​​the display area AA, and the other end may be electrically connected to a gate driving circuit in a right peripheral area of ​​the display area AA. This can realize bilateral driving of the pixel circuits in the first display area and improve the display effect.

[0095] Next, one first signal line 21 will be described as an example. In some examples, as shown in FIG. 4, the first signal line 21 is divided into three first sub-signal lines extending along the first direction X by two second display areas A2a and A2b in the first direction X, and includes, for example, a first first sub-signal line 211, a second first sub-signal line 212, and a third first sub-signal line 213. The first first sub-signal line 211 may be electrically connected to a gate driving circuit in a left peripheral area of ​​the second display area A2a, and may be electrically connected to one row of pixel circuits in the first display area A1 on the left side of the second display area A2a. The second first sub-signal line 212 may be electrically connected to one row of pixel circuits in the first display area A1 between the second display areas A2a and A2b. The third first sub-signal line 213 may be electrically connected to a gate driving circuit in a right peripheral region of the second display area A2b, and may be electrically connected to a row of pixel circuits in the first display area A1 on the right side of the second display area A2b. In some examples, the pixel circuits connected to the first first sub-signal line 211, the second second sub-signal line 212, and the third first sub-signal line 312 may be located in the same row. In this example, the first first sub-signal line 211, the second first sub-signal line 212, and the third first sub-signal line 213 are electrically connected in sequence to realize bilateral driving and improve the display effect. The first first sub-signal line 211 and the second first sub-signal line 212 may be electrically connected via one first transfer line 41, and similarly, the second first sub-signal line 212 and the third first sub-signal line 213 may be electrically connected via another one first transfer line 41.

[0096] 4, the first transfer line 41 electrically connected between the first first sub-signal line 211 and the second first sub-signal line 212 may include at least a first line segment 411 and a third line segment 413 extending along the second direction Y, and a second line segment 412 extending along the first direction X. The second line segment 412 is connected between the first line segment 411 and the third line segment 413. For example, the first line segment 411 may have one end electrically connected to the first first sub-signal line 211 and the other end electrically connected to a first end of the second line segment 412, and the third line segment 413 may have one end electrically connected to the second first sub-signal line 212 and the other end electrically connected to a second end of the second line segment 412.

[0097] In some examples, as shown in FIG. 4, the center line of the second display region A2a in the first direction X is the first midline OO', and the center line in the second direction Y is the second midline QQ'. The plurality of first signal lines 21 partitioned by the second display region A2a may be divided into two groups. The number of first signal lines 21 in the two groups may be the same or different. For example, the plurality of first signal lines 21 may be divided into two groups using the second midline QQ', and the first group may include the plurality of first signal lines 21 located above the second midline QQ', and the second group may include the plurality of first signal lines 21 located below the second midline QQ'. The first signal lines 21 of the first group may bypass the second display area A2a from a first side (e.g., the upper side) in the second direction Y of the second display area A2a via the first transfer line 41, and the other first signal line 21 may bypass the second display area A2a from a second side (e.g., the lower side) in the second direction Y of the second display area A2a via the first transfer line 41. In this example, by transferring the first signal lines from both the upper and lower sides of the second display area, it is possible to prevent the wiring from being densely arranged and affecting the display effect. In some examples, in the area on the second midline QQ' side, the first transfer line 41 electrically connected to the first signal line 21 close to the second midline QQ' may be located on the side closer to the second display area A2a of the first transfer line 41 electrically connected to the first signal line 21 away from the second midline QQ'. This makes it possible to prevent the first transfer lines from crossing each other.

[0098] The connection method between the second first sub-signal line 212 and the third first sub-signal line 213 is almost the same as the connection method between the first first sub-signal line 211 and the second first sub-signal line 212, so it will not be described here. The first transfer line connected to the first first sub-signal line 211 and the first transfer line connected to the third first sub-signal line 213 may be located on the same side in the second direction Y of the second display areas A2a and A2b. However, this embodiment is not limited to this. In another example, the first transfer line connected to the first first sub-signal line 211 and the first transfer line connected to the third first sub-signal line 213 may be located on different sides in the second direction Y of the second display areas A2a and A2b. For example, the first transfer line connected to the first first sub-signal line 211 may be located above the second display region A2a in the second direction Y, and the first transfer line connected to the third first sub-signal line 213 may be located below the second display region A2b in the second direction Y.

[0099] Next, one third signal line 31 will be described as an example. In some examples, as shown in FIG. 4, the third signal line 31 is partitioned by the second display area A2a in the second direction Y. The third signal line 31 may include three second sub-signal lines (for example, a first second sub-signal line 311, a second second sub-signal line 312, and a third second sub-signal line 313). The first second sub-signal line 311 may be electrically connected to a plurality of first pixel circuits in a first display area below the second display area A2a. The second second sub-signal line 312 may be electrically connected to a plurality of second effective pixel circuits in a first display area to the left of the second display area A2a. The third second sub-signal line 313 may be electrically connected to a plurality of first pixel circuits in a first display area above the second display area A2a. For example, the pixel circuits electrically connected to the first second sub-signal line 311 and the third second sub-signal line 313 of the same second signal line 31 may be located in the same column, and the second light-emitting element electrically connected to the second effective pixel circuit electrically connected to the second second sub-signal line 312 of the same second signal line 31 may be located in the same column as the first light-emitting element electrically connected to the first pixel circuit electrically connected to the first second sub-signal line 311. The first second sub-signal line 311 and the second second sub-signal line 312 may be electrically connected via the second transfer line 42a, and the third second sub-signal line 313 and the second second sub-signal line 312 may be electrically connected via the second transfer line 42b. All of the three second sub-signal lines 311, 312, and 313 may extend along the second direction Y, and all of the second transfer lines 42a and 42b may extend along the first direction X.

[0100] In some examples, as shown in FIG. 4, the second signal lines 31 divided by the second display area A2a may be divided into two groups, and the number of the second signal lines 31 in the two groups may be the same or different. For example, the second signal lines 31 may be divided into two groups using a first median line OO', and the first group may include the second signal lines 31 located on the left side of the first median line OO', and the second group may include the second signal lines 31 located on the right side of the first median line OO'. The second signal lines 31 of the first group may bypass the second display area A2a from one side (e.g., the left side) of the second display area A2a in the first direction X, and the second signal lines 31 of the second group may bypass the second display area A2a from the other side (e.g., the right side) of the second display area A2a in the first direction X. In this example, by transferring the second signal lines from both the left and right sides of the second display area, it is possible to avoid densely arranging the wiring. In some examples, in the region on the first midline OO' side, the second signal line 31 close to the first midline OO' may be electrically connected to a second effective pixel circuit in one column close to the second display region A2a, the second signal line 31 away from the first midline OO' may be electrically connected to a second effective pixel circuit in one column away from the second display region A2a, and the second transfer line electrically connected to the second signal line 31 close to the first midline OO' may be located on the side closer to the second display region A2a of the second transfer line electrically connected to the second signal line 31 away from the second midline QQ'. However, this embodiment is not limited to this. For example, in the region on the first midline OO' side, the second transfer line electrically connected to the second signal line away from the first midline OO' may be located on the side closer to the second display region A2a of the second transfer line electrically connected to the second signal line close to the first midline OO'.

[0101] The transfer method of the second signal lines partitioned by the second display area A2b is substantially the same as the transfer method of the second signal lines partitioned by the second display area A2a, and therefore will not be described here.

[0102] 4, the first transfer line 41 electrically connected to the first signal line 21 may be located around the second transfer lines 42a and 42b electrically connected to the second signal line 31. That is, the first transfer line 41 may be located on the side of the second transfer line 42a or the second transfer line 42b away from the second display area A2a. In this example, by disposing the second effective pixel circuit in a nearby area of ​​the second display area, it is possible to prevent the transparent conductive line electrically connecting the second effective pixel circuit and the second light-emitting element from being too long, and ensure the display effect.

[0103] 5 is a schematic diagram of a pixel circuit arrangement in a first display area in at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in FIG. 5, a plurality of pixel circuits in the first display area may be arranged in an array. A plurality of pixel circuits arranged sequentially along a first direction X may be referred to as a row of pixel circuits, and a plurality of pixel circuits arranged sequentially along a second direction Y may be referred to as a column of pixel circuits.

[0104] In some examples, as shown in FIG. 5, at least one second pixel circuit 10 may be provided between a plurality of first pixel circuits 11 arranged sequentially along the first direction X. The second pixel circuit 10 may be arranged between a plurality of columns of first pixel circuits 11. For example, one column of second pixel circuits 10 may be provided for every M columns of first pixel circuits 11. Compared with a first display region in which only first pixel circuits are provided, by compressing every M columns of first pixel circuits in the conventional manner along the first direction X, the arrangement space of one column of second pixel circuits 10 can be newly increased, and the space occupied by the pixel circuits of M columns before compression and the pixel circuits of M+1 columns after compression may be the same. Here, M may be an integer of 2 or more. In this example, as shown in FIG. 5, M may be 2, that is, by compressing the original two columns of first pixel circuits along the first direction X, the arrangement space of one column of second pixel circuits can be newly increased, and the space occupied by the pixel circuits of two columns before compression and the pixel circuits of three columns after compression may be the same. In another example, M may be 4 or 8. However, this embodiment is not limited thereto. In another example, the first pixel circuits may be compressed along the second direction Y to newly increase the space for arranging the second pixel circuits. For example, by compressing the first pixel circuits of the original R rows along the second direction Y, the space for arranging the second pixel circuits of one row may be newly increased, and the pixel circuits of the R rows before compression and the pixel circuits of the R+1 rows after compression may occupy the same space. R may be an integer greater than 1.

[0105] In some examples, a column of second pixel circuits 10 may include a plurality of second effective pixel circuits and a plurality of ineffective pixel circuits, or may include a plurality of ineffective pixel circuits. The second effective pixel circuits may be located within the first display area around the second display area.

[0106] FIG. 6 is a schematic diagram of the arrangement of the first signal lines in at least one embodiment of the present disclosure. In FIG. 6, only a few first signal lines are shown as an example, and the second effective pixel circuits arranged around the periphery of the second display area are omitted. In some examples, as shown in FIG. 6, the first signal line 21 is electrically connected to one row of pixel circuits in the first display area, and signal transmission can be realized by bypassing the second display area from the upper or lower side of the second display area via the first transfer line 41. There may be an overlapping portion between the orthogonal projections on the base substrate of the first line segment 411 and the third line segment 413 of the first transfer line 41 electrically connected to the first signal line 21 and the orthogonal projections on the base substrate of the multiple ineffective pixel circuits 15. The orthogonal projections on the base substrate of the second line segment 412 of the first transfer line 41 may be located between adjacent pixel circuit rows. In this example, by arranging the first line segment 411 and the third line segment 413 of the first transfer line 41 in the region where the ineffective pixel circuits are located, it is possible to avoid occupying the space of the effective pixel circuits, and also to avoid occupying the space of the second display region due to the windings in the second display region, thereby ensuring the size of the second display region. However, this embodiment is not limited to this. In another example, when the second pixel circuits are newly added by compressing the first pixel circuits along the second direction, the first line segment and the third line segment of the first transfer line may be arranged between adjacent pixel circuit columns, and there may be an overlapping portion between the orthogonal projection of the second line segment on the base substrate and the orthogonal projection of the multiple ineffective pixel circuits on the base substrate.

[0107] In some examples, as shown in Fig. 6, there may be an overlapping portion between the orthogonal projection on the base substrate of the first transfer line 41 electrically connected to different first signal lines 21 and the orthogonal projection on the base substrate of different invalid pixel circuits. For example, one first transfer line may be arranged in an area where multiple invalid pixel circuits are located. However, this embodiment is not limited to this. For example, multiple first transfer lines may be arranged in an area where invalid pixel circuits of the same column are located.

[0108] FIG. 7 is another schematic diagram of the layout of the first signal line in at least one embodiment of the present disclosure. In FIG. 7, the first signal line around the second display area A2a is shown as an example. In FIG. 7, the transparent conductive line and the light-emitting element are omitted. The pixel circuit of this example is described by taking a 7T1C pixel circuit as an example. In this example, the first reset control signal received by the pixel circuit of the i-th row may be the same as the scan line signal received by the pixel circuit of the i-1-th row, that is, the gates of the first reset transistor T1 of the pixel circuit of the i-th row and the threshold compensation transistor T2 of the pixel circuit of the i-1-th row may receive the same signal. The second reset control signal received by the pixel circuit of the i-th row may be the same as the scan signal received by the pixel circuit of the i-th row, that is, the gates of the threshold compensation transistor T2, the gate of the data writing transistor T4, and the gate of the second reset transistor T7 of the pixel circuit may receive the same signal. In this example, the first reset control line RST1(i) electrically connected to the pixel circuits in the i-th row can transmit the same signal as the scan line GL(i) electrically connected to the pixel circuits in the (i-1)th row, where i is an integer greater than 0.

[0109] In some examples, as shown in FIG. 7, the first signal line in this example may include a first reset control line and a light emission control line. The first signal line is partitioned by the second display area A2a. In FIG. 7, the first reset control line partitioned by the second display area A2a will be described using the first reset control lines RST1(i) and RST1(i+1) as an example. In FIG. 7, the light emission control line partitioned by the second display area A2a will be described using the light emission control line EML(i) as an example. For example, the first reset control line RST1(i) may be electrically connected to the first transfer line 41a to bypass the second display area A2a from above the second display area A2a, the light emission control line EML(i) may be electrically connected to the first transfer line 41b to bypass the second display area A2a from above the second display area A2a, and the first reset control line RST1(i+1) may be electrically connected to the first transfer line 41c to bypass the second display area A2a from above the second display area A2a. The third signal line of this example may include the first reset control line, the scanning line, and the light emission control line. The third signal line is not partitioned by the second display area. In FIG. 7, the first reset control line that is not partitioned by the second display area A2a will be described by taking the first reset control line RST1(i-1) as an example.

[0110] In some examples, the display substrate may further include a fifth signal line. The fifth signal line is partitioned by the second display area and does not bypass the second display area via the first transfer line. The fifth signal line may be electrically connected to an adjacent first signal line or a third signal line transmitting the same signal via a third transfer line, thereby eliminating the need to connect to the first transfer line that bypasses the second display area from above or below the second display area.

[0111] In some examples, the fifth signal line may include a scanning line. In FIG. 7, the scanning line that is partitioned by the second display area A2a and does not bypass the second display area A2a via the first transfer line is described using the scanning line GL(i) as an example. In some examples, the scanning line GL(i) may include three fifth sub-signal lines formed by partitioning by two second display areas. In FIG. 7, a first fifth sub-signal line 231 and a second fifth sub-signal line 232 formed by partitioning by the second display area A2a are shown as examples. One end of the first fifth sub-signal line 231 of the scanning line GL(i) may be electrically connected to a scanning driving circuit in the left peripheral region to receive a scanning signal, and the other end of the first fifth sub-signal line 231 may extend to an edge close to the second display region A2a, one end of the third fifth sub-signal line may be electrically connected to a scanning driving circuit in the right peripheral region to receive a scanning signal, and the other end of the third fifth sub-signal line may extend to an edge close to the second display region A2b. The second fifth sub-signal line 232 may be located in the first display region between the second display regions A2a and A2b. In this example, the first sub signal line is exemplified by the first reset control line RST1(i+1), and the first reset control line RST1(i+1) may include three first sub signal lines formed by being partitioned by two second display areas, and Fig. 7 shows, as an example, a first first sub signal line 211 and a second second sub signal line 212 formed by being partitioned by the second display area A2a. The first first sub signal line 211 may be electrically connected to one end of the second first sub signal line 212 via a first transfer line 41c, and the other end of the second first sub signal line 212 may be electrically connected to a third first sub signal line via another first transfer line. One end (e.g., one end close to the second display region A2a) of the second fifth sub-signal line 232 of the scanning line GL(i) may be electrically connected to one end (e.g., one end close to the second display region A2a) of the second first sub-signal line 212 of the first reset control line RST1(i+1) via the third transfer line 43. For example, the second fifth sub-signal line 232 of the scanning line GL(i), the second first sub-signal line 212 of the first reset control line RST1(i+1), and the third transfer line 43 may have an integrated structure.In some examples, the third transfer line 43 may be located at the edge close to the second display area A2a of the second fifth sub-signal line 232 of the scanning line GL(i). In another example, one end close to the second display area A2b of the second fifth sub-signal line 232 of the scanning line GL(i) may be electrically connected to one end close to the second display area A2b of the second first sub-signal line 212 of the first reset control line RST1(i+1) via the third transfer line, and the third transfer line may be located at the edge close to the second display area A2b. In another example, both ends of the second fifth sub-signal line 232 of the scanning line GL(i) may be electrically connected to both ends of the second first sub-signal line 212 of the first reset control line RST1(i+1) via the third transfer line, respectively. However, this embodiment is not limited to this. In another example, the third transfer line 43 may be located in a conductive layer different from the second fifth sub-signal line 232 of the scanning line GL(i) and the second first sub-signal line 212 of the first reset control line RST1(i+1), for example, on the side of the scanning line GL(i) and the first reset control line RST1(i+1) away from the base substrate. In this example, the scanning lines partitioned by the second display region are electrically connected to adjacent first signal lines that transmit the same signal, thereby realizing signal transmission and reducing the number of transfer lines.

[0112] In another example, the first signal line may include a scanning line and a light emission control line, and the fifth signal line may include a first reset control line. The scanning line separated by the second display area may be transferred through the first transfer line and bypass the second display area, and the first reset control line separated by the second display area may be electrically connected to an adjacent scanning line that transmits the same signal, thereby realizing signal transmission. However, this embodiment is not limited thereto.

[0113] 7, there may be an overlap between the orthogonal projections of the first transfer line 41a, the second transfer line 41b, and the third transfer line 41c on the base substrate and the orthogonal projections of the same multiple invalid pixel circuits on the base substrate. A plurality of first transfer lines may be arranged in the region where one column of invalid pixel circuits is located.

[0114] 8 is a partial plan view of the display substrate of region P1 in FIG. 7. FIG. 9 is a local cross-sectional schematic view along the R-R' direction in FIG. 8. FIG. 10A is a partial plan view of the display substrate after the semiconductor layer in FIG. 8 is formed. FIG. 10B is a partial plan view of the display substrate after the first conductive layer in FIG. 8 is formed. FIG. 10C is a partial plan view of the display substrate after the second conductive layer in FIG. 8 is formed. FIG. 10D is a partial plan view of the display substrate after the third insulating layer in FIG. 8 is formed. FIG. 10E is a partial plan view of the display substrate after the third conductive layer in FIG. 8 is formed. FIG. 10F is a partial plan view of the display substrate after the fourth insulating layer in FIG. 8 is formed.

[0115] In some examples, as shown in Figures 7 and 8, a first circuit area A11 and a second circuit area A12 are arranged in the first display area with a gap therebetween in the first direction X. The first circuit area A11 has multiple columns of first pixel circuits 11 (e.g., two columns of first pixel circuits 11), and the second circuit area A12 has one column of second pixel circuits (e.g., may include multiple ineffective pixel circuits 15, or may include multiple second effective pixel circuits and multiple ineffective pixel circuits). Figure 8 shows an example of two rows and multiple columns of pixel circuits.

[0116] In some examples, as shown in Fig. 8 and Fig. 9, in a direction perpendicular to the display substrate, the display substrate of the first display region A1 may include a base substrate 100 and a circuit configuration layer provided on the base substrate 100. The circuit configuration layer may include a semiconductor layer 50, a first conductive layer 51, a second conductive layer 52, a third conductive layer 53, and a fourth conductive layer 54, which are sequentially provided on the base substrate 100. A first insulating layer 101 is provided between the semiconductor layer 50 and the first conductive layer 51, a second insulating layer 102 is provided between the first conductive layer 51 and the second conductive layer 52, a third insulating layer 103 is provided between the second conductive layer 52 and the third conductive layer 53, and a fourth insulating layer 104 is provided between the third conductive layer 53 and the fourth conductive layer 54. In some examples, the first insulating layer 101 to the fourth insulating layer 104 may all be inorganic insulating layers. Alternatively, the first insulating layer 101 to the third insulating layer 103 may be inorganic insulating layers, and the fourth insulating layer 104 may be an organic insulating layer. In some examples, at least one transparent conductive layer and a light emitting structure layer may be provided on the side of the circuit structure layer away from the base substrate 100. The transparent conductive layer may include a plurality of transparent conductive lines. The transparent conductive lines may be configured to be electrically connected to the second effective pixel circuit and the anode of the second light emitting element. The light emitting structure layer may include a plurality of first light emitting elements and a plurality of second light emitting elements. The light emitting structure layer may include an anode layer, a pixel definition layer, an organic light emitting layer, and a cathode layer that are provided in sequence. However, this embodiment is not limited thereto.

[0117] In some exemplary embodiments, as shown in FIGS. 8 to 10A , the semiconductor layer 50 in the first display region A1 includes at least active layers of a plurality of transistors in a plurality of pixel circuits (e.g., an active layer 1510 of the first reset transistor 151, an active layer 1520 of the threshold compensation transistor 152, an active layer 1530 of the driving transistor 153, an active layer 1540 of the data writing transistor 154, an active layer 1550 of the first emission control transistor 155, an active layer 1560 of the second emission control transistor 156, and an active layer 1570 of the first emission control transistor 157). The active layer 1560 of the first pixel circuit 11 and the active layer 1570 of the second reset transistor 157, as well as the active layer 1110 of the first reset transistor 111 of the first pixel circuit 11, the active layer 1120 of the threshold compensation transistor 112, the active layer 1130 of the driving transistor 113, the active layer 1140 of the data writing transistor 114, the active layer 1150 of the first light-emitting control transistor 115, the active layer 1160 of the second light-emitting control transistor 116, and the active layer 1170 of the second reset transistor 117. In this example, the active layers of the seven transistors of one pixel circuit may be of a monolithic structure. In some examples, at least one active layer may include at least one channel region and a plurality of doping regions. The channel region may not be doped with impurities and has semiconductor properties. The plurality of doping regions may be on both sides of the channel region and are doped with impurities and therefore have electrical conductivity. The impurities may be changed according to the type of transistor. In some instances, the doped regions of the active layer can be interpreted as source or drain electrodes of a transistor, and the portions of the active layer between the transistors can be interpreted as impurity doped wiring that can be used to electrically connect the transistors.

[0118] In some exemplary embodiments, as shown in FIGS. 8 to 10B , the first conductive layer 51 in the first display area A1 is connected to the gates of a plurality of transistors of a plurality of pixel circuits and the first capacitor plate of the storage capacitor (for example, the gate 1511 of the first reset transistor 151, the gate 1521 of the threshold compensation transistor 152, the gate 1531 of the driving transistor 153, the gate 1541 of the data writing transistor 154, the gate 1551 of the first emission control transistor 155, the gate 1561 of the second emission control transistor 156, the gate 1571 of the second reset transistor 157, and the first capacitor plate 1581 of the storage capacitor 158 of the first pixel circuit 11). The gate 1111 of the threshold compensation transistor 112, the gate 1131 of the driving transistor 113, the gate 1141 of the data writing transistor 114, the gate 1151 of the first light-emitting control transistor 115, the gate 1161 of the second light-emitting control transistor 116, the gate 1171 of the second reset transistor 117, and the first capacitor plate 1181 of the storage capacitor 118), a plurality of scanning lines (e.g., scanning lines GL(i-1) and GL(i)), a plurality of light-emitting control lines (e.g., light-emitting control lines EML(i-1) and EML(i)), and a plurality of first reset control lines (e.g., first reset control lines RST1(i-1), RST1(i), and RST1(i+1)).

[0119] 10B, the first reset control line RST1(i) may be integral with the gate 1511 of the first reset transistor 151 of the invalid pixel circuit 15 in the i-th row, the gate 1111 of the first reset transistor 111 of the first pixel circuit 11 in the i-th row, and the gate of the second reset transistor of the pixel circuit in the i-1th row. The first reset control line RST1(i+1) may be integral with the gate 1571 of the second reset transistor 157 of the invalid pixel circuit 15 in the i-th row, the gate 1171 of the second reset transistor 117 of the first pixel circuit 11 in the i-th row, and the gate of the first reset transistor of the pixel circuit in the i+1th row. The scanning line GL(i) may be integral with the gate 1541 of the data write transistor 154 and the gate 1521 of the threshold compensation transistor 152 of the invalid pixel circuit 15 in the i-th row, and the gate 1141 of the data write transistor 114 and the gate 1121 of the threshold compensation transistor 112 of the first pixel circuit 11 in the i-th row. The light emission control line EML(i) may be integral with the gate 1551 of the first light emission control transistor 155 and the gate 1561 of the second light emission control transistor 156 of the invalid pixel circuit 15 in the i-th row, and the gate 1151 of the first light emission control transistor 115 and the gate 1161 of the second light emission control transistor 116 of the first pixel circuit 11 in this row. The first capacitor plate 1581 of the storage capacitor 158 of the invalid pixel circuit 15 may be integral with the gate 1531 of the drive transistor 153. The first capacitor plate 1181 of the storage capacitor 118 of the first pixel circuit 11 may be integral with the gate 1131 of the driving transistor 113. However, this embodiment is not limited thereto.

[0120] In some exemplary embodiments, as shown in FIGS. 8 to 10C, the second conductive layer 52 in the first display area A1 may include second capacitor plates of storage capacitors of a plurality of pixel circuits (e.g., including the second capacitor plate 1582 of the storage capacitor 158 of the inactive pixel circuit 15 and the second capacitor plate 1182 of the storage capacitor 118 of the first pixel circuit 11), a plurality of first initial signal lines (e.g., including the first initial signal lines INIT1(i-1) and INIT1(i)), and a plurality of second initial signal lines (e.g., including the second initial signal lines INIT2(i-1), INIT2(i) and INIT2(i+1)). The second capacitor plate 1182 of the storage capacitor 118 of the first pixel circuit 11 has a fretwork area, and the orthogonal projection of the gate 1131 of the driving transistor 113 on the base substrate may cover the orthogonal projection of the fretwork area on the base substrate. The orthogonal projection of the openwork area on the base substrate may be a polygon, but this embodiment is not limited thereto.

[0121] In some exemplary embodiments, as shown in FIGS. 8 to 10D, the third insulating layer 103 in the first display area A1 may have a plurality of vias, for example, including the first via V1 to the ninth via V9, the eleventh via V11, and the twelfth via V12. The third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the first via V1 to the fifth via V5 are removed to expose the surface of the semiconductor layer 50. The third insulating layer 103 and the second insulating layer 102 in the sixth via V6, the eleventh via V11, and the twelfth via V12 are removed to expose the surface of the first conductive layer 51. The third insulating layer 103 in the seventh via V7 to the ninth via V9 are removed to expose the surface of the second conductive layer 52.

[0122] In some exemplary embodiments, as shown in FIGS. 8 to 10E, the third conductive layer 53 of the first display area A1 may include a plurality of connection electrodes (for example, including a first connection electrode CP1 to a sixth connection electrode CP6) and a plurality of first transfer lines (for example, the first transfer lines 41a, 41b, and 41c). The first connection electrode CP1 may be electrically connected to a first doped region of the active layer 1110 of the first reset transistor 111 of the first pixel circuit 11 through a first via V1, and may be electrically connected to a first initial signal line INIT(i) through a seventh via V7. The second connection electrode CP2 may be electrically connected to a first doped region of the active layer 1120 of the threshold compensation transistor 112 of the first pixel circuit 11 through a second via V2, and may be electrically connected to a gate 1131 of the driving transistor 113 through a sixth via V6. The third connection electrode CP3 may be electrically connected to the first doped region of the active layer 1140 of the data write transistor 114 through the third via V3. The fourth connection electrode CP4 may be electrically connected to the first doped region of the active layer 1150 of the first light-emitting control transistor 115 through the fourth via V4, and may be electrically connected to the second capacitor plate 1182 of the storage capacitor 118 through the eighth via V8. The fifth connection electrode CP5 may be electrically connected to the second doped region of the active layer 1160 of the second light-emitting control transistor 116 through the fifth via V5. The sixth connection electrode CP6 may be electrically connected to the second initial signal line INIT2(i+1) through the ninth via V9, and may be electrically connected to the first doped region of the active layer 1170 of the second reset transistor 117.

[0123] 7 and 10E, the first transfer line 41a may include a fourth line segment 414a, a first line segment 411a, a second line segment, a third line segment, and a fifth line segment, which are connected in sequence. The first transfer line 41b may include a fourth line segment 414b, a first line segment 411b, a second line segment, a third line segment, and a fifth line segment, which are connected in sequence. The first transfer line 41c may include a first line segment, a second line segment, and a third line segment, which are connected in sequence. The first line segment and the third line segment both extend along the second direction Y, and the second line segment extends along the first direction X.

[0124] In some examples, as shown in FIG. 7 and FIG. 10E, the fourth line segment 414a of the first transfer line 41a may have one end electrically connected to the first reset control line RST1(i) through the eleventh via V11, and the other end electrically connected to the first line segment 411a extending along the second direction Y. The fourth line segment 414a of the first transfer line 41a first extends along the second direction Y away from the light emission control line EML(i), and then extends along the first direction X toward the second display area A2a. The orthogonal projection of the fourth line segment 414a on the base substrate may be L-shaped. The first line segment 411a may be located in one second circuit area A12, and the connection position between the fourth line segment 414a and the first reset control line RST1(i) may be located in another second circuit area A12 adjacent to the second circuit area A12 in which the first line segment 411a is located. However, this embodiment is not limited to this. For example, at least one second circuit area may be provided between the second circuit area in which the first line segment 411a is located and the second circuit area in which the connection position between the fourth line segment 414a and the first reset control line RST1(i) is located.

[0125] In some examples, as shown in FIG. 7 and FIG. 10E, the fourth line segment 414b of the first transfer line 41b may have one end electrically connected to the light emission control line EML(i) through the twelfth via V12, and the other end electrically connected to the first line segment 411b extending along the second direction Y. The fourth line segment 414b of the first transfer line 41b first extends along the second direction Y away from the first reset control line RST1(i), and then extends along the first direction X toward the second display area A2a. The orthogonal projection of the fourth line segment 414b on the base substrate may be L-shaped. The first line segment 411b may be located in one second circuit area A12, and the connection position between the fourth line segment 414b and the light emission control line EML(i) may be located in another second circuit area A12 adjacent to the second circuit area A12 in which the first line segment 411b is located. However, this embodiment is not limited thereto.

[0126] In this example, the first signal lines separated by the second display area are electrically connected by a first transfer line located on the third conductive layer, and the first transfer line is made of a metal material, thereby reducing the effect of resistance on signal transmission.

[0127] The arrangement of the third and fifth line segments of the first transfer line can be referred to in the arrangement of the first and fourth line segments, and therefore will not be described here. For example, the first and third line segments of one first transfer line may be substantially symmetrical with respect to a first center line in the first direction of the second display area, and the fourth and fifth line segments may be substantially symmetrical with respect to the first center line in the first direction of the second display area.

[0128] 8 to 10F, the fourth insulating layer 104 in the first display region A1 may have a plurality of vias, for example, including a thirteenth via V13 to a fifteenth via V15. The fourth insulating layer 104 in the thirteenth via V13 to the fifteenth via V15 is removed to expose the surface of the third conductive layer 53.

[0129] In some exemplary embodiments, as shown in FIGS. 8-9, the fourth conductive layer 54 of the first display region A1 may include a plurality of data lines (e.g., including data lines DL(j) and DL(j-2)), a plurality of first power lines (e.g., including first power lines PL1(j) and PL1(j-2)), and a plurality of anode connecting electrodes (e.g., anode connecting electrode CP7). The anode connecting electrode CP7 may be electrically connected to the fifth connecting electrode CP5 through a fifteenth via V15. The data line DL(j) may be electrically connected to the third connecting electrode CP3 through a thirteenth via V13. The first power line PL1(j) may be electrically connected to the fourth connecting electrode CP4 through a fourteenth via V14.

[0130] In this example, in the second circuit region A12 in which the ineffective pixel circuits are located and which have a portion overlapping with the orthogonal projection of the first transfer line on the base substrate, a via electrically connected to the first transfer line may be opened only in the third insulating layer, or the connection electrode of the third conductive layer electrically connected to the ineffective pixel circuit may be removed to leave a space for installing the first transfer line. The film layer structure of the ineffective pixel circuits in the remaining second circuit region A12 may be substantially the same as the film layer structure of the first pixel circuit, and therefore will not be described here.

[0131] FIG. 11 is a schematic diagram of the arrangement of the second signal lines in at least one embodiment of the present disclosure. FIG. 11 shows only a few second signal lines partitioned by the second display area A2a as an example. In some examples, as shown in FIG. 11, the second signal lines 31 may include a first second sub signal line 311 and a third second sub signal line 313 extending along the second direction Y, and a second second sub signal line 312 extending along the second direction Y. The second second sub signal line 312 may be electrically connected to one column of pixel circuits (e.g., may include a plurality of second effective pixel circuits and a plurality of ineffective pixel circuits, or may include only a plurality of second effective pixel circuits), and the first second sub signal line 311 and the third second sub signal line 313 may be electrically connected to the first pixel circuits 11 in the same column. The first second sub-signal line 311 and the second second sub-signal line 312 may be electrically connected via a second transfer line 42a, and the third second sub-signal line 313 and the second second sub-signal line 312 may be electrically connected via a second transfer line 42b. The second transfer line 42a and the second transfer line 42b may extend along the first direction X and may be located between adjacent pixel circuit rows.

[0132] FIG. 12 is another schematic diagram of the arrangement of the second signal line in at least one embodiment of the present disclosure. FIG. 12 shows an example in which the data lines around the second display area A2a are the second signal lines. In FIG. 12, the transparent conductive lines and the light-emitting elements are omitted. In some examples, as shown in FIG. 12, the second signal lines are described by taking the data line DL(k) and the data line DL(k+1) as an example. The data line DL(k) may include three second sub-signal lines 311a, 312a, and 313a, and the data line DL(k+1) may include three second sub-signal lines 311b, 312b, and 313b. The first second sub-signal line 311a and the third second sub-signal line 313a of the data line DL(k) may be electrically connected to the first pixel circuit 11 of the same column, and the second second sub-signal line 312a may be electrically connected to the second effective pixel circuit 12 of one column. The first second sub-signal line 311b and the third second sub-signal line 313b of the data line DL(k+1) may be electrically connected to the first pixel circuits 11 in the same column, and the second second sub-signal line 312b may be electrically connected to the second effective pixel circuits 12 in one column. The first second sub-signal line 311a and the second second sub-signal line 312a of the data line DK(k) may be electrically connected via the second transfer line 42a, and the second second sub-signal line 312a and the third second sub-signal line 313a may be electrically connected via the second transfer line 42b. The first second sub-signal line 311b and the second second sub-signal line 312b of the data line DK(k+1) may be electrically connected via a second transfer line 42c, and the second second sub-signal line 312b and the third second sub-signal line 313b may be electrically connected via a second transfer line 42d. For example, the second transfer lines 42a, 42b, 42c, and 42d may all extend along the first direction X.

[0133] In some examples, as shown in FIG. 12, the second display region A2a has a first midline OO' in the first direction X. In a region on the first midline OO' side (for example, a region to the left of the first midline OO'), the first second sub-signal line 311a of the data line DL(k) is located on a side of the first second sub-signal line 311b of the data line DL(k+1) away from the first midline OO'. The second second sub-signal line 312a of the data line DL(k) is located on a side of the second second sub-signal line 312b of the data line DL(k+1) closer to the second display region A2a. The second transfer line 42a electrically connected to the second second sub-signal line 312a of the data line DL(k) may be located on a side of the second transfer line 42c electrically connected to the second second sub-signal line 312b of the data line DL(k+1) closer to the second display region A2a. The length of the second transfer line 42a along the first direction X may be shorter than the length of the second transfer line 42c along the first direction X. The second transfer line 42b electrically connected to the second second sub-signal line 312a of the data line DL(k) may be located on the side closer to the second display region A2a of the second transfer line 42d electrically connected to the second second sub-signal line 312b of the data line DL(k+1). The length of the second transfer line 42b along the first direction X may be shorter than the length of the second transfer line 42d along the first direction X.

[0134] Fig. 13 is a partial schematic plan view of the display substrate in the region P2 of Fig. 12. Fig. 14 is a partial schematic plan view of the display substrate after the third conductive layer in Fig. 13 is formed. In this example, the film layer structure of the first reset transistor 121, threshold compensation transistor 122, drive transistor 123, data write transistor 124, first light emission control transistor 125, second light emission control transistor 12, second reset transistor 127, and storage capacitor 128 of the second effective pixel circuit 12 is almost the same as the film layer structure of the first reset transistor 111, threshold compensation transistor 112, drive transistor 113, data write transistor 114, first light emission control transistor 115, second light emission control transistor 116, second reset transistor 117, and storage capacitor 118 of the first pixel circuit 11, so that they will not be described here.

[0135] In some examples, as shown in Figures 12 to 14, the second transfer line 42a may be located in the third conductive layer, one end of the second transfer line 42a may be electrically connected to the first second sub-signal line 311a of the data line DL(k) through a 17th via V17 opened in the fourth insulating layer, and the other end of the second transfer line 42a may be electrically connected to the second second sub-signal line 312a through a 16th via V16 opened in the fourth insulating layer. The second transfer line 42c may be located in the third conductive layer, one end of the second transfer line 42c may be electrically connected to the first second sub-signal line 311b of the data line DL(k+1) through a 19th via V19 opened in the fourth insulating layer, and the other end of the second transfer line 42c may be electrically connected to the second second sub-signal line 312b through an 18th via V18 opened in the fourth insulating layer.

[0136] In some examples, there may be overlapping portions between the orthogonal projections, on the base substrate, of the connection positions of the second transfer line 42a and the first second sub-signal line 311a and the connection positions of the second transfer line 42a and the second second sub-data line 312a and the same first reset control line. There may be overlapping portions between the orthogonal projections, on the base substrate, of the connection positions of the second transfer line 42c and the first second sub-signal line 311b and the connection positions of the second transfer line 42c and the second second sub-signal line 312b and the same first reset control line.

[0137] FIG. 15 is a schematic diagram of the layout of the first initial signal line and the second initial signal line in at least one embodiment of the present disclosure. In some examples, as shown in FIG. 15, when the first initial signal supplied by the first initial signal line INIT1 is different from the second initial signal supplied by the second initial signal line INIT2, the first initial signal line INIT1 and the second initial signal line INIT2 are wired along the outer edge of the second display area A2a and the second display area A2b, bypassing the two second display areas, not occupying the space of the second display area, and not interfering with the surrounding pixel circuits. When the first initial signal supplied by the first initial signal line INIT1 is the same as the second initial signal supplied by the second initial signal line INIT2, one connection electrode may be provided on each of the outer edges of the second display areas A2a and A2b to connect the first initial signal lines INIT1 located on both sides of the second display area A2a in the first direction X. However, this embodiment is not limited to this.

[0138] The manufacturing process of the display substrate is exemplified below. The "patterning process" in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal materials, inorganic materials, or transparent conductive materials, and organic material coating, mask exposure, and development for organic materials. The deposition may be any one or more of sputtering, deposition, and chemical vapor deposition, the coating may be any one or more of spraying, spin coating, and inkjet printing, and the etching may be any one or more of dry etching and wet etching, and the disclosure is not limited thereto. A "thin film" refers to a thin film formed by depositing, coating, or other methods of a material on a base substrate. If the "thin film" does not require a patterning process in the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process in the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern".

[0139] In some exemplary embodiments, the manufacturing process of the display substrate may include the following operations.

[0140] (1) Form a semiconductor layer.

[0141] In some exemplary embodiments, as shown in FIG. 10A, a semiconductor thin film is deposited on a base substrate 100, and the semiconductor thin film is patterned by a patterning process to form a semiconductor layer 50 in the first display area A1. The active layers of the seven transistors of one pixel circuit may be an integral structure that is connected to each other. In some examples, the material of the semiconductor layer 50 may include, for example, polysilicon. However, this embodiment is not limited thereto.

[0142] In some exemplary embodiments, the base substrate 100 may be a rigid substrate such as a glass substrate, but the present embodiment is not limited thereto. The base substrate may be, for example, a flexible substrate.

[0143] (2) forming a first conductive layer;

[0144] 10B, a first insulating thin film and a first conductive thin film are sequentially deposited on the base substrate 100 on which the above structure is formed, and the first conductive thin film is patterned by a patterning process to form a first insulating layer 101 covering the semiconductor layer 50 and a first conductive layer 51 disposed on the first insulating layer 101 in the first display area A1. The first conductive layer 51 may include a first gate metal layer (including a gate and a capacitor plate) of a pixel circuit, a scan line, a first reset control line and a light emitting control line.

[0145] (3) forming a second conductive layer;

[0146] 10C, a second insulating thin film and a second conductive thin film are sequentially deposited on the base substrate 100 on which the above structure is formed, and the second conductive thin film is patterned by a patterning process to form a second insulating layer 102 covering the first conductive layer 51, and a second conductive layer 52 disposed on the second insulating layer 102 in the first display area A1. The second conductive layer 52 may include a second gate metal layer (e.g., including a capacitor plate), a first initial signal line and a second initial signal line of the pixel circuit.

[0147] (4) Form a third insulating layer.

[0148] In some exemplary embodiments, as shown in FIG. 10D, a third insulating thin film is deposited on the base substrate 100 on which the above pattern is formed, and the third insulating thin film is patterned by a patterning process to form a third insulating layer 103.

[0149] (5) forming a third conductive layer;

[0150] 10E and 14, a third conductive thin film is deposited on the base substrate on which the above pattern is formed, and the third conductive thin film is patterned by a patterning process to form a third conductive layer 53 on the third insulating layer 103 in the first display area A1. The third conductive layer 53 may include a first source-drain metal layer (e.g., including a plurality of connection electrodes) of the pixel circuit, a first transfer line, and a second transfer line.

[0151] (6) Form a fourth insulating layer.

[0152] In some exemplary embodiments, as shown in FIG. 10F, a fourth insulating thin film is deposited on the base substrate 100 on which the above pattern is formed, and the fourth insulating thin film is patterned by a patterning process to form a fourth insulating layer 104.

[0153] (7) Forming a fourth conductive layer.

[0154] 8 and 13, a fourth conductive thin film is deposited on the base substrate on which the above pattern is formed, and the fourth conductive thin film is patterned by a patterning process to form a fourth conductive layer 54 on the fourth insulating layer 104 in the first display area A1. The fourth conductive layer 54 may include a first power line and a data line.

[0155] The circuit configuration layer of the first display area A1 is completed up to this point. The second display areas A2a and A2b may include a base substrate 100, and a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, and a fourth insulating layer 104 laminated on the base substrate 100.

[0156] (8) Sequentially forming a first planar layer, a first transparent conductive layer, a second planar layer, a second transparent conductive layer, a third planar layer, a third transparent conductive layer, a fourth planar layer, an anode layer, a pixel defining layer, an organic light emitting layer, and a cathode layer.

[0157] In some exemplary embodiments, a first flat thin film is applied to the base substrate 100 on which the pattern is formed, and the first flat thin film is patterned by a patterning process to form a first flat layer. Then, a first transparent conductive thin film is deposited on the base substrate on which the pattern is formed, and the first transparent conductive thin film is patterned by a patterning process to form a first transparent conductive layer. Then, a second flat thin film is applied to the base substrate on which the pattern is formed, and the second flat thin film is patterned by a patterning process to form a second flat layer. Then, a second transparent conductive thin film is deposited on the base substrate on which the pattern is formed, and the second transparent conductive thin film is patterned by a patterning process to form a second transparent conductive layer. Then, a third flat thin film is applied to the base substrate on which the pattern is formed, and the third flat thin film is patterned by a patterning process to form a third flat layer. Then, a third transparent conductive thin film is deposited on the base substrate on which the pattern is formed, and the third transparent conductive thin film is patterned by a patterning process to form a third transparent conductive layer. However, this embodiment is not limited thereto. In other instances, only one or two transparent conductive layers may be provided.

[0158] Then, an anode thin film is deposited on the base substrate on which the pattern is formed, and the anode thin film is patterned by a patterning process to form an anode layer. Then, a pixel definition thin film is applied to the base substrate on which the pattern is formed, and a pixel definition layer is formed by a mask, exposure and development process. A plurality of pixel openings that expose the anode layer are formed in the pixel definition layer. Then, an organic light-emitting layer is formed in the formed pixel openings, and the organic light-emitting layer is connected to the anode. Then, a cathode thin film is deposited, and the cathode thin film is patterned by a patterning process to form a cathode layer, and the cathode layer is electrically connected to the organic light-emitting layer and the second power line, respectively. In some examples, a package layer is formed on the cathode layer, and the package layer may include a laminated structure of inorganic material / organic material / inorganic material.

[0159] In some exemplary embodiments, the first conductive layer 51, the second conductive layer 52, the third conductive layer 53, and the fourth conductive layer 54 may be made of one or more metal materials selected from the group consisting of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of these metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 may be made of one or more silicon oxides (SiOx), silicon nitrides (SiNx), and silicon oxynitrides (SiON), and may be a single layer, a multi-layer, or a composite layer. The first insulating layer 101 and the second insulating layer 102 may be referred to as gate insulating (GI) layers, and the third insulating layer 103 may be referred to as an interlayer dielectric (ILD) layer. The first to fourth planar layers can be made of organic materials such as polyimide, acrylic, and polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, and polyethylene terephthalate. The anode layer can be made of a reflective material such as metal, and the cathode layer can be made of a transparent conductive material. However, this embodiment is not limited to this.

[0160] The structure of the display substrate and its manufacturing process in this embodiment are merely examples. In some exemplary embodiments, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs. For example, a conductive layer may be newly added on the side of the fourth conductive layer away from the base substrate, and the first transfer line and the second transfer line may be disposed in the newly added conductive layer. However, this embodiment is not limited thereto.

[0161] The manufacturing process of this exemplary embodiment can be realized by utilizing current mature manufacturing equipment, has good compatibility with existing manufacturing processes, is simple to realize the process, is easy to implement, has high production efficiency, low production cost, and high yield rate.

[0162] FIG. 16 is another schematic diagram of pixel circuits in the first display region in at least one embodiment of the present disclosure. In some examples, as shown in FIG. 16, the second pixel circuits 10 may be arranged between the first pixel circuits 11 in multiple columns and the first pixel circuits 11 in multiple rows. In some examples, one column of the second pixel circuits 10 may be arranged for every a column of the first pixel circuits 11, or one row of the second pixel circuits 10 may be arranged for every b row of the first pixel circuits 11, where a and b may be integers of 2 or more. Compared with the first display region in which only the first pixel circuits are arranged, the arrangement space of the second pixel circuits 10 in one row and one column can be newly increased by compressing the original first pixel circuits arranged in an a×b array along the first direction X and the second direction Y, and the occupied space of the pixel circuits arranged in the a×b array before compression may be the same as that of the pixel circuits arranged in the (a+1)×(b+1) array after compression. In this example, as shown in FIG. 16, both a and b may be 4. However, this embodiment is not limited to this.

[0163] FIG. 17 is another schematic diagram of a display substrate in at least one embodiment of the present disclosure. FIG. 18 is a schematic diagram of the transparent conductive lines in the region P3 in FIG. 17. In some exemplary embodiments, as shown in FIG. 17, the second display regions A2a and A2b may be circular. Taking the second display region A2a as an example, the second display region Aa may be divided into four sub-display regions along the midlines of the third direction F3 and the fourth direction F4. The third direction F3 crosses both the first direction X and the second direction Y, and the angle between the third direction F3 and the first direction X in the clockwise direction may be about 30 to 60 degrees, for example, about 45 degrees, and the fourth direction F4 crosses the third direction F3, and may be perpendicular to the third direction F3, for example. For example, the second light-emitting elements 14 in two sub-display areas arranged along the first direction X may be electrically connected to the second effective pixel circuit in the first display area A1 adjacent to the first direction X via the transparent conductive line L, and the second light-emitting elements 14 in two sub-display areas arranged along the second direction Y may be electrically connected to the second effective pixel circuit in the first display area A1 adjacent to the second direction Y via the transparent conductive line L. However, this embodiment is not limited to this.

[0164] FIG. 19 is another schematic diagram of the wiring arrangement of the first signal line in at least one embodiment of the present disclosure. In some examples, as shown in FIGS. 17 to 19, the first signal line 21 partitioned into the second display area A2a and the second display area A2b may be electrically connected via the first transfer line 41. The first transfer line 41 may include a second line segment 412 extending along the first direction X, and a first line segment 411 and a third line segment 413 extending along the second direction Y. There may be an overlapping portion between the orthogonal projection of the first line segment 411 and the third line segment 413 on the base substrate and the orthogonal projection of the multiple invalid pixel circuits 15 arranged along the second direction Y on the base substrate, and there may be an overlapping portion between the orthogonal projection of the second line segment 412 on the base substrate and the orthogonal projection of the multiple invalid pixel circuits 15 arranged along the first direction X on the base substrate. In some examples, the multiple first signal lines 21 may include a first reset control line, a light emission control line, and a scanning line. However, this embodiment is not limited thereto. In another embodiment, the plurality of first signal lines may include a first reset control line and a light emission control line, and the connection method of the scanning lines partitioned for the second display area can refer to the description of the previous embodiment, so it is omitted here.

[0165] 20 and 21 are partial plan views of a display substrate according to at least one embodiment of the present disclosure. Fig. 20 shows a connection position between a first line segment of a first transfer line and a first signal line. Fig. 21 shows a connection position between a first line segment of a first transfer line and a second line segment. Fig. 22 is a partial enlarged schematic view of the connection position between the first line segment of a first transfer line and a second line segment in at least one embodiment of the present disclosure.

[0166] In some exemplary embodiments, as shown in Figures 20 to 22, the first display region A1 may include a first circuit region A11 and a second circuit region A12. The first circuit regions A11 are both partitioned by the second circuit region A12 in the first direction X and the second direction Y. A plurality of first pixel circuits are provided in one first circuit region A11, and for example, the first pixel circuits arranged in a 4x4 array may be provided in one first circuit region A11. A plurality of second pixel circuits (for example, including a plurality of ineffective pixel circuits, or including a plurality of second effective pixel circuits and a plurality of ineffective pixel circuits) are provided in the second circuit region A12.

[0167] In some examples, as shown in FIG. 19 to FIG. 22, one first transfer line 41 may include a first line segment 411, a second line segment 412, and a third line segment 413 that are connected in sequence. The first line segment 411 and the third line segment 413 may have the same layer structure, and may be located in, for example, the fourth conductive layer, and the second line segment 412 may be located in the first conductive layer. The connection relationship between the first signal line and the first transfer line will be described using the light emission control line EML(i) as an example. As shown in FIG. 20, the first line segment 411 of the first transfer line may be electrically connected to the light emission control line EML(i) through the second via V21, and the fourth insulating layer, the third insulating layer, and the second insulating layer in the second via V21 may be removed to expose the surface of the light emission control line EML(i) of the first conductive layer. The connection position of the first line segment 411 and the light emission control line EML(i) may be located in the second circuit area A12. In this embodiment, six first line segments of the first transfer lines may be arranged in the first direction X in one second circuit region A12. The data lines and the first power lines of the fourth conductive layer of the second circuit region A12 in which an ineffective pixel circuit exists that has a portion overlapping with the orthogonal projection of the first line segment 411 on the base substrate may be removed, and the vias that realize the connection between the connection electrode opened in the third insulating layer of the second circuit region A12 and the remaining film layers may be removed, thereby providing the arrangement space for the first line segment 411, avoiding the influence on the connection of the first line segment 411, and reducing the wiring capacitance of the first line segment 411. However, this embodiment is not limited to this. For example, the fourth conductive layer and the third conductive layer of the second circuit region in which an ineffective pixel circuit exists that has a portion overlapping with the orthogonal projection of the first line segment on the base substrate may both be removed, and the vias that realize the connection between the electrode opened in the third insulating layer of the second circuit region and the remaining film layers may be removed.

[0168] In some examples, as shown in FIG. 21 and FIG. 22, the first line segment 411 may be electrically connected to the second line segment 412 located on the first conductive layer through the via V22. The fourth insulating layer, the third insulating layer, and the second insulating layer in the via V22 may be removed. An overlapping portion may exist between the orthogonal projection of the second line segment 412 on the base substrate and the orthogonal projection of the multiple invalid pixel circuits of the second circuit area A12 on the base substrate. For example, the active layers, the first gate metal layer, and the second gate metal layer of the multiple invalid pixel circuits arranged along the first direction X may be intermittently provided. An overlapping portion may not exist between the orthogonal projection of the second line segment 412 on the base substrate and the orthogonal projection of the active layers and gates of the transistors of the invalid pixel circuits on the base substrate. The active layer of the transistor of the invalid pixel circuit having a portion overlapping with the orthogonal projection of the second line segment 412 on the base substrate may be partitioned by the second line segment 412, leaving only the active layer of the invalid pixel circuit having no portion overlapping with the second line segment 412, thereby preventing the active layer of the invalid pixel circuit from affecting the second line segment 412. In addition, the wiring located on the first conductive layer and the second conductive layer to which the invalid pixel circuit is electrically connected may be removed, thereby providing a space for arranging the second line segment 412 and reducing the wiring capacitance of the second line segment 412. However, this embodiment is not limited to this. In another example, the second line segment 412 may be located on the second conductive layer. The arrangement of the third line segment can be referred to the description of the first line segment, so it will be omitted here.

[0169] The film layer structure of the display substrate of this embodiment can be referred to in the description of the above embodiment, so a detailed description will be omitted here.

[0170] The display substrate according to the present embodiment has a first transfer line disposed in an area where an ineffective pixel circuit is located, so that the driving control of the pixel circuit can be ensured without occupying the space of the effective pixel circuit and the space of the second display area, and the size of the second display area can be ensured. The first transfer line may include a first line segment and a third line segment disposed in the fourth conductive layer, and a second line segment disposed in the first conductive layer or the second conductive layer, and the first transfer line may be made of a metal material, so that the influence of the resistor on the transmission of the gate driving signal can be reduced. The film layer structure of the ineffective pixel circuit that affects the arrangement of the first transfer line may be completely or partially removed, so that the capacitance of the first transfer line can be reduced and the signal transmission can be ensured.

[0171] FIG. 23 is another schematic diagram of the arrangement of the first signal line in at least one embodiment of the present disclosure. In some examples, as shown in FIG. 23, the first transfer line 41 electrically connected to the first signal line 21 may include a second line segment 412 extending along the first direction X, and a first line segment 411 and a third line segment 413 extending along the second direction Y. The first line segment 411 and the third line segment 413 may be disposed between adjacent pixel circuit columns, and the second line segment 412 may be disposed between adjacent pixel circuit columns. In this example, the orthogonal projection of the first transfer line 41 on the base substrate may be located between adjacent pixel circuits. The remaining configuration of the display substrate of this embodiment can be referred to the description of the above embodiment, so it will be omitted here.

[0172] Fig. 24 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Fig. 25 is a schematic diagram of the first signal line of Fig. 24. Figs. 24 and 25 only show the layout of the first signal line around the second display area A2a. The wiring layout around the second display area A2b is similar to the wiring layout around the second display area A2a, so it is omitted here.

[0173] In some exemplary embodiments, as shown in FIG. 24 and FIG. 25, the first signal line 21 may include three first sub signal lines (e.g., including a first first sub signal line 211 and a second first sub signal line 212) extending along the first direction X. The first first sub signal line 211 may be electrically connected to the second first sub signal line 211 via a first transfer line 41 to bypass the second display area A2a, and the second first sub signal line 211 may be electrically connected to the third first sub signal line via another first transfer line to bypass the second display area A2b. For example, the first transfer line 41 may first extend along the second direction Y, then extend along the first direction X, and further extend along the second direction Y. In this example, the first transfer line 41 may be located in the edge area of ​​the second display area A2a. For example, the first first sub-signal line 211, the second first sub-signal line 211, and the first transfer line 41 may be an integral structure, for example, located on the first conductive layer or the second conductive layer. The first signal line in this example is wound through the first transfer line provided in the edge region of the second display area, so as to reduce the load on the first signal line and improve the display uniformity.

[0174] In some examples, as shown in Figures 24 and 25, a shield wiring 61 may be provided in the peripheral region of the second display region A2a. The orthogonal projection of the shield wiring 61 on the base substrate may cover the orthogonal projection of the multiple first transfer lines 41 on the base substrate. In some examples, the orthogonal projection of the shield wiring 61 on the base substrate may be a ring such as a rectangular ring or a circular ring. In this example, the gaps between the multiple first transfer lines 41 can be covered with the shield wiring 61, thereby making it possible to avoid the occurrence of interference phenomena.

[0175] In some examples, the shield wiring 61 may be electrically connected to the first power supply line. For example, the shield wiring 61 may be electrically connected to the first power supply line arranged in the first display area on the upper side and the lower side of the second display area A2a. The shield wiring 61 may have the same layer structure as the first power supply line. For example, the shield wiring 61 may be located in the third conductive layer, and the first signal line 21 may be located in the first conductive layer or the second conductive layer. In another example, the shield wiring 61 may be electrically connected to the first initial signal line or the second initial signal line. For example, the shield wiring 61 may be electrically connected to the first initial signal line or the second initial signal line arranged in the first display area on the left side and the right side of the second display area A2a. The shield wiring 61 may have the same layer structure as the first initial signal line or the second initial signal line, and may be located in the second conductive layer, and the first signal line 21 may be located in the first conductive layer. In another example, the shield wiring 61 may be electrically connected to the second power supply line. However, this embodiment is not limited to this. The shield wiring may be electrically connected to another wiring that supplies a DC signal.

[0176] In some examples, the plurality of first signal lines 21 may include a scan line, a first reset control line, and a light emission control line. In another example, the plurality of first signal lines 21 may include a scan line, a first reset control line, a light emission control line, a first initial signal line, and a second initial signal line. However, this embodiment is not limited thereto. In another example, the plurality of first signal lines 21 may include a first initial signal line and a second initial signal line, and the scan line, the first reset control line, and the light emission control line may be arranged in the manner as in the above-mentioned embodiment.

[0177] Fig. 26 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Fig. 27 is a schematic diagram of the second signal line of Fig. 26. Fig. 26 shows only the arrangement of the first signal line and the second signal line around the second display area A2a. The wiring arrangement around the second display area A2b is similar to the wiring arrangement around the second display area A2a, so it is omitted here.

[0178] In some exemplary embodiments, as shown in FIG. 26 and FIG. 27, the second signal line 31 may include two second sub-signal lines (e.g., including a first second sub-signal line 311 and a second second sub-signal line 312). The first second sub-signal line 311 may be electrically connected to a column of first pixel circuits 11 in a first display area below the second display area A2a, and the second second sub-signal line 312 may be electrically connected to a column of first pixel circuits 11 in a first display area above the second display area A2a. The first pixel circuits connected to the first second sub-signal line 311 of the one second signal line 31 may be located in the same column as the first pixel circuits connected to the second second sub-signal line 312. The first second sub-signal line 311 and the second second sub-signal line 312 may be electrically connected via a second transfer line 42. For example, the second transfer line 42 may first extend along the first direction X, then extend along the second direction Y, and then extend again along the first direction X. In this example, the second transfer line 42 may be located in the edge region of the second display region A2a. In some examples, the first second sub-signal line 311, the second second sub-signal line 312, and the second transfer line 42 of the second signal line 31 may be an integral structure, for example, located in the third conductive layer or the fourth conductive layer. The second signal line in this example bypasses the second display region via the second transfer line in the edge region of the second display region, which can reduce the load of the second signal line and improve the display uniformity.

[0179] In some examples, as shown in Fig. 26, a shield wiring 61 may be provided in the peripheral area of ​​the second display area A2a. The orthogonal projection of the shield wiring 61 on the base substrate may cover the orthogonal projection of the multiple first transfer lines 41 and the multiple second transfer lines 42 on the base substrate. The explanation of the shield wiring 61 and the first signal line 21 can be referred to in the explanation of the above embodiment, so it will be omitted here. In this example, the occurrence of interference phenomena can be avoided by covering the gaps between the multiple first transfer lines 41 and the gaps between the multiple second transfer lines 42 with the shield wiring 61.

[0180] In some examples, the second signal line 31 may include a data line, which may be electrically connected to the first pixel circuits in the same column in the first display area above and below the second display area A2a, and the second effective pixel circuit electrically connected to the second light-emitting element in the same column as the first pixel circuit in the second display area A2a may be electrically connected to another data line. However, this embodiment is not limited thereto. In other examples, the second signal line may further include an initial signal line (e.g., a first initial signal line, a second initial signal line).

[0181] In some exemplary embodiments, the first signal line around the second display region A2a may have the same winding method as the first signal line around the second display region A2b, or may have a different winding method. For example, the first signal line around the second display region A2a may have the winding method shown in FIG. 6 or FIG. 19, while the first signal line around the second display region A2b may have the winding method shown in FIG. 25. Also, the second signal line around the second display region A2a may have the winding method shown in FIG. 11, while the second signal line around the second display region A2b may have the winding method shown in FIG. 27. However, this embodiment is not limited to this.

[0182] FIG. 28 is another schematic diagram of a display substrate in at least one embodiment of the present disclosure. In some examples, as shown in FIG. 28, the display region of the display substrate may include a first display region A1 and a second display region A2. The first display region A1 may surround the second display region A2. The first signal line 21 partitioned by the second display region A2 may be electrically connected by a first transfer line 41 that bypasses the second display region A2 on one side in the second direction Y, thereby realizing that pixel circuits in the same row on both the left and right sides of the second display region A2 receive the same signal. The arrangement of the first transfer line and the arrangement of the second signal line in this embodiment can be referred to in the description of the above embodiment, so they will not be described here. However, this embodiment is not limited thereto. In other examples, the display region of the display substrate may include three or more second display regions.

[0183] At least one embodiment of the present disclosure also provides a display device including a display substrate as described above.

[0184] Fig. 29 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Fig. 29, this embodiment provides a display device including a display substrate 91 and a photosensitive sensor 92 located on the light emission side of a display component layer away from the display substrate 91. There is an overlapping portion between the orthogonal projection of the photosensitive sensor 92 on the display substrate 91 and the second display region A2a or A2b.

[0185] In some exemplary embodiments, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be any product or part having a display function, such as an OLED display, a mobile phone, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigation system, and the embodiments of the present disclosure are not limited thereto.

[0186] The drawings in this disclosure only relate to the structures in this disclosure, and other structures can refer to the general design. Unless there is a conflict, the embodiments in this disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments. It should be understood that those skilled in the art can modify or equivalently replace the technical solutions of this disclosure without departing from the spirit and scope of the technical solutions of this disclosure, and all should be included in the scope of the claims of this disclosure. [Explanation of symbols]

[0187] 10 Second pixel circuit 11 First pixel circuit 12 Second effective pixel circuit 13 First light emitting element 14 Second light-emitting element 15 Invalid pixel circuit 21 First signal line 22 Third signal line 31 Second signal line 32 4th signal line 41 First Transfer Line 41a 1st transfer line 41b Second Transfer Line 41c 3rd Transfer Line 42 Second Transfer Line 42a 2nd Transfer Line 42b Second Transfer Line 42c 2nd Transfer Line 42d 2nd Transfer Line 43 Third Transfer Line 50 Semiconductor layer 51 First conductive layer 52 Second conductive layer 53 Third conductive layer 54 4th conductive layer 61 Shielded wiring 91 Display board 92 Photosensitive Sensor 100 Base Board 101 First insulating layer 102 Second insulating layer 103 Third insulating layer 104 4th insulating layer 111 First reset transistor 112 Threshold compensation transistor 113 Drive transistor 114 Transistor 115 First light emission control transistor 116 Second light emission control transistor 117 Second reset transistor 118 Memory Capacitor 121 First reset transistor 122 Threshold compensation transistor 123 Drive transistor 124 Transistor 125 First light emission control transistor 127 Second reset transistor 128 Memory Capacitor 151 First reset transistor 152 Threshold compensation transistor 153 Drive transistor 154 Transistor 155 First light emission control transistor 156 Second light emission control transistor 157 Second Reset Transistor 158 Memory Capacitor 211 1st sub signal line 212 Second sub-signal line 213 1st sub signal line 231 5th sub-signal line 232 5th sub-signal line 311 Second sub-signal line 311a Second sub-signal line 311b Second sub-signal line 312 Second sub-signal line 312a Second sub-signal line 312b Second sub-signal line 313 Second sub-signal line 313a Second sub-signal line 313b Second sub-signal line 411 First line 411a 1st line 411b First line 412 Second line segment 413 Third line segment 414a 4th line 414b 4th line 1110 Active layer Gate 1111 1120 Active layer Gate 1121 1130 Active layer Gate 1131 1140 Active layer Gate 1141 1150 Active layer Gate 1151 1160 Active layer Gate 1161 1170 Active layer Gate 1171 1181 1st capacitor plate 1182 Second Capacitor Plate 1510 Active layer 1511 Gate 1520 Active layer 1521 Gate 1530 Active layer Gate 1531 1540 Active layer Gate 1541 1550 Active layer 1551 Gate 1560 Active layer Gate 1561 1570 Active layer Gate 1571 1581 1st capacitor plate 1582 2nd capacitor plate

Claims

1. A display substrate including a base substrate, a plurality of pixel circuits, a plurality of first light-emitting elements, a plurality of second light-emitting elements, and at least one first signal line extending in a first direction; the base substrate includes a first display area and at least one second display area, the first display area at least partially surrounding the at least one second display area; the plurality of pixel circuits and the plurality of first light-emitting elements are located in the first display area, the plurality of pixel circuits include a plurality of first pixel circuits and a plurality of second pixel circuits, the plurality of second pixel circuits include a plurality of second effective pixel circuits and a plurality of ineffective pixel circuits; the plurality of second light-emitting elements are located in the at least one second display area, at least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least one first light-emitting element among the plurality of first light-emitting elements, the at least one first pixel circuit is configured to drive the emission of the at least one first light-emitting element, at least one second effective pixel circuit among the plurality of second effective pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements, the at least one second effective pixel circuit is configured to drive the emission of the at least one second light-emitting element, At least one first signal line extending in a first direction is located in the first display area and is electrically connected to a plurality of pixel circuits in the first display area, and the first signal line is partitioned into at least two first sub-signal lines by the at least one second display area; A display substrate, wherein adjacent first sub-signal lines among the at least two first sub-signal lines are electrically connected via a first transfer line, and at least a portion of the first transfer line is located between the plurality of first pixel circuits.

2. The orthogonal projection of the first transfer line on the base substrate is an overlapping portion exists between an orthogonal projection of the first transfer line on the base substrate and an orthogonal projection of at least one ineffective pixel circuit of the first display area on the base substrate; a first transfer line is projected on the base substrate between the first pixel circuits and the second pixel circuits; The display substrate according to claim 1 , wherein the orthogonal projection of the first transfer line on the base substrate is located in a peripheral region of the at least one second display region.

3. 2. The display substrate of claim 1, wherein the first transfer line includes at least a first line segment, a second line segment, and a third line segment connected in sequence, the extension directions of the first line segment and the third line segment are the same, and the extension direction of the second line segment intersects with the extension direction of the first line segment.

4. There is an overlapping portion between the orthogonal projections of the first line segment and the third line segment on the base substrate and the orthogonal projections of a plurality of ineffective pixel circuits of the first display area on the base substrate, and the orthogonal projection of the second line segment on the base substrate is located between the plurality of pixel circuits, or The display substrate according to claim 3 , wherein there is an overlapping portion between the orthogonal projections of the first line segment, the second line segment, and the third line segment on the base substrate and the orthogonal projections of a plurality of ineffective pixel circuits of the first display area on the base substrate.

5. 4. The display substrate of claim 3, wherein the first line segment, the second line segment and the third line segment have a same layer structure, or the first line segment and the third line segment have a same layer structure and the first line segment and the second line segment are located in different conductive layers.

6. In a direction perpendicular to the display substrate, the pixel circuit includes at least an active layer, a first gate metal layer, a second gate metal layer and a first source-drain metal layer provided on the base substrate, and the active layer, the first gate metal layer and the second gate metal layer of the invalid pixel circuit are all provided discontinuously; 5. The display substrate of claim 4, wherein the orthogonal projection of the second segment of the first transfer line on the base substrate is located in an area where the invalid pixel circuit is located, and there is no overlapping portion between the orthogonal projection of the second segment on the base substrate and the orthogonal projection of the active layer, the first gate metal layer, and the second gate metal layer of the invalid pixel circuit on the base substrate.

7. 7. The display substrate of claim 6, wherein a first source / drain metal layer of an ineffective pixel circuit having an overlapping portion with a positive projection of the first line segment or the third line segment of the first transfer line on the base substrate is not electrically connected to an active layer, a first gate metal layer and a second gate metal layer of the ineffective pixel circuit.

8. The display substrate according to claim 6, wherein the first line segment and the third line segment of the first transfer line are located on a side of the first source / drain metal layer away from the base substrate, and the second line segment and the first gate metal layer or the second gate metal layer have the same layer structure.

9. 3. The display substrate according to claim 2, wherein when the orthogonal projection of the first transfer line on the base substrate is located in the peripheral region of the second display region, a shield wiring is provided in the peripheral region of the second display region, and the orthogonal projection of the shield wiring on the base substrate covers the orthogonal projection of the first transfer line on the base substrate.

10. The display substrate of claim 1 , wherein the at least one first signal line comprises at least one of a light emitting control line, a first reset control line, a second reset control line, a scan line, a first initial signal line, and a second initial signal line.

11. at least one second signal line located in the first display area and extending in a second direction, the second direction intersecting the first direction; 2. The display substrate according to claim 1, wherein the second signal line is divided into at least two second sub-signal lines by the at least one second display region, and adjacent second sub-signal lines among the at least two second sub-signal lines are electrically connected via a second transfer line.

12. The display substrate of claim 11 , wherein the at least one second signal line comprises a data line.

13. The display substrate of claim 11 , wherein the second transfer line is located on a side of the second signal line closer to the base substrate in a direction perpendicular to the display substrate.

14. The display substrate of claim 11 , wherein the first transfer line is located on a side of the second transfer line that is away from the second display region.

15. 12. The display substrate of claim 11, wherein a positive projection of the second transfer line on the base substrate is located in a peripheral region of the second display region, a shield wiring is provided in the peripheral region of the second display region, and the positive projection of the shield wiring on the base substrate covers the positive projection of the second transfer line on the base substrate.

16. The display substrate of claim 9 , wherein the shielding wiring is electrically connected to a first power line.

17. a plurality of first signal lines are divided into two groups, the second display area has a first side and a second side opposed to each other in a second direction, the first signal lines of the first group bypass the second display area from a first side thereof via the first transfer lines, the first signal lines of the second group bypass the second display area from a second side thereof via the first transfer lines, the second direction intersects with the first direction, Or, The display substrate of claim 1 , wherein the base substrate includes two second display areas, the two second display areas being aligned in the first direction.

18. 18. The display substrate of claim 17, wherein the first signal line is partitioned into three first sub-signal lines by the two second display areas, the first first sub-signal line and the second first sub-signal line are electrically connected via a first first transfer line, the second first sub-signal line and the third first sub-signal line are electrically connected via a second first transfer line, the first first transfer line bypasses a first second display area, and the second first transfer line bypasses a second second display area.

19. 20. The display substrate of claim 18, wherein the first first transfer line and the second first transfer line are located on the same side of the two second display areas in a second direction, and the second direction intersects with the first direction.

20. A display device comprising the display substrate according to claim 1 .

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