Display substrate, its operation method, and display device

Abstract

A display substrate and an operating method thereof, and a display device, the display unit being located on a base substrate and including a display region and a non-light-emitting region, in a sub-pixel of the display region, a driving transistor controls a magnitude of a driving current flowing through a light-emitting device, the light-emitting device is driven by the driving current to emit light, the scanning signal line extends along a first direction, penetrates the non-light-emitting region and the display region, and transmits a scanning signal, the vertical signal line is located in the display region and extends along a second direction intersecting the first direction, the scanning signal line includes an outer ring portion including a first conductive line and a second conductive line, the first conductive line extends along the first direction and extends from the non-light-emitting region to the display region, the second conductive line extends along the first direction and extends from the non-light-emitting region to the display region, the first conductive line and the second conductive line are spaced apart from the first conductive line in the second direction, the first conductive line and the second conductive line overlap with the vertical signal line, the scanning signal line includes a body portion extending along the first direction, the first conductive line and the second conductive line are electrically connected to the body portion.

Description

[Technical field]

[0001] At least one embodiment of the present disclosure relates to a display substrate and a method for operating the same, and a display device. [Background technology]

[0002] With the development of display technology, OLED technology is increasingly applied to transparent display. Transparent display is an important and unique field of display technology, which means that images are displayed in a transparent state, and viewers can see not only the image on the display device, but also the scene behind the display device. Transparent display devices using AMOLED technology generally divide each pixel area into a display area and a non-emitting area, and pixel driving circuits and light-emitting devices are installed in the display area to realize image display, and the non-emitting area realizes light transmission. Summary of the Invention [Means for solving the problem]

[0003] At least one embodiment of the present disclosure comprises: a display unit disposed on the base substrate, the display unit including a display region and a non-light-emitting region, the display region including sub-pixels, the sub-pixels including driving transistors and light-emitting devices, the driving transistors configured to control a magnitude of a driving current flowing through the light-emitting devices, the light-emitting devices configured to receive the driving current and be driven by the driving current to emit light; a scanning signal line disposed on the base substrate, generally extending along a first direction, penetrating the non-light-emitting region and the display region, and transmitting a scanning signal; a display substrate including a display panel and vertical signal lines extending along a first direction, the scanning signal lines including at least one outer ring portion, each of the at least one outer ring portion including a first conductive line extending generally along the first direction from the non-light emitting region to the display region, and a second conductive line extending generally along the first direction from the non-light emitting region to the display region and spaced apart from the first conductive line in the second direction, the first conductive line and the second conductive line both overlapping with the vertical signal line in a direction perpendicular to the base substrate, the scanning signal lines including a main body portion extending generally along the first direction, the first conductive line and the second conductive line both being electrically connected to the main body portion. A display substrate is provided, in which at least one outer ring part can effectively reduce the load (or resistance) of the scanning signal line and avoid excessive overlap with the vertical signal line, and the first and second conductive wires of the at least one outer ring part can extend from the non-light-emitting region to the display region, and can overlap with the vertical signal line located at the edge of the display region close to the non-light-emitting region in a direction perpendicular to the base substrate, so that when a problem such as a short circuit occurs at the location where the vertical signal line and one of the first and second conductive wires of the same outer ring part overlap, the short-circuited one of the first and second conductive wires can be cut off to stop its operation, thereby avoiding the influence on the display effect of the display unit where it is located, and realizing pixel repair of the display unit.

[0004] For example, in a display substrate according to at least one embodiment of the present disclosure, the scanning signal line includes a first sub-scanning signal line, the first sub-scanning signal line extends generally along the first direction, transmits a first scanning signal, and includes a first outer ring portion. The at least one outer ring portion includes the first outer ring portion, the first sub-scanning signal line includes a first body portion extending generally along the first direction, and a first conductive line of the first outer ring portion and a second conductive line of the first outer ring portion are both electrically connected to the first body portion. The display substrate includes a first power supply line, the first power supply line is connected to a first voltage terminal and configured to provide a first power supply voltage to the sub-pixel, and includes a vertical portion extending generally along the second direction, the vertical signal line includes a vertical portion of the first power supply line, and the first conductive line of the first outer ring portion and the second conductive line of the first outer ring portion overlap with the vertical portion of the first power supply line in a direction perpendicular to the base substrate.

[0005] For example, in a display substrate according to at least one embodiment of the present disclosure, the vertical signal line further includes a data signal line transmitting a data signal, the sub-pixel further includes a data writing transistor configured to transmit the data signal to the driving transistor under control of the first scanning signal, and the first sub-scanning signal line is configured to provide the first scanning signal to the data writing transistor.

[0006] For example, in a display substrate according to at least one embodiment of the present disclosure, the non-light-emitting region of the display unit includes a first non-light-emitting region and a second non-light-emitting region, the first non-light-emitting region is located on a first side of the display region in the first direction, and the second non-light-emitting region is located on a second side of the display region opposite to the first side in the first direction. The first sub-scanning signal line passes through the first non-light-emitting region, the display region, and the second non-light-emitting region in order, and the first body portion includes a first portion located in the first non-light-emitting region and a second portion located in the second non-light-emitting region. The first sub-scanning signal line further includes a first branch portion and a second branch portion, the first branch portion is electrically connected to the first portion of the first body portion and the second portion of the first body portion, and includes a first conductive wire of the first outer ring portion, and the first conductive wire of the first outer ring portion is electrically connected to the first body portion. The second branch portion is electrically connected to a first portion of the first main body portion and a second portion of the first main body portion and includes a second conductive wire of the first outer ring portion, and the second conductive wire of the first outer ring portion is electrically connected to the first main body portion.

[0007] For example, in a display substrate according to at least one embodiment of the present disclosure, the first sub-scanning signal line further includes a second outer ring portion, and the at least one outer ring portion further includes the second outer ring portion, and the first conductive wire of the second outer ring portion and the second conductive wire of the second outer ring portion are both electrically connected to the first body portion. The vertical signal line includes a second power supply line, and the second power supply line is electrically connected to a second voltage terminal and configured to provide the sub-pixel with a second power supply voltage different from the first power supply voltage, and extends along the second direction. The first conductive wire of the second outer ring portion and the second conductive wire of the second outer ring portion overlap with the second power supply line in a direction perpendicular to the base substrate.

[0008] For example, in a display substrate according to at least one embodiment of the present disclosure, a first conducting wire of the first outer ring portion and a second conducting wire of the first outer ring portion extend from the first non-light-emitting region to the display region, and a first conducting wire of the second outer ring portion and a second conducting wire of the second outer ring portion extend from the second non-light-emitting region to the display region. The first sub-scanning signal line further includes an intermediate connection portion, the first outer ring portion and the second outer ring portion are both closed rings, and a first portion of the first main portion, the first outer ring portion, the intermediate connection portion, the second outer ring portion, and the second portion of the first main portion are connected in sequence.

[0009] For example, in a display substrate according to at least one embodiment of the present disclosure, a vertical portion of the first power line is located at a first edge of the display area in the first direction, and the second power line is located at a second edge of the display area opposite the first edge in the first direction.

[0010] For example, in a display substrate according to at least one embodiment of the present disclosure, the scanning signal lines extend generally along the first direction, are aligned and spaced apart from the first sub-scanning signal lines in the second direction, transmit a second scanning signal different from the first scanning signal, and further include a second sub-scanning signal line including a third outer ring portion, the at least one outer ring portion includes the third outer ring portion, the second sub-scanning signal line includes a second body portion extending generally along the first direction, a first conductor of the third outer ring portion and a second conductor of the third outer ring portion are both electrically connected to the second body portion, and the first conductor of the third outer ring portion and the second conductor of the third outer ring portion overlap with a vertical portion of the first power supply line and the second power supply line in a direction perpendicular to the base substrate.

[0011] For example, in a display substrate according to at least one embodiment of the present disclosure, the non-light-emitting region of the display unit includes a first non-light-emitting region and a second non-light-emitting region, the first non-light-emitting region is located on a first side of the display region in the first direction, the second non-light-emitting region is located on a second side of the display region opposite to the first side in the first direction, the second body portion includes a first portion located in the first non-light-emitting region and a second portion located in the second non-light-emitting region, and the second sub-scanning signal line includes a third branch portion and a fourth branch portion, the third branch portion is electrically connected to the first portion of the second body portion and the second portion of the second body portion, includes a first conductive wire of the third outer ring portion, the first conductive wire of the third outer ring portion is electrically connected to the second body portion, the fourth branch portion is electrically connected to the first portion of the second body portion and the second portion of the second body portion, includes a second conductive wire of the third outer ring portion, and the second conductive wire of the third outer ring portion is electrically connected to the second body portion.

[0012] For example, in a display substrate according to at least one embodiment of the present disclosure, a first conductive wire of the third outer ring portion and a second conductive wire of the third outer ring portion each extend from the first non-light-emitting region to the display region and then to the second non-light-emitting region.

[0013] For example, in a display substrate according to at least one embodiment of the present disclosure, an annular area of ​​the third outer ring portion is larger than an annular area of ​​the first outer ring portion and is larger than an annular area of ​​the second outer ring portion.

[0014] For example, in a display substrate according to at least one embodiment of the present disclosure, the first conductive wire of the third outer ring portion and the second conductive wire of the third outer ring portion all overlap with the data signal line in a direction perpendicular to the base substrate, overlap with the vertical portion of the first power line in a direction perpendicular to the base substrate, and overlap with the second power line in a direction perpendicular to the base substrate.

[0015] For example, in a display substrate according to at least one embodiment of the present disclosure, the vertical signal line further includes a detection signal line for transmitting a detection signal, the sub-pixel further includes a detection transistor, the second sub-scanning signal line is configured to provide the second scanning signal to the detection transistor, and the detection transistor is configured to realize external compensation by detecting an electrical characteristic of the sub-pixel using the detection signal under the control of the second scanning signal, and the first conducting wire of the third outer ring portion and the second conducting wire of the third outer ring portion both overlap with the detection signal line in a direction perpendicular to the base substrate.

[0016] For example, in a display substrate according to at least one embodiment of the present disclosure, the display unit includes a plurality of the sub-pixels arranged in an array, the array includes a first pixel row extending along the first direction and a second pixel row extending along the first direction, the first pixel row includes first and second sub-pixels arranged adjacent to each other, the second pixel row includes third and fourth sub-pixels arranged adjacent to each other, the first sub-scanning signal line is configured to provide the first scanning signal to data transistors of the third sub-pixel and the fourth sub-pixel, a first conductive wire of the third outer ring portion is configured to provide the second scanning signal to the detection transistors of the first sub-pixel and the second sub-pixel, and the second conductive wire of the third outer ring portion is configured to provide the second scanning signal to the detection transistors of the third sub-pixel and the fourth sub-pixel.

[0017] For example, in a display substrate according to at least one embodiment of the present disclosure, the data signal lines include a first data line providing the data signal to the first sub-pixel, a second data line providing the data signal to the second sub-pixel, a third data line providing the data signal to the third sub-pixel, and a fourth data line providing the data signal to the fourth sub-pixel, the first data line, the second data line, the third data line, and the fourth data line being arranged spaced apart in the first direction, and the first conductive line of the third outer ring portion and the second conductive line of the third outer ring portion overlap with the first data line, the second data line, the third data line, and the fourth data line in a direction perpendicular to the base substrate.

[0018] For example, in a display substrate according to at least one embodiment of the present disclosure, the display unit further includes an auxiliary scanning line, a first connecting line and a second connecting line. The auxiliary scanning line extends along the first direction, and the first connecting line extends along the auxiliary scanning line. scanning a second connection line electrically connected to the first sub-scanning signal line and the second connection line spaced apart from the first connection line in the second direction; scanning The auxiliary line is electrically connected to the first sub-scanning signal line. scanning The lines are configured to provide the first scanning signal to the data transistor of the first sub-pixel and the data transistor of the second sub-pixel, and the first conductive line of the third outer ring portion and the second conductive line of the third outer ring portion both overlap with the first connecting line and the second connecting line in a direction perpendicular to the base substrate.

[0019] For example, in a display substrate according to at least one embodiment of the present disclosure, the auxiliary scanning line has a first end and a second end opposite to each other in the first direction, the first connecting line is electrically connected to the first end of the auxiliary scanning line and the first outer ring portion, and the second connecting line is electrically connected to the second end of the auxiliary scanning line and the second outer ring portion.

[0020] For example, in a display substrate according to at least one embodiment of the present disclosure, the number of the outer ring portions included in the second sub-scanning signal lines is smaller than the number of the outer ring portions included in the first sub-scanning signal lines.

[0021] For example, in a display substrate according to at least one embodiment of the present disclosure, the first power supply line further includes a horizontal portion electrically connected to the vertical portion and extending generally along the first direction, the horizontal portion including an inner ring portion, the inner ring portion including a third conductive line and a fourth conductive line. The third conductive line extends generally along the first direction and is located in the display area, and the fourth conductive line extends generally along the first direction and is located in the display area and is spaced apart from the third conductive line in the second direction. The third conductive line and the fourth conductive line both overlap with the vertical signal line in a direction perpendicular to the base substrate, and provide the same first power supply voltage to the sub-pixels.

[0022] For example, in a display substrate according to at least one embodiment of the present disclosure, the third conducting wire and the fourth conducting wire both overlap with the data signal line in a direction perpendicular to the base substrate.

[0023] For example, in a display substrate according to at least one embodiment of the present disclosure, the vertical signal line further includes a detection signal line transmitting a detection signal, the scanning signal line further includes a second sub-scanning signal line, the second sub-scanning signal line extends generally along the first direction, is spaced apart from the first sub-scanning signal line in the second direction, and transmits a second scanning signal different from the first scanning signal, the sub-pixel further includes a detection transistor, the second sub-scanning signal line is configured to provide the second scanning signal to the detection transistor, and the detection transistor is configured to realize external compensation by detecting an electrical characteristic of the sub-pixel under control of the second scanning signal, and the third conducting line and the fourth conducting line both overlap with the detection signal line in a direction perpendicular to the base substrate.

[0024] For example, in a display substrate according to at least one embodiment of the present disclosure, the display unit includes a plurality of the sub-pixels arranged in an array, the array includes a first pixel row extending along the first direction and a second pixel row extending along the first direction, the first pixel row includes first and second sub-pixels arranged adjacent to each other, the second pixel row includes third and fourth sub-pixels arranged adjacent to each other, and the data signal lines include a first data line for providing the data signals to the first sub-pixels and a second data line for providing the data signals to the second sub-pixels. a third data line providing the data signal to the third sub-pixel, and a fourth data line providing the data signal to the fourth sub-pixel, wherein the first data line, the second data line, the third data line, the fourth data line, and the detection signal line are arranged spaced apart in the first direction, the detection signal line is sandwiched between the third conducting line and the fourth conducting line and is adjacent to the third conducting line and the fourth conducting line, and the third conducting line and the fourth conducting line all overlap with the third data line, the fourth data line, and the detection signal line in a direction perpendicular to the base substrate.

[0025] For example, in a display substrate according to at least one embodiment of the present disclosure, the sub-pixel includes a driving transistor and a light-emitting device, the driving transistor is configured to control a magnitude of a driving current flowing through the light-emitting device, the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light, and includes a first electrode, and the display unit further includes a pixel defining layer that limits an opening area of ​​the first electrode of the sub-pixel and exposes at least a portion of the outer ring portion.

[0026] For example, in a display substrate according to at least one embodiment of the present disclosure, the display unit further includes a connection structure and a first relay electrode. The connection structure includes a connection part electrically connected to a first part of the first electrode and a second part of the first electrode and located in the non-light-emitting region. The first relay electrode includes a part electrically connected to a first electrode of the driving transistor and located in the non-light-emitting region, the connection part is electrically connected in the non-light-emitting region to the part of the first relay electrode located in the non-light-emitting region, the pixel definition layer includes a part located in the non-display region, the part of the pixel definition layer located in the non-display region has a groove recessed in a direction away from the display region, at least a part of the orthogonal projection of the connection part onto the base substrate is located within the orthogonal projection of the groove onto the base substrate, the groove has an edge facing the connection part, and there is a gap between the edge of the connection part away from the display region in the first direction and the edge of the groove.

[0027] For example, in a display substrate according to at least one embodiment of the present disclosure, the display substrate includes a first power line and a second power line. The first power line is electrically connected to a first voltage end and configured to provide a first power supply voltage to the sub-pixels, and includes a vertical portion extending generally along the second direction, and the second power line is electrically connected to a second voltage end and configured to provide a second power supply voltage different from the first power supply voltage to the sub-pixels, and extends along the second direction. The vertical portion of the first power line and the second power line are arranged to be spaced apart in the first direction, and are respectively located at a first edge of the display area in the first direction and a second edge of the display area opposite to the first edge in the first direction, and a region between an edge of the vertical portion of the first power line away from the second power line and an edge of the second power line away from the vertical portion of the first power line is the display area.

[0028] At least one embodiment of the present disclosure further provides a display device including any one of the display substrates according to the embodiments of the present disclosure.

[0029] At least one embodiment of the present disclosure further provides a method for operating a display substrate applied to any one of the display substrates according to the embodiments of the present disclosure, the method including cutting a portion of one of the first conductive wire and the second conductive wire of the same outer ring portion located in the display area.

[0030] For example, in a method of operating a display substrate according to at least one embodiment of the present disclosure, on the side of the cut portion of one of the first and second conductors of the same outer ring portion, closer to the base substrate, there is no conductive layer that overlaps one of the first and second conductors of the same outer ring portion in a direction perpendicular to the base substrate.

[0031] In order to more clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly described below. It is obvious that the drawings described below are not the limitations of the present disclosure, but are only relevant to some implementations of the present disclosure. [Brief description of the drawings]

[0032] [Figure 1A] 1 is a schematic overall plan view of a display substrate according to an embodiment of the present disclosure; [Figure 1B] FIG. 1 is a block diagram of a display substrate in accordance with at least one embodiment of the present disclosure. [Figure 2A] 2 is an equivalent circuit diagram of a pixel circuit of a display unit of a display substrate according to an embodiment of the present disclosure. [Figure 2B-2D] FIG. 4 is a signal timing diagram of a driving method of a pixel circuit according to an embodiment of the present disclosure. [Figure 3A] 1 is a schematic plan view of a display unit of a display substrate according to at least one embodiment of the present disclosure. [Figure 3B] FIG. 3B is a schematic diagram of a third sub-pixel in FIG. 3A. [Figure 3C] FIG. 3C is an enlarged view of a portion including a connection structure in FIG. 3B. [Figure 4A] FIG. 3C is a schematic cross-sectional view taken along line AA' in FIG. 3B. [Figure 4B]3C is a schematic cross-sectional view taken along lines BB' and CC' in FIG. 3B. [Figure 4C] FIG. 3B is a schematic cross-sectional view taken along line DD' in FIG. 3A. [Figure 4D] 3C is a schematic cross-sectional view of a display substrate according to another embodiment of the present disclosure taken along line AA' in FIG. 3B. [Figure 5A] 3B is a schematic plan view of a first conductive layer of the display unit shown in FIG. 3A. [Figure 5B] 3B is a schematic plan view of a first insulating layer of the display unit shown in FIG. 3A. [Figure 5C] 3B is a schematic plan view of a semiconductor layer of the display unit shown in FIG. 3A. [Figure 5D] 3B is a schematic plan view of a second conductive layer of the display unit shown in FIG. 3A. [Figure 5E] 3B is a schematic plan view of a third insulating layer of the display unit shown in FIG. 3A. [Figure 5F] 3B is a schematic plan view of a third conductive layer of the display unit shown in FIG. 3A. [Figure 5G] 3B is a schematic plan view of a fourth insulating layer of the display unit shown in FIG. 3A. [Figure 5H] 3B is a schematic plan view of a fifth insulating layer of the display unit shown in FIG. 3A. [Figure 5I] 3B is a schematic plan view of a fourth conductive layer of the display unit shown in FIG. 3A. [Figure 5J] 3B is a schematic plan view of a fifth conductive layer of the display unit shown in FIG. 3A. [Figure 5K] FIG. 3B is a schematic plan view of a pixel defining layer of the display unit shown in FIG. 3A. [Figure 6A] FIG. 3B is an enlarged schematic view of portion A in FIG. 3A, including at least one outer annulus. [Figure 6B] FIG. 3B is an enlarged schematic view of portion B in FIG. 3A, including at least one inner ring portion. [Figure 7] FIG. 3C is another schematic cross-sectional view taken along line AA' in FIG. 3B. [Figure 8A] FIG. 8 is an enlarged schematic view of a portion C in FIG. [Figure 8B]8 is an enlarged schematic diagram of a position of portion C in FIG. 7 of another display substrate according to an embodiment of the present disclosure. [Figure 9] FIG. 8B is a schematic plan view of portion C shown in FIG. 8A. [Figure 10] FIG. 2 is a schematic diagram of an arrangement scheme of multiple sub-pixels of one display unit according to an embodiment of the present disclosure. [Figure 11A] 3B is a partial schematic plan view of a first auxiliary unit H1 of the display unit shown in FIG. 3A. [Figure 11B] FIG. 11B is a schematic cross-sectional view taken along line EE' in FIG. 11A. [Figure 11C] 11C is a schematic plan view showing the positional relationship between the second lamination layer, the fourth lamination layer, the fifth lamination layer and the eighth lamination layer in FIG. 11B. FIG. [Figure 12A] 3B is a partial schematic plan view of a second auxiliary unit H2 of the display unit shown in FIG. 3A. [Figure 12B] FIG. 12B is a schematic cross-sectional view taken along line FF' in FIG. 12A. [Figure 13A] 3B is a partial schematic plan view of a third auxiliary unit H3 of the display unit shown in FIG. 3A. [Figure 13B] FIG. 13B is a schematic cross-sectional view taken along line GG' in FIG. 13A. [Figure 14A] FIG. 3B is a schematic diagram of layers, including a pixel defining layer and part of a first electrode, of the display unit shown in FIG. 3A. [Figure 14B] FIG. 14B is an enlarged schematic view of a portion P0 enclosed by a dashed line in FIG. 14A. [Figure 15] 1 is a schematic diagram of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure in conjunction with the drawings of the embodiments of the present disclosure. The embodiments described below are not all the embodiments, but only some of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without requiring creative labor belong to the scope of protection of the present disclosure.

[0034] Unless otherwise defined, technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art to which the present invention belongs. The terms "first", "second" and similar terms used in this disclosure do not denote order, number, or importance, but are merely used to distinguish different components. Similarly, similar terms such as "include" or "comprise" mean that the element or object appearing before the term encompasses the elements or objects listed after the term and their equivalents, without excluding other elements or objects. Similar terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Top", "bottom", "left", "right", and the like are used only to express relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships may change accordingly.

[0035] In this disclosure, an orthogonal projection of a structure onto a base substrate is an orthogonal projection of the structure onto the surface of the base substrate on which each transistor and various signal lines are located.

[0036] In the present disclosure, the statement that structure A and structure B constitute a continuous integrally molded structure means that structure A and structure B are integral structures made of the same material, have no seams, and are uniform in texture, and are formed, for example, by the same patterning process. The letters A and B are used to refer to the corresponding structures described in the specification.

[0037] At least one embodiment of the present disclosure provides a display substrate including a base substrate and a display unit, the display unit is disposed on the base substrate and includes a display region and a non-light-emitting region, the display region includes a sub-pixel, the sub-pixel includes a driving transistor and a light-emitting device, the driving transistor is configured to control a magnitude of a driving current flowing through the light-emitting device, and includes a gate, a first pole and a second pole, the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light, and includes a first electrode, the first electrode includes a first portion and a second portion spaced apart from each other, the display unit further includes a connection structure and a first relay electrode, the connection structure includes a connection portion connected to the first portion of the first electrode and the second portion of the first electrode and located in the non-light-emitting region, the first relay electrode includes a portion connected to the first pole of the driving transistor and located in the non-light-emitting region, and the connection portion is electrically connected in the non-light-emitting region to the portion of the first relay electrode located in the non-light-emitting region.

[0038] At least one embodiment of the present disclosure further provides a display substrate including a base substrate, a display unit, a scanning signal line, and a vertical signal line. The display unit is disposed on the base substrate and includes a display region and a non-light-emitting region, the display region includes a sub-pixel, the sub-pixel includes a driving transistor and a light-emitting device, the driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device, the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light, the scanning signal line is disposed on the base substrate, generally extends along a first direction, passes through the non-light-emitting region and the display region, and transmits a scanning signal. The vertical signal line is disposed on the base substrate and located in the display region, generally extends along a second direction intersecting the first direction. The scanning signal line includes at least one outer ring portion, each of the at least one outer ring portion includes a first conducting line and a second conducting line. A first conductive wire extends generally along the first direction from the non-light-emitting region to the display region, and a second conductive wire extends generally along the first direction from the non-light-emitting region to the display region and is spaced apart from the first conductive wire in the second direction. Both the first conductive wire and the second conductive wire overlap with the vertical signal line in a direction perpendicular to the base substrate, and the scanning signal line includes a body portion extending generally along the first direction, and both the first conductive wire and the second conductive wire are electrically connected to the body portion. In the display substrate, the first conductive wire and the second conductive wire transmit the same scanning signal, and the first conductive wire and the second conductive wire of at least one outer ring portion extend from the non-light-emitting region to the display region and overlap with the vertical signal line.

[0039] At least one embodiment of the present disclosure further provides a display substrate including a base substrate and a display unit. The display unit isThe display unit is disposed on the base substrate and includes a display area. The display area includes a plurality of subpixels, each of which includes a driving transistor and a light-emitting device, the driving transistor being configured to control a magnitude of a driving current flowing through the light-emitting device, and including a gate, a first pole, and a second pole. The light-emitting device is configured to receive the driving current and be driven by the driving current to emit light, and includes a first electrode, the first electrode being connected to the first pole of the driving transistor. The display unit further includes a pixel definition layer that limits an aperture area of ​​the plurality of subpixels, and two adjacent subpixels of the plurality of subpixels of the display unit are an upper subpixel and a lower subpixel, respectively, and a direction perpendicular to an arrangement direction of the upper subpixel and the lower subpixel is a reference direction. The first electrode of the upper subpixel has a first edge close to the lower subpixel and a second edge that intersects with the first edge and is located on a first side of the first edge in the reference direction. The aperture region of the upper subpixel has a first edge close to the lower subpixel and a second edge that intersects with the first edge and is located on the first side of the first edge in the reference direction, a distance between a first edge of the first electrode of the upper subpixel and the first edge of the aperture region of the upper subpixel is a first distance, a distance between a second edge of the first electrode of the upper subpixel and the second edge of the aperture region of the upper subpixel is a second distance, and the first distance is greater than the second distance.

[0040] At least one embodiment of the present disclosure further provides a display substrate including a base substrate and a display unit disposed on the base substrate, the display unit including a display region and a non-light-emitting region, the display region including a sub-pixel, the sub-pixel including a driving transistor and a light-emitting device, the driving transistor configured to control a magnitude of a driving current flowing through the light-emitting device, the light-emitting device configured to receive the driving current and be driven by the driving current to emit light, the light-emitting device including a first electrode and a common electrode connected to a common voltage terminal. the display unit includes an auxiliary electrode line, a first auxiliary electrode, and an auxiliary insulating layer, the auxiliary electrode line includes a vertical portion located in the display area and a horizontal portion located at least partially in the non-light-emitting area and connected to the vertical portion, the first auxiliary electrode is located in the non-light-emitting area and is electrically connected to the common electrode, the auxiliary insulating layer includes a first auxiliary via located in the non-light-emitting area and exposing at least a portion of the horizontal portion, the first auxiliary electrode is connected to the horizontal portion through the first auxiliary via, the horizontal portion, the first auxiliary electrode, and the first auxiliary via constitute one auxiliary unit, the display unit includes a plurality of the auxiliary units, the horizontal portion of the auxiliary electrode line extends along a first direction, the vertical portion of the auxiliary electrode line extends along a second direction intersecting the first direction, and the plurality of auxiliary units are arranged spaced apart from each other in the second direction.

[0041] At least one embodiment of the present disclosure further provides a display device including any one of the display substrates according to the embodiments of the present disclosure.

[0042] The display substrate according to the present disclosure can be applied to a transparent display device, for example, a large transparent display device, which includes a display panel larger than 55 inches. The transparent display device displays an image in a transparent state, and a viewer can see not only the displayed image on the display device, but also the scene behind the display device.

[0043] Organic Light Emitting Diode (OLED) is an active light-emitting display device, which has advantages such as light-emitting, ultra-thin, wide viewing angle, high brightness, high contrast, low power consumption, and fast response speed. According to the driving method, OLED can be divided into two types: Passive Matrix (PM) type and Active Matrix (AM) type. AMOLED is a current-driven device that uses an independent thin film transistor (TFT) to control each sub-pixel, and each sub-pixel can be continuously and independently driven to emit light. In a transparent display device using AMOLED technology, each pixel area is generally divided into a display area and a non-emitting area, and a pixel driving circuit and a light-emitting device 20 are installed in the display area to realize image display, and the non-emitting area realizes light transmission.

[0044] In the manufacturing process of the display device circuit, thin film transistor, or organic light emitting diode, the thin film transistor may deteriorate in characteristics or have an internal short circuit.

[0045] If the thin film transistor is not driven normally, no current or voltage is applied to the organic light emitting diode connected to the thin film transistor, resulting in a dark spot in one pixel or subpixel. Alternatively, if the source electrode and drain electrode driving the thin film transistor are short-circuited, the thin film transistor cannot be driven normally, and the voltage applied to the source electrode is directly applied to the drain electrode, so it is not turned on / off, and the subpixel is always kept in a conductive state, resulting in a bright spot.

[0046] Bright spots are easily visible to the user due to their good visibility, which deteriorates the display quality. Therefore, even if only one bright spot appears in the display area, the display device is considered defective, which causes a problem that the display device is not manufactured as a final product. In particular, dark spots or bright spots in a transparent display device or a top-emission large display device may be visible to the user's eyes, so a solution is needed to avoid or minimize dark spots or bright spots.

[0047] In a transparent display device, since it is necessary to leave a sufficient non-emitting area, the display area space in which to install pixel driving circuits is limited, and it is necessary to reduce the amount of circuit wiring in the display area as much as possible.

[0048] At least one embodiment of the present disclosure provides a display substrate including a base substrate and a display unit, the display unit is disposed on the base substrate and includes a display region and a non-light-emitting region, the display region includes a sub-pixel, the sub-pixel includes a driving transistor and a light-emitting device, the driving transistor is configured to control a magnitude of a driving current flowing through the light-emitting device, and includes a gate, a first pole and a second pole, the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light, and includes a first electrode, the first electrode includes a first portion and a second portion spaced apart from each other, the display unit further includes a connection structure and a first relay electrode, the connection structure includes a connection portion connected to the first portion of the first electrode and the second portion of the first electrode and located in the non-light-emitting region, the first relay electrode includes a portion connected to the first pole of the driving transistor and located in the non-light-emitting region, and the connection portion is electrically connected in the non-light-emitting region to the portion of the first relay electrode located in the non-light-emitting region.

[0049] For example, Fig. 1A is a schematic overall plan view of a display substrate according to an embodiment of the present disclosure. As shown in Fig. 1A, a display substrate 10 includes a base substrate 1 and a display unit P disposed on the base substrate, for example, including a plurality of display units P, for example, the plurality of display units P are arranged in an array. Each display unit P includes a sub-pixel display region 11 and a non-emissive region 12, for example, the display unit P includes a plurality of sub-pixels arranged in an array, the array includes a first pixel row extending along a first direction D1 and a second pixel row extending along the first direction D1, the first pixel row includes a first sub-pixel P1 and a second sub-pixel P2 adjacently disposed, and the second pixel row includes a third sub-pixel P3 and a fourth sub-pixel P4 adjacently disposed. In FIG. 1A, the display area 11 of each display unit P includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3 and a fourth sub-pixel P4 as an example; of course, in other embodiments, the display area 11 of each display unit P also includes more than four or less than four sub-pixels.

[0050] For example, the first sub-pixel P1 is a red sub-pixel (R) that emits red light, the second sub-pixel P2 is a green sub-pixel (G) that emits green light, Third sub-pixel P3 The first sub-pixel P1, the second sub-pixel P2, and the fourth sub-pixel P3 may be a white sub-pixel (W) that emits white light, and the fourth sub-pixel P4 may be a blue sub-pixel (B) that emits blue light. Third sub-pixel P3 The emission color of the fourth sub-pixel P4 is not limited to the above, and is not limited in the embodiments of the present disclosure.

[0051] In some embodiments, the shape of each sub-pixel may be rectangular, diamond, pentagonal, or hexagonal. In one exemplary embodiment, the four sub-pixels may be arranged in a horizontal parallel manner to form a RWBG pixel array. In another embodiment, the four sub-pixels may be arranged in a square, diamond, vertical parallel manner, etc., and the present disclosure is not limited thereto.

[0052] FIG. 2A is an equivalent circuit schematic diagram of pixel circuits of four sub-pixels of one display unit P shown in FIG. 1A. Combining FIG. 1A and FIG. 2A, each of the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3 and the fourth sub-pixel P4 includes a pixel circuit, the pixel circuit includes a driving transistor T1 and a light-emitting device 20, the display area 11 is a light-emitting area and is used to display an image, the non-light-emitting area is a non-light-emitting area and is not used to display an image, and can see through the non-display environment. The driving transistor T1 is configured to control the magnitude of the driving current flowing through the light-emitting device 20, and includes a gate, a first pole and a second pole. The light-emitting device 20 is configured to receive the driving current and be driven by the driving current to emit light. For example, the display substrate is an organic light-emitting diode (OLED) display substrate, and the light-emitting device 20 is an OLED.

[0053] 1B is a block diagram of a display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 1B, for example, each of the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3 and the fourth sub-pixel P4 includes a pixel circuit for driving the light emitting device 20 to emit light. The display substrate may further include a plurality of scan lines, and a plurality of data lines are used to provide scan signals (control signals) and data signals to the sub-pixels, thereby driving the sub-pixels. According to needs, the display substrate may further include a power line, a detection line, etc.

[0054] The pixel circuit includes a driving sub-circuit for driving the light emitting device 20 to emit light, and a detection sub-circuit for detecting an electrical characteristic of the sub-pixel to realize external compensation. The embodiments of the present disclosure do not limit the specific structure of the pixel circuit.

[0055] 1B shows a schematic diagram of a 3T1C pixel circuit for the display substrate. According to needs, the pixel circuit may further include a compensation circuit, a reset circuit, etc., and the pixel circuit may be, for example, a 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. The embodiments of the present disclosure are not limited thereto.

[0056] As shown in FIG. 2A and FIG. 1A , in an exemplary embodiment, each display unit P further includes a first scanning signal line G1, a second scanning signal line G2, a first power line vdd, a second power line vss, four data signal lines D (in FIG. 2A , the four data signal lines D are the first data signal line D1 to the fourth data signal line D4, respectively, where the first sub-pixel P1 is connected to the first data signal line D1, the second sub-pixel P2 is connected to the second data signal line D2, the third sub-pixel P3 is connected to the third data signal line D3, and the fourth sub-pixel P4 is connected to the fourth data signal line D4), a detection signal line S, and four pixel circuits respectively corresponding to the four sub-pixels P1\P2\P3\P4.

[0057] For example, the first scanning signal line G1 and the second scanning signal line G2 extend along the first direction D1 and are arranged along the second direction D2, and the first direction D1 and the second direction D2 cross each other, for example, the first direction and the second direction D2 are perpendicular to each other. The first power supply line vdd, the data signal lines D1\D2\D3\D4, and the detection signal line S may extend along the second direction D2 and be arranged along the first direction D1.

[0058] For example, four data signal lines D and one detection signal line S are disposed between a first power line vdd and a second power line vss, two data signal lines D3\D4 of the four data signal lines D1\D2\D3\D4 are located between the detection signal line S and the first power line vdd, and the other two data signal lines D1\D2 of the four data signal lines D are located between the detection signal line S and the second power line vss. In this way, four sub-pixels are formed by disposing four data signal lines D1\D2\D3\D4 and one detection signal line S between the first power line vdd and the second power line vss, and accordingly, four sub-pixels are formed by disposing one first power line vdd, one second power line vss, and four data signal lines D1\D2\D3\D4 between the two detection signal lines S.

[0059] 2B-2D are signal timing diagrams of a driving method of a pixel circuit according to an embodiment of the present disclosure. Referring to FIG. 2A and FIG. 2B, for example, each pixel circuit of the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3 and the fourth sub-pixel P4 includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitance Cst. A first scanning signal line G1 is connected to the gate electrode of the second transistor T2 in each sub-pixel, and a second scanning signal line G2 is connected to the gate electrode of the third transistor T3 in each sub-pixel. In each sub-pixel, a first pole of the second transistor T2 is electrically connected to a first capacitance electrode of the storage capacitance Cst and the gate of the first transistor T1, a data signal line is connected to a second pole of the second transistor T2, and the second pole of the second transistor T2 is configured to receive a data signal GT, the second transistor T2 is a data transistor and is configured to write the data signal DT to the gate of the first transistor T1 and the storage capacitance Cst in response to a first control signal G1, a first pole of the first transistor T1 is electrically connected to the second capacitance electrode of the storage capacitance Cst and is configured to be electrically connected to a first electrode of the light-emitting element 20, a first power supply line VDD is connected to the second pole of the first transistor T1, and the second pole of the first transistor T1 is configured to receive a first power supply voltage V1 (e.g., a high power supply voltage VDD), No.The first transistor T1 is a driving transistor, configured to control a current for driving the light-emitting element under the control of the voltage of the gate of the first transistor T1, the first pole of the third transistor T3 is electrically connected to the first pole of the first transistor T1 and the second capacitance electrode of the storage capacitance Cst, the detection signal line S is connected to the second pole of the third transistor T3, the second pole of the third transistor T3 is connected to the first detection line S and is configured to be connected to an external detection circuit 11, the third transistor T3 is a detection transistor, configured to realize external compensation by detecting the electrical characteristics of the subpixel to which it belongs in response to the second control signal G2, the electrical characteristics including, for example, the threshold voltage and / or carrier mobility of the first transistor T1, or the threshold voltage, driving current, etc. of the light-emitting element. The external detection circuit 11 includes, for example, general circuits such as a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), which will not be further described in the embodiments of the present disclosure.

[0060] The transistors employed in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure will be described using thin film transistors as an example. The source and drain of the transistor employed here may be structurally symmetrical, so the source and drain may not be structurally distinct. In the embodiments of the present disclosure, in order to distinguish between the two poles of the transistor other than the gate, one is directly described as the first pole and the other as the second pole. In addition, when distinguishing according to the characteristics of the transistor, the transistor can be divided into N-type and P-type transistors. When the transistor is a P-type transistor, the on voltage is a low level voltage (e.g., 0V, -5V, -10V or other suitable voltage), and the off voltage is a high level voltage (e.g., 5V, 10V or other suitable voltage), and when the transistor is an N-type transistor, the on voltage is a high level voltage (e.g., 5V, 10V or other suitable voltage), and the off voltage is a low level voltage (e.g., 0V, -5V, -10V or other suitable voltage). It should be noted that in the following description, the transistors in FIG. 1B are all N-type transistors as an example, but this is not intended to limit the present disclosure.

[0061] Below, the operation principle of the pixel circuit shown in FIG. 2A will be described in conjunction with the signal timing diagrams shown in FIGS. 2B-2D. FIG. 2B shows a signal timing diagram of the display process of the pixel circuit, and FIGS. 2C and 2D show signal timing diagrams of the detection process of the pixel circuit.

[0062] For example, as shown in FIG. 2B, the display process of an image of each frame includes a data writing and reset stage 1 and a light emitting stage 2. FIG. 2B shows the timing waveforms of each signal in each stage. The operation process of the 3T1C pixel circuit includes a data writing and reset stage 1, in which the first control signal G1 and the second control signal G2 are both on signals, the second transistor T2 and the third transistor T3 are conductive, and the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2. ,aThe analog-to-digital converter writes a reset signal to the first electrode of the light-emitting element (e.g., the anode of an OLED) through the first detection line 130 and the third transistor T3, and the first transistor T1 is turned on and generates a driving current to charge the first electrode of the light-emitting element to an operating voltage. In the light-emitting stage 2, the first control signal G1 and the second control signal G2 are both off signals, and due to the bootstrap effect of the storage capacitance Cst, the voltage across the storage capacitance Cst does not change, so the first transistor T1 operates in a saturated state and the current does not change, driving the light-emitting element to emit light.

[0063] For example, Fig. 2C shows a signal timing diagram when the pixel circuit detects the threshold voltage. The operation process of the 3T1C pixel circuit is as follows: the first control signal G1 and the second control signal G2 are both ON signals, the second transistor T2 and the third transistor T3 are conductive, and the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2; ,a The analog-to-digital converter writes a reset signal to the first electrode (node ​​S) of the light-emitting element via the first detection line 130 and the third transistor T3, charges the node S until the first transistor T1 is conductive and turned off, and the digital-to-analog converter samples the voltage on the first detection line 130 to obtain the threshold voltage of the first transistor T1. This process can be performed, for example, while the display device is shut down.

[0064] For example, Fig. 2D shows a signal timing diagram when the pixel circuit detects the threshold voltage. The operation process of the 3T1C pixel circuit is as follows: in the first stage, the first control signal G1 and the second control signal G2 are both ON signals, the second transistor T2 and the third transistor T3 are conductive, and the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2; ,aThe analog-to-digital converter writes a reset signal to the first electrode (node ​​S) of the light-emitting element through the first detection line 130 and the third transistor T3. In a second stage, the first control signal G1 is an off signal, the second control signal G1 is an on signal, the second transistor T2 is cut off, and the third transistor T3 is turned on. , No. The first detection line 130 is floated, and due to the bootstrap effect of the storage capacitance Cst, the voltage across the storage capacitance Cst does not change, the first transistor T1 operates in a saturated state and the current does not change, driving the light-emitting element to emit light, and the digital-to-analog converter samples the voltage on the first detection line 130 and adjusts the magnitude of the light-emitting current to calculate the carrier mobility in the first transistor T1. For example, the process can be performed in a blanking phase between display phases.

[0065] Through the above detection, the electrical characteristics of the first transistor T1 can be obtained and a corresponding compensation algorithm can be realized.

[0066] For example, as shown in Fig. 1B, the display substrate 10 may further include a data driving circuit 03 and a scan driving circuit 04. The data driving circuit 03 is configured to send a data signal, such as the above-mentioned data signal DT, according to demand (such as an image signal input to the display device). The pixel circuit of each sub-pixel is further configured to receive the data signal and apply the data signal to the gate of the first transistor. The scan driving circuit 04 is configured to output various scan signals, such as the above-mentioned first control signal G1 and second control signal G2, and is, for example, a gate driving circuit (GOA) fabricated on an integrated circuit chip (IC) or directly on the display substrate.

[0067] For example, the display substrate 10 further includes a control circuit 02. For example, the control circuit 02 is configured to control the data driving circuit 03 to apply a data signal, and to control the gate driving circuit 04 to apply a scanning signal. An example of the control circuit 02 is a timing control circuit (T-con). The control circuit 02 may be in various forms, for example, includes a processor 021 and a memory 022, the memory 022 includes executable code, and the processor 021 executes the executable code to perform the detection method.

[0068] For example, the processor 021 may be a central processing unit (CPU) or other type of processing device having data processing and / or instruction execution capabilities, and may include, for example, a microprocessor, a programmable logic controller (PLC), etc.

[0069] For example, the memory 022 may include one or more computer program products, which may include various types of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or high-speed cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash, etc. One or more computer program instructions may be stored in the computer-readable storage medium, and the processor 021 may perform the desired functions according to the program instructions. Various application programs and various data, such as electrical characteristic parameters obtained in the above detection method, may also be stored in the computer-readable storage medium.

[0070] FIG. 3A is a schematic plan view of one display unit P of a display substrate 10 according to at least one embodiment of the present disclosure, FIG. 3B is a schematic view of a third sub-pixel P3 in FIG. 3A, FIG. 3C is an enlarged view of a portion L including a connection structure in FIG. 3B, and FIG. 4A is a schematic cross-sectional view along line A-A' in FIG. 3B. Referring to FIGS. 3A-3C and 4A, the light-emitting device 20 includes a first electrode 2 including a first portion 21 and a second portion 22 spaced apart from each other. The display unit P further includes a connection structure 3 and a first relay electrode 4. The connection structure 3 connects the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2, and includes a connection portion 30 located in the non-light-emitting region 12. The first relay electrode 4 is connected to the first pole T1s of the driving transistor T1 and includes a portion located in the non-light-emitting region 12, and the connection portion 30 is electrically connected in the non-light-emitting region 12 to the portion of the first relay electrode 4 located in the non-light-emitting region 12. In the display substrate 10 according to the embodiment of the present disclosure, multiple portions of the first electrode 2, for example, the first portion 21 and the second portion 22, are connected to the first pole T1s of the driving transistor T1 via the connection portion 30 and the first relay electrode 4. In this manner, the aperture region of one subpixel (taking the third subpixel P3 as an example) includes a first subopening 601 and a second subopening 602 (shown in FIG. 5K), and the first subopening 601 and the second subopening 602 are regions corresponding to the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2, respectively. For example, the first portion 21 of the first electrode 2 covers the first subopening 601, and the second portion 22 of the first electrode 2 covers the second subopening 602. The first part 21 of the first electrode 2 and the second part 22 of the first electrode 2 are electrically connected to the connection part 30 located in the non-light-emitting region 12 in the non-light-emitting region 12, and are connected to the first pole T1s of the driving transistor T1 via the part of the first relay electrode 4 located in the display region 11. When a display defect such as a dark spot occurs in one of the two parts of the sub-pixel opening region, the first or second part of the first electrode 2 corresponding to that position is blocked, so that the dark spot occurrence region does not perform the display function, reducing the dark spot defect of the sub-pixel, realizing the repair of the sub-pixel, and improving the image quality, thereby ensuring the excellent display effect of the product.In addition, the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 are electrically connected to the connection portion 30 located in the non-light-emitting region 12, and are connected to the first pole T1s of the driving transistor T1 through the portion of the first relay electrode 4 located in the display region 11, so that a via for connecting the connection portion 30 and the first relay electrode 4 is easily manufactured in the non-light-emitting region 12. Compared with the embodiment in which the first portion 21 and the second portion 22 of the first electrode 2 and the first relay electrode 4 are connected in the display region 11, a pixel circuit is not installed in the non-light-emitting region 12, so that the alignment process for manufacturing a via for connecting the connection portion 30 and the first relay electrode 4 at a position corresponding to the connection portion 30 in the non-light-emitting region 12 according to the embodiment of the present disclosure is easy, and the yield can be obviously increased.

[0071] It should be noted that in at least one embodiment of the present disclosure, the vertical portion vdd1 of the first power line vdd and the second power line vss are arranged apart from each other in the first direction D1, and are respectively located at a first edge in the first direction D1 of the display area 11 and a second edge opposite to the first edge in the first direction D1 of the display area 11. The area between the edge of the vertical portion vdd1 of the first power line vdd away from the second power line vss and the edge of the second power line vss away from the vertical portion vdd1 of the first power line vdd is the display area 11.

[0072] For example, as shown in FIG. 4A, the light-emitting element is an organic light-emitting diode, and includes a first electrode 2, a second electrode 24, and a light-emitting layer 23 located between the first electrode 2 and the second electrode 24. For example, the first electrode has a high work function material as an anode, and is, for example, an ITO / Ag / ITO laminated structure, or an ITO / Al / ITO laminated structure (sandwich structure), or an ITO / (Al+Ag) / ITO laminated structure (sandwich structure). Of course, the first electrode is not limited to the sandwich structure, and the material of the first electrode is not limited to the types listed above. The second electrode 24 has a low work function material as a cathode, and is, for example, a semi-transparent metal or metal alloy material such as an Ag / Mg alloy material. For example, the light-emitting element has a top-emission structure, and the first electrode 2 has a reflective property, while the second electrode 122 has a transmissive or semi-transparent property.

[0073] 3B-3C and 4A, the first relay electrode 4 includes a first relay portion 41, which is located in the display area 11 and connected to the first electrode of the drive transistor T1. A portion of the first relay electrode 4 located in the non-light-emitting area 12 includes a second relay portion 42, which is connected to the first relay portion 41, the connection portion 30 and the second relay portion 42 are disposed in different layers, and the connection portion 30 is connected to the second relay portion 42 in the non-light-emitting area 12 through a first via V0.

[0074] For example, as shown in FIG. 4A , the display unit P further includes a second relay electrode 5, which is located in the non-light-emitting region 12 and between the connection portion 30 and the second relay portion 42 in a direction perpendicular to the base substrate 1. The orthogonal projection of the second relay electrode 5 onto the base substrate 1 is the orthogonal projection of the connection portion 30 onto the base substrate 1 and Second relay section 42 Both of these at least partially overlap with the orthogonal projections onto the base substrate 1. The connection portion 30 is connected to the second relay portion 42 via the second relay electrode 5, and is connected via a plurality of segments, which reduces the via depth required when the connection portion 30 is directly connected to the second relay portion 42 via a single via, thereby increasing the manufacturing yield of the display substrate.

[0075] 4A, the display substrate 10 further includes a first insulating layer 101, a second insulating layer 102 located on the side of the first insulating layer 101 that is distant from the base substrate 1, a third insulating layer 103 located on the side of the second insulating layer 102 that is distant from the base substrate 1, and a fourth insulating layer 104 located on the side of the second relay electrode 5 that is distant from the third insulating layer 103 in a direction perpendicular to the base substrate 1, and the interlayer insulating layer 105 is located on the side of the fourth insulating layer 104 that is distant from the third insulating layer 103 in a direction perpendicular to the base substrate 1. The first via V0 includes a first sub-via V01 that penetrates the first insulating layer 101 and the third insulating layer 103, and the second relay electrode 5 is connected to the second relay portion 42 through the first sub-via V01. No. The 1 via V0 further includes a second sub-via V02 that penetrates the fourth insulating layer 104, and the connection portion 30 is connected to the second relay electrode 5 via the second sub-via V02, thereby realizing the connection of the connection portion 30 to the second relay portion 42 via a multi-stage via.

[0076] For example, the first relay portion 41 and the second relay portion 42 have a continuous integrally molded structure. For example, the material of the first relay electrode 4 is a metal material such as copper, aluminum, chromium, a copper alloy, an aluminum alloy, a chromium alloy, or a manganese alloy, but is not limited to the above types.

[0077] For example, the display unit P further includes an interlayer insulating layer 105, which is not located in the non-light-emitting region 12 but is located in the display region 11, and is located between the first electrode 2 and the second relay electrode 5 in a direction perpendicular to the base substrate 1. As shown in FIG. 4A and FIG. 5H, the first electrode 2 is electrically connected to the first pole T1s of the driving transistor T1 through an opening O1 penetrating the interlayer insulating layer 5 along a direction perpendicular to the base substrate 1. For example, the opening O1 communicates with the second sub-via V02, and the first electrode 2 enters the second sub-via V02 through an opening O1 penetrating the interlayer insulating layer 5 and is connected to the second relay electrode 5. For example, the orthogonal projection of the first via onto the base substrate 1 is located within the orthogonal projection of the opening O1 onto the base substrate 1, that is, the orthogonal projection of the second sub-via V02 and the first sub-via V01 onto the base substrate 1 is located within the orthogonal projection of the opening O1 onto the base substrate 1. In this way, the first electrode 2 and the first pole T1s of the driving transistor T1 can be electrically connected through the large opening O1 in the interlayer insulating layer 105 in the non-light-emitting area, and the connection between the connection part 30 and the second relay electrode 5 can be easily realized in the non-light-emitting area. When a large opening O1 is made in the non-light-emitting area, the requirements for the manufacturing process are low, it is easy to realize, the accuracy of the manufactured opening O1 is high, and the impact on other surrounding structures is small, and the problems of low yield of via manufacturing and large impact on surrounding structures due to the spatial limitation of drilling in the insulating layer of the display area 11 are avoided.

[0078] For example, as shown in Fig. 4A, the interlayer insulating layer 105 is not located in the non-light emitting region 12A, but is located in the display region 11, i.e., does not include the portion located in the non-light emitting region 12A. For example, in the manufacturing process of the interlayer insulating layer 105, the portion of the material layer for forming the interlayer insulating layer 105 located in the non-light emitting region 12A is completely removed by a patterning process, so that the region in the non-light emitting region that is in the same layer as the interlayer insulating layer 105 is configured as an opening O1, i.e., the orthogonal projection of the opening O1 onto the base substrate 1 is located within the non-light emitting region 12A, and the area of ​​the orthogonal projection of the opening O1 onto the base substrate 1 is equal to the area of ​​the non-light emitting region 12A. In this way, by not providing the interlayer insulating layer 105 in the non-light emitting region, the manufacturing difficulty of the interlayer insulating layer 105 is further reduced and the manufacturing yield of the display substrate is increased, compared to the embodiment in which a via is manufactured in the non-display region 12A for the first electrode 2 to pass through.

[0079] For example, the area of ​​the opening O1 as orthogonally projected onto the base substrate 1 is larger than the area of ​​one subpixel adjacent to the opening O1 as orthogonally projected onto the base substrate 1. For example, combining Figures 4A and 1, in the arrangement direction of the display region 11 and the non-light-emitting region 12A, the maximum width W1 of the opening O1 is larger than the maximum width W2 of one subpixel, and here we take one subpixel P3 adjacent to the opening O1 as an example.

[0080] In another embodiment, for example, as shown in FIG. 4D, the orthogonal projection of the opening O1 on the base substrate 1 is located in the non-light-emitting region 12A, and the area of ​​the orthogonal projection of the opening O1 on the base substrate 1 is smaller than the area of ​​the non-light-emitting region 12A. That is, in the process of manufacturing the interlayer insulating layer 105, a part of the part of the material layer for forming the interlayer insulating layer 105 located in the non-light-emitting region 12A is removed by a patterning process to form the opening O1, and the opening O1 is a large via penetrating the interlayer insulating layer 105, and at least a part of the edge of the opening O1 is surrounded by the material of the interlayer insulating layer 105. Other features and corresponding technical effects of the embodiment shown in FIG. 4D are all similar to those of FIG. 4A, and the description of FIG. 4A may be referred to.

[0081] For example, as shown in Fig. 4A, the interlayer insulating layer 105 has a fault at the boundary between the display area 11 and the non-light emitting area 12, i.e., a staircase structure 001 is present at the edge of the interlayer insulating layer 105 close to the non-light emitting area 12, and the first electrode 2 covers the staircase structure 001, thereby extending to the non-light emitting area 12 across the staircase structure 001, and the interlayer insulating layer 105 is not provided on the side of the staircase structure 001 close to the non-light emitting area 12, so that the connection portion 30 may be located in the step of the staircase structure 001 and in the space close to the non-light emitting area 12. Compared with the embodiment in which the interlayer insulating layer 105 is located in the display area 11 and the non-light emitting area 12, this embodiment can avoid the need to form a via in the interlayer insulating layer 105 for connecting the connection portion 30 and the second relay electrode 5, which simplifies the manufacturing process of the display substrate and is of great significance in improving the yield of the display substrate. The interlayer insulating layer 105 has a large thickness in a direction perpendicular to the base substrate 1, for example, the thickness of the interlayer insulating layer 105 in a direction perpendicular to the base substrate 1 is greater than 6000 Å, thereby fulfilling its insulating function and its function as a flat layer. When a via is manufactured to connect the connection portion 30 and the second relay electrode 5 penetrating the interlayer insulating layer 105, the size of the via is different from that of the via for other purposes in the interlayer insulating layer 105 in a direction parallel to the base substrate, for example, the size of the via is required to be large in a direction parallel to the base substrate, so that when a plurality of types of vias penetrating the interlayer insulating layer 105 are manufactured by the same patterning process, it is difficult to simultaneously meet these different sizes, and it is difficult to ensure the alignment rate of the mask, and the thickness of the interlayer insulating layer 105 is large, so that it is difficult to meet the accuracy rate of these different sizes during the etching process. However, the above-described aspect of the embodiment of the present disclosure avoids fabricating a via in the interlayer insulating layer 105 for connecting the connection portion 30 and the second relay electrode 5, penetrating the interlayer insulating layer 105, thereby making it possible to avoid the above-described problem.

[0082] For example, the material of the interlayer insulating layer 105 is an organic insulating material, which may include, for example, a resin material, an acrylic material, etc., and may be, for example, polyimide (PI), acrylate, epoxy resin, polymethylmethacrylate (PMMA), etc., but is not limited to the above-mentioned types. For example, the interlayer insulating layer 105 is a planarization layer.

[0083] For example, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 are, for example, inorganic insulating layers, for example, insulating materials including oxides of silicon such as silicon oxide, silicon nitride, and silicon nitroxide, nitrides of silicon, and nitroxides of silicon, or metal nitroxides such as aluminum oxide and titanium nitride.

[0084] For example, as shown in FIG. 3A, the display substrate 10 further includes a first signal line G1 / G2 and a second signal line D1-D4 disposed on the base substrate 1. The first signal line G1 / G2 transmits a scanning signal. For example, the first signal line includes a first sub-scanning signal line G1 and a second sub-scanning signal line G2, the first sub-scanning signal line G1 transmits a first scanning signal, and the second sub-scanning signal line G2 transmits a second scanning signal, for example, the first scanning signal and the second scanning signal may be scanning signals for each row, for example, the first scanning signal and the second scanning signal are the same scanning signal, see FIG. 2B above. Or, in another embodiment, the first scanning signal and the second scanning signal are different signals. For example, the second signal line D1-D4 transmits a data signal DT. The first signal line generally extends along a first direction D1, and the second signal lines D1-D4 generally extend along a second direction D2 intersecting the first direction D1. The sub-pixel further includes a data writing transistor T2 configured to transmit a data signal to the driving transistor T1 under control of a first scanning signal.

[0085] It should be noted that "extending generally along the first direction D1" includes extending substantially along the first direction D1, and may be at least generally along the first direction D1. For example, in some examples, the first signal line extending generally along the first direction D1 may have a certain curved portion, or in some examples, the first signal line extending generally along the first direction D1 may have a certain curved portion. First direction D1 The strip-like edge extending along the direction may not be a smooth line, for example, the edge may have burrs or sawtooth, in short, it is sufficient that the overall extension tendency is along the first direction D1. The same is true for "extending along the second direction D2 as a whole." The same is true for "extending along a certain direction as a whole" mentioned in this disclosure.

[0086] For example, while combining Fig. 3B-3C, the connection structure 3 includes at least two extension parts, and the at least two extension parts include a first extension part 31 and a second extension part 32. The first extension part 31 has a first end and a second end opposite to the first end, and extends from the display area 11 to the non-light emitting area 12, the first end of the first extension part 31 is connected to the first part 21 of the first electrode 2, and the second end of the first extension part 31 is located in the non-light emitting area 12. The second extension part 32 has a first end and a second end opposite to the first end, and extends from the display area 11 to the non-light emitting area 12, the first end of the second extension part 32 is connected to the second part 22 of the first electrode 2, and the second end of the second extension part 32 is located in the non-light emitting area 12. The connection part 30 is connected to the second end of the first extension part 31 and the second end of the second extension part 32. In this way, the connection portion 30 is connected to the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 via at least two channels, i.e., the first extension portion 31 and the second extension portion 32, respectively. When a display defect such as a dark spot occurs in one of the region of the first portion 21 corresponding to the first electrode 2 and the region of the second portion 22 corresponding to the first electrode 2 in the opening region of one subpixel, for example the third subpixel P3, one of the first extension portion 31 and the second extension portion 32 corresponding to the region where the display defect such as a dark spot occurs is cut, thereby not displaying the region where the display defect such as a dark spot occurs. The first extension portion 31 and the second extension portion 32 are strip-shaped extending along the first direction D1 and are easy to cut, thereby making it easy to repair the subpixel and improving the display quality.

[0087] For example, the second end of the first extension portion 31 has a first cuttable portion 310, and the second end of the second extension portion 32 has a second cuttable portion 320. At a position directly opposite the first cuttable portion 310 on the side of the first cuttable portion 310 close to the base substrate 1, there is no conductive layer overlapping the first cuttable portion 310 in a direction perpendicular to the base substrate 1, and at a position directly opposite the second cuttable portion 320 on the side of the second cuttable portion 320 close to the base substrate 1, there is no conductive layer overlapping the second cuttable portion 320 in a direction perpendicular to the base substrate 1. In this way, when a display defect such as a dark spot occurs in a subpixel, other conductive layers are not damaged in the process of cutting the first cuttable portion 310 or the second cuttable portion 320, and thus cutting is easy, repair of the subpixel is realized, and display quality is improved.

[0088] For example, as shown in FIG. 3C, the maximum width W of the gap between the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 in the second direction D2 SP is the maximum width W of the connection portion 30 in the second direction D2 C By making the width smaller than this, it is ensured that the connection portion 30 has a sufficient width in the second direction D2 to connect the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2, and the distance between the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 is not too large and does not occupy too much space, thereby simultaneously realizing a display panel with a high PPI.

[0089] For example, the first portion 21 of the first electrode 2, the second portion 22 of the first electrode 2, the first extension portion 31, the second extension portion 32, and the connection portion 30 are a continuous integrally molded structure, which simplifies the structure of the display substrate. The continuous integrally molded structure can be formed by performing the same patterning process on the same material layer, which simplifies the manufacturing process of the display substrate.

[0090] For example, as shown in FIG. 3A-3B, each subpixel further includes a first power supply line vdd, the first power supply line vdd is connected to the first voltage end VDD and configured to provide a first power supply voltage to the subpixel, the first power supply line vdd is disposed in the same layer as the first pole of the driving transistor T1, and includes a vertical portion vdd1, the vertical portion vdd1 generally extends along the second direction D2 and is connected to its adjacent subpixel. For example, the first power supply line vdd further includes a horizontal portion vdd2, the horizontal portion vdd2 is electrically connected to the vertical portion and generally extends along the first direction D1 to be connected to each subpixel of the display unit, thereby providing the first power supply voltage to each subpixel of the display unit. For example, the horizontal portion vdd2 in FIG. 3B is connected to the third subpixel P3 and the fourth subpixel P4, and FIG. 3A shows the vertical portion vdd1 in FIG. 3B. vdd1 and further includes another horizontal portion vdd2 connected to the first sub-pixel P1 and the second sub-pixel P2, thereby realizing providing the first power supply voltage from the vertical portion vdd1 to each sub-pixel of the display unit. For example, the first extension portion 31 and the second extension portion 32 extend across the first power supply line vdd and the second signal line to the non-light-emitting region 12 and are connected to a connection portion located in the non-light-emitting region 12.

[0091] 3A, the non-emitting area 12 and the display area 11 are aligned in the second direction D2, the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 are aligned in the second direction D2, and the first extension portion 31 and the second extension portion 32 extend generally along the first direction D1. This arrangement can coordinate the positions of the non-emitting areas of the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 corresponding to the sub-pixels in which they are located, thereby making it easy to extend the first extension portion 31 and the second extension portion 32 from the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 to the non-emitting area 12, and realize the connection between the connection portion 30 located in the non-emitting area 12 and the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2.

[0092] For example, the non-light-emitting region 12 includes a first non-light-emitting region 12A and a second non-light-emitting region 12B, the first non-light-emitting region 12A is located on a first side in a first direction D1 of the display region 11, and the second non-light-emitting region 12B is located on a second side opposite to the first side in the first direction D1 of the display region 11. The first sub-pixel P1 and the third sub-pixel P3 are adjacent to the first non-light-emitting region 12A, and the second sub-pixel P2 and the fourth sub-pixel P4 are adjacent to the first non-light-emitting region 12A. A connection structure 3 is provided corresponding to each of the sub-pixels, and the connection structure 3 connects the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 of the adjacent sub-pixel. The connection portion 30 of the connection structure 3 corresponding to the first sub-pixel P1 and the connection portion 30 of the connection structure 3 corresponding to the third sub-pixel P3 are located in the first non-light-emitting region 12A. The connection portion 30 of the connection structure 3 corresponding to the second subpixel P2 and the connection portion 30 of the connection structure 3 corresponding to the fourth subpixel P4 are located in the second non-emissive region 12B, whereby the first electrodes of each subpixel of the display unit P both include a first portion and a second portion, and the first portion and the second portion of the first electrode of each subpixel can be connected to the first pole T1s of the driving transistor T1 located in the display region 11 via the connection portion and the first relay electrode (or the first relay electrode and the second relay electrode) located in the corresponding non-emissive region.

[0093] For example, as shown in FIG. 3A, the first signal line G1 / G2, which provides scanning signals to the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3 and the fourth sub-pixel P4, is located in the boundary region between the first pixel row and the second pixel row, thereby providing scanning signals to both the first pixel row and the second pixel row on both sides of the boundary region.

[0094] For example, the planar pattern of the first sub-pixel P1 and the planar pattern of the second sub-pixel P2 are symmetrical with respect to an axis of symmetry extending along the second direction D2, the planar pattern of the third sub-pixel P3 and the planar pattern of the fourth sub-pixel P4 are symmetrical along the axis of symmetry, and the planar pattern of the first non-emitting area 12A and the planar pattern of the second non-emitting area 12B are symmetrical with respect to the axis of symmetry, which rationally utilizes space and improves the uniformity of the display substrate, thereby improving the display uniformity of the display area and reducing the difficulty of manufacturing the display substrate.

[0095] 4A , for example, the display unit P further includes a pixel defining layer 6 including a first portion 61 and a second portion 62. The first portion 61 is located between the first electrodes 2 of adjacent sub-pixels to limit an aperture area 60 of the sub-pixels, and the light-emitting layer 23 of the light-emitting device 20 is located at least in the aperture area 60. The second portion 62 is located between the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 to separate the first portion 21 of the first electrode 2 from the second portion 22 of the first electrode 2.

[0096] For example, as shown in FIG. 4A , the orthogonal projection of the connection portion 30 onto the base substrate 1 is located within the orthogonal projection of the first portion 61 of the pixel defining layer 6 onto the base substrate 1, thereby avoiding the connection portion 30 and the first portion 61 of the pixel defining layer 6 from occupying independent spaces, saving space, and using the first portion 61 of the pixel defining layer 6 to provide a protective effect for the connection portion 30.

[0097] For example, the light-emitting elements of the display substrate 10 according to some embodiments of the present disclosure may adopt a top emission structure.

[0098] 4A, for each subpixel, take the third subpixel P3 as an example, further includes a first capacitance C1 including a first plate Ca and a second plate Cb. The first plate Ca is electrically connected to the gate T1g of the driving transistor T1 and is disposed in the same layer as the gate of the driving transistor T1, for example, the first plate Ca and the gate T1g of the driving transistor T1 are a continuous integral structure, and the orthogonal projection of the second plate Cb onto the base substrate 1 and the orthogonal projection of the first plate Ca onto the base substrate 1 at least partially overlap.

[0099] For example, as shown in FIG. 4A, the subpixel further includes a second capacitance C2 including a first electrode plate Ca and a third electrode plate Cc, taking the third subpixel P3 as an example. The third electrode plate Cc includes an overlapping portion and a non-overlapping portion, and the orthogonal projection of the overlapping portion onto the base substrate 1 overlaps with the orthogonal projection of the first electrode plate Ca onto the base substrate 1, and the orthogonal projection of the non-overlapping portion onto the base substrate 1 does not overlap with the orthogonal projection of the first electrode plate Ca onto the base substrate 1 and at least partially overlaps with the orthogonal projection of the second electrode plate Cb onto the base substrate 1. FIG. 4B is a schematic cross-sectional view taken along lines B-B' and C-C' in FIG. 3B. As shown in FIG. 4B, the non-overlapping portion and the second electrode plate Cb are connected via the second via V2, and the third electrode plate Cc is used as the first relay portion 41, i.e., the first relay portion 41 and the second electrode plate Cb are connected via the second via V2, simplifying the structure and manufacturing process of the display substrate 10.

[0100] For example, as shown in Fig. 4B, the second plate Cb and the first pole T1s of the driving transistor T1 are disposed on the same layer, for example, the second plate Cb and the first pole T1s of the driving transistor T1 are formed in a continuous, integral structure, thereby realizing an electrical connection between the second plate Cb and the first pole T1s of the driving transistor T1, thereby realizing an electrical connection between the first relay part 41 and the first pole T1s of the driving transistor T1. The third plate Cc is used as the first relay part 41, and the second plate Cb and the first pole T1s of the driving transistor T1 are formed in a continuous, integral structure, which greatly simplifies the structure and manufacturing process of the display substrate 10.

[0101] For example, as shown in FIG. 4B, the first pole T1s of the driving transistor T1 is connected to the active layer T1a of the driving transistor T1 through a plurality of vias to reduce the contact resistance. For example, the plurality of vias are arranged spaced apart from each other along the second direction D2. For example, the first pole T1s of the driving transistor T1 is connected to the active layer T1a of the driving transistor T1 through three vias, namely, via V91, via V92, and via V93, and the vias V91, V92, and V93 all penetrate the second insulating layer 102 and the third insulating layer 103. Of course, the number of the plurality of vias is not limited to three and can be designed according to demand.

[0102] FIG. 5A is a schematic plan view of the first conductive layer of the display unit shown in FIG. 3A; FIG. 5B is a schematic plan view of the first insulating layer of the display unit shown in FIG. 3A; FIG. 5C is a schematic plan view of the semiconductor layer of the display unit shown in FIG. 3A; FIG. 5D is a schematic plan view of the second conductive layer of the display unit shown in FIG. 3A; FIG. 5E is a schematic plan view of the third insulating layer of the display unit shown in FIG. 3A; FIG. 5F is a schematic plan view of the third conductive layer of the display unit shown in FIG. 3A; FIG. 5G is a schematic plan view of the fourth insulating layer of the display unit shown in FIG. 3A; FIG. 5H is a schematic plan view of the fifth insulating layer of the display unit shown in FIG. 3A; FIG. 5I is a schematic plan view of the fourth conductive layer of the display unit shown in FIG. 3A; and FIG. 5J is a schematic plan view of the fifth conductive layer of the display unit shown in FIG. 3A. As shown in Figures 5A-5I, combining Figure 4A, the display substrate 10 includes a first conductive layer 100, a first insulating layer 101, a semiconductor layer 600, a second insulating layer 102, a second conductive layer 200, a third insulating layer 103, a third conductive layer 300, a fourth insulating layer 104, a fifth insulating layer 105, a fourth conductive layer 400 and a fifth conductive layer 500, which are stacked on the base substrate 1 in order along a direction away from the base substrate 1, and the fifth insulating layer 105 is the above-mentioned interlayer insulating layer 105.

[0103] For example, materials for the semiconductor layer 600 include, but are not limited to, silicon-based materials (such as amorphous silicon a-Si and polycrystalline silicon p-Si), metal oxide semiconductors (such as IGZO, ZnO, AZO, IZTO), and organic materials (such as sexithiophene and polythiophene).

[0104] 4A and 5A-5J, the first conductive layer 100 includes a first relay portion 41, a second relay portion 42 and a third plate Cc, and the semiconductor layer 600 includes an active layer T1a of the driving transistor T1, an active layer T2a of the data transistor T2 and an active layer T3a of the detection transistor T3. The second conductive layer 200 includes the first sub-scanning signal line G1 and the second sub-scanning signal line G2, the gate T1g of the driving transistor T1, the gate T2g of the data transistor T2, and the gate T3g of the detection transistor T3, the first electrode plate Ca, the horizontal portion vdd2 of the first power line vdd, and the auxiliary power line vdd3, which extends along the second direction D2 corresponding to the vertical portion vdd1 of the first power line vdd, and is electrically connected to the vertical portion vdd1 of the first power line vdd through a plurality of vias V4 penetrating the third insulating layer 103, thereby being connected in parallel to the vertical portion vdd1 of the first power line vdd, thereby achieving the effect of reducing the resistance of the first power line vdd. Also, as shown in FIG. 5D, the auxiliary power line vdd3 is electrically connected to the horizontal portion vdd2, thereby realizing the electrical connection between the horizontal portion vdd2 and the vertical portion vdd1. For example, the auxiliary power line vdd3 and the horizontal portion vdd2 are disposed on the same layer, and both are located on the second conductive layer 200. For example, the auxiliary power line vdd3 and the horizontal portion vdd2 are a continuous integral structure. The third conductive layer 300 includes the first pole T1s and the second pole T1d of the driving transistor T1, the first pole T2s and the second pole T2d of the data transistor T2, the first pole T3s and the second pole T3d of the detection transistor T3, the data lines D1\D2\D3\D4, the detection signal line S, and the vertical portion vdd1 of the first power line vdd. As can be seen from FIG. 4A and FIG. 5H, the interlayer insulating layer 105 is disposed only in the display area 11, and there is no interlayer insulating layer 105 in the non-light-emitting area 12.

[0105] 4A and 5I, for example, the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 are connected to the first pole T1s of the driving transistor T1, and each include a first sub-electrode layer 2a, a second sub-electrode layer 2b, and a third sub-electrode layer 2c that are stacked in order along a direction perpendicular to the base substrate 1 and away from the base substrate 1. The fourth conductive layer 400 includes a connection portion 30, a first extension portion 31, a second extension portion 32, the first sub-electrode layer 2a of the first portion 21, and the first sub-electrode layer 2a of the second portion 22. The fifth conductive layer 500 includes the third sub-electrode layer 2c of the first portion 21 and the third sub-electrode layer 2c of the second portion 22. For example, the display substrate 10 further includes a sixth conductive layer, which is located between the fourth conductive layer 400 and the fifth conductive layer 500 in a direction perpendicular to the base substrate 1, and includes a second sub-electrode layer 2b of the first portion 21 and a second sub-electrode layer 2b of the second portion 22.

[0106] 4C is a schematic cross-sectional view taken along line D-D' in FIG. 3A. Combining FIG. 5A and FIG. 4C, the first conductive layer 100 further includes an intermediate connection portion 43 located in the boundary region between the first pixel row and the second pixel row. The second pole T3d of the detection transistor T3 is connected to the active layer T3a of the detection transistor T3 through an intermediate via V33 penetrating the third insulating layer 103, and is connected to the intermediate connection portion 43 through a second connection via V32 penetrating the third insulating layer 103 and the first insulating layer 101, and the detection signal line S is connected to the intermediate connection portion 43 through a first connection via V31 penetrating the third insulating layer 103 and the first insulating layer 101, thereby realizing the connection between the detection signal line S and the second pole T3d of the detection transistor T3. At the same time, the second pole T3d' of the detection transistor of the fourth subpixel P4 is connected to the active layer T3a' of the detection transistor of the fourth subpixel P4 through a via V35 that penetrates the third insulating layer 103, and is connected to the intermediate connection part 43 through a via V34 that penetrates the third insulating layer 103 and the first insulating layer 101, thereby realizing that the second pole T3d of the detection transistor of the third subpixel P3 and the second pole T3d' of the detection transistor of the fourth subpixel P4 are connected to the same detection signal line S through the same intermediate connection part 43, and simplifying the structure and manufacturing process of the display substrate 10.

[0107] For example, as shown in Figures 4C and 5C, the second pole T3d of the detection transistor T3 of the first subpixel P1 (i.e., the upper subpixel below) and the second pole T3d of the detection transistor T3 of the third subpixel P3 (i.e., the lower subpixel below) form a continuous integrally molded electrode, the active layer T3a of the detection transistor T3 of the first subpixel P1 and the active layer T3a of the detection transistor T3 of the third subpixel P3 integrally mold the active layer IAL, and the integrally molded electrode is electrically connected to the integrally molded active layer IAL through an intermediate via V33.

[0108] For example, as shown in FIG. 4A, the third electrode plate Cc is located on the side closer to the base substrate 1 than the first electrode plate Ca.

[0109] For example, combining FIG. 4A and FIG. 5A, the display substrate 10 further includes a light-shielding layer 7 located on the side of the semiconductor layer 200 close to the base substrate 1. The orthogonal projection of the active pattern (i.e., the active layer T1a or the channel region) of the driving transistor T1 onto the base substrate 1 is located within the orthogonal projection of the light-shielding layer 7 onto the base substrate 1, thereby using the light-shielding layer 7 to block the top light from the side of the active pattern of the driving transistor T1 away from the base substrate 1, and prevent the top light from irradiating the channel region of the driving transistor T1, thereby preventing the performance of the driving transistor T1 from being reduced by light illumination. For example, the light-emitting device 20 is a top-emission type, and the light emitted from the light-emitting layer 23 is emitted from the side of the light-emitting device 20 away from the base substrate 1; of course, the light-emitting device 20 may be a bottom-emission type, and the light emitted from the light-emitting layer 23 is emitted from the base substrate 1. For example, the light-shielding layer 7 is used as the first relay portion 41, that is, the two have the same structure, thereby simplifying the structure and manufacturing process of the display substrate 10.

[0110] At least one embodiment of the present disclosure further provides a method for operating a display substrate, which is applied to any one of the display substrates 10 according to the embodiments of the present disclosure. Referring to FIG. 3C , the method includes cutting a portion of the connection structure 3 of the display substrate 10 located in a non-light-emitting region, thereby isolating the connection structure 3 from one of the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2, where "isolating" means that the connection structure 3 is no longer electrically connected to one of the first portion 21 and the second portion 22, for example. B One of the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 is blocked from the connection portion 30 of the connection structure 3 located in the non-light-emitting region 12. In this way, for one subpixel, taking the third subpixel P3 as an example here, when a display defect such as a dark spot occurs in one of the region of the aperture region corresponding to the first portion 21 of the first electrode 2 and the region corresponding to the second portion 22 of the first electrode 2, for example, when a display defect such as a dark spot occurs in the region corresponding to the first portion 21 of the first electrode 2, it is possible to block the first portion 21 of the first electrode 2 and the connection structure 3, thereby preventing the region where the display defect such as a dark spot occurs from being displayed, thereby realizing the repair of the subpixel and improving the display quality.

[0111] For example, the side of the connection structure 3 close to the base substrate 1 does not have any conductive layer overlapping the part of the connection structure 3 to be cut in the direction perpendicular to the base substrate 1, for example, the side of the first cuttable portion 310 close to the base substrate 1 does not have any conductive layer overlapping the first cuttable portion 310 in the direction perpendicular to the base substrate 1, and the side of the second cuttable portion 320 close to the base substrate 1 does not have any conductive layer overlapping the second cuttable portion 320 in the direction perpendicular to the base substrate 1, and at this time, the operation method of the display substrate includes cutting one of both the first part 21 of the first electrode 2 and the second part 22 of the first electrode 2 and the connection portion 30 by cutting one of both the first cuttable portion 310 and the second cuttable portion 320. In this way, other conductive layers are not damaged in the process of cutting the first cuttable portion 310 or the second cuttable portion 320, thereby making it easy to cut, realizing repair of the subpixel, and improving the display quality. For example, a laser irradiation method can be adopted to cut the first cuttable portion 310 or the second cuttable portion 320 to form a notch (not shown), for example the notch dividing the first cuttable portion 310 or the second cuttable portion 320 into two parts spaced apart in the first direction D1, one connected to the first part of the first electrode or the second part of the first electrode, and the other connected to the connection portion 30.

[0112] At least one embodiment of the present disclosure further provides a display substrate including a base substrate, a display unit, a scanning signal line, and a vertical signal line. The display unit is disposed on the base substrate and includes a display region and a non-light-emitting region. The display region includes sub-pixels, each of which includes a driving transistor and a light-emitting device, the driving transistor being configured to control a magnitude of a driving current flowing through the light-emitting device, and the light-emitting device being configured to receive the driving current and be driven by the driving current to emit light. The scanning signal line is disposed on the base substrate, generally extends along a first direction, passes through the non-light-emitting region and the display region, and transmits a scanning signal. The vertical signal line is disposed on the base substrate and located in the display region, generally extends along a second direction intersecting the first direction. The scanning signal line includes at least one outer ring portion, each of the at least one outer ring portion includes a first conductive line and a second conductive line. The first conductive line generally extends along the first direction and extends from the non-light-emitting region to the display region. The second conductive wire extends generally along the first direction, extends from the non-light-emitting region to the display region, and is spaced apart from the first conductive wire in the second direction. The first conductive wire and the second conductive wire both overlap with the vertical signal wire in a direction perpendicular to the base substrate, the scanning signal line includes a body portion extending generally along the first direction, and the first conductive wire and the second conductive wire are both electrically connected to the body portion. In the display substrate, the first conductive wire and the second conductive wire transmit the same scanning signal, and the first conductive wire and the second conductive wire of at least one outer ring portion extend from the non-light-emitting region to the display region and overlap with the vertical signal wire. This allows the at least one outer ring portion to effectively reduce the load (or resistance) of the scanning signal line and avoid excessive overlap with the vertical signal line.In addition, the first and second conductive wires of at least one outer ring portion extend from the non-light-emitting region to the display region, and thereby can overlap with the vertical signal line located at the edge of the display region close to the non-light-emitting region in a direction perpendicular to the base substrate. Thus, when a problem such as a short circuit occurs at the point where the vertical signal line overlaps with one of the first and second conductive wires of the same outer ring portion, the short-circuited one of the first and second conductive wires can be cut off to stop it from operating, thereby avoiding any impact on the display effect of the display unit where it is located, and realizing pixel repair of the display unit.

[0113] Exemplarily, for example, FIG. 6A is an enlarged schematic diagram of a portion A including at least one outer ring portion in FIG. 3A. Combining FIG. 3A, FIG. 6A, and FIG. 5D, the display substrate 10 includes vertical signal lines, which are disposed on the base substrate 1 and located in the display area 11, and generally extend along a second direction D2 intersecting the first direction D1. For example, the vertical signal lines include the above-mentioned first power line vdd, second power line vss, data lines D1 to D4, detection lines S, connection lines (described below), etc. In the embodiment shown in FIG. 3A and FIG. 6A, the first sub-scanning signal line G1 generally extending along the first direction D1 transmits a first scanning signal and includes a first outer ring portion R1. The at least one outer ring portion includes a first outer ring portion R1, the first outer ring portion R1 including a first conductive wire R11 and a second conductive wire R12, the first conductive wire R11 of the first outer ring portion R1 generally extending along a first direction D1, extending from the non-light-emitting region 12A to the display region 11. The second conductive wire R12 of the first outer ring portion R1 generally extending along the first direction D1, extending from the non-light-emitting region 12A to the display region 11, and separated from the first conductive wire R11 of the first outer ring portion R1 in a second direction D2. The first sub-scanning signal line G1 includes a first body portion G10 extending generally along the first direction D1, and the first conductor R11 of the first outer ring portion R1 and the second conductor R12 of the first outer ring portion R1 are both connected to the first body portion G10, whereby the first conductor R11 of the first outer ring portion R1, the second conductor R12 of the first outer ring portion R1 and the first body portion G10 all transmit the first scanning signal.

[0114] As described above, the display substrate 10 includes a first power supply line vdd, which is connected to a first voltage terminal and configured to provide a first power supply voltage to the sub-pixel, and includes a vertical portion vdd1 extending generally along the second direction D2. As shown in FIG. 6A, the vertical signal line includes a vertical portion vdd1 of the first power supply line vdd. The first conductive line R11 of the first outer ring portion R1 and the second conductive line R12 of the first outer ring portion R1 both overlap with the vertical portion vdd1 of the first power supply line vdd in a direction perpendicular to the base substrate 1. In this way, the first conductive line R11 of the first outer ring portion R1 and the second conductive line R12 of the first outer ring portion R1 extend from the non-light-emitting region 12A to the display region 11, and thereby can overlap with a vertical signal line, such as the first power supply line vdd, located at an edge of the display region 11 close to the non-light-emitting region 12A in a direction perpendicular to the base substrate 1. Thus, the first outer ring portion R1 can effectively reduce the load (or resistance) of the first sub-scanning signal line G1, and can avoid overlapping with the vertical portion vdd1 too much, and overlaps at only two points. If a problem such as a short circuit occurs at the overlapping point between the vertical portion vdd1 and one of the first conducting wire R11 of the first outer ring portion R1 and the second conducting wire R12 of the first outer ring portion R1, the shorted one of the first conducting wire R11 of the first outer ring portion R1 and the second conducting wire R12 of the first outer ring portion R1 can be cut, for example, at the position of the first side or the second side opposite to each other in the first direction D1 of the vertical portion vdd1, the shorted one of the first conducting wire R11 of the first outer ring portion R1 and the second conducting wire R12 of the first outer ring portion R1 can be cut, and the cut conducting wire can be stopped, avoiding the influence on the display effect of the display unit P where it is located, and realizing the pixel repair of the display unit P. The uncut one of the first conductive wire R11 of the first outer ring portion R1 and the second conductive wire R12 of the first outer ring portion R1 continues to provide the first scanning signal to the multiple sub-pixels P1 to P4 of the display unit P, thereby maintaining the normal operation of the multiple sub-pixels P1 to P4 of the display unit P, and reducing the impact of the above-mentioned short-circuit problem on the display effect.

[0115] For example, the vertical signal line is a data signal line that transmits the data signal DT. LineThe first sub-scanning signal line G1 is configured to provide a first scanning signal to the data writing transistor T2, for example, the first sub-scanning signal line G1 provides a first scanning signal to a plurality of sub-pixels P1 to P4 of the display unit P. For example, in the embodiment shown in FIG. 6A, the first conductive wire R11 of the first outer ring portion R1 and the second conductive wire R12 of the first outer ring portion R1 overlap with the first data signal line D1 in a direction perpendicular to the base substrate 1. Of course, in other embodiments, the first conductive wire R11 of the first outer ring portion R1 and the second conductive wire R12 of the first outer ring portion R1 may overlap with the second data signal line D2 in a direction perpendicular to the base substrate 1, or may overlap with the third data signal line D3 in a direction perpendicular to the base substrate 1, or may overlap with the fourth data signal line D4 in a direction perpendicular to the base substrate 1. For example, in other embodiments, the first conductive wire R11 of the first outer ring portion R1 and the second conductive wire R12 of the first outer ring portion R1 may overlap with multiple data signal lines of the display unit P, which can be designed according to needs.

[0116] For example, the non-light-emitting region of the display unit P includes a first non-light-emitting region 12A and a second non-light-emitting region 12B, where the first non-light-emitting region 12A is located on a first side in the first direction D1 of the display region 11, and the second non-light-emitting region 12B is located on a second side opposite to the first side in the first direction D1 of the display region 11. The first sub-scanning signal line G1 passes through the first non-light-emitting region 12A, the display region 11, and the second non-light-emitting region 12B in order. The first body portion G10 includes a first portion G101 located in the first non-light-emitting region 12A and a second portion G102 located in the second non-light-emitting region 12B. The first sub-scanning signal line G1 further includes a first branch portion and a second branch portion. The first branch portion is connected to the first portion G101 of the first body portion G10 and the second portion G102 of the first body portion G10, and includes a first conductive wire R11 of the first outer ring portion R1. The first conducting wire R11 of the first outer ring portion R1 is located on a first side in the second direction D2 of the first body portion G10, and the first conducting wire R11 of the first outer ring portion R1 is electrically connected to the first body portion G10. The second branch portion is connected to the first part G101 of the first body portion G10 and the second part G102 of the first body portion G10, and includes a second conducting wire R12 of the first outer ring portion R1, and the second conducting wire R12 of the first outer ring portion R1 is located on a second side opposite to the first side of the first body portion G10 in the second direction D2, and the second conducting wire R12 of the first outer ring portion R1 and the first body portion G10 make rational use of space to correspond to the first pixel row and the second pixel row arranged along the second direction D2.

[0117] For example, as shown in FIG. 6A and FIG. 5D, the first sub-scanning signal line G1 further includes a second outer ring portion R2, and the at least one outer ring portion includes the second outer ring portion R2. The first conductive wire R21 of the second outer ring portion R2 and the second conductive wire R22 of the second outer ring portion R1 are both connected to the first body portion G10. The vertical signal line includes a second power supply line vss, which is connected to a second voltage terminal and configured to provide a second power supply voltage different from the first power supply voltage to the subpixel, and extends along the second direction D2. The first conductive wire R21 of the second outer ring portion R2 and the second conductive wire R22 of the second outer ring portion R2 overlap with the second power supply line vss in a direction perpendicular to the base substrate 1. In this way, the second outer ring portion R2 can reduce the load (or resistance) of the first sub-scanning signal line G1 and avoid excessive overlap with the second power line vss, and overlaps only two places. If a problem such as a short circuit occurs at the overlapping portion between the vertical portion vdd1 and one of the first conducting wire R21 of the second outer ring portion R2 and the second conducting wire R22 of the second outer ring portion R2, the shorted one of the first conducting wire R21 of the second outer ring portion R2 and the second conducting wire R22 of the second outer ring portion R2 can be cut, for example, at the position of the first side or the second side facing the second power line vss in the first direction D1, the shorted one of the first conducting wire R21 of the second outer ring portion R2 and the second conducting wire R22 of the second outer ring portion R2 can be cut, and the cut conducting wire can be stopped, avoiding the influence on the display effect of the display unit P where it is located, and realizing the pixel repair of the display unit P. The uncut one of the first conductive wire R21 of the second outer ring portion R2 and the second conductive wire R22 of the second outer ring portion R2 continues to provide the first scanning signal to the multiple sub-pixels P1 to P4 of the display unit P, thereby maintaining the normal operation of the multiple sub-pixels P1 to P4 of the display unit P, and reducing the impact of the above-mentioned short-circuit problem on the display effect.

[0118] For example, the first power supply voltage is, for example, a high power supply voltage VDD, and the second power supply voltage is, for example, a low power supply voltage VSS.

[0119] For example, as shown in Figures 6A and 5D, the second outer ring portion R2 and the first outer ring portion R1 are spaced apart from each other in the first direction D1, and in the embodiment of the present disclosure, the signal lines between the second outer ring portion R2 and the first outer ring portion R1 are densely packed, thus avoiding problems such as frequent short circuits and reduced production yields due to excessive overlap between the second outer ring portion R2 and the first outer ring portion R1 and the signal lines extending along the second direction D2. Of course, according to different layout structures, the lengths of the second outer ring portion R2 and the first outer ring portion R1 in the first direction D1 can be designed according to needs to determine which signal lines extending along the second reverse direction D2 the second outer ring portion R2 and the first outer ring portion R1 overlap with in the direction perpendicular to the base substrate 1, and the embodiment of the present disclosure is not limited thereto.

[0120] 6A and 5D, the first conducting wire R11 of the first outer ring portion R1 and the second conducting wire R12 of the first outer ring portion R1 extend from the first non-light-emitting region 12A to the display region 11, and the first conducting wire R21 of the second outer ring portion R2 and the second conducting wire R22 of the second outer ring portion R2 extend from the second non-light-emitting region 12B to the display region 11. The first sub-scanning signal line G1 further includes an intermediate connection portion G103. The first outer ring portion R1 and the second outer ring portion R2 are both closed rings, and the first part G101 of the first main body portion G10, the first outer ring portion R1, the intermediate connecting portion G103, the second outer ring portion R2 and the second part G102 of the first main body portion G10 are connected in sequence, thereby realizing that the first part G101 of the first main body portion G10, the first outer ring portion R1, the intermediate connecting portion G103, the second outer ring portion R2 and the second part of the first main body portion G10 transmit a first scanning signal along the first direction D1.

[0121] For example, as shown in Figures 6A and 5D, the first outer ring portion R1 and the second outer ring portion R2 are symmetrical with respect to an axis of symmetry extending along the second direction D2, so that the display unit P and the pixel array are more uniform, and the display effect of the entire display area is uniform.

[0122] For example, in order to simplify the structure and manufacturing process of the display substrate 10, the first part of the first main body portion G10, the first outer ring portion R1, the intermediate connecting portion G103, the second outer ring portion R2 and the second part of the first main body portion G10 are a continuous integrally molded structure (i.e., an integrated structure).

[0123] For example, as shown in Fig. 6A and Fig. 5D, the first conductive wire R11 of the first outer ring portion R1 has a first end and a second end facing each other in the first direction D1, the second conductive wire R12 of the first outer ring portion R1 has a first end and a second end facing each other in the first direction D1, and the first outer ring portion R2 further includes a third connecting line R13 and a fourth connecting line R14. The third connecting line R13 is located in the first non-light-emitting area 12A, extends along the second direction D2, and is connected to a first end of the first conductive wire R11 and a first end of the second conductive wire R12, and the fourth connecting line R14 is located in the display area 11, extends along the second direction D2, and is connected to a second end of the conductive wire R11 and a second end of the second conductive wire R12, so that the first outer ring portion R1 forms a closed ring. The same is true for the second outer ring portion R2.

[0124] For example, the vertical portion vdd1 of the first power supply line vdd is located at a first edge in the first direction D1 of the display area 11, and the second power supply line vss is located at a second edge opposite to the first edge in the first direction D1 of the display area 11. As a result, the first conducting wire R11 and the second conducting wire R12 of the first outer ring portion R1 extend from the first non-light-emitting area 12A to the display area 11 so as to overlap with the vertical portion vdd1 of the first power supply line vdd, and the first conducting wire R21 and the second conducting wire R22 of the second outer ring portion R2 extend from the second non-light-emitting area 12B to the display area 11 so as to overlap with the second power supply line vss.

[0125] For example, as shown in FIG. 6A and FIG. 5D, as described above, the scanning signal line further includes a second sub-scanning signal line G2, which generally extends along the first direction D1, is spaced apart from the first sub-scanning signal line G1 in the second direction D2, and transmits a second scanning signal different from the first scanning signal. The second sub-scanning signal line G2 includes a third outer ring portion R3, and the at least one outer ring portion includes the third outer ring portion R3. The second sub-scanning signal line G2 includes a second body portion G20 generally extending along the first direction D1. , No. The first conductor R31 of the second conductor 3 of the third outer ring portion R3 and the second conductor R32 of the third outer ring portion R3 are both connected to the second body portion G20. The first conductor R31 of the third outer ring portion R3 and the second conductor R32 of the third outer ring portion R3 overlap with the vertical portion vdd1 of the first power line vdd and the second power line vss in a direction perpendicular to the base substrate 1. This allows the third outer ring portion R3 to effectively reduce the load (or resistance) of the second sub-scanning signal line G2 and to avoid excessive overlap with the vertical portion vdd1 and the second power line vss, and the third outer ring portion R3 overlaps with each of the vertical portion vdd1 and the second power line vss at only two points. If a problem such as a short circuit occurs at a point where the vertical portion vdd1 or the second power line vss overlaps with one of the first conductor R31 of the third outer ring portion R3 and the second conductor R32 of the third outer ring portion R3, the shorted one of the first conductor R31 of the third outer ring portion R3 and the second conductor R32 of the third outer ring portion R3 can be cut, for example, at a position on the opposing first or second side in the first direction D1 of the vertical portion vdd1 or the second power line vss, the shorted one of the first conductor R31 of the third outer ring portion R3 and the second conductor R32 of the third outer ring portion R3 can be cut, and the cut conductor can be stopped from operating, avoiding any influence on the display effect of the display unit P where it is located, and realizing pixel repair of the display unit P. The uncut one of the first conductive wire R31 of the third outer ring portion R3 and the second conductive wire R32 of the third outer ring portion R3 continues to provide the first scanning signal to the multiple sub-pixels P1 to P4 of the display unit P, thereby maintaining the normal operation of the multiple sub-pixels P1 to P4 of the display unit P, and reducing the impact of the above-mentioned short-circuit problem on the display effect.

[0126] 6A, when a short circuit occurs at a position PA where the third data signal line D3 and the first conductive wire R31 of the third outer ring portion R3 overlap, the first conductive wire R31 of the third outer ring portion R3 can be cut at a position PA1 on the first side of the third data signal line D3 in the first direction D1, or the first conductive wire R31 of the third outer ring portion R3 can be cut at a position PA2 on the second side of the third data signal line D3 in the first direction D1, so that the first conductive wire R31 of the third outer ring portion R3 does not transmit current, thereby eliminating the short circuit at the position PA, and the uncut second conductive wire R32 of the third outer ring portion R3 provides the second scanning signal to the sub-pixel of the display unit P. The repair method of each vertical signal line is similar to the above and will not be described one by one.

[0127] For example, as shown in Figures 6A and 5D, the first conductive wire R31 of the third outer ring portion R3 and the second conductive wire R32 of the third outer ring portion R3 respectively extend from the first non-light-emitting region 12A to the display region 11 and then to the second non-light-emitting region 12B. That is, the first conductive wire R31 of the third outer ring portion R3 and the second conductive wire R32 of the third outer ring portion R3 sequentially penetrate the first non-light-emitting region 12A, the display region 11 and the second non-light-emitting region 12B and penetrate the entire display region 11 along the first direction D1, thereby overlapping all vertical signal lines in the display region 11 that generally extend along the second direction D2 in the direction perpendicular to the base substrate 1, and solving the pixel repair when the above-mentioned short circuit occurs for all vertical signal lines.

[0128] For example, the second body portion G20 includes a first portion located in the first non-light emitting region 12A and a second portion located in the second non-light emitting region 12B, and the second sub-scanning signal line G2 includes a third branch portion and a fourth branch portion. The third branch portion is connected to the first portion of the second body portion G20 and the second portion of the second body portion G20, and includes a first conductive wire R31 of the third outer ring portion R3. The first conductive wire R31 of the third outer ring portion R3 is located on the first side in the second direction D2 of the second body portion G20, and the first conductive wire R31 of the third outer ring portion R3 is electrically connected to the second body portion G20. The fourth branch portion is connected to the first portion of the second body portion G20 and the second portion of the second body portion G20, and includes a second conductive wire R32 of the third outer ring portion R3. The second conductive wire R32 of the third outer ring portion R3 is located on a second side opposite to the first side of the second body portion G20 in the second direction D2, and the second conductive wire R32 of the third outer ring portion R3 is electrically connected to the second body portion G20, so as to rationally utilize the space corresponding to the first pixel row and the second pixel row arranged along the second direction D2, and to facilitate providing the second scanning signal to the first pixel row and the second pixel row using the second sub-scanning signal line G2.

[0129] 6A, the first conducting wire R31 of the third outer ring portion R3 and the second conducting wire R32 of the third outer ring portion R3 overlap with the data signal lines in a direction perpendicular to the base substrate 1, overlap with the vertical portion vdd1 of the first power supply line vdd in a direction perpendicular to the base substrate 1, and overlap with the second power supply line vss in a direction perpendicular to the base substrate 1. For example, the data signal lines include a first data line D1 providing a data signal to the first sub-pixel P1, a second data line D2 providing a data signal DT to the second sub-pixel P2, a third data line D3 providing a data signal DT to the third sub-pixel P3, and a fourth data line D4 providing a data signal DT to the fourth sub-pixel P4, and the first data line D1, the second data line D2, the third data line D3, and the fourth data line D4 are arranged at a distance from each other in the first direction D1. For example, the first conductive wire R31 of the third outer ring portion R3 and the second conductive wire R32 of the third outer ring portion R3 are both data signal lines D1 to D4 of the sub-pixels P1 to P4 of the display unit P. Overlaps withThis can solve the pixel repair problem when the above-mentioned short circuit occurs in any of the data signal lines D1 to D4, the vertical portion vdd1 of the first power line vdd, and the second power line vss.

[0130] For example, the vertical signal line further includes a detection signal line S for transmitting a detection signal. The subpixel further includes a detection transistor T3, and the second sub-scanning signal line G2 is configured to provide a second scanning signal to the detection transistor T3, and the detection transistor T3 is configured to realize external compensation by utilizing the electrical characteristics of the detection signal detection subpixel under the control of the second scanning signal. For example, as shown in FIG. 6A, the first conducting wire R31 of the third outer ring portion R3 and the second conducting wire R32 of the third outer ring portion R3 both overlap with the detection signal line S in a direction perpendicular to the base substrate 1. This can also solve the pixel repair when the above-mentioned short circuit occurs for the detection signal line S.

[0131] For example, the first sub-scanning signal line G1 is configured to provide a first scan signal to the data transistor T2 of the third sub-pixel P3 and the data transistor T2 of the fourth sub-pixel P4, the first conductive wire R31 of the third outer ring portion R3 is configured to provide a second scan signal to the detection transistor T3 of the first sub-pixel P1 and the detection transistor T3 of the second sub-pixel P2, and the second conductive wire R32 of the third outer ring portion R3 is configured to provide a second scan signal to the detection transistor T3 of the third sub-pixel P3 and the detection transistor T3 of the fourth sub-pixel P4. The first conductive wire R31 of the third outer ring portion R3 and the second conductive wire R3 of the third outer ring portion R3 all overlap with the first data line D1, the second data line D2, the third data line D3, and the fourth data line D4 in a direction perpendicular to the base substrate 1.

[0132] For example, as shown in FIG. 6A , the portions of the first conducting wire R31 of the third outer ring portion R3 that overlap with the channel regions of the detection transistors T3 of the third sub-pixel P3 and the fourth sub-pixel P4 respectively form the gate T3g-3 of the detection transistor T3 of the third sub-pixel P3 and the gate T3g-4 of the detection transistor T3 of the fourth sub-pixel P4, and the portions of the second conducting wire R32 of the third outer ring portion R3 that overlap with the channel regions of the detection transistors T3 of the first sub-pixel P1 and the second sub-pixel P2 respectively form the gate T3g-1 of the detection transistor T3 of the first sub-pixel P1 and the gate T3g-2 of the detection transistor T3 of the second sub-pixel P2.

[0133] 5D, the first sub-scanning signal line G1 and the second sub-scanning signal line G2 are located in the same layer, for example, the second conductive layer 200. Therefore, the outer ring portions, for example, the first outer ring portion R1, the second outer ring portion R2, and the third outer ring portion R3 are all located in the same conductive layer, for example, the second conductive layer 200.

[0134] 6A and 5D, the annular area of ​​the third outer ring portion R3 is larger than that of the first outer ring portion R1 and is larger than that of the second outer ring portion R2. For example, the length of the third outer ring portion R3 in the first direction D1 is larger than that of the second outer ring portion R2 in the first direction D1 and is larger than that of the first outer ring portion R1 in the first direction D1, and the width of the third outer ring portion R3 in the second direction D2 is larger than that of the second outer ring portion R2 in the second direction D2 and is larger than that of the first outer ring portion R1 in the second direction D2. The third outer ring portion R3 extends along the first direction D1 from a non-display area 12A located on a first side of the display area 11 of one display unit to enter the display area 11, and penetrates the display area 11 along the first direction D1 to enter a non-display area 12B located on a second side of the display area 11, and the first outer ring portion R1 and the second outer ring portion R2 do not span the entire display area 11 along the first direction D1.

[0135] For example, as shown in FIG. 6A, a portion of the intermediate connection portion G103 of the first sub-scanning signal line G1 that overlaps with the channel region of the data transistor of the third sub-pixel P3 constitutes the gate T2g-3 of the data transistor T2 of the third sub-pixel P3, and a portion of the intermediate connection portion G103 that overlaps with the channel region of the data transistor of the fourth sub-pixel P4 constitutes the gate T2g-4 of the data transistor T2 of the fourth sub-pixel P4.

[0136] For example, Figure 6A , Figure 5D 5F, the display unit P further includes an auxiliary scanning line G3, a first connecting line CL1, and a second connecting line CL2, and the auxiliary scanning line G3 extends along a first direction D1. The first connecting line CL1 is connected to the auxiliary scanning line G3 and the first sub-scanning signal line G1. The second connecting line CL2 and the first connecting line CL1 are spaced apart in the second direction D2 and connected to the auxiliary scanning line G3 and the first sub-scanning signal line G1. The auxiliary scanning line G3 is configured to provide a first scanning signal to the data transistor T2 of the first sub-pixel P1 and the data transistor T2 of the second sub-pixel P2, and the first conducting wire R31 of the third outer ring portion R3 and the second conducting wire R32 of the third outer ring portion R3 overlap with the first connecting line CL1 and the second connecting line CL2 in a direction perpendicular to the base substrate 1. This can solve the pixel repair when the short circuit occurs in both the first connecting line CL1 and the second connecting line CL2.

[0137] 5D, the first sub-scanning signal line G1 and the auxiliary scanning line G3 are disposed in the same layer, and in the same layer as the first pole of the driving transistor, and are both located in the second conductive layer 200. The first connecting line CL1 and the second connecting line CL2 are located in the third conductive layer 300, and are disposed in a different layer from the first sub-scanning signal line G1.

[0138] For example, as shown in FIG. 5F, the auxiliary scanning line G3 has a first end and a second end facing each other in the first direction D1, the first connecting line CL1 is connected to the first end of the auxiliary scanning line G3 and the first outer ring portion R1, and the second connecting line CL2 is connected to the second end of the auxiliary scanning line G3 and the second outer ring portion R2.

[0139] 5E-5F and 6A, a first end of the auxiliary scanning line G3 is connected to a first end of the first connection line CL1 through a via V71 penetrating the third insulating layer 103, a second end of the first connection line CL1 is connected to a first sub-scanning signal line G1 through a via V61 penetrating the third insulating layer 103, a second end of the auxiliary scanning line G3 is connected to a first end of the second connection line CL2 through a via V72 penetrating the third insulating layer 103, and a second end of the second connection line CL2 is connected to the first sub-scanning signal line G1 through a via V62 penetrating the third insulating layer 103. For example, a second end of the first connection line CL1 is connected to the second outer ring portion R2 through the via V61, and a second end of the second connection line CL2 is connected to the second outer ring portion R2 through the via V62.

[0140] For example, the number of outer ring parts included in the second sub-scanning signal line G2 is smaller than the number of outer ring parts included in the first sub-scanning signal line G. For example, the number of outer ring parts included in the second sub-scanning signal line G2 is 1, that is, the number of third outer ring parts R3 is 1, and the number of outer ring parts included in the first sub-scanning signal line G1 is 2, which are one first outer ring part R1 and one second outer ring part R2 respectively. For most of the outer ring parts included in the first sub-scanning signal line G1, it is easy to install the outer ring parts at multiple positions, and flexibly meet the demand for multiple positions, for example, each of the two positions of one display unit is connected to the first end and the second end of the auxiliary scanning line G3. At the same time, the second sub-scanning signal line G2 only needs to include a small outer ring portion to satisfy the overlap with multiple types of vertical signal lines, thereby avoiding the need to install multiple outer ring portions, and simplifying the structure and reducing the difficulty of manufacturing the display substrate, which is very important for increasing the manufacturing yield of the display substrate, especially for a display substrate having such a complex structure and high separation rate.

[0141] For example, FIG. 6B is an enlarged schematic diagram of part B in FIG. 3A, which includes at least one inner ring. Combining FIG. 5D and FIG. 6B, the horizontal portion vdd2 of the first power line vdd includes an inner ring R4, which includes a third conductor R41 and a fourth conductor R42. The third conductor R41 generally extends along the first direction D1 and is located in the display area 11. The fourth conductor R42 generally extends along the first direction D1 and is located in the display area 11, and is spaced apart from the third conductor R41 in the second direction D2. The third conductor R41 and the fourth conductor R42 both overlap at least some of the vertical signal lines in a direction perpendicular to the base substrate 1, and provide the same first power supply voltage to a plurality of sub-pixels of the display unit P.

[0142] For example, the horizontal portion vdd2 of the first power supply line vdd, the first sub-scanning signal line G1, and the second sub-scanning signal line G2 are arranged in the same layer, arranged in a different layer from the vertical portion vdd1 of the first power supply line vdd, and are electrically connected to the vertical portion vdd1 through a via (as specifically described above).

[0143] 6B, the third conducting wire R41 and the fourth conducting wire R42 both overlap with at least some of the data signal lines of the display unit P in the direction perpendicular to the base substrate 1, for example, the third conducting wire R41 and the fourth conducting wire R42 both overlap with the third data signal line D3 and the fourth data signal line D4 in the direction perpendicular to the base substrate 1. As a result, when a short circuit occurs at the position where the third data signal line D3 and the fourth data signal line D4 overlap with the third conducting wire R41 or the fourth conducting wire R42, pixel repair can be achieved in both cases. 6B , when a short circuit occurs at a position PO where the fourth data signal line D4 overlaps with the third conducting wire R41, the third conducting wire R41 is cut at a position p1 on the first side of the fourth data signal line D4 in the first direction D1, or the third conducting wire R41 is cut at a position p2 on the second side of the fourth data signal line D4 in the first direction D1, so that the third conducting wire R41 does not transmit current, thereby eliminating the short circuit at the position PO, and the uncut fourth conducting wire R42 provides the second power supply voltage to the sub-pixel of the display unit P. The repair method for each vertical signal line is similar to the above, and will not be described one by one.

[0144] Of course, in other embodiments, the third conducting wire R41 and the fourth conducting wire R42 may overlap all the data signal lines D1 to D4 of the display unit P in the direction perpendicular to the base substrate 1. In this way, when a short circuit occurs at the position where the data signal lines D1 to D4 overlap with the third conducting wire R41 and the fourth conducting wire R42, pixel repair can be achieved in either case.

[0145] For example, as shown in Fig. 6B, the third conducting wire R41 and the fourth conducting wire R42 both overlap with the detection signal line S in a direction perpendicular to the base substrate 1. This can solve the pixel repair when the above-mentioned short circuit occurs in both the third data signal line D3 and the fourth data signal line D4.

[0146] For example, the detection signal line S is sandwiched between the third data line D3 and the fourth data line D4 and adjacent to the third data line D3 and the fourth data line D4, and the third conducting wire R41 and the fourth conducting wire R42 all overlap with the third data line D3, the fourth data line D4, and the detection signal line S in a direction perpendicular to the base substrate 1. In this way, one ring structure which is the inner ring portion R4 overlaps with a plurality of vertical signal lines at a position where the vertical signal lines are densely arranged, thereby solving the pixel repair when the above-mentioned short circuit occurs in the third data signal line D3, the fourth data signal line D4, and the detection signal line S.

[0147] Figure 5K is a schematic plan view of the pixel defining layer of the display unit shown in Figure 3A. For example, the pixel defining layer 6 exposes at least a portion of the outer ring portion. Combining Figures 3A, 5K and 6A, for example, the pixel defining layer 6 exposes a portion of the first outer ring portion R1 and a portion of the second outer ring portion R2.

[0148] 3A, 3C, 5K, and 6A, the pixel definition layer 6 includes a portion located in the non-display area 12A, and the portion of the pixel definition layer 6 located in the non-display area 12A has a groove 63 recessed in a direction away from the display area, and at least a part of the orthogonal projection of the connection portion 30 onto the base substrate 1 is located within the orthogonal projection of the groove 63 onto the base substrate 1. The groove 63 is In the first direction D1 The connection portion 30 has an edge 631 facing the connection portion 30, and there is a gap between the edge 301 of the connection portion 30 that is away from the display area 11 in the first direction D1 and the edge 631 of the groove 63. That is, the edge 631 of the groove 63 is located on the side of the edge 301 of the connection portion 30 that is away from the display area 11.

[0149] At least one embodiment of the present disclosure further provides a method for operating a display substrate, which is applied to any one of the display substrates 10 according to the embodiments of the present disclosure, and the method for operating the display substrate 1 includes cutting a portion of one of the first and second conductive wires of a same outer ring portion, which is located in the display area 11. The same outer ring portion may be, for example, the first outer ring portion R1, the second outer ring portion R2, and the third outer ring portion R3.

[0150] For example, there is no conductive layer that overlaps with one of the first and second conductive wires of the same outer ring portion in a direction perpendicular to the base substrate 1 on the side of the cut portion of one of the first and second conductive wires of the same outer ring portion. For example, as described above, a short circuit occurs at the position PA where the third data signal line D3 in FIG. 6A overlaps with the first conductive wire R31 of the third outer ring portion R3, and the first conductive wire R31 of the third outer ring portion R3 can be cut at the position PA1 or position PA2 in FIG. 6A. In this way, when a display defect such as the above-mentioned short circuit occurs in a subpixel, the other conductive layer is not damaged in the process of cutting one of the first and second conductive wires of the same outer ring portion, and thus the cutting is easy, the subpixel is repaired, and the display quality is improved. The processing method for repairing the subpixel for other outer ring portions or inner ring portions is similar to this, so it will not be described one by one.

[0151] For example, a laser irradiation method can be used to cut one of the first conductive wire and the second conductive wire of the same outer ring portion to form a notch (not shown).

[0152] At least one embodiment of the present disclosure further provides a display substrate including a base substrate and a display unit, the display unit being disposed on the base substrate and including a display region and a non-light-emitting region, the display region including a sub-pixel, the sub-pixel including a driving transistor and a light-emitting device, the driving transistor being configured to control a magnitude of a driving current flowing through the light-emitting device, the sub-pixel including a gate, a first pole and a second pole, the light-emitting device being configured to receive the driving current and be driven by the driving current to emit light, the sub-pixel including a first electrode, the first electrode including a first portion and a second portion spaced apart from each other, the first portion and the second portion being connected to a first pole of the driving transistor, and a front electrode including a first electrode and a second electrode; The electrode assembly includes a first sub-electrode layer and a second sub-electrode layer stacked in sequence along a direction perpendicular to the base substrate from a direction closer to the base substrate to a direction away from the base substrate, wherein the first sub-electrode layer of the first portion has a first edge close to the second portion, and the second sub-electrode layer of the first portion has a second edge close to the second portion, the first edge being located on the side of the second edge away from the second portion, the first sub-electrode layer of the second portion has a third edge close to the first portion, and the second sub-electrode layer of the second portion has a fourth edge close to the first portion, and the third edge being located on the side of the fourth edge away from the first portion.

[0153] Illustratively, Fig. 7 is another cross-sectional schematic diagram along the line A-A' in Fig. 3B, Fig. 8A is an enlarged schematic diagram of part C in Fig. 7, and Fig. 9 is a plan schematic diagram of part C shown in Fig. 8A. As shown in Figs. 7-9, in the display substrate 10, the first electrode 2 includes a first portion 21 and a second portion 22 that are spaced apart from each other, and the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 are connected to the first pole T1s of the driving transistor T1 (see the description of Fig. 4A for a specific connection manner), and each of the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 includes a first sub-electrode layer 2a and a second sub-electrode layer 2b that are stacked in order along a direction perpendicular to the base substrate 1 from a direction close to the base substrate 1 to a direction away from the base substrate 1. The first sub-electrode layer 2a of the first portion 21 of the first electrode 2 has a first edge 2a-1 close to the second portion 22 of the first electrode 2, and the second sub-electrode layer 2b of the first portion 21 of the first electrode 2 has a second edge 2b-1 close to the second portion 22 of the first electrode 2, the first edge 2a-1 being located on the side of the second edge 2b-1 away from the second portion 22 of the first electrode 2, the first sub-electrode layer 2a of the second portion 22 of the first electrode 2 has a third edge 2a-2 close to the first portion 21 of the first electrode 2, and the second sub-electrode layer 2b of the second portion 22 of the first electrode 2 has a fourth edge 2b-2 close to the first portion 21 of the first electrode 2, and the third edge 2a-2 is located on the side of the fourth edge 2b-2 away from the first portion 21 of the first electrode 2. That is, in the display substrate, the mutually close edges of the first sub-electrode layer 2a of the first portion 21 and the first sub-electrode layer 2a of the second portion 22 of the first electrode 2 (e.g., an anode) are each shrunk relative to the mutually close edges of the second sub-electrode layer of the first portion 21 and the second sub-electrode layer of the first portion 22.In this way, after forming the first sub-electrode layer 2a of the first portion 21 and the first sub-electrode layer 2a of the second portion 22, when the second sub-electrode layer 2b of the first portion 21 and the second sub-electrode layer 2b of the second portion 22 are formed by a patterning process, contact between the second sub-electrode layer 2b of the first portion 21 and the second sub-electrode layer 2b of the second portion 22 due to a gap that is too small can be prevented, contact between the second sub-electrode layer 2b of the first portion 21 and the first sub-electrode layer 2a of the second portion 22, and contact between the second sub-electrode layer 2b of the second portion 22 and the first sub-electrode layer 2a of the first portion 21 can be prevented, and the difficulty of patterning can be reduced and the production yield of the display substrate can be increased. If the design regarding the edges of the first portion 21 and the second portion 22 of the display substrate shown in FIG. 8A according to an embodiment of the present disclosure is not adopted, the gap between the second sub-electrode layer 2b of the first portion 21 and the second sub-electrode layer 2b of the second portion 22 needs to be enlarged, thus reducing the size of the opening area 60 of the pixel defining layer 6; therefore, the design regarding the edges of the first portion 21 and the second portion 22 of the display substrate shown in FIG. 8A according to an embodiment of the present disclosure further enhances the aperture ratio of the sub-pixel.

[0154] For example, in some embodiments, the orthogonal projection of the first sub-electrode layer 2a of the first portion 21 of the first electrode 2 onto the base substrate 1 is located within the orthogonal projection of the second sub-electrode layer 2b of the first portion 21 of the first electrode 2 onto the base substrate 1, the area of ​​the orthogonal projection of the first sub-electrode layer 2a of the first portion 21 of the first electrode 2 onto the base substrate 1 is smaller than the area of ​​the orthogonal projection of the second sub-electrode layer 2b of the first portion 21 of the first electrode 2 onto the base substrate 1, the orthogonal projection of the first sub-electrode layer 2a of the second portion 22 of the first electrode 2 onto the base substrate 1 is located within the orthogonal projection of the second sub-electrode layer 2b of the second portion 22 of the first electrode 2 onto the base substrate 1, and the area of ​​the orthogonal projection of the first sub-electrode layer 2a of the second portion 22 of the first electrode 2 onto the base substrate 1 is smaller than the area of ​​the orthogonal projection of the second sub-electrode layer 2b of the second portion 22 of the first electrode 2 onto the base substrate 1, further reducing the risk of contact between sub-electrode layers spaced apart from each other in the above ideal state.

[0155] For example, as shown in FIGS. 7 to 9 , the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 further include a third sub-electrode layer 2c, and the third sub-electrode layer 2c of the first portion 21 of the first electrode 2 is stacked with the second sub-electrode layer 2b of the first portion 21 of the first electrode 2 in the direction perpendicular to the base substrate 1 and is located on the side of the second sub-electrode layer 2b of the first portion 21 of the first electrode 2 that is away from the base substrate 1, and the third sub-electrode layer 2c of the second portion 22 of the first electrode 2 is stacked with the second sub-electrode layer 2b of the second portion 22 of the first electrode 2 in the direction perpendicular to the base substrate 1. layer 2b and is located on the side of the second sub-electrode layer 2b of the second portion 22 of the first electrode 2 facing away from the base substrate 1, the third sub-electrode layer 2c of the first portion 21 of the first electrode 2 has a fifth edge 2c-1 close to the second portion 22 of the first electrode 2, and the first edge 2a-1 is located on the side of the fifth edge 2c-1 facing away from the second portion 22 of the first electrode 2, and the third sub-electrode layer 2c of the second portion 22 of the first electrode 2 has a sixth edge 2c-2 close to the first portion 21 of the first electrode 2, and the third edge 2a-2 is located on the side of the sixth edge 2c-2 facing away from the first portion 21 of the first electrode 2. That is, the edge close to the second portion 22 of the first sub-electrode layer 2a of the first portion 21 is further shrunk relative to the edge close to the second portion 22 of the third sub-electrode layer 2c of the first portion 21, and the edge close to the first portion 21 of the first sub-electrode layer 2a of the second portion 22 is further shrunk relative to the edge close to the first portion 21 of the third sub-electrode layer 2c of the second portion 22, thereby preventing contact between the third sub-electrode layer 2c of the first portion 21 and the first sub-electrode layer 2a of the second portion 22, and preventing contact between the third sub-electrode layer 2c of the second portion 22 and the first sub-electrode layer 2a of the first portion 21. Furthermore, if a design is not adopted in which the first edge 2a-1 of the display substrate shown in FIG. 8A according to an embodiment of the present disclosure is farther from the second portion 22 than the fifth edge 2c-1, and the third edge 2a-2 is farther from the first portion 21 than the sixth edge 2c-2, then it would be necessary to increase the distance between the third sub-electrode layer 2c of the first portion 21 and the third sub-electrode layer 2c of the second portion 22, thus reducing the size of the opening area 60 of the pixel definition layer 6. Therefore, the design of the edges of the first portion 21 and the second portion 22 of the display substrate shown in FIG. 8A according to an embodiment of the present disclosure further increases the aperture ratio of the sub-pixels.

[0156] For example, the orthogonal projection of the first sub-electrode layer 2a of the first portion 21 of the first electrode 2 onto the base substrate 1 is located within the orthogonal projection of the third sub-electrode layer 2c of the first portion 21 of the first electrode 2 onto the base substrate 1, and the area of ​​the orthogonal projection of the first sub-electrode layer 2a of the first portion 21 of the first electrode 2 onto the base substrate 1 is smaller than the area of ​​the orthogonal projection of the third sub-electrode layer 2c of the first portion 21 of the first electrode 2 onto the base substrate 1; the orthogonal projection of the first sub-electrode layer 2a of the second portion 22 of the first electrode 2 onto the base substrate 1 is located within the orthogonal projection of the third sub-electrode layer 2c of the second portion 22 of the first electrode 2 onto the base substrate 1, and the area of ​​the orthogonal projection of the first sub-electrode layer 2a of the second portion 22 of the first electrode 2 onto the base substrate 1 is smaller than the area of ​​the orthogonal projection of the third sub-electrode layer 2c of the second portion 22 of the first electrode 2 onto the base substrate 1, further reducing the risk of contact between sub-electrode layers spaced apart from each other in the above ideal state.

[0157] 8A, the second edge 2b-1 is shrunk more than the fifth edge 2c-1, i.e., the second edge 2b-1 is located on the side of the fifth edge 2c-1 that is farther from the second portion 22, and the fourth edge 2b-2 is shrunk more than the sixth edge 2c-2, i.e., the fourth edge 2b-2 is located on the side of the sixth edge 2c-2 that is farther from the first portion 21. This further reduces the risk of contact between the second sub-electrode layer 2b of the first portion 21 and the second sub-electrode layer 2b of the second portion 22, the risk of contact between the second sub-electrode layer 2b of the first portion 21 and the first sub-electrode layer 2a of the second portion 22, the risk of contact between the second sub-electrode layer 2b of the second portion 22 and the first sub-electrode layer 2a of the first portion 21, and the risk of contact between the third sub-electrode layer 2c of the second portion 22 and the first sub-electrode layer 2a of the first portion 21. Other features and technical effects of FIG. 8B are similar to the embodiment shown in FIG. 8A.

[0158] For example, in the embodiment shown in FIG. 8B, the second sub-electrode layer 2b of the first portion 21, the third sub-electrode layer 2c of the first portion 21, the second sub-electrode layer 2b of the second portion 22, and the third sub-electrode layer 2c of the second portion 22 may be formed by the same patterning process using the same mask, for example, by adopting an etching process such as a wet etching process, so as to simplify the manufacturing process of the display substrate 10, and the material of the second sub-electrode layer 2b and the material of the third sub-electrode layer 2c are different, so that they have different etching rates, thereby obtaining the structure shown in FIG. 8B.

[0159] The patterning process in the present disclosure includes, for example, a photoetching process, but may of course be other patterning processes.

[0160] For example, the material of the first sub-electrode layer 2a of the first portion 21 and the first sub-electrode layer 2a of the second portion 22 is a transparent conductive material, the material of the second sub-electrode layer 2b of the first portion 21 and the second sub-electrode layer 2b of the second portion 22 is a metal material, and the material of the third sub-electrode layer 2c of the first portion 21 and the third sub-electrode layer 2c of the second portion 22 is a transparent conductive material. For example, the material of the second sub-electrode layer 2b may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials combining the above metals. For example, the material of the first sub-electrode layer 2a and the material of the third sub-electrode layer 2c are conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and aluminum zinc oxide (AZO). Of course, the materials of the first sub-electrode layer 2a, the second sub-electrode layer 2b and the third sub-electrode layer 2c are not limited to the types listed above, and are not limited thereto in the embodiments of the present disclosure.

[0161] 8A, the orthogonal projection of the second sub-electrode layer 2b of the first portion 21 of the first electrode 2 onto the base substrate 1 is located within the orthogonal projection of the third sub-electrode layer 2c of the first portion 21 of the first electrode 2 onto the base substrate 1, and the orthogonal projection of the second sub-electrode layer 2b of the second portion 22 of the first electrode 2 onto the base substrate 1 is located within the orthogonal projection of the third sub-electrode layer 2c of the second portion 22 of the first electrode 2 onto the base substrate 1. That is, each side of the second sub-electrode layer 2b of the first portion 21 is shrunk within the corresponding side of the third sub-electrode layer 2c of the first portion 21, and each side of the second sub-electrode layer 2b of the second portion 22 is shrunk within the corresponding side of the third sub-electrode layer 2c of the second portion 22.

[0162] For example, as shown in FIG. 8A, the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 are aligned in the vertical direction, the first edge 2a-1 and the second edge 2b-1 are spaced apart in the vertical direction by a first distance d1, the third edge 2a-2 and the fourth edge 2b-2 are spaced apart in the vertical direction by a second distance d2, and the first distance d1 and the second distance d2 are approximately equal.

[0163] For example, the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 are aligned in the vertical direction, the first edge 2a-1 and the second edge 2b-1 are spaced apart by a first distance d1 in the vertical direction, and the third edge 2a-2 and the fourth edge 2b-2 are spaced apart by a second distance d2 in the vertical direction. The first distance d1 is in the range of 1 μm to 1.5 μm, and the second distance d2 is in the range of 1 μm to 1.5 μm, thereby effectively preventing contact between the second sub-electrode layer 2b of the first portion 21 and the second sub-electrode layer 2b of the second portion 22, contact between the second sub-electrode layer 2b of the first portion 21 and the first sub-electrode layer 2a of the second portion 22, and contact between the second sub-electrode layer 2b of the second portion 22 and the first sub-electrode layer 2a of the first portion 21.

[0164] For example, the third distance d3 between the first edge 2a-1 and the third edge 2a-2 is greater than the fourth distance d4 between the second edge 2b-1 and the fourth edge 2b-2. For example, the third distance d3 between the first edge 2a-1 and the third edge 2a-2 is not smaller than 6 μm, or the fourth distance d4 between the second edge 2b-1 and the fourth edge 2b-2 is not smaller than 4 μm. This effectively prevents contact between the second sub-electrode layer 2b of the first portion 21 and the second sub-electrode layer 2b of the second portion 22 due to the spacing being too small, and prevents contact between the second sub-electrode layer 2b of the first portion 21 and the first sub-electrode layer 2a of the second portion 22, and between the second sub-electrode layer 2b of the second portion 22 and the first sub-electrode layer 2a of the first portion 21.

[0165] 8B, the fifth edge 2c-1 and the second edge 2b-1 are substantially flush with each other, and the sixth edge 2c-2 and the fourth edge 2b-2 are substantially flush with each other, thereby reducing the risk of contact between the sub-electrode layers spaced apart from each other in the ideal state, thereby reducing the difficulty of manufacturing the display substrate 10. For example, in order to simplify the manufacturing process of the display substrate 10, the second sub-electrode layer 2b of the first portion 21, the third sub-electrode layer 2c of the first portion 21, the second sub-electrode layer 2b of the second portion 22, and the third sub-electrode layer 2c of the second portion 22 may be formed by the same patterning process using the same mask. For example, in the manufacturing process of the display substrate 10, after forming the first conductive layer 100, the first insulating layer 101, the semiconductor layer 600, the second insulating layer 102, the second conductive layer 200, the third insulating layer 103, the third conductive layer 300, the fourth insulating layer 104, and the fifth insulating layer 105 on the base substrate 1, a first conductive material layer is formed covering the fifth insulating layer 105, a first mask is used to perform a first patterning process on the first conductive material layer to form the first sub-electrode layer 2a of the first portion 21 and the second sub-electrode layer 2b of the first portion 21, and a second conductive material layer is formed covering the first sub-electrode layer 2a of the first portion 21 and the second sub-electrode layer 2b of the first portion 21, and a second conductive material layer is formed covering the first sub-electrode layer 2a of the first portion 21 and the second sub-electrode layer 2b of the first portion 21. a third conductive material layer located on the side away from the base substrate 1, the third conductive material layer and the second conductive material layer being stacked in a direction perpendicular to the base substrate 1; and a second patterning process is performed on the second conductive material layer and the third conductive material layer by using a second mask to form the second sub-electrode layer 2 b of the first portion 21, the third sub-electrode layer 2 c of the first portion 21, the second sub-electrode layer 2 b of the second portion 22 and the third sub-electrode layer 2 c of the second portion 22. In this way, the fifth edge 2 c-1 and the second edge 2 b-1 are approximately flush with each other, and the sixth edge 2 c-2 and the fourth edge 2 b-2 are approximately flush with each other, which simplifies the manufacturing process of the display substrate 10 and reduces the manufacturing difficulty of the display substrate 10.

[0166] It should be explained that the above "substantially flush" is not limited to being completely flush. Since the material of the first conductive material layer and the material of the second conductive material layer for forming the second sub-electrode layer 2b and the third sub-electrode layer 2c are different, for example, there is a certain deviation distance between the fifth edge 2c-1 and the second edge 2b-1, and the deviation distance is 5% or less of the size in the direction of the third sub-electrode layer 2c of the first portion 21 or 5% or less of the size in the direction of the second sub-electrode layer 2b of the first portion 21, both of which may be understood as the fifth edge 2c-1 and the second edge 2b-1 being substantially flush. Similarly, the sixth edge 2c-2 and the fourth edge 2b-2 being substantially flush may also be understood as being substantially flush.

[0167] For example, the orthogonal projection of the second sub-electrode layer 2b of the first portion 21 of the first electrode 2 onto the base substrate 1 and the orthogonal projection of the third sub-electrode layer 2c of the first portion 21 of the first electrode 2 onto the base substrate 1 substantially overlap, and the orthogonal projection of the second sub-electrode layer 2b of the second portion 22 of the first electrode 2 onto the base substrate 1 and the orthogonal projection of the third sub-electrode layer 2c of the second portion 22 of the first electrode 2 onto the base substrate 1 substantially overlap. As with the above-mentioned "substantially flush," "substantially overlap" here also means that there is a deviation in a certain direction between the two substantially overlapping projections, and the deviation belonging to 5% or less of the size of the second sub-electrode layer 2b of the first portion 21 in that direction may be understood as the orthogonal projection of the second sub-electrode layer 2b of the first portion 21 of the first electrode 2 onto the base substrate 1 and the orthogonal projection of the third sub-electrode layer 2c of the first portion 21 of the first electrode 2 onto the base substrate 1 substantially overlap. Similarly, the orthogonal projection of the second sub-electrode layer 2b of the second portion 22 of the first electrode 2 onto the base substrate 1 and the orthogonal projection of the third sub-electrode layer 2c of the second portion 22 of the first electrode 2 onto the base substrate 1 approximately overlap.

[0168] For example, in a display substrate according to at least one embodiment of the present disclosure, the orthogonal projections of the channel regions of all the transistors of the subpixel onto the base substrate 1 are all located within the orthogonal projections of the first electrode 2 onto the base substrate 1, and the channel regions of all the transistors of the subpixel are located on the side of the first electrode 2 closer to the base substrate 1. For example, in each subpixel, the orthogonal projections of the channel regions of the drive transistor T1, the channel region of the data transistor T2, and the channel region of the detection transistor T3 onto the base substrate 1 are all located within the orthogonal projections of the first electrode 2 onto the base substrate 1, and the channel regions of the drive transistor T1, the channel region of the data transistor T2, and the channel region of the detection transistor T3 are located on the side of the first electrode 2 closer to the base substrate 1. In this way, all the transistor channel regions of the subpixel are shielded from light by the first electrode 2, and the first electrode 2 is used to shield the toplight from the side of the transistor channel regions away from the base substrate 1.

[0169] The light-emitting device 20 further includes a light-emitting layer 23, which is located on the side of the first electrode 2 facing away from the base substrate 1, the first electrode 2 being a reflective electrode, and light emitted from the light-emitting layer 23 is emitted from the side of the first electrode 2 facing away from the base substrate 1.

[0170] For example, as shown in FIGS. 3A-3B , in the display substrate 10 according to at least one embodiment, in each subpixel (e.g., P1 to P4), the orthogonal projection of the channel region of the driving transistor T1 onto the base substrate 1 is located within the orthogonal projection of the second portion 22 of the first electrode 2 onto the base substrate 1, and the orthogonal projection of the channel region of the data writing transistor T2 onto the base substrate 1 and the orthogonal projection of the channel region of the detection transistor T3 onto the base substrate 1 are both located within the orthogonal projection of the first portion 21 of the first electrode 2 onto the base substrate 1, so that the four subpixels P1 to P4 of one display unit P are approximately symmetrical (almost symmetrical) in the first direction D1 or the second direction D2. In the case where most of the devices are symmetrical (the whole is symmetrical, and it is not necessary for each layer and each device to be symmetrical), the first and second parts of the first electrode of each subpixel are reasonably aligned with the position of the channel region of each transistor of the corresponding subpixel, so as to realize reasonable spatial utilization and spatial arrangement, and to reduce the area of ​​the display area as much as possible, which is of great significance for a transparent display device using this display substrate, and can combine the area of ​​the non-emissive area to achieve the requirement of utilizing the display area to display an image, and can also better combine the function of transmitting an environmental image through the non-emissive area.

[0171] 10 is a schematic diagram of an arrangement of a plurality of sub-pixels in one display unit P according to an embodiment of the present disclosure. For example, as shown in FIG. 10, the length of one sub-pixel in the second direction D2 is greater than the width of the sub-pixel in the first direction D1, the first part 21 of the first electrode 2 and the second part 22 of the first electrode 2 are aligned in the second direction D2, and the area of ​​the orthogonal projection of the first sub-pixel P1 onto the base substrate 1 and the area of ​​the orthogonal projection of the third sub-pixel P3 onto the base substrate 1 are both greater than the area of ​​the orthogonal projection of the second sub-pixel P2 onto the base substrate 1 and the area of ​​the orthogonal projection of the fourth sub-pixel P4 onto the base substrate 1. In this way, the first sub-pixel P1 and the third sub-pixel P3, which are large in size, are aligned along the length direction and located in the same column of sub-pixels, which can rationally arrange the sub-pixels in the display area 11 and prevent the display area 11 from occupying too much area, thereby not affecting the space of the non-emitting area 12. For example, the area of ​​the orthogonal projection of the first subpixel P1 onto the base substrate 1 is larger than the area of ​​the orthogonal projection of the third subpixel P3 onto the base substrate 1, the area of ​​the orthogonal projection of the second subpixel P2 onto the base substrate 1, and the area of ​​the orthogonal projection of the fourth subpixel P4 onto the base substrate 1, so that the larger subpixels are located in the same row, which makes it easy to regularly arrange four subpixels in one display unit P by utilizing the limited area of ​​the display region 11.

[0172] For example, the first sub-pixel P1 emits red (R) light, the second sub-pixel P2 emits blue (B) light, the third sub-pixel P3 emits white (W) light, and the fourth sub-pixel P4 emits green (G) light, so that sub-pixels of different areas correspond to corresponding emission colors, thereby balancing the difference in lifetime of the light-emitting layers emitting light of different colors.

[0173] At least one embodiment of the present disclosure further provides a display substrate including a base substrate and a display unit disposed on the base substrate, the display unit including a display region and a non-light-emitting region, the display region including a sub-pixel, the sub-pixel including a driving transistor and a light-emitting device, the driving transistor configured to control a magnitude of a driving current flowing through the light-emitting device, the light-emitting device configured to receive the driving current and be driven by the driving current to emit light, the light-emitting device including a common electrode connected to a common voltage terminal, the display unit including an auxiliary electrode line, a first auxiliary electrode, and an auxiliary insulating layer. The auxiliary electrode line includes a vertical portion located in the display area and a horizontal portion located at least partially in the non-light-emitting area and connected to the vertical portion, a first auxiliary electrode is located in the non-light-emitting area and electrically connected to the common electrode, an auxiliary insulating layer includes a first auxiliary via located in the non-light-emitting area and exposing at least a part of the horizontal portion, the first auxiliary electrode is connected to the horizontal portion through the first auxiliary via, the horizontal portion, the first auxiliary electrode, and the first auxiliary via constitute one auxiliary unit, the display unit includes a plurality of the auxiliary units, the horizontal portion of the auxiliary electrode line extends along a first direction, the vertical portion of the auxiliary electrode line extends along a second direction intersecting the first direction, and the plurality of auxiliary units are arranged spaced apart from each other in the second direction. In the display panel, a first auxiliary electrode connected in parallel to a common electrode is provided in the non-light-emitting area to reduce the resistance of the original common electrode.

[0174] Illustratively, FIG. 11A is a partial plan view schematic diagram of the first auxiliary unit H1 of the display unit shown in FIG. 3A, and FIG. 11B is a cross-sectional view schematic diagram along the line E-E' in FIG. 11A. Combining FIG. 3A and FIG. 11A-11B, in a display substrate according to at least one embodiment of the present disclosure, the light-emitting device 20 includes a common electrode connected to a common voltage terminal. The common electrode is, for example, a second electrode 24 (hereinafter referred to as a common electrode 24), for example, a common cathode. The display unit P includes an auxiliary electrode line 8, a first auxiliary electrode 91, and an auxiliary insulating layer 104. For example, the auxiliary electrode line 8 is located on the third conductive layer 300, so refer to FIG. 11A-11B and FIG. 5F. The auxiliary electrode line 8 includes a vertical portion 81 located in the display area 11, and a horizontal portion 821 connected to the vertical portion 81 and located at least partially in the non-light-emitting area 12. For example, the horizontal portion 821 and the vertical portion 81 are a continuous integrally molded structure. For example, the horizontal portion 821 of the auxiliary electrode wire 8 extends along a first direction D1, and the vertical portion 81 of the auxiliary electrode wire 8 extends along a second direction D2 intersecting the first direction D1. The first auxiliary electrode 91 is located in the non-light-emitting region 12 and is electrically connected to the common electrode 24, the auxiliary insulating layer 104 includes a first auxiliary via V001 located in the non-light-emitting region 12 and exposing at least a part of the horizontal portion 821, and the first auxiliary electrode 91 is connected to the horizontal portion 821 through the first auxiliary via V001. That is, by utilizing the first auxiliary via V001, the horizontal portion 821 is connected to the common electrode 24 through the first auxiliary electrode 91. In this way, by installing the first auxiliary via V001 and the first auxiliary electrode 91 in the non-light-emitting area 12 and extending the horizontal portion 821 from the display area 11 to the non-light-emitting area 12, the first auxiliary electrode 91 is electrically connected to the horizontal portion 821 of the auxiliary electrode line 8 in the non-light-emitting area 12 via the first auxiliary via V001.The first auxiliary electrode 91 is further electrically connected to the common electrode 24, thereby realizing an electrical connection between the horizontal portion 821 of the auxiliary electrode line 8 and the common electrode 24 in the non-light-emitting area 12, thereby adding the first auxiliary electrode 91 and the auxiliary electrode line 8 connected in parallel to the common electrode 24, reducing the resistance of the original common electrode, and not occupying space in the display area 11, but utilizing the non-light-emitting area 12 where space is very sufficient to install the first auxiliary electrode 91, the first auxiliary via V001 and the horizontal portion 821 of the auxiliary electrode line 8.

[0175] For example, the auxiliary electrode line 8 here is the second power line vss. For an explanation of the display area 11 and the non-light emitting area 12, please refer to the above explanation.

[0176] For example, the auxiliary insulating layer 104 and the fourth insulating layer 104 are in the same layer and made of the same material, and are similarly formed by performing the same patterning on the same film layer, and the same patterning process is, for example, a photoetching process including steps such as exposure and development.

[0177] For example, the interlayer insulating layer 105 and the fifth insulating layer are in the same layer and made of the same material, and are similarly formed by performing the same patterning on the same film layer, and the same patterning process is, for example, a photoetching process including steps such as exposure and development.

[0178] For example, as shown in FIG. 11B, the first auxiliary electrode 91 includes a first sub-conductive layer 901, a first laminated portion 91a, and a second laminated portion 91b. The first sub-conductive layer 901 is connected to the horizontal portion 821 through a first auxiliary via V001. The first laminated portion 91a is electrically connected to the first sub-conductive layer 901 and laminated in a direction perpendicular to the base substrate 1, and includes a first laminated layer 911 and a second laminated layer 912 located on the side of the first sub-conductive layer 901 that is away from the base substrate 1 and laminated on each other in a direction perpendicular to the base substrate 1, and the second laminated layer 912 is located on the side of the first laminated layer 911 that is away from the base substrate 1 and connected to the common electrode 24. The first laminated portion 91a is located at the end of the first auxiliary electrode 91 closest to the display area 11, and is directly connected to a structure in the display area 11. For example, the second laminated layer 912 is directly connected to the common electrode 24, and there is no other electrode or structure between them. The second laminated portion 91b and the first sub-conductive layer 901 are laminated in a direction perpendicular to the base substrate 1, and are located on the side of the first sub-conductive layer 901 that is away from the base substrate 1, and on the side of the first laminated portion 91a that is away from the display region 11. The second laminated portion 91b and the first laminated portion 91a are electrically connected via the first sub-conductive layer 901, and for example, the second laminated portion 91b and the first sub-conductive layer 901 are in direct contact, and the second laminated portion 91b and the first laminated portion 91a are in direct contact. For example, the surfaces of the second laminated portion 91b and the first sub-conductive layer 901 that are laminated in a direction perpendicular to the base substrate 1 are in direct contact, and the surfaces of the second laminated portion 91b and the first laminated portion 91a that are laminated in a direction perpendicular to the base substrate 1 are in direct contact. The second laminate portion 91b includes a third laminate layer 913 and a fourth laminate layer 914 that are laminated on top of each other in a direction perpendicular to the base substrate 1, and the third laminate layer 913 and the first laminate layer 911 are made of the same material, are arranged in the same layer and are spaced apart from each other in a direction parallel to the base substrate 1, and the fourth laminate layer 914 and the second laminate layer 912 are made of the same material, are arranged in the same layer and are spaced apart from each other in a direction parallel to the base substrate 1.

[0179] For example, the third lamination layer 913 and the first lamination layer 911 are formed by the same process. The same process may be a patterning process, for example, the patterning process includes forming the third lamination layer 913 and the first lamination layer 911 by performing deposition using a deposition mask plate, or includes performing processes such as exposure, development, and etching using a mask plate. Or, the same process may not include a patterning process, for example, and only includes a deposition or deposition process, so that the third lamination layer 913 and the first lamination layer 911 are naturally isolated (described below), thereby simplifying the manufacturing process of the display substrate.

[0180] Similarly, for example, the fourth lamination layer 914 and the second lamination layer 912 are formed by the same process. The same process may be a patterning process, for example, including forming the fourth lamination layer 914 and the second lamination layer 912 by performing deposition using a deposition mask plate, or including performing processes such as exposure, development, and etching using a mask plate. Or, the same process may not include a patterning process, for example, and may only include a deposition or deposition process, thereby naturally isolating the fourth lamination layer 914 and the second lamination layer 912 (described below), thereby simplifying the manufacturing process of the display substrate.

[0181] 11B, the second lamination layer 912 is connected to the common electrode 24 and is in direct contact with the first sub-conductive layer 901, for example, in the first region TP1. For example, the first lamination layer 911 is in contact with the first sub-conductive layer 901. The second lamination layer 912 includes an upper portion covering the upper surface of the first lamination layer 911 away from the base substrate 1 and a side portion covering the side surface of the first lamination layer 911 intersecting with the upper surface, and the side portion is in contact with the first sub-conductive layer 901. That is, the first region TP1 is located at the edge close to the second stacking portion 91b of the second laminate layer 912, the side of the second laminate layer 912 is the edge portion close to the second laminate portion 91b of the second laminate layer 912 (the portion of the second laminate layer 912 located in the first region TP1), and the edge portion of the second laminate layer 912 is in direct contact with the first sub-conductive layer 901.

[0182] For example, as shown in FIG. 11B, the second laminate layer 912 covers the top surface of the first laminate layer 911 facing away from the base substrate 1 and the side surface that intersects with the top surface, and the edge portion of the second laminate layer 912 near the second laminate portion 91b covers at least the side surface of the first laminate layer 911, i.e., by covering the edge of the first laminate layer 911 near the second laminate portion 91b, the edge portion of the second laminate layer 912 near the second laminate portion 91b can directly contact the first sub-conductive layer 901.

[0183] 11B, the second lamination portion 91b further includes a fifth lamination layer 915 and a sixth lamination layer 916. The fifth lamination layer 915 is located between the first conductive sub-layer 901 and the third lamination layer 913, and the sixth lamination layer 916 is located between the fifth lamination layer 915 and the third lamination layer 913. The fifth lamination layer 915 and the sixth lamination layer 916 are laminated with the first sub-conductive layer 901, the third lamination layer 913, and the fourth lamination layer 914 in a direction perpendicular to the base substrate 1 and are electrically connected to each other, and the fifth lamination layer 915 and the sixth lamination layer 916 are all spaced apart from the first lamination layer 911 and the second lamination layer 912 in a direction parallel to the base substrate 1, that is, the third lamination layer 913, the fourth lamination layer 914, the fifth lamination layer 915, and the sixth lamination layer 916 are all spaced apart from the first lamination layer 911 and the second lamination layer 912 in a direction parallel to the base substrate 1. For example, the orthogonal projection of the sixth lamination layer 916 onto the base substrate 1 includes a middle region CR and an edge region PR surrounding the middle region CR, and the orthogonal projection of the fifth lamination layer 915 onto the base substrate 1 does not overlap with the edge region PR but overlaps with the middle region CR. At least a part of the orthogonal projection of the first region TP1 onto the base substrate 1 is located within the orthogonal projection of the edge region PR onto the base substrate 1. In this way, by stacking a plurality of conductive layers to form the second stacked portion 91b, it is more advantageous to better reduce the resistance of the original common electrode. For example, while combining with FIG. 4A, the light-emitting device 20 includes the above-mentioned first electrode 2 and light-emitting layer 23 located in the display area 11, the light-emitting layer 23 is sandwiched between the first electrode 2 and the common electrode 24, and the first electrode 2 includes a first sub-electrode layer 2a, a second sub-electrode layer 2b, and a third sub-electrode layer 2c stacked in order along a direction perpendicular to the base substrate 1 from a direction closer to the base substrate 1 to a direction away from the base substrate 1.For example, the first sub-conductive layer 901 and the first sub-electrode layer 2a of the first auxiliary electrode 91 are made of the same material and are disposed in the same layer, the first laminated layer 911 and the light-emitting layer 23 are made of the same material and are disposed in the same layer and form a continuous integral structure, the second laminated layer 912 and the common electrode 24 are made of the same material and are disposed in the same layer and form a continuous integral structure, the third laminated layer 913 and the light-emitting layer 23 are made of the same material and are disposed in the same layer, the fourth laminated layer 914, the second laminated layer 912 and the common electrode 24 are made of the same material and are disposed in the same layer, the fifth laminated layer 915 and the second sub-electrode layer 2b are made of the same material and are disposed in the same layer, and the sixth laminated layer 916 and the third sub-electrode layer 2c are made of the same material and are disposed in the same layer. In this way, the first sub-conductive layer 901 and the first sub-electrode layer 2a of the first auxiliary electrode 91 can be formed by the same process, the first laminated layer 911, the light-emitting layer 23, and the third laminated layer 913 can be formed by the same process, the fourth laminated layer 914, the second laminated layer 912, and the common electrode 24 can be formed by the same process, the fifth laminated layer 915 and the second sub-electrode layer 2b can be formed by the same process, and the sixth laminated layer 916 and the third sub-electrode layer 2c can be formed by the same process. The "same process" here can refer to the above interpretation. In this way, the layer structures of the first auxiliary electrode 91 can be formed by adopting processes corresponding to the above functional layers in the display area 11, and there is no need to add a film layer manufacturing process or a patterning process to install the first auxiliary electrode 91.

[0184] For example, in the manufacturing process of the display substrate shown in FIG. 11B, for example, the fifth stacking layer 915 and the sixth stacking layer 916 can be formed by the same patterning process using the same mask, for example, by adopting an etching process, such as a wet etching process, thereby simplifying the manufacturing process of the display substrate; and the materials of the fifth stacking layer 915 and the sixth stacking layer 916 are different, and the materials of the fifth stacking layer 915 and the sixth stacking layer 916 are the same as the materials of the second sub-electrode layer 2b and the third sub-electrode layer 2c, respectively, and reference can be made to the previous description of the materials of the second sub-electrode layer 2b and the third sub-electrode layer 2c, thereby forming a fifth stacking layer 915 that is shrunk inward more than the sixth stacking layer 916 shown in FIG. 11B, that is, the orthogonal projection of the fifth stacking layer 915 onto the base substrate 1 does not overlap with the edge region PR, but overlaps with the middle region CR. After forming the fifth stacking layer 915 and the sixth stacking layer 916, steps of forming the first stacking layer 911, the light-emitting layer 23 and the third stacking layer 913, and steps of forming the fourth stacking layer 914 and the second stacking layer 912 are carried out in sequence.

[0185] In the process of forming the first lamination layer 911, the light-emitting layer 23, and the third lamination layer 913 on the side of the sixth lamination layer 916 away from the base substrate 1, for example, a deposition method is adopted to form the first lamination layer 911, the light-emitting layer 23, and the third lamination layer 913, and the first lamination layer 911 and the light-emitting layer 23 can be formed as an integral structure. Due to the existence of the fifth lamination layer 915 and the sixth lamination layer 916, the fifth lamination layer 915 and the sixth lamination layer 916 have a certain thickness, and there is a step between the upper surface of the sixth lamination layer 916 away from the base substrate 1 and the upper surface of the first sub-conductive layer 901 away from the base substrate 1, and the third lamination layer 913 and the first lamination layer 911 are mutually isolated by the step. And there is a step between the upper surface of the third lamination layer 913 away from the base substrate 1 and the upper surface of the first lamination layer 911 away from the base substrate 1.

[0186] Subsequently, in the process of forming the fourth lamination layer 914, the second lamination layer 912, and the common electrode 24, the fourth lamination layer 914, the second lamination layer 912, and the common electrode 24 are formed by, for example, a deposition method, and the second lamination layer 912 and the common electrode 24 can be formed as an integral structure. Due to the step between the upper surface of the third lamination layer 913 that is away from the base substrate 1 and the upper surface of the first lamination layer 911 that is away from the base substrate 1, the fourth lamination layer 914 and the second lamination layer Since the second laminate layer 912 and the fifth laminate layer 915 are mutually isolated, and the fifth laminate layer 915 is shrunk inward more than the sixth laminate layer 916, i.e., the orthogonal projection of the fifth laminate layer 915 onto the base substrate 1 overlaps with the middle region CR but not with the edge region PR, the second laminate layer 912 and the first sub-conductive layer 901 can be brought into contact in the first region TP1, and at least a portion of the orthogonal projection of the first region TP1 onto the base substrate 1 is located within the orthogonal projection of the edge region PR onto the base substrate 1.

[0187] In this way, the common electrode 24 and the first sub-conductive layer 901 are connected, thereby realizing a parallel connection between the first auxiliary electrode 91 and the common electrode 24, thereby reducing the resistance of the original common electrode 24.

[0188] For example, when the sum of the thickness of the fifth laminate layer 915 in a direction perpendicular to the base substrate 1 and the thickness of the sixth laminate layer 916 in a direction perpendicular to the base substrate 1 is 6000 Å or more, the fifth laminate layer 915 has a sufficient thickness, thereby forming a sufficient step between the upper surface of the sixth laminate layer 916 facing away from the base substrate 1 and the upper surface of the first sub-conductive layer 901 facing away from the base substrate 1, and further ensuring reliability in that the third laminate layer 913 and the first laminate layer 911 are cut from each other by the step, and reliability in that the fourth laminate layer 914 and the second laminate layer 912 are cut from each other.

[0189] 11B, the first auxiliary electrode 91 further includes a third laminated portion 91c. The third laminated portion 91c is laminated with the first sub-conductive layer 901 in a direction perpendicular to the base substrate 1, is located on the side of the first sub-conductive layer 901 that is away from the base substrate 1, is electrically connected to the first laminated portion 91a and the second laminated portion 91b via the first sub-conductive layer 901, and includes a seventh laminated layer 917 and an eighth laminated layer 918 that are laminated with each other in a direction perpendicular to the base substrate 1, the seventh laminated layer 917 and the third laminated layer 913 are disposed in the same layer and are spaced apart from each other in a direction parallel to the base substrate 1, and the eighth laminated layer 918 and the fourth laminated layer 914 are disposed in the same layer and are spaced apart from each other in a direction parallel to the base substrate 1.

[0190] For example, the eighth lamination layer 918 and the first sub-conductive layer 901 are in direct contact, for example, the eighth lamination layer 918 and the first sub-conductive layer 90 are in contact in the second region TP2, and at least a part of the orthogonal projection of the second region TP2 onto the base substrate 1 is located within the orthogonal projection of the edge region PR onto the base substrate 1. Similar to the situation in the first region TP1, the eighth lamination layer 918 covers the upper surface of the seventh lamination layer 917 away from the base substrate 1 and the side surface intersecting the upper surface, and the edge portion of the eighth lamination layer 918 close to the second lamination portion 91b covers at least the side surface of the seventh lamination layer 917, i.e., by covering the edge close to the second lamination portion 91b of the seventh lamination layer 917, the edge portion of the eighth lamination layer 918 close to the second lamination portion 91b can be in direct contact with the first sub-conductive layer 901.

[0191] For example, the seventh stacking layer 917, the third stacking layer 913, and the light emitting layer 23 are made of the same material and are disposed in the same layer, and the eighth stacking layer 918, the fourth stacking layer 914, and the second stacking layer 912 are made of the same material and are disposed in the same layer. In this way, the seventh stacking layer 917, the third stacking layer 913, and the light emitting layer 23 can be formed by the same process, and the eighth stacking layer 918 and the fourth stacking layer 914 can be formed by the same process. The above interpretation may be referred to for the "same process" here. As with the formation of the structure in the first region TP1, in the process of forming the seventh stacking layer 917, the third stacking layer 913, and the light-emitting layer 23 using the same process, the seventh stacking layer 917 and the third stacking layer 913 can be separated by a step formed using the fifth stacking layer 915 and the sixth stacking layer 916, and in the process of forming the eighth stacking layer 918, the fourth stacking layer 914, and the second stacking layer 912 using the same process, the eighth stacking layer 918 and the fourth stacking layer 914 are separated.

[0192] 11C is a schematic plan view showing the positional relationship between the second, fourth, fifth and eighth lamination layers in FIG. 11B. Combining FIG. 11B and FIG. 11C, for example, the second lamination layer 912 and the eighth lamination layer 918 are a continuous integral structure, and the integral structure has an edge portion surrounding the second lamination portion 91b, and the edge portion is in direct contact with the first sub-conductive layer 901, that is, in the peripheral region surrounding the entire second lamination portion 91b, the first sub-conductive layer 901 can be in direct contact with the continuous integral structure consisting of the second lamination layer 912 and the eighth lamination layer 918, thereby connecting the first sub-conductive layer 901 and the continuous integral structure consisting of the second lamination layer 912 and the eighth lamination layer 918 at multiple positions, and ensuring the reliability of the electrical connection between the first sub-conductive layer 901 and the common electrode 24. The first region TP1 and the second region TP2 are two parts located on opposite sides of the second stacking portion 91b in the peripheral region, and Figure 11B uses the two positions of the first region TP1 and the second region TP2 as examples to illustrate how the first sub-conductive layer 901 is electrically connected to the common electrode 24.

[0193] 11A and 11B, the interlayer insulating layer 105 of the display substrate is located on the side of the auxiliary insulating layer 104 that is away from the base substrate 1, the edge of the interlayer insulating layer 105 is located in the non-light-emitting region 12, and a part of the first sub-conductive layer 901 covers the interlayer insulating layer 105. The first region TP1 is located within the orthogonal projection of the interlayer insulating layer 105 onto the base substrate 1, i.e., the edge portion of the second laminated layer 912 contacts the first sub-conductive layer 901 at the interlayer insulating layer 105, thereby utilizing the thickness of the interlayer insulating layer 105 to reduce the step in the direction of the base substrate 1 between the second laminated layer 912 (which forms a continuous integral structure with the common electrode 24) located on the pixel defining layer 6 and the first sub-conductive layer 901, and prevent the second laminated layer 912 from breaking, thereby ensuring the reliability of the connection between the second laminated layer 912 and the first sub-conductive layer 901 in the first region TP1.

[0194] 11B, the second region TP2 is located on the side away from the display region 11 in the orthogonal projection of the interlayer insulating layer 105 onto the base substrate 1. The transition of layers such as the fifth lamination layer 915 reduces the step between the first sub-conductive layer 901 and the eighth lamination layer 918, eliminating the need to extend the thicker interlayer insulating layer 105 through the first auxiliary via V001, thereby avoiding the effect of the thicker interlayer insulating layer 105 on the connection of each layer at the first auxiliary via V001.

[0195] 11B configures one auxiliary unit, and the display unit P includes a plurality of auxiliary units. The auxiliary units are arranged spaced apart from each other in the second direction D2.

[0196] For example, a plurality of auxiliary units arranged at intervals in the second direction D2 are all located in the non-light emitting region 12 and have the same or different distances to the display region 11 in the first direction D1.

[0197] For example, the multiple auxiliary units include a first auxiliary unit H1 and a second auxiliary unit H2, and the first auxiliary unit H1 and the second auxiliary unit H2 have similar specific structures and are both the auxiliary units shown in FIG. 11B above, but have different specific installation positions.

[0198] For example, as shown in FIG. 3A, the multiple auxiliary units include a first auxiliary unit H1 and a second auxiliary unit H2, where the first auxiliary unit H1 and the second auxiliary unit H2 are both located in the non-light-emitting area 12 and have different distances to the display area 11 in the first direction D1.

[0199] 12A is a partial schematic plan view of the second auxiliary unit H2 of the display unit shown in FIG. 3A, and FIG. 12B is a schematic cross-sectional view taken along line FF' in FIG. 12A.

[0200] The second auxiliary unit H2 is different from the first auxiliary unit H1 as follows: As shown in Figures 12A and 12B, the distance between the first auxiliary via V002 of the second auxiliary unit H2 and the display area 11 in the first direction D1 is greater than the distance between the first auxiliary via V001 of the first auxiliary unit H1 and the display area 11 in the first direction D1, that is, combining Figures 3A, 12A, and 12B, the distance between the edge of the first auxiliary via V002 of the second auxiliary unit H2 close to the display area 11 and the edge of the second power line vss close to the non-light-emitting area 12B is greater than the distance between the edge of the first auxiliary via V001 of the first auxiliary unit H1 close to the display area 11 and the edge of the second power line vss close to the non-light-emitting area 12B. As a result, by offsetting the second auxiliary unit H2 and the first auxiliary unit H1 in the second direction D2, it is more advantageous to utilize limited space; particularly in a high PPI (Pixels Per Inch) display substrate, when the area of ​​each display unit is small and multiple auxiliary units need to be installed using the limited area, by offsetting the second auxiliary unit H2 and the first auxiliary unit H1 in the second direction D2, the multiple auxiliary units can better adapt to the nearby circuit arrangement situation.

[0201] 5G and 12A, the first auxiliary via V002 of the second auxiliary unit H2 has a trapezoidal planar shape, which increases the contact area between the first conductive sub-layer 901 and the lateral portion 821. Of course, the first auxiliary via V002 may be a circular hole, a rectangular hole, or the like.

[0202] For example, as shown in Figures 12A and 12B, the length of the horizontal portion 821 of the second auxiliary unit H2 in the first direction D1 is greater than the length of the horizontal portion 821 of the first auxiliary unit H1 in the first direction D1, thereby enabling the via of the second auxiliary unit H2 to be positioned away from the display area 22.

[0203] For example, one display unit P includes at least three first auxiliary units H1, the number of second auxiliary units H2 is equal to or greater than one, and at least one second auxiliary unit H2 is located between at least three first auxiliary units H1 in the second direction D2. For example, as shown in FIG. 3A, one display unit P has three first auxiliary units H1 and one second auxiliary unit H2, and the one second auxiliary unit H2 is located between three first auxiliary units H1. Of course, in other embodiments, the number of first auxiliary units H1 and second auxiliary units H2 in each display unit may be designed by determining the need to reduce the resistance of the original common electrode according to the size of the display substrate. The present disclosure does not limit the number of first auxiliary units H1 and second auxiliary units H2.

[0204] Table 1 below is a relationship table between one auxiliary unit and the common electrode voltage drop, and shows the effect of installing one auxiliary unit on the common electrode voltage drop.

[0205] Relationship table between one auxiliary unit and common electrode voltage drop [Table 1]

[0206] For example, as shown in FIG. 12B, the first lamination layer 911 of the first lamination part 91a of the second auxiliary unit H2 includes an intermediate via SP, and the second lamination layer 912 of the first lamination part 91a is electrically connected to the first sub-conductive layer 901 of the second auxiliary unit H2 through the intermediate via SP. That is, as shown in FIG. 12B, the first lamination layer 911 of the first lamination part 91a of the second auxiliary unit H2 includes a first portion 911a close to the display area 11 and a second portion 911b away from the display area 11, and between the first portion 911a of the first lamination layer 911 and the second portion 911b of the first lamination layer 911, there is an intermediate via SP exposing the first sub-conductive layer 901 of the second auxiliary unit H2, thereby at least partially blocking the first portion 911a of the first lamination layer 911 and the second portion 911b of the first lamination layer 911. The second lamination layer 912 of the first lamination portion 91a is electrically connected to the first sub-conductive layer 901 of the second auxiliary unit H2 through the intermediate via SP, thereby further increasing the contact area between the first sub-conductive layer 901 and the second lamination layer 912 and realizing the electrical connection between the common electrode 24 and the first sub-conductive layer 901 in the first region TP1 and the second region TP2. In addition, the intermediate via SP realizing the electrical connection between the common electrode 24 and the first sub-conductive layer 901, and further ensuring the reliability of the electrical connection between the common electrode 24 and the first sub-conductive layer 901, thereby ensuring the parallel connection between the first auxiliary electrode 91 and the common electrode 24 of the second auxiliary unit H2 and reducing the resistance of the original common electrode 24. In addition, the distance in the first direction D1 between the first auxiliary via V002 of the second auxiliary unit H2 and the display area 11 is greater than the distance in the first direction D1 between the first auxiliary via V001 of the first auxiliary unit H1 and the display area 11, and the length in the first direction D1 of the horizontal portion 821 of the second auxiliary unit H2 is greater than the length in the first direction D1 of the horizontal portion 821 of the first auxiliary unit H1, so that the design provides sufficient space for the installation of the intermediate via SP.

[0207] For example, the intermediate via SP in FIG. 12B can be realized by a laser drilling method, i.e., using a laser to punch out the first laminate layer 911, thereby exposing the first sub-conductive layer 901, and the distance in the first direction D1 between the first auxiliary via V002 of the second auxiliary unit H2 and the display area 11 is large, providing enough space for the laser drilling method to avoid the wiring being too crowded and destroying other structures near the intermediate via SP.

[0208] For example, the distance in the first direction D1 between the first auxiliary via V002 of the second auxiliary unit H2 and the display area 11 is at least twice the distance in the first direction D1 between the first auxiliary via V001 of the first auxiliary unit H1 and the display area 11, thereby providing enough space for the installation of the intermediate via SP, providing enough space for laser drilling, and avoiding the wiring being too crowded and destroying other structures near the intermediate via SP.

[0209] Other structures of the second auxiliary unit H2 shown in FIG. 12B, such as the second laminate layer 912, which is connected to the common electrode 24, and the first laminate layer 911, the third laminate layer 913, ..., the eighth laminate layer 918, etc., are all similar to those shown in FIG. 11B, and therefore the description in FIG. 11B may be referred to and will not be repeated here.

[0210] For example, the area of ​​the planar shape of the first auxiliary via V001 of the second auxiliary unit H2 is larger than the area of ​​the planar shape of the first auxiliary via V001 of the first auxiliary unit H1, i.e., the area of ​​the orthogonal projection of the first auxiliary via V001 of the second auxiliary unit H2 onto the base substrate 1 is larger than the area of ​​the orthogonal projection of the first auxiliary via V001 of the first auxiliary unit H1 onto the base substrate 1. Since the second auxiliary unit H2 is far from the display region 11 and the horizontal portion 821 of the second auxiliary unit is long and has a large resistance, the area of ​​the first auxiliary via V001 of the second auxiliary unit H2 is large, and the resistance of the entire structure formed by connecting the first auxiliary electrode 91 to the horizontal portion 821 via the first auxiliary via V001 of the second auxiliary unit H2 is reduced, thereby reducing the resistance of the entire second auxiliary unit H2.

[0211] For example, one display unit P includes at least two first auxiliary units H1, and the number of second auxiliary units H2 is equal to or greater than 1, thereby more effectively reducing the resistance of the original common electrode. For example, one display unit P includes at least three first auxiliary units H1, and at least one second auxiliary unit H2 is located between at least three first auxiliary units H1 in the second direction D2, so that the positions of the auxiliary units with different distances to the display area 11 in one display unit P are reasonably arranged, making full use of the limited space, and more effectively reducing the resistance of the original common electrode.

[0212] 3A, in one display unit P, at least two first auxiliary units H1 include a first auxiliary unit H1, a second auxiliary unit H1, and a third auxiliary unit H1, where the first auxiliary unit H1 and the second auxiliary unit H1 are located in the second sub-pixel P2, and the third auxiliary unit and the second auxiliary unit H2 are located in the fourth sub-pixel P4. In this way, the auxiliary units are arranged along the entire display unit P in the second direction D2, and the resistance of the original common electrode is reduced in a balanced manner at each position, thereby improving the display uniformity of the display substrate.

[0213] For example, as shown in FIG. 3A , the first first auxiliary unit H1 and the second first auxiliary unit H1 are respectively located on both sides of the connection portion 30 of the second sub-pixel P2 that face each other in the second direction D2, and the third first auxiliary unit H1 and the second auxiliary unit H2 are located on both sides of the connection portion 30 of the fourth sub-pixel P4 that face each other in the second direction D2, thereby coordinating with the position of the connection portion 30 and making full use of the blank areas at both sides of the connection portion 30 that face each other in the second direction D2, and providing as many first auxiliary units H1 as possible.

[0214] For example, as shown in FIG. 3A, in the second direction D2, the second auxiliary unit H2 may be located on a side of the connection portion 30 of the fourth subpixel P4 that is closer to the boundary between the fourth subpixel P4 and the second subpixel P2, or in other embodiments, the second auxiliary unit H2 may be located on a side of the connection portion 30 of the fourth subpixel P4 that is away from the boundary between the fourth subpixel P4 and the second subpixel P2.

[0215] 11B, 3A, 3C and 4A, the area of ​​the planar shape of the first auxiliary via V001 of the first auxiliary unit H1 is larger than the area of ​​the planar shape of the first via V0. Since the structure installed in the first auxiliary via V001 of the first auxiliary unit H1 is complicated and used to reduce resistance, the area of ​​the first auxiliary via V001 of the first auxiliary unit H1 is larger than the area of ​​a general via, for example, the first via V0, which is advantageous in sufficiently ensuring the reliability of the first auxiliary electrode 91 being connected to the horizontal portion 821 through the first auxiliary via V001 of the second auxiliary unit H2.

[0216] 13A is a partial schematic plan view of the third auxiliary unit H3 of the display unit shown in FIG. 3A, and FIG. 13B is a schematic cross-sectional view taken along line GG' in FIG. 13A.

[0217] 3A and 13A-13B, for example, the display unit P further includes a second auxiliary electrode 92 located in the display area 11 and electrically connected to the common electrode 24, the auxiliary insulating layer 104 further includes a second auxiliary via V003 located in the display area 11 and exposing at least a portion of the vertical portion 81 of the auxiliary electrode line 8, and the second auxiliary electrode 92 is connected to the vertical portion 81 of the auxiliary electrode line 8 through the second auxiliary via V003. That is, by utilizing the second auxiliary via V003, the vertical portion 81 of the auxiliary electrode line 8 is connected to the common electrode 24 through the second auxiliary electrode 92. In this way, by installing the first auxiliary via V001 and the first auxiliary electrode 91 in the non-light-emitting area 12, and also installing the second auxiliary via V003 and the second auxiliary electrode 92 in the display area 11, the second auxiliary electrode 92 and the common electrode 2 are connected in parallel, further reducing the resistance of the original common electrode 24; and the auxiliary insulating layer 104 is the existing fourth insulating layer 104 in the display area 11. Installing the second auxiliary via V003 is advantageous in that it utilizes limited space to install the second auxiliary electrode 92 without occupying any further area of ​​the display area 11.

[0218] 13B, the orthogonal projection of the first sub-conductive layer 901 onto the base substrate 1 is located within the orthogonal projection of the vertical portion 81 of the auxiliary electrode line 8 onto the base substrate 1. Thus, providing the first sub-conductive layer 901 does not occupy any additional area of ​​the display region 11, which is more advantageous in saving space; particularly for a high PPI (Pixels Per Inch) display substrate, the area of ​​each display unit is small, and it is particularly important to provide the second auxiliary electrode 92 using the limited space.

[0219] 13B, the second auxiliary electrode 92 includes a second sub-conductive layer 902, a first laminated portion 92a, and a second laminated portion 92b. The second sub-conductive layer 902 is connected to the vertical portion 81 of the auxiliary electrode line 8 through a second auxiliary via V003, the first laminated portion 92a is electrically connected to the second sub-conductive layer 902 of the second auxiliary electrode 92 and laminated in a direction perpendicular to the base substrate 1, and includes a first laminated layer 921 and a second laminated layer 922 located on the side of the second sub-conductive layer 902 of the second auxiliary electrode 92 that is away from the base substrate 1 and laminated on each other in a direction perpendicular to the base substrate 1. The second laminated layer 922 of the second auxiliary electrode 92 is located on the side of the first laminated layer of the second auxiliary electrode 92 that is away from the base substrate 1 and is connected to the common electrode 24. The second laminated portion 92b includes a third laminated layer 923 and a fourth laminated layer 924 that are laminated with the second sub-conductive layer 902 of the second auxiliary electrode 92 in a direction perpendicular to the base substrate 1, are located on the side of the second sub-conductive layer 902 of the second auxiliary electrode 92 that is away from the base substrate 1, are located on the side of the first laminated portion 92a of the second auxiliary electrode 92 that is away from the display region 11, are electrically connected to the first laminated portion 92a of the second auxiliary electrode 92 via the second sub-conductive layer 902, and are laminated with each other in a direction perpendicular to the base substrate 1. The third laminated layer 923 of the second auxiliary electrode 92 and the first laminated layer 921 of the second auxiliary electrode 92 are made of the same material, are disposed in the same layer, and are spaced apart from each other in a direction parallel to the base substrate 1, and the fourth laminated layer 924 of the second auxiliary electrode 92 and the second laminated layer 922 are made of the same material, are disposed in the same layer, and are spaced apart from each other in a direction parallel to the base substrate 1.

[0220] For example, referring to Fig. 13B, the third lamination layer 923 and the first lamination layer 921 are formed by the same process. The same process may be a patterning process, for example, using a deposition mask plate to perform deposition to form the third lamination layer 923 and the first lamination layer 921, or the patterning process may include, for example, using a mask plate to perform processes such as exposure, development, and etching. Or, the same process may not include a patterning process, for example, by only including a deposition or deposition process, so that the third lamination layer 923 and the first lamination layer 921 are naturally isolated (to be described below), thereby simplifying the manufacturing process of the display substrate.

[0221] Similarly, referring to FIG. 13B, the fourth lamination layer 924 and the second lamination layer 922 are formed by the same process. The same process may be a patterning process, for example, using a deposition mask plate to perform deposition to form the fourth lamination layer 924 and the second lamination layer 922, or the patterning process may include, for example, using a mask plate to perform processes such as exposure, development, and etching. Or, the same process may not include a patterning process, for example, by only including a deposition or deposition process, so that the fourth lamination layer 924 and the second lamination layer 922 are naturally isolated (described below), thereby simplifying the manufacturing process of the display substrate.

[0222] 13B, the second laminated layer 922 of the second auxiliary electrode 92 is connected to the common electrode 24 and directly contacts the second sub-conductive layer 902 of the second auxiliary electrode 92. For example, the second laminated layer 922 and the first sub-conductive layer 901 contact each other in the first region TP1. For example, the first laminated layer 921 of the second auxiliary electrode 92 contacts the first sub-conductive layer 901, and the second laminated layer 922 of the second auxiliary electrode 92 includes an upper portion covering the upper surface of the first laminated layer 921 of the second auxiliary electrode 92 that is away from the base substrate 1 and a side portion covering the side surface of the first laminated layer 921 of the second auxiliary electrode 92 that intersects with the upper surface, and the side portion of the second auxiliary electrode 92 contacts the second sub-conductive layer 902. That is, the first region TP1 is located at the edge close to the second stacking portion 92b of the second stacking layer 922, the side of the second stacking layer 922 is the edge portion close to the second stacking portion 92b of the second stacking layer 922 (the portion of the second stacking layer 922 located in the first region TP1), and the edge portion of the second stacking layer 922 is in direct contact with the second sub-conductive layer 902.

[0223] For example, as shown in FIG. 13B, the second laminate layer 922 covers the top surface of the first laminate layer 921 facing away from the base substrate 1 and the side surface that intersects with the top surface, and the edge portion of the second laminate layer 922 near the second laminate portion 92b covers at least the side surface of the first laminate layer 921, i.e., by covering the edge of the first laminate layer 921 near the second laminate portion 92b, the edge portion of the second laminate layer 922 near the second laminate portion 92b can directly contact the second sub-conductive layer 902.

[0224] For example, as shown in FIG. 13B, the second lamination unit 92b further includes a fifth lamination layer 925 and a sixth lamination layer 926. The fifth lamination layer 925 is located between the second sub-conductive layer 902 and the third lamination layer 923, and the sixth lamination layer 926 is located between the fifth lamination layer 925 and the third lamination layer 923, and the fifth lamination layer 925 and the sixth lamination layer 926 are stacked with the second sub-conductive layer 902, the third lamination layer 923 and the fourth lamination layer 924 in a direction perpendicular to the base substrate 1 and are electrically connected to each other, and the fifth lamination layer 925 and the sixth lamination layer 926 are all separated from the first lamination layer 921 and the second lamination layer 922 in a direction parallel to the base substrate 1, i.e., the third lamination layer 923, the fourth lamination layer 924, the fifth lamination layer 925 and the sixth lamination layer 926 are all separated from the first lamination layer 921 and the second lamination layer 922 in a direction parallel to the base substrate 1. For example, the orthogonal projection of the sixth stacked layer 926 onto the base substrate 1 includes a middle region CR and an edge region PR surrounding the middle region CR, and the orthogonal projection of the fifth stacked layer 925 onto the base substrate 1 does not overlap the edge region PR but overlaps the middle region CR. At least a part of the orthogonal projection of the first region TP1 onto the base substrate 1 is located within the orthogonal projection of the edge region PR onto the base substrate 1. In this way, by stacking multiple conductive layers to form the second stacked portion 92b, it is more advantageous to better reduce the resistance of the original common electrode. For example, while combining with FIG. 4A, the light-emitting device 20 includes the above-mentioned first electrode 2 and light-emitting layer 23 located in the display region 11, the light-emitting layer 23 is sandwiched between the first electrode 2 and the common electrode 24, and the first electrode 2 includes a first sub-electrode layer 2a, a second sub-electrode layer 2b and a third sub-electrode layer 2c stacked in order along a direction perpendicular to the base substrate 1 and away from the base substrate 1.For example, the second sub-conductive layer 902 and the first sub-electrode layer 2a of the first auxiliary electrode 92 are made of the same material and are disposed in the same layer, the first laminate layer 921 and the light-emitting layer 23 form a continuous integral structure, the second laminate layer 922 and the common electrode 24 form a continuous integral structure, the third laminate layer 923 and the light-emitting layer 23 are made of the same material and are disposed in the same layer, the fourth laminate layer 924, the second laminate layer 922 and the common electrode 24 are made of the same material and are disposed in the same layer, the fifth laminate layer 925 and the second sub-electrode layer 2b are made of the same material and are disposed in the same layer, and the sixth laminate layer 926 and the third sub-electrode layer 2c are made of the same material and are disposed in the same layer. In this way, the second sub-conductive layer 902 and the first sub-electrode layer 2a of the first auxiliary electrode 92 can be formed by the same process, the first laminated layer 921, the light-emitting layer 23, and the third laminated layer 923 can be formed by the same process, the fourth laminated layer 924, the second laminated layer 922, and the common electrode 24 can be formed by the same process, the fifth laminated layer 925 and the second sub-electrode layer 2b can be formed by the same process, and the sixth laminated layer 926 and the third sub-electrode layer 2c can be formed by the same process. The "same process" here can refer to the above interpretation. In this way, the layer structures of the first auxiliary electrode 92 can be formed by adopting processes corresponding to the above functional layers in the display area 11, and there is no need to add a film layer manufacturing process or patterning process to install the first auxiliary electrode 92.

[0225] For example, in the manufacturing process of the display substrate shown in FIG. 13B, for example, the fifth stacking layer 925 and the sixth stacking layer 926 can be formed by the same patterning process using the same mask, for example, by adopting an etching process, such as a wet etching process, thereby simplifying the manufacturing process of the display substrate; and the materials of the fifth stacking layer 925 and the sixth stacking layer 926 are different, and the materials of the fifth stacking layer 925 and the sixth stacking layer 926 are the same as the materials of the second sub-electrode layer 2b and the third sub-electrode layer 2c, respectively, and reference can be made to the previous description of the materials of the second sub-electrode layer 2b and the third sub-electrode layer 2c, thereby forming a fifth stacking layer 925 that is shrunk inward more than the sixth stacking layer 926 shown in FIG. 13B, that is, the orthogonal projection of the fifth stacking layer 925 onto the base substrate 1 does not overlap with the edge region PR, but overlaps with the middle region CR. After forming the fifth stacking layer 925 and the sixth stacking layer 926, steps of forming the first stacking layer 921, the light-emitting layer 23 and the third stacking layer 923, and steps of forming the fourth stacking layer 924 and the second stacking layer 922 are carried out in sequence.

[0226] In the process of forming the first lamination layer 921, the light emitting layer 23, and the third lamination layer 923 on the side of the sixth lamination layer 926 away from the base substrate 1, for example, a deposition method is adopted to form the first lamination layer 921, the light emitting layer 23, and the third lamination layer 923, and the first lamination layer 921 and the light emitting layer 23 can be formed as an integral structure. Due to the existence of the fifth lamination layer 925 and the sixth lamination layer 926, the fifth lamination layer 925 and the sixth lamination layer 926 have a certain thickness, and there is a step between the upper surface of the sixth lamination layer 926 away from the base substrate 1 and the upper surface of the second sub-conductive layer 902 away from the base substrate 1, and the third lamination layer 923 and the first lamination layer 921 are mutually isolated by the step. And there is a step between the upper surface of the third lamination layer 923 away from the base substrate 1 and the upper surface of the first lamination layer 921 away from the base substrate 1.

[0227] Subsequently, in the process of forming the fourth lamination layer 924, the second lamination layer 922, and the common electrode 24, the fourth lamination layer 924, the second lamination layer 922, and the common electrode 24 are formed by, for example, a deposition method, and the second lamination layer 922 and the common electrode 24 can be formed as an integral structure. Due to the step between the upper surface of the third lamination layer 923 that is away from the base substrate 1 and the upper surface of the first lamination layer 921 that is away from the base substrate 1, the fourth lamination layer 924 and the second lamination layer Since the layers 922 and 923 are mutually isolated, and the fifth laminate layer 925 is shrunk inward more than the sixth laminate layer 926, i.e., the orthogonal projection of the fifth laminate layer 925 onto the base substrate 1 does not overlap with the edge region PR but overlaps with the middle region CR, the second laminate layer 922 and the second sub-conductive layer 902 can be brought into contact in the first region TP1, and at least a portion of the orthogonal projection of the first region TP1 onto the base substrate 1 is located within the orthogonal projection of the edge region PR onto the base substrate 1.

[0228] In this way, the common electrode 24 and the second conductive sub-layer 902 are connected, thereby connecting the first auxiliary electrode 92 and the common electrode 24 in parallel, and the resistance of the original common electrode 24 can be reduced.

[0229] For example, as shown in FIG. 13B, when the sum of the thickness of the fifth laminate layer 925 in the direction perpendicular to the base substrate 1 and the thickness of the sixth laminate layer 926 in the direction perpendicular to the base substrate 1 is 6000 Å or more, the fifth laminate layer 925 has a sufficient thickness, thereby forming a sufficient step between the upper surface of the sixth laminate layer 926 facing away from the base substrate 1 and the upper surface of the second sub-conductive layer 902 facing away from the base substrate 1, and further ensuring reliability in that the third laminate layer 923 and the first laminate layer 921 are mutually isolated by the step, and reliability in that the fourth laminate layer 924 and the second laminate layer 922 are mutually isolated.

[0230] 13B, the first auxiliary electrode 92 further includes a third laminated portion 92c. The third laminated portion 92c includes a seventh laminated layer 927 and an eighth laminated layer 928 that are laminated with the second sub-conductive layer 902 in a direction perpendicular to the base substrate 1, are located on the side of the second sub-conductive layer 902 that is away from the base substrate 1, are electrically connected to the first laminated portion 92a and the second laminated portion 92b via the second sub-conductive layer 902, and are laminated with each other in a direction perpendicular to the base substrate 1, the seventh laminated layer 927 and the third laminated layer 923 are disposed in the same layer and are spaced apart from each other in a direction parallel to the base substrate 1, and the eighth laminated layer 928 and the fourth laminated layer 924 are disposed in the same layer and are spaced apart from each other in a direction parallel to the base substrate 1.

[0231] For example, the eighth lamination layer 928 and the second conductive sub-layer 902 are in direct contact with each other. Second conductive sub-layer 902 are in contact with each other in the second region TP2, and at least a part of the orthogonal projection of the second region TP2 onto the base substrate 1 is located within the orthogonal projection of the edge region PR onto the base substrate 1. Similar to the situation in the first region TP1, the eighth stacked layer 928 covers the top surface of the seventh stacked layer 927 that faces away from the base substrate 1 and the side surface that intersects with the top surface, and the edge portion of the eighth stacked layer 928 close to the second stacked portion 92b covers at least the side surface of the seventh stacked layer 927, i.e., covers the edge of the seventh stacked layer 927 close to the second stacked portion 92b, so that the edge portion of the eighth stacked layer 928 close to the second stacked portion 92b can directly contact the second sub-conductive layer 902.

[0232] For example, the seventh stacking layer 927, the third stacking layer 923, and the light emitting layer 23 are made of the same material and are disposed in the same layer, and the eighth stacking layer 928, the fourth stacking layer 924, and the second stacking layer 922 are made of the same material and are disposed in the same layer. In this way, the seventh stacking layer 927, the third stacking layer 923, and the light emitting layer 23 are formed by the same process, and the eighth stacking layer 928 and the fourth stacking layer 924 are formed by the same process. The above interpretation may be referred to for the "same process" here. As with the formation of the structure in the first region TP1, in the process of forming the seventh stacking layer 927, the third stacking layer 923, and the light-emitting layer 23 using the same process, the seventh stacking layer 927 and the third stacking layer 923 can be separated by a step formed using the fifth stacking layer 925 and the sixth stacking layer 926, and in the process of forming the eighth stacking layer 928, the fourth stacking layer 924, and the second stacking layer 922 using the same process, the eighth stacking layer 928 and the fourth stacking layer 924 are separated.

[0233] 13B and 5H, for example, the interlayer insulating layer 105 is the fifth insulating layer 105, that is, the interlayer insulating layer 105 and the fifth insulating layer 105 are disposed in the same layer and are made of the same material. The fifth insulating layer 105 has a third auxiliary via V004, and the orthogonal projection of the third auxiliary via V004 onto the base substrate 1 is located within the orthogonal projection of the vertical portion 81 of the auxiliary electrode line 8 onto the base substrate 1. The second auxiliary via V003 of the second auxiliary unit H2 communicates with the third auxiliary via V004, and the second auxiliary via V003 is exposed from the third auxiliary via V004. For example, a portion of the first laminate portion 92a of the second auxiliary unit H2 is located within the third auxiliary via V004, the first region TP1 is located within the third auxiliary via V004, the second laminate portion 92b of the second auxiliary unit H2 is located within the third auxiliary via V004, a portion of the third laminate portion 92c of the second auxiliary unit H2 is located within the third auxiliary via V004, at least a portion of the second sub-conductive layer 902 is located within the third auxiliary via V004, and the second region TP2 is located within the third auxiliary via V004.

[0234] Figure 14A is a schematic diagram of layers including a pixel defining layer and a portion of the first electrode of the display unit P shown in Figure 3A, Figure 14B is an enlarged schematic diagram of portion P0 shown in the dashed box in Figure 14A, and the layers included in Figure 14B are more than those in Figure 14A and include the layers in Figure 3A.

[0235] 14A-14B and 5K, the pixel definition layer 6 defines an aperture region 60, which includes a plurality of pixel apertures located in the display region 111, and the plurality of pixel apertures correspond to a plurality of sub-pixels, respectively, and are aperture regions of the plurality of sub-pixels. For example, in each of the plurality of sub-pixels, the orthogonal projection of the pixel aperture onto the base substrate 1 is located within the orthogonal projection of the first electrode 2 onto the base substrate 1. Two adjacent sub-pixels among the plurality of sub-pixels of the display unit P are an upper sub-pixel and a lower sub-pixel, respectively, and a direction perpendicular to the arrangement direction of the upper sub-pixel and the lower sub-pixel is a reference direction. For example, the reference direction is the first direction D1, and the arrangement direction of the upper sub-pixel and the lower sub-pixel is the second direction D2. Hereinafter, an example will be described in which the first sub-pixel P1 is an upper sub-pixel and the third sub-pixel P3 is a lower sub-pixel. In this embodiment, the second sub-pixel P2 may be an upper sub-electrode, and the fourth sub-pixel P4 may be a lower sub-electrode. Alternatively, in some other embodiments, the upper and lower subpixels may be aligned along the first direction D1, or along any direction, and the embodiments of the present disclosure do not limit the positions and alignment directions of the upper and lower subpixels.

[0236] 14A-14B, the first electrode 2 of the first subpixel P1 has a first edge u21a close to the third subpixel P3 and a second edge u21b that intersects with the first edge u21a and is located on a first side of the first edge u21a in the first direction D1, and the opening region of the first subpixel P1 has a first edge u61a close to the third subpixel P3 and a second edge u61b that intersects with the first edge u61a and is located on a first side of the first edge u61a in the first direction D1. The distance between the first edge u21a of the first electrode 2 of the first subpixel P1 and the first edge u61a of the aperture region of the first subpixel P1 is a first distance d1, and the distance between the second edge u21b of the first electrode 2 of the first subpixel P1 and the second edge u61b of the aperture region of the first subpixel P1 is a second distance d2, the first distance d1 is larger than the second distance d2, and in the first subpixel P1, the first edge u21a of the first electrode 2 extends beyond the corresponding edge of the aperture region of the subpixel in the arrangement direction of the two adjacent subpixels more than the first direction D1, For example, the first subpixel P1 and the third subpixel P3, This ensures that the first electrode 2 of the first subpixel P1 can cover a larger area in the boundary region between the first subpixel P1 and the third subpixel P3 in the second direction D2, so that when a transistor of the pixel circuit is installed in the boundary region between the first subpixel P1 and the third subpixel P3 (e.g., at least a portion of the detection transistor T3 of the first subpixel P1 is located in the boundary region), the portion of the first electrode 2 of the first subpixel P1 close to the boundary region between the first subpixel P1 and the third subpixel P3 can sufficiently cover at least a portion of the channel region of the transistor located in the boundary region, preventing the light-irradiated channel region from affecting the performance of the transistor.

[0237] For example, the first interval d1 is an average interval in the first direction D1, and for example, the first edge u21a of the first electrode 2 of the first subpixel P1 and the first edge u61a of the aperture region 60 of the first subpixel P1 are substantially parallel, and the second edge u21b of the first electrode 2 of the first subpixel P1 and the second edge u61b of the aperture region 60 of the first subpixel P1 are substantially parallel. Being substantially parallel is not limited to being completely parallel. In the present disclosure, the edges of the first electrode of each subpixel and the edges of the aperture region of each subpixel are not limited to being straight lines, and these edges may also include curved portions, and it is sufficient that each position along the first direction D1 satisfies the above distance relationship.

[0238] For example, referring to Figures 14A-14B, in each subpixel of the multiple subpixels, the first electrode 2 includes a first portion 21 and a second portion 22 arranged in the second direction D2 and spaced apart from each other, the first portion 21 of the first electrode 2 and the second portion 22 of the first electrode 2 are connected to a first pole of the driving transistor, the aperture area of ​​the subpixel includes a first subopening 601 and a second subopening 602, the first portion 21 of the first electrode 2 covers the first subopening 601, and the second portion 22 of the first electrode 2 covers the second subopening 602.

[0239] The non-emissive region 12A and the display region 11 are arranged in the first direction D1 and are adjacent to the first subpixel P1 and the third subpixel P3. Here, an edge of the first portion 21 of the first electrode 2 of the first subpixel P1 that is close to the third subpixel P3 is defined as a first edge u21a of the first electrode 2 of the first subpixel P1, an edge of the first portion 21 of the first electrode 2 of the first subpixel P1 that intersects with the first edge u21a and is close to the non-emissive region 12A is defined as a second edge u21b of the first electrode 2 of the first subpixel P1, an edge of the first sub-opening 601 of the first subpixel P1 that is close to the third subpixel P3 is defined as a first edge u61a of the first sub-opening 601 of the first subpixel P1, and an edge of the first sub-opening 601 of the first subpixel P1 that is close to the non-emissive region 12A is defined as a second edge u61b of the opening region 60 of the first subpixel P1.

[0240] For example, referring to Figures 14A-14B, in the first pixel P1, the orthogonal projection of the channel region T3a of the detection transistor T3 onto the base substrate 1 is located within the orthogonal projection of the first electrode 2 onto the base substrate 1, for example, within the orthogonal projection of the first portion 21 of the first electrode 2 onto the base substrate 1, and the first edge u21a of the first electrode 2 of the first subpixel P1 is located on the side of the channel region C3 of the detection transistor T3 of the first subpixel P1 closer to the third subpixel P3 in the second direction D2, i.e., the first edge u21a of the first electrode 2 of the first pixel P1 is located outside the channel region C3 of the detection transistor T3 of the first pixel P1, sufficiently ensuring that the first electrode 2 of the first pixel P1 can cover at least a portion of the channel region C3 of the detection transistor T3 located in the boundary region between the first subpixel P1 and the third subpixel P3. In the third pixel P3, the first edge d21a of the first electrode 2 of the third subpixel P3 is located on the side of the channel region C3 of the detection transistor T3 of the third subpixel P3 closer to the first subpixel P1 in the second direction D2, i.e., the first edge d21a of the first electrode 2 of the third subpixel P3 is located outside the channel region C3 of the detection transistor T3 of the third subpixel P3, sufficiently ensuring that the first electrode 2 of the third pixel P3 can sufficiently cover at least a portion of the channel region C3 of the detection transistor T3 located in the boundary region between the first subpixel P1 and the third subpixel P3.

[0241] For example, the first pole T3s of the detection transistor T3 of the first subpixel P1 is 2nd poleThe first pole T3s of the detection transistor T3 of the third subpixel P3 is located on the side of the second pole T3d away from the third subpixel P3, and the first pole T3s of the detection transistor T3 of the third subpixel P3 is located on the side of the second pole away from the upper sub-electrode. In the second direction D2, the distance between the first pole T3s of the detection transistor T3 of the first subpixel P1 and the first pole T3s of the detection transistor T3 of the third subpixel P3 is smaller than the length of the aperture region of the first subpixel P1 in the second direction D2 and smaller than the length of the aperture region of the third subpixel P3 in the second direction D2, thereby ensuring that the detection transistor T3 is located near the boundary region between the first subpixel P1 and the third subpixel P3 and favoring a reduction in the distance between adjacent subpixels in the second direction D2, making the arrangement of the pixel array more compact and achieving a high PPI.

[0242] It should be explained that the length of the aperture region of the first subpixel P1 in the second direction D2 means the length of the first aperture region 601 of the first subpixel P1 in the second direction D2, and the length of the aperture region of the third subpixel P3 in the second direction D2 means the length of the first aperture region 601 of the third subpixel P3 in the second direction D2.

[0243] For example, in at least one embodiment, the distance between the first pole T3s of the detection transistor T3 of the first subpixel P1 and the first pole T3s of the detection transistor T3 of the third subpixel P3 is less than ½ the width of the aperture region 60, effectively reducing the distance between adjacent subpixels in the second direction D2, making the pixel array arrangement more compact and achieving a high PPI.

[0244] For example, referring to FIGS. 14A-14B and the previous FIG. 6A , the second sub-scanning signal line G2 includes an annular portion, i.e., a third outer ring portion R3. A portion of the third outer ring portion R3 overlapping with the active layer T3a of the detection transistor T3 of the first sub-pixel P1 in the direction perpendicular to the base substrate 1 and a portion of the third outer ring portion R3 overlapping with the active layer T3a of the detection transistor T3 of the third sub-pixel P3 in the direction perpendicular to the base substrate 1 constitute the gate of the detection transistor T3 of the first sub-pixel P1 and the gate of the detection transistor T3 of the third sub-pixel P3, respectively. The orthogonal projection of the third outer ring portion R3 onto the base substrate 1 constitutes an annular region. The orthogonal projections onto the base substrate 1 of the second pole T3d of the detection transistor T3 of the third sub-pixel P3 and the second pole T3d of the detection transistor T3 of the third sub-pixel P3 are both located within the annular region. By rationally utilizing the limited space to design the positional relationship between the first pole T3s and the second pole T3d of the two detection transistors T3 located at least partially within the third outer ring portion R3 and the boundary region, the channel region of the detection transistor T3 can be covered by the first electrode of the sub-pixel in which it is located, and a compact structure is realized, thereby improving the performance and PPI of the detection transistor T3.

[0245] For example, the first electrode 2 of the third subpixel P3 has a first edge d21a close to the first subpixel P1 and a second edge d21b intersecting the first edge d21a and close to the non-emitting region 12A, and the opening region of the third subpixel P3 has a first edge d61a close to the first subpixel P1 and a second edge d61b intersecting the first edge d61a and close to the non-emitting region 12A. The distance between the first edge d21a of the first electrode 2 of the third subpixel P3 and the first edge d61a of the aperture region of the third subpixel P3 is a third distance d3, and the distance between the second edge d21b of the first electrode 2 of the third subpixel P3 and the second edge d61b of the aperture region of the third subpixel P3 is a fourth distance d4. The third distance d3 is larger than the fourth distance d4. In the third subpixel P3, the first edge of the first electrode 2 exceeds the corresponding edge of the aperture region of the subpixel in the arrangement direction of two adjacent subpixels, for example, in the second direction D2, more than in the first direction D1. This ensures that the third first electrode 2 can cover a larger area in the boundary region between the first subpixel P1 and the third subpixel P3, so that when a transistor of the pixel circuit (e.g., the detection transistor T3 of the third subpixel P3) is installed in the boundary region between the first subpixel P1 and the third subpixel P3, the portion of the first electrode 2 of the third subpixel P3 that is close to the boundary region between the first subpixel P1 and the third subpixel P3 can fully cover the channel region of the transistor installed in the boundary region, preventing the light-irradiated channel region from affecting the performance of the transistor.

[0246] Here, the edge of the first portion 21 of the first electrode 2 of the third subpixel P3 that is close to the first subpixel P1 is referred to as the first edge d21a of the first electrode 2 of the third subpixel P3, the edge of the first portion 21 of the first electrode 2 of the third subpixel P3 that intersects with the first edge d21a and is close to the non-emitting region 12A is referred to as the second edge d21b of the first electrode 2 of the third subpixel P3, the edge of the first sub-opening 601 of the third subpixel P3 that is close to the first subpixel P1 is referred to as the first edge d61a of the opening region of the third subpixel P3, and the edge of the first sub-opening 601 of the third subpixel P3 that intersects with the first edge d61a and is close to the non-emitting region 12A is referred to as the second edge d61b of the opening region of the third subpixel P3.

[0247] 14B , the first electrode 2 of the first subpixel P1 further has a fourth edge u21d facing the second edge u21b thereof, and the aperture region of the first subpixel P1, e.g., the first sub-aperture 601, further has a fourth edge u61d facing the second edge u61b thereof. For example, in some embodiments, the first distance d1 is greater than the distance between the fourth edge u21d of the first electrode 2 of the first subpixel P1 and the fourth edge u61d of the aperture region of the first subpixel P1, thereby ensuring that at least a part of the channel region of the sensing transistor T3 located in the boundary region of the first subpixel P1 is covered and shielded by the first electrode. In some embodiments, the third subpixel P3 is similar, that is, the first electrode 2 of the third subpixel P1 further has a fourth edge d21d facing its second edge d21b, and the aperture region of the third subpixel P3, e.g., the first sub-aperture 601, further has a fourth edge d61d facing its second edge d61b. For example, in some embodiments, the third spacing d3 is greater than the distance between the fourth edge d21d of the first electrode 2 of the third subpixel P3 and the fourth edge d61d of the aperture region of the third subpixel P3, ensuring that at least a part of the channel region of the sensing transistor T3 located in the boundary region of the third subpixel P3 is covered and shielded by the first electrode.

[0248] For example, as shown in Figures 14B, 3A and 5E, in the first subpixel P1, the first pole T3s of the detection transistor T3 is electrically connected to the active layer T3a of the detection transistor T3 through the upper via V51, and in the third subpixel P3, the first pole T3s of the detection transistor T3 is electrically connected to the active layer T3a of the detection transistor T3 through the lower via V52. Combining Figures 14B and 4C, the orthogonal projection of the first edge u21a of the first electrode 2 of the first subpixel P1 onto the base substrate 1 at least partially overlaps with the orthogonal projection of the edge of the intermediate via V33 away from the third subpixel P3 in the second direction D2 onto the base substrate 1, i.e., the first electrode 2 of the first subpixel P1 extends along the second direction D2 to the edge of the intermediate via V33 away from the third subpixel P3 in the second direction D2. The orthogonal projection of the first edge d21a of the first electrode 2 of the third subpixel P3 onto the base substrate 1 at least partially overlaps with the orthogonal projection of the edge of the intermediate via V33 away from the first subpixel P1 in the second direction D2 onto the base substrate 1, i.e., the first electrode 2 of the third subpixel P3 extends along the second direction D2 to the edge of the intermediate via V33 away from the third subpixel P3 in the second direction D2. In this way, it is ensured that the first electrode 2 of the first subpixel P1 and the second electrode 2 of the third subpixel P3 each cover the channel region C3 of the detection transistor T3 located within the boundary region of the corresponding subpixel, and that there is a sufficient gap between the first electrode 2 of the first subpixel P1 and the second electrode 2 of the third subpixel P3, so that the edge of the first electrode and the edge of the via are aligned, which reduces the manufacturing difficulty and increases the manufacturing yield of the display substrate.

[0249] For example, as shown in FIG. 14B, the integrally molded electrode IAL spans the gap between the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3 along the second direction D2, and both ends of the integrally molded electrode IAL that are opposed to each other in the second direction D2 are respectively located on both sides in the second direction D2 of the gap between the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3.

[0250] 14B, 5B and 5E, as shown in FIG. 5A, the intermediate connection portion 43 is located on a side of the active layer T3a of the detection transistor T3 closer to the base substrate 1, for example, on the first conductive layer 100. Also, at least a part of the orthogonal projection of the intermediate connection portion 43 onto the base substrate 1 is located within the orthogonal projection onto the base substrate 1 of the interval between the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3, the detection signal line S is connected to the intermediate connection portion 43 via a first connection via V31, and the integrally molded active layer IAL is connected to the intermediate connection portion 43 via a second connection via V32. A first connection via V31 corresponding to the intermediate connection portion 43 is provided in the interval between the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3. V31 and the second connection via V32 and the first connection via V31, the second connection via V32 and the intermediate via V33 located in the boundary region between adjacent upper and lower sub-pixels in the pixel array are neatly arranged to align the edges of the first electrodes and the edges of the vias, thereby reducing manufacturing difficulty and increasing the manufacturing yield of the display substrate.

[0251] For example, as shown in FIG. 14B , the orthogonal projection onto the base substrate 1 of the first edge u21a of the first electrode 2 of the first subpixel P1, the orthogonal projection onto the base substrate 1 of the edge of the first connection via V31 that faces away from the third subpixel P3 in the second direction D2, and the orthogonal projection onto the base substrate 1 of the edge of the second connection via V32 that faces away from the third subpixel P3 in the second direction D2 all at least partially overlap, and the orthogonal projection onto the base substrate 1 of the first edge d21a of the first electrode 2 of the third subpixel P3 and First connecting via V31The orthogonal projection of the edge of the first connection via V31 away from the first subpixel P1 in the second direction D2 onto the base substrate 1 and the orthogonal projection of the edge of the second connection via V32 away from the first subpixel P1 both at least partially overlap, that is, the first electrode 2 of the first subpixel P1 extends along the second direction D2 to the edge of the first connection via V31 away from the lower subpixel, and to the edge of the second connection via V32 away from the lower subpixel. The first electrode 2 of the third subpixel P3 extends along the second direction D2 to the edge of the first connection via V31 away from the upper subpixel in the second direction D2, and to the edge of the second connection via V32 away from the upper subpixel in the second direction D2. In this way, the intermediate via V33, the first connection via V31, and the second connection via V32, which are located in the boundary region between adjacent upper and lower sub-pixels in the pixel array, can be neatly aligned, reducing manufacturing difficulty and increasing the manufacturing yield of the display substrate.

[0252] For example, as shown in FIG. 14B, the third interval d3 and the first interval d1 are both larger than the width of the interval in the second direction D2 between the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3. The width of the interval in the second direction D2 between the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3 is the interval between the first edge u21a of the first electrode 2 of the first subpixel P1 and the first edge d21a of the first electrode 2 of the third subpixel P3, and the interval is, for example, the average value of the distance between two of the positions along the first direction D1. This can ensure that the third interval d3 and the first interval d1 are sufficiently large, thereby ensuring that the first electrode 2 of the first subpixel P1 and the first electrode 2 of the third subpixel P3 can sufficiently cover the channel region C3 of the detection transistor T3 of the first subpixel P1 and the channel region C3 of the detection transistor T3 of the third subpixel P3, respectively.

[0253] For example, as shown in FIG. 14B, the first electrode 2 of the first subpixel P1 further has a third edge u22c away from the third subpixel P3, and the first sub-aperture 601 of the first subpixel P1 further has a third edge u62c away from the third subpixel P3, the distance between the third edge u22c of the first electrode 2 of the first subpixel P1 and the third edge u62c of the first sub-aperture 601 of the first subpixel P1 is a fifth interval d5, and the first interval d1 is greater than the fifth interval d5. In each subpixel, for example, the first subpixel P1, the orthogonal projections of the drive transistor T1 and the data write transistor T2 onto the base substrate 1 are located within the orthogonal projections of the aperture area of ​​the subpixel in which they are located onto the base substrate 1; for example, the orthogonal projections of the drive transistor T1 and the data write transistor T2 of the first subpixel P1 onto the base substrate 1 are located within the orthogonal projections of the second opening 602 and the first opening 601 of the first subpixel P1 onto the base substrate 1, and the orthogonal projections of the drive transistor T1 and the data write transistor T2 of the third subpixel P3 onto the base substrate 1 are located within the orthogonal projections of the second opening 602 and the first opening 601 of the third subpixel P3 onto the base substrate 1; and in the first subpixel P1, the distance between the channel region C1 of the drive transistor T1 and the third edge u62c of the second subopening 602 is greater than the distance between the channel region C3 of the detection transistor T3 and the first edge u61a of the first subopening 601. As a result, the channel region C1 of the driving transistor T1 is covered and shielded by the corresponding first electrode, and the first interval d1 is greater than the fifth interval d5, which further ensures that the channel region C3 of the detection transistor T3 of the first sub-pixel P1 is covered and shielded by the corresponding first electrode.

[0254] Here, the edge of the second part 22 of the first electrode 2 of the first subpixel P1 that faces away from the third subpixel P3 is defined as the third edge u22c of the first electrode 2 of the first subpixel P1, and the edge of the second sub-opening 602 of the first subpixel P1 that faces away from the third subpixel P3 is defined as the third edge u62c of the opening region of the first subpixel P1.

[0255] For example, the distance between the third edge of the first electrode 2 of the third subpixel P3, which is away from the first subpixel P1, and the third edge of the opening region 60 of the third subpixel P3, which is away from the first subpixel P1, is the sixth interval d6, and the third interval d3 is greater than the sixth interval d6. And, in the third subpixel P1, the distance between the channel region C1 of the driving transistor T1 and the third edge d62c of the second sub-opening 602 is greater than the distance between the channel region C3 of the detection transistor T3 and the first edge d61a of the first sub-opening 601. As a result, the channel region C1 of the driving transistor T1 is covered and shielded by the corresponding first electrode, and the third interval d3 is greater than the sixth interval d6, which further ensures that the channel region C3 of the detection transistor T3 of the third subpixel P3 is covered and shielded by the corresponding first electrode.

[0256] Here, the edge of the second part 22 of the first electrode 2 of the third subpixel P3 that faces away from the first subpixel P1 is defined as the third edge d22c of the first electrode 2 of the third subpixel P3, and the edge of the second sub-opening 602 of the third subpixel P3 that faces away from the first subpixel P1 is defined as the third edge d62c of the opening region of the third subpixel P3.

[0257] For example, combining FIG. 5C and FIG. 14B, the orthogonal projection of the data writing transistor T2 onto the base substrate 1 is also located within the orthogonal projection of the opening region onto the base substrate 1, whereby the orthogonal projection of the channel region C2 of the data writing transistor T2 onto the base substrate 1 is located within the orthogonal projection of the opening region onto the base substrate 1 and is covered and shielded by the first electrode. As a result, the orthogonal projection of the channel regions of all the transistors of the pixel circuit onto the base substrate is all located within the orthogonal projection of the first electrode of the subpixel in which it is located onto the base substrate. For example, combining FIG. 5C and FIG. 14B, in each subpixel of the plurality of subpixels, the orthogonal projection of the channel region C1 of the driving transistor T1 onto the base substrate 1 is located within the orthogonal projection of the second portion 22 of the first electrode 2 onto the base substrate 1. The orthogonal projection of the channel region C2 of the data writing transistor onto the base substrate 1 is located within the orthogonal projection of the first electrode of the subpixel in which it is located onto the base substrate. Shadow, located within the orthogonal projection of the first portion 21 of the first electrode 2 onto the base substrate 1, and located on the side of the orthogonal projection of the channel region C3 of the detection transistor T3 onto the base substrate 1 closer to the second portion 22 of the first electrode 2.

[0258] For example, at least a part of the orthogonal projection of the detection transistor T3 onto the base substrate 1 is located outside the orthogonal projection of the opening region onto the base substrate 1. For example, the orthogonal projection of at least a part of the second pole T3d of the detection transistor T3 onto the base substrate 1 is located outside the orthogonal projection of the opening region onto the base substrate 1. Located in With this design, the first electrode can meet the requirement of covering and shielding the channel regions of all the transistors in the pixel circuit of the subpixel in which it is located, without making the first electrode too large, thereby ensuring the spacing between the first electrode of the adjacent first subpixel P1 and the first electrode of the third subpixel P3, and allowing the part of the detection transistor T3 that does not need to be shielded to be located in the spacing between the first electrode of the adjacent first subpixel P1 and the first electrode of the third subpixel P3, making full use of the limited space and achieving high PPI.

[0259] For example, referring to FIGS. 14A-14B, the area of ​​the aperture region of the third subpixel P3 is larger than the area of ​​the aperture region 60 of the first subpixel P1, and the third interval d3 is larger than the first interval d1. For example, the area of ​​the first sub-opening 601 of the third sub-pixel P3 is larger than the area of ​​the first sub-opening 601 of the first sub-pixel P1, or the sum of the area of ​​the first sub-opening 601 and the area of ​​the second sub-opening 602 of the third sub-pixel P3 is larger than the sum of the area of ​​the first sub-opening 601 and the area of ​​the second sub-opening 602 of the first sub-pixel P1, for example, the first sub-pixel P1 emits red light and the third sub-pixel P3 emits white light, and the third distance d3 is larger than the first distance d1, thereby ensuring that the first electrodes of the adjacent first and third sub-pixels P1 and P3 can both shield the channel regions of the detection transistors located in the boundary region between the first and third sub-pixels P1 and P3.

[0260] It should be noted that in the above embodiment, the edges of the first electrode of a subpixel and the edges of the opening region of a subpixel are introduced by taking the case where the first electrode of a subpixel includes a first portion and a second portion spaced apart from each other as an example, but the embodiment of the present disclosure is not limited to this case. In other embodiments, the first electrode of a subpixel may be a complete whole, or may include more than two parts spaced apart from each other. In various cases, the first electrode is taken as a whole to determine its first edge, second edge, third edge and fourth edge.

[0261] At least one embodiment of the present disclosure further provides a display device 1000, which includes any one of the display substrates 10 according to the embodiments of the present disclosure, as shown in Fig. 15. The display device 1000 may be a device having a display function, such as an organic light emitting diode display device, a quantum dot light emitting diode display device, or other types of devices, but is not limited thereto in the embodiments of the present disclosure.

[0262] The structure, function, technical effects, etc. of the display device according to the embodiment of the present disclosure may be referred to the corresponding description of the display substrate 10 according to the embodiment of the present disclosure above, and will not be described further herein.

[0263] For example, the display device 1000 according to at least one embodiment of the present disclosure may be any product or component having a display function, such as a display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., and the embodiments of the present disclosure are not limited thereto.

[0264] The above are merely exemplary embodiments of the present disclosure, and are not intended to limit the protection scope of the present disclosure, which is determined based on the scope defined in the claims.

Claims

1. A display substrate, A base substrate; a display unit disposed on the base substrate, the display unit including a display area and a non-light-emitting area, the display area including a sub-pixel, the sub-pixel including a driving transistor and a light-emitting device, the driving transistor configured to control a magnitude of a driving current flowing through the light-emitting device, the light-emitting device configured to receive the driving current and be driven by the driving current to emit light; a scanning signal line disposed on the base substrate, extending generally along a first direction, passing through the non-light-emitting region and the display region, and transmitting a scanning signal; a vertical signal line disposed on the base substrate and positioned in the display area, the vertical signal line generally extending along a second direction intersecting the first direction; The scanning signal line includes at least one outer ring portion, and each of the at least one outer ring portion includes: a first conductive line extending generally along the first direction from the non-light emitting region to the display region; a second conductive line that extends generally along the first direction, extends from the non-light-emitting region to the display region, and is spaced apart from the first conductive line in the second direction; A display substrate, wherein the first conductor and the second conductor both overlap with the vertical signal line in a direction perpendicular to the base substrate, the scanning signal line includes a main body portion extending generally along the first direction, and the first conductor and the second conductor are both electrically connected to the main body portion.

2. The scanning signal line is a first sub-scanning signal line extending generally along the first direction, transmitting a first scanning signal, and including a first outer ring portion, the at least one outer ring portion including the first outer ring portion, the first sub-scanning signal line including a first body portion extending generally along the first direction, a first conducting wire of the first outer ring portion and a second conducting wire of the first outer ring portion both being electrically connected to the first body portion, The display substrate is a first power supply line connected to a first voltage end and configured to provide a first power supply voltage to the sub-pixel, the first power supply line including a vertical portion extending generally along the second direction, the vertical signal line including the vertical portion of the first power supply line; The display substrate according to claim 1 , wherein the first conducting wire of the first outer ring portion and the second conducting wire of the first outer ring portion overlap with a vertical portion of the first power line in a direction perpendicular to the base substrate.

3. the vertical signal lines further include data signal lines transmitting data signals; The sub-pixel is 3. The display substrate of claim 2, further comprising a data writing transistor configured to transmit the data signal to the driving transistor under control of the first scanning signal, the first sub-scanning signal line configured to provide the first scanning signal to the data writing transistor.

4. the non-light-emitting region of the display unit includes a first non-light-emitting region and a second non-light-emitting region, the first non-light-emitting region is located on a first side of the display region in the first direction, and the second non-light-emitting region is located on a second side of the display region opposite to the first side in the first direction; The first sub-scanning signal line passes through the first non-light emitting region, the display region, and the second non-light emitting region in this order, and the first body portion includes a first portion located in the first non-light emitting region and a second portion located in the second non-light emitting region, and the first sub-scanning signal line is a first branch portion electrically connected to a first portion of the first body portion and a second portion of the first body portion, the first branch portion including a first conductive wire of the first outer ring portion, the first conductive wire of the first outer ring portion being electrically connected to the first body portion; 4. The display substrate of claim 3, further comprising: a second branch portion electrically connected to a first portion of the first main body portion and a second portion of the first main body portion, the second branch portion including a second conductive wire of the first outer ring portion, the second conductive wire of the first outer ring portion being electrically connected to the first main body portion.

5. the first sub-scanning signal line further includes a second outer ring portion, the at least one outer ring portion further includes the second outer ring portion, and a first conductive wire of the second outer ring portion and a second conductive wire of the second outer ring portion are both electrically connected to the first body portion; The vertical signal line is 5. The display substrate of claim 4, further comprising: a second power supply line electrically connected to a second voltage terminal and configured to provide the sub-pixel with a second power supply voltage different from the first power supply voltage, the second power supply line extending along the second direction, the first conductive line of the second outer ring portion and the second conductive line of the second outer ring portion overlapping with the second power supply line in a direction perpendicular to the base substrate.

6. a first conductive wire of the first outer ring portion and a second conductive wire of the first outer ring portion extend from the first non-light-emitting region to the display region, and a first conductive wire of the second outer ring portion and a second conductive wire of the second outer ring portion extend from the second non-light-emitting region to the display region, The first sub-scanning signal line is 6. The display substrate of claim 5, further comprising an intermediate connecting portion, wherein the first outer ring portion and the second outer ring portion are both closed rings, and the first portion of the first main body portion, the first outer ring portion, the intermediate connecting portion, the second outer ring portion, and the second portion of the first main body portion are connected in sequence.

7. 6. The display substrate of claim 5, wherein the vertical portion of the first power supply line is located at a first edge of the display area in the first direction, and the second power supply line is located at a second edge of the display area opposite the first edge in the first direction.

8. The scanning signal line is a second sub-scanning signal line extending generally along the first direction, arranged to be spaced apart from the first sub-scanning signal line in the second direction, transmitting a second scanning signal different from the first scanning signal, and including a third outer ring portion, the at least one outer ring portion including the third outer ring portion, the second sub-scanning signal line including a second body portion extending generally along the first direction, a first conducting wire of the third outer ring portion and a second conducting wire of the third outer ring portion being both electrically connected to the second body portion, The display substrate according to claim 3 , wherein the first conducting wire of the third outer ring portion and the second conducting wire of the third outer ring portion overlap with the vertical portion of the first power line and the second power line in a direction perpendicular to the base substrate.

9. the non-light-emitting region of the display unit includes a first non-light-emitting region and a second non-light-emitting region, the first non-light-emitting region is located on a first side of the display region in the first direction, and the second non-light-emitting region is located on a second side of the display region opposite to the first side in the first direction; the second body portion includes a first portion located in the first non-light emitting region and a second portion located in the second non-light emitting region, The second sub-scanning signal line is a third branch portion electrically connected to a first portion of the second body portion and a second portion of the second body portion, the third branch portion including a first conductive wire of the third outer ring portion, the first conductive wire of the third outer ring portion being electrically connected to the second body portion; 9. The display substrate of claim 8, further comprising: a fourth branch portion electrically connected to a first portion of the second main body portion and a second portion of the second main body portion, the fourth branch portion including a second conductive wire of the third outer ring portion, the second conductive wire of the third outer ring portion being electrically connected to the second main body portion.

10. The display substrate of claim 9 , wherein the first conductive wire of the third outer ring portion and the second conductive wire of the third outer ring portion each extend from the first non-light-emitting region to the display region and then to the second non-light-emitting region.

11. The display substrate of claim 8 , wherein an annular area of ​​the third outer ring portion is larger than an annular area of ​​the first outer ring portion and is larger than an annular area of ​​the second outer ring portion.

12. 9. The display substrate of claim 8, wherein the first conducting wire of the third outer ring portion and the second conducting wire of the third outer ring portion overlap with the data signal line in a direction perpendicular to the base substrate, overlap with a vertical portion of the first power supply line in a direction perpendicular to the base substrate, and overlap with the second power supply line in a direction perpendicular to the base substrate.

13. the vertical signal lines further include detection signal lines transmitting detection signals; The sub-pixel further includes a detection transistor, the second sub-scanning signal line is configured to provide the second scanning signal to the detection transistor, and the detection transistor is configured to use the detection signal to detect an electrical characteristic of the sub-pixel under control of the second scanning signal to realize external compensation; The display substrate according to claim 8 , wherein the first conducting wire of the third outer ring portion and the second conducting wire of the third outer ring portion overlap with the detection signal line in a direction perpendicular to the base substrate.

14. The display unit includes a plurality of the sub-pixels arranged in an array, the array including a first pixel row extending along the first direction and a second pixel row extending along the first direction, the first pixel row including first and second sub-pixels arranged adjacent to each other, the second pixel row including third and fourth sub-pixels arranged adjacent to each other, the first sub-scanning signal line is configured to provide the first scan signal to data transistors of the third sub-pixel and the fourth sub-pixel; 14. The display substrate of claim 13, wherein a first conductive line of the third outer ring portion is configured to provide the second scanning signal to the detection transistors of the first subpixel and the second subpixel, and a second conductive line of the third outer ring portion is configured to provide the second scanning signal to the detection transistors of the third subpixel and the fourth subpixel.

15. the data signal lines include a first data line providing the data signal to the first sub-pixel, a second data line providing the data signal to the second sub-pixel, a third data line providing the data signal to the third sub-pixel, and a fourth data line providing the data signal to the fourth sub-pixel, the first data line, the second data line, the third data line, and the fourth data line being spaced apart from each other in the first direction; 15. The display substrate of claim 14, wherein the first conductive wire of the third outer ring portion and the second conductive wire of the third outer ring portion overlap with the first data line, the second data line, the third data line, and the fourth data line in a direction perpendicular to the base substrate.

16. The display unit includes: An auxiliary scanning line extending along the first direction; a first connection line electrically connected to the auxiliary connection line and the first sub-scanning signal line; a second connection line spaced apart from the first connection line in the second direction and electrically connected to the auxiliary connection line and the first sub-scanning signal line; the auxiliary connection line is configured to provide the first scanning signal to the data transistor of the first sub-pixel and the data transistor of the second sub-pixel; The display substrate according to claim 8 , wherein the first conducting wire of the third outer ring portion and the second conducting wire of the third outer ring portion overlap with the first connecting line and the second connecting line in a direction perpendicular to the base substrate.

17. the auxiliary scanning line has a first end and a second end opposed to each other in the first direction, 17. The display substrate of claim 16, wherein the first connection line is electrically connected to a first end of the auxiliary scanning line and the first outer ring portion, and the second connection line is electrically connected to a second end of the auxiliary scanning line and the second outer ring portion.

18. The display substrate of claim 8 , wherein a number of the outer ring portions included in the second sub-scanning signal lines is smaller than a number of the outer ring portions included in the first sub-scanning signal lines.

19. the first power line further includes a horizontal portion electrically connected to the vertical portion and extending generally along the first direction; The lateral portion includes an inner annular portion, the inner annular portion having: a third conductive line extending generally along the first direction and positioned in the display area; a fourth conductive line extending generally along the first direction, located in the display area, and spaced apart from the third conductive line in the second direction; The display substrate of claim 3 , wherein the third conductive line and the fourth conductive line overlap the vertical signal line in a direction perpendicular to the base substrate to provide the same first power supply voltage to the sub-pixels.

20. The display substrate of claim 19 , wherein the third conductive line and the fourth conductive line overlap the data signal line in a direction perpendicular to the base substrate.

21. the vertical signal lines further include detection signal lines transmitting detection signals; The scanning signal line is a second sub-scanning signal line extending generally along the first direction and spaced apart from the first sub-scanning signal line in the second direction, the second sub-scanning signal line transmitting a second scanning signal different from the first scanning signal; The sub-pixel further includes a detection transistor, the second sub-scanning signal line is configured to provide the second scanning signal to the detection transistor, and the detection transistor is configured to realize external compensation by detecting an electrical characteristic of the sub-pixel under control of the second scanning signal; The display substrate of claim 19 , wherein the third conducting wire and the fourth conducting wire overlap with the detection signal line in a direction perpendicular to the base substrate.

22. The display unit includes a plurality of the sub-pixels arranged in an array, the array including a first pixel row extending along the first direction and a second pixel row extending along the first direction, the first pixel row including first and second sub-pixels arranged adjacent to each other, the second pixel row including third and fourth sub-pixels arranged adjacent to each other, the data signal lines include a first data line that provides the data signal to the first sub-pixel, a second data line that provides the data signal to the second sub-pixel, a third data line that provides the data signal to the third sub-pixel, and a fourth data line that provides the data signal to the fourth sub-pixel, the first data line, the second data line, the third data line, the fourth data line, and the detection signal line are arranged to be spaced apart in the first direction; 20. The display substrate of claim 19, wherein the detection signal line is sandwiched between the third conducting line and the fourth conducting line and is adjacent to the third conducting line and the fourth conducting line, and the third conducting line and the fourth conducting line all overlap with the third data line, the fourth data line and the detection signal line in a direction perpendicular to the base substrate.

23. The subpixel includes a drive transistor and a light emitting device, the drive transistor configured to control a magnitude of a drive current through the light emitting device, the light emitting device configured to receive the drive current and be driven by the drive current to emit light, the light emitting device including a first electrode; The display substrate of claim 1 , wherein the display unit further comprises a pixel defining layer, the pixel defining layer defining an opening area of ​​the first electrode of the sub-pixel and exposing at least a portion of the outer ring portion.

24. The display unit includes: a connection structure including a connection portion electrically connected to a first portion of the first electrode and a second portion of the first electrode and located in the non-light-emitting region; a first relay electrode electrically connected to a first electrode of the driving transistor and including a portion located in the non-light emitting region, the connection portion further including a first relay electrode electrically connected in the non-light emitting region to the portion of the first relay electrode located in the non-light emitting region; 24. The display substrate of claim 23, wherein the pixel definition layer includes a portion located in the non-display area, the portion of the pixel definition layer located in the non-display area has a groove recessed in a direction away from the display area, at least a portion of a orthogonal projection of the connection portion onto the base substrate is located within a orthogonal projection of the groove onto the base substrate, the groove has an edge facing the connection portion, and there is a gap between the edge of the connection portion away from the display area in the first direction and the edge of the groove.

25. The display substrate is a first power supply line electrically connected to a first voltage end and configured to provide a first power supply voltage to the sub-pixel, the first power supply line including a vertical portion extending generally along the second direction; a second power supply line electrically connected to a second voltage terminal and configured to provide a second power supply voltage different from the first power supply voltage to the sub-pixel, the second power supply line extending along the second direction; the vertical portion of the first power line and the second power line are arranged to be spaced apart in the first direction, and are respectively located at a first edge of the display area in the first direction and a second edge of the display area opposite to the first edge in the first direction; 2. The display substrate according to claim 1, wherein a region between an edge of the vertical portion of the first power line away from the second power line and an edge of the second power line away from the vertical portion of the first power line is the display region.

26. A display device, comprising a display substrate according to any one of claims 1-25.

27. A method for operating a display substrate according to any one of claims 1 to 25, comprising cutting a portion of one of the first and second conducting wires of the same outer ring portion located in the display area.

28. A method for operating a display substrate as described in claim 27, wherein the cut portion of one of the first and second conductive wires of the same outer ring portion is not present on the side closer to the base substrate with any conductive layer overlapping one of the first and second conductive wires of the same outer ring portion in a direction perpendicular to the base substrate.

Images