Display substrate and display device

Abstract

A display substrate and a display device, the display substrate including a display region and a non-display region, the non-display region including a rounded corner region, the display substrate including a circuit structure layer, the circuit structure layer including a pixel circuit and a control driving circuit, the circuit structure layer further including a plurality of reset output lines and a plurality of reset transfer lines located in the non-display region and arranged on a side of the control driving circuit closer to the display region, the reset output lines are arranged in a different layer from the reset transfer lines, the extension direction of the reset output lines intersects with the extension direction of the reset transfer lines, the reset transfer lines are connected to the pixel circuits, and there is an overlapping portion between the orthogonal projection at a base of the at least one reset transfer line located in the rounded corner region and the orthogonal projection at bases of the plurality of reset output lines.

Description

[Technical field]

[0001] The present disclosure relates to the field of display technology, but is not limited thereto, and more particularly to a display substrate and a display device. [Background technology]

[0002] Organic Light Emitting Diodes (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices with advantages such as autonomous light emission, wide viewing angle, high contrast, low power consumption, extremely fast response speed, light weight, thin type, bendability, and low cost. As display technology develops, flexible displays that use OLEDs or QLEDs as light-emitting elements and thin film transistors (TFTs) for signal control have become the mainstream product in the current display field. Summary of the Invention [Means for solving the problem]

[0003] The following is a summary of the subject matter described herein. This summary is not intended to limit the scope of protection of the claims.

[0004] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising a display region and a non-display region, the display region comprising at least one round corner, the non-display region comprising a round corner region located outside the round corner, the display substrate comprising a base and a circuit structure layer disposed on the base, the circuit structure layer comprising: pixel circuits located in the display region and arranged in an array; and a control driving circuit located in the non-display region, the pixel circuits comprising reset transistors, and the control driving circuit configured to provide a driving signal to the reset transistor; the circuit structure layer further includes a plurality of reset output lines and a plurality of reset transfer lines located in the non-display area and disposed on a side of the control and driving circuit close to the display area, the reset output lines and the reset transfer lines are disposed in a different layer, and an extending direction of the reset output lines intersects with an extending direction of the reset transfer lines; the reset output line is electrically connected to the control drive circuit and the reset transfer line, and the reset transfer line is connected to the pixel circuit; An overlapping portion exists between the orthogonal projection of the at least one reset transfer line located in the rounded corner region onto a base and the orthogonal projection of the multiple reset output lines onto bases.

[0005] In some possible implementations, the circuit structure layer further includes a reset connection line located in the non-display area and disposed on a side of the control driving circuit close to the display area, the reset connection line and the reset output line are disposed in a different layer, the extension direction of the reset connection line intersects with the extension direction of the reset output line, and the pixel circuits arranged in an array include a plurality of reset signal lines; the reset connection line is electrically connected to the reset transfer line and the reset signal line, At least one reset connection line and a plurality of reset output lines located in the rounded corner region have an overlapping portion when orthogonally projected onto a base.

[0006] In some possible implementations, the pixel circuit further includes a write transistor, and the control drive circuit is further configured to provide a drive signal to the write transistor; the circuit structure layer further includes a plurality of control output lines located in the non-display area and disposed on a side of the control driving circuit close to the display area, the control output lines and the reset output lines are disposed in a different layer, and an extending direction of the control output lines intersects with an extending direction of the reset output lines; The control output line is connected to the control drive circuit and the pixel circuit, respectively, and an overlapping portion exists between the orthogonal projection at a base of the control output line and the orthogonal projection at bases of the plurality of reset output lines.

[0007] In some possible implementations, the circuit structure layer further includes a control connection line located in the non-display area and arranged on a side of the control driving circuit close to the display area, the control connection line and the reset output line are arranged in a different layer, the extension direction of the control connection line crosses the extension direction of the reset output line, the pixel circuits arranged in an array include a plurality of control signal lines, and the control pole of the writing transistor is electrically connected to the control signal line; the control connection line is electrically connected to the control output line and the control signal line, At least one control connection line and a plurality of reset output lines located in the rounded corner region have an overlapping portion when orthogonally projected onto the base.

[0008] In some possible implementations, the control and drive circuit includes a plurality of cascaded control shift registers, the control shift registers including an output terminal; an output terminal of the control shift register of the i stage is electrically connected to the i th reset output line, 1≦i≦M; an output terminal of the control shift register of the j stage is electrically connected to the jS th control output lines, S+1≦j≦M+S, M is the total number of rows of the pixel circuit, and S≧1; The reset output line and the control output line connected to the output terminal of the same control shift register are connected to each other, and there is an overlapping portion between the orthogonal projection at the base of the reset output line and the orthogonal projection at the base of the control output line.

[0009] In some possible implementations, the circuit structure layer further includes a light emitting driving circuit located in the non-display area, the light emitting driving circuit being located on a side of the control driving circuit away from the display area, the pixel circuit including a light emitting transistor, and the light emitting driving circuit configured to provide a driving signal to the light emitting transistor; the circuit structure layer further includes a plurality of light emitting output lines located in the non-display area and disposed on a side of the control driving circuit close to the display area, the light emitting output lines are disposed in a layer different from the reset output lines, and an extending direction of the light emitting output lines intersects with an extending direction of the reset output lines; The light-emitting output line is connected to the light-emitting drive circuit and the pixel circuit, respectively, and an overlapping portion exists between the orthogonal projection of the light-emitting output line at a base and the orthogonal projection of the plurality of reset output lines at bases.

[0010] In some possible implementations, the circuit structure layer further includes an emission connecting line located in the non-display area and disposed on a side of the control driving circuit close to the display area, the emission connecting line and the reset output line are disposed in a different layer, the extension direction of the emission connecting line crosses the extension direction of the reset output line, and the pixel circuits arranged in an array include a plurality of emission signal lines; the light-emitting connection line is electrically connected to the light-emitting output line and the light-emitting signal line, At least one light emitting connection line and a plurality of reset output lines located in the round corner region have an overlapping portion when orthogonally projected onto a base.

[0011] In some possible implementations, the light emission driver circuit includes a plurality of cascaded light emission shift registers, the light emission shift registers including an output terminal; The output terminals of at least one stage of the light emission shift register are electrically connected to a plurality of light emission output lines.

[0012] In some possible implementations, when the light emitting shift register is electrically connected to at least two light emitting output lines, the circuit structure layer further includes a light emitting connection part located in the non-display area and disposed on a side of the control and driving circuit close to the display area, the light emitting connection part is disposed in a layer different from the light emitting output lines, and the extension direction of the light emitting connection part crosses the extension direction of the light emitting output lines; At least two light-emitting output lines connected to the same light-emitting shift register are electrically connected via the light-emitting connection portion, and the light-emitting connection portion is located on the side of the plurality of reset output lines away from the display area.

[0013] In some possible implementations, the circuit structure layer further includes a scanning drive circuit located in the non-display area, the scanning drive circuit being located between the control drive circuit and the emission drive circuit, the pixel circuit including a compensation transistor, and the scanning drive circuit being configured to provide a drive signal to the compensation transistor; the circuit structure layer further includes a plurality of scanning output lines located in the non-display area and disposed on a side of the control driving circuit close to the display area, the scanning output lines and the reset output lines are disposed in a different layer, and an extending direction of the scanning output lines crosses an extending direction of the reset output lines; The scanning output line is connected to the scanning drive circuit and the pixel circuit, respectively, and an overlapping portion exists between the orthogonal projection at a base of the scanning output line and the orthogonal projection at bases of a plurality of reset output lines.

[0014] In some possible implementations, the circuit structure layer further includes a scanning connection line located in the non-display area and disposed on a side of the control driving circuit close to the display area, the scanning connection line and the reset output line are disposed in a different layer, the extension direction of the scanning connection line intersects with the extension direction of the reset output line, and the pixel circuits arranged in an array include a plurality of scanning signal lines; the scanning connection lines are electrically connected to the scanning output lines and the scanning signal lines, At least one scan connection line and a plurality of reset output lines located in the rounded corner region have an overlapping orthogonal projection at their bases.

[0015] In some possible implementations, the scan drive circuit includes a plurality of cascaded scan shift registers, the scan shift registers including an output terminal; The output terminals of at least one stage of the scanning shift register are electrically connected to a plurality of scanning output lines.

[0016] In some possible implementations, when the scanning shift register is electrically connected to at least two scanning output lines, the circuit structure layer further includes a scanning connection part located in the non-display area and disposed on a side of the control driving circuit close to the display area, the scanning connection part is disposed in a layer different from that of the scanning output lines, and the extending direction of the scanning connection part crosses the extending direction of the scanning output lines; At least two scan output lines connected to the same scan shift register are electrically connected via the scan connection portion, and the scan connection portion is located on a side of the plurality of reset output lines away from a display area.

[0017] In some possible implementations, the S+1th stage control shift register to the M+Sth stage control shift register are located between the light emission driving circuit and the scan driving circuit; The multiple-stage control shift registers located in the round corner region are arranged along the boundary of the round corner, The multiple-stage light-emitting shift registers located in the round corner region are arranged along the boundary of the round corner, A multi-stage scanning shift register located in the rounded corner region is arranged along the boundary of the rounded corner.

[0018] In some possible implementations, the circuit structure layer further includes a plurality of first initial output lines located in the non-display area and disposed on a side of the control driving circuit close to the display area, the first initial output lines and the reset output lines are disposed in a different layer, the extension direction of the first initial output lines crosses the extension direction of the reset output line, and the pixel circuits arranged in an array include a plurality of first initial signal lines and a plurality of second initial signal lines; The first initial output line is electrically connected to one of the first initial signal line and the second initial signal line of the pixel circuit, and there is an overlapping portion between the orthogonal projection of the first initial output line at a base and the orthogonal projection of the multiple reset output lines at bases.

[0019] In some possible implementations, the circuit structure layer further includes a plurality of first initial connection lines located in the non-display area and disposed on a side of the control driving circuit close to the display area, the first initial connection lines and the reset output lines are disposed in a different layer, and the extension direction of the first initial connection lines crosses the extension direction of the reset output line; the first initial output line is electrically connected to one of a first initial signal line and a second initial signal line of a pixel circuit via the first initial connection line; An overlapping portion exists between the orthogonal projection of the first initial connection line located in the rounded corner region onto its base and the orthogonal projection of the plurality of reset output lines onto their bases.

[0020] In some possible implementations, the circuit structure layer further includes a first initial power supply line located in the non-display area and disposed on a side of the control driving circuit close to the display area, the first initial power supply line and the reset output line are disposed in a different layer, and the extension direction of the first initial power supply line is parallel to the extension direction of the reset output line; The first initial power supply line is electrically connected to the plurality of first initial output lines, and an orthogonal projection of the first initial power supply line at a base at least partially overlaps with an orthogonal projection of the plurality of reset output lines at a base.

[0021] In some possible implementations, the circuit structure layer further includes a plurality of second initial connection lines located in the non-display area and disposed on a side of the control driving circuit close to the display area, the second initial connection lines and the reset output line are disposed in a different layer, the extension direction of the second initial connection lines crosses the extension direction of the reset output line, and the extension direction of the first initial connection lines is parallel to the extension direction of the second initial connection lines; The second initial connection line is electrically connected to the other of the first initial signal line and the second initial signal line of the pixel circuit, and there is an overlapping portion between the orthogonal projection of the second initial connection line at a base and the orthogonal projection of the multiple reset output lines at bases.

[0022] In some possible implementations, the circuit structure layer further includes a second initial power supply line located in the non-display area and disposed on a side of the control driving circuit close to the display area, the second initial power supply line and the reset output line are disposed in a different layer, and the second initial connection line and the second initial power supply line are disposed in the same layer, the extension direction of the first initial power supply line is parallel to the extension direction of the second initial power supply line, and the second initial power supply line is disposed on the side of the first initial power supply line close to the display area; The second initial power supply line is electrically connected to the plurality of second initial connection lines, and an orthogonal projection of the second initial power supply line at a base at least partially overlaps with an orthogonal projection of the plurality of reset output lines at a base.

[0023] In some possible implementations, the circuit structure layer includes a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer and a fifth conductive layer, which are sequentially stacked on the base; the first conductive layer includes a reset signal line, a light emitting signal line, a scanning signal line and a control signal line; the second conductive layer includes a first initial signal line, a second initial signal line and a scanning connection portion; the third conductive layer includes a light emitting connection portion; the fourth conductive layer includes a reset transfer line, a first initial output line, a light emission output line, a scanning output line, and a control output line; The fifth conductive layer includes a reset connecting line, a first initial connecting line, a light emitting connecting line, a scan connecting line, a control connecting line, a second initial connecting line, a first initial power supply line and a second initial power supply line.

[0024] In some possible implementations, the reset output line is located in the first conductive layer or the second conductive layer.

[0025] In a second aspect, the present disclosure further provides a display device comprising the above-mentioned display substrate.

[0026] Other aspects may be understood after reading and understanding the accompanying drawings and detailed description. [Brief description of the drawings]

[0027] [Figure 1] FIG. 2 is a schematic diagram showing the structure of a display substrate. [Diagram 2] FIG. 2 is a schematic diagram showing the division of a display substrate into regions. [Diagram 3] FIG. 13 is a structural schematic diagram of another display substrate. [Figure 4] FIG. 2 is a structural schematic diagram of a round corner region in a display substrate according to an embodiment of the present disclosure. [Diagram 5] FIG. 2 is a structural schematic diagram of a bezel region in a display substrate according to an embodiment of the present disclosure. [Figure 6A] FIG. 2 is a schematic diagram of an equivalent circuit of a pixel circuit. [Figure 6B] 4 is an operation timing chart of the pixel circuit. [Figure 7] FIG. 2 is a partial cascade schematic diagram of a driving circuit according to an example embodiment. [Figure 8] 1 is a structural schematic diagram of a round corner region of a display substrate according to an exemplary embodiment; [Figure 9A] FIG. 2 is an equivalent circuit diagram of a light emission shift register according to an example embodiment. [Figure 9B] 9B is a timing chart of the light emission shift register of FIG. 9A. [Figure 10A] FIG. 2 is an equivalent circuit diagram of a scanning shift register according to an example embodiment. [Figure 10B] 10B is a timing chart of the scanning shift register of FIG. 10A. [Figure 11A] FIG. 2 is an equivalent circuit diagram of a control shift register according to an example embodiment. [Figure 11B] 11B is a timing chart of the control shift register of FIG. 11A. [Figure 12] FIG. 4 is a structural schematic diagram of a first conductive layer in the bezel area. [Figure 13] FIG. 2 is a schematic diagram showing the structure of a first conductive layer in a rounded corner region. [Figure 14] FIG. 4 is a schematic diagram showing the structure of a second conductive layer in the bezel area. [Figure 15] FIG. 4 is a schematic diagram of the structure of the bezel region after the second conductive layer is formed. [Figure 16]FIG. 4 is a schematic diagram showing the structure of a second conductive layer in a rounded corner region. [Figure 17] FIG. 4 is a schematic diagram of the structure of a rounded corner region after a second conductive layer is formed. [Figure 18] FIG. 4 is a schematic diagram showing the structure of a third conductive layer in the bezel area. [Figure 19] FIG. 13 is a schematic diagram of the structure of the bezel region after the third conductive layer is formed. [Figure 20] FIG. 4 is a schematic diagram showing the structure of a third conductive layer in a rounded corner region. [Figure 21] FIG. 13 is a schematic diagram of the structure of a rounded corner region after a third conductive layer is formed. [Figure 22] FIG. 4 is a structural schematic diagram of a fourth insulating layer in the bezel region. [Figure 23] FIG. 13 is a schematic diagram of the structure of the bezel region after a fourth insulating layer is formed. [Figure 24] FIG. 13 is a structural schematic diagram of a fourth insulating layer in a rounded corner region. [Diagram 25] FIG. 13 is a schematic diagram of the structure of the rounded corner region after a fourth insulating layer is formed. [Figure 26] FIG. 4 is a schematic diagram showing the structure of a fourth conductive layer in the bezel area. [Figure 27] FIG. 13 is a schematic diagram of the structure of the bezel region after a fourth conductive layer is formed. [Figure 28] FIG. 13 is a schematic diagram showing the structure of a fourth conductive layer in a rounded corner region. [Figure 29] FIG. 13 is a schematic diagram of the structure of a rounded corner region after a fourth conductive layer is formed. [Diagram 30] FIG. 13 is a structural schematic diagram of a fifth insulating layer in the bezel region. [Diagram 31] FIG. 13 is a schematic diagram of the structure of the bezel region after a fifth insulating layer is formed. [Diagram 32] FIG. 13 is a schematic diagram of the structure of the fifth insulating layer in the rounded corner region. [Diagram 33] FIG. 13 is a schematic diagram of the structure of a rounded corner region after a fifth insulating layer is formed. [Diagram 34] FIG. 4 is a schematic diagram of the structure of a fifth conductive layer in the bezel area. [Diagram 35] FIG. 13 is a schematic diagram of the structure of the bezel region after a fifth conductive layer is formed. [Diagram 36]FIG. 13 is a schematic diagram showing the structure of a fifth conductive layer in a rounded corner region. [Figure 37] FIG. 13 is a schematic diagram of the structure of a rounded corner region after a fifth conductive layer is formed. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The drawings are for better understanding of the technical solution of the present disclosure, constitute a part of the specification, and are used to explain the technical solution of the present disclosure together with the embodiments of the present application, and are not intended to limit the technical solution of the present disclosure. The shapes and sizes of each part in the drawings are for the purpose of merely explaining the contents of the present disclosure and do not reflect the true ratio.

[0029] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the drawings. The embodiments may be implemented in many different forms. As can be easily understood by those skilled in the art, the manner and content may be converted into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the description of the following embodiments. If there is no conflict, the embodiments and features of the embodiments of the present disclosure may be combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure relate only to structures related to the embodiments of the present disclosure, and other structures may refer to general designs.

[0030] The ratios of the drawings in this disclosure can be used as a reference for the actual process, but are not limited thereto. For example, the aspect ratio of the channel, the thickness and pitch of each film layer, and the width and pitch of each signal line can be adjusted according to actual needs. In addition, the number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the numbers shown in the drawings, and the drawings described in this disclosure are merely structural schematic diagrams, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0031] In the drawings, the size, thickness or area of ​​one or more components may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the dimensions, and the shape and size of one or more parts in the drawings do not reflect the true ratio. In addition, the drawings are schematic illustrations of ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, etc. shown in the drawings.

[0032] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components and are not intended to be limiting in terms of quantity.

[0033] In this specification, for convenience, the positions of components are described with reference to the drawings using terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inside", and "outside". However, this is for the purpose of explaining and simplifying the specification, and is not intended to indicate or suggest that the described device or element has a specific orientation and must be configured and operated in a specific orientation. Therefore, it is not intended to limit the present disclosure. The positional relationship of the components is appropriately changed depending on the direction in which the components are described. Therefore, it is not limited to the terms described in the specification, and may be appropriately changed in some cases.

[0034] In this specification, unless otherwise clearly specified and limited, the terms "attached", "coupled" and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection. It may be a mechanical connection or an electrical connection. It may be a direct connection, an indirect connection via a linker, or an internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific situation.

[0035] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, a channel region refers to a region through which a current mainly flows.

[0036] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. The functions of the "source electrode" and the "drain electrode" may be interchanged, such as when using transistors with reversed polarity or when the direction of current flow during circuit operation changes. Thus, in this specification, the terms "source electrode" and "drain electrode" may be interchanged.

[0037] In this specification, "electrical connection" includes cases where components are connected via an element having a certain electrical function. The "element having a certain electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the components being connected. Examples of the "element having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and elements having various other functions.

[0038] In this specification, "parallel" refers to a state in which the angle between two straight lines is between -10° and 10°, including a state in which the angle is between -5° and 5°, and "perpendicular" refers to a state in which the angle between two straight lines is between 80° and 100°, including a state in which the angle is between 85° and 95°.

[0039] In this specification, the terms "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive film." Similarly, an "insulating film" may be changed to an "insulating layer."

[0040] In this description, the term "disposed in the same layer" refers to a structure formed by patterning two (or more) types of structures by the same patterning process, and the materials may be the same or different. For example, the materials of the precursors forming the multiple structures disposed in the same layer are the same, and the materials finally formed may be the same or different.

[0041] The shapes such as triangles, rectangles, trapezoids, pentagons, and hexagons in this specification are not strictly defined, and may be approximate triangles, rectangles, trapezoids, pentagons, and hexagons, and may have some small deformations due to tolerances, and may have chamfers, arc edges, deformations, and the like.

[0042] In this disclosure, "about" does not specify a precise limit, but allows for values ​​within process or measurement error.

[0043] The display substrate uses low temperature polysilicon (LTPS) technology, which has the advantages of high resolution, high response speed, high brightness, and high aperture ratio. Although it has been welcomed by the market, LTPS technology also has some drawbacks, such as high production costs and high power consumption. At this time, the low temperature polycrystalline oxide (LTPO) technology has been introduced. Compared with LTPS technology, LTPO technology has a smaller leakage current and faster pixel response, and an oxide layer is added to the display substrate, which reduces the energy consumption required for exciting the pixel points and reduces the power consumption when displaying the screen. However, compared with display products using LTPS technology, display products using LTPO technology require additional driving circuits to control the metal oxide transistors in the display products, so that display products using LTPO technology cannot achieve narrow bezels.

[0044] Fig. 1 is a structural schematic diagram of a display substrate, Fig. 2 is a schematic diagram of an area division of the display substrate, Fig. 3 is a structural schematic diagram of another display substrate, Fig. 4 is a structural schematic diagram of a rounded corner area in a display substrate according to an embodiment of the present disclosure, and Fig. 5 is a structural schematic diagram of a bezel area in a display substrate according to an embodiment of the present disclosure. As shown in Figs. 1 to 3, the display substrate according to the embodiment of the present disclosure includes a display area AA and a non-display area AA', the display area AA includes at least one round corner C, and the non-display area AA' includes a rounded corner area CR located outside the round corner, the display substrate includes a base and a circuit structure layer disposed on the base, the circuit structure layer includes pixel circuits P located in the display area AA and arranged in an array, and a control drive circuit located in the non-display area AA', the pixel circuits include reset transistors, and the control drive circuit is configured to supply a drive signal to the reset transistor.

[0045] As shown in FIG. 2, the display area AA further includes a linear bezel L, and the non-display area includes a bezel area BR located outside the linear bezel.

[0046] In the present disclosure, as shown in Figures 4 and 5, the circuit structure layer further includes a plurality of reset output lines RST_OL and a plurality of reset transfer lines RST_TL located in the non-display area and arranged on the side closer to the display area of ​​the control driving circuit Gate PGOA, the reset output lines RST_OL and the reset transfer lines RST_TL are arranged in a different layer, and the extension direction of the reset output lines RST_OL intersects with the extension direction of the reset transfer lines RST_TL. R(i) in Figures 4 and 5 indicates the pixel circuit of the i-th row.

[0047] In the present disclosure, the reset output line RST_OL is electrically connected to the control drive circuit and the reset transfer line RST_TL, and the reset transfer line RST_TL is connected to the pixel circuit. An overlapping portion exists between the orthogonal projection of at least one reset transfer line RST_TL located in the round corner region CR at its base and the orthogonal projection of the multiple reset output lines RST_OL at their bases.

[0048] In exemplary embodiments, the base may be a rigid base or a flexible base, and the rigid base may be one or more of, but is not limited to, glass, metal foil strips, and the flexible base may be one or more of, but is not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0049] In an exemplary embodiment, the boundary shape of the display area may be a rectangle with rounded corners, as shown in Figures 1 and 2, but the present disclosure is not limited thereto. The display substrate according to the present disclosure can achieve a large-angle folding function of four sides, which can improve the problem of wrinkles when bonding modules, and improve the product yield.

[0050] In an exemplary embodiment, the display substrate may further include a light emitting structure layer disposed on the side of the circuit structure layer away from the base, the light emitting structure layer including light emitting elements located in the display area and arranged in an array.

[0051] In an exemplary embodiment, the light-emitting element may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). The OLED may include a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) that are stacked together.

[0052] In an exemplary embodiment, the display substrate may include other film layers, such as spacer columns, and the present disclosure is not limited thereto.

[0053] In an exemplary embodiment, the display area includes pixel units arranged in an array, at least one pixel unit includes at least three sub-pixels, and at least one sub-pixel includes a pixel circuit and a light-emitting element, and the pixel circuit located in the same sub-pixel is electrically connected to the light-emitting element and configured to drive the light-emitting element to emit light.

[0054] In an exemplary embodiment, a pixel unit may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, although the present disclosure is not limited thereto.

[0055] In an exemplary embodiment, the shape of the sub-pixel in the pixel unit may be a rectangle, a rhombus, a pentagon, or a hexagon. If the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or hexagonal manner, and if the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or square manner, and the present disclosure is not limited thereto.

[0056] In an exemplary embodiment, the display substrate may be an LTPO display substrate or an LTPS display substrate.

[0057] In an exemplary embodiment, the pixel circuits arranged in an array include a plurality of data signal lines, a plurality of reset signal lines, a plurality of control signal lines, a plurality of scanning signal lines, a plurality of emission signal lines, a plurality of first initial signal lines, and a plurality of second initial signal lines.

[0058] In an exemplary embodiment, the data signal line extends in a first direction and the plurality of data signal lines are arranged in a second direction. The reset signal line extends in a second direction and the plurality of reset signal lines are arranged in the first direction. The control signal line extends in a second direction and the plurality of control signal lines are arranged in the first direction. The scanning signal line extends in a second direction and the plurality of scanning signal lines are arranged in the first direction. The light emitting signal line extends in a second direction and the plurality of light emitting signal lines are arranged in the first direction. The first initial signal line extends in a second direction and the plurality of first initial signal lines are arranged in the first direction. The second initial signal line extends in a second direction and the plurality of second initial signal lines are arranged in the first direction.

[0059] In an exemplary embodiment, Fig. 6A is an equivalent circuit schematic diagram of a pixel circuit. As shown in Fig. 6A, the pixel circuit may include seven transistors (first transistor T1 to seventh transistor T7), one capacitor C, and nine signal lines (a data signal line DATA, a control signal line G, a scanning signal line S, a reset signal line RST, an emission signal line E, a first initial signal line INIT1, a second initial signal line INIT2, a first power supply line VDD, and a second power supply line VSS).

[0060] In an exemplary embodiment, the first plate of the capacitor C is connected to the first power supply line VDD, and the second plate of the capacitor C is connected to the first node N1. The control pole of the first transistor T1 is connected to the reset signal line RST, the first pole of the first transistor T1 is connected to the first initial signal line INIT1, the second pole of the first transistor is connected to the first node N1, the control pole of the second transistor T2 is connected to the scan signal line S, the first pole of the second transistor T2 is connected to the first node N1, and the second pole of the second transistor T2 is connected to the second node N2. The control pole of the third transistor T3 is connected to the first node N1, the first pole of the third transistor T3 is connected to the second node N2, and the second pole of the third transistor T3 is connected to the third node N3. The control pole of the fourth transistor T4 is connected to the control signal line G, the first pole of the fourth transistor T4 is connected to the data signal line DATA, and the second pole of the fourth transistor T4 is connected to the third node N3. The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, the second electrode of the fifth transistor T5 is connected to the third node N3, the control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the second node N2, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element. The control electrode of the seventh transistor T7 is connected to the control signal line G, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting element L, and the second electrode of the light-emitting element is connected to the second power supply line VSS.

[0061] In an exemplary embodiment, the first transistor T1 and the seventh transistor T7 may be referred to as reset transistors, and when an effective level signal is input to the reset signal line RST, the first transistor T1 transfers an initialization voltage to the first node N1 to initialize the charge amount of the first node N1, and the seventh transistor T7 transfers an initialization voltage to the first pole of the light-emitting element L to initialize the charge amount of the first pole of the light-emitting element L.

[0062] In an exemplary embodiment, the third transistor T3 may be referred to as a drive transistor, and the third transistor T3 determines the drive current flowing between the first power supply line VDD and the second power supply line VSS in response to the potential difference between the control pole and the first pole.

[0063] In an exemplary embodiment, the fourth transistor T4 may be referred to as a write transistor, etc., and when a valid level signal is input to the control signal line G, the fourth transistor T4 inputs the data voltage of the data signal line DATA to the pixel circuit.

[0064] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. When an effective level signal is input to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to cause the light emitting element L to emit light.

[0065] In an exemplary embodiment, the first power supply line VDD continues to provide a high level signal and the second power supply line VSS continues to provide a low level signal.

[0066] In an exemplary embodiment, the second transistor T2 is a metal oxide transistor and is an N-type transistor, and the first transistor T1, the third transistor T3 to the seventh transistor T7 are low-temperature polysilicon transistors and are P-type transistors. The oxide transistors can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.

[0067] 6B is an operation timing chart of the pixel circuit. Hereinafter, the pixel circuit according to the exemplary embodiment will be described with the operation process of the pixel circuit shown in FIG. 6B. The operation process of the pixel circuit may include:

[0068] The first stage A1 is called a reset stage, in which the signals of the control signal line G and the light emitting signal line E are both high level signals, and the signals of the reset signal line RST and the scanning signal line S are low level signals. The signal of the reset signal line RST is a low level signal, the first transistor T1 is turned on, the signal of the first initial signal line INIT1 is supplied to the first node N1 to initialize the capacitor C and clear the original data voltage of the capacitor C, the seventh transistor T7 is turned on, and the initial voltage of the second initial signal line INIT2 is supplied to the first pole of the light emitting element L to initialize (reset) the first pole of the light emitting element L and clear the voltage previously stored therein to complete the initialization. The signals of the control signal line G and the light emitting signal line E are high level signals, and the signal of the scanning signal line S is a low level signal, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off, and the light emitting element L does not emit light at this stage.

[0069] The second stage A2 is called a data writing stage or threshold compensation stage, in which the control signal line G is a low level signal, the signals of the reset signal line RST, the emission signal line E and the scanning signal line S are high level signals, and the data signal line DATA outputs a data voltage. In this stage, the first node N1 is a low level signal, so the third transistor T3 is turned on. The signal of the control signal line G is a low level signal, the fourth transistor T4 is turned on, and the signal of the scanning signal line S is a high level signal, so the second transistor T2 is turned on. By turning on the second transistor T2 and the fourth transistor T4, the data voltage output by the data signal line DATA is supplied to the first node N1 via the third node N3, the turned-on third transistor T3, the second node N2, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line DATA and the threshold voltage of the third transistor T3 is charged in the capacitor C until the voltage of the first node N1 becomes Vd-|Vth|, where Vd is the data voltage output by the data signal line DATA and Vth is the threshold voltage of the third transistor T3. The signal of the reset signal line RST is a high-level signal, and the first transistor T1 and the seventh transistor T7 are turned off. The signal of the light-emitting signal line E is a high-level signal, and the fifth transistor T5 and the sixth transistor T6 are turned off.

[0070] The third stage A3 is called a light-emitting stage, in which the signals of the scanning signal line S and the light-emitting signal line E are low level signals, and the signals of the reset signal line RST and the control signal line G are high level signals. The signals of the control signal line G and the reset signal line RST are high level signals, and the first transistor T1, the fourth transistor T4 and the seventh transistor T7 are turned off. The signal of the scanning signal line S is a low level signal, and the second transistor T2 is turned off. The signal of the light-emitting signal line E is a low level signal, and the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output from the first power supply line VDD supplies a driving voltage to the first pole of the light-emitting element L through the fifth transistor T5, the third transistor T3 and the sixth transistor T6 that are turned on, thereby driving the light-emitting element L to emit light.

[0071] In the driving process of the pixel circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control pole and the first pole. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is given by the following formula:

[0072] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0073] Here, I is the driving current flowing through the third transistor T3, i.e., the driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line DATA, and Vdd is the power supply voltage output by the first power supply line VDD.

[0074] In an exemplary embodiment, as shown in FIG. 3, the display substrate may further include a timing controller and a source driving circuit located in the non-display area.

[0075] In an exemplary embodiment, the timing controller can supply gradation values ​​and control signals that conform to the specifications of the source drive circuit to the source drive circuit, supply a clock signal and a scan start signal, etc. that conform to the specifications of the scan drive circuit to the scan drive circuit, supply a clock signal and a control start signal, etc. that conform to the specifications of the control drive circuit to the control drive circuit, and supply a clock signal and a light emission stop signal, etc. that conform to the specifications of the light emission drive circuit to the light emission drive circuit.

[0076] In an exemplary embodiment, the source driving circuit may generate data voltages to be supplied to the data signal lines using the gray scale values ​​and control signals received from the timing controller, For example, the source driving circuit may sample gray scale values ​​using a clock signal and apply data voltages corresponding to the gray scale values ​​to the data signal lines in units of pixel rows.

[0077] In an exemplary embodiment, the scan driving circuit can generate a scan signal to be supplied to the scan signal line by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan driving circuit can sequentially supply a scan signal having an on-level pulse to the scan signal line. For example, the scan driving circuit may be configured as a shift register, and generate a scan signal so as to transfer the scan start signal, which is supplied in the form of an on-level pulse, to a next-stage circuit under the control of a clock signal.

[0078] In an exemplary embodiment, the control drive circuit can generate a control signal to be supplied to the control signal line by receiving a clock signal, a control start signal, etc. from the timing controller. For example, the control drive circuit can sequentially supply a control signal having an on-level pulse to the control signal line. For example, the control drive circuit may be configured as a shift register, and generate a control signal to transfer the control start signal, which is sequentially supplied in the form of an on-level pulse under the control of the clock signal, to a next-stage circuit.

[0079] In an exemplary embodiment, the light emission drive circuit can generate a light emission signal to be supplied to a light emission signal line by receiving a clock signal, a light emission stop signal, etc. from a timing controller. For example, the light emission drive circuit can sequentially supply a light emission signal having a cutoff level pulse to the light emission signal line. For example, the light emission drive circuit may be configured as a shift register, and generate a light emission signal so as to transfer the light emission stop signal, which is supplied in the form of a cutoff level pulse in sequence under the control of a clock signal, to a next stage circuit.

[0080] a control driving circuit configured to supply a driving signal to the reset transistor; the circuit structure layer further includes a plurality of reset output lines and a plurality of reset transfer lines located in the non-display area and disposed on a side of the control driving circuit closer to the display area, the reset output lines being disposed in a different layer from the reset transfer lines, the extension direction of the reset output lines intersects with the extension direction of the reset transfer lines, the reset output lines are electrically connected to the control driving circuit and the reset transfer line, respectively, and the reset transfer line is connected to the pixel circuit; and there is an overlapping portion between the orthogonal projection at the base of the at least one reset transfer line located in the rounded corner area and the orthogonal projection at the base of the plurality of reset output lines. In the present disclosure, there is an overlap between the orthogonal projection at the base of at least one reset transfer line located in the rounded corner region and the orthogonal projection at the bases of multiple reset output lines, thereby reducing the area occupied by the rounded corner region and achieving a narrower frame.

[0081] In an exemplary embodiment, as shown in Figures 4 and 5, the circuit structure layer may further include a reset connection line RST_CL located in the non-display area and installed on the side closer to the display area of ​​the control driving circuit, the reset connection line RST_CL is installed in a different layer from the reset output line RST_OL, and the extension direction of the reset connection line RST_CL intersects with the extension direction of the reset output line RST_OL.

[0082] In an exemplary embodiment, the reset connection line RST_CL is electrically connected to the reset transfer line RST_TL and the reset signal line, respectively, as shown in Figures 4 and 5. The control drive circuit is electrically connected to the reset signal line of the pixel circuit through the reset output line, the reset transfer line, and the reset connection line in sequence.

[0083] In an exemplary embodiment, as shown in FIGS. 4 and 5, the reset connection line RST_CL may be installed in a different layer from the reset signal line.

[0084] In an exemplary embodiment, as shown in Fig. 4, at least one reset connection line RST_CL located in the rounded corner region and the multiple reset output lines RST_OL may have an overlapping portion when orthogonally projected onto the base. By having an overlapping portion when at least one reset connection line RST_CL located in the rounded corner region and the multiple reset output lines RST_OL are orthogonally projected onto the base, it is possible to reduce the area occupied by the rounded corner region and realize a narrower frame.

[0085] In an exemplary embodiment, the control drive circuit may be further configured to provide a drive signal to the write transistor.

[0086] In an exemplary embodiment, as shown in Figures 4 and 5, the circuit structure layer may further include a plurality of control output lines G_OL located in the non-display area and arranged on the side closer to the display area of ​​the control driving circuit, the control output lines are arranged in a different layer from the reset output lines RST_OL, and the extension direction G_OL of the control output lines G_OL intersects with the extension direction of the reset output lines RST_OL.

[0087] In an exemplary embodiment, as shown in Figures 4 and 5, the control output line G_OL is connected to a control drive circuit and a pixel circuit, respectively, and there is an overlap between the orthogonal projection at the base of the control output line G_OL and the orthogonal projection at the bases of multiple reset output lines RST_OL.

[0088] In an exemplary embodiment, as shown in Figures 4 and 5, the circuit structure layer further includes a control connecting line G_CL located in the non-display area and installed on the side closer to the display area of ​​the control driving circuit, the control connecting line G_CL is installed in a different layer from the reset output line RST_OL, and the extension direction of the control connecting line G_CL intersects with the extension direction of the reset output line RST_OL.

[0089] In an exemplary embodiment, the control connecting line G_CL may be electrically connected to the control output line G_OL and the control signal line, respectively, as shown in Figures 4 and 5. The control driving circuit is in turn electrically connected to the control signal line of the pixel circuit through the control output line and the control connecting line.

[0090] In an exemplary embodiment, the control connection line G_CL may be installed in a different layer from the control signal line.

[0091] In an exemplary embodiment, as shown in Fig. 4, at least one control connection line G_CL located in the rounded corner region and the multiple reset output lines RST_OL may have an overlapping portion when orthogonally projected onto the base. By having an overlapping portion when at least one control connection line G_CL located in the rounded corner region and the multiple reset output lines RST_OL are orthogonally projected onto the base, it is possible to reduce the area occupied by the rounded corner region and realize a narrower frame.

[0092] Fig. 7 is a partial cascade schematic diagram of a driving circuit according to an exemplary embodiment, as shown in Fig. 7, the control driving circuit includes a plurality of control shift registers GateP cascaded together, and the control shift registers include output terminals. The output terminal of the control shift register GateP(i) of the i-th stage is electrically connected to the i-th reset output line RST_OL, where 1≦i≦M, and the output terminal of the control shift register GateP(j) of the j-th stage is electrically connected to the jS-th control output line G_OL, where S+1≦j≦M+S, where M is the total number of rows of pixel circuits, and S≧1. Fig. 7 is explained by taking S=14 as an example.

[0093] In an exemplary embodiment, as shown in Figures 4 and 5, the reset output line RST_OL and the control output line G_OL, which are connected to the output terminal of the same control shift register, are connected to each other, and there may be an overlapping portion between the orthogonal projection at the base of the reset output line RST_OL and the orthogonal projection at the base of the control output line G_OL.

[0094] In an exemplary embodiment, as shown in Figures 3 and 7, the circuit structure layer may further include an emission driving circuit located in the non-display area, where the emission driving circuit is located on the side away from the display area of ​​the control driving circuit, and the emission driving circuit is configured to provide a driving signal to the emission transistor.

[0095] In an exemplary embodiment, as shown in Figures 4 and 5, the circuit structure layer may further include a plurality of light-emitting output lines EM_OL located in the non-display area and arranged on the side closer to the display area of ​​the control driving circuit, the light-emitting output lines EM_OL are arranged in a different layer from the reset output lines RST_OL, and the extension direction of the light-emitting output lines EM_OL intersects with the extension direction of the reset output lines RST_OL.

[0096] In an exemplary embodiment, as shown in Figures 4 and 5, the light-emitting output line EM_OL is connected to the light-emitting drive circuit and the pixel circuit, respectively, and there is an overlapping portion between the orthogonal projection at the base of the light-emitting output line EM_OL and the orthogonal projection at the bases of the multiple reset output lines RST_OL.

[0097] In an exemplary embodiment, as shown in Figures 4 and 5, the circuit structure layer further includes an emission connecting line E_CL located in the non-display area and installed on the side of the control driving circuit closer to the display area, the emission connecting line E_CL is installed in a layer different from the reset output line RST_OL, and the extension direction of the emission connecting line E_CL intersects with the extension direction of the reset output line RST_OL.

[0098] In an exemplary embodiment, as shown in Figures 4 and 5, the light emitting connection line E_CL is electrically connected to the light emitting output line E_OL and the light emitting signal line, respectively. The light emitting driving circuit is electrically connected to the light emitting signal line of the pixel circuit through the light emitting output line and the light emitting connection line in sequence.

[0099] In an exemplary embodiment, the light emitting connection lines E_CL are disposed in a different layer from the light emitting signal lines.

[0100] In an exemplary embodiment, as shown in Fig. 4, at least one light emitting connecting line E_CL and multiple reset output lines RST_OL located in the rounded corner region may have an overlapping portion when orthogonally projected onto the base. By having an overlapping portion when at least one light emitting connecting line E_CL and multiple reset output lines RST_OL located in the rounded corner region are orthogonally projected onto the base, it is possible to reduce the area occupied by the rounded corner region and realize a narrower frame.

[0101] In an exemplary embodiment, as shown in Fig. 7, the light emission drive circuit includes a plurality of cascaded light emission shift registers EM(1) to EM(K1), and the light emission shift registers include output terminals. The output terminals of at least one stage of the light emission shift register are electrically connected to a plurality of light emission output lines E_OL. Figs. 4, 5 and 7 will be described taking an example in which the output terminals of one stage of the light emission shift register are electrically connected to two light emission output lines E_OL.

[0102] In an exemplary embodiment, as shown in Figures 4 and 5, when the light-emitting shift register is electrically connected to at least two light-emitting output lines E_OL, the circuit structure layer may include a light-emitting connection part E_CN located in the non-display area and installed on the side closer to the display area of ​​the control driving circuit, the light-emitting connection part E_CN is installed in a layer different from the light-emitting output lines E_OL, and the extension direction of the light-emitting connection part E_CN intersects with the extension direction of the light-emitting output lines E_OL.

[0103] In an exemplary embodiment, as shown in FIG. 4 and FIG. 5, at least two light-emitting output lines E_OL connected to the same light-emitting shift register may be electrically connected via a light-emitting connection E_CN.

[0104] In an exemplary embodiment, as shown in FIGS. 4 and 5, the light emitting connections E_CN may be located on the side of the reset output lines RST_OL away from the display area.

[0105] In an exemplary embodiment, as shown in Figures 3 and 7, the circuit structure layer may further include a scanning driving circuit located in the non-display area, where the scanning driving circuit is located between the control driving circuit and the emission driving circuit, and the scanning driving circuit is configured to supply a driving signal to the compensation transistor.

[0106] In an exemplary embodiment, as shown in Figures 4 and 5, the circuit structure layer may further include a plurality of scanning output lines S_OL located in the non-display area and arranged on a side closer to the display area of ​​the control driving circuit, where the scanning output lines S_OLv are arranged in a different layer from the reset output lines RST_OL, and the extension direction of the scanning output lines S_OL intersects with the extension direction of the reset output lines RST_OL.

[0107] In an exemplary embodiment, as shown in Figures 4 and 5, the scanning output line S_OL is connected to a scanning driving circuit and a pixel circuit, respectively, and there is an overlap between the orthogonal projection at the base of the scanning output line S_OL and the orthogonal projection at the base of the multiple reset output lines RST_OL.

[0108] In an exemplary embodiment, as shown in Figures 4 and 5, the circuit structure layer may further include a scanning connection line S_CL located in the non-display area and installed on the side closer to the display area of ​​the control driving circuit, the scanning connection line S_CL is installed in a different layer from the reset output line RST_OL, and the extension direction of the scanning connection line S_CL intersects with the extension direction of the reset output line RST_OL.

[0109] In an exemplary embodiment, the scanning connection line S_CL is electrically connected to the scanning output line S_OL and the scanning signal line, respectively, as shown in Figure 4 and Figure 5. The scanning driving circuit is sequentially electrically connected to the scanning signal line of the pixel circuit through the scanning output line and the scanning connection line.

[0110] In an exemplary embodiment, as shown in FIG. 4 and FIG. 5, the scan connection lines S_CL are disposed in a different layer from the scan signal lines.

[0111] In an exemplary embodiment, as shown in Fig. 4, at least one scanning connection line S_CL and multiple reset output lines RST_OL located in the rounded corner region may have an overlapping portion when orthogonally projected onto the base. By having an overlapping portion when at least one scanning connection line S_CL and multiple reset output lines RST_OL located in the rounded corner region are orthogonally projected onto the base, it is possible to reduce the area occupied by the rounded corner region and realize a narrower frame.

[0112] In an exemplary embodiment, as shown in Fig. 7, the scan driving circuit includes a plurality of cascaded scan shift registers GateN(1) to GateN(K2), and the scan shift registers include output terminals. The output terminals of at least one stage of the scan shift register may be electrically connected to a plurality of scan output lines S_OL. Figs. 4, 5 and 7 will be described taking as an example that the output terminals of one stage of the scan shift register are electrically connected to two scan output lines S_OL.

[0113] In an exemplary embodiment, as shown in Figures 4 and 5, when the scanning shift register is electrically connected to at least two scanning output lines S_OL, the circuit structure layer further includes a scanning connection part S_CN located in the non-display area and installed on a side of the control driving circuit closer to the display area, the scanning connection part S_CN is installed in a layer different from the scanning output lines S_OL, and the extension direction of the scanning connection part S_CN intersects with the extension direction of the scanning output lines S_OL.

[0114] In an exemplary embodiment, as shown in FIGS. 4 and 5, at least two scan output lines S_OL connected to the same scan shift register may be electrically connected via a scan connection S_CN.

[0115] In an exemplary embodiment, as shown in FIGS. 4 and 5, the scan connections S_CN may be located on the side of the reset output lines RST_OL away from the display area.

[0116] In an exemplary embodiment, as shown in Figures 4 and 5, the circuit structure layer may further include a plurality of first initial output lines INIT1_OL located in the non-display area and arranged on a side closer to the display area of ​​the control driving circuit, the first initial output lines INIT1_OL are arranged in a different layer from the reset output lines RST_OL, and the extension direction of the first initial output lines INIT1_OL intersects with the extension direction of the reset output lines RST_OL.

[0117] In an exemplary embodiment, as shown in FIGS. 4 and 5, the first initial output line INIT1_OL may be electrically connected to one of the first initial signal line and the second initial signal line of the pixel circuit.

[0118] In an exemplary embodiment, there is an overlap between the orthogonal projection of the first initial output line INIT1_OL at the base and the orthogonal projection of the plurality of reset output lines RST_OL at the base.

[0119] In an exemplary embodiment, as shown in Figures 4 and 5, the circuit structure layer further includes a plurality of first initial connection lines INIT1_CL located in the non-display area and arranged on a side closer to the display area of ​​the control driving circuit, the first initial connection lines INIT1_CL are arranged in a different layer from the reset output lines RST_OL, and the extension direction of the first initial connection lines INIT1_CL intersects with the extension direction of the reset output lines RST_OL.

[0120] In an exemplary embodiment, as shown in Figures 4 and 5, the first initial output line INIT1_OL is electrically connected to one of the first initial signal line and the second initial signal line of the pixel circuit via the first initial connection line INIT1_CL.

[0121] In an exemplary embodiment, as shown in Fig. 4, there may be an overlapping portion between the orthogonal projection at the base of the first initial connection line INIT1_CL located in the rounded corner region and the orthogonal projection at the base of the multiple reset output lines RST_OL. By having an overlapping portion between the orthogonal projection at the base of the first initial connection line INIT1_CL located in the rounded corner region and the orthogonal projection at the base of the multiple reset output lines RST_OL, it is possible to reduce the area occupied by the rounded corner region and realize a narrower frame.

[0122] In an exemplary embodiment, as shown in Figures 4 and 5, the circuit structure layer may further include a first initial power supply line INIT1_SL located in the non-display area and installed on a side closer to the display area of ​​the control driving circuit, the first initial power supply line INIT1_SL is installed in a layer different from the reset output line RST_OL, and the extension direction of the first initial power supply line INIT1_SL is parallel to the extension direction of the reset output line RST_OL.

[0123] In an exemplary embodiment, as shown in Figures 4 and 5, the first initial power supply line INIT1_SL is electrically connected to a plurality of first initial output lines INIT1_OL. The first initial power supply line INIT1_SL is electrically connected to the first initial signal line of the pixel circuit via the first initial output line INIT1_OL and the first initial connection line INIT1_CL.

[0124] In an exemplary embodiment, the first initial power supply line INIT1_SL is installed in a different layer from the first initial output line INIT1_OL.

[0125] In an exemplary embodiment, as shown in FIGS. 4 and 5, the orthogonal projection of the first initial power supply line INIT1_SL at the base at least partially overlaps with the orthogonal projection of the multiple reset output lines RST_OL at the base.

[0126] In an exemplary embodiment, as shown in Figures 4 and 5, the circuit structure layer may further include a plurality of second initial connection lines INIT2_CL located in the non-display area and arranged on a side closer to the display area of ​​the control driving circuit, the second initial connection lines INIT2_CL are arranged in a different layer from the reset output line RST_OL, the extension direction of the second initial connection line INIT2_CL intersects with the extension direction of the reset output line RST_OL, and the extension direction of the first initial connection line INIT1_CL is parallel to the extension direction of the second initial connection line INIT2_CL.

[0127] In an exemplary embodiment, the second initial connection line INIT2_CL may be electrically connected to the other one of the first initial signal line and the second initial signal line of the pixel circuit, as shown in Figures 4 and 5. When the second initial connection line INIT2_CL is electrically connected to the first initial signal line, the first initial connection line INIT1_CL is electrically connected to the second initial signal line, and when the second initial connection line INIT2_CL is electrically connected to the second initial signal line, the first initial connection line INIT1_CL is electrically connected to the first initial signal line, and the present disclosure is not limited thereto.

[0128] In an exemplary embodiment, as shown in FIGS. 4 and 5, there is an overlap between the orthogonal projection of the second initial connection line INIT2_CL at the base and the orthogonal projection of the multiple reset output lines RST_OL at the base.

[0129] In an exemplary embodiment, as shown in Figures 4 and 5, the circuit structure layer may further include a second initial supply line INIT2_SL located in the non-display area and arranged on a side closer to the display area of ​​the control driving circuit, where the second initial supply line INIT2_SL is arranged in a different layer from the reset output line RST_OL and arranged in the same layer as the second initial connection line INIT2_CL, the extending direction of the first initial supply line INIT1_SL is parallel to the extending direction of the second initial supply line INIT2_SL, and the second initial supply line INIT2_SL is arranged on the side closer to the display area of ​​the first initial supply line INIT1_SL.

[0130] In an exemplary embodiment, as shown in FIGS. 4 and 5, the second initial power supply line INIT2_SL may be integrally formed with the second initial connection line INIT2_CL.

[0131] In an exemplary embodiment, as shown in Figures 4 and 5, the second initial power supply line INIT2_SL is electrically connected to a plurality of second initial connection lines INIT2_CL, and the orthogonal projection at a base of the second initial power supply line INIT2_SL at least partially overlaps with the orthogonal projection at a base of the plurality of reset output lines RST_OL.

[0132] 8 is a structural schematic diagram of a round corner region of a display substrate according to an exemplary embodiment. As shown in FIG. 8, in the exemplary embodiment, the multi-stage control shift register GateP located in the round corner region may be arranged along the boundary of the round corner.

[0133] In an exemplary embodiment, as shown in FIG. 8, the multi-stage light emitting shift registers EM located in the rounded corner area may be arranged along the border of the rounded corner.

[0134] In an exemplary embodiment, as shown in FIG. 8, a multi-stage scan shift register GateN located in a round corner area is arranged along the boundary of the round corner.

[0135] In an exemplary embodiment, as shown in Fig. 8, the display substrate may further include a low-level power line VSSL located on the side of the light-emitting driving circuit away from the display area AA. The low-level power line VSSL is electrically connected to the cathode of the light-emitting element and is configured to supply a low level to the cathode of the light-emitting element.

[0136] In an exemplary embodiment, the display substrate may further include an electrostatic discharge circuit ESD located in the non-display area, as shown in Figure 8. The electrostatic discharge circuit may be configured to discharge the electrostatic charge of a plurality of driving circuits.

[0137] In an exemplary embodiment, the light emission shift register EM may include a plurality of light emission transistors and a plurality of light emission capacitors. The circuit structure of the light emission shift register may be 13T3C or 10T3C, and the present disclosure is not limited thereto.

[0138] In an exemplary embodiment, the scan shift register GateN may include a plurality of scan transistors and a plurality of scan capacitors. The circuit structure of the scan shift register may be 13T3C or 10T3C, and the present disclosure is not limited thereto.

[0139] In an exemplary embodiment, the control shift register GateP includes a plurality of control transistors and a plurality of control capacitors, and the circuit structure of the control shift register may be 8T2C, and the present disclosure is not limited thereto.

[0140] Fig. 9A is an equivalent circuit diagram of an emission shift register according to an exemplary embodiment, and Fig. 9B is a timing chart of the emission shift register of Fig. 9A. As shown in Fig. 9 and Fig. 9B, in an exemplary embodiment, the emission shift register includes a first emission transistor ET1 to a thirteenth emission transistor ET13 and a first emission capacitor EC1 to a third emission capacitor EC3.

[0141] In an exemplary embodiment, the control pole of the first light emitting transistor ET1 is electrically connected to the third clock signal terminal ECK3, the first pole of the first light emitting transistor ET1 is electrically connected to the input terminal EIN, and the second pole of the first light emitting transistor ET1 is electrically connected to the first node E1. The control pole of the second light emitting transistor ET2 is electrically connected to the first node E1, the first pole of the second light emitting transistor ET2 is electrically connected to the third clock signal terminal ECK3, and the second pole of the second light emitting transistor ET2 is electrically connected to the second node E2. The control pole of the third light emitting transistor ET3 is electrically connected to the third clock signal terminal ECK3, the first pole of the third light emitting transistor ET3 is electrically connected to the second power supply terminal VGL, and the second pole of the third light emitting transistor ET3 is electrically connected to the second node E2. The control electrode of the fourth light-emitting transistor ET4 is electrically connected to the third node E3, the first electrode of the fourth light-emitting transistor ET4 is electrically connected to the first clock signal terminal ECK1, and the second electrode of the fourth light-emitting transistor ET4 is electrically connected to the fifth node E5. The control electrode of the fifth light-emitting transistor ET5 is electrically connected to the fourth node E4, the first electrode of the fifth light-emitting transistor ET5 is electrically connected to the fifth node E5, and the second electrode of the fifth light-emitting transistor ET5 is electrically connected to the first power supply terminal VGH. The control electrode of the sixth light-emitting transistor ET6 is electrically connected to the fourth node E4, the first electrode of the sixth light-emitting transistor ET6 is electrically connected to the first clock signal terminal ECK1, and the second electrode of the sixth light-emitting transistor ET6 is electrically connected to the sixth node E6. The control electrode of the seventh light-emitting transistor ET7 is electrically connected to the first clock signal terminal ECK1, the first electrode of the seventh light-emitting transistor ET7 is electrically connected to the sixth node E6, and the second electrode of the seventh light-emitting transistor ET7 is electrically connected to the seventh node E7. The control electrode of the eighth light-emitting transistor ET8 is electrically connected to the first node E1, the first electrode of the eighth light-emitting transistor ET8 is electrically connected to the first power supply terminal VGH, and the second electrode of the eighth light-emitting transistor ET8 is electrically connected to the seventh node E7.The control electrode of the ninth light-emitting transistor ET9 is electrically connected to the seventh node E7, the first electrode of the ninth light-emitting transistor ET9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth light-emitting transistor ET9 is electrically connected to the output terminal EOUT. The control electrode of the tenth light-emitting transistor ET10 is electrically connected to the third node E3, the first electrode of the tenth light-emitting transistor ET10 is electrically connected to the second power supply terminal VGL, and the second electrode of the tenth light-emitting transistor ET10 is electrically connected to the output terminal EOUT. The control electrode of the eleventh light-emitting transistor ET11 is electrically connected to the second power supply terminal VGL, the first electrode of the eleventh light-emitting transistor ET11 is electrically connected to the second node E2, and the second electrode of the eleventh light-emitting transistor ET11 is electrically connected to the fourth node E4. The control electrode of the twelfth light-emitting transistor ET12 is electrically connected to the second power supply terminal VGL, the first electrode of the twelfth light-emitting transistor ET12 is electrically connected to the first node E1, and the second electrode of the twelfth light-emitting transistor ET12 is electrically connected to the third node E3. The control electrode of the thirteenth light-emitting transistor ET13 is electrically connected to the second clock signal terminal ECK2, the first electrode of the thirteenth light-emitting transistor ET13 is electrically connected to the first node E1, and the second electrode of the thirteenth light-emitting transistor ET13 is electrically connected to the first power supply terminal VGH. The first electrode plate EC11 of the first light-emitting capacitor EC1 is electrically connected to the fourth node E4, and the second electrode plate EC12 of the first light-emitting capacitor EC1 is electrically connected to the sixth node E6. The first electrode plate EC21 of the second light-emitting capacitor EC2 is electrically connected to the seventh node E7, and the second electrode plate EC22 of the second light-emitting capacitor EC2 is electrically connected to the first power supply terminal VGH. A first plate EC31 of the third light-emitting capacitor EC3 is electrically connected to the third node E3, and a second plate EC32 of the third light-emitting capacitor EC3 is electrically connected to the fifth node E5.

[0142] In an exemplary embodiment, the first light emitting transistor ET1 to the thirteenth light emitting transistor ET13 may be a P-type transistor or an N-type transistor.

[0143] In an exemplary embodiment, the first power supply terminal VGH continues to supply a high level signal, and the second power supply terminal VGL continues to supply a low level signal. Since the second power supply terminal VGL continues to supply a low level signal, the eleventh light emitting transistor ET11 and the twelfth light emitting transistor ET12 continue to be turned on.

[0144] In an exemplary embodiment, the second clock signal terminal ECK2 is a low-level signal in the power-on initialization stage, which prevents the ninth light-emitting transistor ET9 and the tenth light-emitting transistor ET10 of the final stage light-emitting shift register from being simultaneously turned on due to a delay in the output signal, and is a low-level signal in the abnormal shutdown stage, which prevents the ninth light-emitting transistor ET9 and the tenth light-emitting transistor ET10 from being simultaneously turned on. The second clock signal terminal ECK2 continues to supply a high-level signal in the normal display stage, i.e., the thirteenth light-emitting transistor ET13 continues to be turned off in the normal display stage.

[0145] Taking the first light emitting transistor ET1 to the thirteenth light emitting transistor ET13 as an example being P-type transistors, as shown in FIG. 9B, the operation process of the light emitting shift register according to the exemplary embodiment includes the following steps.

[0146] In the first stage B1, the signal at the first clock signal terminal ECK1 is a high level signal, the signal at the third clock signal terminal ECK3 is a low level signal, the signal at the third clock signal terminal ECK3 is a low level signal, the first light emitting transistor ET1, the third light emitting transistor ET3 and the twelfth light emitting transistor ET12 are turned on, the turned-on first light emitting transistor ET1 transfers the high level signal at the input terminal EIN to the first node E1 to make the level of the first node E1 a high level signal, the turned-on twelfth light emitting transistor ET12 transfers the high level signal at the first node E1 to the third node E2, and the second light emitting transistor ET2, the fourth light emitting transistor ET4, the eighth light emitting transistor ET8 and the tenth light emitting transistor ET10 are turned off. Also, the turned-on third light emitting transistor ET3 transfers the low level signal of the third power supply terminal VGL to the second node E2 to make the level of the second node E2 low, and the turned-on eleventh light emitting transistor ET11 transfers the low level signal of the second node E2 to the fourth node E4 to make the level of the fourth node E4 low, and the fifth light emitting transistor ET5 and the sixth light emitting transistor ET6 are turned on. The signal of the first clock signal terminal ECK1 is a high level signal, and the seventh light emitting transistor ET7 is turned off. Also, the ninth light emitting transistor ET9 is turned off by the third light emitting capacitor EC3. In the first stage P1, since the ninth light emitting transistor ET9 and the tenth light emitting transistor ET10 are both turned off, the signal of the output terminal EOUT remains at the previous low level.

[0147] In the second stage B2, the signal of the first clock signal terminal ECK1 is a low level signal, and the signal of the third clock signal terminal ECK3 is a high level signal. The signal of the first clock signal terminal ECK1 is a low level signal, and the seventh light emitting transistor ET7 is turned on. The signal of the third clock signal terminal ECK3 is a high level signal, and the first light emitting transistor ET1 and the third light emitting transistor ET3 are turned off. Due to the action of the third light emitting capacitor EC3, the first node E1 and the third node E3 can continue to hold the high level signal of the previous stage, and due to the action of the first light emitting capacitor EC1, the fourth node E4 can continue to hold the low level signal of the previous stage, so the fifth light emitting transistor ET5 and the sixth light emitting transistor ET6 are turned on. The second light emitting transistor ET2, the fourth light emitting transistor ET4, the eighth light emitting transistor ET8, and the tenth light emitting transistor ET10 are turned off. In addition, the low-level signal of the first clock signal terminal ECK1 is transferred to the seventh node E7 via the sixth light-emitting transistor ET6 and the seventh light-emitting transistor ET7 that are turned on, the ninth light-emitting transistor ET9 is turned on, and the turned-on ninth light-emitting transistor ET9 outputs a high-level signal of the first power supply terminal VGH, so that the signal of the output terminal EOUT is a high-level signal.

[0148] In the third stage B3, the signal at the third clock signal terminal ECK3 is a low level signal, and the signal at the first clock signal terminal ECK1 is a high level signal. The signal at the first clock signal terminal ECK1 is a high level signal, and the seventh light emitting transistor ET7 is turned off. The second light emitting transistor ET2, the fourth light emitting transistor ET4, the eighth light emitting transistor ET8, and the tenth light emitting transistor ET10 are turned off. The signal at the third clock signal terminal ECK3 is a low level signal, and the first light emitting transistor ET1 and the third light emitting transistor ET3 are turned on. Due to the action of the second light emitting capacitor EC3, the ninth light emitting transistor ET9 maintains an on state, and the turned-on ninth light emitting transistor ET9 outputs a high level signal at the first power supply terminal VGH, so that the signal at the output terminal EOUT remains at a high level.

[0149] In the fourth stage B4, the signal of the first clock signal terminal ECK1 is a low level signal, and the signal of the third clock signal terminal ECK3 is a high level signal. The signal of the third clock signal terminal ECK3 is a high level signal, and the first light emitting transistor ET1 and the third light emitting transistor ET3 are turned off. The signal of the first clock signal terminal ECK1 is a low level, and the seventh light emitting transistor ET7 is turned on. Due to the accumulation effect of the third light emitting capacitor EC3, the levels of the first node E1 and the third node E3 maintain the high level signal of the previous stage, and the second light emitting transistor ET2, the fourth light emitting transistor ET4, the eighth light emitting transistor ET8, and the tenth light emitting transistor ET10 are turned off. Due to the accumulation effect of the first light emitting capacitor EC1, the fourth node E4 continues to maintain the low level of the previous stage, and the fifth light emitting transistor ET5 and the sixth light emitting transistor ET6 are turned on. In addition, the low-level signal of the first clock signal terminal ECK1 is transferred to the seventh node E7 via the sixth light-emitting transistor ET6 and the seventh light-emitting transistor ET7 that are turned on, and the ninth light-emitting transistor ET9 that is turned on outputs a high-level signal of the first power supply terminal VGH, so that the signal of the output terminal EOUT remains at a high level.

[0150] In the fifth stage B5, the signal of the first clock signal terminal ECK1 is a high level signal, and the signal of the third clock signal terminal ECK3 is a low level signal. The signal of the third clock signal terminal ECK3 is a low level signal, and the first light emitting transistor ET1 and the third light emitting transistor ET3 are turned on. The signal of the first clock signal terminal ECK1 is a high level signal, and the seventh light emitting transistor ET7 is turned off. The first light emitting transistor ET1 that is turned on transfers the low level signal of the input terminal EIN to the first node E1 to make the level of the first node E1 low, the twelfth light emitting transistor ET12 that is turned on transfers the low level signal of the first node E1 to the third node E3 to make the level of the third node E3 low, and the second light emitting transistor ET2, the fourth light emitting transistor ET4, the eighth light emitting transistor ET8 and the tenth light emitting transistor ET10 are turned on. The second light emitting transistor ET2 that is turned on transfers the low-level signal of the third clock signal terminal ECK3 to the second node E2, and the level of the second node E2 can be further lowered, so that the second node E2 and the fourth node E4 continue to maintain the low level of the previous stage, and the fifth light emitting transistor ET5 and the sixth light emitting transistor ET6 are turned on. The signal of the first clock signal terminal ECK1 is a high-level signal, and the seventh light emitting transistor ET7 is turned off. In addition, the eighth light emitting transistor ET8 that is turned on transfers the high-level signal of the first power supply terminal VGH to the seventh node E7, and the ninth light emitting transistor ET9 is turned off. The tenth light emitting transistor ET10 that is turned on outputs a low-level signal of the second power supply terminal VGL, so that the signal of the output terminal EOUT becomes low level.

[0151] FIG 10A is an equivalent circuit diagram of a scan shift register according to an exemplary embodiment, and FIG 10B is a timing chart of the scan shift register of FIG 10A. As shown in FIG 10A and FIG 10B, in an exemplary embodiment, the scan shift register may include a first scan transistor ST1 to a thirteenth scan transistor ST13 and a first scan capacitor SC1 to a third scan capacitor SC3.

[0152] In an exemplary embodiment, the control electrode of the first scan transistor ST1 is electrically connected to the third clock signal terminal SCK3, the first electrode of the first scan transistor ST1 is electrically connected to the input terminal SIN, and the second electrode of the first scan transistor ST1 is electrically connected to the first node S1. The control electrode of the second scan transistor ST2 is electrically connected to the first node S1, the first electrode of the second scan transistor ST2 is electrically connected to the third clock signal terminal SCK3, and the second electrode of the second scan transistor ST2 is electrically connected to the second node S2. The control electrode of the third scan transistor ST3 is electrically connected to the third clock signal terminal SCK3, the first electrode of the third scan transistor ST3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third scan transistor ST3 is electrically connected to the second node S2. The control electrode of the fourth scan transistor ST4 is electrically connected to the third node S3, the first electrode of the fourth scan transistor ST4 is electrically connected to the first clock signal terminal SCK1, and the second electrode of the fourth scan transistor ST4 is electrically connected to the fifth node S5. The control electrode of the fifth scan transistor ST5 is electrically connected to the fourth node S4, the first electrode of the fifth scan transistor ST5 is electrically connected to the fifth node S5, and the second electrode of the fifth scan transistor ST5 is electrically connected to the first power supply terminal VGH. The control electrode of the sixth scan transistor ST6 is electrically connected to the fourth node S4, the first electrode of the sixth scan transistor ST6 is electrically connected to the first clock signal terminal SCK1, and the second electrode of the sixth scan transistor ST6 is electrically connected to the sixth node S6. The control electrode of the seventh scan transistor ST7 is electrically connected to the first clock signal terminal SCK1, the first electrode of the seventh scan transistor ST7 is electrically connected to the sixth node S6, and the second electrode of the seventh scan transistor ST7 is electrically connected to the seventh node S7. The control electrode of the eighth scanning transistor ST8 is electrically connected to the first node S1, the first electrode of the eighth scanning transistor ST8 is electrically connected to the first power supply terminal VGH, and the second electrode of the eighth scanning transistor ST8 is electrically connected to the seventh node S7.The control electrode of the ninth scan transistor ST9 is electrically connected to the seventh node S7, the first electrode of the ninth scan transistor ST9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth scan transistor ST9 is electrically connected to the output terminal SOUT. The control electrode of the tenth scan transistor ST10 is electrically connected to the third node S3, the first electrode of the tenth scan transistor ST10 is electrically connected to the second power supply terminal VGL, and the second electrode of the tenth scan transistor ST10 is electrically connected to the output terminal SOUT. The control electrode of the eleventh scan transistor ST11 is electrically connected to the second power supply terminal VGL, the first electrode of the eleventh scan transistor ST11 is electrically connected to the second node S2, and the second electrode of the eleventh scan transistor ST11 is electrically connected to the fourth node S4. The control electrode of the twelfth scan transistor ST12 is electrically connected to the second power supply terminal VGL, the first electrode of the twelfth scan transistor ST12 is electrically connected to the first node S1, and the second electrode of the twelfth scan transistor ST12 is electrically connected to the third node S3. The control electrode of the thirteenth scan transistor ST13 is electrically connected to the second clock signal terminal SCK2, the first electrode of the thirteenth scan transistor ST13 is electrically connected to the first node S1, and the second electrode of the thirteenth scan transistor ST13 is electrically connected to the first power supply terminal VGH. The first plate SC11 of the first scan capacitor SC1 is electrically connected to the fourth node S4, and the second plate SC12 of the first scan capacitor SC1 is electrically connected to the sixth node S6. The first plate SC21 of the second scan capacitor SC2 is electrically connected to the seventh node S7, and the second plate SC22 of the second scan capacitor SC2 is electrically connected to the first power supply terminal VGH. A first plate SC31 of the third scanning capacitor SC3 is electrically connected to the third node S3, and a second plate SC32 of the third scanning capacitor SC3 is electrically connected to a fifth node S5.

[0153] In an exemplary embodiment, the first scan transistor ST1 to the thirteenth scan transistor ST13 may be P-type transistors or N-type transistors. The tenth scan transistor ST10 is an output transistor.

[0154] In an exemplary embodiment, the first power supply terminal VGH continues to supply a high level signal, and the second power supply terminal VGL continues to supply a low level signal. Since the second power supply terminal VGL continues to supply a low level signal, the eleventh scan transistor ST11 and the twelfth scan transistor ST12 continue to be turned on.

[0155] In an exemplary embodiment, the second clock signal terminal SCK2 is a low level signal in the power-on initialization stage to prevent the ninth scan transistor ST9 and the tenth scan transistor ST10 of the final stage scan shift register from being simultaneously turned on due to delay of the output signal, and is a low level signal in the abnormal shutdown stage to prevent the ninth scan transistor ST9 and the tenth scan transistor ST10 from being simultaneously turned on. The second clock signal terminal SCK2 continues to supply a high level signal in the normal display stage, i.e., keeps the thirteenth scan transistor ST13 off in the normal display stage.

[0156] Taking the first scan transistor ST1 to the thirteenth scan transistor ST13 as an example being P-type transistors, as shown in FIG. 10B, the operation process of the scan shift register according to the exemplary embodiment includes the following steps.

[0157] In the first stage C1, the signal of the first clock signal terminal SCK1 is a high level signal, the signal of the third clock signal terminal SCK3 is a low level signal, the signal of the third clock signal terminal SCK3 is a low level signal, the first scan transistor ST1, the third scan transistor ST3 and the twelfth scan transistor ST12 are turned on, the turned-on first scan transistor ST1 transfers the high level signal of the input terminal SIN to the first node S1 to make the level of the first node S1 a high level signal, the turned-on twelfth scan transistor ST12 transfers the high level signal of the first node S1 to the third node S2, and the second scan transistor ST2, the fourth scan transistor ST4, the eighth scan transistor ST8 and the tenth scan transistor ST10 are turned off. Also, the turned-on third scan transistor ST3 transfers the low level signal of the second power terminal VGL to the second node S2 to make the level of the second node S2 low, and the turned-on eleventh scan transistor ST11 transfers the low level signal of the second node S2 to the fourth node S4 to make the level of the fourth node S4 low, and the fifth scan transistor ST5 and the sixth scan transistor ST6 are turned on. The signal of the first clock signal line SCK1 is a high level signal, and the seventh scan transistor ST7 is turned off. Also, the ninth scan transistor ST9 is turned off by the third scan capacitor SC3. In the first stage P1, since both the ninth scan transistor ST9 and the tenth scan transistor ST10 are turned off, the signal of the output terminal SOUT remains at the previous low level.

[0158] In the second stage C2, the signal of the first clock signal terminal SCK1 is a low level signal, and the signal of the third clock signal terminal SCK3 is a high level signal. The signal of the first clock signal terminal SCK1 is a low level signal, and the seventh scan transistor ST7 is turned on. The signal of the third clock signal terminal SCK3 is a high level signal, and the first scan transistor ST1 and the third scan transistor ST3 are turned off. Due to the action of the third scan capacitor SC3, the first node S1 and the third node S3 can continue to hold the high level signal of the previous stage, and due to the action of the first scan capacitor SC1, the fourth node S4 can continue to hold the low level signal of the previous stage, so the fifth scan transistor ST5 and the sixth scan transistor ST6 are turned on. The second scan transistor ST2, the fourth scan transistor ST4, the eighth scan transistor ST8 and the tenth scan transistor ST10 are turned off. In addition, the low level signal of the first clock signal terminal SCK1 is transferred to the seventh node S7 via the sixth scan transistor ST6 and the seventh scan transistor ST7 that are turned on, and the ninth scan transistor ST9 is turned on. The turned-on ninth scan transistor ST9 outputs a high level signal of the first power supply terminal VGH, so that the signal of the output terminal SOUT is a high level signal.

[0159] In the third stage C3, the signal at the third clock signal terminal SCK3 is a low level signal, and the signal at the first clock signal terminal SCK1 is a high level signal. The signal at the first clock signal terminal SCK1 is a high level signal, and the seventh scan transistor ST7 is turned off. The second scan transistor ST2, the fourth scan transistor ST2, the eighth scan transistor ST8, and the tenth scan transistor ST10 are turned off. The signal at the third clock signal terminal SCK3 is a low level signal, and the first scan transistor ST1 and the third scan transistor ST3 are turned on. Due to the action of the third scan capacitor SC3, the ninth scan transistor ST9 maintains an on state, and the turned-on ninth scan transistor ST9 outputs a high level signal at the first power supply terminal VGH, so that the signal at the output terminal SOUT remains at a high level.

[0160] In the fourth stage C4, the signal of the first clock signal terminal SCK1 is a low level signal, and the signal of the third clock signal terminal SCK3 is a high level signal. The signal of the third clock signal terminal SCK3 is a high level signal, and the first scan transistor ST1 and the third scan transistor ST3 are turned off. The signal of the first clock signal terminal SCK1 is a low level, and the seventh scan transistor ST7 is turned on. Due to the storage effect of the third scan capacitor SC3, the levels of the first node S1 and the third node S3 maintain the high level signal of the previous stage, and the scan transistor ST2, the fourth scan transistor ST4, the eighth scan transistor ST8, and the tenth scan transistor ST10 are turned off. Due to the storage effect of the first scan capacitor SC1, the fourth node S4 continues to maintain the low level of the previous stage, and the fifth scan transistor ST5 and the sixth scan transistor ST6 are turned on. In addition, the low level signal of the first clock signal terminal SCK1 is transferred to the seventh node S7 via the sixth scan transistor ST6 and the seventh scan transistor ST7 that are turned on, and the ninth scan transistor ST9 that is turned on outputs a high level signal of the first power supply terminal VGH, so that the signal of the output terminal SOUT remains at a high level.

[0161] In the fifth stage C5, the signal of the first clock signal terminal SCK1 is a high level signal, and the signal of the third clock signal terminal SCK3 is a low level signal. The signal of the third clock signal terminal SCK3 is a low level signal, and the first scan transistor ST1 and the third scan transistor ST3 are turned on. The signal of the first clock signal terminal SCK1 is a high level signal, and the seventh scan transistor ST7 is turned off. The first scan transistor ST1 that is turned on transfers the low level signal of the input terminal SIN to the first node S1 to make the level of the first node S1 low, the twelfth scan transistor ST12 that is turned on transfers the low level signal of the first node S1 to the third node S3 to make the level of the third node S3 low, and the second scan transistor ST2, the fourth scan transistor ST4, the eighth scan transistor ST8, and the tenth scan transistor ST10 are turned on. The second scan transistor ST2, which is turned on, transfers the low-level signal of the third clock signal terminal SCK3 to the second node S2, and the level of the second node S2 can be further lowered, so that the second node S2 and the fourth node S4 continue to maintain the low level of the previous stage, and the fifth scan transistor ST5 and the sixth scan transistor ST6 are turned on. The signal of the first clock signal terminal SCK1 is a high-level signal, and the seventh scan transistor ST7 is turned off. In addition, the eighth scan transistor ST8, which is turned on, transfers the high-level signal of the first power supply terminal VGH to the seventh node S7, and the ninth scan transistor ST9 is turned off. The tenth scan transistor ST10, which is turned on, outputs the low-level signal of the second power supply terminal VGL, so that the signal of the output terminal SOUT becomes low.

[0162] Fig. 11A is an equivalent circuit diagram of a control shift register according to an exemplary embodiment, and Fig. 11B is a timing chart of the control shift register of Fig. 11A. As shown in Fig. 11A and Fig. 11B, the control shift register may include a first control transistor GT1 to an eighth control transistor GT8, a first control capacitor GC1 and a second control capacitor GC2.

[0163] In an exemplary embodiment, a control pole of the first control transistor GT1 is electrically connected to the first clock signal terminal CK, a first pole of the first control transistor GT1 is electrically connected to the input terminal GIN, a second pole of the first control transistor GT1 is electrically connected to a first node G1, a control pole of the second control transistor GT2 is electrically connected to the first node G1, a first pole of the second control transistor GT2 is electrically connected to the first clock signal terminal CK, a second pole of the second control transistor GT2 is electrically connected to a second node G2, and a control pole of the third control transistor GT3 is electrically connected to the first node G3. is electrically connected to the first clock signal terminal GGCK11, a first electrode of the third control transistor GT3 is electrically connected to the second power supply terminal VGL, a second electrode of the third control transistor GT3 is electrically connected to the second node G2, a control electrode of the fourth control transistor GT4 is electrically connected to the second node G2, a first electrode of the fourth control transistor GT4 is electrically connected to the first power supply terminal VGH, a second electrode of the fourth control transistor GT4 is electrically connected to the output terminal GOUT, a control electrode of the fifth control transistor GT5 is electrically connected to the third node G3, A first electrode of the fifth control transistor GT5 is electrically connected to the second clock signal terminal GCK2, a second electrode of the fifth control transistor GT5 is electrically connected to the output terminal GOUT, a control electrode of the sixth control transistor GT6 is electrically connected to the second node G2, a first electrode of the sixth control transistor GT6 is electrically connected to the first power supply terminal VGH, a second electrode of the sixth control transistor GT6 is electrically connected to the first electrode of the seventh control transistor GT7, a control electrode of the seventh control transistor GT7 is electrically connected to the second clock signal terminal GCK2, and a third electrode of the seventh control transistor GT7 is electrically connected to the second node G3. the second pole of the eighth control transistor GT8 is electrically connected to the first node G1, the control pole of the eighth control transistor GT8 is electrically connected to the second power supply terminal VGL, the first pole of the eighth control transistor GT8 is electrically connected to the first node G1, the second pole of the eighth control transistor GT8 is electrically connected to the third node G3, the first plate GC11 of the first control capacitor GC1 is electrically connected to the first power supply terminal VGH, the second plate GC12 of the first control capacitor GC1 is electrically connected to the second node G2, and the first plate GC21 of the second control capacitor GC2 is electrically connected to the output terminal GOUT;The second plate GC22 of the second control capacitor GC2 is electrically connected to the third node G3.

[0164] In an exemplary embodiment, the first control transistor GT1 to the eighth control transistor GT8 may be P-type transistors or N-type transistors.

[0165] In the exemplary embodiment, the first power supply terminal VGH continues to provide a high level signal and the second power supply terminal VGL continues to provide a low level signal.

[0166] Taking the first control transistor GT1 to the eighth control transistor GT8 as an example being P-type transistors, as shown in FIG. 11B, the operation process of the control shift register according to an exemplary embodiment includes the following steps.

[0167] In the input stage D1, the signals at the first clock signal terminal GCK1 and the input terminal GIN are low level signals, and the signal at the second clock signal terminal GCK2 is high level signal. Since the signal at the first clock signal terminal GCK1 is a low level signal, the first control transistor GT1 is turned on, and the signal at the input terminal GIN is transferred to the first node G1 through the first control transistor GT1. Since the signal at the eighth control transistor GT8 receives the low level signal at the second power supply terminal VGL, the eighth control transistor GT8 is turned on. The level of the third node G3 can control the fifth control transistor GT5 to be on, and the signal at the second clock signal terminal GCK2 is transferred to the output terminal GOUT through the fifth control transistor GT5, that is, in the input stage D1, the output terminal GOUT is the signal at the second clock signal terminal GCK2, which is a high level signal. Also, since the signal at the first clock signal terminal GCK1 is a low-level signal, the third control transistor GT3 is turned on, and the low-level signal at the second power supply terminal VGL is transferred to the second node G2 via the third control transistor GT3. At this time, the fourth control transistor GT4 and the sixth control transistor GT6 are both turned on. Since the signal at the second clock signal terminal GCK2 is a high-level signal, the seventh control transistor GT7 is turned off.

[0168] In the output stage D2, the signal at the first clock signal terminal GCK1 is a high level signal, the signal at the second clock signal terminal GCK2 is a low level signal, and the signal at the input terminal GIN is a high level signal. The fifth control transistor GT5 is turned on, and the signal at the second clock signal terminal GCK2 becomes the signal at the output terminal GOUT through the fifth control transistor GT5. In the output stage D2, the level of one end connected to the output terminal OUT of the second control capacitor GC2 becomes the signal at the second power supply terminal VGL, and the eighth control transistor GT8 is turned off due to the bootstrap action of the second control capacitor GC2, the fifth control transistor GT5 is turned on better, and the signal at the output terminal GOUT is a low level signal. Also, since the signal at the first clock signal terminal GCK1 is a high level signal, the first control transistor GT1 and the third control transistor GT3 are both turned off. The second control transistor GT2 turns on, and the high-level signal at the first clock signal terminal GCK1 is transferred to the second node G2 via the second control transistor GT2, so that the fourth control transistor GT4 and the sixth control transistor GT6 are both turned off. Since the signal at the second clock signal terminal GCK2 is a low-level signal, the seventh control transistor GT7 turns on.

[0169] In the buffer stage D3, the signals at the first clock signal terminal GCK1 and the second clock signal terminal GCK2 are both high level signals, the signal at the input terminal GIN is a high level signal, the fifth control transistor GT5 is turned on, and the second clock signal terminal GCK2 becomes the output signal GOUT through the fifth control transistor GT5. Due to the bootstrap action of the second control capacitor C2, the level of the first node G1 becomes VGL-VthN1. Also, since the signal at the first clock signal terminal GCK1 is a high level signal, the first control transistor GT1 and the third control transistor GT3 are both turned off, the eighth control transistor GT8 is turned on, the second control transistor GT2 is turned on, and the high level signal at the first clock signal terminal GCK1 is transferred to the second node G2 through the second control transistor GT2, so that the fourth control transistor GT4 and the sixth control transistor GT6 are both turned off. Since the signal at the second clock signal terminal GCK2 is a high level signal, the seventh control transistor GT7 is turned off.

[0170] In the first sub-stage D41 of the stable stage D4, the signal at the first clock signal terminal GCK1 is a low level signal, and the signals at the second clock signal terminal GCK2 and the input terminal GIN are high level signals. Since the signal at the first clock signal terminal GCK1 is a low level signal, the first control transistor GT1 is turned on, the signal at the input terminal GIN is transferred to the first node G1 via the first control transistor GT1, and the second control transistor GT2 is turned off. Since the eighth control transistor GT8 is in an on state, the fifth control transistor GT5 is turned off. Since the signal at the first clock signal terminal GCK1 is a low level, the third control transistor GT3 is turned on, the fourth control transistor GT4 and the sixth control transistor GT6 are both turned on, and the high level signal at the first power supply terminal VGH is transferred to the output terminal GOUT via the fourth control transistor GT4, that is, the signal at the output terminal GOUT is a high level signal.

[0171] In a second sub-stage t42 of the stable stage t4, the signal at the first clock signal terminal GCK1 is a high level signal, the signal at the second clock signal terminal GCK2 is a low level signal, and the signal at the input terminal GIN is a high level signal. The fifth control transistor GT5 and the second control transistor GT2 are both turned off. Since the signal at the first clock signal terminal GCK1 is a high level signal, the first control transistor GT1 and the third control transistor GT3 are both turned off, and due to the holding action of the first control capacitor GC1, the fourth control transistor GT4 and the sixth control transistor GT6 are both turned on, and the high level signal is transferred to the output terminal GOUT via the fourth control transistor GT4, i.e., the signal at the output terminal GOUT is a high level signal.

[0172] In the second sub-stage t42, since the signal at the second clock signal terminal GCK2 is a low level signal, the seventh control transistor GT7 is turned on, thereby transmitting a high level signal to the third node G3 and the first node G1 via the sixth control transistor GT6 and the seventh control transistor GT7, so that the signals at the third node G3 and the first node G1 maintain a high level signal.

[0173] In the third sub-stage t43, the signals of the first clock signal terminal GCK1 and the second clock signal terminal GCK2 are both high level signals, and the signal of the input terminal GIN is a high level signal. The fifth control transistor GT5 and the second control transistor GT2 are turned off. Since the signal of the first clock signal terminal GCK1 is a high level signal, the first control transistor GT1 and the third control transistor GT3 are both turned off, and the fourth control transistor GT4 and the sixth control transistor GT6 are both turned on. The high level signal is transferred to the output terminal GOUT via the fourth control transistor GT4, i.e., the signal of the output terminal GOUT is a high level signal.

[0174] In an exemplary embodiment, the circuit structure layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a fifth conductive layer that are sequentially stacked on a base.

[0175] In an exemplary embodiment, the first conductive layer may include a reset signal line, a light emitting signal line, a scanning signal line and a control signal line.

[0176] In an example embodiment, the second conductive layer may include a first initial signal line, a second initial signal line, and a scan connection S_CN.

[0177] In an example embodiment, the third conductive layer may include the light emitting connection EM_CN.

[0178] In an example embodiment, the fourth conductive layer may include a reset transfer line RST_TL, a first initial output line INIT1_OL, an emission output line EM_OL, a scanning output line S_OL, and a control output line G_OL.

[0179] In an exemplary embodiment, the fifth conductive layer may include a reset connection line RST_CL, a first initial connection line INIT1_CL, an emission connection line EM_CL, a scan connection line S_CL, a control connection line G_CL, a second initial connection line INIT2_CL, a first initial power supply line INIT1_SL and a second initial power supply line INIT2_SL.

[0180] In an exemplary embodiment, the reset output line RST_OL may be located on the first conductive layer or on the second conductive layer, and the present disclosure is not limited thereto.

[0181] In an exemplary embodiment, the reset output line is located in the first conductive layer or the second conductive layer, the reset transfer line and the reset connection line are located in the fourth conductive layer and the fifth conductive layer, multiple conductive layers are separated between the reset transfer line and the reset connection line and the reset output line, and the distance between the reset transfer line and the reset connection line and the reset output line is relatively far, so that the problem of signal crosstalk caused by overlapping signal lines can be avoided, and the display effect of the display substrate can be improved.

[0182] In an exemplary embodiment, the low-level power line VSSL may be located on the fourth conductive layer, the fifth conductive layer, or the fourth conductive layer and the fifth conductive layer, and the present disclosure is not limited thereto.

[0183] In the present disclosure, the "patterning process" includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal materials, inorganic materials, or transparent conductive materials, and organic material coating, mask exposure, development, and the like. The deposition may be any one or more of sputtering, deposition, and chemical vapor deposition, the coating may be any one or more of spraying, spin coating, and inkjet printing, and the etching may be any one or more of dry etching and wet etching, and the present disclosure is not limited thereto. A "thin film" refers to a thin film prepared by deposition, coating, or other methods based on a certain material. If the "thin film" does not require a patterning process in the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process in the entire manufacturing process, it is called a "thin film" before the patterning process, and is called a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". In the present disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display device. In the exemplary embodiment of the present disclosure, "the orthogonal projection of B is within the orthogonal projection of A" means that the boundary of the orthogonal projection of B is within the boundary of the orthogonal projection of A, or the boundary of the orthogonal projection of A overlaps with the boundary of the orthogonal projection of B.

[0184] Hereinafter, a display substrate according to an exemplary embodiment will be described by taking the reset output line located on the first conductive layer as an example, according to a manufacturing process of the display substrate.

[0185] (1) Forming a first conductive layer on a base includes depositing a semiconductor thin film on a base, patterning the semiconductor thin film by a patterning process to form a semiconductor layer, depositing a first insulating thin film on the base on which the semiconductor layer is formed, patterning the first insulating thin film by a patterning process to form a first insulating layer, depositing a first conductive thin film on the first insulating layer, and patterning the first conductive thin film by a patterning process to form a first conductive layer, as shown in Figures 12 and 13. Figure 12 is a structural schematic diagram of the first conductive layer in the bezel region, and Figure 13 is a structural schematic diagram of the first conductive layer in the round corner region.

[0186] In an exemplary embodiment, the first conductive layer may include a reset signal line, a light emitting signal line, a scanning signal line, a control signal line, and a reset output line RST_OL.

[0187] (2) Forming the second conductive layer includes depositing a second insulating thin film on a base on which the first conductive layer is formed, patterning the second insulating thin film by a patterning process to form a second insulating layer, depositing a second conductive thin film on the base on which the second insulating layer is formed, and patterning the second conductive thin film by a patterning process to form a second conductive layer, as shown in Figures 14 to 17. Figure 14 is a structural schematic diagram of the second conductive layer in the bezel region, Figure 15 is a structural schematic diagram of the bezel region after the second conductive layer is formed, Figure 16 is a structural schematic diagram of the second conductive layer in the round corner region, and Figure 17 is a structural schematic diagram of the round corner region after the second conductive layer is formed.

[0188] In an example embodiment, the second conductive layer may include a first initial signal line, a second initial signal line, and a scan connection S_CN.

[0189] (3) Forming the third conductive layer includes depositing a third insulating thin film on a base on which the second conductive layer is formed, patterning the third insulating thin film by a patterning process to form a third insulating layer, depositing a third conductive thin film on the third insulating layer, and patterning the third conductive thin film by a patterning process to form a third conductive layer, as shown in Figures 18 to 21. Figure 18 is a structural schematic diagram of the third conductive layer in the bezel region, Figure 19 is a structural schematic diagram of the bezel region after the third conductive layer is formed, Figure 20 is a structural schematic diagram of the third conductive layer in the rounded corner region, and Figure 21 is a structural schematic diagram of the rounded corner region after the third conductive layer is formed.

[0190] In an example embodiment, the third conductive layer may include the light emitting connection EM_CN.

[0191] (4) Forming the fourth insulating layer includes depositing a fourth insulating thin film on a base on which the third conductive layer is formed, and patterning the fourth insulating thin film by a patterning process to form a fourth insulating layer, as shown in Figures 22 to 25. Figure 22 is a structural schematic diagram of the fourth insulating layer in the bezel region, Figure 23 is a structural schematic diagram of the bezel region after the fourth insulating layer is formed, Figure 24 is a structural schematic diagram of the fourth insulating layer in the rounded corner region, and Figure 25 is a structural schematic diagram of the rounded corner region after the fourth insulating layer is formed.

[0192] In an exemplary embodiment, the fourth insulating layer includes a plurality of via patterns, including a first via V1 penetrating the second to fourth insulating layers, a second via V2 penetrating the third and fourth insulating layers, and a third via V3 opened in the fourth insulating layer, where the first via V1 exposes the reset output line, the second via V2 exposes the scan connection portion, and the third via V3 exposes the light emitting connection portion.

[0193] (5) Forming the fourth conductive layer includes depositing a fourth conductive thin film on a base on which the fourth insulating layer is formed, and patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer, as shown in Figures 26 to 29. Figure 26 is a structural schematic diagram of the fourth conductive layer in the bezel region, Figure 27 is a structural schematic diagram of the bezel region after the fourth conductive layer is formed, Figure 28 is a structural schematic diagram of the fourth conductive layer in the rounded corner region, and Figure 29 is a structural schematic diagram of the rounded corner region after the fourth conductive layer is formed.

[0194] In an example embodiment, the fourth conductive layer may include a reset transfer line RST_TL, a first initial output line INIT1_OL, an emission output line EM_OL, a scanning output line S_OL, and a control output line G_OL.

[0195] In an exemplary embodiment, the reset transfer line is electrically connected to the reset output line through a first via, the control output line electrically connected to the same control shift register is electrically connected to the reset output line through the first via, the scan output line is electrically connected to the scan connection through a second via, and the light emission output line is electrically connected to the light emission connection through a third via.

[0196] (6) Forming the fifth insulating layer includes depositing a fifth insulating thin film on a base on which the fourth conductive layer is formed, and patterning the fifth insulating thin film by a patterning process to form a fifth insulating layer, as shown in Figures 30 to 33. Figure 30 is a structural schematic diagram of the fifth insulating layer in the bezel region, Figure 31 is a structural schematic diagram of the bezel region after the fifth insulating layer is formed, Figure 32 is a structural schematic diagram of the fifth insulating layer in the rounded corner region, and Figure 33 is a structural schematic diagram of the rounded corner region after the fifth insulating layer is formed.

[0197] In an exemplary embodiment, the fifth insulating layer includes a plurality of via patterns, including a fourth via V4 to an eighth via V8 opened in the fifth insulating layer. The fourth via V4 exposes a reset transfer line, the fifth via V5 exposes a first initial output line, the sixth via V6 exposes a light emitting output line, the seventh via V7 exposes a scanning output line, and the eighth via V8 exposes a control output line.

[0198] (7) Forming the fifth conductive layer includes depositing a fifth conductive thin film on a base on which a fifth insulating layer is formed, and patterning the fifth conductive thin film by a patterning process to form a fifth conductive layer, as shown in Figures 34 to 37. Figure 34 is a structural schematic diagram of the fifth conductive layer in the bezel region, Figure 35 is a structural schematic diagram of the bezel region after the fifth conductive layer is formed, Figure 36 is a structural schematic diagram of the fifth conductive layer in the rounded corner region, and Figure 37 is a structural schematic diagram of the rounded corner region after the fifth conductive layer is formed.

[0199] In an exemplary embodiment, the fifth conductive layer may include a reset connection line RST_CL, a first initial connection line INIT1_CL, an emission connection line EM_CL, a scan connection line S_CL, a control connection line G_CL, a second initial connection line INIT2_CL, a first initial power supply line INIT1_SL, and a second initial power supply line INIT2_SL.

[0200] In an exemplary embodiment, the reset connection line is electrically connected to the reset transfer line through the fourth via, the first initial power supply line and the first initial connection line are electrically connected to the first initial output line through the fifth via, the light emitting connection line is electrically connected to the light emitting output line through the sixth via, the scan connection line is electrically connected to the scan output line through the seventh via, and the control connection line is electrically connected to the control output line through the eighth via.

[0201] (8) Forming a planarization layer includes applying a planarization thin film to the base on which the fifth conductive layer is formed, and patterning the planarization thin film by etching to form a planarization layer.

[0202] (9) Forming the light-emitting device includes depositing a transparent conductive thin film on a base on which a planarization layer is formed, patterning the transparent conductive thin film by a patterning process to form an anode, depositing a pixel-defining thin film on the base on which the anode is formed, patterning the pixel-defining thin film by a patterning process to form a pixel-defining layer, depositing a cathode thin film on the base on which the pixel-defining layer is formed, and patterning the cathode thin film by a patterning process to form a cathode.

[0203] In an exemplary embodiment, the semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a two-layer, or a multilayer. The active layer thin film may use various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxide nitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene, polythiophene, etc., that is, the present disclosure is suitable for transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0204] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0205] In an exemplary embodiment, the first to fifth conductive thin films may be made of one or more metal materials selected from the group consisting of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloy materials of the above metals, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0206] In an exemplary embodiment, the planarization layer may use an organic material.

[0207] The display substrate according to the embodiments of the present disclosure can be applied to display products with any resolution.

[0208] An embodiment of the present disclosure further provides a display device comprising a display substrate.

[0209] In an exemplary embodiment, the display device may be any product or component with a display function, such as a display, a television, a mobile phone, a tablet, a navigation system, a digital photo frame, a wearable display product, and the like.

[0210] The display substrate can be any of the display substrates according to the above-mentioned embodiments, and the implementation principles and effects are similar, so they will not be described here.

[0211] The drawings in the present disclosure only relate to the structures according to the embodiments of the present disclosure, and other structures may refer to the general design.

[0212] For clarity, the thicknesses and sizes of layers or microstructures are exaggerated in the figures illustrating the embodiments of the present disclosure. When an element such as a layer, film, region, or substrate is referred to as being located "on" or "under" another element, it is understood that the element can be located "directly" on or "under" the other element, or intermediate elements can be present.

[0213] Although the embodiments disclosed in the present disclosure are as described above, they are merely examples adopted to facilitate the understanding of the present disclosure and are not used to limit the present disclosure. Those skilled in the art can make any modifications and changes in the embodiments and details without departing from the spirit and scope of the present disclosure. However, the scope of patent protection of the present disclosure shall comply with the scope defined by the appended claims. [Explanation of symbols]

[0214] AA display area AA' hidden area BR Bezel area CR rounded corner area P pixel circuit RST_OL Reset output line RST_TL Reset transfer line

Claims

1. A display substrate, the display substrate includes a base and a circuit structure layer disposed on the base, the circuit structure layer including pixel circuits arranged in an array in the display area and a control drive circuit in the non-display area, the pixel circuits including reset transistors, and the control drive circuit configured to supply a drive signal to the reset transistor; the circuit structure layer further includes a plurality of reset output lines and a plurality of reset transfer lines located in the non-display area and disposed on a side of the control and driving circuit close to the display area, the reset output lines and the reset transfer lines are disposed in a different layer, and an extending direction of the reset output lines intersects with an extending direction of the reset transfer lines; the reset output line is electrically connected to the control drive circuit and the reset transfer line, and the reset transfer line is connected to the pixel circuit; A display substrate in which there is an overlapping portion between the orthogonal projection of at least one reset transfer line located in the rounded corner region and the orthogonal projection of a plurality of reset output lines located in the rounded corner region.

2. the circuit structure layer further includes a reset connection line located in the non-display area and disposed on a side of the control driving circuit close to the display area, the reset connection line and the reset output line are disposed in a different layer, an extension direction of the reset connection line intersects with an extension direction of the reset output line, and the pixel circuits arranged in an array include a plurality of reset signal lines; the reset connection line is electrically connected to the reset transfer line and the reset signal line, 2. The display substrate according to claim 1, wherein an overlap exists between at least one reset connection line and a plurality of reset output lines located in the rounded corner region when projected orthogonally onto a base thereof.

3. the pixel circuit further includes a write transistor, the control drive circuit further configured to provide a drive signal to the write transistor; the circuit structure layer further includes a plurality of control output lines located in the non-display area and disposed on a side of the control driving circuit close to the display area, the control output lines and the reset output lines are disposed in a different layer, and an extending direction of the control output lines intersects with an extending direction of the reset output lines; 2. The display substrate according to claim 1, wherein the control output line is connected to the control drive circuit and the pixel circuit, respectively, and an overlap exists between a normal projection of the control output line at a base and a normal projection of a plurality of reset output lines at bases.

4. the circuit structure layer further includes a control connection line located in the non-display area and installed on a side of the control driving circuit close to the display area, the control connection line is installed in a layer different from the reset output line, an extending direction of the control connection line intersects with an extending direction of the reset output line, the pixel circuits arranged in an array include a plurality of control signal lines, and a control electrode of the write transistor is electrically connected to the control signal line; the control connection line is electrically connected to the control output line and the control signal line, 4. The display substrate according to claim 3, wherein the at least one control connection line and the plurality of reset output lines located in the rounded corner region are orthogonally projected onto the base, and have an overlapping portion.

5. The control and driving circuit includes a plurality of control shift registers connected in cascade, the control shift register including an output terminal; an output terminal of the control shift register of the i stage is electrically connected to the i th reset output line, 1≦i≦M; an output terminal of the control shift register of the j stage is electrically connected to the j-S th control output lines, S+1≦j≦M+S, M is the total number of rows of the pixel circuit, and S≧1; 4. The display substrate according to claim 3, wherein the reset output line and the control output line connected to the output terminal of the same control shift register are connected to each other, and there is an overlapping portion between the orthogonal projection at the base of the reset output line and the orthogonal projection at the base of the control output line.

6. the circuit structure layer further includes a light emitting driving circuit located in the non-display area, the light emitting driving circuit being located on a side of the control driving circuit away from the display area, the pixel circuit including a light emitting transistor, and the light emitting driving circuit configured to supply a driving signal to the light emitting transistor; the circuit structure layer further includes a plurality of light emitting output lines located in the non-display area and disposed on a side of the control driving circuit close to the display area, the light emitting output lines are disposed in a layer different from the reset output lines, and an extending direction of the light emitting output lines intersects with an extending direction of the reset output lines; The display substrate according to claim 5 , wherein the light-emitting output line is connected to the light-emitting drive circuit and the pixel circuit, respectively, and there is an overlapping portion between the orthogonal projection of the light-emitting output line at a base and the orthogonal projection of a plurality of reset output lines at bases.

7. the circuit structure layer further includes an emission connecting line located in the non-display area and disposed on a side of the control driving circuit close to the display area, the emission connecting line and the reset output line are disposed in a different layer, an extending direction of the emission connecting line intersects with an extending direction of the reset output line, and the pixel circuits arranged in an array include a plurality of emission signal lines; the light-emitting connection line is electrically connected to the light-emitting output line and the light-emitting signal line, The display substrate according to claim 6 , wherein the at least one light-emitting connecting line and the plurality of reset output lines located in the rounded corner region are orthogonally projected onto the base, and have an overlapping portion.

8. the light emission drive circuit includes a plurality of light emission shift registers connected in cascade, the light emission shift register including an output terminal; 8. The display substrate according to claim 7, wherein the output terminals of at least one stage of the light-emitting shift register are electrically connected to a plurality of light-emitting output lines.

9. When the light-emitting shift register is electrically connected to at least two light-emitting output lines, the circuit structure layer further includes a light-emitting connection part located in the non-display area and disposed on a side of the control and driving circuit close to the display area, the light-emitting connection part is disposed in a layer different from that of the light-emitting output lines, and an extending direction of the light-emitting connection part intersects with an extending direction of the light-emitting output lines; 7. The display substrate according to claim 6, wherein at least two light-emitting output lines connected to the same light-emitting shift register are electrically connected via the light-emitting connection portion, and the light-emitting connection portion is located on a side away from the display area of ​​the plurality of reset output lines.

10. The circuit structure layer further includes a scanning driving circuit located in the non-display area, the scanning driving circuit being located between the control driving circuit and the emission driving circuit, the pixel circuit including a compensation transistor, and the scanning driving circuit being configured to supply a driving signal to the compensation transistor; the circuit structure layer further includes a plurality of scanning output lines located in the non-display area and disposed on a side of the control driving circuit close to the display area, the scanning output lines and the reset output lines are disposed in a different layer, and an extending direction of the scanning output lines crosses an extending direction of the reset output lines; 10. The display substrate according to claim 9, wherein the scanning output line is connected to the scanning drive circuit and the pixel circuit, respectively, and an overlapping portion exists between an orthogonal projection of the scanning output line at a base and an orthogonal projection of a plurality of reset output lines at bases.

11. the circuit structure layer further includes a scanning connection line located in the non-display area and disposed on a side of the control driving circuit close to the display area, the scanning connection line and the reset output line are disposed in a different layer, an extending direction of the scanning connection line intersects with an extending direction of the reset output line, and the pixel circuits arranged in an array include a plurality of scanning signal lines; the scanning connection lines are electrically connected to the scanning output lines and the scanning signal lines, 11. The display substrate according to claim 10, wherein the at least one scanning connection line and the plurality of reset output lines located in the rounded corner region are orthogonally projected onto a base thereof, and have an overlapping portion.

12. When the scanning shift register is electrically connected to at least two scanning output lines, the circuit structure layer further includes a scanning connection part located in the non-display area and disposed on a side of the control driving circuit close to the display area, the scanning connection part is disposed in a layer different from that of the scanning output lines, and an extending direction of the scanning connection part intersects with an extending direction of the scanning output lines; 11. The display substrate according to claim 10, wherein at least two scanning output lines connected to the same scanning shift register are electrically connected via the scanning connection portion, and the scanning connection portion is located on a side of the plurality of reset output lines away from a display area.

13. the circuit structure layer further includes a plurality of first initial output lines located in the non-display area and disposed on a side of the control driving circuit close to the display area, the first initial output lines are disposed in a layer different from the reset output line, an extending direction of the first initial output lines intersects with an extending direction of the reset output line, the pixel circuits arranged in an array include a plurality of first initial signal lines and a plurality of second initial signal lines, 13. The display substrate of claim 12, wherein the first initial output line is electrically connected to one of the first initial signal line and the second initial signal line of a pixel circuit, and an overlapping portion exists between an orthogonal projection of the first initial output line at a base and an orthogonal projection of a plurality of reset output lines at bases.

14. A display substrate as described in claim 13, wherein the circuit structure layer further includes a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer and a fifth conductive layer which are sequentially stacked on the base, and the reset output line is located in the first conductive layer or the second conductive layer.

15. A display device comprising the display substrate according to claim 1 .

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