PIXEL CIRCUIT, DISPLAY PANEL, DRIVING METHOD AND DISPLAY DEVICE

Abstract

A pixel circuit, a display panel, a driving method, and a display device. The pixel circuit includes a light-emitting element (E0), a driving circuit (11), a first energy storage circuit (12), a second energy storage circuit (13), a write control circuit (14) and a first control circuit (10). A first end of the first energy storage circuit (12) is electrically connected to a control end of the driving circuit (11), a second end of the first energy storage circuit (12) is electrically connected to a first end of the driving circuit (11), and a first end of the second energy storage circuit (13) is electrically connected to a control end of the driving circuit (11). The write control circuit (14) controls, under the control of a first write control signal, to connect or disconnect the write end (DW) and the second end of the second energy storage circuit (13). The first control circuit (10) controls, under the control of the first control signal, to connect or disconnect the power supply voltage end (Vd) and the first end of the driving circuit (11). The driving circuit (11) generates a driving current for driving the light-emitting element (E0) under the control of the potential of its control end. A current-type pixel circuit capable of threshold voltage self-compensation is provided for application in organic light-emitting diode displays.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to PCT international application No. PCT / CN2022 / 098080, filed June 10, 2022, and PCT international application No. PCT / CN2022 / 096196, filed May 31, 2022, the entire contents of which are incorporated herein by reference. The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a display panel, a driving method and a display device. [Background technology]

[0002] OLED (Organic Light Emitting Diode) display has become one of the hotspots in the current flat panel display research field, and pixel circuit design is the core technical content of OLED display. In the related art, it has been impossible to provide a current-type pixel circuit that can self-compensate the threshold voltage as a current-type pixel circuit applied to OLED display. Summary of the Invention

[0003] In a first aspect, an embodiment of the present disclosure provides a pixel circuit including a light emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a write control circuit, and a first control circuit, A first end of the first energy storage circuit is electrically connected to a control end of the driving circuit, and a second end of the first energy storage circuit is electrically connected to the first end of the driving circuit, and the first energy storage circuit is used for storing electrical energy; A first end of the second energy storage circuit is electrically connected to a control end of the driving circuit, and the second energy storage circuit is used to store electrical energy; The write control circuit is electrically connected to a first write control end, a write end and a second end of the second energy storage circuit respectively, and is used to control the communication or disconnection between the write end and the second end of the second energy storage circuit under the control of a first write control signal provided by the first write control end; The first control circuit is electrically connected to a first control end, a power supply voltage end and a first end of the driving circuit, and is used to control the communication between the power supply voltage end and the first end of the driving circuit to be interrupted or connected under the control of a first control signal provided by the first control end; A second end of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to generate a driving current for driving the light-emitting element under the control of the potential of its control end, providing a pixel circuit.

[0004] Optionally, the first control circuit is used to control communication between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first control signal in two discontinuous stages within one display period.

[0005] Alternatively, a display period of the pixel circuit includes an initialization step, a self-discharge step, a data preparation step, a data writing step, and a light emitting step, which are set in sequence, The first control circuit is used to control communication between the power supply voltage terminal and the first terminal of the driving circuit under control of the first control signal during the initialization stage, the data preparation stage, the data writing stage and the light emitting stage, and to control disconnection between the power supply voltage terminal and the first terminal of the driving circuit under control of the first control signal during the self-discharge stage.

[0006] Optionally, the write control circuit is used to control the write end and the second end of the second energy storage circuit to be disconnected under the control of the first write control signal in the initialization stage, the data preparation stage and the light emitting stage, and to control the write end and the second end of the second energy storage circuit to be connected under the control of the first write control signal in the self-discharge stage and the data write stage.

[0007] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a reference voltage writing circuit; The reference voltage write circuit is electrically connected to a second write control terminal, a reference voltage terminal and a control terminal of the driving circuit respectively, and is used to write the reference voltage supplied by the reference voltage terminal to the control terminal of the driving circuit under the control of a second write control signal supplied by the second write control terminal.

[0008] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second control circuit, and the second end of the driving circuit is electrically connected to the first pole of the light-emitting element, and the second pole of the light-emitting element is electrically connected to a first voltage end; The second control circuit is electrically connected to a second control terminal, a reset voltage terminal and a first pole of the light-emitting element, respectively, and is used to control the reset voltage supplied by the reset voltage terminal to be written to the first pole of the light-emitting element under the control of a second control signal supplied by the second control terminal.

[0009] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a resistor circuit, wherein the second end of the driving circuit is electrically connected to the first pole of the light-emitting element through the resistor circuit, and the second pole of the light-emitting element is electrically connected to a first voltage terminal.

[0010] Optionally, the first energy storage circuit includes a first capacitance, the second energy storage circuit includes a second capacitance, and the write control circuit includes a first transistor; A first end of the first capacitance is electrically connected to a control end of the driving circuit, and a second end of the first capacitance is electrically connected to a first end of the driving circuit; a first end of the second capacitance is electrically connected to a control end of the driving circuit; A control pole of the first transistor is electrically connected to the first write control terminal, a first pole of the first transistor is electrically connected to the write terminal, a second pole of the first transistor is electrically connected to the second terminal of the second capacitance, and a back gate of the first transistor is electrically connected to a second voltage terminal.

[0011] Optionally, the first control circuit includes a second transistor and the drive circuit includes a drive transistor; a control electrode of the second transistor is electrically connected to the first control end, a first electrode of the second transistor is electrically connected to the power supply voltage end, a second electrode of the second transistor is electrically connected to the first end of the driving circuit, and a back gate of the second transistor is electrically connected to a second voltage end; The control pole of the driving transistor is the control end of the driving circuit, the first pole of the driving transistor is the first end of the driving circuit, the second pole of the driving transistor is the second end of the driving circuit, and the back gate of the driving transistor is electrically connected to a second voltage end.

[0012] Optionally, the reference voltage writing circuit includes a third transistor; A control pole of the third transistor is electrically connected to the second write control terminal, a first pole of the third transistor is electrically connected to the reference voltage terminal, a second pole of the third transistor is electrically connected to the control terminal of the drive circuit, and a back gate of the third transistor is electrically connected to the second voltage terminal.

[0013] Optionally, the second control circuit includes a fourth transistor; A control electrode of the fourth transistor is electrically connected to the second control terminal, a first electrode of the fourth transistor is electrically connected to the reset voltage terminal, a second electrode of the fourth transistor is electrically connected to a first electrode of the light-emitting element, and a back gate of the fourth transistor is electrically connected to a third voltage terminal.

[0014] Alternatively, the fourth transistor is an n-type transistor, and the third voltage end is the reset voltage end; or The fourth transistor is a p-type transistor, and the third voltage end is a second voltage end.

[0015] Alternatively, the fourth transistor is an n-type transistor, and a deep n-well is provided between a back gate and a P-type base of the fourth transistor to isolate the back gate and the P-type base of the fourth transistor, and the back gate of the fourth transistor and a first electrode of the fourth transistor are both electrically connected to the reset voltage terminal.

[0016] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes an n-well and a p-well; the doping concentration of the n-well is greater than the doping concentration of the deep n-well; the ratio of the thickness of the n-well to the thickness of the deep n-well is 0.4 to 0.6, The ratio of the thickness of the p-well to the thickness of the deep n-well is 0.4 to 0.6.

[0017] In a second aspect, an embodiment of the present disclosure provides a display panel including multiple rows and multiple columns of the pixel circuits described above.

[0018] In a third aspect, an embodiment of the present disclosure is a driving method applied to the pixel circuit described above, the driving method comprising: A write control circuit controls the write end and the second end of the second energy storage circuit to communicate with each other or to be cut off under the control of a first write control signal; A first control circuit controls, under the control of a first control signal, to connect or disconnect a power supply voltage terminal and a first terminal of the driving circuit; The driving circuit generates a driving current for driving the light-emitting element under control of a potential at a control end thereof.

[0019] Optionally, the driving method further comprises: The first control circuit controls, under control of the first control signal, to communicate between the power supply voltage terminal and the first terminal of the drive circuit in two discontinuous stages within one display period.

[0020] Alternatively, the display period of the pixel circuit includes an initialization step, a self-discharge step, a data preparation step, a data writing step, and a light emitting step, which are set in sequence, and the driving method includes: During the initialization step, the data preparation step, the data writing step and the light emitting step, the first control circuit controls the power supply voltage terminal and the first terminal of the driving circuit to communicate with each other under the control of the first control signal; In the self-discharge step, the first control circuit controls, under the control of the first control signal, to cut off the connection between the power supply voltage terminal and the first terminal of the driving circuit.

[0021] Alternatively, the display period of the pixel circuit includes an initialization step, a self-discharge step, a data preparation step, a data writing step, and a light emitting step, which are set in sequence, and the driving method includes: In the initialization step, the data preparation step and the light emission step, the write control circuit controls the write end and the second end of the second energy storage circuit to be disconnected under the control of a first write control signal; In the self-discharge step and the data writing step, the write control circuit controls, under the control of the first write control signal, the write end and the second end of the second energy storage circuit to be communicated with each other.

[0022] In a fourth aspect, an embodiment of the present disclosure provides a display device including the above-mentioned display panel.

[0023] Optionally, the display panel includes a first silicon substrate, and a pixel circuit and a gate driving circuit disposed on the first silicon substrate; The display device further includes a second silicon substrate and a display driver chip disposed on the second silicon substrate.

[0024] Optionally, the area of ​​the first silicon substrate is larger than the area of ​​the second silicon substrate; The minimum width of a signal line included in the display panel is greater than the width of a signal line included in the display driver chip. [Brief description of the drawings]

[0025] [Figure 1] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Diagram 2] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Diagram 3] FIG. 2 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 4] FIG. 2 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Diagram 5] FIG. 2 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 6] 6 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 5 of the present disclosure. [Figure 7] 1 is a schematic diagram of an NMOS transistor (N-type metal oxide semiconductor transistor) structure and a PMOS transistor (P-type metal oxide semiconductor transistor) structure in at least one embodiment of the present disclosure. [Figure 8] 1A and 1B are schematic diagrams illustrating the structure of an NMOS transistor and the structure of a PMOS transistor according to the related art. [Figure 9] FIG. 2 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 10] FIG. 1 is a structural diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, the technical aspects of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, but it is obvious that the described embodiments are only some embodiments of the present disclosure, and are not all embodiments. Based on the embodiments of the present disclosure, other embodiments obtained by those skilled in the art without paying creative labor shall all be within the scope of protection of the present disclosure.

[0027] The transistors used in all the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with similar characteristics. In the embodiments of the present disclosure, in order to distinguish between the two poles of the transistor other than the gate, one pole is called a first electrode and the other pole is called a second electrode.

[0028] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be the drain and the second electrode may be the source, or the first electrode may be the source and the second electrode may be the drain.

[0029] The pixel circuit according to the embodiment of the present disclosure includes a light emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a writing control circuit and a first control circuit; A first end of the first energy storage circuit is electrically connected to a control end of the driving circuit, and a second end of the first energy storage circuit is electrically connected to the first end of the driving circuit, and the first energy storage circuit is used for storing electrical energy; A first end of the second energy storage circuit is electrically connected to a control end of the driving circuit, and the second energy storage circuit is used to store electrical energy; The write control circuit is electrically connected to a first write control end, a write end and a second end of the second energy storage circuit respectively, and is used to control the communication or disconnection between the write end and the second end of the second energy storage circuit under the control of a first write control signal provided by the first write control end; The first control circuit is electrically connected to a first control end, a power supply voltage end and a first end of the driving circuit, and is used to control the communication between the power supply voltage end and the first end of the driving circuit to be interrupted or connected under the control of a first control signal provided by the first control end; A second end of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to generate a driving current for driving the light-emitting element under the control of the potential of its control end.

[0030] During operation of the pixel circuit according to the embodiment of the present disclosure, The write control circuit controls the voltage signal supplied by the write end to be written to the second end of the second energy storage circuit under the control of a first write control signal, and the first control circuit controls the connection or disconnection between the power supply voltage end and the first end of the driving circuit under the control of the first control signal, thereby controlling the self-discharge threshold compensation process of the driving transistor included in the driving circuit, the first energy storage circuit and the second energy storage circuit are capable of controlling the potential of the control end of the driving circuit by voltage division, and the driving circuit generates a driving current for driving the light-emitting element under the control of the potential of its control end.

[0031] During operation of the pixel circuit described in the embodiments of the present disclosure, by controlling to adjust the capacitance value of the first capacitance included in the first energy storage circuit and the capacitance value of the second capacitance included in the second energy storage circuit, the drive current of the drive circuit that drives the light-emitting element to emit light can be controlled to be independent of the threshold voltage of the drive transistor included in the drive circuit.

[0032] The embodiments of the present disclosure can provide a current-type pixel circuit that is simple in structure and capable of self-compensating the threshold voltage, for application in an OLED (Organic Light Emitting Diode) display.

[0033] In at least one embodiment of the present disclosure, the first control circuit may control communication between the power supply voltage terminal and the first terminal of the drive circuit under control of the first control signal in two discontinuous stages within one display period.

[0034] During operation of the pixel circuit according to the embodiment of the present disclosure, a display period of the pixel circuit may include an initialization stage, a self-discharge stage, a data preparation stage, a data writing stage and a light emitting stage, which are set in sequence; The first control circuit is used to control communication between the power supply voltage terminal and the first terminal of the driving circuit under control of the first control signal during the initialization stage, the data preparation stage, the data writing stage and the light emitting stage, and to control disconnection between the power supply voltage terminal and the first terminal of the driving circuit under control of the first control signal during the self-discharge stage.

[0035] In at least one embodiment of the present disclosure, the two discontinuous stages may be, but are not limited to, the initialization stage and the self-discharge stage, respectively.

[0036] During operation of the pixel circuit according to the embodiment of the present disclosure, a display period of the pixel circuit may include an initialization stage, a self-discharge stage, a data preparation stage, a data writing stage and a light emitting stage, which are set in sequence; The write control circuit is used to control the write end and the second end of the second energy storage circuit to be disconnected under control of the first write control signal during the initialization stage, the data preparation stage and the light emitting stage, and to control the write end and the second end of the second energy storage circuit to be connected under control of the first write control signal during the self-discharge stage and the data write stage.

[0037] As shown in FIG. 1, a pixel circuit according to at least one embodiment of the present disclosure includes a light emitting element E0, a first control circuit 10, a driving circuit 11, a first energy storage circuit 12, a second energy storage circuit 13, and a write control circuit 14; The first control circuit 10 is electrically connected to a first control end DS, a power supply voltage end Vd, and a first end of the driving circuit 11, and is used to control the communication between the power supply voltage end Vd and the first end of the driving circuit 11 to be disconnected or connected under the control of a first control signal supplied by the first control end DS, and the power supply voltage end Vd is used to supply a power supply voltage; A first end of the first energy storage circuit 12 is electrically connected to a control end of the driving circuit 11, and a second end of the first energy storage circuit 12 is electrically connected to a first end of the driving circuit 11, and the first energy storage circuit 12 is used for storing electrical energy; A first end of the second energy storage circuit 13 is electrically connected to a control end of the driving circuit 11; The write control circuit 14 is electrically connected to the first write control end WS1, the write end DW and the second end of the second energy storage circuit 13, respectively, and is used to control the communication or disconnection between the write end DW and the second end of the second energy storage circuit 13 under the control of a first write control signal provided by the first write control end WS1; A second end of the driving circuit 11 is electrically connected to the light emitting element E0, and the driving circuit 11 is used to generate a driving current for driving the light emitting element E0 under the control of the potential of its control end.

[0038] During operation of at least one embodiment of a pixel circuit as shown in FIG. 1 of the present disclosure, the write control circuit 14 transmits a voltage signal provided by the write end DW under control of a first write control signal, the first energy storage circuit 12 is used to store a data voltage and control a gate-source voltage of a drive transistor included in the drive circuit 11, and the first control circuit 10 can control a self-discharge threshold compensation process of the drive transistor included in the drive circuit 11.

[0039] During operation of at least one embodiment of the pixel circuit as shown in FIG. 1 of the present disclosure, the writing of the data voltage is divided by the first energy storage circuit 12 and the second energy storage circuit 13, and the dynamic range of the data voltage is increased, which is advantageous for the design of the DAC (digital-to-analog converter) in the source driver and the uniformity of the output of the data line.

[0040] In operation of at least one embodiment of the pixel circuit as shown in FIG. 1 of the present disclosure, a display period includes an initialization phase, a self-discharge phase, a data preparation phase, a data writing phase and a light emitting phase, which are set in sequence; In the initialization stage, the data preparation stage, the data writing stage and the light emitting stage, the first control circuit 10 controls the power supply voltage terminal Vd to communicate with the first terminal of the driving circuit 11 under the control of the first control signal; In the self-discharge stage, the first control circuit 10 controls the first control signal to cut off the connection between the power supply voltage terminal Vd and the first terminal of the driving circuit 11; In the initialization stage, the data preparation stage and the light emission stage, the write control circuit 14 controls the write end DW and the second end of the second energy storage circuit 13 to be disconnected under the control of the first write control signal; In the self-discharge phase and the data write phase, the write control circuit 10 controls the communication between the write end DW and the second end of the second energy storage circuit 13 under the control of the first write control signal.

[0041] The pixel circuit according to at least one embodiment of the present disclosure may further include a reference voltage writing circuit; The reference voltage write circuit is electrically connected to a second write control terminal, a reference voltage terminal and a control terminal of the driving circuit respectively, and is used to write the reference voltage supplied by the reference voltage terminal to the control terminal of the driving circuit under the control of a second write control signal supplied by the second write control terminal.

[0042] In a specific implementation, the pixel circuit may further include a reference voltage writing circuit, which writes a reference voltage to a control end of the driving circuit under control of a second write control signal, to control the on / off of a driving transistor included in the driving circuit.

[0043] In at least one embodiment of the present disclosure, the pixel circuit further includes a second control circuit, and a second end of the driving circuit is electrically connected to a first pole of the light-emitting element, and a second pole of the light-emitting element is electrically connected to a first voltage end; The second control circuit is electrically connected to a second control terminal, a reset voltage terminal and a first pole of the light-emitting element, respectively, and is used to control the reset voltage supplied by the reset voltage terminal to be written to the first pole of the light-emitting element under the control of a second control signal supplied by the second control terminal.

[0044] In a specific implementation, the second control circuit is used to control the light-emitting element not to emit light by writing the reset voltage to the first pole of the light-emitting element under the control of the second control signal in a non-light-emitting stage so that the difference between the potential of the first pole of the light-emitting element and the potential of the second pole of the light-emitting element is smaller than the lighting voltage of the light-emitting element.

[0045] Alternatively, the light emitting element may be an organic light emitting diode, the first pole of the light emitting element may be an anode of the organic light emitting diode, and the second pole of the light emitting element may be a cathode of the organic light emitting diode, but is not limited thereto.

[0046] As shown in FIG. 2 , in addition to at least one embodiment of the pixel circuit shown in FIG. 1 , the pixel circuit according to at least one embodiment of the present disclosure may further include a reference voltage writing circuit 16; The reference voltage write circuit 16 is electrically connected to a second write control terminal WS2, a reference voltage terminal R2 and a control terminal of the driving circuit 11, respectively, and is used to write the reference voltage Vref supplied by the reference voltage terminal R2 to the control terminal of the driving circuit 11 under the control of a second write control signal supplied by the second write control terminal WS2.

[0047] In operation of at least one embodiment of the pixel circuit shown in FIG. 2 of the present disclosure, a display period includes an initialization stage, a self-discharge stage, a data preparation stage, a data writing stage and a light emitting stage, which are set in sequence; In the initialization stage and the self-discharge stage, the reference voltage write circuit 16 writes the reference voltage Vref provided by the reference voltage terminal R2 into the control terminal of the driving circuit 11 under the control of the second write control signal; In the data preparation stage, the data writing stage and the light emitting stage, the reference voltage writing circuit 16 controls the connection between the reference voltage terminal R2 and the control terminal of the driving circuit 11 to be disconnected under the control of the second write control signal.

[0048] As shown in FIG. 3 , in addition to at least one embodiment of the pixel circuit shown in FIG. 2 , the pixel circuit according to at least one embodiment of the present disclosure may further include a second control circuit 20; A second end of the driving circuit 11 is electrically connected to a first electrode of the light emitting element E0, and a second electrode of the light emitting element E0 is electrically connected to a first voltage end V1; The second control circuit 20 is electrically connected to the second control end AZ, the reset voltage end Vf and the first pole of the light-emitting element E0, respectively, and is used to control the reset voltage supplied by the reset voltage end Vf to be written to the first pole of the light-emitting element E0 under the control of the second control signal supplied by the second control end AZ.

[0049] During operation of at least one embodiment of a pixel circuit as shown in FIG. 3 of the present disclosure, the second control circuit 20 is used to control the light-emitting element E0 not to emit light by writing a reset voltage supplied by a reset voltage terminal Vf to the first pole of the light-emitting element E0 during a non-light-emitting stage under the control of a second control signal, so that the difference between the potential of the first pole of the light-emitting element E0 and the potential of the second pole of the light-emitting element E0 is smaller than the lighting voltage of the light-emitting element E0.

[0050] In at least one embodiment of the pixel circuit as shown in FIG. 3 of the present disclosure, the first voltage end V1 may be, but is not limited to, a common electrode voltage Vcom.

[0051] In at least one embodiment of the present disclosure, Vcom may be, but is not limited to, greater than or equal to -12V and less than or equal to -9V.

[0052] Optionally, the pixel circuit according to at least one embodiment of the present disclosure may further include a resistor circuit, and the second end of the driving circuit is electrically connected to the first pole of the light-emitting element through the resistor circuit, so as to prevent a short circuit between the first pole of the light-emitting element and the second pole of the light-emitting element; The second pole of the light emitting device is electrically connected to a first voltage terminal.

[0053] As shown in FIG. 4, in addition to at least one embodiment of the pixel circuit shown in FIG. 3, the pixel circuit described in at least one embodiment of the present disclosure may further include a resistor circuit 40, and a second end of the driving circuit 11 is electrically connected to a first electrode of the light-emitting element E0 via the resistor circuit 40.

[0054] In at least one embodiment of the present disclosure, the resistance circuit may be made of the same host material as the gate of the drive transistor included in the drive circuit, for example, the host material may be a polysilicon material, and the conductivity of the resistance circuit may be, but is not limited to, one that can resist the conductivity of the gate of the drive transistor.

[0055] In at least one embodiment of the present disclosure, the resistance circuit 40 may include a first resistor, a first end of the first resistor being electrically connected to a second end of the driving circuit 11, and a second end of the first resistor being electrically connected to a first pole of the light-emitting element E0, but is not limited thereto.

[0056] Optionally, the first energy storage circuit includes a first capacitance, the second energy storage circuit includes a second capacitance, and the write control circuit includes a first transistor; A first end of the first capacitance is electrically connected to a control end of the driving circuit, and a second end of the first capacitance is electrically connected to a first end of the driving circuit; a first end of the second capacitance is electrically connected to a control end of the driving circuit; A control pole of the first transistor is electrically connected to the first write control terminal, a first pole of the first transistor is electrically connected to the write terminal, a second pole of the first transistor is electrically connected to the second terminal of the second capacitance, and a back gate of the first transistor is electrically connected to a second voltage terminal.

[0057] In at least one embodiment of the present disclosure, the capacitance value of the second capacitance may be, but is not limited to, smaller than the capacitance value of the first capacitance.

[0058] Optionally, the first control circuit includes a second transistor and the drive circuit includes a drive transistor; a control electrode of the second transistor is electrically connected to the first control end, a first electrode of the second transistor is electrically connected to the power supply voltage end, a second electrode of the second transistor is electrically connected to the first end of the driving circuit, and a back gate of the second transistor is electrically connected to a second voltage end; The control pole of the driving transistor is the control end of the driving circuit, the first pole of the driving transistor is the first end of the driving circuit, the second pole of the driving transistor is the second end of the driving circuit, and the back gate of the driving transistor is electrically connected to a second voltage end.

[0059] Optionally, the reference voltage writing circuit includes a third transistor; A control pole of the third transistor is electrically connected to the second write control terminal, a first pole of the third transistor is electrically connected to the reference voltage terminal, a second pole of the third transistor is electrically connected to the control terminal of the drive circuit, and a back gate of the third transistor is electrically connected to the second voltage terminal.

[0060] Optionally, the second control circuit includes a fourth transistor; A control electrode of the fourth transistor is electrically connected to the second control terminal, a first electrode of the fourth transistor is electrically connected to the reset voltage terminal, a second electrode of the fourth transistor is electrically connected to a first electrode of the light-emitting element, and a back gate of the fourth transistor is electrically connected to a third voltage terminal.

[0061] In at least one embodiment of the present disclosure, the fourth transistor may be an n-type transistor, and the third voltage end may be the reset voltage end; or The fourth transistor may be a p-type transistor, and the third voltage end may be a second voltage end.

[0062] As shown in FIG. 5, in addition to at least one embodiment of the pixel circuit shown in FIG. the first energy storage circuit 12 includes a first capacitance C1, the second energy storage circuit 13 includes a second capacitance C2, the write control circuit 14 includes a first transistor P1, the driving circuit 11 includes a driving transistor P0, the first control circuit 10 includes a second transistor P2, the second control circuit 20 includes a fourth transistor P4, the reference voltage write circuit 16 includes a third transistor P3, and the light emitting element is an organic light emitting diode O1; A first end of the first capacitance C1 is electrically connected to the gate of the driving transistor P0, and a second end of the first capacitance C1 is electrically connected to the source of the driving transistor P0; A first end of the second capacitor C2 is electrically connected to the gate of the driving transistor P0; The gate of the first transistor P1 is electrically connected to the first write control end WS1, the source of the first transistor P1 is electrically connected to the write end DW, the drain of the first transistor P1 is electrically connected to the second end of the second capacitor C2, and the back gate of the first transistor P1 is electrically connected to a high voltage end, which is used to supply a high voltage VDD; The gate of the third transistor P3 is electrically connected to the second write control end WS2, the source of the third transistor P3 is electrically connected to the reference voltage end R2, the drain of the third transistor P3 is electrically connected to the gate of the driving transistor P0, the back gate of the third transistor P3 is electrically connected to the high voltage end, and the reference voltage end R2 is used to supply a reference voltage Vref; The gate of the second transistor P2 is electrically connected to the first control end DS, the source of the second transistor P2 is electrically connected to the power supply voltage end Vd, the drain of the second transistor P2 is electrically connected to the source of the driving transistor P0, the back gate of the second transistor P2 is electrically connected to the high voltage end, and the power supply voltage end Vd is used to supply a power supply voltage ELVDD; The gate of the fourth transistor P4 is electrically connected to the second control end AZ, the source of the fourth transistor P4 is electrically connected to the ground end G1, the drain of the fourth transistor P4 is electrically connected to the anode of the organic light emitting diode O1, and the back gate of the fourth transistor P4 is electrically connected to the high voltage end; A common electrode voltage Vcom is applied to the cathode of the organic light emitting diode O1.

[0063] In at least one embodiment of the present disclosure, the first transistor P1, the second capacitor C2 and the fourth transistor P4 may be arranged outside the display area, and the driving transistor P0, the second transistor P2, the third transistor P3 and the first capacitor C1 may be arranged inside the display area, but is not limited to this.

[0064] In at least one embodiment of the pixel circuit shown in FIG. 5, the third voltage terminal is the high voltage terminal, the first voltage terminal is supplied with a common electrode voltage Vcom, and the reset voltage terminal is the ground terminal G1.

[0065] In at least one embodiment of the present disclosure, ELVDD-Vref is 1.5V or more, and the value of ELVDD may range from 2V or more to 8V or less, but is not limited thereto.

[0066] In at least one embodiment of the pixel circuit shown in FIG. 5, all transistors are PMOS transistors, but are not limited to such.

[0067] In at least one embodiment of a pixel circuit as shown in FIG. 5 of the present disclosure, the drive transistor P0 is equivalent to a current source controlled by a gate voltage, thereby realizing direct control of the drive current through O1 by the data voltage Vdata, and therefore at least one embodiment of a pixel circuit as shown in FIG. 5 of the present disclosure is a current-type pixel circuit.

[0068] In at least one embodiment of the pixel circuit shown in FIG. 5 of the present disclosure, the data voltage Vdata is divided by C1 and C2 and written to the gate of the driving transistor P0, thereby widening the dynamic range of the data voltage Vdata, which is advantageous for the design of a DAC (digital-to-analog converter) in a source driver and the uniformity of the output of the data line.

[0069] As shown in FIG. 6, during operation of at least one embodiment of the pixel circuit as shown in FIG. 5 of the present disclosure, a display cycle includes an initialization stage S1, a self-discharge stage S2, a data preparation stage S3, a data writing stage S5 and a light emitting stage S6, which are set in sequence; In the initialization stage S1, WS1 supplies a low voltage signal, WS2 supplies a low voltage signal, DS supplies a low voltage signal, AZ supplies a low voltage signal, R1 supplies a reference voltage Vref, DW supplies a reference voltage Vref, P1 and P4 are turned on, P2 is turned on, P3 is turned on, the power supply voltage ELVDD is applied to the source of P0, the reference voltage Vref is applied to the gate of P0, and the drain of P0 is connected to the ground terminal G1, and ELVDD-Vref is greater than |Vth|, so that P0 can be turned on at the beginning of the self-discharge stage S2, where Vth is the threshold voltage of P0 when there is no backgate effect; In the self-discharge stage S2, AZ supplies a low voltage signal, WS1 supplies a low voltage signal, WS2 supplies a low voltage signal, DS supplies a high voltage signal, R1 supplies a reference voltage Vref, DW supplies a reference voltage Vref, P4 is turned on to connect the drain of P0 to the ground terminal G1, P3 is turned on to input the reference voltage Vref to the gate of P0, P1 is turned on, and P2 is turned off; At the start of the self-discharge stage S2, P0 is turned on and discharged through P0 and P4, thereby decreasing the source potential Vs of P0. As Vs decreases, the backgate effect occurs, and |Vth_ef| is equal to a×(VDD-Vs)+|Vth|, where Vth_ef is the threshold voltage of P0 when the backgate effect is present, and a is the coefficient of the backgate effect. As Vs decreases, Vgs also decreases at the same time. When |Vth_ef| increases and becomes equal to |Vgs|, P0 is turned off and the discharge is stopped. At this time, a×(VDD-Vs)+|Vth|=Vg-Vs.

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[0070] As can be seen from the above operation process, during the operation of at least one embodiment of the pixel circuit shown in FIG. 5 of the present disclosure, in the light emitting stage, the gate-source voltage of the driving transistor P0 can compensate for the threshold voltage of the driving transistor P0, so that the light emitting current of the organic light emitting diode O1 is independent of the threshold voltage Vth, and the display uniformity is improved.

[0071] At least one embodiment of the pixel circuit shown in FIG. 5 of the present disclosure is a current-type pixel circuit using all PMOS transistors, and has a wider anode dynamic range than a current-type pixel circuit constructed using NMOS transistors under a comparable process platform, for the following reasons. In the case of a current-type pixel circuit constructed using NMOS transistors, when the anode voltage of the organic light-emitting diode O1 is set to a negative voltage, the negative voltage is input to the source or drain of the transistor in the pixel circuit, and if the transistor is an n-type transistor, a forward-biased diode exists between the back gate and source of the transistor, causing a latch-up effect and causing the pixel circuit to operate abnormally. Therefore, a current-type pixel circuit using PMOS transistors has a wider anode dynamic range, and if the transistors in the current-type pixel circuit are all PMOS transistors, the potential of the anode of the organic light-emitting diode O1 may be a negative voltage.

[0072] At least one embodiment of the pixel circuit as shown in FIG. 5 of the present disclosure uses a current type pixel driving method, and the driving transistor included in the driving circuit in at least one embodiment of the pixel circuit as shown in FIG. 5 of the present disclosure is a PMOS transistor, so that if the anode of O1 and the cathode of O1 are shorted, no spot or line defect will occur due to the anode voltage of O1 being negative.

[0073] At least one embodiment of the pixel circuit as shown in FIG. 5 of the present disclosure can prevent the occurrence of the low grayscale bright spot phenomenon caused by leakage from the N-type base of the first transistor P1 for transmitting a data voltage to the first capacitance C1 toward the drain of the first transistor P1, and the cause of this phenomenon is as follows: The transistors used in at least one embodiment of the pixel circuit as shown in FIG. 5 of the present disclosure are PMOS transistors. Therefore, even if current leaks from the N-type base of the first transistor P1 toward the drain of the first transistor P1 to the first capacitor C1 during a non-light-emitting stage, causing the potential of the gate of P0 to increase, the light emission brightness of the organic light-emitting diode is not increased and no bright spot is generated because the drive transistor P0 is also a PMOS transistor.

[0074] In the related art, P0 is an NMOS transistor, and the higher the potential of the gate of P0, the brighter the organic light-emitting diode becomes, so that when light leaks from the drain of P1 to the first capacitor C1 during the non-emitting stage, the potential of the gate of P0 rises, increasing the luminance of the organic light-emitting diode and causing a bright spot. In view of this, at least one embodiment of the present disclosure sets the transistor to a PMOS transistor in order to solve the above problem.

[0075] At least one embodiment of the pixel circuit shown in FIG. 5 of the present disclosure is a current-type pixel circuit, which can compensate for the decrease in lifetime caused by an increase in the internal resistance of the organic light-emitting diode O1, and in at least one embodiment of the pixel circuit shown in FIG. 5 of the present disclosure, a high voltage VDD is applied to the back gate of each transistor, but ELVDD is not applied, so that the n-well potential of the base of each transistor is separated from ELVDD, and as a result, ELVDD can be flexibly set within a range smaller than VDD.

[0076] At least one embodiment of the pixel circuit as shown in FIG. 5 of the present disclosure may be, but is not limited to, a current-type pixel circuit applied to a silicon-based OLED (organic light-emitting diode) microdisplay chip. At least one embodiment of the present disclosure is based on a specific semiconductor process platform and uses only PMOS transistors to design a pixel circuit, thereby overcoming the space restriction of MOS transistors due to design rules in a pixel circuit in which PMOS transistors and NMOS transistors are mixed, and can effectively reduce the pixel area and improve the PPI (Pixels Per Inch).

[0077] In at least one embodiment of the present disclosure, the fourth transistor may be an N-type transistor, and in this case, the third voltage terminal may be a reset voltage terminal.

[0078] In a specific implementation, when the fourth transistor is an NMOS transistor, the back gate of the fourth transistor and the source of the fourth transistor may be electrically connected to a reset voltage terminal; A deep n-well is provided between the back gate and the P-type base of the fourth transistor so as to isolate the back gate and the P-type base of the fourth transistor, and the back gate of the fourth transistor and the source of the fourth transistor are both electrically connected to the reset voltage terminal.

[0079] In a related technology, in a display panel, the back gate of an N-type transistor in a pixel circuit and the back gate of an N-type transistor in a drive circuit (the drive circuit is for supplying a drive signal to the pixel circuit) are both electrically connected to the P-type base, whereas in at least one embodiment of the present disclosure, the back gate of a fourth transistor in a pixel circuit needs to be electrically connected to a reset voltage terminal and a voltage signal of 0V is input to the P-type base, so that a deep n-well needs to be provided between the P-type base and the back gate of the fourth transistor in order to isolate the P-type base and the back gate of the fourth transistor.

[0080] In at least one embodiment of the present disclosure, the dynamic range of the anode of the organic light emitting diode O1 needs to be expanded to negative voltage, and if the withstand voltage of each transistor is 8V and ELVDD is 3V, the minimum anode reset voltage can be -5V, so it is necessary to input a voltage signal of -5V to the back gate of the fourth transistor (generally, the source of an NMOS transistor and the back gate of an NMOS transistor are electrically connected to the same voltage terminal). Therefore, it is necessary to isolate the P-type base from the back gate of the fourth transistor.

[0081] FIG. 7 is a structural diagram of an NMOS transistor and a PMOS transistor in accordance with at least one embodiment of the present disclosure.

[0082] In FIG. 7, reference numeral 60 denotes a P-type base, reference numeral 61 denotes a deep n-well, reference numeral 621 denotes a gate of an NMOS transistor, reference numeral 622 denotes a gate of a PMOS transistor, reference numeral 631 denotes a backgate of an NMOS transistor, reference numeral 632 denotes a source of an NMOS transistor, reference numeral 633 denotes a drain of an NMOS transistor, reference numeral 641 denotes a backgate of a PMOS transistor, reference numeral 642 denotes a source of a PMOS transistor, reference numeral 643 denotes a drain of a PMOS transistor, reference numeral 65 denotes an insulating structure, reference numerals 661 and 663 denote N-wells, and reference numeral 662 denotes a P-well.

[0083] In FIG. 7, the NMOS transistor may be the fourth transistor.

[0084] As shown in FIG. 7, a deep n-well 61 is provided between the back gate 631 of the NMOS transistor and the P-type base 60 so as to enable a voltage signal of −5 V to be input to the back gate of the NMOS transistor while a voltage signal of 0 V can be input to the P-type base 60.

[0085] Optionally, the pixel circuit according to at least one embodiment of the present disclosure may further include an n-well, and the doping concentration of the n-well is greater than the doping concentration of the deep n-well; The ratio of the thickness of the n-well to the thickness of the deep n-well is 0.4 to 0.6, but is not limited thereto.

[0086] For example, the thickness of the n-well may be 0.5 um, and the thickness of the deep n-well may be 1 um.

[0087] In a specific implementation, the pixel circuit described in at least one embodiment of the present disclosure may further include a p-well, and the ratio of the thickness of the p-well to the thickness of the deep n-well is greater than or equal to 0.4 and less than or equal to 0.6.

[0088] For example, the thickness of the p-well may be 0.5um and the thickness of the deep n-well may be 1um.

[0089] In the related art, since a deep n-well is not provided between the back gate 631 and the P-type base 60 of the NMOS transistor, it is not possible to input different voltage signals to the back gate 631 and the P-type base 60 of the NMOS transistor.

[0090] FIG. 8 is a schematic diagram showing the structures of an NMOS transistor and a PMOS transistor in the related art.

[0091] FIG. 8 differs from FIG. 7 in that the deep n-well 61 is not provided.

[0092] As shown in FIG. 9, in addition to at least one embodiment of the pixel circuit shown in FIG. 5, the pixel circuit according to at least one embodiment of the present disclosure further includes a first resistor R01; The first resistor R01 is connected between the drain of the driving transistor P0 and the anode of the organic light emitting diode O1; A first end of the first resistor R01 is electrically connected to the drain of the driving transistor P0, and a second end of the first resistor R01 is electrically connected to the anode of the organic light emitting diode O1; The first resistor R01 can prevent a short circuit between the anode of the organic light emitting diode O1 and the cathode of the organic light emitting diode O1.

[0093] A display panel according to an embodiment of the present disclosure includes multiple rows and multiple columns of the pixel circuits described above.

[0094] A driving method according to an embodiment of the present disclosure is applied to the pixel circuit described above, and the driving method includes: A write control circuit controls the write end and the second end of the second energy storage circuit to communicate with each other or to be cut off under the control of a first write control signal; A first control circuit controls, under the control of a first control signal, to connect or disconnect a power supply voltage terminal and a first terminal of the driving circuit; The drive circuit generates a drive current for driving the light emitting element under control of the potential of the control end.

[0095] Optionally, a display period of the pixel circuit includes an initialization stage, a self-discharge stage, a data preparation stage, a data writing stage and a light emitting stage, which are set in sequence, and the driving method according to at least one embodiment of the present disclosure includes: During the initialization step, the data preparation step, the data writing step and the light emitting step, the first control circuit controls the power supply voltage terminal and the first terminal of the driving circuit to communicate with each other under the control of the first control signal; In the self-discharge step, the first control circuit may control, under control of the first control signal, to cut off between the power supply voltage terminal and the first terminal of the driving circuit.

[0096] Optionally, a display period of the pixel circuit includes an initialization stage, a self-discharge stage, a data preparation stage, a data writing stage and a light emitting stage, which are set in sequence, and the driving method according to at least one embodiment of the present disclosure includes: In the initialization step, the data preparation step and the light emission step, the write control circuit controls the write end and the second end of the second energy storage circuit to be disconnected under the control of a first write control signal; In the self-discharge step and the data writing step, the write control circuit may control, under control of the first write control signal, to communicate between the write end and the second end of the second energy storage circuit.

[0097] A display device according to at least one embodiment of the present disclosure includes the above-mentioned display panel.

[0098] In at least one embodiment of the present disclosure, the display panel includes a first silicon substrate, and a pixel circuit and a gate driving circuit disposed on the first silicon substrate; The display device further includes a second silicon substrate and a display driver chip disposed on the second silicon substrate.

[0099] In a specific implementation, the area of ​​the first silicon substrate is larger than the area of ​​the second silicon substrate; The minimum width of a signal line included in the display panel is greater than the width of a signal line included in the display driver chip.

[0100] As shown in FIG. 10, the display panel includes a first silicon substrate 201, and a pixel circuit and a gate driving circuit 202 provided on the first silicon substrate 201. In FIG. 20, the symbol A0 is an effective display area, and the pixel circuit is provided in the effective display area. The display device further includes a second silicon substrate 203 and a display driver chip disposed on the second silicon substrate 203 .

[0101] In at least one embodiment of the present disclosure, a first transistor included in the pixel circuit, a fourth transistor included in the pixel circuit, and a second capacitance included in the pixel circuit may be provided outside the effective display area, and a drive transistor included in the pixel circuit, a second transistor included in the pixel circuit, a third transistor included in the pixel circuit, and a second capacitance included in the pixel circuit may be provided inside the effective display area, but is not limited to this.

[0102] Optionally, but not limited to, the capacitance value of the first capacitance is greater than the capacitance value of the second capacitance.

[0103] As shown in FIG. 10, the display driving chip may include, but is not limited to, a display driving integrated circuit 301, a source driver 302, a timing controller 303, a data processor 304, an input / output interface 305, a signal receiver 306, and a bias voltage and reference voltage supply circuit 307.

[0104] In at least one embodiment of the present disclosure, the area of ​​the first silicon substrate is larger than the area of ​​the second silicon substrate; The minimum width of a signal line included in the display panel is greater than the width of a signal line included in the display driver chip.

[0105] In at least one embodiment of the present disclosure, the display panel and the display driving chip may be manufactured using different process recipes, for example, the display panel may be manufactured using a 100 nm process and the display driving chip may be manufactured using a 28 nm process so that the line width of the signal lines included in the display driving chip is smaller than the line width of the signal lines included in the display panel and the spacing between the signal lines included in the display driving chip is smaller than the spacing between the signal lines included in the display panel.

[0106] The display device according to the embodiment of the present disclosure may be any product or part having a display function, such as a mobile phone, a tablet PC, a television, a display, a notebook PC, a digital photo frame, or a navigator.

[0107] The above is a preferred embodiment of the present disclosure, and it should be noted that those skilled in the art may further make some improvements and modifications without departing from the principles described in the present disclosure, and these improvements and modifications should also be considered to be within the scope of protection of the present disclosure.

Claims

1. A pixel circuit including a light-emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a writing control circuit, and a first control circuit, wherein a first end of the first energy storage circuit is electrically connected to a control end of the driving circuit, a second end of the first energy storage circuit is electrically connected to a first end of the driving circuit, and the first energy storage circuit is used to store electrical energy, a first end of the second energy storage circuit is electrically connected to the control end of the driving circuit, and the second energy storage circuit is used to store electrical energy, the writing control circuit is electrically connected to a first writing control end, a writing end, and a second end of the second energy storage circuit respectively, and is used to control so that communication or interruption is made between the writing end and the second end of the second energy storage circuit under the control of a first writing control signal supplied by the first writing control end, the first control circuit is electrically connected to a first control end, a power supply voltage end, and the first end of the driving circuit respectively, and is used to control so that communication or interruption is made between the power supply voltage end and the first end of the driving circuit under the control of a first control signal supplied by the first control end, a second end of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to generate a driving current for driving the light-emitting element under the control of the potential of its control end.

2. The first control circuit is used to control so that communication is made between the power supply voltage end and the first end of the driving circuit under the control of the first control signal in two discontinuous stages within one display period, according to the pixel circuit of Claim 1.

3. The display period of the pixel circuit includes an initialization stage, a self-discharge stage, a data preparation stage, a data writing stage, and a light-emitting stage set successively, and the first control circuit is used to control so that communication is made between the power supply voltage end and the first end of the driving circuit under the control of the first control signal in the initialization stage, the data preparation stage, the data writing stage, and the light-emitting stage, and to control so that interruption is made between the power supply voltage end and the first end of the driving circuit under the control of the first control signal in the self-discharge stage, according to the pixel circuit of Claim 2.

4. The writing control circuit is used to control, under the control of the first writing control signal, the disconnection between the writing terminal and the second terminal of the second energy storage circuit during the initialization stage, the data preparation stage, and the light emission stage, and to control, under the control of the first writing control signal, the communication between the writing terminal and the second terminal of the second energy storage circuit during the self-discharge stage and the data writing stage. The pixel circuit according to claim 3.

5. Further including a reference voltage writing circuit, The reference voltage writing circuit is electrically connected to the second writing control terminal, the reference voltage terminal, and the control terminal of the driving circuit respectively, and is used to write the reference voltage supplied by the reference voltage terminal to the control terminal of the driving circuit under the control of the second writing control signal supplied by the second writing control terminal. The reference voltage writing circuit includes a third transistor. The control electrode of the third transistor is electrically connected to the second writing control terminal, the first electrode of the third transistor is electrically connected to the reference voltage terminal, the second electrode of the third transistor is electrically connected to the control terminal of the driving circuit, and the back gate of the third transistor is electrically connected to the second voltage terminal. The pixel circuit according to any one of claims 1 to 4.

6. Further including a second control circuit, the second terminal of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the first voltage terminal. The second control circuit is electrically connected to the second control terminal, the reset voltage terminal, and the first electrode of the light-emitting element respectively, and is used to control, under the control of the second control signal supplied by the second control terminal, the writing of the reset voltage supplied by the reset voltage terminal to the first electrode of the light-emitting element. The second control circuit includes a fourth transistor. The control electrode of the fourth transistor is electrically connected to the second control terminal, the first electrode of the fourth transistor is electrically connected to the reset voltage terminal, the second electrode of the fourth transistor is electrically connected to the first electrode of the light-emitting element, and the back gate of the fourth transistor is electrically connected to the third voltage terminal. The pixel circuit according to any one of claims 1 to 4.

7. The pixel circuit according to any one of claims 1 to 4 further includes a resistance circuit, a second end of the driving circuit is electrically connected to a first pole of the light emitting element through the resistance circuit, and a second pole of the light emitting element is electrically connected to a first voltage terminal.

8. The first energy storage circuit includes a first capacitor, the second energy storage circuit includes a second capacitor, and the writing control circuit includes a first transistor. A first end of the first capacitor is electrically connected to a control end of the driving circuit, and a second end of the first capacitor is electrically connected to a first end of the driving circuit. A first end of the second capacitor is electrically connected to the control end of the driving circuit. A control pole of the first transistor is electrically connected to the first writing control end, a first pole of the first transistor is electrically connected to the writing end, a second pole of the first transistor is electrically connected to a second end of the second capacitor, and a back gate of the first transistor is electrically connected to a second voltage terminal. The pixel circuit according to any one of claims 1 to 4.

9. The first control circuit includes a second transistor, and the driving circuit includes a driving transistor. A control pole of the second transistor is electrically connected to the first control end, a first pole of the second transistor is electrically connected to the power supply voltage terminal, a second pole of the second transistor is electrically connected to a first end of the driving circuit, and a back gate of the second transistor is electrically connected to the second voltage terminal. A control pole of the driving transistor is the control end of the driving circuit, a first pole of the driving transistor is the first end of the driving circuit, a second pole of the driving transistor is the second end of the driving circuit, and a back gate of the driving transistor is electrically connected to the second voltage terminal. The pixel circuit according to any one of claims 1 to 4.

10. The fourth transistor is an n-type transistor, and the third voltage terminal is the reset voltage terminal, or The fourth transistor is a p-type transistor, and the third voltage terminal is the second voltage terminal. The pixel circuit according to claim 6.

11. The fourth transistor is an n-type transistor, and a deep n-well is provided between the back gate of the fourth transistor and the P-type base so that the back gate of the fourth transistor and the P-type base are isolated from each other. The back gate of the fourth transistor and the first pole of the fourth transistor are both electrically connected to the reset voltage terminal. The pixel circuit further includes an n-well and a p-well. The doping concentration of the n-well is greater than the doping concentration of the deep n-well. The ratio of the thickness of the n-well to the thickness of the deep n-well is 0.4 or more and 0.6 or less. The ratio of the thickness of the p-well to the thickness of the deep n-well is 0.4 or more and 0.6 or less. The pixel circuit according to claim 10.

12. A display panel including a plurality of rows and a plurality of columns of the pixel circuits according to claim 1.

13. A driving method applied to the pixel circuit according to claim 1, wherein the driving method includes: The writing control circuit controls, under the control of the first writing control signal, the communication or interruption between the writing terminal and the second terminal of the second energy storage circuit. The first control circuit controls, under the control of the first control signal, the communication or interruption between the power supply voltage terminal and the first terminal of the driving circuit. The driving circuit generates a driving current for driving the light-emitting element under the control of the potential of its control terminal.

14. The driving method includes: Within one display period, in two discontinuous stages, the first control circuit controls, under the control of the first control signal, the communication between the power supply voltage terminal and the first terminal of the driving circuit. The display period of the pixel circuit includes an initialization stage, a self-discharge stage, a data preparation stage, a data writing stage, and a light-emitting stage set in sequence. The driving method includes: In the initialization stage, the data preparation stage, the data writing stage, and the light-emitting stage, the first control circuit controls, under the control of the first control signal, the communication between the power supply voltage terminal and the first terminal of the driving circuit. In the self-discharge stage, the first control circuit controls, under the control of the first control signal, the interruption between the power supply voltage terminal and the first terminal of the driving circuit. Or The display period of the pixel circuit includes an initialization stage, a self-discharge stage, a data preparation stage, a data writing stage, and a light-emitting stage that are set successively. The driving method is as follows: In the initialization stage, the data preparation stage, and the light-emitting stage, the writing control circuit controls so that the connection between the writing terminal and the second terminal of the second energy storage circuit is blocked under the control of the first writing control signal. The driving method according to claim 13, further including: in the self-discharge stage and the data writing stage, the writing control circuit controls so that the connection between the writing terminal and the second terminal of the second energy storage circuit is communicated under the control of the first writing control signal.

15. A display device including the display panel according to claim 12, wherein the display panel includes a first silicon substrate, a pixel circuit provided on the first silicon substrate, and a gate driving circuit. The display device further includes a second silicon substrate and a display driving chip provided on the second silicon substrate. The area of the first silicon substrate is larger than the area of the second silicon substrate. A display device, wherein the minimum width of the signal lines included in the display panel is larger than the width of the signal lines included in the display driving chip.

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