A computer memory system that employs local generation of a global bit line (GBL) clock signal to reduce the branching of a clock signal read path to improve signal tracking, and related methods

Abstract

A computer memory system that employs local generation of a global bit line (GBL) clock signal to reduce the branching of the clock signal read path to improve signal tracking, and a related method. The memory system includes one or more memory banks each including a memory array composed of memory bit cells organized into respective memory row circuits and memory column circuits. A global bit line (GBL) keeper circuit in the GBL control path within the memory system is coupled to the GBL to latch output read data from a word line path within a selected memory row circuit of a selected memory bank in a read operation. To improve the tracking of the timing of the GBL control path with the word line path within the memory row circuit, the GBL clock signal and the local WL clock signal within a given memory bank are locally separately supplied from one source clock within the selected memory bank.

Description

Technical Field

[0001] The technology of the present disclosure relates to computer memory systems, and more particularly, to memory arrays implemented with multiple memory banks to improve memory performance and power consumption.

Background Art

[0002] A processor-based system including a memory system supports read and write operations from a central processing unit (CPU) or other processors. Memory is used not only for data storage but also for storing program code for storing instructions to be executed. Such processor-based systems have conventionally employed both cache and non-cache system memories. For example, a processor can include a local cache memory. In a processor-based system, multiple CPUs can access a shared cache memory. A processor-based system also employs a main memory or system memory that includes memory storage units (i.e., memory bit cells) across the physical address space of the processor-based system. Each of these various types of memory generally employs a memory array including memory bit cells organized in a matrix structure for storing data. Memory rows containing memory bit cells in each column are accessed to read data words from the memory or write data words to the memory. Memory bit cells can be provided in memories of various technologies, such as bit cells of static random access memory (RAM) (SRAM) or dynamic RAM (DRAM).

[0003] Generally, to improve memory performance and power consumption, it is desirable to implement a memory system with a large-sized memory array using multiple memory banks. By providing multiple memory banks in the memory system, the memory capacity can be divided into different arrays that can be accessed independently. Also, providing memory banks separately in the memory system means that the power consumption can be managed independently from other memory banks for each memory bank. Therefore, for example, if software or data is persistent in one part of the memory but not in another part, these separate parts of the memory may be divided into separate memory banks, thereby saving power without affecting other parts that may be fully powered for memory access while each is separately powered down or put into an idle state.

[0004] The trade-off of adopting memory banking in a memory system is not only the dynamic power consumption of reading, but also the requirement for a hierarchical clock signal to control and optimize the timing of the critical path of reading. Different control signals are generated at the local memory bank level and at the global level where signals from different memory banks (e.g., global bit lines (GBL)) are combined to produce the final output read data. For example, the local word line (WL) clock signal used to control the timing of the local decoding operation within the memory bank selected for the read operation may be generated from the global source clock. Also, the GBL clock signal generated from the same source clock may be used to control the timing of the GBL keeper circuit that latches the data value of the output read data from the selected memory array before the next read operation. The timing of the global path and the local path of the memory system need to be adjusted or tracked with each other to avoid glitches and performance delays of the memory data. For example, if the GBL clock signal latches the GBL in the GBL keeper circuit before the local WL clock signal asserts new data from the memory read to the GBL, the GBL keeper circuit may compete with the GBL driver circuit. On the other hand, if the GBL clock signal is overly delayed and delays the latch of the GBL keeper circuit, it may keep the GBL in a floating state for a long time even after the output read data becomes available, thus lengthening the memory access time. Implementing such clock signal tracking becomes even more difficult due to various process, voltage, temperature (PVT) variations. SUMMARY OF THE INVENTION

[0005] Exemplary aspects disclosed herein include a computer memory system that employs local generation of a global bit line (GBL) clock signal to reduce the branching of a clock signal read path to improve signal tracking. Related methods are also disclosed. The memory system includes one or more memory banks each including a memory array composed of a plurality of memory bit cells organized into respective memory row circuits and memory column circuits. Memory words are read or written by selecting memory row circuits within a word line (WL) path according to a memory address decoded by a decode circuit. The memory system includes a global decode circuit that decodes a memory address for memory operation to select a memory bank for a memory access. Each memory bank includes a local decode circuit that further decodes the memory address to select a corresponding memory row circuit within the memory array for a memory access. In each of one or more memory banks within the memory system, each memory row circuit is coupled to a global bit line (GBL). A selected memory row circuit within a selected memory bank for a read operation asserts its output read data to the GBL for providing to a requesting circuit within the computer system. A GBL keeper circuit within a GBL control path within the memory system is coupled to the GBL and latches the output read data from the WL path within the selected memory row circuit of the selected memory bank in a read operation. A local WL clock signal and a GBL clock signal both supplied from one source clock control the respective timings of a selected memory row circuit within a selected memory bank and the timing of the GBL control path in a read operation. It is important that the timing of the GBL control path is synchronized (i.e., tracked) with the timing of the word line path. This is to prevent the output read data asserted by the selected memory row circuit on the GBL from being latched by the GBL keeper circuit too early and competing with other memories accessed earlier on the GBL, or being latched too late to lengthen the memory access time.In this regard, a delay circuit may be inserted into the GBL control path to track these timing paths based on different circuit paths of the local WL clock signal and the GBL clock signal. However, tracking becomes more difficult because the effects of various process, voltage, and temperature (PVT) variations reach the access path. Increasing the delay of the delay circuit in the GBL control path can offset the effects of PVT variations, but at the cost of shortening the memory access time.

[0006] In this regard, in an exemplary aspect, in order to improve the tracking of the timing of the GBL control path with the word line path of the memory row circuits within a memory bank, the GBL clock signal and the local WL clock signal within a given memory bank are locally supplied separately from a single source clock within the selected memory bank. This is in contrast to separately supplying the GBL clock signal and the local WL clock signal outside of the selected memory bank in the global area of the memory system, where the path lengths of the separately provided GBL clock signal and local WL clock signal would be longer than if such clock signals were locally generated within the selected memory bank. In this way, the separate and different path lengths that the GBL clock signal and the local WL clock signal pass through after being separately supplied from the source clock are shortened. Thereby, the timing differences that occur in separate GBL control paths and WL paths as a result of PVT variations in the memory system can be reduced. To locally generate the GBL clock signal and the local WL clock signal within the selected memory bank, a clock control generation circuit is locally provided within the memory bank and coupled between the global decode circuit and each of the memory circuit rows within the memory bank. In this way, as a result of the decode operation from the global decode circuit, when a given memory bank is selected for a read operation, the clock control generation circuit receives an indication that that memory bank is selected. Then, the clock control generation circuit can generate the GBL clock signal and the local WL clock signal using the indication that that memory bank is selected. In an exemplary aspect, the clock control generation circuit can be implemented as an OR-based logic circuit coupled to each of the memory row circuits, and the GBL clock signal and the local WL clock signal are generated as a result of selecting any one of the memory row circuits within the selected memory bank. In one example, the OR-based logic circuit within the clock control generation circuit may be provided as a dynamic circuit where separate transistors are coupled to each memory row circuit and a common precharge line.In this manner, when any one of the memory row circuits is selected within a given memory bank, the precharge line is pulled down to an active state and a GBL clock signal is generated within the GBL control path.

[0007] In another exemplary aspect, a memory bank within a memory system includes distinct memory sub-banks that are controlled by a memory sub-bank control circuit. The memory sub-bank control circuit includes circuitry that also needs to be clocked by a clock signal supplied from the source clock in order to control the multiplexing of the outputs of the memory row circuits from each of the distinct memory sub-banks to the GBL. Again, it is important that the timing of the circuit path of the memory sub-bank control circuit track the WL path of the selected memory row circuit within the selected memory sub-bank so that the read output data from the selected memory row circuit is not asserted on the GBL too early or too late. In this regard, in another example, the clock control generation circuit is also configured to generate a local memory sub-bank clock signal that controls the timing of the memory sub-bank control path within the memory sub-bank control circuit. The clock control generation circuit is configured to separately generate (i.e., divide) the memory sub-bank clock signal from the source block, similar to the GBL clock signal and the local WL clock signal.

[0008] In this regard, in an exemplary aspect, a memory system is provided. The memory system includes a first memory array including a plurality of first memory row circuits. Each of the plurality of first memory row circuits is configured to generate first output read data coupled to a plurality of global bit lines (GBLs) in response to a first global read word line (RWL) signal on the plurality of global RWLs indicating selection of the first memory row circuit of the plurality of first memory row circuits for a first read operation and in response to a first local WL clock signal. The memory system also includes a GBL keeper circuit coupled to the plurality of GBLs. The GBL keeper circuit is configured to latch the first output read data onto the plurality of GBLs in response to a GBL clock signal. The memory system also includes a clock control generation circuit including a local clock node. The clock control generation circuit is configured to receive a source clock, receive a first global RWL signal on the plurality of global RWLs indicating a first read operation to the first memory array, generate a first local WL clock signal from the source clock received on the local clock node in response to receiving the first global RWL signal, and generate a GBL clock signal from the source clock received on the local clock node.

[0009] In another exemplary aspect, a method is provided for generating a GBL clock signal that clocks a GBL keeper circuit within a memory system. The method includes receiving a source clock. The method also includes receiving a first global RWL signal on a plurality of global RWLs indicative of a first read operation to a selected first memory row circuit among a plurality of first memory row circuits. In response to receiving the first global RWL signal, the method also includes generating a first local WL clock signal from the source clock received on a local clock node, generating a GBL clock signal from the source clock received on the local clock node, the first global RWL signal on the plurality of global RWLs indicating a selection of the first memory row circuit, and in response to the first local WL clock signal, generating first output read data coupled to a plurality of GBLs from the selected first memory row circuit. The method also includes latching the first output read data onto the plurality of GBLs in response to the GBL clock signal.

[0010] Those skilled in the art will understand the scope of the present disclosure and realize its further aspects upon reading the following detailed description of the preferred embodiments in connection with the accompanying drawings. The accompanying drawings, which are incorporated herein and constitute a part of this specification, illustrate some aspects of the present disclosure and together with the description serve to explain the principles of the present disclosure.

Brief Description of the Drawings

[0011]

Figure 1

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[0012] Exemplary aspects disclosed herein include a computer memory system that employs local generation of a global bit line (GBL) clock signal to reduce the branching of the clock signal read path to improve signal tracking. Related methods are also disclosed. The memory system includes one or more memory banks, each including a memory array composed of a plurality of memory bit cells organized into respective memory row circuits and memory column circuits. Memory words are read or written by selecting a memory row circuit within a word line (WL) path according to a memory address decoded by a decode circuit. The memory system includes a global decode circuit that decodes a memory address for memory operation to select a memory bank for memory access. Each memory bank includes a local decode circuit that further decodes the memory address to select a corresponding memory row circuit within the memory array for memory access. In each of one or more memory banks within the memory system, each memory row circuit is coupled to a global bit line (GBL). The selected memory row circuit within the selected memory bank for a read operation asserts its output read data on the GBL to be provided to a requesting circuit within the computer system. A GBL keeper circuit within the GBL control path within the memory system is coupled to the GBL and latches the output read data from the WL path within the selected memory row circuit of the selected memory bank in a read operation. A local WL clock signal and a GBL clock signal, both supplied from a single source clock, control the respective timings of the selected memory row circuits within the selected memory bank and the timing of the GBL control path in a read operation. It is important that the timing of the GBL control path is synchronized (i.e., tracked) with the timing of the word line path. This is to prevent the output read data asserted by the selected memory row circuit on the GBL from being latched by the GBL keeper circuit too early and competing with other memories accessed earlier on the GBL, or being latched too late and lengthening the memory access time.In this regard, a delay circuit may be inserted into the GBL control path in order to track these timing paths based on different circuit paths of the local WL clock signal and the GBL clock signal. However, tracking becomes more difficult due to the effects of various process, voltage, temperature (PVT) variations on the access path. Increasing the delay of the delay circuit in the GBL control path can offset the effects of PVT variations, but at the cost of shortening the memory access time.

[0013] In this regard, in an exemplary aspect, in order to improve the tracking of the timing between the GBL control path and the word line path of the memory row circuits within a memory bank, the GBL clock signal and the local WL clock signal within a given memory bank are locally supplied separately from a single source clock within the selected memory bank. This is in contrast to separately supplying the GBL clock signal and the local WL clock signal outside of the selected memory bank in the global area of the memory system, where the path lengths of the separately provided GBL clock signal and local WL clock signal would be longer than if such clock signals were locally generated within the selected memory bank. In this way, the separate and different path lengths that the GBL clock signal and the local WL clock signal pass through after being separately supplied from the source clock are shortened. Thereby, the timing differences that occur between the separate GBL control path and the WL path as a result of PVT variations in the memory system can be reduced. To locally generate the GBL clock signal and the local WL clock signal within the selected memory bank, a clock control generation circuit is locally provided within the memory bank and coupled between the global decode circuit and each of the memory circuit rows within the memory bank. In this way, as a result of the decode operation from the global decode circuit, when a given memory bank is selected for a read operation, the clock control generation circuit receives an indication that that memory bank is selected. Then, the clock control generation circuit can generate the GBL clock signal and the local WL clock signal using the indication that that memory bank is selected. In an exemplary aspect, the clock control generation circuit may be implemented as an OR-based logic circuit coupled to each of the memory row circuits, and the GBL clock signal and the local WL clock signal are generated as a result of selecting any one of the memory row circuits within the selected memory bank. In one example, the OR-based logic circuit within the clock control generation circuit may be provided as a dynamic circuit where separate transistors are coupled to each memory row circuit and a common precharge line.In this manner, when any one of the memory row circuits is selected within a given memory bank, the precharge line is pulled down to an active state and a GBL clock signal is generated within the GBL control path.

[0014] An example of a computer memory system that employs local generation of a GBL clock signal to reduce the branching of the clock signal readout path to improve signal tracking begins with FIG. 4. Before discussing these memory systems, an exemplary processor-based system including a memory system that includes the supply of a global bit line (GBL) clock signal for clocking a GBL keeper circuit within a global GBL control path outside of a memory bank within the memory system is first described in FIGS. 1-3 below.

[0015] In this regard, FIG. 1 is a diagram of an exemplary processor-based system 100 that includes a processor 102 configured to issue memory requests (i.e., data read requests and data write requests) to a memory system 104. The memory system 104 includes a cache memory system 106 and a system memory 108. The system memory 108 is memory that can be fully addressed by the physical address (PA) space of the processor-based system 100. For example, the system memory 108 may be a dynamic random access memory (DRAM) provided on a separate DRAM chip. The processor 102 includes one or more respective CPUs 110(0)-110(N), where "N" is a positive integer representing the number of CPUs included in the processor 102. The processor 102 may be packaged in an integrated circuit (IC) chip 112.

[0016] Continuing to refer to FIG. 1, the cache memory system 106 includes one or more cache memories 114(1) to 114(X), where "X" is a positive integer representing the number of cache memories included in the processor 102. The cache memories 114(1) to 114(X) may be at different levels within the processor-based system 100 and are logically positioned between the CPUs 110(0) to 110(N) and the system memory 108. The memory controller 116 controls access to the system memory 108. For example, in response to processing a load instruction, the CPUs 110(0) to 110(N) as the requesting devices can issue a data request 118 to read data. The data request 118 includes the target address of the data to be read from the memory. Taking CPU 110(0) as an example, if the requested data is not in the private cache memory 114(1) which can be considered as a level 1 (L1) cache memory (i.e., a cache miss for the cache memory 114(1)), the private cache memory 114(1) sends the data request 118, in this example via the interconnect bus 120, to the shared cache memory 114(X) shared by all of the CPUs 110(0) to 110(N) which can be a level 3 (L3) cache memory. The requested data in the data request 118 is ultimately satisfied either in the cache memories 114(1) to 114(X) or, if not included in any of the cache memories 114(1) to 114(X), in the system memory 108.

[0017] The cache memories 114(1) to 114(X) and / or the system memory 108 within the memory system 104 of FIG. 1 can employ a memory array including memory bit cells generally organized in a row structure and a column structure to store data. Memory rows containing memory bit cells in each column are accessed to read data words from the memory or write data words to the memory. The memory bit cells can be provided in memories of different technologies, such as bit cells of static random access memory (RAM) (SRAM) or dynamic RAM (DRAM). As another example, the system memory 108 may be implemented with multiple large-sized memory arrays using multiple memory banks to improve memory performance and power consumption. By providing multiple memory banks in the memory within the memory system 104, the memory capacity can be divided among different arrays that can be independently accessed by the CPUs 110(1) to 110(N). Also, providing separate memory banks in the memory system 104 means that the power consumption for each memory bank can be managed independently from other memory banks. Thus, for example, if software or data is persistent in one part of the memory but not in another, these separate parts of the memory may be divided into separate memory banks, thereby saving power without affecting other parts that may be fully powered for memory access while each is separately powered down or put into an idle state.

[0018] In this regard, FIG. 2 is a diagram of an exemplary memory system 200 that may be included in the memory within the memory system 104 in the processor-based system 100 of FIG. 1 as an example. As shown, in this example the memory system 200 includes eight memory banks 202(0) to 202(7). The memory system 200 also includes a global data input / output (I / O) (GDIO) circuit 204 that includes circuitry capable of supporting each of the memory banks 202(0) to 202(7). As will be described below, the GDIO circuit 204 includes circuitry involved in generating signals for selecting the memory banks 202(0) to 202(7) to be accessed based on the received memory address. Also, as will be described below, the GDIO circuit 204 provides a clock signal supplied from the source clock 206 to clock the circuitry within the GDIO circuit 204 and also locally to the accessed memory banks 202(0) to 202(7) to perform a memory access to the accessed memory address. These clock signals control the timing of the circuitry within the memory system 200 involved in performing the memory access.

[0019] Continuing to refer to FIG. 2, the GDIO circuit 204 receives a source clock for clocking other circuits within the memory system 200 as part of a memory access transaction. The GDIO circuit 204 includes a GDIO clock circuit 208 that generates a GBL clock signal 210 supplied from the source clock 206 to latch output read data from the memory arrays 213(1), 213(2) within the selected memory banks 202(0)-202(7) and controls the selected GBL keeper circuits 212. As shown in the GBL control timing path 3 of FIG. 2, the GBL clock signal 210 is distributed to the GBL keeper circuits 212 within the GDIO circuit 204. As shown in the example of access to the memory bank 202(3) in FIG. 2, the GDIO clock circuit 208 also distributes the source clock 206 to the selected memory bank 202(3) to clock the circuits involved in the memory access to such a memory bank 202(3). In this regard, the global bank clock circuit 214 within the memory bank 202(3) receives the source clock 206. The global bank clock circuit 214 generates a local WL clock signal 216 within the local read WL (RWL) timing path 1 local to the memory bank 202(3) to clock the local decode circuit 218 and optionally the memory bit cells (in the case of dynamic bit cells) within the selected memory arrays 213(1), 213(2) to control the timing of memory access to such memory bit cells. The global bank clock circuit 214 also generates a sub-bank clock signal 224 in the sub-bank control timing path 2 that clocks the multiplexing circuit 225 and controls multiplexing the output read data from the memory arrays 213(1), 213(2) within the selected sub-bank of the memory bank 202(3) for a memory read operation onto the GBL 226 configured to be latched by the GBL keeper circuit 212.

[0020] In this way, different clock signals (GBL clock signal 210, local WL clock signal 216, and sub-bank clock signal 224) are all supplied from the source clock 206, and control the timing of the GDIO circuit 204 and the circuits within the selected memory bank 202(3) for memory access. Therefore, the timings of the global and local paths of the timing paths 1, 2, 3 to which these clock signals 210, 216, 224 are distributed need to track each other to avoid memory data glitches and performance delays. For example, if the GBL clock signal 210 latches GBL226 to the GBL keeper circuit 212 before the local WL clock signal 216 and the global bank clock circuit 214 generate new data from the memory read operation onto GBL226, the GBL keeper circuit 212 may compete with the global bit line driver circuit. On the other hand, if the GBL clock signal 210 is overly delayed to delay the latch of the GBL keeper circuit 212, it may keep GBL226 in a floating state for a long time even after the output read data becomes available, thus lengthening the memory access time. Achieving such tracking of the clock signals 210, 216, 224 becomes even more difficult due to various PVT variations.

[0021] The memory bank 202(3) that can be the memory bank 202 of the memory system 200 in FIG. 2 is shown in more detail in FIG. 3. To further explain the tracking of the GBL clock signal 210, the local WL clock signal 216, and the sub-bank clock signal 224, as well as the problem of the difficulty in tracking due to PVT variations, the memory bank 202 is further described in detail below. In this regard, in this example, the memory bank 202(3) includes two memory sub-banks 300(1), 300(2). Each memory sub-bank 300(1), 300(2) includes respective memory arrays 302(1), 302(2) that include a plurality of memory row circuits 304(1), 304(2). Only two memory row circuits 304(1), 304(2) are shown, each having respective memory bit cells 305(1)(1)~305(1)(X), 305(2)(1)~305(2)(X). However, it should be noted that each memory array 302(1), 302(2) can include a plurality of memory row circuits. In this example, the memory bit cells 305(1)(1)~305(1)(X), 305(2)(1)~305(2)(X) are dynamic static random access memory (DRAM) bit cells that are clocked by local WL clock signals 216(1), 216(2) within local RWL timing path 1 local to the memory bank 202, as opposed to static random access memory (SRAM) bit cells. Each memory sub-bank 300(1), 300(2) also includes respective local decoder circuits 306(1), 306(2) configured to receive the global decoded memory address as a global read word line (RWL) signal 308 (Grwk<31:0>) on the global RWL 309 for memory operation to select the memory bank 202 for memory access. The local decoder circuits 306(1), 306(2) in the selected memory bank 202 are configured to decode such a global RWL signal 308 into local word lines (WL) 310(1), 310(2) and select the corresponding memory row circuits 304(1), 304(2) for memory access.When selected, the memory row circuits 304(1) and 304(2) assert the bits stored in their respective memory bit cells 305(1)(1) to 305(1)(X) and 305(2)(1) to 305(2)(X) to the GBL 226 and are configured to be latched by the GBL keeper circuit 212.

[0022] Continuing to refer to FIG. 3, the memory bank 202 also includes a global bank clock circuit 214 that generates a sub-bank clock signal 224 on a sub-bank control timing path 2 local to the memory bank 202 to clock the GBL bank circuit 227. The sub-bank clock signal 224 controls the GBL bank circuit 227 to multiplex the output read data from the memory arrays 302(1) and 302(2) in the selected memory sub-banks 300(1) and 300(2) of the memory bank 202 for memory read operations onto the GBL 226. The GBL is latched by a GBL keeper circuit 212 clocked by a GBL clock signal 210 on a GBL control timing path 3 in a global area of the memory system 200 outside the memory bank 202, and is configured to latch the output read data from the memory arrays 302(1) and 302(2) onto data outputs 316(1) to 316(X) coupled to the GBL 226. The GBL keeper circuit 212 is coupled to each of the GBL 226. Similar to the number of the GBL 226, the number of the memory bit cells 305(1)(1) to 305(1)(X) is of an "X" bit width. The GBL clock signal 210 is controlled by a global clock gating control (CGC) circuit 312 and is supplied from a source clock 206 at a branch point 207 within a global area of the memory system 200. The GBL clock signal 210 can be delayed by a delay chain circuit 314 to control the timing of the GBL clock signal 210 as a delayed GBL clock signal 210D as part of controlling the tracking of the GBL clock signal 210 with respect to the local WL clock signals 216(1) and 216(2).

[0023] Accordingly, as shown in FIG. 3 and as described above, the GBL clock signal 210, the local WL clock signals 216(1), 216(2), and the sub-bank clock signal 224 are each supplied from the source clock 206 at the branch point 207. The local WL clock signals 216(1), 216(2) and the sub-bank clock signal 224 are locally branched at the branch points 209(1), 209(2) within the memory bank 202. Accordingly, these clock signals 210, 216(1), 216(2), 224 take different respective circuit timing paths 1, 2, and 3 through the local area of the memory bank 202, through the memory sub-banks 300(1), 300(2) and the global bank clock circuit 214, and through the GBL keeper circuit 212 in the global area of the memory system 200. The global and local timings of the timing paths 1 to 3 of the memory system 200 need to be adjusted or tracked with each other to avoid memory data glitches and performance delays. The timing of the sub-bank control timing path 2 needs to be adjusted with the local RWL timing path 1 so that the global bank clock circuit 214 does not multiplex the read output data from the memory arrays 302(1), 302(2) to the GBL 226 before the memory arrays 302(1), 302(1) generate the read output data affected by the local WL clock signals 216(1), 216(2) in the local RWL timing path 1.

[0024] Also, the timing of the GBL control timing path 3 needs to be adjusted with the sub-bank control timing path 2. For example, when the timing of the GBL clock signal 210 is such that the GBL keeper circuit 212 latches GBL226 before the sub-bank clock signal 224 multiplexes new data from the memory read operation into GBL226, the GBL keeper circuit 212 may compete with the GBL driver circuit. On the other hand, if the GBL clock signal 210 is overly delayed to delay the latch of the GBL keeper circuit 212, it may keep GBL226 in a floating state for a long time even after the output read data becomes available at GBL226, thus lengthening the memory access time. Achieving such clock signal tracking becomes even more difficult due to various PVT variations.

[0025] If the branches between the GBL clock signal 210, the local WL clock signals 216(1), 216(2), and the sub-bank clock signal 224 can be delayed to a later local convergence point within the memory bank 202, the timing difference between timing paths 1 to 3 can be reduced with respect to PVT variations compared to the GBL clock signal 210 that branches within the global area of the memory system 200. The GBL clock signal 210, the local WL clock signals 216(1), 216(2), and the sub-bank clock signal 224 can track each other better with respect to PVT variations, and thus, as described above, the memory glitches and latch errors between timing paths 1 and 2, and between timing paths 2 and 3 in FIG. 3 can be minimized.

[0026] In this regard, FIG. 4 is a circuit diagram of another exemplary memory system 400 that includes a memory bank 402 of one or more memory banks. The memory bank 402 does not include memory sub-banks as illustrated in the memory system 200 of FIG. 3. The memory system 400 of FIG. 4 is configured like the memory system 200 of FIG. 2, and the memory bank 402 can be like the memory banks 202(0)-202(7) of the memory system 200 of FIG. 2. The memory bank 402 includes a memory array 403 that includes one or more memory row circuits 404. Note that only one memory row circuit 404 is shown, but the memory array 403 can include multiple memory row circuits 404. As will be described in more detail later, it is desirable to reduce the branch path between the timing path that controls the assertion of the output read data 420 from the selected memory row circuit 404 in the memory array 403 to the GBLs 426(0)-426(X), and the timing path that controls the GBL keeper circuit 412 that latches the output read data 420. In this regard, as will be described in more detail later, the local WL clock signal 416 that controls the local RWL timing path 1 of the selected memory row circuit 404 within the memory bank 402, and the GBL clock signal 411 that controls the GBL control timing path 3 that controls the latching timing of the output read data 420 from the GBLs 426(0)-426(X), are both locally supplied from the source clock 206 within the memory bank 402. In this regard, the local WL clock signal 416 that controls the local RWL timing path 1 and the GBL clock signal 411 that controls the GBL control timing path 3 branch within the local memory bank 402, in contrast to the global branch point within the memory system 400 outside the memory bank 402 as provided in the memory system 200 of FIG. 3. In this way, the branch between the local RWL timing path 1 and the GBL control timing path 3 is reduced, and it becomes possible to be better designed to track each other against PVT variations, so that the memory glitch and latch error between the timing paths 1 and 3 can be minimized.

[0027] Referring to FIG. 4, each memory row circuit 404 includes a plurality of memory bit cells 405(0) to 405(X) organized in a row. For example, the memory bit cells 405(0) to 405(X) can be SRAM bit cells or DRAM bit cells. In this example, the memory bit cells 405(0) to 405(X) are DRAM bit cells clocked by a local WL clock signal 416 within a local RWL timing path 1 local to the memory bank 402. The memory system 400 includes a global decode circuit 434 configured to decode a memory address 436 received for a memory access operation into a globally decoded memory address in order to generate a global RWL signal 408 on a global RWL409(Grwl<31:0>) for the selected memory bank 402. The memory bank 402 includes respective local decoder circuits 406 configured to receive the global RWL signal 408 and generate a local word line (WL) signal 410 on a local WL413 corresponding to a particular memory row circuit 404 within a memory array 403 for memory access. When selected in a memory read operation, the memory row circuit 404 is configured to assert the data bits stored in the respective memory bit cells 405(0) to 405(X) to respective GBLs 426(0) to 426(X) as output read data 420. The timing at which the data bits of the respective memory bit cells 405(0) to 405(X) are asserted to the respective GBLs 426(0) to 426(X) as the output read data 420 is controlled by the local WL clock signal 416. GBL latch 432(0) to 432(2) within the GBL keeper circuit 412 are coupled to the GBLs 426(0) to 426(X) and are configured to latch the output read data 420 from the respective GBLs 426(0) to 426(X) in response to a delayed GBL clock signal 411D which is a delayed version of the GBL clock signal 411. A delay circuit 435 is provided in the GBL control timing path 3 to control the delay of the GBL clock signal 411 to the delayed GBL clock signal 411D.

[0028] Continuing to refer to FIG. 4, memory bank 402 includes a global bank clock circuit 414 configured to receive from source clock 206 and provide the source clock to clock control generation circuit 440. Clock control generation circuit 440 includes local clock node 442. Clock control generation circuit 440 is configured to receive global RWL signal 408 on global RWL 409 for memory read operations. Next, clock control generation circuit 440 is configured to generate a first local WL clock signal 416 supplied from source clock 206 on local clock node 442. Clock control generation circuit 440 is also configured to generate GBL clock signal 411 supplied from source clock 206 on local clock node 442. GBL keeper circuit 412 is coupled to local clock node 442 and includes a GBL clock input 446 that receives GBL clock signal 411 supplied from source clock 206. Both the first local WL clock signal 416 and GBL clock signal 411 are supplied from source clock 206, but the first local WL clock signal 416 and GBL clock signal 411 do not branch into respective local RWL timing path 1 and GBL control timing path 3 until branch point 444 at local clock node 442 that is local within the selected memory bank 402. In this way, the branch between local RWL timing path 1 and GBL control timing path 3 is reduced and can be better designed to track each other against PVT variations, so that memory glitch and latch error between timing paths 1 and 3 can be minimized.

[0029] In this example of the memory system 400 of FIG. 4, it is desirable to control the clock control generation circuit 440 to distribute the source clock 206 to the local clock node 422 only when the memory bank 402 is selected. This is because the clock control generation circuit 440 within the memory bank 402 does not clock the circuits within the local RWL timing path 1 within the memory bank 402 when the memory bank 402 is not selected. It is also desirable for the clock control generation circuit 440 within the memory bank 402 not to clock the circuits within the GBL control timing path 3 when the memory bank 402 is not selected, whereby the GBL keeper circuit 412 can be clocked based on other memory banks accessed within the memory system 400 without contention.

[0030] In this regard, as shown in FIG. 4, the clock control generation circuit 440 also includes an OR-based logic circuit 448 coupled to the global RWL 409. The OR-based logic circuit is a circuit configured to perform an OR logic operation (e.g., OR, NOR, XOR) on an input and generate an output as a result of the logic operation. The OR-based logic circuit 448 is configured to perform an OR-based logic operation on the global RWL signal 408 on the global RWL 409. In this example, to implement the OR-based logic circuit 448, a plurality of pull-down circuits 450 (e.g., N-type field effect transistors (NFETs)). Only one pull-down circuit 450 is shown in FIG. 4, but it should be noted that each of the global RWLs 409 is coupled to the respective gate of each of the respective pull-down circuits 450. In this way, when the global read WL signal 408 becomes active, each of its coupled pull-down circuits 450 becomes active. Since the global RWL 409 is a one-active hot WL, when each memory bank 402 is accessed, only one of the pull-down circuits 450 becomes active. Each of the pull-down circuits 450 is coupled to a clock control output 452 that is coupled to a clock controller 454 (e.g., a NAND gate). The clock control output 452 controls the output of the source clock 206 to the local clock node 442 by the global bank clock circuit 414 by controlling the clock controller 454. When any of the pull-down circuits 450 pulls down the clock control output 452, the clock controller 454 distributes the source clock 206 to the local clock node 442. When none of the pull-down circuits 450 pulls down the clock control output 452, the clock controller 454 does not distribute the source clock 206 to the local clock node 442. In this way, for the clock control generation circuit 440 to distribute the source clock 206 to the local clock node 442 to generate the local WL clock signal 416 and the GBL clock signal 411, the global RWL signal 408 must be active, indicating that its memory bank 402 is selected.

[0031] Note that the clock control output 452 need not be precharged. Alternatively, instead of the OR-based logic circuit 448 including the pull-down circuit 450, the OR-based logic circuit 448 can include a pull-up circuit configured to charge the clock control output 452 in response to its coupled global RWL signal 408 being activated. In this alternative form, the clock control output 452 need not be pre-discharged beforehand.

[0032] FIG. 5 is a flowchart showing an exemplary read operation process 500 executed by a selected memory row circuit in a selected memory bank within a memory system, where both the GBL clock signal and the local WL clock signal are locally supplied from one source clock within the memory bank. The exemplary read operation process 500 of FIG. 5 is discussed with respect to the exemplary memory system 400 of FIG. 4.

[0033] In this regard, the first step of the read operation process 500 is to receive the source clock 206 (block 502 in FIG. 5). The next step of the read operation process 500 is to receive the first global RWL signal 408 on the plurality of global RWLs 409 indicating the first read operation to the selected first memory row circuit 404 among the plurality of first memory row circuits 404 (block 504 in FIG. 5). In response to receiving the first global RWL signal 408 (block 506 in FIG. 5), the next steps can be to generate the first local WL clock signal 416 from the source clock 206 received on the local clock node 442 (block 508 in FIG. 5), generate the GBL clock signal 411 from the source clock 206 received on the local clock node 442 (block 510 in FIG. 5), and in response to the first global RWL signal 408 on the plurality of global RWLs 409 indicating the selection of the first memory row circuit 404 and the first local WL clock signal 416, generate the first output read data 420 coupled to the plurality of GBLs 426(0) to 426(X) from the selected first memory row circuit 404 (block 512 in FIG. 5). The next step in the read operation process 500 can be to latch the first output read data 420 on the plurality of GBLs 426(0) to 426(X) in response to the GBL clock signal 411 (block 514 in FIG. 5).

[0034] Locally supplying a GBL clock signal and a local WL clock signal from one source clock within a memory bank of a memory system can also be achieved in a memory system where the memory bank further includes memory sub - banks. In such a system, the memory bank can further include a sub - bank control circuit including a clocked circuit that controls multiplexing the output read data from a selected memory sub - bank within the memory bank to the GBL latched by a GBL keeper circuit. This sub - bank control circuit has separate clocked timing paths based on a clock signal supplied from one source clock. Also, it is sometimes desirable to minimize the branch in the path length of such timing paths, minimizing the branch in the timing paths from the local RWL timing path for the selected memory sub - bank and the GBL control timing path for the GBL keeper circuit.

[0035] In this regard, FIG. 6 is a circuit diagram of another exemplary memory system 600 including a memory bank 602 having a plurality of memory sub - banks 603(1), 603(2). Common elements between the memory system 400 of FIG. 4 and the memory system 600 of FIG. 6 are denoted by common element numbers and are not described again. As will be discussed in more detail below, the GBL clock signal 411 within the GBL control timing path 3, the local WL clock signals 416, 616 within the RWL timing paths 1.a, 1.b within each of the memory sub - banks 603(1), 603(2), and the sub - bank control clock signal 666 within the sub - bank control timing path 2 are all locally supplied from the source clock 206 within the memory bank 602 to minimize the path length branch between such timing paths.

[0036] In this regard, as shown in FIG. 6, the memory system 400 includes a memory bank 602 that includes a memory array 605 including two memory sub-banks 603(1) and 603(2). The memory sub-bank 603(1) is the memory bank 402 in the memory system 400 of FIG. 4. The second memory sub-bank 603(2) is essentially the same as the first memory sub-bank 603(1). The second memory sub-bank 603(2) includes a plurality of memory row circuits 604, each including a plurality of memory bit cells 607(0) to 607(X) in one row. For example, the memory bit cells 607(0) to 607(X) can be SRAM bit cells or DRAM bit cells. In this example, the memory bit cells 607(0) to 607(X) are DRAM bit cells clocked by a local WL clock signal 616 within a local RWL timing path 1.b local to the sub-memory bank 603(2). The memory bit cells 607(0) to 607(X) within the memory row circuit 404 in the memory sub-bank 603(1) are clocked by a local WL clock signal 416 within a local RWL timing path 1.a local to the sub-memory bank 603(1). As described above for the memory system 400 of FIG. 4, the memory system 600 of FIG. 6 includes another global decoding circuit 634 for the memory sub-bank 603(2) configured to decode the memory address 436 received for memory access operation into a global decoded memory address for generating a global RWL sig on the global RWL(Grwl<31:0>) for the selected memory sub-banks 603(1) and 603(2). The memory bank sub-bank 603(2) includes respective local decoder circuits 606 configured to receive the global RWL signal 408 and generate a local WL signal 610 on a local WL613 corresponding to a specific memory row circuit 604 within the memory sub-bank 603(2) for memory access. When selected in a memory read operation, the memory row circuits 604 are configured to assert the data bits stored in the respective memory bit cells 607(0) to 607(X) to the respective GBL426(0) to 426(X) as output read data 420.The timing at which the data bits of the respective memory bit cells 607(0) to 607(X) are asserted to the respective GBLs 426(0) to 426(X) as the output read data 420 is controlled by the local WL clock signal 616.

[0037] Continuing to refer to FIG. 6, in this example, in addition to the first local WL clock signal 416, the clock control generation circuit 640 is also configured to generate a second local WL clock signal 616 supplied from the source clock 206 at the branch point 444 on the local clock node 442. In this example of the memory system 600 of FIG. 6, it is desirable to control the clock control generation circuit 640 to distribute the source clock 206 to the local clock node 422 only when one of the memory sub-banks 603(1), 603(2) is selected. This is to prevent the clock control generation circuit 640 in the memory bank 602 from clocking the circuits in the local RWL timing path 1.a or the local RWL timing path 1.b in the respective memory sub-banks 603(1), 603(2) when they are not selected. It is also desirable that when one of the memory sub-banks 603(1), 603(2) is not selected, the clock control generation circuit 440 in the memory bank 602 does not clock the circuits in the GBL control timing path 3, so that the GBL keeper circuit 412 can be clocked based on other memory banks accessed in the memory system 600 without contention.

[0038] In this regard, as shown in FIG. 6, the clock control generation circuit 640 also includes an OR-based logic circuit 648 coupled to the global RWL 409. The OR-based logic circuit 648 is similar to the OR-based logic circuit 448. The clock control generation circuit 640 is configured to perform an OR-based logic operation on the global RWL signal 408 on the global RWL 409 for the second memory sub-bank 603(2). In this example, to implement the OR-based logic circuit 648, a plurality of pull-down circuits 650 (e.g., N-type field effect transistors (NFETs)) are used. Although only one pull-down circuit 650 is shown in FIG. 6, it should be noted that each of the global RWL 409 is coupled to the respective gate of each of the pull-down circuits 650. In this way, when the global read WL signal 408 selects and activates the memory sub-bank 603(2), each of its respective coupled pull-down circuits 650 becomes active. Since the global RWL 409 is a one-active hot WL, when each memory sub-bank 603(2) is accessed, only one of the pull-down circuits 450 becomes active. Each of the pull-down circuits 650 is coupled to a clock control output 652 coupled to a clock controller 454 (e.g., a NAND gate), and by controlling the clock controller 454, controls the output of the source clock 206 by the global bank clock circuit 414 to the local clock node 442. When any of the pull-down circuits 650 pulls down the clock control output 652, the clock controller 454 distributes the source clock 206 to the local clock node 442. When none of the pull-down circuits 650 pulls down the clock control output 452, the clock controller 454 does not distribute the source clock 206 to the local clock node 442.In this manner, for the clock control generation circuit 440 to distribute the source clock 206 to the local clock node 442 to generate the respective local WL clock signals 416, 616 and the GBL clock signal 411, the global RWL signal 408 must be active indicating that one or the memory sub-banks 603(1), 603(2) are selected.

[0039] Note that the clock control output 452 does not need to be precharged. Alternatively, instead of the OR-based logic circuits 448, 648 including the pull-down circuits 450, 650, it should also be noted that the OR-based logic circuits 448, 648 can include a pull-up circuit configured to charge the clock control output 452 in response to the combined global RWL signal 408 being activated. In this alternative form, the clock control output 452 does not need to be discharged beforehand.

[0040] Continuing to refer to FIG. 6, the memory system 600 also includes a memory sub-bank control circuit 660 configured to multiplex assert data bits from selected memory row circuits 404, 604 asserted on GBLs 426(0) to 426(X). This is because in a memory read operation, only one of the memory sub-banks 603(1), 603(2) is selected to effectively assert the output read data 420 on GBLs 426(0) to 426(X), so as to prevent signal level contention from occurring on GBLs 426(0) to 426(X) in response to a read operation to memory bank 602. In this regard, the memory sub-bank control circuit 660 includes a plurality of multiplexing circuits 662(0) to 662(X) that control which memory bit cells 405(0) to 405(X), 607(0) to 607(X) of each of the memory sub-banks 603(1) to 603(2) in each of the selected memory row circuits 404, 604 are coupled to GBLs 426(0) to 426(X) based on their respective local WL signals 410, 610. The multiplexing circuits 662(0) to 662(X) also need to be controlled by a clock signal supplied from the source clock 206. In this regard, the multiplexing circuits 662(0) to 662(X) are also coupled to a local bank clock circuit 664 that is coupled to the local clock node 442 at the branch point 444. The local bank clock circuit 664 provides a sub-bank control clock signal 666 for clocking the circuits within the memory sub-bank control circuit 660 in the sub-bank control timing path 2 supplied from the source clock 206 on the local clock node 442. In this way, in this example, the branch of the sub-bank control timing path 2 also occurs locally within the selected memory bank 602 at the local clock node 442 and starts at the same local clock node 442 as the local RWL timing paths 1.a and 1.b and the GBL control timing path 3 for improved timing path tracking.

[0041] FIG. 7 is a block diagram of an exemplary processor-based system 700 that includes a processor 702 configured to execute computer instructions for execution. The processor-based system also includes a memory system 704 configured to locally generate within the memory bank a GBL clock signal and a local WL clock signal that control the timing of the respective GBL control path and the WL path within the selected memory row circuitry within the memory bank. Both the GBL clock signal and the WL clock signal are locally supplied from a source clock 706 within the memory bank of the memory system 704. The memory system 704 of FIG. 7 may include, by way of non-limiting example, the memory systems 400, 600 of FIGS. 4 and 6.

[0042] Continuing to refer to FIG. 7, the processor-based system 700 may be one or more circuits included in an electronic substrate card, such as, for example, a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or other device, and may represent, for example, a server or a user's computer. The processor 702 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, etc. The processor 702 is configured to execute the processing logic in the computer instructions for performing the operations and steps discussed herein. The processor 702 also includes an instruction cache 708 for temporary high-speed access memory storage of instructions. Instructions fetched or prefetched from memory, such as system memory 710 via a system bus 712, are stored in the instruction cache 708.

[0043] Processor 702 and system memory 710 are coupled to system bus 712 and can interconnect peripheral devices included in processor-based system 700. As is well known, processor 702 communicates with these other devices by exchanging address, control, and data information via system bus 712. For example, processor 702 can communicate a burst transaction request to memory controller 714 within system memory 710 as an example of a slave device. Although not shown in FIG. 7, a plurality of system buses 712 may be provided, in which case each system bus constitutes a different fabric. In this example, memory controller 714 is configured to provide memory access requests to memory array 716 within system memory 710. Memory array 716 is composed of an array of memory bit cells for storing data. System memory 710 can be, by way of non-limiting example, read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0044] Other devices may be connected to the system bus 712. As shown in FIG. 7, these devices may include, by way of example, a system memory 710, one or more input devices 718, one or more output devices 720, a modem 722, and one or more display controllers 724. The input device 718 can include any type of input device including, but not limited to, input keys, switches, voice processors, etc. The output device 720 can include any type of output device including, but not limited to, voice, video, other visual indicators, etc. The modem 722 can be any device configured to enable data exchange with a network 726. The network 726 can be any type of network including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH (trademark) network, and the Internet. The modem 722 can be configured to support any desired type of communication protocol. The processor 702 can also be configured to access the display controller 724 via a system bus 721 and control the information transmitted to one or more displays 728. The display 728 can include any type of display including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0045] When executed by a processor such as processor 702 in the processor-based system 700 of FIG. 7, a set of instructions 730 may be included that locally generate, within the memory bank, a GBL clock signal and a local WL clock signal that control the timing between each GBL control path and the WL path within the selected memory row circuitry in the memory bank. The instructions 730 may be stored in the system memory 710, the processor 702, and / or the instruction cache 708 as an example of a non-transitory computer-readable medium 732. The instructions 730 may also exist, in whole or at least in part, within the system memory 710 and / or within the processor 702 during their execution. The instructions 730 may further be transmitted or received via the network 726 via the modem 722 such that the network 726 includes the non-transitory computer-readable medium 732, or as another example, the input device 718.

[0046] The non-transitory computer-readable medium 732 is shown as a single medium in the exemplary embodiment, but the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by a processing device and that causes a processing device to execute any one or more of the methodologies of the embodiments disclosed herein. Thus, the term "computer-readable medium" should be taken to include, without limitation, solid-state memory, optical media, and magnetic media.

[0047] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied as machine-executable instructions, which may be used to cause a general-purpose processor or a special-purpose processor programmed with the instructions to execute the steps. Alternatively, the steps may be executed in combination with hardware and software.

[0048] The embodiments disclosed herein may include a computer program product that can include a machine-readable medium (or computer-readable medium) storing instructions that can be used to program a computer system (or other electronic device) to execute a process according to the embodiments disclosed herein, or can be provided as software. The machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, the machine-readable medium includes machine-readable storage media (e.g., ROM, random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

[0049] Unless stated otherwise specifically, and as will be apparent from the foregoing discussion, throughout this specification, discussions using terms such as "processing," "computing," "determining," "displaying," etc. refer to actions and processes of a computer system, or similar electronic computing device, that manipulate and transform data represented as physical (electronic) quantities within the registers of the computer system and memory into other data similarly represented as physical quantities within the memory, registers, or other such information storage devices, transmission devices, or display devices of the computer system.

[0050] The algorithms and displays presented in this specification are not inherently related to any particular computer or other device. Various systems may be used with programs in accordance with the teachings of this specification, or it may prove convenient to construct more specialized devices to perform the required method steps. The structures required for these various systems will be apparent from the above description. In addition, the embodiments described in this specification are not described with reference to any particular programming language. It should be appreciated that various programming languages may be used to implement the teachings of the embodiments as described herein.

[0051] One of ordinary skill in the art will further understand that the various illustrative logical blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, instructions stored in memory or another computer-readable medium, instructions executed by a processor or other processing device, or a combination of both. The components of the distributed antenna system described herein may be embodied, by way of example, in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. For clarity of explanation of this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described generally above from a functional standpoint. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Skilled artisans will be able to implement the described functionality in various ways for each particular application, but such implementation decisions should not be construed as causing a departure from the scope of the present embodiments.

[0052] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or executed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, a controller may be a processor. The processor may be a microprocessor, but in the alternative, may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0053] The embodiments disclosed herein may be embodied as hardware and instructions stored on hardware, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An illustrative memory medium is coupled to the processor such that the processor can read information from, and write information to, the memory medium. In the alternative, the memory medium may be integral to the processor. The processor and the memory medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the memory medium may reside as discrete components in a remote station, base station, or server.

[0054] Note that the operation steps described in any of the exemplary embodiments in this specification are explained for the purpose of providing examples and discussions. The operations described can be performed in many different orders other than the order shown. Furthermore, the operations described as a single operation step may actually be executed in a plurality of different steps. In addition, one or more operation steps discussed in the exemplary embodiments may be combined. Also, those skilled in the art will understand that information and signals can be represented using any of a variety of technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that can be referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields, or particles, optical fields or particles, or any combination thereof.

[0055] Unless explicitly stated otherwise, it is never intended that any method described in this specification be construed as requiring that its steps be performed in a particular order. Thus, when a method claim does not actually recite the order in which the steps are to be followed, or when the steps are not specifically recited in the claim or the specification as being limited to a particular order, it is never intended that a particular order be inferred.

[0056] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit and scope of the invention. Since modifications, combinations, sub - combinations, and variations of the disclosed embodiments incorporating the spirit and substance of the invention can be conceived by those skilled in the art, the invention should be construed to include all within the scope of the appended claims and their equivalents.

Claims

1. A first memory array, Multiple first memory row circuits, Each of the plurality of first memory row circuits is configured to generate first output read data coupled to a plurality of global bit lines (GBLs) in response to a first global RWL signal on a plurality of global read word lines (RWLs) indicating the selection of a first memory row circuit from among the plurality of first memory row circuits for a first read operation, and in response to a first local WL clock signal, A first memory array including, A GBL keeper circuit coupled to the plurality of GBLs, The GBL keeper circuit is configured to latch the first output readout data onto the plurality of GBLs in response to the GBL clock signal, Clock control generation circuit including local clock node and A memory system including the clock control generation circuit, Receiving the source clock, Receiving the first global RWL signal indicating the first read operation to the first memory array via the plurality of global RWLs, In response to receiving the first global RWL signal, On the local clock node, the first local WL clock signal is generated from the received source clock, On the local clock node, the GBL clock signal is generated from the received source clock. A memory system configured to perform the following actions.

2. The memory system according to claim 1, further comprising a global decode circuit, the global decode circuit is Receiving a memory address for a read operation, The received memory address is decoded into a globally decoded memory address, The first global RWL signal is generated based on the globally decoded memory address, A memory system configured to perform the following actions.

3. A memory system according to claim 1, wherein each of the plurality of first memory row circuits comprises a plurality of first memory bit cells.

4. The memory system according to claim 1, The first memory array is, The global RWL signal is decoded to the local decode memory address. Based on the local decode memory address, activate the first memory row circuit among the plurality of first memory row circuits. In response to the first local WL clock signal, first output readout data is generated to be coupled to the plurality of GBLs. A memory system equipped with a local row decoding circuit configured as follows.

5. The memory system according to Claim 1, The GBL keeper circuit further comprises a GBL clock input connected to a local clock node, The GBL keeper circuit is configured to receive a GBL clock signal on the GBL clock input in the memory system.

6. The memory system according to claim 1, The clock control generation circuit further comprises a first OR-based logic circuit connected to the plurality of global RWLs, The aforementioned clock control generation circuit is A first OR-based logic operation is performed on the first global RWL signal on the plurality of global RWLs. Based on the OR-based logic operation, a GBL lock signal is generated from the source clock received on the local clock node. A memory system configured in such a way.

7. The memory system according to claim 6, The OR-based logic circuit comprises multiple pull-down circuits and a clock controller, each pull-down circuit being connected to each of the multiple global RWLs, and each pull-down circuit being connected to the clock control output. Each of the aforementioned pull-down circuits is configured to discharge the clock control output when the connected global RWL is activated. The memory system is configured such that the clock controller generates a GBL clock signal on a local clock node in response to the discharge of the clock control output.

8. The memory system according to claim 7, The memory system is configured not to pre-charge the clock control output.

9. The memory system according to claim 6, The OR-based logic circuit comprises multiple pull-up circuits and a clock controller. Each pull-up circuit is connected to each of the multiple global RWLs, and each pull-up circuit is connected to the clock control output. Each of the aforementioned pull-up circuits is configured to charge the clock control output when the connected global RWL is activated. The clock controller is configured to generate a GBL clock signal on a local clock node in response to charging of the clock control output, in a memory system.

10. The memory system according to claim 9, The memory system is configured so as not to discharge the clock control output in advance.

11. A memory system according to claim 1, The first memory bank comprises a first memory subbank including a first memory array and a second memory subbank including a second memory array including a plurality of second memory row circuits, Each of the plurality of second memory row circuits is configured to generate second output read data coupled to a plurality of GBLs in response to a second global RWL signal on a plurality of global RWLs indicating that one of the plurality of second memory row circuits has been selected for a second read operation, and in response to a second local WL clock signal. The GBL keeper circuit is further configured to latch second output readout data on multiple GBLs in response to a GBL clock signal. The aforementioned clock control generation circuit is Receiving a second global RWL signal on multiple global RWLs indicating a second read operation to the second memory array, When a second global RWL signal is received, a second local WL clock signal is generated from the source clock received on the local clock node. A GBL clock signal is generated from the source clock received on the local clock node. A memory system configured in such a way.

12. The memory system according to claim 11, The clock control generation circuit further comprises a second OR-based logic circuit connected to the plurality of global RWLs, The aforementioned clock control generation circuit is A second OR-based logic operation is performed on the second global RWL signal on the plurality of global RWLs to generate a GBL clock signal. Based on the second OR-based logic operation described above, a GBL clock signal is generated from the source clock received on the local clock node. A memory system configured in such a way.

13. The memory system according to claim 12, Each of the plurality of first memory row circuits comprises a plurality of first memory bit cells. Each of the plurality of second memory row circuits comprises a plurality of second memory bit cells, The memory bank includes a memory subbank control circuit, The aforementioned memory subbank control circuit is Multiple first multiplexing circuits connected to one of the multiple first memory bit cells in each of the multiple first memory row circuits, and one of the multiple GBLs, Multiple second multiplexing circuits connected to one of the multiple second memory bit cells in each of the multiple second memory row circuits, and one of the multiple GBLs, Equipped with, The aforementioned memory subbank control circuit is In response to a first global RWL signal indicating the selection of a first memory row circuit on multiple global RWLs, and a memory subbank control clock signal, the first output read data is connected to multiple GBLs. In response to a second global RWL signal indicating the selection of a second memory row circuit on multiple global RWLs, and a memory subbank control clock signal, the second output read data is connected to multiple GBLs. A memory system configured in such a way.

14. The memory system according to claim 13, The aforementioned clock control signal generation circuit is When the first global RWL signal is received, a memory subbank control clock signal is generated from the source clock received on the local clock node. When the second global RWL signal is received, a memory subbank control clock signal is generated from the source clock received on the local clock node. A memory system configured in such a way.

15. A method for generating a global bit line (GBL) clock signal for clocking a GBL keeper circuit in a memory system, Steps in which the source clock is reached, The steps include receiving a first global read word line (RWL) signal indicating a first read operation to a selected group of first memory row circuits on a group of global RWLs, In response to the reception of the first global RWL signal, The steps include generating a first local WL clock signal on a local clock node from the received source clock, The steps include generating a GBL clock signal on a local clock node from the received source clock, The steps include generating first output read data connected to a plurality of GBLs from the selected first memory row circuit in response to a first global RWL signal and a first local WL clock signal on a plurality of global RWLs indicating the selection of a selected first memory row circuit, The steps include latching first output read data on multiple GBLs in response to a GBL clock signal, A method that includes this.

16. The method according to claim 15, The steps include receiving a memory address for a read operation, The steps include: decoding the received memory address into a globally decoded memory address, A step of generating a first global RWL signal based on a globally decoded memory address, Methods that further include the above.

17. The method according to claim 15, The steps include performing an OR-based logical operation on a first global RWL signal on multiple global RWLs, The steps include generating a GBL clock signal from a source clock received on a local clock node based on OR-based logical operations, Methods that further include the above.

18. The method according to claim 17, The step of performing an OR-based logical operation on the first global RWL signal is: The steps include: discharging the clock control output in response to the activation of one of several global RWLs; The steps include generating a GBL clock signal from the received source clock in response to the discharge of the clock control output, Methods that further include the above.

19. The method according to claim 18, A method further comprising the step of not pre-charging the local clock node.

20. The method according to claim 17, The step of performing an OR-based logical operation on the first global RWL signal is: A step of charging the clock control output in response to a global RWL among a plurality of activated global RWLs, The steps include generating a GBL clock signal from the received source clock in response to the charging of the clock control output, Methods that include...

21. The method according to claim 20, A method further comprising the step of pre-discharging the local clock node.

22. The method according to claim 15, The steps include receiving a second global RWL signal on multiple global RWLs that indicates a second read operation to a selected second memory row circuit, The steps include generating a second local WL clock signal from a source clock received on a local clock node in response to the reception of a second global RWL signal, The steps include generating a GBL clock signal from a source clock received on a local clock node, The steps include generating second output read data from a selected second memory row circuit in response to a second global RWL signal and a second local WL clock signal indicating the selection of a second memory row circuit on multiple global RWLs, The steps include latching the second output readout data into multiple GBLs in response to the GBL clock signal, Methods that further include the above.

23. The method according to claim 22, The steps include performing a second OR-based logical operation on a second global RWL signal on multiple global RWLs, The steps include generating a GBL clock signal from a source clock received on a local clock node based on a second OR-based logic operation, Methods that further include the above.

24. The method according to claim 23, The steps include: combining first output read data into multiple GBLs in response to a first global RWL signal on multiple global RWLs indicating the selection of a first memory row circuit and a memory subbank control clock signal; The steps include: coupling the second output read data to multiple GBLs in response to a second global RWL signal on multiple global RWLs indicating the selection of a second memory row circuit and a memory subbank control clock signal; Methods that further include the above.

25. The method according to claim 24, In response to receiving the first global RWL signal, the steps include generating a memory subbank control clock signal from the source clock received on the local clock node, In response to receiving a second global RWL signal, the process involves generating a memory subbank control clock signal from the source clock received on the local clock node, Methods that further include the above.

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