Control of Ion Energy Distribution with Respect to Substrate Edge by Non-Sinusoidal Voltage Source

Abstract

The bias voltage supply system includes a main bias electrode disposed below the substrate support surface. The main bias electrode controls the voltage on the upper surface of the substrate existing on the substrate support surface. This bias voltage supply system includes an edge ring electrode disposed within an edge ring that circumscribes the substrate support surface. The edge ring electrode controls the voltage on the upper surface of the edge ring. This bias voltage supply system includes a voltage supply system that generates a prescribed voltage waveform as a function of time at a bias voltage supply node. A first branch circuit electrically connects the bias voltage supply node and the main bias electrode. A second branch circuit electrically connects the bias voltage supply node and the edge ring electrode. The second branch circuit includes a series capacitor and a shunt capacitor.

Description

Background Art

[0001] Plasma processing systems are used to fabricate semiconductor devices, such as chips / dies on semiconductor wafers. In a plasma processing system, a semiconductor wafer is exposed to various types of plasma to cause a defined change in the state of the semiconductor wafer, such as by material deposition and / or material removal and / or material implantation and / or material modification. During plasma processing of the semiconductor wafer, radio frequency (RF) power is transmitted through a process gas in a chamber to convert the process gas into a plasma to which the semiconductor wafer is exposed. Reactive components of the plasma, such as radicals and ions, interact with the materials on the semiconductor wafer to achieve a defined effect on the semiconductor wafer. In some plasma processing systems, a bias voltage is applied at the level of the semiconductor wafer to attract charged components in the plasma towards the semiconductor wafer.

[0002] Since the semiconductor industry continues to progress towards reducing chip size and improving chip performance, it is necessary to use features with higher density and aspect ratio to define transistors on the chip, which makes the transistors more sensitive to fabrication process variations. The reduction of on-chip feature size may require some fabrication process variations of just a few atoms to improve etching uniformity control. A uniform ion flux at the very edge of the semiconductor wafer, for example, within about 5 millimeters (mm) from the edge, is a stringent requirement for plasma etching and deposition for microelectronics fabrication. Also, achieving a substantially uniform ion flux at the edge of the semiconductor wafer is a meaningful challenge since about 10% of the dies on the substrate are affected by the fabrication process results occurring within a radial distance of about 5 mm from the outer peripheral edge of the semiconductor wafer. Non-uniformities in the fabrication process results near the outer peripheral edge of the semiconductor wafer may occur due to structural, temporal, and / or electrical discontinuities around the periphery of the semiconductor wafer. The various embodiments described herein are made in this context. SUMMARY OF THE INVENTION

[0003] In an exemplary embodiment, a bias voltage supply system is disclosed. The bias voltage supply system includes a primary bias electrode disposed below a substrate support surface. The primary bias electrode is configured to control the voltage on the upper surface of the substrate when present on the substrate support surface. The bias voltage supply system also includes an edge ring electrode disposed within an edge ring circumscribing the substrate support surface. The edge ring electrode is configured to control the voltage on the upper surface of the edge ring. The bias voltage supply system also includes a voltage supply system configured to generate a defined voltage waveform as a function of time at a bias voltage supply node. The bias voltage supply system also includes a first branch circuit electrically connected between the bias voltage supply node and the primary bias electrode. The bias voltage supply system also includes a second branch circuit electrically connected between the bias voltage supply node and the edge ring electrode. The second branch circuit includes a series capacitor and a shunt capacitor.

[0004] In an exemplary embodiment, a bias voltage supply system is disclosed. The bias voltage supply system includes a main bias electrode disposed below a substrate support surface. The main bias electrode is configured to control the voltage on the upper surface of the substrate when present on the substrate support surface. The bias voltage supply system also includes an edge ring electrode disposed within an edge ring circumscribing the substrate support surface. The edge ring electrode is configured to control the voltage on the upper surface of the edge ring. The bias voltage supply system also includes a first voltage supply system configured to generate a first defined voltage waveform as a function of time on the main bias electrode. The first voltage supply system includes a first voltage source and a second voltage source. The first voltage source is configured to generate a first time-constant voltage amplitude. The second voltage source is configured to generate a first time-varying voltage. The first time-constant voltage amplitude and the first time-varying voltage combine to form the first defined voltage waveform. The bias voltage supply system also includes a second voltage supply system configured to generate a second defined voltage waveform as a function of time on the edge ring electrode. The second voltage supply system includes a third voltage source and a fourth voltage source. The third voltage source is configured to generate a second time-constant voltage amplitude. The fourth voltage source is configured to generate a second time-varying voltage. The second time-constant voltage amplitude and the second time-varying voltage combine to form the second defined voltage waveform.

[0005] In an exemplary embodiment, a method for supplying a bias voltage during plasma processing of a substrate is disclosed. The method includes generating a defined voltage waveform as a function of time on a bias voltage supply node. The method also includes transmitting a first version of the defined voltage waveform from the bias voltage supply node to a main bias electrode disposed below a substrate support surface to control a voltage on an upper surface of a substrate present on the substrate support surface. The method also includes transmitting a second version of the defined voltage waveform to an edge ring electrode disposed within an edge ring that circumscribes the substrate support surface to control a voltage on an upper surface of the edge ring.

[0006] Other aspects and advantages of the embodiments disclosed herein will become more apparent from the following detailed description of the invention and the accompanying drawings.

Brief Description of the Drawings

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[0026] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0027] FIG. 1A shows a vertical cross-sectional view through a portion of an exemplary substrate plasma processing system 100 according to some embodiments. System 100 includes a substrate support structure 101 having a substrate support surface 103 configured to support substrate 105 during processing of substrate 105 by plasma 107 generated above substrate support structure 101. In some embodiments, substrate support structure 101 is an electrostatic chuck configured to generate an electrostatic force to hold substrate 105 against substrate support surface 103. In some embodiments, an edge ring 109 surrounds substrate support structure 101, and thus substrate support surface 103 is circumscribed by edge ring 109.

[0028] FIG. 1B shows a plan view of a substrate 105 disposed on a substrate support structure 101, in which an edge ring 109 surrounds the substrate support structure 101, as referred to as view A-A in FIG. 1A, according to some embodiments. In some embodiments, RF power is transmitted from a coil, an electrode, and / or an antenna to a plasma processing region above the substrate support structure 101 to which a process gas (or gas mixture) is supplied. The RF power converts the process gas / mixture into plasma 107 within the plasma processing region. Plasma 107 is generated to cause a change in the substrate 105 in a controlled manner. In various fabrication processes, the change in the substrate 105 can be a change in the material or surface condition on the substrate 105. For example, in various fabrication processes, the change in the substrate 105 can include one or more of etching of material from the substrate 105, deposition of material on the substrate 105, and / or modification of the material present on the substrate 105. It should be understood that the plasma processing system 100 can be any type of plasma processing system in which RF power is transmitted to a process gas / mixture within the plasma processing region to generate plasma 107 on a substrate 105 supported on the substrate support structure 101.

[0029] In some embodiments, the substrate 105 is a semiconductor wafer that has undergone a fabrication procedure. However, it should be understood that in various embodiments, the substrate 105 can be essentially any type of substrate that undergoes a plasma-based fabrication process. For example, in some embodiments, the substrate 105 is formed from silicon, sapphire, GaN, GaAs, or SiC, and / or other substrate materials, and can include glass panels / substrates, metal foils, metal sheets, polymer materials, etc. Also, in various embodiments, the substrate 105 can vary in form, shape, and / or size. For example, in some embodiments, the substrate 105 is a semiconductor wafer having an outer diameter of 200 mm, 300 mm, 450 mm, or another size. Also, in some embodiments, the substrate 105 is a non-circular substrate, such as a rectangular substrate for a flat panel display, among other shapes.

[0030] The main bias electrode 111 is disposed within the substrate support structure 101 below the substrate support surface 103. In some embodiments, the substrate support structure 101 is formed from a dielectric material such as a ceramic material or other types of dielectric materials, and the main bias electrode 111 is formed from a conductive material. The edge ring electrode 113 is disposed within the edge ring 109. In some embodiments, the edge ring 109 is formed from a dielectric material and the edge ring electrode 113 is formed from a conductive material. The main bias electrode 111 is electrically connected to the bias voltage supply system 115 as indicated by the connection 117. The edge ring electrode 113 is also electrically connected to the bias voltage supply system 115 as indicated by the connection 119. The bias voltage supply system 115 is configured to control the voltage on the main bias electrode 111 and the voltage on the edge ring electrode 113. The main bias electrode 111 is configured to control the voltage on the upper surface 105T of the substrate 105 when the substrate 105 is present on the substrate support surface 103. The voltage applied to the main bias electrode 111 may differ from the corresponding voltage on the upper surface 105T of the substrate 105 due to various materials present between the main bias electrode 111 and the upper surface 105T of the substrate 105, such as a combination of the dielectric material of the substrate support structure 101 above the main bias electrode 111 and the material(s) of the substrate 105 itself. In some embodiments, the material(s) present between the main bias electrode 111 and the upper surface 105T of the substrate 105 may be electrically represented as a substantially fixed capacitance. The edge ring electrode 113 is configured to control the voltage on the upper surface 109T of the edge ring 109. The voltage applied to the edge ring electrode 113 may differ from the corresponding voltage on the upper surface 109T of the edge ring 109 due to the material of the edge ring 109 above the edge ring electrode 113. In some embodiments, the material(s) of the edge ring 109 above the edge ring electrode 113 may be electrically represented as a substantially fixed capacitance.

[0031] Figure 2A shows an enlarged vertical cross - sectional view of the edge ring 109 adjacent to the substrate support structure 101 with the substrate 105 on the substrate support surface 103, according to some embodiments. In this example, the upper surface 109T of the edge ring 109 is higher than the upper surface 105T of the substrate 105. The vertical heights 1D, 2D, 3D, 4D, 5D, and 6D above the upper surface 105T of the substrate 105 are indicated by lines 201, 202, 203, 204, 205, and 206, respectively. Successive ones of the vertical heights 1D, 2D, 3D, 4D, 5D, and 6D are separated by a constant distance increment of 1D, where D is any distance. The vertical heights 1D, 2D, 3D, and 4D above the upper surface 109T of the edge ring 109 are indicated by lines 207, 208, 209, and 210, respectively. Successive ones of the vertical heights 1D, 2D, 3D, and 4D above the edge ring 109 are separated by a constant distance increment of 1D.

[0032] The plasma sheath thickness above the substrate 105 is the distance from the upper surface 105T of the substrate 105 to the bulk of the plasma 107. Similarly, the plasma sheath thickness above the edge ring 109 is the distance from the upper surface 109T of the edge ring 109 to the bulk of the plasma 107. Application of a negative voltage to the upper surface 105T of the substrate 105 via the main bias electrode 111 establishes the plasma sheath above the substrate 105. The voltage on the upper surface 105T of the substrate 105 controls the thickness of the plasma sheath above the substrate 105. Application of a negative voltage to the upper surface 109T of the edge ring 109 via the edge ring electrode 113 establishes the plasma sheath above the edge ring 109. The voltage on the upper surface 109T of the edge ring 109 controls the thickness of the plasma sheath above the edge ring 109. The thickness of the plasma sheath above the substrate 105 depends partially on the voltage on the upper surface 105T of the substrate 105. Similarly, the thickness of the plasma sheath above the edge ring 109 depends partially on the voltage on the upper surface 109T of the edge ring 109. In the example of FIG. 2A, a voltage potential of -100V on the upper surface 105T of the substrate 105 moves the plasma sheath boundary away from the upper surface 105T of the substrate 105 by a distance increment of 1D. Similarly, in the example of FIG. 2A, a voltage potential of -100V on the upper surface 109T of the edge ring 109 moves the plasma sheath boundary away from the upper surface 109T of the edge ring 109 by a distance increment of 1D.

[0033] When bombarding ions from the plasma 107 travel through the plasma sheath, the ions acquire kinetic energy directed in a direction perpendicular to the equipotential lines that define the plasma sheath. Also, when the equipotential lines that define the plasma sheath are flat over the entire path of the traveling ions, the ion angular distribution function (IADF) is minimized (close to 0 degrees). Ideally, the plasma sheath boundary is flat across the substrate 105 and the edge ring 109, and thus the IADF is perpendicular (90 degrees) to the upper surface 105T of the substrate 105 all the way to the outer peripheral edge of the substrate 105. For example, in FIG. 2A, when the voltage on the upper surface 105T of the substrate 105 is -600 V and the voltage on the upper surface 109T of the edge ring 109 is -400 V, the plasma sheath boundary on the transition portion between the substrate 105 and the edge ring 109 is flat as shown by lines 206, 212, and 210, and thus the ions in the plasma sheath will not acquire substantially horizontal energy, that is, the ions will travel toward the substrate 105 in a direction substantially perpendicular to the upper surface 105T of the substrate 105.

[0034] Figure 2B shows waveform 220 for the RF bias voltage applied to the upper surface 105T of substrate 105 and waveform 222 for the RF bias voltage applied to the upper surface 109T of edge ring 109, according to some embodiments. Waveform 220 and waveform 222 have the same frequency and are phase synchronized. Waveform 220 has a peak negative voltage of -600V, and waveform 222 has a peak negative voltage of -400V, corresponding to a potential difference (ΔV1) of -200V. Thus, when waveforms 220 and 222 are at their respective peak negative voltages, the plasma sheath boundary is flat across the transition region between substrate 105 and edge ring 109, as indicated by lines 206, 212, and 210 in Figure 2A. However, at other phases of waveforms 220 and 222, the voltages on the upper surface 105T of substrate 105 and the upper surface 109T of edge ring 109 do not provide a flat plasma sheath boundary across the transition region between substrate 105 and edge ring 109. For example, when the voltage on the upper surface 105T of substrate 105 is -300V, the voltage on the upper surface 109T of edge ring 109 is -200V, corresponding to a potential difference (ΔV2) of -100V, which does not provide a flat plasma sheath boundary across the transition region between substrate 105 and edge ring 109, as indicated by lines 203, 211, and 208 in Figure 2A. When the RF bias voltage waveforms 220 and 222 circulate in phase, the plasma sheath boundary bends up and down at the transition region between the upper surface 105T of substrate 105 and the upper surface 109T of edge ring 109. This bending of the plasma sheath boundary causes impinging ions (such as those used for reactive ion etching) to impinge on substrate 105 at an angle that is not perpendicular to the upper surface 105T of substrate 105. The increase in the IADF of the impinging ions at the edge of substrate 105 causes non-uniformity in the process results (such as etching rate, etching profile, etc.) at the edge of substrate 105, which typically requires empirical evaluation, such as by imaging the substrate 105 etching profile results for different applied sinusoidal RF bias voltage waveforms.

[0035] When a sinusoidal RF bias voltage is used to bias the substrate 105, discontinuities in the structure of the substrate 105, the main bias electrode 111, and the edge ring 109 near the edge of the substrate 105 often cause non-uniform process results on the substrate 105. Also, the examples of FIGS. 2A and 2B show that, unless the upper surface 105T of the substrate 105 and the upper surface 109T of the edge ring 109 are at the same altitude (in the same horizontal plane), it is impossible for the sinusoidal waveform to provide an ideal flat plasma sheath boundary across the transition between the substrate 105 and the edge ring 109 over the time period during which impact ions travel through the plasma sheath.

[0036] In some embodiments, an independent RF bias is added under the edge ring 109 to control the uniformity of process results on the substrate 105 near the outer peripheral edge of the substrate 105. However, the RF biasing of the substrate 105 and the edge ring 109 has a relatively wide ion energy distribution (IED), and there is no control over the ion energy level and the full width at half maximum (FWHM) of the IED above the substrate 105 and / or the edge ring 109. Additionally, edge ring 109 erosion due to reactive ion etching is another problem associated with supplying a sinusoidal RF bias voltage to the edge ring electrode 113. Edge ring 109 erosion can add operating costs in manufacturing due to more frequent replacement of the edge ring 109, which can reduce the benefits in manufacturing yield provided by the use of the edge ring 109.

[0037] Narrow IEDs provide advantages in achieving desired plasma process results on substrate 105 compared to wide IEDs in various applications, particularly in reactive ion etching (RIE), atomic layer deposition (ALD), atomic layer etching (ALE), etc. Narrow IEDs can be obtained by a certain negative voltage on the surface 105T of the substrate 105 being processed, such as on a silicon wafer for plasma etching and / or deposition. There are also many substrates 105 and substrate support structures 101 made of dielectric materials. Unless the main bias electrode 111 voltage is controlled, positively charged ions will travel through the plasma sheath to reduce the negative surface charge on the upper surface 105T of the substrate 105 and correspondingly reduce the sheath potential. In some embodiments, assuming a substantially constant ion flux through the plasma sheath, a linear ramp of the main bias electrode 111 voltage is used to maintain a certain negative voltage on the upper surface 105T of the substrate 105. However, in some embodiments, when the ion flux through the plasma varies with time, a non-linear ramp of the main bias electrode 111 voltage is used to maintain a certain negative voltage on the upper surface 105T of the substrate 105.

[0038] In some situations, when the plasma sheath is maintained without collapse even during a relatively short time period (> 1 millisecond) compared to the processing time (>> 1 second), an excessive amplitude of the voltage will be required on the main bias electrode 111. Implementing a high-voltage generator to supply the excessive amplitude of the voltage on the main bias electrode 111 is costly and inefficient. Also, charge accumulation is another problem associated with a relatively long time period during which a negative voltage exists on the upper surface 105T of the substrate 105. The periodically switched polarity of the voltage on the main bias electrode 111 solves these problems regarding the excessive amplitude requirement of the voltage and charge accumulation. To obtain a narrow IED, it is necessary to avoid a collision sheath that occurs when the sheath travel time of the ions (t_ion) is greater than the duration (t_Vneg) of a constant negative voltage on the upper surface 105T of the substrate 105. A high switching frequency leads to such conditions (t_ion > t_Vneg) due to a short t_Vneg. Therefore, a linear ramp of the voltage on the order of microseconds may be required for the main bias electrode 111. In some embodiments, the switching frequency is between 10 kilohertz and 1 megahertz.

[0039] There are two parameters to be controlled in a non-sinusoidal voltage source, namely, Vstep and dV / dt. In some embodiments, the voltage applied to the main bias electrode 111 remains substantially constant over a period of time to discharge the cation-charged substrate 105. The plasma sheath collapses during this period of time. Then, Vstep is applied to the main bias electrode 111 to achieve a target negative voltage on the upper surface 105T of the substrate 105. Then, after the target negative voltage is achieved on the upper surface 105T of the substrate 105 by Vstep, the voltage gradient dV / dt is applied to the main bias electrode 111 until the end of the switching cycle to maintain the target negative voltage on the upper surface 105T of the substrate 105. The voltage Vstep sets the desired ion energy, and the voltage dV / dt sets the full width at half maximum (FWHM) of the IED. The voltage dV / dt = I_ion / C_substrate, where I_ion is the ion current incident on the substrate 105 and C_substrate is the capacitance between the upper surface 105T of the substrate 105 and the main bias electrode 111 to which the controlled bias voltage is applied directly or indirectly. The above process of applying Vstep and dV / dt to achieve and maintain the target negative voltage on the upper surface 105T of the substrate 105 via the main bias electrode 111 can also be used to achieve and maintain the target voltage on the upper surface 109T of the edge ring 109 via the edge ring electrode 113.

[0040] A uniform IED on the substrate surface is important for manufacturing yield. However, the IED is often non-uniform near the edge of the substrate due to discontinuities in the substrate, baseplate electrode, and edge ring structure. According to various embodiments disclosed herein, independent non-sinusoidal voltage control for the edge ring 109 provides control of the IED uniformity with respect to the edge of the substrate 105. An independent voltage source is used to provide independent non-sinusoidal voltage control for the edge ring 109. The independent voltage source is coordinated with the voltage switching on the main bias electrode 111 in a manner that provides a substantially uniform process result across the substrate 105.

[0041] In some embodiments, the edge ring electrode 113 is used to provide independent IED control for the upper surface 109T of the edge ring 109. Insertion of the edge ring electrode 113 below the upper surface 109T of the edge ring 109 can be achieved in various ways. In an exemplary embodiment, the edge ring electrode 113 is electrically separated from the main bias electrode 111. In this embodiment, an independent voltage source is implemented for the edge ring electrode 113. In another exemplary embodiment, the edge ring electrode 113 branches from the main bias electrode 111. In some embodiments, the edge ring electrode 113 is an additional electrode branched from the main bias electrode 111. In some embodiments, the edge ring electrode 113 is formed as an extension of the main bias electrode 111. Embodiments in which the edge ring electrode 113 branches from the main bias electrode 111 do not require an independent voltage source for the edge ring electrode 113. Rather, in embodiments in which the edge ring electrode 113 branches from the main bias electrode 111, the voltage on the edge ring electrode 113 is controlled by edge ring 109 capacitance optimization to substantially match the substrate 105 capacitance. In various embodiments, various techniques such as variable capacitors and temperature-controlled capacitance are used for edge ring 109 capacitance optimization. The various embodiments disclosed herein for applying independent non-sinusoidal voltage and IED control to the edge ring 109 provide an improvement in process uniformity near the edge of the substrate 105. The various embodiments disclosed herein also provide new tools for improving process uniformity with respect to non-sinusoidal voltage sources and IEDs controlled by edge ring 109 capacitance.

[0042] In some embodiments, a separate arbitrary (non-sinusoidal) bias voltage waveform is applied to each of the substrate 105 and the edge ring 109, respectively, to maintain a substantially flat plasma sheath boundary across the transition between the substrate 105 and the edge ring 109. FIG. 3 shows an exemplary arbitrary (non-sinusoidal) bias voltage waveform that can be applied to each of the upper surface 105T of the substrate 105 and the upper surface 109T of the edge ring 109 by the main bias electrode 111 and the edge ring electrode 113, respectively, according to some embodiments. It should be understood that the bias voltage waveform of FIG. 3 is shown by way of example. In other embodiments, an essentially arbitrary (non-sinusoidal) bias voltage waveform can be applied to the upper surface 105T of the substrate 105 and the upper surface 109T of the edge ring 109, as needed, to achieve and maintain a substantially flat plasma sheath boundary across the transition between the substrate 105 and the edge ring 109. FIG. 3 shows a pulsed voltage waveform 301 defined as an ongoing series of pulse cycles, where each pulse cycle corresponds to a waveform period and includes an on-duration during which the pulsed voltage waveform 301 has a negative voltage and an off-duration during which the pulsed voltage waveform 301 has a positive voltage. At the start of a pulse cycle in waveform 301, rapid sheath formation occurs in response to a step change (increase) in the bias voltage amplitude. During the on-duration of the pulse cycle in waveform 301, the negative bias voltage is maintained substantially constant to maintain a consistent plasma sheath boundary thickness. During the off-duration of the pulse cycle in waveform 301, a rapid plasma sheath collapse occurs in response to a step change from a negative bias voltage to a positive voltage on the upper surface 105T of the substrate 105 or the upper surface 109T of the edge ring 109.

[0043] FIG. 3 also shows a pulsed voltage waveform 303 defined as a series of ongoing pulse cycles, where each pulse cycle corresponds to a waveform period and includes an on-duration during which the pulsed voltage waveform 303 has a negative voltage and an off-duration during which the pulsed voltage waveform 303 has a positive voltage. At the start of a pulse cycle in waveform 303, a high-speed sheath formation occurs in response to a step change (increase) in the bias voltage amplitude. Over the on-duration of the pulse cycle in waveform 303, the bias voltage amplitude is linearly decreased as a function of time to achieve a decreasing plasma sheath boundary thickness as a function of time. Over the off-duration of the pulse cycle in waveform 303, a high-speed plasma sheath collapse occurs in response to a step change from a negative bias voltage to a positive voltage on the upper surface 105T of the substrate 105 or the upper surface 109T of the edge ring 109.

[0044] FIG. 3 also shows a pulsed voltage waveform 305 defined as a series of ongoing pulse cycles, where each pulse cycle corresponds to a waveform period and includes an on-duration during which the pulsed voltage waveform 305 has a negative voltage and an off-duration during which the pulsed voltage waveform 305 has a positive voltage. At the start of a pulse cycle in waveform 305, a high-speed sheath formation occurs in response to a step change (increase) in the bias voltage amplitude. Over the on-duration of the pulse cycle in waveform 305, the bias voltage amplitude is linearly increased as a function of time to achieve an increasing plasma sheath boundary thickness as a function of time. Over the off-duration of the pulse cycle in waveform 305, a high-speed plasma sheath collapse occurs in response to a step change from a negative bias voltage to a positive voltage on the upper surface 105T of the substrate 105 or the upper surface 109T of the edge ring 109.

[0045] In FIG. 3, the waveform period (pulse cycle) represents the total time to establish and remove the plasma sheath. In some embodiments, the negative voltage amplitude during the on-duration of the pulse cycle is set to induce an ion impact for reactive ion etching. The duty cycles of waveforms 301, 303, 305 are controlled by adjusting the ratio of the waveform period (pulse cycle) corresponding to the on-duration. Exemplary waveforms 301, 303, and 305 can be applied to both the main bias electrode 111 and the edge ring electrode 113.

[0046] Figure 4 shows the application of a pulsed voltage waveform 301 to both the main bias electrode 111 and the edge ring electrode 113 to create a flat plasma sheath boundary in the example of FIG. 2A. Specifically, the pulsed voltage waveform 401 represents the voltage on the upper surface 105T of the substrate 105 corresponding to the application of the pulsed voltage waveform 301 to the main bias electrode 111. The pulsed voltage waveform 403 represents the voltage on the upper surface 109T of the edge ring 109 corresponding to the application of the pulsed voltage waveform 301 to the edge ring electrode 113. The waveform 401 has a pulse cycle 401A that includes an on-duration 401B and an off-duration 401C. The waveform 403 has a pulse cycle 403A that includes an on-duration 403B and an off-duration 403C. The pulsed voltage waveform 401 and the pulsed voltage waveform 403 are synchronized with respect to phase and duty cycle. The on-duration 401B of the pulse cycle 401A applies a bias voltage of -600 V to the upper surface 105T of the substrate 105 via the main bias electrode 111. At the same time, the on-duration 403B of the pulse cycle 403A applies a bias voltage of -400 V to the upper surface 109T of the edge ring 109 via the edge ring electrode 113. Thus, in the example of FIG. 2A, the plasma sheath boundary is flat across the transition region between the substrate 105 and the edge ring 109, as indicated by lines 206, 212, and 210, respectively, over the on-duration 401B of the pulse cycle 401A and the on-duration 403B of the pulse cycle 403A of the pulsed voltage waveforms 401 and 403, respectively. Also, the plasma sheath collapses during the off-duration 401C of the pulse cycle 401A and the off-duration 403C of the pulse cycle 403A of the pulsed voltage waveforms 401 and 403, respectively. In the example of FIG. 2A, the pulsed voltage waveforms 401 and 403 create a flat plasma sheath boundary during a negative bias voltage period that is much longer than the ion transit time through the plasma sheath.Also, the substrate 105 bias voltage and the edge ring 109 bias voltage are matched with equal phase and duty cycle such that the shape of the plasma sheath boundary is constant during the negative bias voltage period and such that the impact IADF can be minimized (close to 0 degrees).

[0047] FIG. 5 shows the application of the pulse voltage waveform 401 of FIG. 4 to the main bias electrode 111, along with the application of a pulse voltage waveform 501 of a shorter duty cycle to the edge ring electrode 113, according to some embodiments. The pulse voltage waveform 501 has a pulse cycle 501A that includes an on-duration 501B and an off-duration 501C. The pulse voltage waveform 503 has a shorter duty cycle compared to the pulse voltage waveform 401 because the ratio of the pulse cycle 501A corresponding to the on-duration 501B is smaller than the ratio of the pulse cycle 401A corresponding to the on-duration 401B. Due to the amplitude of the voltage on the upper surface 109T of the edge ring 109 set to flatten the plasma sheath boundary above the edge of the substrate 105, the traveling angle of the impact ions is about 0 degrees with respect to the normal vector extending from the upper surface 105T of the substrate 105 during the on-duration 501B of the pulse cycle 501A of the pulse voltage waveform 501 applied to the upper surface 109T of the edge ring 109. The on-durations 401B and 501B can be set to be longer and shorter, respectively, than the ion traveling time through the plasma sheath. Under such conditions, during the off-duration 501C of the pulse cycle 501A of the pulse voltage waveform 501, most of the impact ions will be in the center of the plasma sheath, where the ions are mainly affected by the voltage on the upper surface 105T of the substrate 105 because the voltage gradient becomes smaller as it approaches the upper surface 105T of the substrate 105. Thus, the ions that were initially moving perpendicular above the upper surface 109T of the edge ring 109 will lose their energy during the off-duration 501C of the pulse cycle 501A of the pulse voltage waveform 501 and acquire a relatively small kinetic energy towards the substrate 105. Correspondingly, the shorter duty cycle of the pulse voltage waveform 501 applied to the upper surface 109T of the edge ring 109 will serve to reduce the erosion of the edge ring 109 during the reactive ion etching process.

[0048] FIG. 6 shows a pulse voltage waveform 401 applied to the upper surface 105T of the substrate 105 and a pulse voltage waveform 403 applied to the upper surface 109T of the edge ring 109, with the pulse voltage waveform 403 phase-shifted with respect to the pulse voltage waveform 401. Specifically, the pulse voltage waveform 403 is phase-shifted by a phase shift amount 601, and thus the pulse cycle 403A of the pulse voltage waveform 403 starts before the pulse cycle 401A of the pulse voltage waveform 401. In some embodiments, the phase shift amount 601 is set such that the etching rate of the edge of the substrate 105 is reduced by attracting impact ions towards the edge ring 109 first during the phase shift amount 601, before the start of the on-duration 401B (negative voltage) of the pulse cycle 401A of the pulse voltage waveform 401 on the upper surface 105T of the substrate 105. In this way, the phase shift amount 601 serves to reduce the number of impact ions incident on the edge of the substrate 105 by moving the ions initially above the edge of the substrate 105 towards the edge ring 109. Also, in some embodiments, the phase shift amount 601 causes the ions to travel towards the edge ring 109 when the phase cycle 403A of the pulse voltage waveform 403 starts first, and then change direction perpendicular to the substrate 105 when the phase cycle 401A of the pulse voltage waveform 401 starts. In some embodiments, the phase-shifted pulse voltage waveform 403 of FIG. 6 reduces the etching rate at the outer peripheral edge of the substrate 105 when the ion density near the edge of the substrate 105 is higher due to structural, temporal, and / or electrical discontinuities around the periphery of the substrate 105. Also, in some embodiments, it should be understood that the pulse voltage waveform 403 is phase-shifted in the opposite direction, and thus the pulse cycle 403A of the pulse voltage waveform 403 starts after a certain phase shift amount after the pulse cycle 401A of the pulse voltage waveform 401 starts.

[0049] FIG. 7 shows the application of the pulse voltage waveform 305 of FIG. 3 to the main bias electrode 111 and the application of the pulse voltage waveform 303 of FIG. 3 to the edge ring electrode 113, according to some embodiments. Specifically, the pulse voltage waveform 701 represents the voltage on the upper surface 105T of the substrate 105 corresponding to the application of the pulse voltage waveform 305 to the main bias electrode 111. The pulse voltage waveform 703 represents the voltage on the upper surface 109T of the edge ring 109 corresponding to the application of the pulse voltage waveform 303 to the edge ring electrode 113. The waveform 701 has a pulse cycle 701A that includes an on-duration 701B and an off-duration 701C. The waveform 703 has a pulse cycle 703A that includes an on-duration 703B and an off-duration 703C. The pulse voltage waveform 701 and the pulse voltage waveform 703 are synchronized with respect to phase and duty cycle. The on-duration 701B of the pulse cycle 701A applies a bias voltage that linearly increases in amplitude as a function of time from an initial step voltage amplitude to a voltage of -600V to the upper surface 105T of the substrate 105. At the same time, the on-duration 703B of the pulse cycle 703A applies a bias voltage that linearly decreases in amplitude as a function of time from an initial step voltage of -400V to the upper surface 109T of the edge ring 109.

[0050] In some embodiments, the voltage gradients of the pulse voltage waveform 701 during the on-duration 701B and the pulse voltage waveform 703 during the on-duration 703B are collectively adjusted to improve the plasma process results by manipulating ion movement near the edge of the substrate 105. The specific example of FIG. 7 acts to reduce the etching rate at the edge of the substrate 105 without changing the duty cycle or phase alignment between the pulse voltage waveform 701 on the upper surface 105T of the substrate 105 and the pulse voltage waveform 703 on the upper surface 109T of the edge ring 109. In some embodiments, the bends at the plasma sheath boundary between the substrate 105 and the edge ring 109 are reversed during the on-duration 701B of the pulse cycle 701A and the on-duration 703B of the pulse cycle 703A of the pulse voltage waveforms 701 and 703, respectively. However, it should be understood that in various embodiments, the pulse voltage waveforms 701 and 703 can be configured to vary as a function of time in essentially any manner required during the on-durations 701B and 703B of the pulse cycles 701A and 703A, respectively.

[0051] FIG. 8 shows the application of the pulse voltage waveform 801 to the main bias electrode 111 along with the application of the pulse voltage waveform 803 to the edge ring electrode 113, where the pulse voltage waveform 803 includes an inter-level pulsing state, according to some embodiments. The pulse voltage waveform 801 includes a series of consecutive pulse cycles 801A. The pulse voltage waveform 803 includes a series of consecutive pulse cycles 803A. The pulse voltage waveform 801 and the pulse voltage waveform 803 are synchronized with respect to phase. In other words, the same pulse cycle 803A of the pulse voltage waveform 803 occurs over the time course of each pulse cycle 801A of the pulse voltage waveform 801. The pulse voltage waveform 801 represents the voltage on the upper surface 105T of the substrate 105 corresponding to the application of a similar pulse voltage waveform to the main bias electrode 111. The pulse voltage waveform 803 represents the voltage on the upper surface 109T of the edge ring 109 corresponding to the application of a similar pulse voltage waveform to the edge ring electrode 113.

[0052] Waveform 801 has a pulse cycle 801A that includes a first state 801B in which the voltage on the upper surface 105T of the substrate 105 is 0 or positive. The pulse cycle 801A of waveform 801 also has a second state 801C in which the voltage on the upper surface 105T of the substrate 105 is sub-pulsed according to a series of sub-pulse cycles 802A, where each sub-pulse cycle 802A includes an on-duration 802B and an off-duration 802C. The ratio of the sub-pulse cycles 802A having an on-duration 802B defines the duty cycle of the sub-pulse cycles 802A, where this duty cycle can be adjusted as needed to achieve a desired effect on the charged components above the substrate 105.

[0053] Waveform 803 has a pulse cycle 803A that includes a first state 803B and a second state 803C. In the first state 803B, the voltage on the upper surface 109T of the edge ring 109 is sub-pulsed according to a series of sub-pulse cycles 804A, where each sub-pulse cycle 804A includes an on-duration 804B and an off-duration 804C. The ratio of the sub-pulse cycles 804A having an on-duration 804B defines the duty cycle of the sub-pulse cycles 804A. Similarly, in the second state 803C, the voltage on the upper surface 109T of the edge ring 109 is sub-pulsed according to a series of sub-pulse cycles 805A, where each sub-pulse cycle 805A includes an on-duration 805B and an off-duration 805C. The ratio of the sub-pulse cycles 805A having an on-duration 805B defines the duty cycle of the sub-pulse cycles 805A. The duty cycles of the sub-pulse cycles 804A and 805A can be adjusted as needed to achieve a desired effect on the charged components above and near the edge of the substrate 105 and above the edge ring 109.

[0054] In the exemplary embodiment of FIG. 8, the amplitude of the bias voltage applied to the upper surface 109T of the edge ring 109 is lower in the first state 803B than in the second state 803C, which is referred to as inter-level bias voltage pulsing on the edge ring 109. In various embodiments, it should be understood that the inter-level bias voltage pulsing can be applied to the edge ring 109, the substrate 105, or both the edge ring 109 and the substrate 105. Also, in various embodiments, the amplitude of the bias voltage applied in the inter-level bias voltage pulsing can be controlled as needed. Also, in various embodiments, the duty cycle applied in the inter-level bias voltage pulsing can be controlled as needed. Also, in various embodiments, the time lengths of the different states 801B and 801C within the pulse cycle 801A can be defined as needed. Also, the time lengths of the different states 803B and 803C within the pulse cycle 803A can be defined as needed. Further, the example of FIG. 8 shows the pulse cycle 801A as having two states 801B and 801C, and the pulse cycle 803A as having two states 803B and 803C, but in various embodiments, either or both of the pulse cycles 801A and 803A can be defined to include three or more states, where each state is characterized by a specific combination of a bias voltage amplitude, a sub-pulse duty cycle, a sub-pulse time length, and a state time length.

[0055] A particular example of the inter-level bias voltage pulsing shown in FIG. 8 acts to reduce the ion density above the edge of the substrate 105 during the combined application of the first state 801B of the pulse cycle 801A to the upper surface 105T of the substrate 105 and the first state 803B of the pulse cycle 803A to the upper surface 109T of the edge ring 109. Also, the inter-level bias voltage pulsing example of FIG. 8 acts to minimize the IADF above the edge of the substrate 105 during the combined application of the second state 801C of the pulse cycle 801A to the upper surface 105T of the substrate 105 and the second state 803C of the pulse cycle 803A to the upper surface 109T of the edge ring 109. In this way, the inter-level bias voltage pulsing example of FIG. 8 acts to move ions away from the edge of the substrate 105 and towards the edge ring 109, which can act to reduce the plasma density near the edge of the substrate 105, for example, to reduce the etching rate at the edge of the substrate 105, in order to provide etching control at the edge of the substrate 105. In some embodiments, such as that shown in FIG. 8, the inter-level bias voltage pulsing includes both pulse voltage waveform synchronization and pulsing state synchronization on the upper surface 105T of the substrate 105 with respect to the upper surface 109T of the edge ring 109.

[0056] As described with respect to the examples of FIGS. 3-8, various bias voltage waveforms can be applied to the upper surface 105T of the substrate 105 and the upper surface 109T of the edge ring 109 to control the plasma sheath boundary profile near the edge of the substrate 105. Ions travel across the plasma sheath above the substrate 105 according to the plasma sheath potential created by the voltage present on the upper surface 105T of the substrate 105. When the voltage on the substrate 105 oscillates between positive and negative, the plasma sheath potential reflects the voltage oscillation on the substrate 105, and the ions traveling through the plasma sheath are correspondingly affected by the varying plasma sheath potential. At relatively low RF frequencies, the transit time of the impact ions in the plasma sheath (plasma sheath thickness / average ion velocity) can be shorter than the period of a single RF bias voltage waveform. The variation in the plasma sheath potential corresponding to the RF bias voltage frequency instantaneously affects the movement of the ions traveling within the plasma sheath. The various embodiments disclosed herein for applying any (non-sinusoidal) pulsed bias voltage waveform controlled to the upper surface 105T of the substrate 105 and the upper surface 109T of the edge ring 109 enable control of the ions traveling within the plasma sheath at certain locations within the plasma sheath and at certain times within each pulsed bias voltage waveform period to improve the etching uniformity near the edge of the substrate 105. The various embodiments disclosed herein for applying any (non-sinusoidal) pulsed bias voltage waveform controlled to the upper surface 105T of the substrate 105 and the upper surface 109T of the edge ring 109 are significantly more advantageous than various existing techniques that attempt to control the average movement of ions regardless of the time and location of the ions within the plasma sheath. Further, the various embodiments disclosed herein for applying any (non-sinusoidal) pulsed bias voltage waveform controlled to the upper surface 105T of the substrate 105 and the upper surface 109T of the edge ring 109 provide an improvement in the process uniformity results across the substrate 105 while alleviating the related problems by having a powered edge ring 109 in various plasma etching applications.

[0057] FIG. 9A shows an exemplary implementation of the bias voltage supply system 115 of FIG. 1A for implementing various methods described with respect to FIGS. 3-8, in which various bias voltage waveforms are applied to the upper surface 105T of the substrate 105 and the upper surface 109T of the edge ring 109 to control the plasma sheath boundary profile near the outer peripheral edge of the substrate 105. The main bias electrode 111 and the edge ring electrode 113 can be considered components of the bias voltage supply system 115, along with their associated electrical connections 117 and 119, respectively. The bias voltage supply system 115 includes a voltage supply system 901 having an output electrically connected to a bias voltage supply node 905 through a filter 903, as indicated by connections 907 and 909. The voltage supply system 901 is configured to generate a defined voltage waveform 902 as a function of time at the bias voltage supply node 905. In some embodiments, the defined voltage waveform 902 includes a bias voltage step portion (Vstep) 902A and a time-varying bias voltage portion (dV / dt) 902B. In some embodiments, the defined voltage waveform 902 is defined as an ongoing series of pulse cycles, where each pulse cycle includes an on duration and an off duration, such as those previously described with respect to the pulse voltage waveforms of FIGS. 3-8. The voltage supply system 901 is bidirectionally data / signally communicatively connected to a controller 911 that is programmable to direct the operation of the voltage supply system 901 to generate essentially any form of defined voltage waveform 902 as required for a particular plasma processing operation on the substrate 105.

[0058] FIG. 9B shows an exemplary implementation of a voltage supply system 901 according to some embodiments. The voltage supply system 901 includes a first voltage source 901A and a second voltage source 901B, which are electrically connected in series with each other such that their output voltages are combined in total. In some embodiments, each of the first voltage source 901A and the second voltage source 901B is a DC voltage supply. The first voltage source 901A is configured to generate a voltage amplitude that is constant over time according to a defined pulse schedule corresponding to a defined voltage waveform 902. For example, FIG. 9B shows an exemplary pulsed voltage waveform 904 generated and output by the first voltage source 901A, which ultimately becomes the bias voltage step portion (Vstep) 902A of the defined voltage waveform 902. The output of the first voltage source 901A is electrically connected to the input of the second voltage source 901B as shown by the electrical connection 906. The output of the second voltage source 901B is electrically connected to the output of the voltage supply system 901 as shown by the electrical connection 907. The second voltage source 901B is configured to generate a pulsed voltage waveform 908 that varies over time, which ultimately becomes the time-varying bias voltage portion (dV / dt) 902B of the defined voltage waveform 902. In some embodiments, the pulsed voltage waveform 908 that varies over time varies substantially linearly as a function of time during the on-duration of each pulse cycle. Also, in some embodiments, the pulsed voltage waveform 908 that varies over time increases in amplitude in a substantially linear manner as a function of time during the on-duration of each pulse cycle. At the output of the second voltage source 901B, the pulsed voltage waveform 904 is combined with the pulsed voltage waveform 908 that varies over time to generate the defined voltage waveform 902. In this way, the output voltage provided to the bias voltage supply node 905 by the voltage supply system 901 is a combination of the pulsed voltage waveform 904 generated by the first voltage source 901A and the pulsed voltage waveform 908 generated by the second voltage source 901B.Each of the first voltage source 901A and the second voltage source 901B is connected to communicate bidirectionally with the controller 911, and the controller 911 synchronizes the phase and duty cycle of the pulse voltage waveform 904 and the phase and duty cycle of the pulse voltage waveform 908 in order to generate a specified voltage waveform 902, and instructs the operations of the first voltage source 901A and the second voltage source 901B.

[0059] Bias voltage supply system 115 includes a splitting circuit 913 configured to apply the voltage present on bias voltage supply node 905 to each of main bias electrode 111 and edge ring electrode 113 in a controlled manner. Splitting circuit 913 includes a first branch circuit 915 and a second branch circuit 917. The first branch circuit 915 is electrically connected between bias voltage supply node 905 and main bias electrode 111. The first branch circuit 915 includes a series capacitor 919 and a shunt capacitor 921. In some embodiments, each of series capacitor 919 and shunt capacitor 921 is a respective variable capacitor, and the variable capacitor can be remotely controlled via a controller 911 that is in bi-directional data / signal communication with splitting circuit 913. In some embodiments, the first branch circuit 915 includes a switching device 920 implemented to enable bypassing of series capacitor 919, such that bias voltage supply node 905 can be switchably electrically connected directly to the input terminal of series capacitor 919 or to main bias electrode 111 via electrical connection 117. In this way, switching device 920 is controlled to either electrically connect series capacitor 919 in series between bias voltage supply node 905 and main bias electrode 111 or effectively electrically remove series capacitor 919 such that it is not disposed between bias voltage supply node 905 and main bias electrode 111. Also, in some embodiments, the first branch circuit 915 includes a switching device 922 implemented such that shunt capacitor 921 can be electrically connected to or disconnected from electrical connection 117 that extends from the output of the first branch circuit 915 to main bias electrode 111. In this way, switching device 922 is controlled to either electrically connect shunt capacitor 921 between main bias electrode 111 and reference ground potential 927 or effectively electrically remove shunt capacitor 921 from the first branch circuit 915.

[0060] The second branch circuit 917 is electrically connected between the bias voltage supply node 905 and the edge ring electrode 113. The second branch circuit 917 includes a series capacitor 923 and a shunt capacitor 925. In some embodiments, each of the series capacitor 923 and the shunt capacitor 925 is a respective variable capacitor, and the variable capacitor can be remotely controlled via a controller 911 that bi-directionally data / signally communicates with the splitting circuit 913 to set its capacitance. In some embodiments, the second branch circuit 917 includes a switching device 929 implemented to enable bypassing of the series capacitor 923, such that the bias voltage supply node 905 can be switchably electrically connected either to the input terminal of the series capacitor 923 or directly to the edge ring electrode 113 via the electrical connection 119. In this way, the switching device 929 is controlled to either electrically connect the series capacitor 923 in series between the bias voltage supply node 905 and the edge ring electrode 113, or effectively electrically remove the series capacitor 923 such that it is not disposed between the bias voltage supply node 905 and the edge ring electrode 113. Also, in some embodiments, the second branch circuit 917 includes a switching device 931 implemented such that the shunt capacitor 925 can be electrically connected to or disconnected from the electrical connection 119 extending from the output of the second branch circuit 917 to the edge ring electrode 113. In this way, the switching device 931 is controlled to either electrically connect the shunt capacitor 925 between the edge ring electrode 113 and the reference ground potential 927, or effectively electrically remove the shunt capacitor 925 from the second branch circuit 917.

[0061] In some embodiments, the first branch circuit 915 is configured such that the series capacitor 919 and the shunt capacitor 921 are disengaged, and the second branch circuit 917 is configured such that the series capacitor 923 and the shunt capacitor 925 are engaged. More specifically, in these embodiments, the switching devices 920 and 922 are set such that the bias voltage transmitted from the bias voltage supply node 905 to the main bias electrode 111 is controlled by the series capacitor 919 and the shunt capacitor 921, and the switching devices 929 and 931 are set such that the bias voltage transmitted from the bias voltage supply node 905 to the edge ring electrode 113 is controlled by the series capacitor 923 and the shunt capacitor 925. Therefore, in these embodiments, the bias voltage pulse waveform 902 output by the voltage supply system 901 is supplied to the main bias electrode 111, and a modified version of the bias voltage pulse waveform 902 output by the voltage supply system 901 is supplied to the edge ring electrode 113.

[0062] In some embodiments, the first branch circuit 915 is configured such that the series capacitor 919 and the shunt capacitor 921 are engaged, and the second branch circuit 917 is configured such that the series capacitor 923 and the shunt capacitor 925 are engaged. More specifically, in these embodiments, the switching devices 920 and 922 are set such that the bias voltage transmitted from the bias voltage supply node 905 to the main bias electrode 111 is controlled by the series capacitor 919 and the shunt capacitor 921, and the switching devices 929 and 931 are set such that the bias voltage transmitted from the bias voltage supply node 905 to the edge ring electrode 113 is controlled by the series capacitor 923 and the shunt capacitor 925. Therefore, in these embodiments, the first modified version of the bias voltage pulse waveform 902 output by the voltage supply system 901 is supplied to the main bias electrode 111, and the second modified version of the bias voltage pulse waveform 902 output by the voltage supply system 901 is supplied to the edge ring electrode 113.

[0063] Furthermore, in some embodiments, the series capacitor 919 can be engaged in the first branch circuit 915 and the shunt capacitor 921 is disengaged. In some embodiments, the shunt capacitor 921 can be engaged in the first branch circuit 915 and the series capacitor 919 is disengaged. Also, in some embodiments, the series capacitor 923 can be engaged in the second branch circuit 917 and the shunt capacitor 925 is disengaged. In some embodiments, the shunt capacitor 925 can be engaged in the second branch circuit 917 and the series capacitor 923 is disengaged.

[0064] In some embodiments, a voltage sensor 933, e.g., a voltage / current sensor (VI sensor), is connected to measure the real-time voltage on the bias voltage supply node 905 and to transmit this measured voltage to the controller 911. In some embodiments, a voltage sensor 935, e.g., a voltage / current sensor (VI sensor), is connected to measure the real-time voltage at the output of the first branch circuit 915 and to transmit this measured voltage to the controller 911. In some embodiments, a voltage sensor 937, e.g., a voltage / current sensor (VI sensor), is connected to measure the real-time voltage at the output of the second branch circuit 917 and to transmit this measured voltage to the controller 911. In various embodiments, the controller 911 is configured to use the voltage measured by one or more of the voltage sensors 933, 935, and 937 as a (one or more) feedback signal for controlling the operation of the voltage supply system 901 and one or more of the series capacitor 919, shunt capacitor 921, series capacitor 923, and shunt capacitor 925.

[0065] Also, in some embodiments, the bias voltage supply system 115 includes several (N) RF generators 939-1 to 939-N connected to supply an RF bias voltage to the bias voltage supply node 905 via respective impedance matching networks 941-1 to 941-N, where N is greater than or equal to 1. Each of the RF generators 939-1 to 939-N is connected in bi-directional data / signal communication with the controller 911. At the bias voltage supply node 905, the (one or more) RF voltage signals output by the RF generators 939-1 to 939-N are combined with the bias voltage pulse waveform 902 output by the voltage supply system 901. The RF generators 939-1 to 939-N and the corresponding impedance matching networks 941-1 to 941-N are implemented in some embodiments of the bias voltage supply system 115. However, in other embodiments of the bias voltage supply system 115, the RF generators 939-1 to 939-N and the corresponding impedance matching networks 941-1 to 941-N are not implemented.

[0066] FIG. 10 shows an exemplary bias voltage pulse waveform 902 generated by the voltage supply system 901, a corresponding bias voltage waveform 1001 on the upper surface 105T of the substrate 105, and a corresponding bias voltage waveform 1003 on the upper surface 109T of the edge ring 109, according to some embodiments. The bias voltage pulse waveform 902 includes a bias voltage step portion (Vstep) 902A and a time-varying bias voltage portion (dV / dt) 902B. The bias voltage waveform 902 is generated at the bias voltage supply node 905. Accordingly, the bias voltage waveform 1001 on the upper surface 105T of the substrate 105 is based on the bias voltage waveform 902 modified by the first branch circuit 915. Similarly, the bias voltage waveform 1003 on the upper surface 109T of the edge ring 109 is based on the bias voltage waveform 902 modified by the second branch circuit 917. The bias voltage waveform 1001 includes a step portion 1001A and a slope portion 1001B. The bias voltage waveform 1003 includes a step portion 1003A and a slope portion 1003B.

[0067] The shunt capacitor 921 in the first branch circuit 915 controls the amplitude of the step portion 1001A of the bias voltage waveform 1001 on the upper surface 105T of the substrate 105. Specifically, the capacitance setting of the shunt capacitor 921 can be controlled such that the amplitude of the step portion 1001A is set at a certain ratio (0 to 100%) of the amplitude of the bias voltage step portion (Vstep) 902A. When the shunt capacitor 921 is disengaged (or does not exist) in the first branch circuit 915, the amplitude of the step portion 1001A is a fixed ratio of the amplitude of the bias voltage step portion (Vstep) 902A that depends on the parasitic capacitance effect of the substrate support structure 101 and the material of the substrate 105 existing between the main bias electrode 111 and the upper surface 105T of the substrate 105. The above-mentioned fixed ratio of the amplitude of the bias voltage step portion (Vstep) 902A depends on the structure between the output of the voltage supply system 901 and the upper surface 105T of the substrate 105. For example, in the structure such as the filter 903, the impedance matching networks 941-1 to 941-N, and the electrical connections 907, 909, 905, and 117, there may be stray shunt capacitance. Also, when the rise time of the bias voltage step portion (Vstep) 902A is relatively long compared to the ion travel time through the plasma sheath, the series capacitance between the output of the voltage supply system 901 and the upper surface 105T of the substrate 105 may reduce the above-mentioned fixed ratio of the amplitude of Vstep902A due to the ion flux during the rise time of Vstep902A. For example, in some embodiments, various series capacitances can be inserted in the filter 903, the substrate support structure 101, the substrate 105, and / or the electrical connections 907, 909, 905, and 117 for some purposes. The reduction of the above-mentioned fixed ratio of the amplitude of Vstep902A due to the series capacitance can be mostly eliminated by having a relatively short rise time of Vstep902A, for example, Vstep << 1 microsecond.

[0068] The series capacitor 919 in the first branch circuit 915 controls the slope (change in voltage with respect to time) of the sloped portion 1001B of the bias voltage waveform 1001 on the upper surface 105T of the substrate 105. When a voltage is applied to the main bias electrode 111, there is an ion current from the plasma 107 toward the upper surface 105T of the substrate 105, which discharges the negative charges on the upper surface 105T of the substrate 105 and correspondingly causes a decrease in the amplitude of the negative voltage on the upper surface 105T of the substrate 105 over time. To compensate for this ion-induced decrease in the amplitude of the negative voltage on the upper surface 105T of the substrate 105, the time-varying bias voltage portion (dV / dT) 902B of the bias voltage pulse waveform 902 provides an increase in the bias voltage over time. The capacitance setting of the series capacitor 919 is controlled to adjust the change in the bias voltage as a function of time on the upper surface 105T of the substrate 105 to compensate for the ion-induced discharge of the negative charges on the upper surface 105T of the substrate 105. In some embodiments, the capacitance setting of the series capacitor 919 is controlled to maintain a substantially constant voltage on the upper surface 105T of the substrate 105 during the on-duration of the bias voltage pulse waveform 902. However, in other embodiments, the capacitance setting of the series capacitor 919 is controlled to achieve a desired change in voltage (positive dV / dT and / or negative dV / dT) as a function of time on the upper surface 105T of the substrate 105 during the on-duration of the bias voltage pulse waveform 902. When the series capacitor 919 is disengaged / bypassed (or absent) in the first branch circuit 915, the change in voltage (dV / dT) as a function of time on the upper surface 105T of the substrate 105 during the on-duration of the bias voltage pulse waveform 902 will follow the time-varying bias voltage portion (dV / dT) 902B of the bias voltage pulse waveform 902 with a fixed voltage amplitude offset based on the parasitic capacitance effects of the substrate support structure 101 and the material of the substrate 105 existing between the main bias electrode 111 and the upper surface 105T of the substrate 105. In some embodiments, the aforementioned fixed voltage amplitude offset may also be based on the parasitic series capacitance between the output of the voltage supply system 901 and the upper surface 105T of the substrate 105.In some embodiments, the above-described parasitic series capacitance corresponds to various series capacitances inserted in the filter 903, the substrate support structure 101, the substrate 105, and / or the electrical connections 907, 909, 905, and 117 for some purposes.

[0069] The shunt capacitor 925 in the second branch circuit 917 controls the amplitude of the step portion 1003A of the bias voltage waveform 1003 on the upper surface 109T of the edge ring 109. Specifically, the capacitance setting of the shunt capacitor 925 can be controlled to set the amplitude of the step portion 1003A at a certain ratio (0 to 100%) of the amplitude of the bias voltage step portion (Vstep) 902A. When the shunt capacitor 925 is disengaged (or does not exist) in the second branch circuit 917, the amplitude of the step portion 1003A is a fixed ratio of the amplitude of the bias voltage step portion (Vstep) 902A that depends on the parasitic capacitance effect of the edge ring 109 material existing between the edge ring electrode 113 and the upper surface 109T of the edge ring 109. In some embodiments, the amplitude of the step portion 1003A can also be based on the parasitic series capacitance between the output of the voltage supply system 901 and the upper surface 109T of the edge ring 109. In some embodiments, the above-described parasitic series capacitance corresponds to various series capacitances inserted in the filter 903, the edge ring 109, and / or the electrical connections 907, 909, 905, and 119 for some purposes.

[0070] The series capacitor 923 in the second branch circuit 917 controls the slope (change in voltage with respect to time) of the sloped portion 1003B of the bias voltage waveform 1003 on the upper surface 109T of the edge ring 109. When a voltage is applied to the edge ring electrode 113, there is an ion current from the plasma 107 toward the upper surface 109T of the edge ring 109, which discharges the negative charge on the upper surface 109T of the edge ring 109 and, correspondingly, causes a decrease in the amplitude of the negative voltage on the upper surface 109T of the edge ring 109 over time. To compensate for this ion-induced decrease in the amplitude of the negative voltage on the upper surface 109T of the edge ring 109, the time-varying bias voltage portion (dV / dT) 902B of the bias voltage pulse waveform 902 provides an increase in the bias voltage over time. The capacitance setting of the series capacitor 923 is controlled to adjust the change in the bias voltage as a function of time on the upper surface 109T of the edge ring 109 to compensate for the ion-induced discharge of the negative charge on the upper surface 109T of the edge ring 109. In some embodiments, the capacitance setting of the series capacitor 923 is controlled to maintain a substantially constant voltage on the upper surface 109T of the edge ring 109 during the on-duration of the bias voltage pulse waveform 902. However, in other embodiments, the capacitance setting of the series capacitor 923 is controlled to achieve a desired change in voltage (positive dV / dT and / or negative dV / dT) as a function of time on the upper surface 109T of the edge ring 109 during the on-duration of the bias voltage pulse waveform 902. When the series capacitor 923 is disengaged / bypassed (or absent) in the second branch circuit 917, the change in voltage (dV / dT) as a function of time on the upper surface 109T of the edge ring 109 during the on-duration of the bias voltage pulse waveform 902 will follow the time-varying bias voltage portion (dV / dT) 902B of the bias voltage pulse waveform 902 with a fixed voltage amplitude offset based on the intrinsic capacitance effect of the edge ring 109 material existing between the edge ring electrode 113 and the upper surface 109T of the edge ring 109.In some embodiments, the fixed voltage amplitude offset described above can also be based on the parasitic series capacitance between the output of the voltage supply system 901 and the upper surface 109T of the edge ring 109. In some embodiments, the parasitic series capacitance described above corresponds to various series capacitances inserted in the filter 903, the edge ring 109, and / or the electrical connections 907, 909, 905, and 119 for some purposes.

[0071] FIG. 11A shows a chart of various ways in which a splitting circuit 913 can be configured according to various embodiments. A given configuration of the splitting circuit 913 corresponds to a particular engagement / disengagement combination of series capacitor 919, shunt capacitor 921, series capacitor 923, and shunt capacitor 925. FIG. 11B shows a chart depicting possible engagement / disengagement settings of series capacitor 919, shunt capacitor 921, series capacitor 923, and shunt capacitor 925 according to some embodiments. The engagement designation "yes" and the disengagement designation "no" referenced in FIG. 11B for each of series capacitor 919, shunt capacitor 921, series capacitor 923, and shunt capacitor 925 are used in the chart of FIG. 11A to describe the various possible configurations of the splitting circuit 913.

[0072] When the series capacitor 919 is engaged (series capacitor 919 = "yes"), the input terminal of the series capacitor 919 is electrically connected to the bias voltage supply node 905, and the output terminal of the series capacitor 919 is electrically connected to the main bias electrode 111 via the electrical connection 117. When the series capacitor 919 is disengaged (series capacitor 919 = "no"), the series capacitor 919 is either electrically bypassed in the first branch circuit 915 or does not exist, and thus the bias voltage supply node 905 is directly electrically connected to the main bias electrode 111 via the electrical connection 117. When the shunt capacitor 921 is engaged (shunt capacitor 921 = "yes"), the input terminal of the shunt capacitor 921 is electrically connected to the main bias electrode 111 via the electrical connection 117, and the output terminal of the shunt capacitor 921 is electrically connected to the reference ground potential 927. When the shunt capacitor 921 is disengaged (shunt capacitor 921 = "no"), the shunt capacitor 921 is either electrically disconnected from the main bias electrode 111 or does not exist in the first branch circuit 915.

[0073] When the series capacitor 923 is engaged (series capacitor 923 = "yes"), the input terminal of the series capacitor 923 is electrically connected to the bias voltage supply node 905, and the output terminal of the series capacitor 923 is electrically connected to the edge ring electrode 113 via the electrical connection 119. When the series capacitor 923 is disengaged (series capacitor 923 = "no"), the series capacitor 923 is either electrically bypassed in the second branch circuit 917 or does not exist, and thus, the bias voltage supply node 905 is directly electrically connected to the edge ring electrode 113 via the electrical connection 119. When the shunt capacitor 925 is engaged (shunt capacitor 925 = "yes"), the input terminal of the shunt capacitor 925 is electrically connected to the edge ring electrode 113 via the electrical connection 119, and the output terminal of the shunt capacitor 925 is electrically connected to the reference ground potential 927. When the shunt capacitor 925 is disengaged (shunt capacitor 925 = "no"), the shunt capacitor 925 is either electrically disconnected from the edge ring electrode 113 or does not exist in the second branch circuit 917.

[0074] FIG. 12 shows an exemplary RF bias voltage waveform 1201 generated with a bias voltage pulse waveform 902 according to some embodiments. The RF bias voltage waveform 1201 is generated by one or more of RF generators 939-1 to 939-N and is supplied to a bias voltage supply node 905 in combination with the bias voltage pulse waveform 902 generated by a voltage supply system 901. A filter 903 is configured to prevent the RF bias voltage waveform 1201 from proceeding to the voltage supply system 901. In some embodiments, the filter 903 is a low-pass filter or a notch filter configured to block RF frequency signals. In some embodiments, the bias voltage pulse waveform 902 establishes a baseline voltage waveform followed by the RF bias voltage waveform 1201. By a splitting circuit 913, a first portion of the RF bias voltage is applied to a main bias electrode 111, and a second portion of the RF bias voltage is applied to an edge ring electrode 113. The first portion of the RF bias voltage generates an RF bias voltage waveform 1203 on an upper surface 105T of a substrate 105. The second portion of the RF bias voltage generates an RF bias voltage waveform 1205 on an upper surface 109T of an edge ring 109. A shunt capacitor 921 in a first branch circuit 915 controls the amplitude of the RF bias voltage waveform 1203. Similarly, a shunt capacitor 925 in a second branch circuit 917 controls the amplitude of the RF bias voltage waveform 1205. Accordingly, the ratio of the amplitude of the RF bias voltage on the upper surface 105T of the substrate 105 to the amplitude of the RF bias voltage on the upper surface 109T of the edge ring 109 is proportional to the ratio of the amplitude of the bias voltage waveform 1001 on the upper surface 105T of the substrate 105 to the amplitude of the bias voltage waveform 1003 on the upper surface 109T of the edge ring 109. As described above, it is optional to generate the RF bias voltage waveform 1201 together with the bias voltage pulse waveform 902.

[0075] FIG. 13 shows another bias voltage supply system 1301 for implementing the various methods described with respect to FIGS. 3-8 for controlling the plasma sheath boundary profile near the outer peripheral edge of substrate 105, in which various bias voltage waveforms are applied to the upper surface 105T of substrate 105 and the upper surface 109T of edge ring 109. The bias voltage supply system 1301 includes a first voltage supply system 1302 and a second voltage supply system 1310. The first voltage supply system 1302 includes a pulse voltage generator 1303 having an output connected to the main bias electrode 111 via a filter 1305 and an electrical connection 117. The pulse voltage generator 1303 is configured in the same manner as the voltage supply system 901. Thus, the pulse voltage generator 1303 generates a defined voltage waveform 902-1 and supplies it to the main bias electrode 111. The defined voltage waveform 902-1 includes a step portion 902A1 and a slope portion 902B1. The filter 1305 is configured to prevent RF signals from entering the pulse voltage generator 1303. In various embodiments, the filter 1305 is a low-pass filter or a notch filter.

[0076] The first voltage supply system 1302 also optionally includes several (N) RF generators 1307-1 to 1307-N, where N is greater than or equal to 1, connected to supply an RF bias voltage to the main bias electrode 111 via respective impedance matching networks 1309-1 to 1309-N. Each of the RF generators 1307-1 to 1307-N is connected in bidirectional data / signal communication with the controller 911. The controller 911 operates to synchronize the bias voltage waveform output by the pulse voltage generator 1303 with the bias voltage waveforms output by each of the RF generators 1307-1 to 1307-N. The (one or more) RF voltage signals output by the RF generators 1307-1 to 1307-N are combined with the bias voltage pulse waveform 902-1 output by the pulse voltage generator 1303 on the electrical connection 117. The RF generators 1307-1 to 1307-N and the corresponding impedance matching networks 1309-1 to 1309-N are implemented in some embodiments of the first voltage supply system 1302. However, in some embodiments, the RF generators 1307-1 to 1307-N and the corresponding impedance matching networks 1309-1 to 1309-N are not implemented in the first voltage supply system 1302.

[0077] The second voltage supply system 1310 includes a pulse voltage generator 1311 having an output connected to the edge ring electrode 113 via a filter 1313 and an electrical connection 119. The pulse voltage generator 1311 is configured in the same manner as the voltage supply system 901. Thus, the pulse voltage generator 1311 generates a defined voltage waveform 902-2 and supplies it to the edge ring electrode 113. The defined voltage waveform 902-2 includes a step portion 902A2 and a ramp portion 902B2. The filter 1313 is configured to prevent RF signals from entering the pulse voltage generator 1311. In various embodiments, the filter 1313 is a low-pass filter or a notch filter.

[0078] The second voltage supply system 1310 also optionally includes several (N) RF generators 1315-1 to 1315-N connected to supply RF bias voltages to the edge ring electrodes 113 via respective impedance matching networks 1317-1 to 1317-N, where N is greater than or equal to 1. Each of the RF generators 1315-1 to 1315-N is connected in bidirectional data / signal communication with the controller 911. The controller 911 operates to synchronize the bias voltage waveform output by the pulse voltage generator 1311 and the bias voltage waveforms output by each of the RF generators 1315-1 to 1315-N. The (one or more) RF voltage signals output by the RF generators 1315-1 to 1315-N are combined on the electrical connection 119 with the bias voltage pulse waveform 902-2 output by the pulse voltage generator 1311. The RF generators 1315-1 to 1315-N and the corresponding impedance matching networks 1317-1 to 1317-N are implemented in some embodiments of the second voltage supply system 1310. However, in some embodiments, the RF generators 1315-1 to 1315-N and the corresponding impedance matching networks 1317-1 to 1317-N are not implemented in the second voltage supply system 1310.

[0079] In some embodiments, the bias voltage pulse waveform 902-1 is generated to maintain a substantially constant voltage on the upper surface 105T of the substrate 105 during the on-duration of each pulse cycle within the bias voltage pulse waveform 902-1, and the bias voltage pulse waveform 902-2 is generated to maintain a substantially constant voltage on the upper surface 109T of the edge ring 109 during the on-duration of each pulse cycle within the bias voltage pulse waveform 902-2. Thus, a substantially constant voltage difference is maintained during the parallel on-durations of the pulse cycles in the bias voltage pulse waveforms 902-1 and 902-2, where the substantially constant voltage difference is defined to maintain a substantially flat plasma sheath boundary across the transition between the substrate 105 and the edge ring 109. In some embodiments, the step portion 902A1 of the bias voltage pulse waveform 902-1 and the step portion 902A2 of the bias voltage pulse waveform 902-2 are synchronously controlled to achieve a defined voltage difference between the upper surface 105T of the substrate 105 and the upper surface 109T of the edge ring 109. Also, in some embodiments, the ramp portion 902B1 of the bias voltage pulse waveform 902-1 is controlled to compensate for the ion-induced discharge of negative charges on the upper surface 105T of the substrate 105 over the on-duration of each pulse cycle of the bias voltage pulse waveform 902-1 such that the voltage on the upper surface 105T of the substrate 105 remains substantially constant over the on-duration of each pulse cycle of the bias voltage pulse waveform 902-1. Also, in some embodiments, the ramp portion 902B2 of the bias voltage pulse waveform 902-2 is controlled to compensate for the ion-induced discharge of negative charges on the upper surface 109T of the edge ring 109 over the on-duration of each pulse cycle of the bias voltage pulse waveform 902-2 such that the voltage on the upper surface 109T of the edge ring 109 remains substantially constant over the on-duration of each pulse cycle of the bias voltage pulse waveform 902-2.

[0080] Bias voltage pulse waveforms 902-1 and 902-2 can be generated as needed to implement the various methods described with respect to FIGS. 3-8. In some embodiments, controller 911 operates to synchronize the phases of bias voltage pulse waveforms 902-1 and 902-2. In some embodiments, controller 911 operates to synchronize both the phases and duty cycles of bias voltage pulse waveforms 902-1 and 902-2. In some embodiments, controller 911 operates to implement a defined phase shift between bias voltage pulse waveform 902-1 and bias voltage pulse waveform 902-2. In some embodiments, bias voltage pulse waveforms 902-1 and 902-2 are defined to have different phases and / or different duty cycles from each other. Also, in some embodiments, one or both of bias voltage pulse waveforms 902-1 and 902-2 are defined to implement a defined level-to-level pulsing scheme. It should be understood that bias voltage pulse waveforms 902-1 and 902-2 are controllable separately and independently of each other.

[0081] Furthermore, in various embodiments, any number of voltage sensors, such as voltage / current sensors (VI sensors), can be connected within bias voltage supply system 1301 to measure the real-time voltage at a particular location and communicate this measured real-time voltage to controller 911. In some embodiments, controller 911 is configured to use real-time voltage measurements within first voltage supply system 1302 and / or second voltage supply system 1310 to control the operation of any one or more of pulse voltage generator 1303, RF generators 1307-1 through 1307-N, pulse voltage generator 1311, and RF generators 1315-1 through 1315-N.

[0082] FIG. 14 shows an exemplary diagram of a controller 911 according to some embodiments. In some embodiments, the controller 911 includes a processor 1409, a memory hardware unit (HU) 1411 (e.g., a memory), an input HU 1401, an output HU 1405, an input / output (I / O) interface 1403, an I / O interface 1407, a network interface controller (NIC) 1415, and a data communication bus 1413. The processor 1409, the memory HU 1411, the input HU 1401, the output HU 1405, the I / O interface 1403, the I / O interface 1407, and the NIC 1415 communicate with each other via the data communication bus 1413. Examples of the input HU 1401 include a mouse, a keyboard, a stylus, a data collection system, a data collection card, and the like. Examples of the output HU 1405 include a display, a speaker, a device controller, and the like. Examples of the NIC 1415 include a network interface card, a network adapter, and the like. In various embodiments, the NIC 1415 is configured to operate in accordance with one or more communication protocols and associated physical layers, particularly Ethernet and / or EtherCAT. Each of the I / O interfaces 1403 and 1407 is defined to provide compatibility between different hardware units coupled to the I / O interface. For example, the I / O interface 1403 may be defined to convert a signal received from the input HU 1401 into a form, amplitude, and / or speed that is compatible with the data communication bus 1413. Also, the I / O interface 1407 may be defined to convert a signal received from the data communication bus 1413 into a form, amplitude, and / or speed that is compatible with the output HU 1405. Although the various operations described herein are performed by the processor 1409 of the controller 911, it should be understood that in some embodiments, the various operations may be performed by multiple processors of the controller 911 and / or by multiple processors of multiple computing systems connected to the controller 911.

[0083] In various embodiments, the substrate plasma processing system 100 is integrated with electronics for controlling its operation before, during, and after processing of the substrate 105, and those electronics are implemented within a controller 911 configured and connected to control various components and / or sub-parts of the substrate plasma processing system 100, including bias voltage supply systems 115 and 1301. Depending on the substrate 105 processing requirements and / or particular configuration of the substrate plasma processing system 100, the controller 911 is programmed to control any process and / or component disclosed herein, including, in particular, delivery of (one or more) process gases, temperature setting (e.g., heating and / or cooling), pressure setting, vacuum setting, power setting, RF power supply system setting, electrical signal frequency setting, gas flow rate setting, fluid delivery setting, position and motion setting, bias voltage supply system 115 / 1301 setting, transfer of the substrate 105 to and from the substrate plasma processing system 100 and / or to and from a load lock connected to or interfaced with the substrate plasma processing system 100.

[0084] In various embodiments, the controller 911 is defined as electronics having various integrated circuits, logic, memory, and / or software for instructing and controlling various tasks / operations, such as receiving commands, issuing commands, controlling device operations, enabling cleaning operations, enabling endpoint measurements, enabling metrology measurements (light, heat, electricity, etc.), among other tasks / operations. In some embodiments, the integrated circuits within the controller 911 include one or more of firmware that stores program instructions, a digital signal processor (DSP) that executes program instructions (e.g., software) among computing devices, an application specific integrated circuit (ASIC) chip, a programmable logic device (PLD), one or more microprocessors, and / or one or more microcontrollers. In some embodiments, the program instructions are communicated to the controller 911 in the form of various individual settings (or program files) that define the operating parameters for performing processes on the substrate 105 within the substrate plasma processing system 100. In some embodiments, the operating parameters are included in a recipe defined by a process engineer to achieve one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies on the substrate 105.

[0085] In some embodiments, the controller 911 is part of a computer that is integrated with, connected to, or otherwise network-connected to the substrate plasma processing system 100, or is connected to a computer, or a combination thereof. For example, in some embodiments, the controller 911 is implemented in whole or in part in a "cloud" or fab host computer system, which enables remote access for the control of substrate 105 processing by the substrate plasma processing system 100. The controller 911 enables remote access to the substrate plasma processing system 100 to provide monitoring of the current progress of fabrication operations, inspection of the history of past fabrication operations, inspection of trends or performance metrics from multiple fabrication operations, providing changes to processing parameters, providing settings for subsequent processing steps, providing specifications for RF power supply system operating parameters, providing specifications for bias voltage supply system 115 / 1301 operating parameters, and / or providing initiation of a new substrate fabrication process.

[0086] In some embodiments, a remote computer, such as a server computer system, provides a process recipe to the controller 911 over a computer network that includes a local network and / or the Internet. The remote computer includes a user interface that enables entry or programming of parameters and / or settings, and the parameters and / or settings are then communicated from the remote computer to the controller 911. In some examples, the controller 911 receives instructions in the form of settings for processing the substrate 105 within the substrate plasma processing system 100. It should be understood that those settings are specific to the type of process to be performed on the substrate 105 and the type of tools / devices / components that the controller 911 interfaces with or controls. In some embodiments, the controller 911 is distributed, such as by including one or more individual controllers 911 that are network-connected together and synchronized to function towards a common purpose, such as operating the substrate plasma processing system 100 to perform a process defined on the substrate 105. An example of such a distributed controller 911 for such a purpose includes one or more integrated circuits on a chamber that communicate with one or more remote integrated circuits (such as at the platform level or as part of a remote computer) that are combined to control the process in the chamber.

[0087] FIG. 15 shows a flowchart of a method for supplying a bias voltage during plasma processing of a substrate 105 according to some embodiments. The method includes operation 1501 for generating a defined voltage waveform as a function of time on a bias voltage supply node 905. The method also includes operation 1503 for transmitting a first version of the defined voltage waveform from the bias voltage supply node 905 to a main bias electrode 111 disposed below a substrate support surface 103 to control a voltage on an upper surface 105T of a substrate 105 present on the substrate support surface 103. The method also includes operation 1505 for transmitting a second version of the defined voltage waveform to an edge ring electrode 113 disposed within an edge ring 109 circumscribing the substrate support surface 103 to control a voltage on an upper surface 109T of the edge ring 109.

[0088] In some embodiments, in operation 1501, generating the defined voltage waveform includes generating a voltage amplitude that is constant over time, generating a voltage that varies over time, and combining the voltage amplitude that is constant over time and the voltage that varies over time to form the defined voltage waveform on the bias voltage supply node 905. In some embodiments, the voltage that varies over time varies substantially linearly as a function of time. In some embodiments, the defined voltage waveform generated in operation 1501 is a pulse voltage waveform defined as an ongoing series of pulse cycles, and each pulse cycle includes an on duration during which the pulse voltage waveform has a negative voltage and an off duration during which the pulse voltage waveform has a positive voltage. In some embodiments, the method includes generating the defined voltage waveform on the bias voltage supply node 905 in operation 1501 and supplying a radio frequency signal to the bias voltage supply node 905.

[0089] In some embodiments, the method includes using a series capacitor 923 and a shunt capacitor 925 in an electrical circuit 917 extending from a bias voltage supply node 905 to an edge ring electrode 113 to generate a second version of a defined voltage waveform transmitted to the edge ring electrode 113. In some embodiments, the method includes controlling the shunt capacitor 925 to establish a defined voltage difference between an upper surface 105T of the substrate 105 and an upper surface 109T of the edge ring 109 during an on-duration of each pulse cycle of a pulsed voltage waveform corresponding to the defined voltage waveform generated in operation 1501. In some embodiments, the method includes controlling the series capacitor 923 to maintain a defined voltage difference between an upper surface 105T of the substrate 105 and an upper surface 109T of the edge ring 109 at a substantially constant level over an on-duration of each pulse cycle of a pulsed voltage waveform corresponding to the defined voltage waveform generated in operation 1501. In some embodiments, the method includes controlling the series capacitor 923 to vary the voltage on the upper surface 109T of the edge ring 109 as a function of time to compensate for discharge on the upper surface of the edge ring 109 as a function of time.

[0090] In some embodiments, the method includes using a first series capacitor 919 and a first shunt capacitor 921 in a first electrical circuit 915 extending from a bias voltage supply node 905 to a main bias electrode 111 to generate a first version of a defined voltage waveform transmitted to the main bias electrode 111. In some embodiments, the method also includes using a second series capacitor 923 and a second shunt capacitor 925 in a second electrical circuit 917 extending from the bias voltage supply node 905 to an edge ring electrode 113 to generate a second version of a defined voltage waveform transmitted to the edge ring electrode 113. In some embodiments, the method includes controlling the first shunt capacitor 921 and the second shunt capacitor 925 to establish a defined voltage difference between an upper surface 105T of the substrate 105 and an upper surface 109T of the edge ring 109 during an on-duration of each pulse cycle of a pulse voltage waveform corresponding to the defined voltage waveform generated in operation 1501. In some embodiments, the method includes controlling the first series capacitor 919 and the second series capacitor 923 to maintain a defined voltage difference between an upper surface 105T of the substrate 105 and an upper surface 109T of the edge ring 109 at a substantially constant level over an on-duration of each pulse cycle of a pulse voltage waveform corresponding to the defined voltage waveform generated in operation 1501.

[0091] The various embodiments described herein can be practiced with a variety of computer system configurations including portable hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. The various embodiments described herein can also be practiced with a distributed computing environment where tasks are performed by remote processing hardware units linked through a computer network. It should also be understood that the various embodiments disclosed herein include the performance of various computer-implemented operations involving data stored in a computer system. These computer-implemented operations manipulate physical quantities. In various embodiments, the computer-implemented operations are performed by either a general-purpose computer or a dedicated computer. In some embodiments, the computer-implemented operations are performed by a computer selectively activated and / or directed by one or more computer programs stored in a computer memory or retrieved over a computer network. When a computer program and / or digital data is retrieved over a computer network, the digital data can be processed by other computers on the computer network, such as by a cloud of computing resources. The computer program and digital data are stored as computer-readable code on a non-transitory computer-readable medium. A non-transitory computer-readable medium is any data storage hardware unit that stores data, such as a memory device, and the data is thereafter readable by a computer system. Examples of non-transitory computer-readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disc ROM (CD-ROM), CD recordable (CD-R), CD rewritable (CD-RW), digital video / general purpose disc (DVD), magnetic tape, and other optical and non-optical data storage hardware units.In some embodiments, a computer program and / or digital data are distributed among a plurality of computer-readable media in different computer systems within a network of coupled computer systems such that the computer program and / or digital data are executed and / or stored in a distributed fashion.

[0092] The foregoing disclosure includes details from what for purposes of clarity of understanding, but it will be apparent that some changes and modifications can be practiced within the scope of the appended claims. For example, it should be understood that one or more features from any of the embodiments disclosed herein can be combined with one or more features from any of the other embodiments disclosed herein. Accordingly, the embodiments should be regarded as illustrative rather than restrictive, and the claims should not be limited to the details given herein, but may be modified within the scope and equivalents of the described embodiments.

Claims

1. A bias voltage supply system, A main bias electrode disposed below the substrate support surface, the main bias electrode being configured to control the voltage on the upper surface of the substrate on the substrate support surface, the main bias electrode; An edge ring electrode disposed in an edge ring circumscribing the substrate support surface, the edge ring electrode being configured to control the voltage on the upper surface of the edge ring, the edge ring electrode; A voltage supply system configured to generate a prescribed voltage waveform as a function of time on a bias voltage supply node; A first branch circuit electrically connected between the bias voltage supply node and the main bias electrode; A second branch circuit electrically connected between the bias voltage supply node and the edge ring electrode, the second branch circuit including a series capacitor and a shunt capacitor, the second branch circuit; A bias voltage supply system comprising.

2. The bias voltage supply system according to claim 1, wherein the voltage supply system includes a first voltage source and a second voltage source, the first voltage source being configured to generate a voltage amplitude that is constant over time, the second voltage source being configured to generate a voltage that varies over time, and the constant voltage amplitude over time and the voltage that varies over time are combined to form the prescribed voltage waveform, the bias voltage supply system.

3. The bias voltage supply system according to claim 2, wherein the voltage that varies over time varies substantially linearly as a function of time, the bias voltage supply system.

4. The bias voltage supply system according to claim 2, wherein the first voltage source is a first DC voltage supply and the second voltage source is a second DC voltage supply, the bias voltage supply system.

5. The bias voltage supply system according to claim 1, wherein the specified voltage waveform is a pulse voltage waveform defined as a series of ongoing pulse cycles, and each pulse cycle includes an on-duration during which the pulse voltage waveform has a negative voltage and an off-duration during which the pulse voltage waveform has a positive voltage.

6. The bias voltage supply system according to claim 5, wherein the shunt capacitor is set to establish a specified voltage difference between the upper surface of the substrate and the upper surface of the edge ring during the on-duration of each pulse cycle of the pulse voltage waveform.

7. The bias voltage supply system according to claim 6, wherein the series capacitor is set to maintain the specified voltage difference between the upper surface of the substrate and the upper surface of the edge ring at a substantially constant level over the on-duration of each pulse cycle of the pulse voltage waveform.

8. The bias voltage supply system according to claim 7, wherein the series capacitor is set to change the voltage on the upper surface of the substrate as a function of time to compensate for discharge on the upper surface of the substrate as a function of time.

9. The bias voltage supply system according to claim 1, wherein each of the series capacitor and the shunt capacitor is an independently controllable variable capacitor.

10. The bias voltage supply system according to claim 1, further comprising a radio frequency power source electrically connected to supply a radio frequency signal to the bias voltage supply node along with the generation of the specified voltage waveform by the voltage supply system.

11. The bias voltage supply system according to claim 1, wherein the series capacitor is a first series capacitor, the shunt capacitor is a first shunt capacitor, and the first branch circuit includes a second series capacitor and a second shunt capacitor.

12. The bias voltage supply system according to claim 11, wherein the specified voltage waveform is a pulse voltage waveform defined as a series of ongoing pulse cycles, each pulse cycle including an on-duration during which the pulse voltage waveform has a negative voltage and an off-duration during which the pulse voltage waveform has a positive voltage, and the first shunt capacitor and the second shunt capacitor are collectively set to establish a specified voltage difference between the upper surface of the substrate and the upper surface of the edge ring during the on-duration of each pulse cycle of the pulse voltage waveform.

13. The bias voltage supply system according to claim 12, wherein the first series capacitor and the second series capacitor are collectively set to maintain the specified voltage difference between the upper surface of the substrate and the upper surface of the edge ring at a substantially constant level over the on-duration of each pulse cycle of the pulse voltage waveform.

14. The bias voltage supply system according to claim 11, wherein the first series capacitor is a first variable capacitor, the first shunt capacitor is a second variable capacitor, the second series capacitor is a third variable capacitor, the second shunt capacitor is a fourth variable capacitor, and the first variable capacitor, the second variable capacitor, the third variable capacitor, and the fourth variable capacitor are controllable independently of each other.

15. The bias voltage supply system according to claim 11, A bias voltage supply system further comprising a radio frequency power source electrically connected to supply a radio frequency signal to the bias voltage supply node while generating the specified voltage waveform by the voltage supply system. **Claim 16** A bias voltage supply system, A main bias electrode disposed below the substrate support surface, the main bias electrode being configured to control the voltage on the upper surface of the substrate on the substrate support surface, the main bias electrode; An edge ring electrode disposed in an edge ring circumscribing the substrate support surface, the edge ring electrode being configured to control the voltage on the upper surface of the edge ring, the edge ring electrode; A first voltage supply system configured to generate a first specified voltage waveform as a function of time on the main bias electrode, the first voltage supply system including a first voltage supply and a second voltage supply, the first voltage supply being configured to generate a first time-constant voltage amplitude, the second voltage supply being configured to generate a first time-varying voltage, the first time-constant voltage amplitude and the first time-varying voltage being combined to form the first specified voltage waveform, the first voltage supply system; A second voltage supply system configured to generate a second specified voltage waveform as a function of time on the edge ring electrode, the second voltage supply system including a third voltage supply and a fourth voltage supply, the third voltage supply being configured to generate a second time-constant voltage amplitude, the fourth voltage supply being configured to generate a second time-varying voltage, the second time-constant voltage amplitude and the second time-varying voltage being combined to form the second specified voltage waveform, the second voltage supply system; Comprising a bias voltage supply system. **Claim 17** The bias voltage supply system according to claim 16, wherein the first defined voltage waveform is defined as a first series of ongoing pulse cycles, each pulse cycle including an on-duration during which the first pulse voltage waveform has a negative voltage and an off-duration during which the first pulse voltage waveform has a positive voltage. The second defined voltage waveform is defined as a second series of ongoing pulse cycles, each pulse cycle including an on-duration during which the second pulse voltage waveform has a negative voltage and an off-duration during which the second pulse voltage waveform has a positive voltage. A bias voltage supply system in which the first pulse voltage waveform and the second pulse voltage waveform are synchronized. **Claim 18** The bias voltage supply system according to claim 16, further comprising a radio frequency power source electrically connected to supply radio frequency signals to both the main bias electrode and the edge ring electrode, together with the generation of the first defined voltage waveform by the first voltage supply system and the generation of the second defined voltage waveform by the second voltage supply system. **Claim 19** A method for supplying a bias voltage during plasma processing of a substrate, generating a defined voltage waveform as a function of time at a bias voltage supply node; transmitting a first version of the defined voltage waveform from the bias voltage supply node to a main bias electrode disposed below a substrate support surface to control a voltage on an upper surface of a substrate present on the substrate support surface; transmitting a second version of the defined voltage waveform to an edge ring electrode disposed within an edge ring circumscribing the substrate support surface to control a voltage on an upper surface of the edge ring; comprising. **Claim 20** The method according to claim 19, wherein generating the specified voltage waveform includes generating a voltage amplitude that is constant over time, generating a voltage that varies over time, and combining the voltage amplitude that is constant over time and the voltage that varies over time to form the specified voltage waveform on the bias voltage supply node.

21. The method according to claim 20, wherein the voltage that varies over time varies substantially linearly as a function of time.

22. The method according to claim 19, wherein the specified voltage waveform is a pulse voltage waveform defined as a series of ongoing pulse cycles, and each pulse cycle includes an on-duration during which the pulse voltage waveform has a negative voltage and an off-duration during which the pulse voltage waveform has a positive voltage.

23. The method according to claim 22, further comprising using a series capacitor and a shunt capacitor in an electrical circuit extending from the bias voltage supply node to the edge ring electrode to generate the second version of the specified voltage waveform.

24. The method according to claim 23, controlling the shunt capacitor to establish a specified voltage difference between the upper surface of the substrate and the upper surface of the edge ring during the on-duration of each pulse cycle of the pulse voltage waveform.

25. The method according to claim 24, controlling the series capacitor to maintain the specified voltage difference between the upper surface of the substrate and the upper surface of the edge ring at a substantially constant level over the on-duration of each pulse cycle of the pulse voltage waveform.

26. The method according to claim 25, wherein controlling the series capacitor to change the voltage on the upper surface of the edge ring as a function of time to compensate for the discharge on the upper surface of the edge ring as a function of time is further included. **Claim 27** The method according to claim 22, wherein using a first series capacitor and a first shunt capacitor in a first electrical circuit extending from the bias voltage supply node to the main bias electrode to generate the first version of the specified voltage waveform; and using a second series capacitor and a second shunt capacitor in a second electrical circuit extending from the bias voltage supply node to the edge ring electrode to generate the second version of the specified voltage waveform; and is further included. **Claim 28** The method according to claim 27, wherein controlling the first shunt capacitor and the second shunt capacitor to establish a specified voltage difference between the upper surface of the substrate and the upper surface of the edge ring during the on-duration of each pulse cycle of the pulse voltage waveform is further included. **Claim 29** The method according to claim 28, wherein controlling the first series capacitor and the second series capacitor to maintain the specified voltage difference between the upper surface of the substrate and the upper surface of the edge ring at a substantially constant level over the on-duration of each pulse cycle of the pulse voltage waveform is further included. **Claim 30** The method according to claim 19, wherein Generating the specified voltage waveform on the bias voltage supply node and supplying a radio frequency signal to the bias voltage supply node A method further comprising.

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