Memory with dual-column redundancy
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- QUALCOMM INC
- Filing Date
- 2023-04-24
- Publication Date
- 2026-04-20
AI Technical Summary
Existing memory banks with column redundancy schemes can become inoperable if two column groups within a single bank develop defects, as they lack the capability to replace multiple defective column groups simultaneously.
The implementation of a memory bank with dual redundancy, featuring a first switch matrix that couples latches to one of three adjacent column groups in response to column redundancy signals, allowing for the replacement of two defective column groups with redundant ones.
This dual redundancy approach enables the memory bank to maintain operability even when two column groups are defective, ensuring continuous data access and storage by effectively utilizing redundant column groups.
Smart Images
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Abstract
Description
Technical Field
[0001] This application relates to a memory, and more specifically, to a memory bank that can replace a pair of defective column groups with two redundant column groups.
Background Art
[0002] A static random-access memory (SRAM) includes an array of bit cells arranged in rows and columns. To improve performance, such as by reducing the capacitance of bit lines, the array of bit cells is typically subdivided into banks. Without redundancy, a single error in a bank can render the entire bank inoperable. Thus, it is common for each bank to have redundant columns so that the bank can replace a defective column with a redundant column.
[0003] There are two main methods for implementing column redundancy, namely, input / output (I / O) shifting and sense amplifier shifting. I / O shifting is easier to implement but requires more semiconductor die space compared to sense amplifier shifting. In both types of column redundancy, each bank can replace a defective column through the use of redundant columns. Thus, a bank can replace a single defective column using a redundant column. However, defects in two columns in a single bank can render the bank inoperable.
Summary of the Invention
[0004] According to one aspect of the present disclosure, a memory is provided, the memory including a plurality of column groups, each column group within the plurality of column groups including a plurality of multiplexed columns, the plurality of column groups including a first column group, a second column group adjacent to the first column group, and a third column group adjacent to the second column group, and a first switch matrix configured to couple a latch to one of the first column group, the second column group, and the third column group in response to a plurality of column redundancy signals.
[0005] According to another aspect of the present disclosure, a memory is provided, the memory including a plurality of column groups, each column group within the plurality of column groups including a plurality of multiplexed columns, the plurality of column groups including a first column group and a second column group adjacent to the first column group, a first latch, a second latch, and a first switch matrix including a first switch coupled between the first column group and a first central node, a second switch coupled between the first central node and the second column group, a third switch coupled between the first latch and the first central node, and a fourth switch coupled between the first central node and the second latch.
[0006] According to yet another aspect of the present disclosure, a memory is provided, the memory including a plurality of column groups, each column group within the plurality of column groups including a plurality of multiplexed columns, the plurality of column groups including a first column group and a second column group, a first latch, a second latch, a first switch matrix coupled to the first column group, the second column group, the first latch, and the second latch, a first redundant column group including a first plurality of multiplexed redundant columns, and a second redundant column group including a second plurality of multiplexed redundant columns.
[0007] According to yet another aspect of the present disclosure, a method for memory redundancy is provided. The method includes coupling a first latch to a first column group in a plurality of column groups in response to a subset of the plurality of column groups extending from a first column group to a first column group having no defective column groups; coupling the first latch to a second column group adjacent to the first column group in the plurality of column groups in response to the first column group being a first defective column group in the plurality of column groups; and coupling the first latch to a third column group adjacent to the second column group in the plurality of column groups in response to the second column group being a second defective column group in the plurality of column groups.
[0008] These and additional advantages may be more fully understood through the following "Detailed Description of the Invention".
Brief Description of the Drawings
[0009]
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[0010] The implementations of the present disclosure and their advantages are best understood by referring to the following "Detailed Description of the Invention". It should be understood that like reference numerals are used to identify like elements shown in one or more of the figures.
Detailed Description of the Invention
[0011] An I / O shifting redundancy scheme is provided that can replace two defective column groups within a single bank. A memory is disclosed that includes a plurality of column groups and a pair of redundant column groups to provide this advantageous dual redundancy. To provide a better understanding of these innovative features, some terms are first outlined. In an SRAM bank, each bit cell stores a bit signal and the complement of the bit signal. To access these complementary signals, the bit cell is coupled to a pair of bit lines. The SRAM bank includes a plurality of such bit line pairs, and each bit line pair is coupled to a single column of bit cells arranged in a row within a single column according to the corresponding word line. During a write operation, an input latch within an input / output circuit (also referred to herein as an I / O circuit) is coupled to the selected bit cell via the corresponding bit line pair. Similarly, during a read operation, an output latch within the input / output circuit is coupled to the selected bit cell via the corresponding bit line pair.
[0012] This coupling between the bit line pair (and corresponding bit cells) and the input / output circuit can be multiplexed so that the input / output circuit can couple to one of a plurality of multiplexed columns. For example, in a "MUX2" implementation, the bit line pairs can be organized into odd and even pairs. Then, depending on the multiplexing, the input / output circuit can couple to the selected bit line pairs from the corresponding odd and even pairs. Thus, in a write operation, the input / output circuit can couple to the selected bit line pair via a write driver and a write multiplexer. Similarly, during a read operation, the input / output circuit can couple to the selected bit line pair via a read multiplexer and a sense amplifier. Other types of multiplexing of the bit line pairs can be used, such as in a "MUX4" implementation where each input / output circuit can couple to one of four multiplexed columns.
[0013] Regarding column multiplexing, the combination of the write driver, the write multiplexer, the read multiplexer, and the sense amplifier can be referred to herein as a "local data path". The combination of the local data path and the corresponding multiplexed column is referred to herein as a "column group" to emphasize the bit line multiplexing aspect. Each multiplexed column includes a bit line pair and a plurality of bit cells.
[0014] The following description is directed to implementations where the I / O circuit is a global I / O circuit, but it will be understood that the I / O shifting disclosed herein is applicable to implementations where the I / O circuit is a local I / O circuit. The term "global" I / O circuit is used in that a global I / O circuit can be shared between two banks, while a local I / O circuit belongs to only one bank. In the following description, each global I / O circuit is simply referred to as an "I / O circuit" for simplicity.
[0015] To address the possibility of two defective column groups within a single bank, a memory bank including two redundant column groups is disclosed. In the absence of defective column groups within the memory bank, the switch matrix within each I / O circuit is configured to couple the latches within the I / O circuit to the corresponding default column group. Thus, during a read operation, the output latches within the I / O circuit receive data bits retrieved from the default column group. Similarly, the input latches within the I / O circuit provide data bits to be written to the default column group during a write operation. If the memory bank includes a single defective column group, each of one or more of the I / O circuits can instead be coupled to a neighboring column group. For example, assume that there are N column groups arranged from the (N−1)th column group to the 0th column group within the bank. Here, N is a positive integer greater than or equal to 2. Thus, there are N I / O circuits, namely, the (N−1)th I / O circuit corresponding to the (N−1)th column group, the (N−2)th I / O circuit corresponding to the (N−2)th column group, and so on, down to the 0th I / O circuit corresponding to the 0th column group. In the absence of any errors, each I / O circuit is coupled to the corresponding column group. However, assume that the ith column group is the first defective column group within the bank (where i is an integer less than N). From the Nth column group to the (i + 1)th column group, each I / O circuit continues to be coupled to its default column group as described above. From the ith column group to the 0th column group, each global I / O circuit is instead coupled to a column group neighboring or adjacent to the default column group. For example, the ith global I / O circuit is coupled to the (i−1)th column group, the (i−1)th I / O circuit is coupled to the (i−2)th column group, and so on, down to the 0th I / O circuit being coupled to the first redundant column group. For such a single defective column group, the array of column groups can thus be divided into a non-shift region where each I / O circuit is coupled to the default column group and a one-shift region where each I / O circuit is coupled to a column group contiguous or neighboring to the default column group.
[0016] If there are two defective column groups within a single bank, the multiple column groups can instead be divided into a no-shift region, a one-shift region, and a two-shift region. The no-shift region and the one-shift region are as described above and are delimited by the first defective column group. The column group immediately preceding the second defective column group is the first column group within the two-shift region. Each I / O circuit within the two-shift region couples to the next column group of the column groups in the vicinity of the default column group of the I / O circuit. For example, assume as described above that the first defective column group is the i-th column group. Now, the second defective column group can be designated as the j-th column group, where j is an integer less than i and greater than or equal to 0. Thus, the (j + 1)-th column group separates the one-shift region from the two-shift region. In such a case, the (j + 1)-th I / O circuit couples to the (j - 1)-th column group, the j-th I / O circuit couples to the (j - 2)-th column group, and so on, continuing such that the first I / O circuit couples to the first redundant column group and the 0-th I / O circuit couples to the second redundant column group.
[0017] In a given bank, if there are no defective column groups, the entire multiple column groups form a no-shift region. In such a case, neither a one-shift region nor a two-shift region exists. If there is only one defective column group, the multiple column groups are divided into a no-shift region and a one-shift region, and there is no two-shift region. If there are two (non-consecutive) defective column groups, the multiple column groups are divided into a no-shift region, a one-shift region, and a two-shift region. A memory having two consecutive defective column groups can be divided into a no-shift region and a two-shift region (there is no one-shift region).
[0018] To identify defective column groups, the memory can be tested during manufacturing or the like. The memory may be an embedded memory in a system such as a system on a chip (SoC). Thus, the addresses of the defective column groups can be stored in a read-only memory within the SoC, such as an array of fuses. During normal operation of the SoC, one of the plurality of column groups in the memory is addressed for a read or write operation. Thus, there are three possibilities: 1) the addressed column group is within the non-shifted region, 2) the addressed column group is within the one-shift region, and 3) the addressed column group is within the two-shift region. To determine which of these three possibilities exists for the addressed column group, each I / O circuit includes a redundant decoder. For the sake of brevity, each redundant decoder is simply referred to as a decoder in the following description.
[0019] An exemplary memory bank 100 having this improved double redundancy is shown in FIG. 1. The memory bank 100 includes 16 column groups arranged from column group 15 to column group 0. Each column group includes a core including bit line pair(s) (not shown) and bit cells. Since there are 16 column groups, 16 I / O circuits are also arranged from the 15th I / O circuit 125 to the 0th I / O circuit 126. In the non-shifted state, the 16 I / O circuits are coupled one-to-one with a default one of the 16 column groups. For example, the 15th I / O circuit 125 is coupled to the 15th column group, while the 0th I / O circuit 126 is coupled to the 0th column group. Each I / O circuit is coupled to the core of the column group via a local data path (LDP). For example, the 15th I / O circuit 125 can be coupled to the core 120 via the LDP 130 of the 15th column group. The local data path of each column group may include a write multiplexer and a read multiplexer (not shown), as further described herein.
[0020] In memory bank 100, the 11th column group has a first defect 135. Thus, the 11th column group is the first defective column group within memory bank 100. As further described herein, thus, each I / O circuit from the 11th column group to the 0th column group will be in either the 1-shift region 110 or the 2-shift region 115. The 15th column group to the 12th column group is in the non-shift region 105. If the 11th column group were the only defective column group within memory bank 100, the 1-shift region 110 would extend from the 11th column group to the 0th column group. However, memory bank 100 has a second defect 140 in the 7th column. Thus, the 7th column group is the second defective column group within memory bank 100. Thus, the 1-shift region 110 ends at the 9th column group. The 2-shift region 115 extends from the 8th column group to the 0th column group.
[0021] In the non-shift region 105, each I / O circuit couples to the local data path and core within the I / O circuit's default column group. Thus, for example, the 15th I / O circuit 125 couples to the core 120 of the 15th column group via the local data path 130 within the 15th column group. The coupling for each I / O circuit is represented by arrow 140. As the name "1-shift" implies, each I / O circuit within the 1-shift region 110 does not couple to its default column group. Instead, it couples via the local data path within a column group adjacent to its default column group. For example, the 1st I / O circuit 150 couples to the core 160 of the 10th column group via the local data path 155 within the 10th column group. Similarly, each I / O circuit within the 2-shift region 115 couples via the local data path within the next column group adjacent to the column group adjacent to the I / O circuit's default column group. For example, the 7th I / O circuit 165 within the 2-shift region 115 couples to the local data path 170 within the 5th column group and to the core 175 of the 5th column group.
[0022] Due to the double shifting in the 2 - shift region 115, the I / O circuits 180 in the first column group are coupled to the cores 190 in the first redundant column group (first redundant column group, 1 st Red Col) via the local data path 185 in the first redundant column group. Similarly, the 0th I / O circuit 126 is coupled to the core 193 in the second redundant column group (second redundant column group, 2 nd Red Col) via the local data path 192 in the second redundant column group.
[0023] To enable no-shift, 1-shift, and 2-shift operations, each I / O circuit includes a switch matrix (not shown in FIG. 1) that is controlled by a plurality of redundant shift signals. In particular, each switch matrix is controlled by corresponding redundant shift signals and double redundant shift signals. For clarity of illustration, FIG. 1 shows a single redundancy shift (red_shift) signal 151, but in reality, there are 16 different redundant shift signals, one for each I / O circuit. Similarly, for clarity of illustration, FIG. 1 shows a single double red_shift signal 152, but in reality, there are 16 different double redundant shift signals, one for each I / O circuit. Thus, each I / O circuit receives the corresponding redundant shift signal 151 and double redundant shift signal 152. For further clarity of illustration, this reception of the redundant shift signal 151 by the I / O circuit is shown in FIG. 1 only for the I / O circuits for which the redundant shift signal 151 is true. Thus, only the I / O circuits within the 1-shift region 110 and 2-shift region 115 are shown to receive the redundant shift signal 151. The redundant shift signal 151 is false for each I / O circuit in the no-shift region 105. For further clarity of illustration, the reception of the double redundant shift signal 152 by the I / O circuit is shown in FIG. 1 only for the I / O circuits for which the double redundant shift signal 152 is true. The double redundant shift signal 152 is true for each I / O circuit within the 2-shift region 115 except for the first column group within the 2-shift region 115 (which is the 8th column group within the memory bank 100), and is false for each I / O circuit within the no-shift region 105 and 1-shift region 110.
[0024] The I / O circuit arrangement from the 15th I / O circuit 125 to the 0th I / O circuit 126 provides the basis for what is described herein as the "immediately preceding" I / O circuit and the "immediately following" I / O circuit. Except for the 15th I / O circuit 125, each I / O circuit has an immediately preceding I / O circuit within the I / O circuit arrangement. For example, the 12th I / O circuit 149 is the immediately preceding I / O circuit to the 11th I / O circuit 150. More generally, the ith I / O circuit is the immediately preceding I / O circuit to the (i - 1)th I / O circuit, where i is a positive integer. Except for the 0th I / O circuit 126, each I / O circuit has an immediately following I / O circuit within the I / O circuit arrangement. For example, the 11th I / O circuit 150 is the immediately following I / O circuit to the 12th I / O circuit 149. More generally, the (i - 1)th I / O circuit is the immediately following I / O circuit to the ith I / O circuit, where i is also a positive integer. Note that this configuration is arbitrary and could be reversed in an alternative implementation adjacent to the 15th column group, as opposed to two redundant column groups being adjacent to the 0th column group. In such an alternative implementation, the 0th column is the first column and the 15th column is the last column.
[0025] This definition of the immediately preceding I / O circuit and the immediately following I / O circuit, as a result, provides the basis for the definition of what is described herein as the "feedback" signal and the "feedforward" signal. The feedback signal propagates from a given I / O circuit to the immediately preceding I / O circuit. Conversely, the feedforward signal propagates from a given I / O circuit to the immediately following I / O circuit.
[0026] As described above, the term "column group" encompasses a local data path and an associated core consisting of multiplexed bit line pair(s) and bit cells. For example, in the "MUX2" implementation of memory array 100, each of the column groups includes both even and odd bit line pairs. Thus, in such an implementation, each I / O circuit couples to either the even or odd bit line pair in response to a column address specification. More generally, each column group may include a plurality of multiplexed bit line pairs that depend on the dimension or size of column multiplexing. A portion 200 of the MUX2 implementation of memory bank 100 is shown in FIG. 2. For clarity of illustration, portion 200 includes a first column group (1 st column group, Col 1), a zeroth column group, a first redundant column group, 1 st red column), and a second redundant column group, 2 ndincludes only the (red column). The I / O circuit 180 is the default I / O circuit for the first column group. Similarly, the 0th I / O circuit 126 is the default I / O circuit for the 0th column group. Each of the first column group, the 0th column group, the first redundant column group, and the second redundant column group includes both even bit line pairs and odd bit line pairs. Each even bit line pair and odd bit line pair is formed by a bit line bl and a complementary bit line blb. Each bit line pair is coupled to a plurality of bit cells arranged in a row. For clarity of illustration, only one bit cell is shown for each bit line pair. For example, the even bit line pair within the first column group is coupled to the bit cell 215. The bit line pairs and bit cells for each column group form the core 120 (FIG. 1) of the column group. For clarity of illustration, the local data path within each column group is represented only by the write multiplexer and the write driver, but it will be understood that the corresponding read multiplexer and sense amplifier are also included in such an MUX2 implementation form. Thus, the first column group includes the write driver 210-1 and the write multiplexer 205-1, the 0th column group includes the write driver 210-2 and the write multiplexer 205-2, the first redundant column group includes the write driver 210-3 and the write multiplexer 205-3, and the second redundant column group includes the write driver 210-4 and the write multiplexer 205-4. In response to the data input signal during the write operation, each write driver controls the binary state (true or false) of the write driver (wd) signal and the complementary write driver (wdb) signal to the corresponding write multiplexer. Thus, depending on whether the even bit line pair or the odd bit line pair is selected, each write multiplexer drives the appropriate bit line pair accordingly.
[0027] Thus, when there is no error in such an implementation form, the first column group and the second column group will be within the non-shift area. In this case, during the write operation, the I / O circuit 180 responds to its data-in signal and accordingly couples to the write driver 210-1 within the first column group. Similarly, the 0th I / O circuit 126 responds to its data-in signal during the write operation and couples to the write driver 210-2 within the 0th column group in such a non-shift situation. In this case, neither the first redundant column group nor the second redundant column group is used.
[0028] When the first and 0th column groups are included within one shift area, the first I / O circuit 180 couples to the write driver 210-2 within the 0th column group during the write operation that addresses the first column group. Similarly, the 0th I / O circuit 126 couples to the write driver 210-3 within the first redundant column group during the write operation to the 0th column group in such a one-shift situation. Each I / O circuit includes a decoder that controls whether the I / O circuit shifts. Each decoder is shown separately from its I / O circuit in FIG. 2 for the sake of explanation. For example, the decoder 220 controls the shifting of the first I / O circuit 180. Similarly, the decoder 225 controls the shifting of the 0th I / O circuit 126.
[0029] When the first and 0th column groups are included within two shift areas, the data-in signal from the first I / O circuit 180 couples to the write driver 210-3 within the first redundant column group during the write operation to the first column group. Similarly, the data-in signal from the 0th I / O circuit 126 couples to the write driver 210-4 within the second redundant column group during the write operation to the 0th column group. Here, an exemplary switch matrix for each I / O circuit will be described.
[0030] Exemplary Switch Matrix To perform a selection between no shift, single redundant shift, and dual redundant shift within each I / O circuit, each I / O circuit includes a switch matrix. As used herein, a "switch matrix" is considered to include a plurality of switches. An exemplary portion 300 of a memory bank including the i-th column group 301, the (i - 1)-th column group 303, and the (i - 2)-th column group 304 is shown in FIG. 3, where i is a positive integer. In the default state (no column group error and thus no shifting), the i-th switch matrix 305 couples the i-th I / O (io) signal to a (not shown) core within the i-th column group 301. Similarly, the (i - 1)-th switch matrix 310 couples the (i - 1)-th io signal to the (i - 1)-th column group 303 when no error exists. Each switch matrix is controlled by a corresponding decoder. For example, the i-th decoder 315 controls the i-th switch matrix 305. Similarly, the (i - 1)-th decoder 320 controls the (i - 1)-th switch matrix 310. Each combination of decoder and switch matrix is part of a corresponding (not shown) I / O circuit. Thus, the i-th I / O circuit includes the i-th switch matrix 305 and the i-th decoder 315. Similarly, the (i - 1)-th I / O circuit includes the (i - 1)-th switch matrix 310 and the (i - 1)-th decoder 320.
[0031] Referring again to memory bank 100, it will be appreciated that the redundant shift signal 151 and the double redundant shift signal 152 are shown in a simplified form in that each I / O circuit is controlled by an individual redundant shift signal and a double redundant shift signal. When there are N (where N is a positive integer greater than or equal to 2) column groups, there are accordingly N redundant shift signals and N double redundant shift signals. In section 300, the i-th redundant shift signal controls the switching of switch 1B in the i-th switch matrix 305, while the i-th double redundant shift signal controls switch 2A in the i-th switch matrix 305. The (i - 1)-th redundant shift signal controls the switching of a similar switch 1B in the (i - 1)-th switch matrix 310, while the (i - 1)-th double redundant shift signal controls switch 2A in the (i - 1)-th switch matrix 310.
[0032] Switch 1B in the i-th switch matrix 305 is coupled to switch 1A in the (i - 1)-th switch matrix 310. Similarly, switch 1B in the (i - 1)-th switch matrix 310 is coupled to switch 1A in the (i - 2)-th switch matrix (not shown). The coupling between switch 1B and switch 1A in consecutive switch matrices can be regarded as a level 1 coupling. In addition, switch 2B in the i-th switch matrix 305 is coupled to switch 2A in the (i - 1)-th switch matrix 310. Similarly, switch 2B in the (i - 1)-th switch matrix 310 is coupled to switch 2A in the (i - 2)-th switch matrix (not shown). The coupling between switch 2B and switch 2A in consecutive switch matrices can be regarded as a level 2 coupling. Each switch 2B is controlled by a double redundant shift cut signal, as further described herein. For example, the i-th double redundant shift cut signal controls switch 2B in the i-th switch matrix 305. Similarly, the (i - 1)-th double redundant shift cut signal controls switch 2B in the (i - 1)-th switch matrix 310.
[0033] In each switch matrix, switch 1B is configured to close when the corresponding redundant shift signal is true. For example, switch 1B in the i-th switch matrix 305 is configured to close when the i-th redundant shift signal is true. Conversely, each switch 1A is configured to close when the complement of the corresponding redundant shift signal is true. For example, inverter 325 inverts the i-th redundant shift signal to control the switching of switch 1A in the i-th switch matrix 305. Similarly, inverter 330 inverts the (i - 1)-th redundant shift signal to control the switching of switch 1A in the (i - 1)-th switch matrix 310. Within each switch matrix, switches 1A, 1B, 2A, and 2B are coupled to each other via a central node. For example, central node 306 in the i-th switch matrix 305 integrally couples its switches 1A, 1B, 2A, and 2B. Similarly, central node 307 in the (i - 1)-th switch matrix 310 integrally couples its switches 1A, 1B, 2A, and 2B.
[0034] In each switch matrix, switch 2A is configured to close when the corresponding double redundant shift signal is true. For example, when the (i - 1)-th double redundant shift signal is true, switch 2A in the (i - 1)-th switch matrix 310 closes. Similarly, when the i-th double redundant shift signal is true, switch 2A in the i-th switch matrix 305 closes. Each switch 2B is configured to close when the complement of the corresponding double redundant shift cut signal is true. For example, when the i-th double redundant shift cut signal is false, switch 2B in the i-th switch matrix 305 closes. Conversely, when the i-th double redundant shift cut signal is true, switch 2B in the i-th switch matrix 305 opens.
[0035] Each decoder is configured to generate a corresponding binary cut signal, as further described herein. To control the corresponding shift matrix, each decoder feeds forward its redundant shift signal and its double redundant shift signal to the decoder in the immediately following I / O circuit. For example, the i-th decoder 315 feeds forward the i-th redundant shift signal and the i-th double redundant shift signal to the (i - 1)-th decoder 320. Similarly, each decoder feeds back its cut signal to the decoder in the immediately preceding I / O circuit. For example, the (i - 1)-th decoder 315 feeds back its (i - 1)-th cut signal to the i-th decoder 315.
[0036] Accordingly, each decoder may receive a cut signal from the decoder of the immediately following I / O circuit and receive a redundant shift signal and a double redundant shift signal from the decoder of the immediately preceding I / O circuit. Based on these signals and its own cut signal, the decoder then generates its redundant shift signal, its double redundant shift signal, and its double redundant shift cut signal to control the corresponding switch matrix. For example, the i-th decoder 315 receives the (i + 1)-th redundant shift signal and the (i + 1)-th double redundant shift signal from the decoder of the (i + 1)-th I / O circuit (not shown). In addition, the i-th decoder 315 receives the (i - 1)-th cut signal from the (i - 1)-th decoder 320. Based on these signals and the i-th cut signal, the i-th decoder 315 can generate the i-th redundant shift signal, the i-th double redundant shift signal, and the i-th double redundant shift cut signal.
[0037] As further described herein, each decoder can be configured using decoder logic for controlling the generation of its redundant shift signal, its double redundant shift signal, and its double redundant shift cut signal. An exemplary truth table 400 of the decoder logic in the i-th decoder 315 is shown in FIG. 4A. It will be understood that similar logic applies to the remaining decoders such as the (i - 1)-th decoder 320. When the i-th column group 301 is within the non-shifted region 105 of the memory bank 100, the non-shifted mode within the truth table 400 is active. In this non-shifted mode, the i-th cut signal, the (i + 1)-th redundant shift signal, the (i + 1)-th double redundant shift signal, and the (i - 1)-th cut signal are all false (having a binary 0 state). The decoder logic then responds in this non-shifted mode by setting all of the i-th redundant shift signal, the i-th double redundant shift signal, and the i-th double redundant shift cut signal to false. In the non-shifted mode, switch 1a is on, switch 1b is off, switch 2a is off, and switch 2b is on. Accordingly, the i-th io signal propagates to the i-th column group 301 via the switch matrix 305.
[0038] When the i-th column group 301 is instead within the one-shift region 110, the single-shift mode within the truth table 400 is active. In the single-shift mode, there are two possibilities depending on whether the i-th column group 301 is the first defective column group within the one-shift region 110 or whether the i-th column group 301 is immediately after the first defective column group. An example of the first defective column group is the 11-th column group within the memory bank 100. An example of a column group immediately after this first defective column group within the one-shift region 110 in the memory bank 100 is the 10-th column group or the 9-th column group. In both of these possibilities, the decoder logic responds by setting the i-th redundant shift signal to true and setting both the i-th double redundant shift signal and the i-th double redundant shift cut signal to false. This causes the i-th decoder 315 to be controlled such that its switch 1b is on, its switch 2a is off, and its switch 2b is on.
[0039] When the i-th column group 301 is the first defective column group within the one-shift region 110, the single-shift mode for the decoder logic in the i-th decoder 315 is designated as the "single shift (the i-th column is the first defective column)" mode in the truth table 400. In this mode, the i-th cut signal is true, but the (i + 1)-th redundant shift signal, the (i + 1)-th double redundant shift signal, and the (i - 1)-th cut signal are all false. When the i-th column group 301 is immediately after the first defective column group within the one-shift region 110, the single-shift mode for the decoder logic in the i-th decoder 315 is designated as the "single shift (the i-th column is immediately after the first defective column)" mode in the truth table 400. In this mode, the (i + 1)-th redundant shift signal is true, but the i-th cut signal, the (i + 1)-th double redundant shift signal, and the (i - 1)-th cut signal are all false. In both of these one-shift modes, the i-th io signal propagates through the i-th switch matrix 305 and couples to the (i - 1)-th column group 303.
[0040] When the i-th column group 301 is instead within the two-shift region 115, the double-shift mode within the truth table 400 is active. In the double-shift mode, there are three possibilities depending on the position of the i-th column group 301 within the two-shift region 115. In the first possibility, the i-th column group 301 is the second defective column group. An example of the second defective column group is the seventh column group within the memory bank 100. The corresponding mode within the truth table 400 is designated as the "double shift (the i-th column is the second defective column)" mode. In this mode, both the i-th cut signal and the (i + 1)-th redundant shift signal are true, but both the (i + 1)-th double redundant shift signal and the (i - 1)-th cut signal are false. The decoder logic responds to these signal states by setting all of the i-th redundant shift signal, the i-th double redundant shift signal, and the i-th double redundant cut signal to true. This causes switch 1a to be off, switch 1b to be on, switch 2a to be on, and switch 2b to be off.
[0041] In the second possibility of the double shift mode, the i-th column group 301 is the column group immediately after the second defective column group. An example of such a column group within the memory bank 100 is any one of the column groups from the 6th column group to the 0th column group. The corresponding mode in the truth table 400 is designated as the "double shift (the i-th column is immediately after the second defective column)" mode. In this mode, both the (i + 1)-th redundant shift signal and the (i + 1)-th double redundant shift signal are true, but both the i-th cut signal and the (i - 1)-th cut signal are false. The decoder logic responds to these signal states by setting all of the i-th redundant shift signal, the i-th double redundant shift signal, and the i-th double redundant shift cut signal to true. As a result, switch 1a is off, switch 1b is on, switch 2a is on, and switch 2b is off.
[0042] In the third possibility of the double shift mode, the i-th column group 301 is the column group immediately before the second defective column group. An example of such a column group within the memory bank 100 is the 8th column group. The corresponding mode in the truth table 400 is designated as the "double shift (the i-th column is immediately before the second defective column)" mode. In this mode, both the (i + 1)-th redundant shift signal and the (i - 1)-th cut signal are true, but both the i-th cut signal and the (i + 1)-th redundant shift signal are false. The decoder logic responds to these signal states by setting the i-th redundant shift signal and the i-th double redundant shift cut signal to true and setting the i-th double redundant shift signal to false. As a result, switch 1a is off, switch 1b is on, switch 2a is off, and switch 2b is off.
[0043] The truth table 400 can be implemented using various logic gates. A logic gate implementation example for the i-th decoder 315 is shown in FIG. 4B. One function of the i-th decoder 315 is to determine whether the i-th column group 301 is the first defective column group in the corresponding memory bank or the second defective column group. As described above, the test of the memory bank can be performed during manufacturing to identify the addresses of the first defective column group (if any) and the second defective column group (if any). Therefore, there is a set of pre-decoded address signals fa-1, fb-1, and fc-1 that identify the first defective column group. These pre-decoded address signals are true only for the redundant decoder corresponding to the first defective column group. However, at least one of them is false for all the remaining redundant decoders. Similarly, there is a set of pre-decoded address signals fa-2, fb-2, and fc-2 that identify the second defective column group. These pre-decoded address signals are true only for the redundant decoder corresponding to the second defective column group. However, at least one of them is false for all the remaining redundant decoders. Each decoder is configured to assert its cut signal only when a set of pre-decoded address signals fa-1, fb-1, and fc-1 or a set of pre-decoded address signals fa-1, fb-2, and fc-2 is true. For example, if the i-th column group 301 is defective, the i-th decoder 315 asserts the i-th cut signal.
[0044] In the i-th decoder 315, the first NAND gate 405 functions to decode the pre-decoded address signals fa-1, fb-1, and fc-1. The output signal of the first NAND gate 405 goes false only when the i-th column group is the first defective column group, and true otherwise. Similarly, the second NAND gate 410 functions to decode the pre-decoded address signals fa-2, fb-2, and fc-2. The output signal of the second NAND gate 410 goes false only when the i-th column group is the second defective column group, and true otherwise.
[0045] A logic gate such as the NAND gate 415 performs a NAND operation with the output signals from the NAND gates 405 and 410 to generate the i-th cut signal. The combination of NOR gates 425 that perform a NOR operation between the i-th cut signal and the (i + 1)-th redundant shift signal and whose output signal red_shft_n is inverted by the inverter 430 to generate the i-th redundant shift signal can be shown to control the binary state of the i-th redundant shift, as explained with respect to the truth table 400.
[0046] As further shown with respect to the truth table 400, the combination of the NAND gate 435, the inverter 440, the NOR gate 445, and the inverter 450 controls the binary state of the i-th double redundant shift signal. The NAND gate 435 performs a NAND operation between the i-th cut signal and the (i + 1)-th redundant shift signal to generate an output signal that is inverted by the inverter 440. The NOR gate 445 performs a NOR operation between the output signal from the inverter 440 and the (i + 1)-th double redundant shift signal to generate an output signal dred_shft_n that is inverted by the inverter 450 to generate the i-th double redundant shift signal.
[0047] In addition, as described with respect to the truth table 400, it can be shown that the combination of the NAND gate 455, the inverter 460, the NOR gate 465, and the inverter 470 controls the binary state of the i-th double redundant shift cut signal. The NAND gate 455 performs a NAND operation on the i-th redundant shift signal and the (i - 1)-th cut signal to generate an output signal that is inverted by the inverter 460. The NOR gate 465 performs a NOR operation on the output signal of the inverter 460 and the i-th double redundant shift signal to generate an output signal dred_shft_cut_n that is inverted by the inverter 470 to generate the i-th double redundant shift cut signal.
[0048] Note that the single and double column group shifting by the switch matrix disclosed herein does not affect column multiplexing in the local data path. In other words, the column redundancy disclosed herein is independent of column multiplexing, i.e., whether the column multiplexing is MUX2, MUX4, etc. Therefore, the column redundancy disclosed herein can be easily implemented in any suitable memory bank regardless of the size of the column multiplexing.
[0049] Here, some exemplary implementations of the switch matrix will be described.
[0050] Write Path Switch Matrix Referring again to the memory bank portion 300, it will be appreciated that the switch matrix may be shown in a simplified form since there may be a write switch matrix for the write path and a separate read switch matrix for the read path. A portion 500 of the memory bank showing some exemplary write path switch matrices is shown in FIG. 5. The portion 500 includes seven switch matrices for seven column groups from the Nth column group to the (N−6)th column group (where N is a positive integer greater than 6). In this exemplary implementation, each switch 1A and switch 1B is formed by a transmission gate, although other types of switches may be used. Thus, each switch matrix includes a transmission gate 1A and a transmission gate 1B. Each switch 2A and 2B is formed by a tri-state inverter, although other types of switches may be used. Thus, each switch matrix includes a tri-state inverter 2A and a tri-state inverter 2B. The tri-state control signals for the tri-state inverters 2A and 2B are not shown for clarity of illustration. The (N−1)th column group is the first defective column. Thus, the Nth column is still in the default no-shift state. The data input signal for each column group is stored in a corresponding data in (din) latch. The term "latch" is used herein generically to refer to a storage element capable of storing a binary signal.
[0051] Since the Nth column group is in the non-shifted state, its tri-state inverter 2B and transmission gate 1A are in the conducting state. The data-in signal for the Nth column group thus conducts from its din latch to the data-in (din) buffer for the Nth column group. If the (N−1)th column group is the first defective column group, each transmission gate 1A becomes non-conducting successively from the (N−1)th column group up to the (N−6)th column group. Similarly, each transmission gate 1B becomes conducting successively from the (N−1)th column group up to the (N−6)th column group.
[0052] The second defective column group is the (N−4)th column group. The cut signal for each of the defective column groups is true, while the cut signal for each of the remaining column groups is false. Since the defective column groups are the (N−1)th column group and the (N−4)th column group, only these column groups are the column groups for which the cut signal is true. If the (N−4)th column group is the second defective column group, only the (N−1)th column group and the (N−2)th column group are within one shift region. Thus, the tri-state inverter 2B and the transmission gate 1B become conducting in the switch matrix for these column groups, as described analogously for portion 300. The (N−3)th column group to the (N−6)th column group are within two shift regions. Since the (N−3)th column group is the first column group within two shift regions, the transmission gate 1A and the tri-state inverters 2A and 2B in the corresponding switch matrix become non-conducting. Starting from the second defective column group (in this example, the (N−4)th column group), each transmission gate 1B and tri-state inverter 2A become conducting so as to provide the desired dual redundant shift. Due to the inversion of the data input signal in tri-state inverter 2A or 2B, each din buffer can be configured to invert its buffered data input signal. Here, some exemplary read path switch matrices will be described.
[0053] Read path switch matrix A portion 600 of a memory bank showing some exemplary read path switch matrices is shown in FIG. 6. Portion 600 is similar to portion 500 and thus includes seven switch matrices for seven column groups starting from the Nth column group and ending at the (N−6)th column group (where N is a positive integer greater than 6). In this exemplary implementation, each switch 1A and switch 1B, although other types of switches may be used, is formed by a tri-state inverter. Thus, each switch matrix includes a tri-state inverter 1A and a tri-state inverter 1B. Each switch 2A and 2B, although other types of switches may be used, is also formed by a tri-state inverter. Thus, each switch matrix includes a tri-state inverter 2A and a tri-state inverter 2B. Tri-state control signals for tri-state inverters 1A, 1B, 2A, and 2B are not shown for clarity of illustration. The (N−1)th column group is the first defective column group. Thus, the Nth column group is still in the default no-shift state. In some implementations, the read paths for these column groups can be selected between the column groups of the first bank and the column groups of the second bank (banks are not shown for clarity of illustration).
[0054] Since the Nth column group is in the non-shifted state, the tri-state inverters 2B and 1A in the corresponding switch matrix are conductive. Therefore, the data output signal for the Nth column group conducts from the selected bank to the data out (dout) latch for the Nth column group. If the (N - 1)th column group is the first defective column group, each tri-state inverter 1A becomes non-conductive successively from the switch matrix for the (N - 1)th column group to the switch matrix for the (N - 6)th column group. Similarly, each tri-state inverter 1B becomes conductive successively from the switch matrix for the (N - 1)th column group to the switch matrix for the (N - 6)th column group.
[0055] The second defective column group is the (N - 4)th column group. The cut signal for each of the defective column groups is true, while the cut signal for each of the remaining column groups is false. Since the defective column groups are the (N - 1)th column group and the (N - 4)th column group, only these column groups are the column groups for which the cut signal is true. If the (N - 4)th column group is the second defective column group, only the (N - 1)th column group and the (N - 2)th column group are 1-shift columns. Therefore, the tri-state inverters 2B and 1B in the corresponding switch matrix become conductive for such a 1-shift state as described analogously for part 300. The (N - 3)th column group to the (N - 6)th column group are 2-shift column groups. Since the (N - 3)th column group is the first 2-shift column group, the tri-state inverter 1A and the tri-state inverters 2A and 2B in the corresponding switch matrix become non-conductive. Starting from the second defective column group (in this example, the (N - 4)th column group), each tri-state inverter 1B and tri-state inverter 2A become conductive in the corresponding switch matrix so as to provide the desired double redundancy shift.
[0056] Here, a method for the dual-redundancy shift operation of a memory will be described with reference to the flowchart of FIG. 7. The method includes an act 700 of coupling a first latch to a first column group within a plurality of consecutively arranged column groups in response to a subset of a plurality of column groups ranging from a first column group to a first column group having no defective column groups. Referring to FIG. 5, the coupling of the Nth data input latch to the Nth column group is an example of act 700. Similarly, the coupling of the Nth data output latch to the Nth column group as shown in FIG. 6 is another example of act 700. The method also includes an act 705 of coupling a first latch to a second column group consecutive to the first column group within the plurality of column groups in response to the first column group being the first defective column group within the plurality of column groups. The coupling of the (N - 1)th data input latch to the (N - 2)th column group as shown in FIG. 5 is an example of act 705. Similarly, the coupling of the (N - 1)th data output latch to the (N - 2)th column group as shown in FIG. 6 is an example of act 705. Finally, the method includes an act 710 of coupling a first latch to a third column group consecutive to the second column group within the plurality of column groups in response to the second column group being the second defective column group within the plurality of column groups. The coupling of the (N - 4)th data input latch to the (N - 6)th column group as shown in FIG. 5 is an example of act 710. Similarly, the coupling of the (N - 4)th data output latch to the (N - 6)th column group as shown in FIG. 6 is an example of act 710.
[0057] The memory disclosed herein can be incorporated into various electronic systems. For example, as shown in FIG. 8, a mobile phone 800, a laptop 805, and a tablet PC 710 can each include a memory having a dual redundancy shift according to the present disclosure. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers can also be configured using a memory constructed in accordance with the present disclosure.
[0058] Here, the present disclosure will be summarized by the following exemplary clauses. Clause 1. A memory, comprising A plurality of column groups, each column group within the plurality of column groups including a plurality of multiplexed columns, the plurality of column groups including a first column group, a second column group adjacent to the first column group, and a third column group adjacent to the second column group, A first switch matrix configured to couple a latch to one of the first column group, the second column group, and the third column group in response to a plurality of column redundancy signals, A memory. Clause 2. The first switch matrix is A first central node, A first switch coupled between the first column group and the first central node, And a second switch coupled between the first central node and the latch, the memory further comprising A first decoder configured to close the first switch and close the second switch to couple the latch to the first column group in response to the plurality of column groups having no defective column groups from the first column group to the first column group within the plurality of column groups. The memory according to Clause 1. Clause 3. The first switch matrix further comprises A third switch coupled between the first central node and the second column group, and the first decoder is further configured to open the first switch, close the second switch, and close the third switch to couple the latch to the second column group in response to the first column group being the first defective column group within the plurality of column groups. The memory according to Clause 2. Clause 4. The first decoder is further configured to open the second switch in response to the second column group being the second defective column group within the plurality of column groups, and the memory comprises A second switch matrix including a third switch coupled between the latch and a second central node and a fourth switch coupled between the second central node and the third column group, In response to the second column group being the second defective column group, a second decoder configured to close a third switch and close a fourth switch to couple a latch to a third column group; and a memory according to clause 2, further comprising: Clause 5. The memory, further comprising a first redundant column group and a second redundant column group; the memory according to any one of clauses 1 to 4. Clause 6. The memory according to any one of clauses 2 to 4, wherein the first switch comprises a transmission gate and the second switch comprises a tri-state inverter. Clause 7. A memory, comprising a plurality of column groups, each column group within the plurality of column groups including a plurality of multiplexed columns, the plurality of column groups including a first column group and a second column group adjacent to the first column group; a first latch; a second latch; a first switch coupled between the first column group and a first central node, a second switch coupled between the first central node and the second column group, a third switch coupled between the first latch and the first central node, and a fourth switch coupled between the first central node and the second latch; and a first switch matrix. A memory. Clause 8. The first switch matrix, comprising a third latch; a first redundant column group adjacent to the second column group; a second redundant column group adjacent to the first redundant column group; a first switch coupled between the second column group and a second central node, a second switch coupled between the second central node and the first redundant column group, a third switch coupled between the second latch and the second central node, and a fourth switch coupled between the second central node and the third latch; and a second switch matrix; the memory according to clause 7. Clause 9. A first decoder configured to control a first switch matrix in response to whether the first column group is within the shift-free region of a plurality of column groups, within the one-shift region of the plurality of column groups, or within the two-shift region of the plurality of column groups, where the memory is as described in either Clause 7 or 8. Clause 10. The memory according to Clause 9, wherein the first decoder is further configured to decode the address of the first column group to determine whether the first column group is in the shift-free region, the one-shift region, or the two-shift region. Clause 11. The memory according to any one of Clauses 1 to 10, wherein the memory is incorporated into a cellular phone. Clause 12. The memory according to any one of Clauses 1 to 10, wherein the memory is a static random access memory (SRAM). Clause 13. The memory according to any one of Clauses 7 to 12, wherein the first column group comprises a first plurality of bit line pairs, and the second column group comprises a second plurality of bit line pairs. Clause 14. A memory comprising: a plurality of column groups, each column group within the plurality of column groups including a plurality of multiplexed columns, the plurality of column groups including a first column group and a second column group; a first latch; a second latch; a first switch matrix coupled to the first column group, the second column group, the first latch, and the second latch; a first redundant column group including a first plurality of multiplexed redundant columns; and a second redundant column group including a second plurality of multiplexed redundant columns. The memory. Clause 15. The memory according to Clause 14, further comprising a first decoder configured to decode an address signal to control a switching state of the first switch matrix in response to a column redundancy state of the plurality of column groups. The memory according to Clause 14. Clause 16. The first switch matrix is A memory according to clause 15, comprising: a first switch coupled between a first column group and a first central node; a second switch coupled between the first central node and a second column group; a third switch coupled between a first latch and the first central node; and a fourth switch coupled between the first central node and a second latch. Clause 17. A memory according to any one of clauses 14 to 16, wherein each of a plurality of multiplexed columns comprises a plurality of multiplexed bit line pairs. Clause 18. A memory according to clause 15 or 16, wherein a first decoder includes a first logic gate configured to decode a first address signal. Clause 19. The memory according to clause 18, wherein the first decoder further includes a second logic gate configured to decode a second address signal. Clause 20. The memory according to clause 19, wherein the first logic gate and the second logic gate each comprise a NAND gate. Clause 21. A memory according to any one of clauses 14 to 20, wherein the first latch and the second latch each comprise an input latch for a write bit. Clause 22. A method of column redundancy, comprising: coupling a first latch to a first column group within a plurality of consecutively arranged column groups in response to a subset of the plurality of column groups extending from a first column group having no defective column groups to the first column group; coupling the first latch to a second column group consecutive to the first column group within the plurality of column groups in response to the first column group being a first defective column group within the plurality of column groups; coupling the first latch to a third column group consecutive to the second column group within the plurality of column groups in response to the second column group being a second defective column group within the plurality of column groups; including. Clause 23. further comprising decoding a first address to determine whether the first column group is a first defective column group within the plurality of column groups. The method according to clause 22. Clause 24. Further comprising decoding a second address to determine whether the first column group is a second defective column group within a plurality of column groups. The method according to clause 23. Clause 25. Decoding the first address includes decoding the first address in a first logic gate, and decoding the second address includes decoding the second address in a second logic gate. The method according to clause 24. Clause 26. Further comprising coupling a last latch to a last column group within the plurality of column groups in response to the plurality of column groups not having a defective column group. The method according to any one of clauses 22 to 27. Clause 27. Further comprising coupling a last latch to a first redundant column group in response to the plurality of column groups including a first defective column group and not including a second defective column group. The method according to clause 28. Clause 28. Further comprising coupling a last latch to a second redundant column group in response to the plurality of column groups including a first defective column group and a second defective column group. The method according to clause 26. Clause 29. Coupling the last latch to the second redundant column group includes coupling the last input latch to the second redundant column group. The method according to clause 28. Clause 30. Coupling the last latch to the second redundant column group includes coupling the last output latch to the second redundant column group. The method according to clause 28.
[0059] As will be understood by some of those skilled in the art, and depending on the current specific application examples, many modifications, substitutions, and variations can be made to the materials, devices, configurations, and methods of use of the devices of the present disclosure, and to those, without departing from its scope. In light of this, since the specific implementations illustrated and described herein are only some examples, the scope of the present disclosure should not be limited to the scope of such specific implementations, but rather should be fully equivalent to the scope of the claims appended hereinafter, and the scope of their functional equivalents.
Claims
1. It is memory, A plurality of column groups, wherein each column group within the plurality of column groups includes a plurality of multiplexed columns, and the plurality of column groups includes a first column group, a second column group adjacent to the first column group, and a third column group adjacent to the second column group, A first switch matrix is configured to couple a first latch to one of the first column group, the second column group, and the third column group in response to multiple column redundancy signals. Equipped with, The first switch matrix described above, The first central node, A first switch coupled between the first column group and the first central node, A second switch coupled between the first central node and the first latch and The memory is equipped with, The system further comprises a first decoder configured to close a first switch and a second switch in order to couple a first latch to a first column group, in response that the plurality of column groups do not have any defective column groups from the first column group to the first column group. Memory.
2. The first switch matrix described above, The memory according to claim 1, further comprising a third switch coupled between the first central node and the second column group, wherein the first decoder is further configured to open the first switch, close the second switch, and close the third switch in order to couple the first latch to the second column group in response to the first column group being the first defective column group among the plurality of column groups.
3. The first decoder is further configured to open the second switch in response to the second column group being the second defective column group among the plurality of column groups, and the memory is A second switch matrix comprising a third switch coupled between the first latch and the second central node, and a fourth switch coupled between the second central node and the third column group, A second decoder is configured to close the third switch and the fourth switch in order to couple the first latch to the third column group in response to the second column group being the second defective column group. The memory according to claim 2, further comprising:
4. The memory according to claim 1, wherein the first switch comprises a transmission gate and the second switch comprises a tristate inverter.
5. The first latch and, The second latch, A first switch matrix comprising: a first switch coupled between the first column group and the first central node; a third switch coupled between the first central node and the second column group; a second switch coupled between the first latch and the first central node; and a fourth switch coupled between the first central node and the second latch. The memory according to claim 1, comprising:
6. The second column group is the last column group among the plurality of column groups, and the memory is The third latch, The first redundant column group adjacent to the second column group, A second redundant column group adjacent to the first redundant column group, A second switch matrix comprising: a first switch coupled between the second column group and the second central node; a second switch coupled between the second central node and the first redundant column group; a third switch coupled between the second latch and the second central node; and a fourth switch coupled between the second central node and the third latch. The memory according to claim 5, further comprising:
7. The system further comprises a first decoder configured to control the first switch matrix in response to whether the first column group lies within an unshifted region of the plurality of column groups, within a one-shift region of the plurality of column groups, or within a two-shift region of the plurality of column groups. The first decoder is further configured to decode the address of the first column group in order to determine whether the first column group is in the unshifted region, the one-shifted region, or the two-shifted region. The memory according to claim 5.
8. The memory according to claim 5, wherein the memory is included in a cellular phone and the memory is a static random access memory (SRAM).
9. The memory according to claim 5, wherein the first column group comprises a first plurality of bit line pairs, and the second column group comprises a second plurality of bit line pairs.
10. A method for column redundancy in memory, The steps of coupling a first latch to the first column group within a plurality of column groups in response to a subset of column groups ranging from the first column group that does not have a defective column group to the first column group, In response to the step that the first column group is a first defective column group within the plurality of column groups, the first latch is coupled to a second column group adjacent to the first column group within the plurality of column groups. Steps of coupling the first latch to a third column group in the plurality of column groups in response that the second column group is a second defective column group in the plurality of column groups, wherein the third column group is adjacent to the second column group. Includes, The first switch matrix of the memory is configured to couple a first latch to one of the first column group, the second column group, and the third column group in response to a plurality of column redundancy signals. The first switch matrix described above, The first central node, A first switch coupled between the first column group and the first central node, A second switch coupled between the first central node and the first latch and The memory is equipped with, The system further comprises a first decoder configured to close a first switch and a second switch in order to couple a first latch to a first column group, in response that the plurality of column groups do not have any defective column groups from the first column group to the first column group. method.
11. The steps include decoding a first address in order to determine whether the first column group is the first defective column group among the plurality of column groups, The steps include: Decoding a second address in order to determine whether the first column group is the second defective column group among the plurality of column groups; The method according to claim 10, further comprising:
12. The method according to claim 11, wherein the step of decoding the first address includes the step of decoding the first address in a first logic gate, and the step of decoding the second address includes the step of decoding the second address in a second logic gate.
13. The method according to claim 11, further comprising the step of coupling the last latch to the last column group in the plurality of column groups in response that the plurality of column groups do not have any defective column groups.
14. The method according to claim 13, further comprising the step of coupling the last latch to the first redundant column group in response that the plurality of column groups include the first defective column group and do not include the second defective column group.
15. The step of coupling the last latch to the second redundant column group in response to the step in which the plurality of column groups include the first defective column group and the second defective column group, The step of joining the last latch to the second redundant column group includes the step of joining the last input latch to the second redundant column group, The step of joining the last latch to the second redundant column group includes the step of joining the last output latch to the second redundant column group. The method according to claim 13.