Chip Structure and Its Manufacturing Method, Display Substrate, and Display Device

Abstract

A chip structure (10), the chip structure (10) comprising a chip wafer unit (11) and a color conversion layer unit (21) installed on the light emitting side (G) of the chip wafer unit (11), the chip wafer unit (11) including a plurality of sub-pixel light emitting functional layers (12, 12a, 12b, 12c), and the color conversion layer unit (21) including color conversion layers (22, 22a, 22b, 22c) installed on the light emitting side (G) of the chip wafer unit (11). The chip structure (10) further comprises bonding layers (13, 131, 133, 132), the bonding layers being provided between the chip wafer unit (11) and the color conversion layer unit (21) and used for bonding the chip wafer unit (11) and the color conversion layer unit (21).

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a chip structure and a manufacturing method thereof, a display substrate, and a display device.

Background Art

[0002] Micro-LED (micro light-emitting diode) display devices are a new generation of display technologies, having advantages such as high brightness, high luminous efficiency, low power consumption, and high response speed. However, when applying Micro-LEDs to display devices, problems such as material movement and product yield still exist.

Summary of the Invention

Means for Solving the Problems

[0003] In one aspect, a chip structure is provided. The chip structure includes a chip wafer unit and a color conversion layer unit disposed on the light-emitting side of the chip wafer unit. The chip wafer unit includes a plurality of sub-pixel light-emitting functional layers, and the color conversion layer unit includes a color conversion layer disposed on the light-emitting side of the chip wafer unit. The chip structure further includes a bonding layer provided between the chip wafer unit and the color conversion layer unit and used for bonding the chip wafer unit and the color conversion layer unit.

[0004] In some embodiments, the bonding layer is any one of an indium zinc oxide bonding layer, a metal bonding layer, and an adhesive layer.

[0005] In some embodiments, the dimension of the bonding layer in a first direction is smaller than the interval between two adjacent sub-pixel light-emitting functional layers among the plurality of sub-pixel light-emitting functional layers. The first direction is the direction pointing from the chip wafer unit to the color conversion layer unit.

[0006] In some embodiments, the bonding layer is the indium zinc oxide bonding layer, and the dimension range of the indium zinc oxide bonding layer in the first direction is 100 nm to 300 nm. Alternatively, the bonding layer is the metal bonding layer, and the dimension range of the metal bonding layer in the first direction is 6 μm to 12 μm. Alternatively, the bonding layer is the adhesive layer, and the dimension range of the adhesive layer in the first direction is 5 μm to 10 μm.

[0007] In some embodiments, the bonding layer is the indium zinc oxide bonding layer, and the indium zinc oxide bonding layer includes a first indium zinc oxide layer and a second indium zinc oxide layer that are stacked and installed along the first direction, and the first indium zinc oxide layer and the second indium zinc oxide layer are connected by the action of molecular bonding. Alternatively, the bonding layer is the metal bonding layer, and the metal bonding layer includes a first sub-metal layer, a second sub-metal layer, and a third sub-metal layer that are stacked and installed along the first direction, and the second sub-metal layer is installed as a eutectic alloy layer that connects the first sub-metal layer and the third sub-metal layer. The first direction is the direction pointing from the chip wafer unit to the color conversion layer unit.

[0008] In some embodiments, the bonding layer is the indium zinc oxide bonding layer, and the projection of the indium zinc oxide bonding layer on the plurality of sub-pixel light-emitting functional layers covers the plurality of sub-pixel light-emitting functional layers. Alternatively, the bonding layer is the metal bonding layer, and an opening region corresponding to the plurality of sub-pixel light-emitting functional layers is provided in the metal bonding layer. Alternatively, the bonding layer is the adhesive layer, and the projection of the adhesive layer on the plurality of sub-pixel light-emitting functional layers covers the plurality of sub-pixel light-emitting functional layers.

[0009] In some embodiments, the chip structure further includes a first base, the first base is disposed on a side away from the chip wafer unit of the color conversion layer unit, and a projection of the first base of the color conversion layer unit covers a projection of the first base of the bonding layer. The range of the distance between the projection boundary of the first base of the color conversion layer unit and the projection boundary of the first base of the bonding layer is 0 μm to 10 μm.

[0010] In some embodiments, each of the plurality of sub-pixel light-emitting functional layers includes an anode electrode, a current diffusion layer, a p-type gallium nitride layer, and a quantum well layer that are stacked and disposed along a first direction. The chip wafer unit further includes a common cathode layer, and the common cathode layer includes a cathode electrode and a cathode metal layer that are stacked and disposed along a first direction. The cathode metal layer further includes a portion located between two adjacent sub-pixel light-emitting functional layers, and the first direction is a direction pointing from the chip wafer unit to the color conversion layer unit.

[0011] In some embodiments, there is a gap between a portion of the cathode metal layer located between two adjacent sub-pixel light-emitting functional layers and the two sub-pixel light-emitting functional layers. The range of the gap between the sub-pixel light-emitting functional layer and the cathode metal layer is 1 / 10 to 1 / 3 of the range of the gap between two adjacent sub-pixel light-emitting functional layers.

[0012] In some embodiments, among the plurality of anode electrodes, the range of the distance between two adjacent anode electrodes is less than or equal to the range of the distance between the two sub-pixel light-emitting functional layers where the two anode electrodes are located.

[0013] In some embodiments, the chip wafer unit further includes an n-type gallium nitride layer and a gallium nitride buffer layer that are stacked and installed along a first direction, and the n-type gallium nitride layer is installed on a light-emitting side of the plurality of sub-pixel light-emitting functional layers. The bonding layer is installed on a side of the gallium nitride buffer layer away from the n-type gallium nitride layer, and the first direction is a direction pointing from the chip wafer unit to the color conversion layer unit.

[0014] In some embodiments, the plurality of sub-pixel light-emitting functional layers include a first sub-pixel light-emitting functional layer, a second sub-pixel light-emitting functional layer, and a third sub-pixel light-emitting functional layer. The chip structure further includes a first base, and the color conversion layer unit includes a color film layer installed on one side of the first base. The color film layer includes a black matrix layer and a plurality of filter film layers defined by the black matrix layer. The plurality of filter film layers include a first filter film layer, a second filter film layer, and a third filter film layer. The first filter film layer is installed corresponding to the first sub-pixel light-emitting functional layer, the second filter film layer is installed corresponding to the second sub-pixel light-emitting functional layer, and the third filter film layer is installed corresponding to the third sub-pixel light-emitting functional layer.

[0015] The color conversion layer unit further includes a limiting dam layer installed on a side of the color film layer away from the first base. The limiting dam layer is provided with a plurality of opening regions. The plurality of opening regions include a first opening region, a second opening region, and a third opening region. The first opening region is provided corresponding to the first sub-pixel light-emitting functional layer, the second opening region is provided corresponding to the second sub-pixel light-emitting functional layer, and the third opening region is provided corresponding to the third sub-pixel light-emitting functional layer.

[0016] The color conversion layer further includes a first quantum dot conversion part, a second quantum dot conversion part, and a scattering particle part. The first quantum dot conversion part is installed in the first opening region, the scattering particle part is installed in the second opening region, and the second quantum dot conversion part is installed in the third opening region.

[0017] In some embodiments, the projection of the filter film layer on the first base covers the projection of the sub-pixel light-emitting functional layer corresponding to the filter film layer on the first base. The projection of the quantum dot conversion part on the first base covers the projection of the filter film layer corresponding to the quantum dot conversion part on the first base. The projection of the scattering particle part on the first base covers the projection of the second filter film layer on the first base.

[0018] In some embodiments, the range of the distance between the projection boundary of the filter film layer on the first base and the projection boundary of the sub-pixel light-emitting functional layer corresponding to the filter film layer on the first base is 20 μm to 60 μm. The range of the distance between the projection boundary of the quantum dot conversion part on the first base and the projection boundary of the filter film layer corresponding to the quantum dot conversion part on the first base is 23 μm to 68 μm. The range of the distance between the projection boundary of the scattering particle part on the first base and the projection boundary of the second filter film layer on the first base is 23 μm to 68 μm.

[0019] In some embodiments, the range of the dimension of the limiting dam layer in the first direction is 10 μm to 30 μm. The first direction is the direction pointing from the chip wafer unit to the color conversion layer unit.

[0020] In another aspect, a method for manufacturing a chip structure is provided. The method for manufacturing a chip structure includes: forming an initial chip wafer unit, where the initial chip wafer unit includes a temporary base, a plurality of sub-pixel light-emitting functional layers, an n-type gallium nitride layer, and a gallium nitride buffer layer that are stacked and installed; forming a color conversion layer unit, where the color conversion layer unit is formed on one side of the initial first base; and bonding the color conversion layer unit to the light-emitting side of the initial chip wafer unit to form a chip wafer unit and a color conversion layer unit, thereby obtaining a chip structure.

[0021] In some embodiments, the step of bonding the color conversion layer unit to the light emitting side of the initial chip wafer unit includes forming a first indium zinc oxide layer on the side away from the temporary base of the initial chip wafer unit, forming a second indium zinc oxide layer on the side away from the initial first base of the color conversion layer unit, and bonding the first indium zinc oxide layer and the second indium zinc oxide layer to form a bonding layer connecting the initial chip wafer unit and the color conversion layer unit.

[0022] In some embodiments, the step of bonding the color conversion layer unit to the light emitting side of the initial chip wafer unit is to form a first initial sub-metal layer and a second initial sub-metal layer on the side away from the temporary base of the initial chip wafer unit, wherein the second initial sub-metal layer is a plurality of first metalloid bumps formed on the side away from the temporary base of the first initial sub-metal layer, forming a third initial sub-metal layer on the side away from the initial first base of the color conversion layer unit, and bonding the first initial sub-metal layer, the second initial sub-metal layer and the third initial sub-metal layer to form a bonding layer connecting the initial chip wafer unit and the color conversion layer unit.

[0023] In some embodiments, the step of bonding the color conversion layer unit to the light emitting side of the initial chip wafer unit includes connecting the initial chip wafer unit and the color conversion layer unit using an adhesive.

[0024] In some embodiments, the step of bonding the first indium zinc oxide layer and the second indium zinc oxide layer includes treating the surface of the first indium zinc oxide layer away from the temporary base with oxygen plasma, treating the surface of the second indium zinc oxide layer away from the initial first base with oxygen plasma, and pressing and bonding the first indium zinc oxide layer and the second indium zinc oxide layer under a temperature condition of 150°C to 240°C to form a bonding layer.

[0025] In some embodiments, after bonding the color conversion layer unit to the light emitting side of the initial chip wafer unit, the manufacturing method includes removing the temporary base to form a chip wafer unit, and thinning the thickness of the initial first base to form a first base to obtain a chip structure.

[0026] In another aspect, a display substrate is provided. The display substrate includes the chip structure according to any one of the above embodiments.

[0027] In yet another aspect, a display device is provided. The display device includes the above display substrate.

Brief Description of the Drawings

[0028] Hereinafter, in order to more clearly illustrate the technical solutions according to the present disclosure, the drawings used in some embodiments of the present disclosure will be briefly described. However, it is obvious that the drawings in the following description are only some of the drawings of some embodiments of the present disclosure. Those skilled in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and do not limit the actual dimensions of the products according to the embodiments of the present disclosure, the actual flow of the method, the actual timing of the signals, etc.

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BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Hereinafter, with reference to the drawings, some embodiments of the present disclosure will be clearly and completely described. Of course, the embodiments described herein are only a part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art shall be included within the protection scope of the present disclosure.

[0030] Unless otherwise indicated in the context, in this specification and the claims, the term "comprise" and its other forms, such as the third-person singular form "comprises" and the present participle form "comprising", should be interpreted in an open, inclusive sense, that is, "including but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example", or "some examples", etc. are intended to indicate that a particular feature, structure, material, or property related to this embodiment or its example is included in at least one embodiment or example of the present disclosure. The schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described particular features, structures, materials, or properties may be included in any one or more embodiments or examples in any suitable manner.

[0031] Hereinafter, the terms "first" and "second" are for illustrative purposes only and should not be construed as indicating or implying relative importance or indicating the quantity of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the embodiments of the present disclosure, unless otherwise specified, "a plurality" means two or more.

[0032] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0033] "A and / or B" includes three combinations: only A, only B, and the combination of A and B.

[0034] As used herein, "parallel", "perpendicular", and "equal" include the described situations and situations similar to the described situations, and the range of these similar situations is within an acceptable deviation range, and the acceptable deviation range is determined in consideration of the errors related to the measurements being considered by those skilled in the art and the measurements of specific quantities (i.e., the limitations of the measurement system). For example, "parallel" includes true parallel and substantially parallel, where the acceptable deviation range for substantially parallel is, for example, a deviation within 5°, "perpendicular" includes true perpendicular and substantially perpendicular, where the acceptable deviation range for substantially perpendicular may be, for example, a deviation within 5°. "Equal" includes absolutely equal and approximately equal, and within the acceptable deviation range of approximately equal, for example, the difference between the two equal ones is 5% or less of either.

[0035] When a layer or element is referred to as being on another layer or substrate, it is understood that the layer or element may be directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.

[0036] In this specification, exemplary embodiments are described with reference to cross-sectional views and / or plan views which are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are enlarged for clarity. Thus, variations in shape with respect to the drawings, such as those due to manufacturing techniques and / or tolerances, can be assumed. Therefore, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather should be interpreted as including shape deviations resulting from manufacturing and the like. For example, an etching region shown as rectangular typically has curved features. Thus, the regions shown in the drawings are essentially exemplary, and their shapes are not intended to represent the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0037] Many of the current red Micro-LED (Micrometer-sized Light Emitting Diodes) are made of AlGaInP (red light semiconductor) material. At normal chip sizes, their efficiency reaches over 60%. However, when the chip size decreases to the micron level, the efficiency drops to 1% or less. Also, in the mass transfer process, the drawbacks of the AlGaInP material are obvious. Mass transfer requires the material to have good mechanical strength to avoid cracks during the handling and placement of the chips. However, the low mechanical properties of the AlGaInP material pose difficulties for mass transfer.

[0038] Based on this, the present disclosure provides a chip structure 10. As shown in FIGS. 1 to 3, the chip structure 10 includes a chip wafer unit 11 and a color conversion layer unit 21 disposed on the light-emitting side G of the chip wafer unit. Here, the chip wafer unit 11 includes a plurality of sub-pixel light-emitting functional layers 12, and the color conversion layer unit 21 includes a color conversion layer 22 disposed on the light-emitting side G of the chip wafer unit 11. The chip structure 10 further includes a bonding layer 13 disposed between the chip wafer unit 11 and the color conversion layer unit 21 and used to bond the chip wafer unit 11 and the color conversion layer unit 21 together.

[0039] In some examples, as shown in FIGS. 1 to 3, one sub-pixel light-emitting functional layer 12 among the plurality of sub-pixel light-emitting functional layers 12 of the chip wafer unit 11 is configured to emit one of a plurality of color lights, and the plurality of sub-pixel light-emitting functional layers 12 may be configured to emit the same color light. Exemplarily, the plurality of color lights includes blue light. For example, the first sub-pixel light-emitting functional layer 12a is configured to emit blue light. The color conversion layer unit 21 is installed on the light-emitting side G of the chip wafer unit 11, and the color conversion layer unit 21 is provided with a color conversion layer 22 corresponding to the light-emitting side G of each sub-pixel light-emitting functional layer 12.

[0040] Exemplarily, the chip wafer unit 11 and the color conversion layer unit 21 are manufactured independently, and then the chip wafer unit 11 and the color conversion layer unit 21 are bonded through the bonding layer 13 to form the chip structure 10. Thereby, the transfer efficiency of the Micro-LED can be improved, the thickness of the chip can be reduced, and the manufacturing accuracy and the product yield can be improved. Here, the bonding action of the bonding layer 13 may be the action of an adhesive or a metal bonding action. Specifically, referring to the following content, it will not be repeated here.

[0041] In some embodiments, as shown in FIGS. 1 to 3, the bonding layer 13 is any one of an indium zinc oxide bonding layer 131, a metal bonding layer 132, and an adhesive layer 133.

[0042] In some examples, as shown in FIG. 1, the bonding layer 13 is an indium zinc oxide bonding layer 131, and the indium zinc oxide bonding layer 131 includes a first indium zinc oxide layer 131a and a second indium zinc oxide layer 131b that are stacked and installed along the first direction X. The first indium zinc oxide layer 131a and the second indium zinc oxide layer 131b are connected by the action of molecular bonding. The first indium zinc oxide layer 131a is installed to be stacked and connected with the chip wafer unit 11, and the second indium zinc oxide layer 131b is installed to be stacked and connected with the color conversion layer unit 21. Due to the action of molecular bonding between the first indium zinc oxide layer 131a and the second indium zinc oxide layer 131b, the bonding of the chip wafer unit 11 and the color conversion layer unit 21 is realized, thereby forming the chip structure 10. The specific manufacturing method refers to the following content and will not be repeated here.

[0043] Here, the first direction X is the direction pointing from the chip wafer unit 11 to the color conversion layer unit 21. It is understood that the first direction X is parallel to the light emission direction of the chip wafer unit 11.

[0044] The first indium zinc oxide layer 131a is stacked and installed with the chip wafer unit 11 by a photolithography process, and the second indium zinc oxide layer 131b is stacked and installed with the color conversion layer unit 21 by a photolithography process. Since the error dimensions of the formed first indium zinc oxide layer 131a and the second indium zinc oxide layer 131b are small, the formed indium zinc oxide has high accuracy in forming a film layer. By using the indium zinc oxide bonding layer 131 as the bonding layer 13, the accuracy of the formed bonding layer 13 can be improved.

[0045] In some examples, as shown in FIG. 1, the range of the dimension d1 of the indium zinc oxide bonding layer 131 in the first direction X is 100 nm to 300 nm.

[0046] Exemplarily, the dimension d1 of the indium zinc oxide bonding layer 131 in the first direction X is, for example, 100 nm, 150 nm, 200 nm, 250 nm, or 250 nm, etc., and is not limited herein. It is understood that the dimension d1 of the indium zinc oxide bonding layer 131 in the first direction X is the film thickness of the indium zinc oxide bonding layer 131. If the thickness of the indium zinc oxide bonding layer 131 is less than 100 nm, the indium zinc oxide bonding layer 131 cannot have a relatively stable bonding effect. If the thickness of the indium zinc oxide bonding layer 131 is too thick, the thickness of the chip structure 10 increases. By setting the thickness of the indium zinc oxide bonding layer 131 to be 100 nm to 300 nm, the bonding of the chip wafer unit 11 and the color conversion layer unit 21 can be realized better.

[0047] In some examples, as shown in FIG. 2, the bonding layer 13 is an adhesive layer 133. Exemplarily, the material of the adhesive layer 133 is an epoxy resin-based organic adhesive material. Due to the bonding effect of the adhesive layer 133, the bonding of the chip wafer unit 11 and the color conversion layer unit 21 is realized, thereby forming the chip structure 10. The specific manufacturing method is referred to the following content and will not be repeated herein.

[0048] In some examples, as shown in FIG. 2, the range of the dimension d2 of the adhesive layer 133 in the first direction X is 5 μm to 10 μm.

[0049] Exemplarily, the dimension d2 of the adhesive layer 133 in the first direction may be, for example, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm, etc., and is not limited herein.

[0050] In some examples, as shown in FIG. 3, the bonding layer 13 is a metal bonding layer 132. The metal bonding layer 132 includes a first sub-metal layer 132a, a second sub-metal layer 132b, and a third sub-metal layer 132c that are laminated and installed along the first direction X. The second sub-metal layer 132b is installed as a eutectic alloy layer that connects the first sub-metal layer 132a and the third sub-metal layer 132c.

[0051] The first sub-metal layer 132a is installed to be laminated and connected with the chip wafer unit 11, and the third sub-metal layer 132c is installed to be laminated and connected with the color conversion layer unit 21. The eutectic alloy layer (the second sub-metal layer 132b) realizes the connection between the first sub-metal layer 132a and the third sub-metal layer 132c, realizes the bonding between the chip wafer unit 11 and the color conversion layer unit 21, and forms the chip structure 10. For the specific manufacturing method, refer to the following content and it will not be repeated here.

[0052] In some examples, as shown in FIG. 3, the range of the dimension d3 of the metal bonding layer 132 in the first direction X is 6 μm to 12 μm.

[0053] Exemplarily, the dimension d3 of the metal bonding layer 132 in the first direction X is 6 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, etc., and is not limited here.

[0054] In some examples, the manufacturing method of the chip structure 10 includes manufacturing the initial chip wafer unit 110 and the color conversion layer unit 21, then forming the bonding layer 13, bonding the initial chip wafer unit 110 and the color conversion layer unit to obtain the chip wafer unit 11, and forming the chip structure 10. To more clearly explain this technical solution, three embodiments are provided below to explain the manufacturing method of the chip structure 10.

[0055] Note that to clearly explain the manufacturing method of the chip structure 10, hereinafter, the formation of one chip structure 10 is taken as an example for explanation. It is understood that the manufacturing method of the chip structure 10 first forms a wafer 101 including a plurality of chip structures 10 arranged in an array, and then cuts the wafer 101 to form a single chip structure 10. The structure of the wafer 101 is as shown in FIG. 4.

[0056] Hereinafter, a first embodiment of a method for manufacturing the chip structure 10 will be described. According to this embodiment, a chip structure 10 as shown in FIG. 1 is formed. Note that in the steps of manufacturing the chip structure 10, a structural example of the chip structure 10 can be understood with reference to the content shown in FIG. 1 and the step diagrams.

[0057] Example 1

[0058] Specifically, as shown in FIG. 5, the manufacturing steps of the initial chip wafer unit 110 include S101 to S108.

[0059] S101, as shown in FIG. 6, an initial gallium nitride buffer layer 150, an initial n-type gallium nitride layer 160, an initial quantum well layer 1210, and an initial P-type gallium nitride layer 1220 are sequentially formed on one side of the second base 14.

[0060] Exemplarily, the second base 14 may be any of a sapphire base and a silicon-based base.

[0061] Exemplarily, the initial quantum well layer 1210 may be a blue quantum well layer, and a sub-pixel light-emitting functional layer 12 (not shown, refer to FIG. 1) formed by the blue quantum well layer emits blue light.

[0062] S102, as shown in FIGS. 7A and 7B, pattern the initial P-type gallium nitride layer 1220 and the initial quantum well layer 1210, and pattern the initial n-type gallium nitride layer 160 and the initial gallium nitride buffer layer 150. Obtain a P-type gallium nitride layer 122, a quantum well layer 121, an n-type gallium nitride layer 16, and a gallium nitride buffer layer 15.

[0063] Exemplarily, by a photolithography process, pattern the initial quantum well layer 1210 and the initial P-type gallium nitride layer 1220, and remove the initial quantum well layer 1210 and the initial P-type gallium nitride layer 1220 in the regions between adjacent sub-pixel light-emitting functional layers 12 and in the negative electrode region S17.

[0064] For example, as shown in FIGS. 7A and 7B, the initial chip wafer unit 110 includes three sub-pixel regions S1 and one negative electrode region S17. The three sub-pixel regions S1 are the first sub-pixel region S11, the second sub-pixel region S12, and the third sub-pixel region S13, respectively. By means of a photolithography process, the initial quantum well layer 1210 and the initial P-type gallium nitride layer 1220 are patterned, and the initial quantum well layer 1210 and the initial P-type gallium nitride layer 1220 in regions other than the three sub-pixel regions S1 and the negative electrode region S17 are removed. It is understood that the three sub-pixel regions S1 are the light-emitting regions of the chip structure 10. That is, the sub-pixel region S1 and the negative electrode region S17 are simultaneously the sub-pixel region S1 and the negative electrode region S17 of the chip structure 10.

[0065] The plurality of sub-pixel light-emitting functional layers 12 of the chip wafer unit 11 include a first sub-pixel light-emitting functional layer 12a, a second sub-pixel light-emitting functional layer 12b, and a third sub-pixel light-emitting functional layer 12c. The first sub-pixel light-emitting functional layer 12a is located in the first sub-pixel region S11, the second sub-pixel light-emitting functional layer 12b is located in the second sub-pixel region S12, and the third sub-pixel light-emitting functional layer 12c is located in the third sub-pixel region S13. The negative electrode region S17 is used to form the common cathode layer 17. For a specific description of the common cathode layer 17, refer to the following content and will not be repeated here.

[0066] As shown in FIGS. 7A and 7B, in this step, the first quantum well layer 121a and the first p-type gallium nitride layer 122a of the first sub-pixel light-emitting functional layer 12a, the second quantum well layer and the second p-type gallium nitride layer of the second sub-pixel light-emitting functional layer 12b, and the third quantum well layer and the third p-type gallium nitride layer of the third sub-pixel light-emitting functional layer 12c are formed. Here, FIG. 7A is a cross-sectional view obtained along the AA cross-section line of FIG. 7B.

[0067] Exemplarily, using a photolithography process, the initial n-type gallium nitride layer 160 and the initial gallium nitride buffer layer 150 are patterned to form the n-type gallium nitride layer 16 and the gallium nitride buffer layer 15. Here, the n-type gallium nitride layer 16 is a conductive layer connecting the first sub-pixel light-emitting functional layer 12a, the second sub-pixel light-emitting functional layer 12b, the third sub-pixel light-emitting functional layer 12c, and the common cathode layer 17.

[0068] S103, as shown in FIG. 8, form the current diffusion layer 125.

[0069] Exemplarily, first, an initial current diffusion layer is formed, and the initial current diffusion layer is patterned by a photolithography process to form the current diffusion layer 125. The current diffusion layer 125 includes a first current diffusion layer 125a located in the first sub-pixel region S11, a second current diffusion layer located in the second sub-pixel region S12 (not shown, refer to FIG. 7B), and a third current diffusion layer located in the third sub-pixel region S13 (not shown, refer to FIG. 7B).

[0070] The material of the current diffusion layer 125 uses ITO (indium tin oxide). Installing the current diffusion layer 125 in the sub-pixel region S1 is advantageous for hole transport and improves the electrical performance of the chip structure 10.

[0071] In some examples, as shown in FIG. 9, the manufacturing method of the initial chip wafer unit 110 further includes the step of forming a reflective metal layer 123.

[0072] Exemplarily, an initial reflective metal layer is formed on the side away from the second base 14 of the current diffusion layer 125, and the initial reflective metal layer is patterned by a photolithography process to form the reflective metal layer 123 of each sub-pixel light-emitting functional layer 12. The reflective metal layer 123 has the function of reflecting light rays and can improve the light extraction efficiency of the sub-pixel light-emitting functional layer 12.

[0073] Note that in the following exemplary drawings, the reflective metal layer 123 is not shown.

[0074] S104. As shown in FIGS. 10A and 10B, a cathode metal layer 17a is formed. Here, FIG. 10A is a cross-sectional view obtained along the BB cross-sectional line of FIG. 10B.

[0075] Exemplarily, the cathode metal layer 17a is formed by a photolithography process.

[0076] Exemplarily, the material of the cathode metal layer 17a may be any one of titanium, aluminum, nickel, and gold.

[0077] Exemplarily, as shown in FIG. 10B, the cathode metal layer 17a includes a first portion S17c covering the negative electrode region S17 and a second portion S17b located between the sub-pixel light-emitting functional layer 12 adjacent to the common cathode layer 17.

[0078] As shown in FIG. 10B, the cathode metal layer 17a further includes a portion located between two adjacent sub-pixel light-emitting functional layers 12. The cathode metal layer 17a has a function of connecting the n-type gallium nitride layer 16 and the raised cathode electrode 17b (not shown, see FIG. 11A). The portion of the cathode metal layer 17a located between two adjacent sub-pixel light-emitting functional layers 12 is called a support metal layer S17a. By providing the second portion S17b of the cathode metal layer 17a between the sub-pixel light-emitting functional layer 12 adjacent to the common cathode layer 17 and providing the support metal layer S17a between the sub-pixel light-emitting functional layers 12, the chip structure 10 can be strengthened and cracking of the chip structure 10 can be prevented. On the other hand, the volume of the cathode metal layer 17a can be increased and the resistance of the chip structure 10 can be reduced.

[0079] In some examples, as shown in FIG. 10B, there is a gap d4 between the portion of the cathode metal layer 17a located between two adjacent sub-pixel light-emitting functional layers 12 and the two sub-pixel light-emitting functional layers 12. The range of the gap d4 between the sub-pixel light-emitting functional layer 12 and the cathode metal layer 17a is 1 / 10 to 1 / 3 of the range of the gap d5 between two adjacent sub-pixel light-emitting functional layers 12.

[0080] Exemplarily, the range of the distance d4 between the sub-pixel light-emitting functional layer 12 and the cathode metal layer 17a is, for example, 1 / 10, 1 / 4, or 1 / 3 of the range of the distance d5 between two adjacent sub-pixel light-emitting functional layers 12, but is not limited thereto.

[0081] By providing a support metal layer S17a between two adjacent sub-pixel light-emitting functional layers 12 and setting the range of the distance d4 between the sub-pixel light-emitting functional layer 12 and the cathode metal layer 17a to be 1 / 10 to 1 / 3 of the range of the distance d5 between two adjacent sub-pixel light-emitting functional layers 12, while ensuring the aperture ratio of the region where the sub-pixel light-emitting functional layer 12 of the chip structure 10 is located, the area of the cathode metal layer 17a can be increased. As a result, the resistance of the chip structure 10 can be reduced, cracking of the chip structure 10 can be prevented, and the stability of the chip structure 10 can be improved.

[0082] Exemplarily, as shown in FIG. 10B, the range of the distance d4 between the sub-pixel light-emitting functional layer 12 and the cathode metal layer 17a is 8 μm to 10 μm.

[0083] Exemplarily, the distance d4 between the sub-pixel light-emitting functional layer 12 and the cathode metal layer 17a is, for example, 8 μm, 9 μm, or 10 μm, but is not limited thereto.

[0084] S105. As shown in FIGS. 10A and 10B, an insulating layer 18 is formed, and a plurality of via holes H are provided in the insulating layer 18.

[0085] Exemplarily, an initial insulating layer is formed on the side of the cathode metal layer 17a away from the second base 14 by a vapor deposition process, and a plurality of via holes H are formed by a photolithography process. As shown in FIG. 10B, the plurality of via holes H include a first via hole H1, a second via hole H2, a third via hole H3, and a fourth via hole H4. The first via hole H1 is provided corresponding to the first sub-pixel light-emitting functional layer 12a, the second via hole H2 is provided corresponding to the second sub-pixel light-emitting functional layer 12b, the third via hole H3 is provided corresponding to the third sub-pixel light-emitting functional layer 12c, and the fourth via hole H4 is provided corresponding to the negative electrode region S17.

[0086] S106. As shown in FIGS. 11A and 11B, an electrode 19 is formed. The electrode 19 includes a first anode 124a, a second anode 192, a third anode 193, and a cathode electrode 17b. Here, FIG. 11A is a cross-sectional view obtained along the CC cross-section line of FIG. 11B.

[0087] Here, the first anode 124a, the second anode 192, and the third anode 193 are referred to as anode electrodes.

[0088] Exemplarily, the electrode 19 is formed by a patterning process. Here, the first anode 124a is disposed corresponding to the first sub-pixel light-emitting functional layer 12a, the second anode 192 is disposed corresponding to the second sub-pixel light-emitting functional layer 12b, the third anode 193 is disposed corresponding to the third sub-pixel light-emitting functional layer 12c, and the cathode electrode 17b and the cathode metal 17a form a common cathode layer 17.

[0089] S107. As shown in FIG. 12, a temporary base 20 is bonded to the side of the electrode 19 away from the second base 14.

[0090] Exemplarily, a temporary adhesive layer 41 and an adhesive release layer 42 are used to temporarily bond the temporary base 20. The temporary adhesive layer 41 has an adhesive effect, and the adhesive release layer 42 can release the adhesion by ultraviolet irradiation. The temporary adhesive layer 41 and the adhesive release layer 42 have the function of temporarily bonding the temporary base 20.

[0091] S108. As shown in FIG. 13, the second base 14 is removed.

[0092] After removing the second base 14, an initial chip wafer unit 110 is formed.

[0093] Exemplarily, the second base 14 may be a sapphire base, and the sapphire base is peeled off by a laser.

[0094] Exemplarily, the second base 14 may be a silicon-based base. An acid-resistant film or a wax seal is used to protect the temporary base 20. The initial chip wafer unit 110 is placed in a hydrofluoric acid (HF) etching tank, and the second base 14 is removed by etching.

[0095] It is understood that, compared with the chip wafer unit 11, the temporary base 20 is installed on the side of the initial chip wafer unit 110 away from the gallium nitride buffer layer 15 of the electrode 19. The chip wafer unit 11 is obtained by removing the temporary base 20, the adhesive layer 41, and the adhesive release layer 42 on the initial chip wafer unit 110.

[0096] Hereinafter, the manufacturing steps of the color conversion layer unit 21 will be described. As shown in FIG. 14, the manufacturing steps of the color conversion layer unit 21 include steps R201 to R203.

[0097] R201, as shown in FIG. 15A, a color film layer 24 and a confinement dam layer 25 are formed on the initial first base 310.

[0098] The color film layer 24 includes a black matrix layer 23 and a plurality of filter film layers 28 defined by the black matrix layer 23. The confinement dam layer 25 is installed on the side of the initial first base 310 away from the color film layer 24.

[0099] Exemplarily, the initial first base 310 may be a glass base.

[0100] Exemplarily, methods such as coating, exposure, development, and post-baking are used to form the black matrix layer 23 and a plurality of filter film layers 28 defined by the black matrix layer 23. For example, as shown in FIG. 15B, the plurality of filter film layers 28 include a first filter film 241, a second filter film 242, and a third filter film 243. For example, the first filter film 241 is a red filter film, the second filter film 242 is a blue filter film, and the third filter film 243 is a green filter film. Here, FIG. 15A is a cross-sectional view obtained along the DD cross-section line of FIG. 15B.

[0101] Exemplarily, as shown in FIG. 15A, a limiting dam layer 25 is formed on the side away from the initial first base 310 of the black matrix layer 23 by using methods such as coating, exposure, development, and post-baking, and a plurality of opening regions K are defined in the limiting dam layer 25. For example, as shown in FIG. 15B, the plurality of opening regions K include a first opening region K1, a second opening region K2, and a third opening region K3.

[0102] R202. As shown in FIG. 16A, a color conversion layer 22 is formed.

[0103] Exemplarily, as shown in FIG. 16B, the color conversion layer 22 is created in the first opening region K1, the second opening region K2, and the third opening region K3 by using methods such as coating, exposure, development, and post-baking or an inkjet printing method. Exemplarily, the color conversion layer 22 includes a first quantum dot conversion part 22a, a scattering particle part 22b, and a third quantum dot conversion part 22c. Here, the first quantum dot conversion part 22a is formed in the first opening region K1, and the first quantum dot conversion part 22a uses a red quantum dot light-emitting material. The scattering particle part 22b is formed in the second opening region K2, and scattering particles are installed. The third quantum dot conversion part 22c is formed in the third opening region K3, and the third quantum dot conversion part 22c uses a green quantum dot light-emitting material. Here, FIG. 16A is a cross-sectional view obtained along the EE cross-section line of FIG. 16B.

[0104] R203. As shown in FIG. 17, an inorganic encapsulation layer 26 is formed.

[0105] After forming the inorganic sealing layer 26, the color conversion layer unit 21 is obtained.

[0106] Exemplarily, using a CVD (chemical vapor deposition) method, the inorganic sealing layer 26 is deposited on the side away from the initial first base 310 of the color conversion layer 22, and the inorganic sealing layer 26 covers the color conversion layer 22 and the confinement dam layer 25.

[0107] Hereinafter, the step of forming the bonding layer 13 and the step of realizing the assembly of the color conversion layer unit 21 and the initial chip wafer unit 110 through the bonding layer 13 to form the chip structure 10 will be described. As shown in FIG. 18, the above steps include steps T301 to T306.

[0108] T301, as shown in FIG. 19, a first indium zinc oxide layer 131a is formed on the side away from the temporary base 20 of the initial chip wafer unit 110.

[0109] That is, a first indium zinc oxide layer 131a is formed on the side away from the temporary base 20 of the gallium nitride buffer layer 15.

[0110] Exemplarily, the first indium zinc oxide layer 131a is formed by a photolithography process.

[0111] In the manufacturing process of the initial chip wafer unit 110, as shown in FIG. 20, a first large plate M including a plurality of initial chip wafer units 110 arranged in an array is formed simultaneously. In this step, a first indium zinc oxide layer is formed on the initial chip wafer unit 110 of the first large plate M. Next, the first large plate M is cut, for example, by performing a shaped cut, to form a plurality of first initial wafers A. As shown in FIG. 21, the first initial wafer A is circular, and the first initial wafer A includes a plurality of initial chip wafer units 110 provided with the first indium zinc oxide layer 131a. Exemplarily, the size of the first initial wafer A is 4 inches or 6 inches.

[0112] As shown in T302 and FIG. 22, a zinc indium oxide layer 131b is formed on the side away from the initial first base 310 of the color conversion layer unit 21.

[0113] That is, a zinc indium oxide layer 131b is formed on the side away from the initial first base 310 of the inorganic sealing layer 26.

[0114] Exemplarily, the zinc indium oxide layer 131b is formed by a photolithography process.

[0115] In the manufacturing process of the color conversion layer unit 21, as shown in FIG. 23, a second large plate N including a plurality of color conversion layer units 21 arranged in an array is simultaneously formed. In this step, a zinc indium oxide layer 131b is formed on the color conversion layer unit 21 of the second large plate N. Next, the second large plate N is cut, for example, by performing a shaped cutting, to form a plurality of second initial wafers B. As shown in FIG. 24, the second initial wafer B is circular, and the second initial wafer B includes a plurality of color conversion layer units 21 provided with the zinc indium oxide layer 131b. The dimensions of the second initial wafer B are the same as those of the first initial wafer A.

[0116] Hereinafter, the step of finally forming a single chip structure 10 by assembling the first initial wafer A and the second initial wafer B will be described. In the following, the formation of one chip structure 10 will be described as an example.

[0117] T303, as shown in FIG. 25, the indium zinc oxide layer 131a and the zinc indium oxide layer 131b are bonded together.

[0118] By bonding the indium zinc oxide layer 131a and the zinc indium oxide layer 131b, the bonding between the initial chip wafer unit 110 and the color conversion layer unit 21 is realized.

[0119] Exemplarily, the thickness d11 of the first indium zinc oxide layer 131a and the thickness d12 of the second indium zinc oxide layer 131b may be the same or different, and are not limited herein. The sum of the thickness d11 of the first indium zinc oxide layer 131a and the thickness d12 of the second indium zinc oxide layer 131b is the film thickness of the indium zinc oxide bonding layer 131.

[0120] Exemplarily, the step of bonding the first indium zinc oxide layer 131a and the second indium zinc oxide layer 131b includes U1 to U3.

[0121] U1, the surface of the first indium zinc oxide layer 131a on the side away from the temporary base 20 is treated with oxygen plasma to activate the surface of the first indium zinc oxide layer 131a.

[0122] U2, the surface of the second indium zinc oxide layer 131b on the side away from the initial first base 310 is treated with oxygen plasma to activate the surface of the second indium zinc oxide layer 131b.

[0123] U3, the first indium zinc oxide layer 131a and the second indium zinc oxide layer 131b are pressure-bonded under a temperature condition of 150°C to 240°C to form the bonding layer 13.

[0124] Exemplarily, first, the temperature is raised to 150°C, then a pressure of 15000 N is applied, and then the temperature is raised to 200°C at a heating rate of 10°C / min. Then, it is held for 30 minutes to form the bonding layer 13.

[0125] T304, remove the temporary base 20.

[0126] After removing the temporary base 20, the initial chip wafer unit 110 is formed on the chip wafer unit 11, and the structure is as shown in FIG. 26.

[0127] Exemplarily, by irradiating ultraviolet rays, the adhesive release layer 42 is released from the adhesion, and the temporary adhesive layer 41, the adhesive release layer 42, and the temporary base 20 are removed.

[0128] T305. Thin the initial first base 310 to form the first base 31.

[0129] After this step, a structure including a plurality of chip structures 10 as shown in FIG. 1 is obtained.

[0130] Exemplarily, thin the thickness of the initial first base 310 to 60 μm to 200 μm. The shape of the chip structure 10 formed in this way is close to a cube, the arrangement of the chip structure 10 becomes more stable, and it is advantageous for subsequent process use. In the manufacturing process of the chip structure 10, using a thicker initial first base 310 is advantageous for the processing of the chip structure 10.

[0131] Exemplarily, attach an acid-resistant film to the first side of the initial first base 310, and then thin the second side of the initial first base 310. Here, a plurality of sub-pixel light-emitting functional layers 12 are installed on the first side of the initial first base 310.

[0132] T306. Perform cutting to obtain a single chip structure 10.

[0133] Exemplarily, attach a blue film to the side away from the electrode 19 of the first base 31 for protection, and then perform cutting using a laser to obtain a single chip structure 10.

[0134] Through the above steps S101 to S108, steps R201 to R203, and steps T301 to T306, the chip structure 10 as shown in FIG. 1 is formed. The projections of the plurality of sub-pixel light-emitting functional layers 12 in the indium zinc oxide bonding layer 131 cover the plurality of sub-pixel light-emitting functional layers 12. That is, when the indium zinc oxide bonding layer 131 is used as the bonding layer 13, the indium zinc oxide bonding layer 131 is provided throughout the layer, and the orthographic projection of the first base 31 of the indium zinc oxide bonding layer 131 completely covers the orthographic projection of the first base 31 of the plurality of sub-pixel light-emitting functional layers 12. Since the indium zinc oxide bonding layer 131 is a transparent film layer, the indium zinc oxide bonding layer 131 provided throughout the layer does not affect the light rays emitted from the plurality of sub-pixel light-emitting functional layers 12. In this embodiment, using the indium zinc oxide bonding layer 131 as the bonding layer 13 can improve the accuracy of the formed bonding layer 13, thereby improving the product yield of the chip structure 10 and making the thickness of the formed chip structure 10 relatively thin.

[0135] Hereinafter, a second embodiment of the manufacturing method of the chip structure 10 will be described. According to this embodiment, the chip structure 10 as shown in FIG. 2 is formed. In addition, in the steps of manufacturing the chip structure 10, with reference to the content shown in FIG. 2 and the step diagrams, the structural examples of the chip structure 10 can be understood.

[0136] Embodiment 2

[0137] Exemplarily, the manufacturing steps of the initial chip wafer unit 110 refer to steps S101 to S108, and the manufacturing steps of the color conversion layer unit 21 refer to steps R201 to R203, which will not be repeated here.

[0138] After the initial chip wafer unit 110 and the color conversion layer unit 21 are formed, the bonding layer 13 formed by the adhesive layer 133 realizes the assembly of the color conversion layer unit 21 and the initial chip wafer unit 110 to form the chip structure 10. As shown in FIG. 27, this step includes P301 to P305.

[0139] As shown in P301 and FIG. 28, an adhesive layer 133 is applied to the side away from the temporary base 20 of the initial chip wafer unit 110.

[0140] That is, the adhesive layer 133 is applied to the side away from the temporary base 20 of the gallium nitride buffer layer 15.

[0141] Exemplarily, the material of the adhesive layer 133 is an epoxy resin-based organic adhesive material. The adhesive layer 133 is formed by a stencil printing process, and it is ensured that no material for forming the adhesive layer 133 remains in the cutting path 102. Here, as shown in FIG. 4, the cutting path 102 is located between two adjacent chip structures 10 on the wafer 101. Although only one cutting path 102 is shown in FIG. 4, it is understood that the regions between each two adjacent chip structures 10 are all cutting paths 102 in order to obtain a single chip structure 10.

[0142] In the manufacturing process of the initial chip wafer unit 110, a large board including a plurality of initial chip wafer units 110 arranged in an array is formed simultaneously. In the manufacturing process of the color conversion layer unit 21, a large board including a plurality of color conversion layer units 21 arranged in an array is formed simultaneously. Before assembling the color conversion layer unit 21 and the initial chip wafer unit 110, it further includes the step of cutting the large board of the initial chip wafer unit 110 and the large board of the color conversion layer unit 21.

[0143] The large board of the initial chip wafer unit 110 is cut to form a plurality of third initial wafers C. The third initial wafers C include a plurality of initial chip wafer units 110 provided with the adhesive layer 133. The large board of the color conversion layer unit 21 is cut to form a plurality of fourth initial wafers D. The fourth initial wafers D include a plurality of color conversion layer units 21.

[0144] The structures of the third initial wafer C and the fourth initial wafer D can refer to the examples of the first initial wafer A and the second initial wafer B in FIGS. 21 and 24, which will not be repeated here. The difference is that the third initial wafer C includes a plurality of initial chip wafer units 110 provided with an adhesive layer 133, and the first initial wafer A includes a plurality of initial chip wafer units 110 provided with a first indium zinc oxide layer 131a. The fourth initial wafer D includes a plurality of color conversion layer units 21, and the second initial wafer B includes a plurality of color conversion layer units 21 provided with a second indium zinc oxide layer 131b.

[0145] Hereinafter, the steps of finally forming a single chip structure 10 by assembling the third initial wafer C and the fourth initial wafer D will be described.

[0146] P302, As shown in FIG. 29, assemble the color conversion layer unit 21 and the initial chip wafer unit 110.

[0147] Adhere the color conversion layer unit 21 and the initial chip wafer unit 110 with the adhesive layer 133.

[0148] P303, Remove the temporary base 20.

[0149] Specific steps can refer to step T304, which will not be repeated here.

[0150] P304, Thin the initial first base 310 to form the first base 31.

[0151] Specific steps can refer to step T305, which will not be repeated here.

[0152] P305, Perform cutting to obtain a single chip structure 10.

[0153] Specific steps can refer to step T306, which will not be repeated here.

[0154] Through the above steps S101 to S108, steps R201 to R203, and P301 to P305, a chip structure 10 as shown in FIG. 2 is formed. The bonding layer 13 is an adhesive layer 133, and the projections of the adhesive layer 133 on the plurality of sub-pixel light-emitting functional layers 12 cover the plurality of sub-pixel light-emitting functional layers 12. That is, the adhesive layer 133 is provided throughout the layer, and the orthographic projection of the adhesive layer 133 on the first base 31 covers the orthographic projection of the first base of the plurality of sub-pixel light-emitting functional layers 12. The adhesive layer 133 is a transparent organic adhesive material, and the adhesive layer 133 provided throughout the layer does not affect the light rays emitted from the plurality of sub-pixel light-emitting functional layers 12. In this embodiment, using the adhesive layer 133 as the bonding layer 13 can improve the transfer efficiency of Micro-LEDs, reduce the thickness of the chip, and improve the product yield.

[0155] Hereinafter, a third embodiment of the manufacturing method of the chip structure 10 will be described. According to this embodiment, a chip structure 10 as shown in FIG. 3 is formed. In addition, in the steps of manufacturing the chip structure 10, the structural example of the chip structure 10 can be understood with reference to the content shown in FIG. 3 and the step diagram.

[0156] Embodiment 3

[0157] Exemplarily, the manufacturing steps of the initial chip wafer unit 110 refer to steps S101 to S108, and the manufacturing steps of the color conversion layer unit 21 refer to steps R201 to R203, which will not be repeated here.

[0158] After the initial chip wafer unit 110 and the color conversion layer unit 21 are formed, the bonding layer 13 formed by the metal bonding layer 132 realizes the assembly of the color conversion layer unit 21 and the initial chip wafer unit 110 to form the chip structure 10. As shown in FIG. 30, this step includes Q301 to Q306.

[0159] Q301, as shown in FIGS. 31A and 31B, form a first initial sub-metal layer 1310 and a second initial sub-metal layer 1320 on the side away from the temporary base 20 of the initial chip wafer unit 110.

[0160] That is, a first initial sub-metal layer 1310 and a second initial sub-metal layer 1320 are formed on a side away from the dummy base 20 of the gallium nitride buffer layer 15. Here, FIG. 31A is a cross-sectional view obtained along the FF cross-sectional line of FIG. 31B.

[0161] Exemplarily, by a vapor deposition process, a material for forming the first initial sub-metal layer 1310 is deposited on the entire layer on a side away from the dummy base 20 of the gallium nitride buffer layer 15, and the first initial sub-metal layer 1310 is formed by patterning using a photolithography process. The material of the first initial sub-metal layer 1310 may be any one of Au (gold), Ag (silver), Pb (lead), and Sn (tin).

[0162] Exemplarily, as shown in FIG. 31B, the first initial sub-metal layer 1310 includes three opening regions K, and the three opening regions K are a first sub-opening region K11, a second sub-opening region K21, and a third sub-opening region K31, respectively. The first sub-opening region K11 is provided corresponding to the first sub-pixel region S11, the second sub-opening region K21 is provided corresponding to the second sub-pixel region S12, and the third sub-opening region K31 is provided corresponding to the third sub-pixel region S13. Here, that A is provided corresponding to B means that the orthographic projections of A and B on the dummy base 20 overlap or substantially overlap. For example, that the first sub-opening region K11 is provided corresponding to the first sub-pixel region S11 means that the orthographic projections of the first sub-opening region K11 and the first sub-pixel region S11 on the dummy base 20 overlap or substantially overlap.

[0163] Exemplarily, as shown in FIGS. 31A and 31B, the second initial sub-metal layer 1320 includes a plurality of first metal-like bumps 132t, and the structure of the first metal-like bumps 132t may be cylindrical or conical.

[0164] The material of the second initial sub-metal layer 1320 may be In (indium). The temperature at which a eutectic alloy is formed by Au (gold) and In (indium) is 160 °C, the temperature at which a eutectic alloy is formed by Ag (silver) and In (indium) is 180 °C, the temperature at which a eutectic alloy is formed by Pb (lead) and In (indium) is 200 °C, and the temperature at which a eutectic alloy is formed by Sn (tin) and In (indium) is 120 °C.

[0165] Q302, As shown in FIGS. 32A and 32B, a third initial sub-metal layer 1330 is formed on the side away from the initial first base 310 of the color conversion layer unit 21.

[0166] That is, a third initial sub-metal layer 1330 is formed on the side away from the initial first base 310 of the inorganic sealing layer 26.

[0167] Exemplarily, by a vapor deposition process, a material for forming the third initial sub-metal layer 1330 is deposited on the entire layer on the side away from the initial first base 310 of the inorganic sealing layer 26, and the third initial sub-metal layer 1330 is formed by patterning using a photolithography process. The material of the third initial sub-metal layer 1330 may be any one of Au (gold), Ag (silver), Pb (lead), and Sn (tin). The material of the third initial sub-metal layer 1330 may be the same as the material of the first initial sub-metal layer 1310.

[0168] Exemplarily, as shown in FIG. 32B, the third initial sub-metal layer 1330 includes three opening regions K, and the three opening regions K are the fourth sub-opening region K41, the fifth sub-opening region K51, and the sixth sub-opening region K61, respectively. The fourth sub-opening region K41 is provided corresponding to the first sub-pixel region S11, the fifth sub-opening region K51 is provided corresponding to the second sub-pixel region S12, and the sixth sub-opening region K61 is provided corresponding to the third sub-pixel region S13.

[0169] Q303, As shown in FIG. 33, the first initial sub-metal layer 1310, the second initial sub-metal layer 1320, and the third initial sub-metal layer 1330 are bonded.

[0170] Exemplarily, the bonding of the first initial sub-metal layer 1310, the second initial sub-metal layer 1320, and the third initial sub-metal layer 1330 is realized by a metal wafer bonding technique. The metal wafer bonding technique means a technique of completely bonding at a temperature lower than the melting point of each metal by forming a eutectic alloy between two different metals. The metal wafer bonding technique may be classified into a solid-liquid interdiffusion bonding technique and a solid diffusion bonding technique according to the difference in bonding temperature. Here, the requirement for the flatness of the film layer in the solid-liquid interdiffusion bonding technique is lower than that in the solid diffusion bonding technique. Moreover, the bonding strength of the solid-liquid interdiffusion bonding technique is high and the bonding time is short. Therefore, the solid-liquid interdiffusion bonding technique can be used to form the metal bonding layer 132 and realize the assembly of the color conversion layer unit 21 and the initial chip wafer unit 110.

[0171] As shown in FIG. 33, the formed metal bonding layer 132 includes a first sub-metal layer 132a, a second sub-metal layer 132b, and a third sub-metal layer 132c. The first initial sub-metal layer 1310, the second initial sub-metal layer 1320, and the third initial sub-metal layer 1330 form the metal bonding layer 132 by a metal wafer bonding technique. The second sub-metal layer 132b is a eutectic alloy layer formed by a part of the first initial sub-metal layer 1310, a part of the second initial sub-metal layer 1320, and a part of the third initial sub-metal layer 1330.

[0172] Exemplarily, as shown in FIG. 33, the metal bonding layer 132 includes a fourth opening region K4, a fifth opening region, and a sixth opening region. The fourth opening region K4 is provided corresponding to the first sub-pixel region S11, the fifth opening region is provided corresponding to the second sub-pixel region S12, and the sixth opening region is provided corresponding to the third sub-pixel region S13. For the installation of the second sub-pixel region S12 and the third sub-pixel region S13, reference can be made to FIG. 32B. The first sub-opening region K11 and the fourth sub-opening region K41 form the fourth opening region K4. Similarly, the second sub-opening region K21 and the fifth sub-opening region K51 form the fifth opening region, and the third sub-opening region K31 and the sixth sub-opening region K61 form the sixth opening region. For the installation of the second sub-opening region K21, the third sub-opening region K31, the fifth sub-opening region K51, and the sixth sub-opening region K61, reference can be made to FIGS. 31B and 32B.

[0173] Q304. Remove the temporary base 20.

[0174] For the specific steps, reference can be made to step T304, which will not be repeated here.

[0175] Q305. Thin the initial first base 310 to form the first base 31.

[0176] For the specific steps, reference can be made to step T305, which will not be repeated here.

[0177] Q306. Perform cutting to obtain the single chip structure 10.

[0178] For the specific steps, reference can be made to step T306, which will not be repeated here.

[0179] Through the above steps S101 - S108, steps R201 - R203, and Q301 - Q306, a chip structure 10 as shown in FIG. 3 is formed. The bonding layer 13 is a metal bonding layer 132. It is necessary to provide an opening region K corresponding to the plurality of sub - pixel light - emitting functional layers 12 in the metal bonding layer 132. Since the metal bonding layer 132 does not transmit light, it is necessary to provide an opening in the region of the metal bonding layer 132 corresponding to the sub - pixel light - emitting functional layer 12 to emit light. Note that the region of the metal bonding layer 132 corresponding to the sub - pixel light - emitting functional layer 12 means the region where the orthographic projection in the first base 31 of the sub - pixel light - emitting functional layer 12 and the metal bonding layer 132 overlaps. In this embodiment, using the metal bonding layer 132 as the bonding layer 13 can improve the accuracy of the formed bonding layer 13.

[0180] In some embodiments, as shown in FIGS. 34 and 35, among the plurality of sub - pixel light - emitting functional layers 12, the range of the interval d5 between two adjacent sub - pixel light - emitting functional layers 12 is 30 μm to 80 μm.

[0181] Exemplarily, the interval d5 between two adjacent sub - pixel light - emitting functional layers 12, for example, the interval d5 between the first sub - pixel light - emitting functional layer 12a and the second sub - pixel light - emitting functional layer 12b, is 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 75 μm, or 80 μm, etc., and is not limited here. If the interval d5 between two adjacent sub - pixel light - emitting functional layers 12 is too small, for example, if the interval d5 is less than 30 μm, it will cause a cross - color problem between adjacent sub - pixel light - emitting functional layers 12. The design with the range of the interval d5 between two adjacent sub - pixel light - emitting functional layers 12 being 30 μm to 80 μm can effectively prevent cross - color while maintaining the brightness of the chip structure 10.

[0182] Based on the above content, as shown in FIG. 35, the range of the dimension d1 of the indium zinc oxide bonding layer 131 in the first direction X is 100 nm to 300 nm, the range of the dimension d2 of the adhesive layer 133 in the first direction X is 5 μm to 10 μm, and the range of the dimension d3 of the metal bonding layer 132 in the first direction X is 6 μm to 12 μm. The dimension of the bonding layer 13 in the first direction X (for example, dimension d1, dimension d2, or dimension d3) is smaller than the interval d5 between two adjacent sub-pixel light-emitting functional layers 12 among the plurality of sub-pixel light-emitting functional layers 12. Installing in this way can avoid cross-color interference between the sub-pixel light-emitting functional layers 12 and improve the light-emitting effect of the chip structure 10.

[0183] In some embodiments, as shown in FIGS. 34 and 35, among the plurality of anode electrodes, the interval d6 between two adjacent anode electrodes is less than or equal to the interval d5 between the two sub-pixel light-emitting functional layers 12 where the two anode electrodes are located.

[0184] Exemplarily, as shown in FIG. 35, the first sub-pixel light-emitting functional layer 12a is provided corresponding to the first anode 124a, the second sub-pixel light-emitting functional layer 12b is provided corresponding to the second anode 192, and the interval d6 between the first anode 124a and the second anode 192 is smaller than the interval d5 between the first sub-pixel light-emitting functional layer 12a and the second sub-pixel light-emitting functional layer 12b.

[0185] By making the interval d6 between two adjacent anode electrodes less than or equal to the interval d5 between the two sub-pixel light-emitting functional layers 12 where the two anode electrodes are located, that is, the boundary of the sub-pixel light-emitting functional layer 12 where the boundary of the anode electrode is located is crossed. Thereby, while the anode electrode has a conduction effect, it is ensured that the anode electrode has a relatively large area to reflect light rays, and the light-emitting effect of the chip structure 10 can be improved.

[0186] Note that, as shown in FIG. 11B, the interval d13 between the cathode electrode 17b and the adjacent electrode 19 can be set with reference to the interval d6 between two adjacent anode electrodes, which will not be repeated here.

[0187] Exemplarily, the range of the distance d6 between two adjacent anode electrodes is 30 μm to 75 μm, where the anode electrodes include the first anode 124a, the second anode 192, and the third anode 193. For example, the distance d6 between two adjacent anodes, for example, the distance d6 between the first anode 124a and the second anode 192, can be 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 65 μm, or 75 μm, etc., and is not limited herein.

[0188] In some embodiments, as shown in FIGS. 34 and 35, the projection of the filter film layer 28 on the first base 31 covers the projection of the sub-pixel light-emitting functional layer 12 corresponding to the filter film layer 28 on the first base. The projection of the color conversion layer 22 on the first base 31 covers the projection of the filter film layer 28 corresponding to the color conversion layer 22 on the first base 31. The projection of the scattering particle portion 22b on the first base 31 covers the projection of the second filter film 242 on the first base 31. Here, FIG. 35 is a cross-sectional view obtained along the HH cross-section line of FIG. 34.

[0189] That is, along any direction, the dimension of the projection of the filter film layer 28 on the first base 31 is larger than the dimension of the projection of the sub-pixel light-emitting functional layer 12 corresponding to the filter film layer 28 on the first base 31. The dimension of the projection of the color conversion layer 22 on the first base 31 is larger than the dimension of the projection of the filter film layer 28 corresponding to the color conversion layer 22 on the first base 31. The dimension of the projection of the scattering particle portion 22b on the first base 31 is larger than the dimension of the projection of the second filter film 242 on the first base 31.

[0190] Exemplarily, the range of the distance d7 between the projection boundary of the filter film layer 28 on the first base 31 and the projection boundary of the sub-pixel light-emitting functional layer 12 corresponding to the filter film layer 28 on the first base 31 is 20 μm to 60 μm. For example, the distance d7 between the projection boundary of the filter film layer 28 on the first base 31 and the projection boundary of the sub-pixel light-emitting functional layer 12 corresponding to the filter film layer 28 on the first base 31 can be 20 μm, 40 μm, 50 μm, or 60 μm, and is not limited herein.

[0191] Exemplarily, the range of the distance d8 between the projection boundary in the first base 31 of the color conversion layer 22 and the projection boundary in the first base 31 of the filter film layer 28 corresponding to the color conversion layer 22 is 23 μm to 68 μm. For example, the distance d8 between the projection boundary in the first base 31 of the color conversion layer 22 and the projection boundary in the first base 31 of the filter film layer 28 corresponding to the color conversion layer 22 is 23 μm, 30 μm, 35 μm, 42 μm, 50 μm, 60 μm, or 68 μm, etc., and is not limited herein.

[0192] Exemplarily, the range of the distance d9 between the projection boundary in the first base 31 of the scattering particle portion 22b and the projection boundary in the first base 31 of the second filter film 242 is 23 μm to 68 μm. For example, the distance d9 between the projection boundary in the first base 31 of the scattering particle portion 22b and the projection boundary in the first base 31 of the second filter film 242 is 23 μm, 32 μm, 38 μm, 45 μm, 55 μm, 62 μm, or 68 μm, etc., and is not limited herein.

[0193] In some embodiments, as shown in FIGS. 34 and 35, the range of the dimension d10 of the limiting dam layer 25 in the first direction X is 10 μm to 30 μm.

[0194] Exemplarily, the dimension d10 of the limiting dam layer 25 in the first direction X is 10 μm, 15 μm, 20 μm, 25 μm, 28 μm, or 30 μm, etc., and is not limited herein. Making the dimension d10 of the limiting dam layer 25 in the first direction X, that is, its thickness, 10 μm to 30 μm means that the thickness of the limiting dam layer 25 increases. Since the color conversion layer 22 is provided within the opening region K of the limiting dam layer 25, the thickness of the color conversion layer 22 increases simultaneously. Designing in this way can improve the light-emitting effect of the chip structure 10.

[0195] In some embodiments, as shown in FIG. 35, the projection of the color conversion layer unit 21 on the first base 31 covers the projection of the bonding layer 13 on the first base 31.

[0196] Exemplarily, an epoxy resin-based organic adhesive material is used as the material of the bonding layer 13. By installing the projection on the first base 31 of the color conversion layer unit 21 so as to cover the projection on the first base 31 of the bonding layer 13, it can be guaranteed that no organic adhesive material remains at the position of the cutting passage 102 (shown in FIG. 4), which facilitates forming by cutting the chip structure 10.

[0197] In some examples, as shown in FIG. 35, the range of the distance d14 between the projection boundary on the first base 31 of the color conversion layer unit 21 and the projection boundary on the first base 31 of the bonding layer 13 is 0 μm to 10 μm.

[0198] Exemplarily, the distance d14 between the projection boundary on the first base 31 of the color conversion layer unit 21 and the projection boundary on the first base 31 of the bonding layer 13 is 0 μm, 2 μm, 5 μm, 7 μm, 10 μm, etc., and is not limited herein.

[0199] By setting the range of the distance d14 between the projection boundary on the first base 31 of the color conversion layer unit 21 and the projection boundary on the first base 31 of the bonding layer 13 to 0 μm to 10 μm, the adhesion stability of the chip structure 10 can be guaranteed, and when the material of the bonding layer 13 is an epoxy resin-based organic adhesive material, it is guaranteed that no organic adhesive material remains at the position of the cutting passage 102 (shown in FIG. 4).

[0200] Some embodiments of the present disclosure further provide a display substrate 100. As shown in FIG. 36, the display substrate 100 includes a plurality of chip structures 10 described in any of the above embodiments.

[0201] In some embodiments, the display substrate 100 includes a driving backplane. The driving backplane includes a circuit layer, and a plurality of chip structures 10 are installed on the driving backplane. The circuit layer includes, for example, a plurality of pad sets, and each pad set includes a plurality of pads installed separately. The cathode electrode 17b, the first anode 124a, the second anode 192, and the third anode 193 of each chip structure 10 are electrically connected to one pad among the plurality of pads respectively.

[0202] Exemplarily, a plurality of chip structures 10 are transferred to a driving backplane by a mass transfer technique.

[0203] Some embodiments of the present disclosure further provide a display device 1000 including the above-described display substrate 100, as shown in FIG. 37.

[0204] Exemplarily, the display device provided by the embodiments of the present disclosure can be any device that displays regardless of whether it is moving (e.g., video) or stationary (e.g., still image), and regardless of text or image. More specifically, it is expected that the above embodiments may be implemented in multiple types of electronic devices or associated with multiple electronic devices. The multiple types of electronic devices may include, for example, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, global positioning system (GPS) receivers / navigators, cameras, MP4 video players, video cameras, game consoles, wristwatches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car displays (e.g., speed / distance meter displays, etc.), navigators, cockpit controllers and / or displays, camera view displays (e.g., rear view camera displays in vehicles), electrophotography, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of an image of a single gemstone), etc., but are not limited thereto.

[0205] The above are only specific embodiments of the present disclosure, and the protection scope of the present disclosure is not limited thereto. Modifications or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure are all included within the technical scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be based on the scope described in the claims.

Claims

1. A chip wafer unit and a color conversion layer unit disposed on the light-emitting side of the chip wafer unit, wherein the chip wafer unit includes a plurality of sub-pixel light-emitting functional layers, and the color conversion layer unit includes a color conversion layer disposed on the light-emitting side of the chip wafer unit. The chip structure is provided between the chip wafer unit and the color conversion layer unit, and further includes a bonding layer used for bonding the chip wafer unit and the color conversion layer unit. Chip structure.

2. The bonding layer is any one of an indium zinc oxide bonding layer, a metal bonding layer, and an adhesive layer. The chip structure according to Claim 1.

3. The dimension of the bonding layer in the first direction is smaller than the interval between two adjacent sub-pixel light-emitting functional layers among the plurality of sub-pixel light-emitting functional layers. The first direction is the direction pointing from the chip wafer unit to the color conversion layer unit. The chip structure according to Claim 1 or Claim 2.

4. The bonding layer is the indium zinc oxide bonding layer, and the dimension range of the indium zinc oxide bonding layer in the first direction is 100 nm to 300 nm. Alternatively, the bonding layer is the metal bonding layer, and the dimension range of the metal bonding layer in the first direction is 6 μm to 12 μm. Alternatively, the bonding layer is the adhesive layer, and the dimension range of the adhesive layer in the first direction is 5 μm to 10 μm. The chip structure according to Claim 3.

5. The bonding layer is the indium zinc oxide bonding layer, and the indium zinc oxide bonding layer includes a first indium zinc oxide layer and a second indium zinc oxide layer stacked and disposed along the first direction. The first indium zinc oxide layer and the second indium zinc oxide layer are connected by the action of molecular bonding. Alternatively, the bonding layer is the metal bonding layer, and the metal bonding layer includes a first sub-metal layer, a second sub-metal layer, and a third sub-metal layer stacked and disposed along the first direction. The second sub-metal layer is disposed as a eutectic alloy layer connecting the first sub-metal layer and the third sub-metal layer. The chip structure according to Claim 3 or Claim 4.

6. The bonding layer is the indium zinc oxide bonding layer, and the projection of the indium zinc oxide bonding layer on the plurality of sub-pixel light-emitting functional layers covers the plurality of sub-pixel light-emitting functional layers. Alternatively, the bonding layer is the metal bonding layer, and an opening region corresponding to the plurality of sub-pixel light-emitting functional layers is provided in the metal bonding layer. Alternatively, the bonding layer is the adhesive layer, and the projection of the adhesive layer on the plurality of sub-pixel light-emitting functional layers covers the plurality of sub-pixel light-emitting functional layers. The chip structure according to any one of claims 2 to 5.

7. The chip structure further includes a first base, the first base is installed on the side away from the chip wafer unit of the color conversion layer unit, and the projection of the color conversion layer unit on the first base covers the projection of the bonding layer on the first base. The chip structure according to any one of claims 2 to 6.

8. The range of the distance between the projection boundary of the color conversion layer unit on the first base and the projection boundary of the bonding layer on the first base is 0 μm to 10 μm. The chip structure according to claim 7.

9. Each of the plurality of sub-pixel light-emitting functional layers includes an anode electrode, a current diffusion layer, a p-type gallium nitride layer, and a quantum well layer stacked along a first direction. The chip wafer unit further includes a common cathode layer, and the common cathode layer includes a cathode electrode and a cathode metal layer stacked along a first direction. The cathode metal layer further includes a portion located between two adjacent sub-pixel light-emitting functional layers, and the first direction is the direction pointing from the chip wafer unit to the color conversion layer unit. The chip structure according to any one of claims 1 to 8.

10. There is a gap between the portion of the cathode metal layer located between two adjacent sub-pixel light-emitting functional layers and the two sub-pixel light-emitting functional layers. The range of the gap between the sub-pixel light-emitting functional layer and the cathode metal layer is 1 / 10 to 1 / 3 of the range of the gap between two adjacent sub-pixel light-emitting functional layers. The chip structure according to claim 9.

11. Among the plurality of anode electrodes, the range of the gap between two adjacent anode electrodes is not greater than the range of the gap between the two sub-pixel light-emitting functional layers where the two anode electrodes are located. The chip structure according to claim 9 or claim 10.

12. The chip wafer unit further includes an n-type gallium nitride layer and a gallium nitride buffer layer that are stacked and installed along a first direction. The n-type gallium nitride layer is installed on the light-emitting side of the plurality of sub-pixel light-emitting functional layers. The bonding layer is installed on the side of the gallium nitride buffer layer away from the n-type gallium nitride layer. The first direction is the direction pointing from the chip wafer unit to the color conversion layer unit. The chip structure according to any one of claims 1 to 11.

13. The plurality of sub-pixel light-emitting functional layers include a first sub-pixel light-emitting functional layer, a second sub-pixel light-emitting functional layer, and a third sub-pixel light-emitting functional layer. The chip structure further includes a first base. The color conversion layer unit includes a color film layer installed on one side of the first base. The color film layer includes a black matrix layer and a plurality of filter film layers defined by the black matrix layer. The plurality of filter film layers include a first filter film layer, a second filter film layer, and a third filter film layer. The first filter film layer is installed corresponding to the first sub-pixel light-emitting functional layer. The second filter film layer is installed corresponding to the second sub-pixel light-emitting functional layer. The third filter film layer is installed corresponding to the third sub-pixel light-emitting functional layer. The color conversion layer unit further includes a limiting dam layer installed on the side of the color film layer away from the first base. The limiting dam layer is provided with a plurality of opening regions. The plurality of opening regions include a first opening region, a second opening region, and a third opening region. The first opening region is provided corresponding to the first sub-pixel light-emitting functional layer. The second opening region is provided corresponding to the second sub-pixel light-emitting functional layer. The third opening region is provided corresponding to the third sub-pixel light-emitting functional layer. The color conversion layer further includes a first quantum dot conversion part, a second quantum dot conversion part, and a scattering particle part. The first quantum dot conversion part is installed in the first opening region. The scattering particle part is installed in the second opening region. The second quantum dot conversion part is installed in the third opening region. The chip structure according to any one of claims 1 to 12.

14. The projection of the filter film layer on the first base covers the projection of the sub-pixel light-emitting functional layer corresponding to the filter film layer on the first base. The projection of the quantum dot conversion unit on the first base covers the projection of the filter film layer corresponding to the quantum dot conversion unit on the first base. The projection of the scattering particle part on the first base covers the projection of the second filter film layer on the first base. The chip structure according to claim 13.

15. The range of the distance between the projection boundary of the filter film layer on the first base and the projection boundary of the sub-pixel light-emitting functional layer corresponding to the filter film layer on the first base is 20 μm to 60 μm. The range of the distance between the projection boundary of the quantum dot conversion unit on the first base and the projection boundary of the filter film layer corresponding to the quantum dot conversion unit on the first base is 23 μm to 68 μm. The range of the distance between the projection boundary of the scattering particle part on the first base and the projection boundary of the second filter film layer on the first base is 23 μm to 68 μm. The chip structure according to claim 14.

16. The range of the dimension of the limiting dam layer in the first direction is 10 μm to 30 μm. The first direction is the direction pointing from the chip wafer unit to the color conversion layer unit. The chip structure according to any one of claims 13 to 15.

17. A step of forming an initial chip wafer unit, the initial chip wafer unit including a temporary base, a plurality of sub-pixel light-emitting functional layers, an n-type gallium nitride layer, and a gallium nitride buffer layer, which are stacked and installed. A step of forming a color conversion layer unit, which is a step of forming the color conversion layer unit on an initial first base. A step of bonding the color conversion layer unit to the light-emitting side of the initial chip wafer unit to obtain a chip structure. including A manufacturing method of a chip structure.

18. The step of bonding the color conversion layer unit to the light-emitting side of the initial chip wafer unit A step of forming an indium zinc oxide layer on the side away from the temporary base of the initial chip wafer unit. A step of forming a second indium zinc oxide layer on the side away from the initial first base of the color conversion layer unit. A step of bonding the first indium zinc oxide layer and the second indium zinc oxide layer to form a bonding layer connecting the initial chip wafer unit and the color conversion layer unit. including Alternatively, the step of bonding the color conversion layer unit to the light emitting side of the initial chip wafer unit is forming a first initial sub-metal layer and a second initial sub-metal layer on a side away from the temporary base of the initial chip wafer unit, wherein the second initial sub-metal layer is a plurality of first metalloid bumps formed on a side away from the temporary base of the first initial sub-metal layer forming a third initial sub-metal layer on a side away from the initial first base of the color conversion layer unit combining the first initial sub-metal layer, the second initial sub-metal layer, and the third initial sub-metal layer to form a bonding layer connecting the initial chip wafer unit and the color conversion layer unit including Alternatively, the step of bonding the color conversion layer unit to the light emitting side of the initial chip wafer unit is including connecting the initial chip wafer unit and the color conversion layer unit using an adhesive The method for manufacturing a chip structure according to claim 17.

19. The step of bonding the first indium zinc oxide layer and the second indium zinc oxide layer is treating a surface of the first indium zinc oxide layer away from the temporary base with oxygen plasma treating a surface of the second indium zinc oxide layer away from the initial first base with oxygen plasma pressing and bonding the first indium zinc oxide layer and the second indium zinc oxide layer under a temperature condition of 150°C to 240°C to form a bonding layer including The method for manufacturing a chip structure according to claim 18.

20. After bonding the color conversion layer unit to the light emitting side of the initial chip wafer unit, the manufacturing method includes removing the temporary base to form a chip wafer unit thinning the thickness of the initial first base to form a first base to obtain a chip structure including The method for manufacturing a chip structure according to any one of claims 17 to 19.

21. Comprising the chip structure according to any one of claims 1 to 16 A display substrate.

22. Comprising the display substrate according to claim 21 A display device.

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