Display substrate and display device

Abstract

The present disclosure discloses a display substrate and a display device in the field of display technology. The display substrate includes a shift register provided on a base substrate. The shift register includes a plurality of stages of driving circuits. A plurality of stages of driving circuits are provided in the driving circuit region of the base substrate. One stage of the driving circuit region includes a first region and a second region. A first type of transistor is provided in the first region, and a second type of transistor is provided in the second region. One side of the first region is the side far from the second region of the power supply line, and the other side of the first region is the side close to the second region of the active layer of the first type of transistor in the second region. One side of the second region is the side far from the first region of the power supply line, and the other side of the second region is the side close to the second region of the active layer of the first type of transistor in the second region. The present disclosure shortens the width of the driving circuit included in the display substrate along the first direction to achieve a narrow bezel.

Description

Technical Field

[0001] (Cross - reference to related applications) This disclosure claims priority based on Chinese Patent Application No. 202210644140.7 filed in China on June 9, 2022, and all of its contents are incorporated herein by reference. This disclosure relates to the field of display technologies, and in particular, to display substrates and display devices.

Background Art

[0002] The display panel includes a plurality of pixel circuits distributed like an array located in the display area and a shift register located in the edge area. The shift register includes a plurality of stages of driving circuits, and the driving circuits are used to provide corresponding scanning driving signals to the corresponding pixel circuits. Since the shift register is provided in the edge area of the display panel, the arrangement method of the driving circuits determines the frame width of the display panel.

Summary of the Invention

[0003] Embodiments of this disclosure are display substrates, including a shift register provided on a base substrate. The shift register includes a plurality of stages of driving circuits. The driving circuits include a first input circuit, a second input circuit, a first output circuit, and a control circuit. The first output circuit is configured to provide a first scanning driving signal to a first driving signal output terminal under the control of the potentials of a first node and a second node. The first input circuit is configured to input a signal to a third node under the control of a clock signal. The second input circuit is configured to input a signal from a power line to the second node under the control of the potential of the third node. The control circuit is configured to control the potential of the third node and the potential of the first node. A plurality of stages of the driving circuits are provided in the driving circuit area of the base substrate. One stage of the driving circuit area among the plurality of stages of the driving circuits includes a first area and a second area. The first area is provided with a first type of transistor included in the driving circuit, and the second area is provided with a second type of transistor included in the driving circuit. One side of the first region is the side far from the second region of the power line, and the other side of the first region is the side close to the second region of the active layer of the first type of transistor close to the second region. One side of the second region is the side far from the first region of the power line, and the other side of the second region is the side close to the second region of the active layer of the first type of transistor close to the second region. A display substrate is provided.

[0004] Optionally, the power line includes a first power line, and the second input circuit is configured to input a first voltage signal from the first power line to the second node under the control of the potential of the third node. X1 / X3≧0.21, Here, X1 is the width of the first region in the first direction, and X3 is the width of the second region in the first direction. The first direction is a direction intersecting the extending direction of the first power line.

[0005] Optionally, the power line includes a second power line, and the second input circuit is configured to input a second voltage signal from the second power line to the second node under the control of the potential of the third node. X1 / X3≧0.52, Here, X1 is the width of the first region in the first direction, and X3 is the width of the second region in the first direction. The first direction is a direction intersecting the extending direction of the second power line.

[0006] Optionally, the first type of transistor is an N-type transistor, and the second type of transistor is a P-type transistor. The distance between at least one of the N-type transistors and the second power line is smaller than the distance between the P-type transistor and the second power line.

[0007] Optionally, the second input circuit includes a first transistor. The gate of the first transistor is electrically connected to the third node. The first electrode of the first transistor is electrically connected to the second power supply line. The second electrode of the first transistor is electrically connected to the second node. The first transistor is a first type of transistor. WT1 / X1≥0.258, where WT1 is the width of the active layer of the first transistor along the first direction.

[0008] Optionally, the driving circuit further includes a second output circuit. The second output circuit is configured to control to output a second scanning driving signal via a second driving signal output terminal under the control of the potential of the third node. The second output circuit includes a second transistor. The gate of the second transistor is electrically connected to the third node. The first electrode of the second transistor is electrically connected to the second power supply line. The second electrode of the second transistor is electrically connected to the second driving signal output terminal. The second transistor is a first type of transistor. WT2 / X1≥0.33, where WT2 is the width of the active layer of the second transistor along the first direction.

[0009] Optionally, the second input circuit includes a first transistor. The gate of the first transistor is electrically connected to the third node. The first electrode of the first transistor is electrically connected to the second power supply line. The second electrode of the first transistor is electrically connected to the second node. The driving circuit further includes a second output circuit. The second output circuit is configured to control to output a second scanning driving signal via a second driving signal output terminal under the control of the potential of the third node. The second output circuit includes a second transistor. The gate of the second transistor is electrically connected to the third node. The first electrode of the second transistor is electrically connected to the second power supply line. The second electrode of the second transistor is electrically connected to the second driving signal output terminal. Both the first transistor and the second transistor are first type of transistors. WT2 / WT1 ≥ 3.25, WT1 is the width along the first direction of the active layer of the first transistor, and WT2 is the width along the first direction of the active layer of the second transistor.

[0010] Optionally, the display substrate further includes a group of clock signal lines provided in the driving circuit region, and the group of clock signal lines is configured to provide the clock signal. The active layer of at least one first type of transistor is located between the group of clock signal lines and the power supply line in the first direction. The overlapping area between the orthographic projection of the active layer of at least one first type of transistor on the base substrate and the orthographic projection of the power supply line on the base substrate is not more than five-sixths of the area of the active layer of the at least one first type of transistor.

[0011] Optionally, the ratio of the length along the second direction of the active layer of at least one first type of transistor to the height of the driving circuit is 0.75 or less.

[0012] Optionally, the display substrate further includes a first active layer provided in the second region, the first active layer includes a first active part, two second active parts, and two third active parts, and the display substrate further includes a second output circuit. The first active part functions as the active layer of the third transistor, the two second active parts function as the active layers of the fourth transistors, and the two third active parts function as the active layers of the fifth transistors. The third transistor is a transistor that outputs a first voltage signal provided by the first output circuit, the fifth transistor is a transistor that outputs a clock signal provided by the first output circuit, and the fourth transistor is a transistor that outputs a third voltage signal provided by the second output circuit. The channel area of the nth transistor is ARn, and ARn ≥ 2(n - 1)i, where n is 1, 2, or 3, and i is the unit channel area.

[0013] Optionally, the area P1 of the first active part is p, the sum P2 of the areas of the two second active parts is equal to or greater than 2p and equal to or less than 3p, and the sum P3 of the areas of the two third active parts is equal to or greater than 3p and equal to or less than 4p.

[0014] Optionally, the display substrate further includes a clock signal line provided in the drive circuit region, the clock signal line is configured to provide a clock signal, and the first electrode of the fourth transistor is electrically connected to a third power supply line. The ratio of the first distance to the length of the active layer of the third transistor in the first direction is 10.78 or less. The first distance is the distance between one side of the clock signal line far from the display region and one side of the third power supply line close to the display region.

[0015] Optionally, the display substrate further includes a clock signal line provided in the drive circuit region, the clock signal line is configured to provide a clock signal, the first electrode of the fourth transistor is electrically connected to a third power supply line, the ratio of the line width of the first power supply line to the first distance is 0.060 or more, the line width of the first power supply line is the length along the first direction of the first power supply line, and the first distance is the distance between one side of the clock signal line far from the display region and one side of the third power supply line close to the display region.

[0016] Optionally, the display substrate further includes a clock signal line provided in the drive circuit region, the clock signal line is configured to provide a clock signal, and the first electrode of the fourth transistor is electrically connected to a third power supply line. The ratio of the line width of the third power supply line to the first distance is 0.045 or less, the line width of the third power supply line is the length along the first direction of the third power supply line, and the first distance is the distance between one side of the clock signal line far from the display region and one side of the third power supply line close to the display region.

[0017] Optionally, the display substrate further includes a clock signal line group provided in the drive circuit region. The clock signal line group includes at least one clock signal line. The clock signal line is configured to provide a clock signal. The display substrate includes at least two power supply lines. The clock signal line group is located between two of the at least two power supply lines, or the clock signal line group is located on the side far from the display region of the power supply line.

[0018] Optionally, the display substrate includes a first power supply line and a third power supply line. The display substrate further includes a second output circuit. The second input circuit is configured to input a first voltage signal from the first power supply line to the second node under the control of the potential of the third node. The second output circuit is configured to output a third voltage signal from the third power supply line to the second drive signal output terminal under the control of the potential of the third node. The ratio of the second distance to the length of the active layer of the third transistor in the first direction is 8.47 or less. The third transistor is a transistor that outputs a first voltage signal provided by the first output circuit. The second distance is the distance between one side far from the display region of the first power supply line and one side close to the display region of the third power supply line.

[0019] Optionally, the display substrate includes a first power supply line and a third power supply line. The display substrate further includes a second output circuit. The second input circuit is configured to input a first voltage signal from the first power supply line to the second node under the control of the potential of the third node. The second output circuit is configured to output a third voltage signal from the third power supply line to the second drive signal output terminal under the control of the potential of the third node. The ratio of the line width of the first power supply line to the second distance is 0.077 or more. The line width of the first power supply line is the length of the first power supply line in the first direction. The second distance is the distance between one side far from the display region of the first power supply line and one side close to the display region of the third power supply line.

[0020] Optionally, the display substrate includes a first power line and a third power line, the display substrate further includes a second output circuit, the second input circuit is configured to input a first voltage signal from the first power line to the second node under the control of the potential of the third node, and the second output circuit is configured to output a third voltage signal from the third power line to the second drive signal output terminal under the control of the potential of the third node. The ratio of the line width of the third power line to the second distance is 0.058 or more. The line width of the third power line is the length of the third power line in the first direction, and the second distance is the distance between one side of the first power line far from the display area and one side of the third power line close to the display area.

[0021] Optionally, the display substrate includes a first source-drain metal layer and a second source-drain metal layer sequentially stacked along the direction away from the base substrate. The clock signal line includes a first clock signal line portion provided on the first source-drain metal layer or a second clock signal line portion provided on the second source-drain metal layer.

[0022] Optionally, the display substrate further includes a third gate metal layer provided between the first source-drain metal layer and the base substrate. The clock signal line further includes a third clock signal line portion provided on the third gate metal layer. The clock signal line includes the first clock signal line portion, and the third clock signal line portion and the first clock signal line portion are in direct contact or electrically connected to each other via a via, or the clock signal line includes the second clock signal line portion, and the third clock signal line portion and the second clock signal line portion are in direct contact or electrically connected to each other via a via.

[0023] Optionally, the clock signal line includes two clock signal line portions coupled to each other, the two clock signal line portions are provided in different metal layers respectively, one of the two clock signal line portions is continuous, and the other of the two clock signal line portions is not continuous.

[0024] Optionally, the display substrate includes a first transfer electrode. The first electrode of the fifth transistor included in the driving circuit of this stage, the gate of the sixth transistor included in the driving circuit of this stage, and the gate of the seventh transistor included in the driving circuit of the adjacent stage are electrically connected to each other via the same first transfer electrode. The fifth transistor is a transistor that outputs the clock signal included in the first output circuit, the sixth transistor is a transistor that operates under the control of the clock signal included in the control circuit, and the seventh transistor is a transistor that provides an input voltage to the third node included in the first input circuit.

[0025] Optionally, the display substrate includes a first power line and a second power line, the display substrate further includes a second output circuit, the first input circuit includes a seventh transistor, the second input circuit includes an eighth transistor, the seventh transistor is a transistor that provides an input voltage to the third node, the eighth transistor is a transistor that inputs a first voltage signal from the first power line to the second node under the control of the potential of the third node, and the fourth transistor is a transistor that outputs the third voltage signal included in the second output circuit. The extending direction of the active layer of the seventh transistor is the same as or perpendicular to the extending direction of the active layer of the eighth transistor. In the driving circuit of the same stage, the position of the first electrode of the seventh transistor in the second direction is lower than the position of the second electrode of the fourth transistor in the second direction.

[0026] Optionally, the display substrate includes a first power line, the display substrate further includes a second transfer electrode, the second transfer electrode and the first power line are of an integral structure, the second input circuit includes an eighth transistor, the first output circuit includes a third transistor, the eighth transistor is a transistor that inputs a first voltage signal from the first power line to a second node under the control of the potential of the third node, and the third transistor is a transistor that outputs a first voltage signal provided by the first output circuit. The second transfer electrode includes a first electrode portion, a second electrode portion, and a third electrode portion. The first electrode portion functions as a connection electrode between the first power line and the first electrode of the eighth transistor, the second electrode portion is a connection electrode between the first electrode of the eighth transistor and the first electrode of the third transistor, and the third electrode portion functions as the first electrode of the third transistor. The included angle between the first electrode portion and the second electrode portion is equal to or greater than 90 degrees and equal to or less than 120 degrees.

[0027] Optionally, the display substrate further includes a third transfer electrode, the third transfer electrode includes a fourth electrode portion, a fifth electrode portion, and a sixth electrode portion, the second input circuit includes a first transistor and an eighth transistor, the first transistor is a transistor that inputs a second voltage signal from a second power line to the second node under the control of the potential of the third node, the driving circuit further includes a second output circuit, the second output circuit includes a second transistor, the second transistor is a transistor that outputs the second voltage signal from the second power line to a second driving signal output terminal under the control of the potential of the third node, the eighth transistor is a transistor that inputs a first voltage signal from the first power line to the second node under the control of the potential of the third node, the control circuit includes a sixth transistor and a ninth transistor, and the sixth transistor is a transistor that operates under the control of a clock signal. The ninth transistor is a transistor that controls the conduction between the third node and the first node under the control of a second voltage signal from a second power supply line. The first transistor and the second transistor are transistors of a first type, and the eighth transistor and the ninth transistor are transistors of a second type. The fourth electrode portion is configured to electrically connect the bottom gate of the first transistor and the gate of the eighth transistor, and / or the fourth electrode portion is configured to electrically connect the bottom gate of the second transistor and the gate of the eighth transistor. The fifth electrode portion is configured to electrically connect the fourth electrode portion, the first electrode of the ninth transistor, and the upper gate of the first transistor, and / or the fifth electrode portion is configured to electrically connect the fourth electrode portion, the first electrode of the ninth transistor, and the upper gate of the second transistor. The sixth electrode portion is configured to electrically connect the first electrode of the ninth transistor and the second electrode of the sixth transistor.

[0028] Optionally, the included angle between the fourth electrode portion and the fifth electrode portion is 90 degrees or more and less than 130 degrees.

[0029] Optionally, the fifth electrode portion is perpendicular or parallel to the sixth electrode portion.

[0030] Optionally, the first output circuit further includes a first capacitor. The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the first drive signal output terminal. The display substrate further includes a first shield portion. The first plate of the first capacitor is provided between the base substrate and the second plate of the first capacitor. The first shield portion is provided on the side where the second plate of the first capacitor is far from the base substrate.

[0031] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a second shielding portion, and the second input circuit includes a first transistor, in the second shielding portion, an active layer of the first transistor is provided on a side far from the base substrate, an area of a positive projection of the second shielding portion on a power supply line is larger than an area of a positive projection of the active layer of the first transistor on the power supply line.

[0032] An embodiment of the present disclosure is a display substrate including a shift register provided on a base substrate, the shift register including a plurality of stages of driving circuits, the driving circuit including a first input circuit, a second input circuit, a first output circuit, a control circuit, and a second output circuit, the first output circuit being configured to provide a first scanning driving signal to a first driving signal output terminal under control of a potential of a first node and a potential of a second node, the first input circuit being configured to input a signal to a third node under control of a clock signal, the second input circuit being configured to input a signal from a power supply line to the second node under control of a potential of the third node, the control circuit being configured to control a potential of the third node and a potential of the first node, the second output circuit being configured to control to output a second scanning driving signal through a second driving signal output terminal under control of a potential of the third node, the second input circuit including a first transistor, the second output circuit including a second transistor, the driving circuit is configured to provide a scanning driving signal to a display area, a gate of the first transistor is electrically connected to the third node, a first electrode of the first transistor is electrically connected to a second power supply line, a second electrode of the first transistor is electrically connected to the second node, a gate of the second transistor is electrically connected to the third node, a first electrode of the second transistor is electrically connected to the second power supply line, a second electrode of the second transistor is electrically connected to the second driving signal output terminal, and the first transistor and the second transistor are N-type transistors, Further provided is a display substrate in which a ratio value of an area of an oxide active layer of the second transistor to an area of an oxide active layer of the first transistor is 8.74 or more.

[0033] Optionally, the fourth transistor is a transistor that outputs a third voltage signal included in the second output circuit, the fourth transistor is a P-type transistor, and an active layer of the fourth transistor is a low-temperature polysilicon active layer. A ratio value of an area of an oxide active layer of the second transistor to an area of an active layer of the fourth transistor is 1.4 or more.

[0034] Optionally, the power supply line includes a first power supply line and a third power supply line. The second input circuit is configured to input a first voltage signal from the first power supply line to the second node under control of a potential of the third node. The second output circuit is electrically connected to the third power supply line and is configured to provide a third voltage signal from the third power supply line to a second drive signal output end under control of a potential of the third node. A voltage value of the third voltage signal is equal to or higher than a voltage value of the first voltage signal.

[0035] Optionally, a voltage value of the third voltage signal is 1.4 times or more of a voltage value of the first voltage signal.

[0036] Optionally, a gate of the first transistor includes a first gate and a second gate, a gate of the second transistor includes a first gate and a second gate, the first gate is a bottom gate, the second gate is a top gate, and the display substrate includes a first gate metal layer, a second gate metal layer, and a third gate metal layer stacked along a side far from the base substrate. The bottom gate is included in the first gate metal layer, the top gate is included in the second gate metal layer, or the bottom gate is included in the second gate metal layer, the top gate is included in the third gate metal layer, or the bottom gate is included in the first gate metal layer, the top gate is included in the third gate metal layer.

[0037] Optionally, the first gate of the first transistor and the first gate of the second transistor are of an integral structure, the second gate of the first transistor and the second gate of the second transistor are of an integral structure, the display substrate further includes a first source-drain metal layer and a second source-drain metal layer provided on a side of the third gate metal layer far from the base substrate, and the first source-drain metal layer is provided between the third gate metal layer and the second source-drain metal layer. The first gate of the first transistor and the second gate of the first transistor are electrically connected to each other via a connection electrode, and the connection electrode is included in the first source-drain metal layer or the second source-drain metal layer.

[0038] An embodiment of the present disclosure is a display substrate including a shift register provided on a base substrate, the shift register including a plurality of stages of drive circuits. The drive circuit includes a first input circuit, a second input circuit, a first output circuit, and a control circuit. The first output circuit is configured to provide a first scanning drive signal to a first drive signal output terminal under the control of the potential of a first node and the potential of a second node. The first input circuit is configured to input a signal to a third node under the control of a clock signal. The second input circuit is configured to input a signal from a power supply line to the second node under the control of the potential of the third node. The control circuit is configured to control the potential of the third node and the potential of the first node, and further provides a display substrate.

[0039] Optionally, the power supply line includes a first power supply line and a second power supply line. The first input circuit is electrically connected to an input voltage terminal, a first clock signal line, and the third node respectively, and is configured to write an input voltage from the input voltage terminal to the third node under the control of a first clock signal from the first clock signal line. The second input circuit is electrically connected to the third node, the second power supply line, the second node, and the first power supply line respectively, and is configured to write a first voltage signal from the first power supply line to the second node under the control of the potential of the third node, and write a second voltage signal from the second power supply line to the second node. The first output circuit is electrically connected to the second node, the first node, the first power supply line, the second clock signal line, and the first drive signal output terminal respectively, and is configured to output a first voltage signal from the first power supply line to the first drive signal output terminal under the control of the potential of the second node, and output a second clock signal from the second clock signal line to the first drive signal output terminal under the control of the potential of the first node. The control circuit is electrically connected to the second node, the first power supply line, the second clock signal line, the third node, the first node, and the second power supply line respectively, and is configured to control to write a first voltage signal from the first power supply line to the third node under the control of the potential of the second node and the second clock signal from the second clock signal line, and control the conduction between the third node and the first node under the control of the second voltage signal from the second power supply line.

[0040] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a second output circuit. The second output circuit is electrically connected to the third node, the second drive signal output terminal, the third power supply line, and the second power supply line respectively, and is configured to output a third voltage signal from the third power supply line to the second drive signal output terminal under the control of the potential of the third node, and output a second voltage signal from the second power supply line to the second drive signal output terminal.

[0041] Optionally, the second output circuit is further electrically connected to a first control terminal, and the output terminal of the second output circuit is electrically connected to the second drive signal output terminal. The second output circuit is further configured to control the third voltage signal to be output to the second drive signal output terminal under the control of the first control signal from the first control terminal, and is configured to output the second voltage signal to the second drive signal output terminal under the control of the potential of the third node and the first control signal.

[0042] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a constant voltage circuit, and an output terminal of the second output circuit is electrically connected to the second drive signal output terminal through the constant voltage circuit. An input terminal of the constant voltage circuit is electrically connected to an output terminal of the second output circuit, and an output terminal of the constant voltage circuit is electrically connected to the second drive signal output terminal. The constant voltage circuit is configured to constant-voltage the signal output by the second output circuit, obtain a second scanning drive signal, and output the second scanning drive signal through the second drive signal output terminal.

[0043] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a first energy storage circuit and a second energy storage circuit. A first terminal of the first energy storage circuit is electrically connected to an output terminal of the second output circuit, and a second terminal of the first energy storage circuit is electrically connected to the second drive signal output terminal. A first terminal of the second energy storage circuit is electrically connected to an output terminal of the second output circuit, and a second terminal of the second energy storage circuit is electrically connected to the second drive signal output terminal. The first energy storage circuit and the second energy storage circuit are configured to store electrical energy.

[0044] Optionally, the first input circuit includes a seventh transistor, the second input circuit includes a first transistor and an eighth transistor, the first output circuit includes a third transistor, a fifth transistor, and a first capacitor, and the control circuit includes a sixth transistor, a ninth transistor, and a tenth transistor. The gate of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the second power supply line, and the second electrode of the first transistor is electrically connected to the second node. The gate of the eighth transistor is electrically connected to the third node, the first electrode of the eighth transistor is electrically connected to the first power supply line, and the second electrode of the eighth transistor is electrically connected to the second node. The gate of the seventh transistor is electrically connected to the first clock signal line, the first electrode of the seventh transistor is electrically connected to the input voltage terminal, and the second electrode of the seventh transistor is electrically connected to the third node. The gate of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the first power supply line, and the second electrode of the third transistor is electrically connected to the first drive signal output terminal. The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the first drive signal output terminal, and the second electrode of the fifth transistor is electrically connected to the second clock signal line. The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the first drive signal output terminal. The gate of the sixth transistor is electrically connected to the second clock signal line, the first electrode of the sixth transistor is electrically connected to the second electrode of the tenth transistor, and the second electrode of the sixth transistor is electrically connected to the third node. The gate of the tenth transistor is electrically connected to the second node, and the first electrode of the tenth transistor is electrically connected to the first power supply line. The gate of the ninth transistor is electrically connected to the second power supply line, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the first node.

[0045] Optionally, the second output circuit includes a second transistor and a fourth transistor, The gate of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the second power supply line, and the second electrode of the second transistor is electrically connected to the second drive signal output terminal, The gate of the fourth transistor is electrically connected to the third node, the first electrode of the fourth transistor is electrically connected to the third power supply line, and the second electrode of the fourth transistor is electrically connected to the second drive signal output terminal.

[0046] Optionally, the second output circuit includes a second transistor, a fourth transistor, an eleventh transistor, and a twelfth transistor, The gate of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the second electrode of the twelfth transistor, and the second electrode of the second transistor is electrically connected to the second drive signal output terminal, The gate of the fourth transistor is electrically connected to the third node, the first electrode of the fourth transistor is electrically connected to the third power supply line, and the second electrode of the fourth transistor is electrically connected to the second drive signal output terminal, The gate of the eleventh transistor is electrically connected to the first control terminal, the first electrode of the eleventh transistor is electrically connected to the third power supply line, and the second electrode of the eleventh transistor is electrically connected to the second drive signal output terminal, The gate of the twelfth transistor is electrically connected to the first control terminal, and the first electrode of the twelfth transistor is electrically connected to the second power supply line.

[0047] Optionally, the constant voltage circuit includes a thirteenth transistor and a fourteenth transistor, The gate of the thirteenth transistor is electrically connected to the output terminal of the second output circuit, the first electrode of the thirteenth transistor is electrically connected to the second power supply line, and the second electrode of the thirteenth transistor is electrically connected to the second drive signal output terminal, The gate of the 14th transistor is electrically connected to the output terminal of the second output circuit, the first electrode of the 14th transistor is electrically connected to the third power supply line, and the second electrode of the 14th transistor is electrically connected to the second drive signal output terminal.

[0048] Optionally, the first energy storage circuit includes a second capacitor, the second energy storage circuit includes a third capacitor, the first end of the second capacitor is electrically connected to the output terminal of the second output circuit, and the second end of the second capacitor is electrically connected to the second drive signal output terminal. The first end of the third capacitor is electrically connected to the output terminal of the second output circuit, and the second end of the third capacitor is electrically connected to the second drive signal output terminal.

[0049] The embodiment of the present disclosure further provides a display device including the above display substrate. Optionally, the display device according to at least one embodiment of the present disclosure further includes a timing controller, a scanning driver, and a data driver. The timing controller is electrically connected to the scanning driver and the data driver respectively, and is configured to provide corresponding control signals for each of the scanning driver and the data driver. The scanning driver is electrically connected to a plurality of rows of scanning lines respectively, and is configured to provide corresponding scanning signals for each of the plurality of rows of scanning lines. The data driver is electrically connected to a plurality of columns of data lines respectively, and is configured to provide corresponding data signals for each of the plurality of columns of data lines.

Brief Description of the Drawings

[0050]

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Embodiments for Carrying Out the Invention

[0051] Hereinafter, in connection with the drawings of the embodiments of the present disclosure, the technical aspects in the embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only some embodiments of the present disclosure, not all embodiments. Based on the examples in the present disclosure, all other examples obtained by those skilled in the art without creative labor belong to the protection scope of the present disclosure.

[0052] All transistors according to the embodiments of the present disclosure may be thin-film transistors, or field-effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two poles other than the gate of the transistor, one of the poles is called the first electrode and the other pole is called the second electrode.

[0053] During actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.

[0054] The display substrate according to the embodiments of the present disclosure includes a shift register provided on a base substrate, and the shift register includes a plurality of stages of drive circuits. The drive circuit includes a first input circuit, a second input circuit, a first output circuit, and a control circuit. The first output circuit is configured to provide a first scanning drive signal to a first drive signal output terminal under the control of the potential of the first node and the potential of the second node. The first input circuit is configured to input a signal to a third node under the control of a clock signal. The second input circuit is configured to input a signal from a power supply line to the second node under the control of the potential of the third node. The control circuit is configured to control the potential of the third node and the potential of the first node.

[0055] In at least one embodiment of the present disclosure, the power supply line includes a first power supply line and a second power supply line. The first input circuit is electrically connected to an input voltage terminal, a first clock signal line, and the third node respectively, and is configured to write an input voltage from the input voltage terminal to the third node under the control of a first clock signal from the first clock signal line. The second input circuit is electrically connected to the third node, the second power supply line, the second node, and the first power supply line respectively, and is configured to write a first voltage signal from the first power supply line to the second node under the control of the potential of the third node, and write a second voltage signal from the second power supply line to the second node. The first output circuit is electrically connected to the second node, the first node, the first power supply line, a second clock signal line, and a first drive signal output terminal respectively, and is configured to output a first voltage signal from the first power supply line to the first drive signal output terminal under the control of the potential of the second node, and output a second clock signal from the second clock signal line to the first drive signal output terminal under the control of the potential of the first node. The control circuit is electrically connected to the second node, the first power supply line, the second clock signal line, the third node, the first node, and the second power supply line respectively, and is configured to control to write a first voltage signal from the first power supply line to the third node under the control of the potential of the second node and a second clock signal from the second clock signal line, and control the conduction between the third node and the first node under the control of a second voltage signal from the second power supply line.

[0056] Regarding the drive circuit according to at least one embodiment of the present disclosure, during operation, the first input circuit is controlled to write an input voltage to the third node under the control of a first clock signal, the second input circuit controls the potential of the second node under the control of the potential of the third node, the control circuit controls the conduction between the third node and the first power supply line under the control of the potential of the second node and a second clock signal, and controls the conduction between the third node and the first node under the control of a second voltage signal. The first output circuit is controlled to output a first scanning drive signal to the first drive signal output terminal under the control of the potential of the first node and the potential of the second node.

[0057] As shown in FIG. 1, in at least one embodiment of the present disclosure, at least one embodiment of the drive circuit includes a first input circuit 11, a second input circuit 12, a first output circuit 13, and a control circuit 14. The first input circuit 11 is electrically connected to an input voltage terminal STV, a first clock signal line K1, and a third node N3 respectively, and is configured to write an input voltage from the input voltage terminal STV to the third node N3 under the control of a first clock signal from the first clock signal line K1. The second input circuit 12 is electrically connected to the third node N3, a second power supply line VGL, a second node N2, and the first power supply line VGH respectively, and is configured to write a first voltage signal from the first power supply line VGH to the second node N2 under the control of the potential of the third node N3, and write a second voltage signal from the second power supply line VGL to the second node N2. The first output circuit 13 is electrically connected to the second node N2, a first node N1, the first power supply line VGH, a second clock signal line K2, and a first drive signal output terminal GP respectively, and is configured to output a first voltage signal from the first power supply line VGH to the first drive signal output terminal GP under the control of the potential of the second node N2, and output a second clock signal from the second clock signal line K2 to the first drive signal output terminal GP under the control of the potential of the first node N1. The control circuit 14 is electrically connected to the second node N2, the first power supply line VGH, the second clock signal line K2, the third node N3, the first node N1, and the second power supply line VGL, respectively, and controls writing the first voltage signal from the first power supply line VGH to the third node N3 under the control of the potential of the second node N2 and the second clock signal from the second clock signal line K2, and is configured to control the conduction between the third node N3 and the first node N1 under the control of the second voltage signal from the second power supply line VGL.

[0058] In at least one embodiment of the present disclosure, the first voltage signal may be a first high voltage signal, and the second voltage signal may be a low voltage signal, but is not limited thereto.

[0059] In at least one embodiment of the driving circuit shown in FIG. 2, the second node N2 may be a second driving signal output terminal GN, and the second driving signal output terminal GN can be used to provide an N-type scanning driving signal, and the first driving signal output terminal can be used to provide a P-type scanning driving signal.

[0060] In at least one embodiment of the present disclosure, the N-type scanning driving signal is a scanning driving signal for turning on an N-type transistor, and the P-type scanning driving signal is a scanning driving signal for turning on a P-type transistor.

[0061] In at least one embodiment of the present disclosure, the driving circuit can output two types of scanning driving signals simultaneously.

[0062] As shown in FIG. 3, in addition to at least one embodiment of the driving circuit shown in FIG. 1, at least one embodiment of the driving circuit further includes a second output circuit 31. The second output circuit 31 is electrically connected to the third node N3, the second driving signal output terminal GN, the third power supply line VGH2, and the second power supply line VGL, respectively, and outputs the third voltage signal from the third power supply line VGH2 to the second driving signal output terminal GN under the control of the potential of the third node N3, and is configured to output the second voltage signal from the second power supply line VGL to the second driving signal output terminal GN.

[0063] In at least one embodiment of the present disclosure, the third voltage signal may be a second high voltage signal.

[0064] In at least one embodiment of the driving circuit shown in FIG. 3, during operation, a P-type scanning driving signal can be provided via the first driving signal output terminal GP, and an N-type scanning driving signal can be provided via the second driving signal output terminal GN.

[0065] In at least one embodiment of the present disclosure, optionally, the second output circuit is further electrically connected to a first control terminal, an output terminal of the second output circuit is electrically connected to a second driving signal output terminal, the second output circuit outputs the third voltage signal to the second driving signal output terminal under the control of a first control signal from the first control terminal, and is configured to control to output the second voltage signal to the second driving signal output terminal under the control of the potential of the third node and the first control signal.

[0066] During specific implementation, the first control terminal may be electrically connected to a first driving signal output terminal of an adjacent previous-stage driving circuit, and when the adjacent previous-stage driving circuit outputs a valid first scanning driving signal, the second output circuit is controlled to conduct between the second driving signal output terminal of the current-stage driving circuit and a third power supply line, and to disconnect between the second driving signal output terminal of the current-stage driving circuit and a second power supply line.

[0067] As shown in FIG. 4, in addition to at least one embodiment of the driving circuit shown in FIG. 3, at least one embodiment of the driving circuit further includes a constant voltage circuit 41, an output terminal of the second output circuit 31 is electrically connected to the second driving signal output terminal GN via the constant voltage circuit 41, an input terminal of the constant voltage circuit 41 is electrically connected to an output terminal of the second output circuit 31, an output terminal of the constant voltage circuit 41 is electrically connected to the second driving signal output terminal GN, and the constant voltage circuit 41 is configured to constant-voltage the signal output by the second output circuit 31 to obtain a second scanning driving signal and output it via the second driving signal output terminal GN.

[0068] In at least one embodiment of the drive circuit shown in FIG. 4, during operation, the constant voltage circuit 41 constant-voltagizes the signal output by the second output circuit 31 to obtain a second scanning drive signal.

[0069] As shown in FIG. 5, in addition to at least one embodiment of the drive circuit shown in FIG. 4, at least one embodiment of the drive circuit further includes a first energy storage circuit 51 and a second energy storage circuit 52. The first end of the first energy storage circuit 51 is electrically connected to the output end of the second output circuit 31, and the second end of the first energy storage circuit 51 is electrically connected to the second drive signal output end GN. The first end of the second energy storage circuit 52 is electrically connected to the output end of the second output circuit 31, and the second end of the second energy storage circuit 52 is electrically connected to the second drive signal output end GN. The first energy storage circuit 51 and the second energy storage circuit 52 are used to store electrical energy.

[0070] Optionally, the first input circuit includes a seventh transistor, the second input circuit includes a first transistor and an eighth transistor, the first output circuit includes a third transistor, a fifth transistor and a first capacitor, and the control circuit includes a sixth transistor, a ninth transistor and a tenth transistor. The gate of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the second power supply line, and the second electrode of the first transistor is electrically connected to the second node. The gate of the eighth transistor is electrically connected to the third node, the first electrode of the eighth transistor is electrically connected to the first power supply line, and the second electrode of the eighth transistor is electrically connected to the second node. The gate of the seventh transistor is electrically connected to the first clock signal line, the first electrode of the seventh transistor is electrically connected to the input voltage terminal, and the second electrode of the seventh transistor is electrically connected to the third node. The gate of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the first power supply line, and the second electrode of the third transistor is electrically connected to the first drive signal output terminal. The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the first drive signal output terminal, and the second electrode of the fifth transistor is electrically connected to the second clock signal line. The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the first drive signal output terminal. The gate of the sixth transistor is electrically connected to the second clock signal line, the first electrode of the sixth transistor is electrically connected to the second electrode of the tenth transistor, and the second electrode of the sixth transistor is electrically connected to the third node. The gate of the tenth transistor is electrically connected to the second node, and the first electrode of the tenth transistor is electrically connected to the first power supply line. The gate of the ninth transistor is electrically connected to the second power supply line, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the first node.

[0071] Optionally, the second output circuit includes a second transistor and a fourth transistor. The gate of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the second power supply line, and the second electrode of the second transistor is electrically connected to the second drive signal output terminal. The gate of the fourth transistor is electrically connected to the third node, the first electrode of the fourth transistor is electrically connected to the third power supply line, and the second electrode of the fourth transistor is electrically connected to the second drive signal output terminal.

[0072] Optionally, the second output circuit includes a second transistor, a fourth transistor, an eleventh transistor, and a twelfth transistor. The gate of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the second electrode of the twelfth transistor, and the second electrode of the second transistor is electrically connected to the second drive signal output terminal. The gate of the fourth transistor is electrically connected to the third node, the first electrode of the fourth transistor is electrically connected to the third power supply line, the second electrode of the fourth transistor is electrically connected to the second drive signal output terminal, the gate of the eleventh transistor is electrically connected to the first control terminal, the first electrode of the eleventh transistor is electrically connected to the third power supply line, and the second electrode of the eleventh transistor is electrically connected to the second drive signal output terminal. The gate of the twelfth transistor is electrically connected to the first control terminal, and the first electrode of the twelfth transistor is electrically connected to the second power supply line.

[0073] Optionally, the constant voltage circuit includes a thirteenth transistor and a fourteenth transistor. The gate of the thirteenth transistor is electrically connected to the output terminal of the second output circuit, the first electrode of the thirteenth transistor is electrically connected to the second power supply line, and the second electrode of the thirteenth transistor is electrically connected to the second drive signal output terminal. The gate of the fourteenth transistor is electrically connected to the output terminal of the second output circuit, the first electrode of the fourteenth transistor is electrically connected to the third power supply line, and the second electrode of the fourteenth transistor is electrically connected to the second drive signal output terminal.

[0074] Optionally, the first energy storage circuit includes a second capacitor, the second energy storage circuit includes a third capacitor, a first terminal of the second capacitor is electrically connected to an output terminal of the second output circuit, and a second terminal of the second capacitor is electrically connected to the second drive signal output terminal. A first terminal of the third capacitor is electrically connected to an output terminal of the second output circuit, and a second terminal of the third capacitor is electrically connected to the second drive signal output terminal.

[0075] As shown in FIG. 6, in at least one embodiment of the drive circuit shown in FIG. 1, the first input circuit 11 includes a seventh transistor T7, the second input circuit 12 includes a first transistor T1 and an eighth transistor T8, the first output circuit 13 includes a third transistor T3, a fifth transistor T5, and a first capacitor C1, and the control circuit 14 includes a sixth transistor T6, a ninth transistor T9, and a tenth transistor T10. A gate of the first transistor T1 is electrically connected to the third node N3, a source electrode of the first transistor T1 is electrically connected to a second power supply line VGL, and a drain electrode of the first transistor T1 is electrically connected to the second node N2. A gate of the eighth transistor T8 is electrically connected to the third node N3, a source electrode of the eighth transistor T8 is electrically connected to a first power supply line VGH, and a drain electrode of the eighth transistor T8 is electrically connected to the second node N2. A gate of the seventh transistor T7 is electrically connected to the first clock signal line K1, a source electrode of the seventh transistor T7 is electrically connected to the input voltage terminal STV, and a drain electrode of the seventh transistor T7 is electrically connected to the third node N3. A gate of the third transistor T3 is electrically connected to the second node N2, a source electrode of the third transistor T3 is electrically connected to the first power supply line VGH, and a drain electrode of the third transistor T3 is electrically connected to the first drive signal output terminal GP. The gate of the fifth transistor T5 is electrically connected to the first node N1, the source electrode of the fifth transistor T5 is electrically connected to the first drive signal output terminal GP, and the drain electrode of the fifth transistor T5 is electrically connected to the second clock signal line K2. The first electrode plate of the first capacitor C1 is electrically connected to the first node N1, and the second electrode plate of the first capacitor C1 is electrically connected to the first drive signal output terminal GP. The gate of the sixth transistor T6 is electrically connected to the second clock signal line K2, the source electrode of the sixth transistor T6 is electrically connected to the drain electrode of the tenth transistor T10, and the drain electrode of the sixth transistor T6 is electrically connected to the third node N3. The gate of the tenth transistor T10 is electrically connected to the second node N2, and the source electrode of the tenth transistor T10 is electrically connected to the first power supply line VGH. The gate of the ninth transistor T9 is electrically connected to the second power supply line VGL, the source electrode of the ninth transistor T9 is electrically connected to the third node N3, and the drain electrode of the ninth transistor T9 is electrically connected to the first node N1.

[0076] In at least one embodiment of the drive circuit shown in FIG. 6, T1 is an N-type transistor, and the transistors other than T1 are P-type transistors.

[0077] In at least one embodiment of the present disclosure, in order to stably hold the potential of the second node at a low potential at which T3 can be turned on, T1 can be set as an N-type transistor.

[0078] As shown in FIG. 7, in at least one embodiment of the drive circuit shown in FIG. 6 of the present disclosure, during operation, the drive cycle includes an input stage t1, an output stage t2, and a reset stage t3 set before and after the timing. In the input stage t1, K1 provides a low voltage signal, K2 provides a high voltage signal, STV provides a low voltage signal, T7 is turned on to change the potential of N3 to a low voltage, T8 is turned on to raise the potential of N2, T3 is disconnected, T9 is turned on, the potential of N1 is a low voltage signal, T5 is turned on, and GP outputs a high voltage signal. In the output stage t2, K1 provides a high voltage signal, K2 provides a low voltage signal, STV provides a high voltage signal, T7 is disconnected, the potential of N2 is maintained at a high voltage, T10 is disconnected, T6 is turned on, the potential of N3 is maintained at a low voltage, T5 is turned on, T3 is disconnected, and GP outputs a low voltage signal. In the reset stage t3, K1 provides a low voltage signal, K2 provides a high voltage signal, STV provides a high voltage signal, T7 is turned on to make the potential of N3 a high voltage, T1 is turned on to lower the potential of N2, T10 is turned on, T6 is disconnected, T9 is turned on, the potential of N1 is a high voltage, T3 is turned on, T5 is disconnected, and GP outputs a high voltage signal.

[0079] At least one embodiment of the driving circuit shown in FIG. 8 is different from at least one embodiment of the driving circuit shown in FIG. 6 in that the second node N2 is set to the second driving signal output terminal GN, and the second driving signal output terminal GN is used to output an N-type scanning driving signal.

[0080] At least one embodiment of the driving circuit shown in FIG. 9 is different from at least one embodiment of the driving circuit shown in FIG. 6 in that the driving circuit further includes a second output circuit 31. The second output circuit 31 includes a second transistor T2 and a fourth transistor T4. The gate of the second transistor T2 is electrically connected to the third node N3, the source electrode of the second transistor T2 is electrically connected to the second power supply line VGL, and the drain electrode of the second transistor T2 is electrically connected to the second driving signal output terminal GN. The gate of the fourth transistor T4 is electrically connected to the third node N3, the source electrode of the fourth transistor T4 is electrically connected to the third power supply line VGH2, and the drain electrode of the fourth transistor T4 is electrically connected to the second drive signal output terminal GN, which is different in this respect.

[0081] In at least one embodiment of the drive circuit shown in FIG. 9, T1 and T2 are N-type transistors, and the other transistors are P-type transistors, but it is not limited thereto.

[0082] FIG. 10 is an operation timing diagram of at least one embodiment of the drive circuit shown in FIG. 9.

[0083] As shown in FIG. 11, in at least one embodiment of the drive circuit shown in FIG. 3, the first input circuit includes a seventh transistor T7, the second input circuit includes a first transistor T1 and an eighth transistor T8, the first output circuit includes a third transistor T3, a fifth transistor T5 and a first capacitor C1, and the control circuit includes a sixth transistor T6, a ninth transistor T9 and a tenth transistor T10. The gate G1 of the first transistor T1 is electrically connected to the third node N3, the first electrode S1 of the first transistor T1 is electrically connected to the second power supply line VGL, and the second electrode D1 of the first transistor T1 is electrically connected to the second node N2. The gate G8 of the eighth transistor T8 is electrically connected to the third node N3, the first electrode S8 of the eighth transistor T8 is electrically connected to the first power supply line VGH, and the second electrode D8 of the eighth transistor T8 is electrically connected to the second node N2. The gate G7 of the seventh transistor T7 is electrically connected to the first clock signal line K1, the first electrode S7 of the seventh transistor T7 is electrically connected to the input voltage terminal STV, and the second electrode D7 of the seventh transistor T7 is electrically connected to the third node N3. The gate G3 of the third transistor T3 is electrically connected to the second node N2, the first electrode S3 of the third transistor T3 is electrically connected to the first power supply line VGH, and the second electrode D3 of the third transistor T3 is electrically connected to the first drive signal output terminal GP. The gate G5 of the fifth transistor T5 is electrically connected to the first node N1, the first electrode S5 of the fifth transistor T5 is electrically connected to the first drive signal output terminal GP, and the second electrode D5 of the fifth transistor T5 is electrically connected to the second clock signal line K2. The first plate C1a of the first capacitor C1 is electrically connected to the first node N1, and the second plate C1b of the first capacitor C1 is electrically connected to the first drive signal output terminal GP. The gate G6 of the sixth transistor T6 is electrically connected to the second clock signal line K2, the first electrode S6 of the sixth transistor T6 is electrically connected to the second electrode D10 of the tenth transistor T10, and the second electrode D6 of the sixth transistor T6 is electrically connected to the third node N3. The gate G10 of the tenth transistor T10 is electrically connected to the second node N2, and the first electrode S10 of the tenth transistor T10 is electrically connected to the first power supply line VGH. The gate G9 of the ninth transistor T9 is electrically connected to the second power supply line VGL, the first electrode S9 of the ninth transistor T9 is electrically connected to the third node N3, and the second electrode D9 of the ninth transistor T9 is electrically connected to the first node N1. The second output circuit includes a second transistor T2 and a fourth transistor T4. The gate G2 of the second transistor T2 is electrically connected to the third node N3, the first electrode S2 of the second transistor T2 is electrically connected to the second power supply line VGL, and the second electrode D2 of the second transistor T2 is electrically connected to the second drive signal output terminal GN. The gate G4 of the fourth transistor T4 is electrically connected to the third node N3, the first electrode S4 of the fourth transistor T4 is electrically connected to the third power supply line VGH2, and the second electrode D4 of the fourth transistor T4 is electrically connected to the second drive signal output terminal GN.

[0084] In at least one embodiment of the drive circuit shown in FIG. 11, T1 and T2 are N-type transistors, and the other transistors are P-type transistors, but the present invention is not limited thereto.

[0085] At least one embodiment of the drive circuit shown in FIG. 12 is different from at least one embodiment of the drive circuit shown in FIG. 9 in that The second output circuit 31 includes a second transistor T2, a fourth transistor T4, an eleventh transistor T11, and a twelfth transistor T12. The gate of the second transistor T2 is electrically connected to the third node N3, the source electrode of the second transistor T2 is electrically connected to the drain electrode of the twelfth transistor T12, and the drain electrode of the second transistor T2 is electrically connected to the second drive signal output terminal GN. The gate of the fourth transistor T4 is electrically connected to the third node N3, the source electrode of the fourth transistor T4 is electrically connected to the third power supply line VGH2, and the drain electrode of the fourth transistor T4 is electrically connected to the second drive signal output terminal GN. The gate of the eleventh transistor T11 is electrically connected to the first control terminal, the first control terminal is electrically connected to the first drive signal output terminal GP(n - 1) of the adjacent previous-stage drive circuit, the source electrode of the eleventh transistor T11 is electrically connected to the third power supply line VGH2, and the drain electrode of the eleventh transistor T11 is electrically connected to the second drive signal output terminal GN. The gate of the twelfth transistor T12 is electrically connected to the first drive signal output terminal GP(n - 1) of the adjacent previous-stage drive circuit, and the source electrode of the twelfth transistor T12 is electrically connected to the second power supply line VGL.

[0086] In at least one embodiment of the drive circuit shown in FIG. 12, T2, T1, and T12 are N-type transistors, and the other transistors are P-type transistors, but are not limited thereto.

[0087] FIG. 13 is an operation timing diagram of at least one embodiment of the drive circuit shown in FIG. 12.

[0088] At least one embodiment of the drive circuit shown in FIG. 14 is relative to at least one embodiment of the drive circuit shown in FIG. 12 In at least one embodiment of the drive circuit shown in FIG. 14, it further includes a constant voltage circuit 41, and the drain electrodes of the second transistor T2, the fourth transistor T4, and the eleventh transistor T11 are all electrically connected to the second drive signal output terminal GN through the constant voltage circuit 41. The constant voltage circuit 41 includes a thirteenth transistor T13 and a fourteenth transistor T14. The gate of the thirteenth transistor T13 is electrically connected to the drain electrode of the second transistor T2. The source electrode of the thirteenth transistor T13 is electrically connected to the second power supply line VGL. The drain electrode of the thirteenth transistor T13 is electrically connected to the second drive signal output terminal GN. The gate of the fourteenth transistor T14 is electrically connected to the drain electrode of the second transistor T2. The source electrode of the fourteenth transistor T14 is electrically connected to the third power supply line VGH2. The drain electrode of the fourteenth transistor T14 is electrically connected to the second drive signal output terminal GN, which is different in this regard.

[0089] In at least one embodiment shown in FIG. 14, T13 is a P-type transistor and T14 is an N-type transistor.

[0090] At least one embodiment of the drive circuit shown in FIG. 15 is relative to at least one embodiment of the drive circuit shown in FIG. 14 In at least one embodiment of the drive circuit shown in FIG. 15, it further includes a second capacitor C2 and a third capacitor C3. The first end of the second capacitor C2 is electrically connected to the drain electrode of the second transistor T2, and the second end of the second capacitor C2 is electrically connected to the second drive signal output terminal GN. The first end of the third capacitor C3 is electrically connected to the drain electrode of the second transistor T2, and the second end of the third capacitor C3 is electrically connected to the second drive signal output terminal GN, which is different in this regard.

[0091] FIG. 16 is an operation timing diagram of at least one embodiment of the drive circuit shown in FIG. 15.

[0092] The display substrate according to an embodiment of the present disclosure includes a shift register provided on a base substrate. The shift register includes a plurality of stages of drive circuits. The drive circuit includes a first input circuit, a second input circuit, a first output circuit, and a control circuit. The first output circuit is configured to provide a first scanning drive signal to a first drive signal output terminal under the control of the potential of a first node and the potential of a second node. The first input circuit is configured to input a signal to a third node under the control of a clock signal. The second input circuit is configured to input a signal from a power supply line to the second node under the control of the potential of the third node. The control circuit is configured to control the potential of the third node and the potential of the first node. A plurality of stages of the drive circuits are provided in the drive circuit region of the base substrate. One stage of the drive circuit region among the plurality of stages of the drive circuits includes a first region and a second region. The first region is provided with a first type of transistor included in the drive circuit, and the second region is provided with a second type of transistor included in the drive circuit. One side of the first region is the side far from the second region of the power supply line, and the other side of the first region is the side close to the second region of the active layer of the first type of transistor close to the second region. One side of the second region is the side far from the first region of the power supply line, and the other side of the second region is the side close to the second region of the active layer of the first type of transistor close to the second region.

[0093] In at least one embodiment of the present disclosure, as shown in FIG. 17, the power supply lines may include a first power supply line VGH, a second power supply line VGL, and a third power supply line VGH2. One side Y1-1 of the first region Y1 may be the side far from the second region Y2 of the second power supply line VGL. One side Y2-1 of the second region Y2 may be the side far from the first region Y1 of the third power supply line VGH2.

[0094] Optionally, the first type of transistor may be an N-type transistor, and the second type of transistor may be a P-type transistor, but is not limited thereto.

[0095] In an embodiment of the present disclosure, in order to realize the convenience of the manufacturing process, and low parasitic capacitance and wiring electrical resistance, or to shorten the length of some connection wirings, N-type transistors are arranged in one region, and P-type transistors are arranged in another region.

[0096] In at least one embodiment of the present disclosure, the driving circuit region is a region where a plurality of stages of driving circuits are provided, and one stage of driving circuit region may be a region where one stage of driving circuit is provided, but is not limited thereto.

[0097] FIG. 17 is a layout diagram of a part of the driving circuit shown in FIG. 9, where VGH represents the first power supply line, VGL represents the second power supply line, VGH2 represents the third power supply line, A21 represents the first active layer pattern of the second transistor T2, A22 represents the second active layer pattern of the second transistor T2, and A1 represents the active layer of the first transistor T1.

[0098] In FIG. 17, the first power supply line VGH, the second power supply line VGL, and the third power supply line VGH2 may be included in the first source-drain metal layer, A21, A22, and A1 may be included in the second semiconductor layer, and the second semiconductor layer may be fabricated from an oxide. For example, the second semiconductor layer may be fabricated from IGZO (indium gallium zinc oxide).

[0099] In FIG. 17, what is denoted as Y1 is the first region, what is denoted as Y2 is the second region, the left side of the first region Y1 is the side far from the second region Y2 of the second power line VGL, and the right side of the first region Y1 is the side close to the second region Y2 of the active layer A1 of the first transistor T1. The first type of transistor on the side close to the second region is the first transistor T1, and the first transistor T1 is the N-type transistor closest to the second region provided in the first region Y1.

[0100] In at least one embodiment of the present disclosure, the first type of transistor on the side close to the second region may be the first type of transistor closest to the second region provided in the first region.

[0101] In FIG. 17, the right side of the second region Y2 is the side far from the first region Y1 of the third power line VGH2, and the left side of the second region Y2 is the side close to the second region Y2 of the active layer A1 of the first transistor T1.

[0102] Optionally, the power line includes a second power line, and the second input circuit is configured to input a second voltage signal from the second power line to the second node under the control of the potential of the third node. X1 / X3≥0.52, where X1 is the width of the first region in the first direction, and X3 is the width of the second region in the first direction. The first direction is a direction intersecting the extending direction of the second power line.

[0103] In at least one embodiment of the present disclosure, the first direction may be a horizontal direction, and the extending direction of the first power line may be a vertical direction, but is not limited thereto.

[0104] In FIG. 17, what is denoted as X1 is the width of the first region Y1 in the first direction, and what is denoted as X3 is the width of the second region Y2 in the first direction. In order to realize a narrow frame, X1 / X3 can be set to 0.52 or more, but is not limited thereto.

[0105] Optionally, the power line includes a first power line, and the second input circuit is configured to input a first voltage signal from the first power line to the second node under the control of the potential of the third node. X1 / X3≥0.21, where X1 is the width of the first region in the first direction, and X3 is the width of the second region in the first direction. The first direction is a direction intersecting the extending direction of the first power line.

[0106] FIG. 18 is a layout diagram of a part of the driving circuit shown in FIG. 9, where the first power line is denoted as VGH, the second power line is denoted as VGL, the third power line is denoted as VGH2, the first active layer pattern of the second transistor T2 is denoted as A21, the second active layer pattern of the second transistor T2 is denoted as A22, and the active layer of the first transistor T1 is denoted as A1.

[0107] In FIG. 18, the first power line VGH, the second power line VGL, and the third power line VGH2 may be included in the first source-drain metal layer, A21, A22, and A1 may be included in the second semiconductor layer, and the second semiconductor layer may be fabricated from an oxide. For example, the second semiconductor layer may be fabricated from IGZO (indium gallium zinc oxide).

[0108] In FIG. 18, the first region is denoted as Y1, the second region is denoted as Y2, the left side of the first region Y1 is the side far from the second region Y2 of the first power line VGH, and the right side of the first region Y1 is the side close to the second region Y2 of the active layer A1 of the first transistor. The first transistor is the N-type transistor closest to the second region Y2 provided in the first region Y1.

[0109] In FIG. 18, the right side of the second region Y2 is the side far from the first region Y1 of the third power line VGH2, and the left side of the second region Y2 is the side close to the second region Y2 of the active layer A1 of the first transistor T1.

[0110] In FIG. 18, what is denoted as X1 is the width in the first direction of the first region Y1, and what is denoted as X3 is the width in the first direction of the second region Y2. In order to realize a narrow frame, X1 / X3 can be set to 0.21 or more, but is not limited thereto.

[0111] In FIG. 18, what is denoted as Y1-1 is one side of the first region Y1, and what is denoted as Y2-1 is one side of the second region Y2.

[0112] In FIGS. 17 and 18, the ranges of the first region Y1 and the second region Y2 are shown, the boundary in the first direction is clear, and the boundary in the second direction is the height of a one-stage drive circuit. The height of the one-stage drive circuit will be described later.

[0113] In at least one embodiment of the present disclosure, the second direction may be the extending direction of each power line, but is not limited thereto.

[0114] As shown in FIG. 17, what is denoted as F1 may be the first direction, and what is denoted as F2 may be the second direction.

[0115] In at least one embodiment of the present disclosure, the first type of transistor is an N-type transistor, and the second type of transistor is a P-type transistor. The distance between at least one of the N-type transistors and the second power line is smaller than the distance between the P-type transistor and the second power line.

[0116] In at least one embodiment corresponding to FIGS. 27, 38, 48, and 59, the distance between the second transistor and the second power line VGL is smaller than the distance between each P-type transistor (the P-type transistor may be the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, or the tenth transistor T10) and the second power line VGL.

[0117] In a specific implementation, since the second power supply line VGL is provided on the side far from each of the P-type transistors of the second transistor, the distance between the second transistor and the second power supply line VGL is smaller than the distance between the P-type transistor and the second power supply line VGL.

[0118] Optionally, the second input circuit includes a first transistor. The gate of the first transistor is electrically connected to the third node. The first electrode of the first transistor is electrically connected to the second power supply line. The second electrode of the first transistor is electrically connected to the second node. The first transistor is a transistor of the first type. WT1 / X1 ≥ 0.258 Here, WT1 is the width of the active layer of the first transistor along the first direction.

[0119] In FIG. 18, WT1 denotes the width of the active layer A1 of the first transistor T1 in the first direction, X1 is the width of the first region Y1 in the first direction, and the ratio of WT1 to X1 can be 0.258 or more, but is not limited thereto.

[0120] In FIG. 18, WT2-1 denotes the width of the first active layer pattern A21 of the second transistor along the first direction, and WT2-2 denotes the width of the second active layer pattern A22 of the second transistor along the first direction.

[0121] In at least one embodiment of the present disclosure, the driving circuit further includes a second output circuit. The second output circuit is configured to control to output a second scanning driving signal through a second driving signal output end under the control of the potential of the third node. The second output circuit includes a second transistor. The gate of the second transistor is electrically connected to the third node. The first electrode of the second transistor is electrically connected to the second power supply line. The second electrode of the second transistor is electrically connected to the second driving signal output end. The second transistor is a transistor of the first type. WT2 / X1 ≥ 0.33 WT2 is the width along the first direction of the active layer of the second transistor, and X1 is the width of the first region in the first direction.

[0122] In FIG. 17, what is denoted as A21 is the first active layer pattern of the second transistor T2, what is denoted as A22 is the second active layer pattern of the second transistor T2, what is denoted as WT2-1 is the width along the first direction of A21, what is denoted as WT2-2 is the width along the first direction of A22, the active layer of the second transistor T2 includes the first active layer pattern A21 of the second transistor T2 and the second active layer pattern A22 of the second transistor T2, the width WT2 along the first direction of the active layer of the second transistor T2 is the sum value of WT2-1 and WT2-2, and the ratio between WT2 and X1 can be set to 0.33 or more, but is not limited thereto.

[0123] Optionally, the second input circuit includes a first transistor, the gate of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the second power line, the second electrode of the first transistor is electrically connected to the second node, the drive circuit further includes a second output circuit, the second output circuit is configured to control to output a second scanning drive signal via a second drive signal output terminal under the control of the potential of the third node, the second output circuit includes a second transistor, the gate of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the second power line, the second electrode of the second transistor is electrically connected to the second drive signal output terminal, and both the first transistor and the second transistor are transistors of the first type. WT2 / WT1≧3.25, WT1 is the width along the first direction of the active layer of the first transistor, and WT2 is the width along the first direction of the active layer of the second transistor.

[0124] In at least one embodiment of the present disclosure, the ratio between the width WT2 of the active layer of the second transistor along the first direction and the width WT1 of the active layer of the first transistor along the first direction can be set to 3.25 or more, but is not limited thereto.

[0125] In at least one embodiment of the present disclosure, the display substrate further includes a group of clock signal lines provided in the driving circuit region, and the group of clock signal lines is configured to provide the clock signal. The active layer of at least one first-type transistor is located between the group of clock signal lines and the power supply line in the first direction. The overlapping area between the orthographic projection of the active layer of at least one first-type transistor onto the base substrate and the orthographic projection of the power supply line onto the base substrate is 5 / 6 or less of the area of the active layer of the at least one first-type transistor.

[0126] In at least one embodiment of the display substrate shown in FIG. 48 and at least one embodiment of the display substrate shown in FIG. 59, the active layer of the second transistor T2 is located between the group of clock signal lines and the first power supply line VGH in the first direction, and the group of clock signal lines includes a first clock signal line and a second clock signal line. The overlapping area between the orthographic projection of the active layer A1 of the first transistor T1 onto the base substrate and the orthographic projection of the first power supply line VGH onto the base substrate is 5 / 6 or less of the area of the active layer A1 of the first transistor T1.

[0127] Optionally, the ratio between the length of the active layer of at least one first-type transistor along the second direction and the height of the driving circuit is 0.75 or less.

[0128] As shown in FIG. 17, the ratio between the length of the active layer A1 of the first transistor along the second direction and the height H1 of the first region Y1 in the second direction is 0.75 or less, and the height H1 of the first region Y1 in the second direction can be the height of the driving circuit.

[0129] In at least one embodiment of the present disclosure, the second direction may be, but is not limited to, the vertical direction.

[0130] In at least one embodiment of the present disclosure, the display substrate further includes a first active layer provided in the second region, the first active layer includes a first active portion, two second active portions, and two third active portions, and the display substrate further includes a second output circuit. The first active portion functions as the active layer of the third transistor, the two second active portions function as the active layers of the fourth transistors, and the two third active portions function as the active layers of the fifth transistors. The third transistor is a transistor that outputs a first voltage signal provided by the first output circuit, the fifth transistor is a transistor that outputs a clock signal provided by the first output circuit, and the fourth transistor is a transistor that outputs a third voltage signal provided by the second output circuit. The channel area of the n-th transistor is ARn, and ARn ≥ 2(n - 1)i, where n is 1, 2, or 3, and i is the unit channel area.

[0131] In at least one embodiment of the present disclosure, when n is equal to 1, the channel area AR1 of the first transistor may be equal to or greater than i; when n is equal to 2, the channel area AR2 of the second transistor may be equal to or greater than 2i; and when n is equal to 3, the channel area AR3 of the third transistor may be equal to 4i.

[0132] In FIG. 19, what is denoted as A3 is the first active portion, what is denoted as A41 is the first second active portion, what is denoted as A42 is the second second active portion, what is denoted as A51 is the first third active portion, what is denoted as A52 is the second third active portion, what is denoted as A8 is the active layer of the eighth transistor T8, what is denoted as A10 is the active layer of the tenth transistor T10, what is denoted as A6 is the active layer of the sixth transistor T6, what is denoted as A7 is the active layer of the seventh transistor T7, and what is denoted as A9 is the active layer of the ninth transistor T9, and A8, A10, and A6 are continuous with each other.

[0133] A3 functions as the active layer of the third transistor T3, A41 and A42 function as the active layers of the fourth transistor T4, and A51 and A52 function as the active layers of the fifth transistor T5.

[0134] In at least one embodiment shown in FIG. 19, A3, A41, A42, A51, A52, A8, A10, A6, A7, and A9 are included in the first semiconductor layer, and the first semiconductor layer may be a low-temperature polysilicon semiconductor layer, but is not limited thereto.

[0135] Optionally, the area P1 of the first active portion is p, the sum P2 of the areas of the two second active portions is 2p or more and 3p or less, and the sum P3 of the areas of the two third active portions is 3p or more and 4p or less.

[0136] In at least one embodiment shown in FIG. 19, the area P1 of A3 is p, the sum of the areas of A41 and A42 is P2, the sum of the areas of A51 and A52 is P3, P2 may be 2p or more and 3p or less, and P3 may be 3p or more and 4p or less.

[0137] FIG. 20 is a circuit diagram of at least one embodiment of a pixel circuit, FIG. 21 is a circuit diagram of at least one embodiment of a pixel circuit, and FIG. 22 is a circuit diagram of at least one embodiment of a pixel circuit. In FIGS. 20, 21, and 22, the pixel circuit may be an LTPO (low-temperature polycrystalline oxide) pixel circuit.

[0138] In FIG. 20, M1 is denoted as the first reset transistor, M2 is denoted as the threshold compensation transistor, M3 is denoted as the driving transistor, M4 is denoted as the data writing transistor, M5 is denoted as the first light emission control transistor, M6 is denoted as the second light emission control transistor, M7 is denoted as the second reset transistor, Cst is denoted as the storage capacitor, and E0 is denoted as the organic light emitting diode. The one denoted as VDD is the high voltage terminal, the one denoted as E1 is the light emission control line, the one denoted as GL is the scanning line, the one denoted as R1 is the first reset control terminal, the one denoted as R2 is the second reset control terminal, the one denoted as DL is the data line, the one denoted as S0 is the compensation control terminal, the one denoted as I1 is the first initial voltage terminal, and the one denoted as I2 is the second initial voltage terminal.

[0139] The first drive signal output terminal GP in the drive circuit is used to provide a signal to the gate of the data writing transistor M4, and the second drive signal output terminal GN in the drive circuit is used to provide a signal to the gate of the threshold compensation transistor M2 and the gate of the first reset transistor M1.

[0140] In at least one embodiment shown in FIG. 20, M1 and M2 may be N-type transistors, and M3, M4, M5, M6 and M7 may all be P-type transistors.

[0141] In FIG. 21, the one denoted as M1 is the first reset transistor, the one denoted as M2 is the threshold compensation transistor, the one denoted as M3 is the drive transistor, the one denoted as M4 is the data writing transistor, the one denoted as M5 is the first light emission control transistor, the one denoted as M6 is the second light emission control transistor, the one denoted as M7 is the second reset transistor, the one denoted as M8 is the third reset transistor, the one denoted as Cst is the storage capacitor, and the one denoted as E0 is the organic light emitting diode. The one denoted as VDD is the high voltage terminal, the one denoted as E1 is the light emission control line, the one denoted as GL is the scanning line, the one denoted as R1 is the first reset control terminal, the one denoted as R2 is the second reset control terminal, the one denoted as DL is the data line, the one denoted as S0 is the compensation control terminal, the one denoted as I1 is the first initial voltage terminal, the one denoted as I2 is the second initial voltage terminal, the one denoted as I3 is the third initial voltage terminal, and the one denoted as R3 is the third reset control terminal.

[0142] The first drive signal output terminal GP in the drive circuit is used to provide a signal to the gate of the data writing transistor M4, and the second drive signal output terminal GN in the drive circuit is used to provide a signal to the gates of the threshold compensation transistor M2 and the first reset transistor M1.

[0143] In at least one embodiment shown in FIG. 21, M1 and M2 can be N-type transistors, and M3, M4, M5, M6, M7, and M8 can all be P-type transistors.

[0144] In FIG. 22, what is denoted as M1 is the first reset transistor, what is denoted as M2 is the threshold compensation transistor, what is denoted as M3 is the drive transistor, what is denoted as M4 is the data writing transistor, what is denoted as M5 is the first light emission control transistor, what is denoted as M6 is the second light emission control transistor, what is denoted as M7 is the second reset transistor, what is denoted as Cst is the storage capacitor, and what is denoted as E0 is the organic light emitting diode. What is denoted as VDD is the high voltage terminal, what is denoted as E1 is the light emission control line, what is denoted as GL is the scanning line, what is denoted as R1 is the first reset control terminal, what is denoted as DL is the data line, what is denoted as S0 is the compensation control terminal, what is denoted as I1 is the first initial voltage terminal, and what is denoted as I2 is the second initial voltage terminal.

[0145] The first drive signal output terminal GP in the drive circuit is used to provide a signal to the gate of the data writing transistor M4, and the second drive signal output terminal GN in the drive circuit is used to provide a signal to the gates of the threshold compensation transistor M2 and the first reset transistor M1.

[0146] At least one embodiment of the pixel circuit shown in FIG. 22 is different from at least one embodiment of the pixel circuit shown in FIG. 20 in that M7 is an N-type transistor and the gate of M7 is electrically connected to the light emission control line E1.

[0147] In at least one embodiment shown in FIG. 22, M1, M2, and M7 may be N-type transistors, and M3, M4, M5, and M6 may all be P-type transistors.

[0148] In FIGS. 20, 21, and 22, what is denoted as Q1 is the first control node, and the first control node Q1 is electrically connected to the gate of the driving transistor M3.

[0149] In the data writing process of the pixel circuit, the data signal is written to the gate of the driving transistor M3 through the turned-on M4, M3, and M2. In this process, the duration for which the potential of the gate of M4 remains at a low voltage is significantly shorter than the duration for which the potential of the gate of M2 remains at a high voltage. That is, the duration of data writing is determined by the duration for which the potential of the scanning signal from the scanning line GL remains at a low voltage, and the said scanning signal needs to have a short rise and a short fall. That is, the duration of data writing is determined by the duration for which the potential of the first scanning driving signal from the first driving signal output terminal GP remains at a low voltage, and is raised by the potential of the first scanning driving signal to end the data writing process. In the I-V curve (current-voltage curve), the larger the voltage V, the more prominent the warp becomes. For example, when the voltage V is greater than 5V, the leakage current also increases. Here, since the rise of the first scanning driving signal needs to be small, the first voltage signal output by the third transistor T3 (the first voltage signal is a signal from the first power supply line VGH) is smaller. The third voltage signal output by the fourth transistor T4 (the third voltage signal is a signal from the third power supply line VGH2) may have a fall as its high-potential holding time is long. And the larger the third voltage signal output by the third transistor T3, the more advantageous it is for the sufficient turn-on of the threshold compensation transistor M2 and for the high-speed writing of the data signal. The same applies to the signal provided by the second driving signal output terminal GN to the gate of the first reset transistor M1. The larger the third voltage signal output by the third transistor T3, the more advantageous it is for the high-speed writing of the first initial voltage from the first initial voltage terminal to the first control node Q1. In at least one embodiment of the present disclosure, the voltage value of the third voltage signal from the third power supply line VGH2 may be greater than the voltage value of the first voltage signal from the first power supply line VGH. For example, the voltage value of the third voltage signal from the third power supply line VGH2 may be 1.4 times or more the voltage value of the first voltage signal from the first power supply line VGH.

[0150] In at least one embodiment of the present disclosure, the voltage value of the first voltage signal from the first power supply line VGH may be 5V, and the voltage value of the third voltage signal from the third power supply line VGH2 may be 7V, 7.5V or 8V, but is not limited thereto.

[0151] In at least one embodiment of the present disclosure, the display substrate may include a first semiconductor layer, a first gate metal layer, a second semiconductor layer, a second gate metal layer, and a third gate metal layer. The bottom gate of the N-type transistor and the top gate of the P-type transistor can be fabricated from the first gate metal layer. The gate of the N-type transistor has a structure of a top gate plus a bottom gate. Since the problem of threshold voltage drift occurs after long-term use of the oxide transistor, the structure of the top gate plus the bottom gate can stabilize the threshold voltage, and particularly in the case of low-frequency driving, leakage can be effectively prevented.

[0152] Optionally, the first semiconductor layer may be a low-temperature polysilicon semiconductor layer, and the second semiconductor layer may be an oxide semiconductor layer, but is not limited thereto.

[0153] During specific implementation, when the gate of the N-type transistor needs to be closer to the oxide semiconductor layer, the bottom gate of the N-type transistor may be fabricated using the second gate metal layer.

[0154] In at least one embodiment of the present disclosure, the bottom gate of the N-type transistor may be included in the first gate metal layer, the top gate of the N-type transistor may be included in the third gate metal layer, or the bottom gate of the N-type transistor may be included in the second gate metal layer, the top gate of the N-type transistor may be included in the third gate metal layer, or the bottom gate of the N-type transistor may be included in the first gate metal layer, the top gate of the N-type transistor may be included in the second gate metal layer, but is not limited thereto.

[0155] FIG. 23 is a schematic diagram of a first semiconductor layer, a second semiconductor layer, a first gate metal layer, and a second gate metal layer in a layout diagram of a driving circuit in at least one embodiment of a display substrate.

[0156] In at least one embodiment of the present disclosure, the first semiconductor layer, the first gate metal layer, the second semiconductor layer, and the second gate metal layer may be sequentially stacked and installed along a direction away from the base substrate, or the first semiconductor layer, the first gate metal layer, the second gate metal layer, and the second semiconductor layer may be sequentially stacked and installed along a direction away from the base substrate.

[0157] In FIG. 23, what is denoted as C1a is the first electrode plate of the first capacitor C1, and the first electrode plate C1a of C1 is included in the second gate metal layer.

[0158] FIG. 24 is a layout diagram of the first gate metal layer in FIG. 23.

[0159] In FIG. 24, what is denoted as G21 is the bottom gate of T2, what is denoted as G11 is the bottom gate of T1, G21 and G11 are integrally formed, compared with the gate of a P-type transistor, the gate area of T1 and the gate area of T2 are large, covering all of the middle portions of the active layer of T1 and the active layer of T2. Since the oxide is sensitive to light, the bottom gate G21 of T2 and the bottom gate G11 of T1 are used not only as gates but also for light shielding.

[0160] In FIG. 24, what is denoted as G41 is the first gate pattern of T4, what is denoted as G42 is the second gate pattern of T4, what is denoted as G511 is the first gate pattern of T5, G512 is the second gate pattern of T5, what is denoted as G521 is the third gate pattern of T5, what is denoted as G522 is the fourth gate pattern of T5, G41 and G42 are integrally formed, and G511, G512, G521, and G522 are integrally formed. What is denoted as G21 is the bottom gate of T2, what is denoted as G11 is the bottom gate of T1, what is denoted as G3 is the gate of T3, what is denoted as G6 is the gate of T6, what is denoted as G7 is the gate of T7, what is denoted as G8 is the gate of T8, what is denoted as G9 is the gate of T9, and what is denoted as G10 is the gate of T10.

[0161] Figure 25 is a schematic layout diagram in which a third gate metal layer is added in addition to Figure 23.

[0162] In Figure 25, what is denoted as C1b is the second electrode plate of the first capacitor C1, what is denoted as K13 is the third clock signal line portion included in the first clock signal line, and what is denoted as K23 is the third clock signal line portion included in the second clock signal line.

[0163] Figure 32 is a layout diagram of the third gate metal layer in Figure 27. In Figure 32, what is denoted as G12 is the upper gate of T1, and what is denoted as C1b is the second electrode plate of the first capacitor C1.

[0164] As shown in Figure 32, the first gate pattern included in the upper gate of the second transistor T2 is denoted as G221, the second gate pattern included in the upper gate of the second transistor T2 is denoted as G222, the third gate pattern included in the upper gate of the second transistor T2 is denoted as G223, the fourth gate pattern included in the upper gate of the second transistor T2 is denoted as G224, the fifth gate pattern included in the upper gate of the second transistor T2 is denoted as G225, and the sixth gate pattern included in the upper gate of the second transistor T2 is denoted as G226.

[0165] As shown in Figure 32, G221, G222, G223, G224, G225, G226, and G12 can be integrally formed.

[0166] In Figure 32, what is denoted as K13 is the third clock signal line portion included in the first clock signal line, and what is denoted as K23 is the third clock signal line portion included in the second clock signal line.

[0167] Figure 26 is a schematic layout diagram in which a first source-drain metal layer is additionally provided in addition to Figure 25.

[0168] As shown in Figure 26, what is denoted as VGH is the first power line, what is denoted as VGL is the second power line, and what is denoted as VGH2 is the third power line.

[0169] Figure 33 is a layout diagram of the first source-drain metal layer in Figure 27. In Figure 33, what is denoted as VGH is the first power line, what is denoted as VGL is the second power line, what is denoted as VGH2 is the third power line, what is denoted as K11 is the first clock signal line part included in the first clock signal line, and what is denoted as K21 is the first clock signal line part included in the second clock signal line.

[0170] As shown in Figures 26 and 33, the first source-drain metal layer functions as if it fabricates the first power line VGH, the second power line VGL, the third power line VGH2, K11, K21, the transfer electrode, and the source-drain electrodes of the transistor. As can be seen from Figure 26, the first clock signal line is fabricated by the third gate metal layer and the first source-drain metal layer, the second clock signal line is fabricated by the third gate metal layer and the first source-drain metal layer, and the first clock signal line part and the third clock signal line part are electrically connected via vias. Since the electrical resistance is inversely proportional to the area, by fabricating the clock signal line using both metal layers, the area can be significantly increased, and furthermore, the electrical resistance can be significantly reduced.

[0171] FIG. 27 is a schematic diagram in which a second source-drain metal layer and vias are added in addition to the layout diagram shown in FIG. 26. FIG. 28 is a layout diagram of the first semiconductor layer in FIG. 27, FIG. 29 is a layout diagram of the first gate metal layer in FIG. 27, FIG. 30 is a layout diagram of the second semiconductor layer in FIG. 27, FIG. 31 is a layout diagram of the second gate metal layer in FIG. 27, FIG. 32 is a layout diagram of the third gate metal layer in FIG. 27, FIG. 33 is a layout diagram of the first source-drain metal layer in FIG. 27, and FIG. 34 is a layout diagram of the second source-drain metal layer in FIG. 27.

[0172] In at least one embodiment of the present disclosure, the display substrate further includes a clock signal line provided in the driving circuit region, the clock signal line is configured to provide a clock signal, and a first electrode of the fourth transistor is electrically connected to a third power line. A ratio value of the first distance to a length of the active layer of the third transistor in a first direction is 10.78 or less. The first distance is a distance between one side of the clock signal line far from the display region and one side of the third power line close to the display region.

[0173] In a specific implementation, in order to facilitate the realization of a narrow frame, the ratio value of the first distance to the length of the active layer of the third transistor in the first direction can be set to 10.78 or less.

[0174] As shown in FIG. 26, a distance between one side of the first clock signal line portion K11 included in the first clock signal line far from the display region and one side of the third power line VGH2 close to the display region is the first distance J1. As shown in FIG. 23, a length along the first direction of the active layer A3 of the third transistor T3 is WT3. A ratio value of the first distance J1 to WT3 is 10.78 or less.

[0175] In at least one embodiment of the present disclosure, the display substrate further includes a clock signal line provided in the driving circuit region, the clock signal line is configured to provide a clock signal, a first electrode of the fourth transistor is electrically connected to a third power supply line, a ratio value of a line width of the third power supply line to a first distance is 0.060 or more, the line width of the third power supply line is a length along a first direction of the third power supply line, and the first distance is a distance between one side far from a display region of the clock signal line and one side close to the display region of the third power supply line.

[0176] In a specific implementation, in order to facilitate the realization of a narrow frame, the ratio value of the line width of the third power supply line to the first distance can be set to be 0.060 or more.

[0177] As shown in FIG. 26, a distance between one side far from a display region of a first clock signal line portion K11 included in a first clock signal line and one side close to a display region of a third power supply line VGH2 is a first distance J1, XL1 is denoted as a line width of the third power supply line VGH, and a ratio value between XL1 and the first distance J1 is 0.060 or more.

[0178] The display substrate according to at least one embodiment of the present disclosure further includes a clock signal line provided in the driving circuit region, the clock signal line is configured to provide a clock signal, a first electrode of the fourth transistor is electrically connected to a third power supply line, a ratio value of a line width of the third power supply line to the first distance is 0.045 or less, the line width of the third power supply line is a length along a first direction of the third power supply line, and the first distance is a distance between one side far from a display region of the clock signal line and one side close to the display region of the third power supply line.

[0179] In a specific implementation, in order to facilitate the realization of a narrow frame, the ratio value of the line width of the third power supply line to the first distance can be set to be 0.045 or more.

[0180] As shown in FIG. 26, the distance between one side of the first clock signal line portion K11 included in the first clock signal line, which is far from the display area, and one side of the third power supply line VGH2, which is close to the display area, is the first distance J1. XL3 denotes the line width of the third power supply line VGH2, and the ratio between XL3 and the first distance J1 is 0.045 or more.

[0181] The display substrate according to at least one embodiment of the present disclosure further includes a clock signal line group provided in the driving circuit area. The clock signal line group includes at least one clock signal line. The clock signal line is configured to provide a clock signal. The display substrate includes at least two power supply lines. The clock signal line group is located between two of the at least two power supply lines, or the clock signal line group is located on the side far from the display area of the power supply line.

[0182] In at least one embodiment of the present disclosure, the clock signal line group may be located between two power supply lines, or the clock signal line group may be located on the side far from the display area of the power supply line.

[0183] In at least one embodiment of the display substrate shown in FIG. 26, the display area may be provided on the side of the third power supply line VGH2 that is far from the first power supply line VGH.

[0184] As shown in FIG. 37, the display area A0 is provided on the side of the third power supply line VGH2 that is far from the first power supply line VGH.

[0185] As shown in FIGS. 27 to 37, the first clock signal line portion K11 included in the first clock signal line and the third clock signal line portion K13 included in the first clock signal line are provided on the side of the second voltage line VGL that is far from the display area A0, and the first clock signal line portion K21 included in the second clock signal line and the third clock signal line portion K23 included in the second clock signal line portion are provided on the side of the second voltage line VGL that is far from the display area A0.

[0186] In at least one embodiment of the present disclosure, the display substrate includes a first power line and a third power line, the display substrate further includes a second output circuit, the second input circuit is configured to input a first voltage signal from the first power line to the second node under the control of the potential of the third node, and the second output circuit is configured to output a third voltage signal from the third power line to the second drive signal output terminal under the control of the potential of the third node. The ratio of the second distance to the length of the active layer of the third transistor in the first direction is 8.47 or less. The third transistor is a transistor that outputs a first voltage signal included in the first output circuit, and the second distance is the distance between one side of the first power line far from the display area and one side of the third power line close to the display area.

[0187] In a specific implementation, in order to facilitate the realization of a narrow frame, the ratio of the second distance to the length of the active layer of the third transistor in the first direction can be set to 8.47 or less.

[0188] As shown in FIG. 26, the second distance J2 is the distance between one side of the first power line VGH far from the display area and one side of the third power line VGH2 close to the display area. As shown in FIG. 23, the length of the active layer A3 of the third transistor T3 along the first direction is WT3. The ratio of the second distance J2 to WT3 is 8.47 or less.

[0189] In at least one embodiment of the present disclosure, the display substrate includes a first power line and a third power line, the display substrate further includes a second output circuit, the second input circuit is configured to input a first voltage signal from the first power line to the second node under the control of the potential of the third node, and the second output circuit is configured to output a third voltage signal from the third power line to the second drive signal output terminal under the control of the potential of the third node. The ratio of the line width of the first power line to the second distance is 0.077 or more. The line width of the first power line is the length of the first power line in the first direction, and the second distance is the distance between one side far from the display area of the first power line and one side close to the display area of the third power line.

[0190] In a specific implementation, in order to facilitate the realization of a narrow frame, the ratio of the line width of the first power line to the second distance can be set to be 0.077 or more.

[0191] As shown in FIG. 26, the second distance J2 is the distance between one side far from the display area of the first power line VGH and one side close to the display area of the third power line VGH2. XL1 represents the line width of the first power line VGH, and the ratio between XL1 and the second distance J2 is 0.077 or more.

[0192] In at least one embodiment of the present disclosure, the display substrate includes a first power line and a third power line, the display substrate further includes a second output circuit, the second input circuit is configured to input a first voltage signal from the first power line to the second node under the control of the potential of the third node, and the second output circuit is configured to output a third voltage signal from the third power line to the second drive signal output end under the control of the potential of the third node. The ratio of the line width of the third power line to the second distance is 0.058 or more. The line width of the third power line is the length of the third power line in the first direction, and the second distance is the distance between one side far from the display area of the first power line and one side close to the display area of the third power line.

[0193] In a specific implementation, in order to facilitate the realization of a narrow frame, the ratio of the line width of the third power line to the second distance can be set to be 0.058 or more.

[0194] As shown in FIG. 26, the second distance J2 is the distance between one side far from the display region of the first power supply line VGH and one side close to the display region of the third power supply line VGH2, XL3 represents the line width of the third power supply line VGH2, and the ratio between XL3 and the second distance J2 is 0.058 or more.

[0195] The display substrate according to at least one embodiment of the present disclosure includes a first source-drain metal layer and a second source-drain metal layer sequentially stacked along a direction away from the base substrate. The clock signal line includes a first clock signal line portion provided on the first source-drain metal layer or a second clock signal line portion provided on the second source-drain metal layer.

[0196] In at least one embodiment of the present disclosure, the clock signal line may include a first clock signal line portion or a second clock signal line portion. The first clock signal line portion may be provided on the first source-drain metal layer, and the second clock signal line portion may be provided on the second source-drain metal layer.

[0197] Optionally, the display substrate further includes a third gate metal layer provided between the first source-drain metal layer and the base substrate. The clock signal line further includes a third clock signal line portion provided on the third gate metal layer. The clock signal line includes the first clock signal line portion, and the third clock signal line portion and the first clock signal line portion are in direct contact or electrically connected to each other via a via. Or the clock signal line includes the second clock signal line portion, and the third clock signal line portion and the second clock signal line portion are in direct contact or electrically connected to each other via a via.

[0198] Furthermore, in the display substrate according to at least one embodiment of the present disclosure, the clock signal line portion may include a third clock signal line portion, the third clock signal line portion may be provided on a third gate metal layer, and the third clock signal line portion and the first clock signal line portion are in direct contact or electrically connected to each other via a via, or the third clock signal line portion and the second clock signal line portion are in direct contact or electrically connected to each other via a via.

[0199] In at least one embodiment of the present disclosure, the clock signal line includes two clock signal line portions coupled to each other, the two clock signal line portions are provided on different metal layers respectively, one of the two clock signal line portions is continuous, and the other of the two clock signal line portions is not continuous.

[0200] Specifically, during implementation, the clock signal line may include two clock signal line portions provided on different metal layers coupled to each other. One of the clock signal line portions may be continuous, and the other of the clock signal line portions may not be continuous.

[0201] As shown in FIG. 25, the third clock signal line portion K23 included in the second clock signal line is not continuous, and the first conductive connection portion L1 provided on the first gate metal layer is provided between two portions of K23.

[0202] In at least one embodiment of the present disclosure, the third clock signal line portion K13 included in the first clock signal line may be disconnected by another conductive connection portion so that the third clock signal line portion K13 included in the first clock signal line is not continuous.

[0203] As shown in FIG. 26, the first clock signal line portion K11 included in the first clock signal line and the first clock signal line portion K21 included in the second clock signal line are continuous.

[0204] Optionally, the display substrate includes a first transfer electrode. The first electrode of the fifth transistor included in the driving circuit of this stage, the gate of the sixth transistor included in the driving circuit of this stage, and the gate of the seventh transistor included in the driving circuit of the adjacent stage are electrically connected to each other via the same first transfer electrode. The fifth transistor is a transistor that outputs the clock signal included in the first output circuit, the sixth transistor is a transistor that operates under the control of the clock signal included in the control circuit, and the seventh transistor is a transistor that provides an input voltage to the third node included in the first input circuit.

[0205] As shown in FIGS. 27-34, what is denoted as Z1 is the first transfer electrode. The first transfer electrode Z1 is configured to electrically connect the first electrode S5 of the fifth transistor T5 and the gate G6 of the sixth transistor T6, and the first transfer electrode Z1 is configured to electrically connect the gate G6 of the sixth transistor T6 and the gate of the seventh transistor T7 included in the driving circuit of the next adjacent stage.

[0206] FIG. 38 is a layout diagram of at least one embodiment of the display substrate, FIG. 48 is a layout diagram of at least one embodiment of the display substrate, and FIG. 59 is a layout diagram of at least one embodiment of the display substrate.

[0207] FIG. 39 is a layout diagram of the first semiconductor layer in FIG. 38, FIG. 40 is a layout diagram of the first gate metal layer in FIG. 38, FIG. 41 is a layout diagram of the second semiconductor layer in FIG. 38, FIG. 42 is a layout diagram of the second gate metal layer in FIG. 38, FIG. 43 is a layout diagram of the third gate metal layer in FIG. 38, FIG. 44 is a layout diagram of the first source-drain metal layer in FIG. 38, and FIG. 45 is a layout diagram of the second source-drain metal layer in FIG. 38.

[0208] FIG. 49 is a layout diagram of the first semiconductor layer in FIG. 48, FIG. 50 is a layout diagram of the first gate metal layer in FIG. 48, FIG. 51 is a layout diagram of the second semiconductor layer in FIG. 48, FIG. 52 is a layout diagram of the second gate metal layer in FIG. 48, FIG. 53 is a layout diagram of the third gate metal layer in FIG. 48, FIG. 54 is a layout diagram of the first source-drain metal layer in FIG. 48, FIG. 55 is a layout diagram of the second source-drain metal layer in FIG. 48, and FIG. 56 is a layout diagram of the shield layer in FIG. 48. The shield layer can be provided between the third gate metal layer and the first source-drain metal layer.

[0209] FIG. 60 is a layout diagram of the first semiconductor layer in FIG. 59, FIG. 61 is a layout diagram of the first gate metal layer in FIG. 59, FIG. 62 is a layout diagram of the second semiconductor layer in FIG. 59, FIG. 63 is a layout diagram of the second gate metal layer in FIG. 59, FIG. 64 is a layout diagram of the third gate metal layer in FIG. 59, FIG. 65 is a layout diagram of the first source-drain metal layer in FIG. 59, FIG. 66 is a layout diagram of the second source-drain metal layer in FIG. 59. FIG. 67 is a layout diagram of the shield layer in FIG. 59. The shield layer can be provided between the third gate metal layer and the first source-drain metal layer.

[0210] In at least one embodiment of the present disclosure, the display substrate includes a first power line and a second power line, the display substrate further includes a second output circuit, the first input circuit includes a seventh transistor, the second input circuit includes an eighth transistor, the seventh transistor is a transistor that provides an input voltage to a third node, the eighth transistor is a transistor that inputs a first voltage signal from the first power line to a second node under the control of the potential of the third node, and the fourth transistor is a transistor that outputs a third voltage signal provided by the second output circuit. The extending direction of the active layer of the seventh transistor is the same as or perpendicular to the extending direction of the active layer of the eighth transistor. In the same driving circuit, the position of the first electrode of the seventh transistor in the second direction is lower than the position of the second electrode of the fourth transistor in the second direction.

[0211] In at least one embodiment of the present disclosure, the second direction may be, but is not limited to, the vertical direction.

[0212] In at least one embodiment of the display substrate shown in FIGS. 27-34, the extending direction of the active layer A7 of T7 is perpendicular to the extending direction of the active layer A8 of T8. In at least one embodiment of the display substrate shown in FIG. 38, at least one embodiment of the display substrate shown in FIG. 48, and at least one embodiment of the display substrate shown in FIG. 59, the extending direction of the active layer A7 of T7 is parallel to the extending direction of the active layer A8 of T8.

[0213] In at least one embodiment of the display substrate shown in FIG. 27, at least one embodiment of the display substrate shown in FIG. 38, at least one embodiment of the display substrate shown in FIG. 48, and at least one embodiment of the display substrate shown in FIG. 59, the position of the first electrode S7 of the seventh transistor T7 in the second direction is lower than the position of the second electrode D4 of the fourth transistor T4 in the second direction.

[0214] In at least one embodiment of the present disclosure, as shown in FIGS. 33, 44, 54, and 65, by setting the position of the first electrode S7 of the seventh transistor T7 in the second direction to be lower than the position of the second electrode D4 of the fourth transistor T4 in the second direction (the second direction may be the vertical direction), the connection electrodes can be laid out using the saved vertical space, which is advantageous for reducing the vertical height of the driving circuit and realizing a high PPI (Pixels Per Inch, pixel density).

[0215] In at least one embodiment of the present disclosure, the display substrate includes a first power line, the display substrate further includes a second transfer electrode, the second transfer electrode and the first power line are of an integral structure, the second input circuit includes an eighth transistor, the first output circuit includes a third transistor, the eighth transistor is a transistor that inputs a first voltage signal from the first power line to a second node under the control of the potential of the third node, and the third transistor is a transistor that outputs a first voltage signal provided by the first output circuit. The second transfer electrode includes a first electrode portion, a second electrode portion, and a third electrode portion. The first electrode portion functions as a connection electrode between the first power line and the first electrode of the eighth transistor, the second electrode portion is a connection electrode between the first electrode of the eighth transistor and the first electrode of the third transistor, and the third electrode portion functions as the first electrode of the third transistor. The included angle between the first electrode portion and the second electrode portion is not less than 90 degrees and not more than 120 degrees.

[0216] In FIGS. 33, 44, 54, and 65, what is denoted as Z2 is the second transfer electrode. In FIG. 35, what is denoted as Z2 is the second transfer electrode in FIG. 33, and in FIG. 46, what is denoted as Z2 is the second transfer electrode in FIG. 44.

[0217] As shown in FIGS. 35 and 46, the second transfer electrode Z2 includes a first electrode portion Z21, a second electrode portion Z22, and a third electrode portion Z23. The first electrode portion Z21 functions as a connection electrode between the first power line VGH and the first electrode S8 of the eighth transistor T8, the second electrode portion Z22 is a connection electrode between the first electrode S8 of the eighth transistor T8 and the first electrode S3 of the third transistor T3, and the third electrode portion Z23 functions as the first electrode S3 of the third transistor T3.

[0218] In FIG. 33, the one denoted as D8 is the second electrode of T8, the one denoted as S8 is the first electrode of T8, the one denoted as D3 is the second electrode of T3, the one denoted as S3 is the first electrode of T3, the one denoted as S4 is the first electrode of T4, the one denoted as D4 is the second electrode of T4, the one denoted as S5 is the first electrode of T5, the one denoted as D5 is the second electrode of T5, the one denoted as S7 is the first electrode of T7, the one denoted as D7 is the second electrode of T7, the one denoted as S9 is the first electrode of T9, the one denoted as D9 is the second electrode of T9, and the one denoted as D6 is the second electrode of T6.

[0219] In FIGS. 44, 54, and 65, the one denoted as S8 is the first electrode of T8, the one denoted as D3 is the second electrode of T3, the one denoted as S3 is the first electrode of T3, the one denoted as S4 is the first electrode of T4, the one denoted as D4 is the second electrode of T4, the one denoted as S5 is the first electrode of T5, the one denoted as D5 is the second electrode of T5, the one denoted as S7 is the first electrode of T7, the one denoted as D7 is the second electrode of T7, the one denoted as S9 is the first electrode of T9, the one denoted as D9 is the second electrode of T9, and the one denoted as D6 is the second electrode of T6.

[0220] As shown in FIG. 35, the included angle between the first electrode portion Z21 and the second electrode portion Z22 is greater than 90 degrees and less than or equal to 120 degrees.

[0221] As shown in FIG. 46, the included angle between the first electrode portion Z21 and the second electrode portion Z22 is equal to 90 degrees.

[0222] In FIGS. 34, 45, 55, and 66, the one denoted as S2 is the first electrode of T2, the one denoted as D2 is the second electrode of T2, the one denoted as S1 is the first electrode of T1, and the one denoted as D1 is the second electrode of T1.

[0223] As shown in FIGS. 27 - 34, 38 - 45, 48 - 56, and 48 - 68, S1 and S2 are integrally formed, and S2 is electrically connected to the second power line VGL via a via.

[0224] The display substrate according to at least one embodiment of the present disclosure further includes a third transfer electrode, the third transfer electrode includes a fourth electrode portion, a fifth electrode portion, and a sixth electrode portion, the second input circuit includes a first transistor and an eighth transistor, the first transistor is a transistor that inputs a second voltage signal from a second power line to a second node under the control of the potential of a third node, the driving circuit further includes a second output circuit, the second output circuit includes a second transistor, the second transistor is a transistor that outputs a second voltage signal from a second power line to a second driving signal output terminal under the control of the potential of a third node, the eighth transistor is a transistor that inputs a first voltage signal from a first power line to a second node under the control of the potential of the third node, the control circuit includes a sixth transistor and a ninth transistor, the sixth transistor is a transistor that operates under the control of a clock signal, The ninth transistor is a transistor that controls the conduction between a third node and a first node under the control of a second voltage signal from a second power line, the first transistor and the second transistor are transistors of a first type, the eighth transistor and the ninth transistor are transistors of a second type, The fourth electrode portion is configured to electrically connect the bottom gate of the first transistor and the gate of the eighth transistor, and / or the fourth electrode portion is configured to electrically connect the bottom gate of the second transistor and the gate of the eighth transistor, The fifth electrode portion is configured to electrically connect the fourth electrode portion, the first electrode of the ninth transistor, and the upper gate of the first transistor, and / or the fifth electrode portion is configured to electrically connect the fourth electrode portion, the first electrode of the ninth transistor, and the upper gate of the second transistor, The sixth electrode portion is configured to electrically connect the first electrode of the ninth transistor and the second electrode of the sixth transistor.

[0225] Optionally, the included angle between the fourth electrode portion and the fifth electrode portion is not less than 90 degrees and less than 130 degrees.

[0226] Optionally, the fifth electrode portion is perpendicular or parallel to the sixth electrode portion.

[0227] In FIGS. 33, 44, 54, and 65, what is denoted as Z3 is the third transfer electrode, In FIG. 36, what is denoted as Z3 is the third transfer electrode in FIG. 33. In FIG. 47, what is denoted as Z3 is the third transfer electrode in FIG. 44. In FIG. 57, what is denoted as Z3 is the third transfer electrode in FIG. 54.

[0228] As shown in FIGS. 36, 47, and 57, the third transfer electrode Z3 includes a fourth electrode portion Z31, a fifth electrode portion Z32, and a sixth electrode portion Z33. The fourth electrode portion Z31 is configured to electrically connect the bottom gate G11 of the first transistor T1 and the gate G8 of the eighth transistor T8. The fourth electrode portion Z31 is configured to electrically connect the bottom gate G21 of the second transistor T2 and the gate G8 of the eighth transistor T8. The fifth electrode portion Z32 is configured to electrically connect the fourth electrode portion Z31, the first electrode S9 of the ninth transistor T9, and the upper gate G12 of the first transistor T1. The fifth electrode portion Z32 is configured to electrically connect the fourth electrode portion Z31, the first electrode S9 of the ninth transistor T9, and the upper gate of the second transistor T2. The sixth electrode portion Z33 is configured to electrically connect the first electrode S9 of the ninth transistor T9 and the second electrode D6 of the sixth transistor T6.

[0229] As shown in FIG. 36, the included angle between Z31 and Z32 is greater than 90 degrees and less than or equal to 130 degrees.

[0230] As shown in FIGS. 47 and 57, the included angle between Z31 and Z32 is equal to 90 degrees.

[0231] As shown in FIG. 36, Z32 is perpendicular to Z33.

[0232] As shown in FIGS. 47 and 57, Z32 is parallel to Z33.

[0233] In at least one embodiment of the present disclosure, the first output circuit further includes a first capacitor, a first plate of the first capacitor is electrically connected to a first node, a second plate of the first capacitor is electrically connected to a first drive signal output end, and the display substrate further includes a first shield portion. The first plate of the first capacitor is provided between the base substrate and the second plate of the first capacitor. The first shield portion is provided on a side of the second plate of the first capacitor away from the base substrate.

[0234] As shown in FIGS. 48 - 56 and FIGS. 59 - 67, the first plate C1a of the first capacitor C1 is provided between the base substrate and the second plate C1b of the first capacitor C1, the first shield portion B1 is provided on a side of the second plate C1b of the first capacitor away from the base substrate, and the first shield portion B1 is included in the shield layer. The first shield portion B1 is used to prevent an extra parasitic capacitance from occurring in a metal layer provided between the third power line VGH2 of the first source - drain metal layer and the plate of the first capacitor C1, and a first shield portion is provided between the plate of the first capacitor C1 and the third power line VGH2.

[0235] FIG. 58 is a schematic diagram of the overlap of the shield layer shown in FIG. 56 and the third gate metal layer shown in FIG. 53.

[0236] FIG. 68 is a schematic diagram of the overlap of the shield layer shown in FIG. 67 and the third gate metal layer shown in FIG. 64.

[0237] The display substrate according to at least one embodiment of the present disclosure further includes a second shield portion, and the second input circuit includes a first transistor. The second shield portion is provided on a side of the active layer of the first transistor away from the base substrate. The area of the orthographic projection of the second shield portion on the power line is larger than the area of the orthographic projection of the active layer of the first transistor on the power line.

[0238] As shown in FIGS. 48 to 56 and FIGS. 59 to 67, the second shield portion B2 is included in the shield layer, the second shield portion B2 is provided on the side of the active layer A1 of the first transistor T1 far from the base substrate, the area of the orthographic projection of the second shield portion B2 onto the first power line VGH is larger than the area of the orthographic projection of the active layer A1 of the first transistor T1 onto the first power line VGH.

[0239] In a specific implementation, a second shield portion is provided between the first power line VGH and the active layer A1 of the first transistor T1. The second shield portion is included in the shield layer. The second shield portion is used to shield the parasitic capacitance between the first power line VGH and the active layer A1 of the first transistor T1, and the parasitic capacitance between the first power line VGH and the gate of the first transistor T1 (the gate of the first transistor T1 includes the upper gate and the bottom gate of the first transistor T1).

[0240] In at least one embodiment of the present disclosure, in an embodiment where there is no overlap between the active layer A1 of the first transistor T1 and the first power line VGH, a shield layer may be provided to prevent the generation of parasitic capacitance. The shield layer may be provided between the third gate metal layer and the first source-drain metal layer.

[0241] In at least one embodiment of the display substrate shown in FIG. 38, compared with FIG. 27, by arranging the active layer A8 of the eighth transistor T8 to extend along the first direction, the wiring length of the connection electrode between the eighth transistor T8 and the first transistor T1 is reduced, the space on the side of the first power line VGH close to the seventh transistor T7 is fully utilized, the space utilization rate can be increased, the space above the eighth transistor T8 can be saved for laying out the connection wiring between the clock signal line and the transistor, which is beneficial to shortening the vertical dimension, and furthermore, a higher resolution can be achieved. Also, in order to prevent the generation of parasitic capacitance between the first power line VGH and the oxide, in at least one embodiment of the display panel shown in FIG. 38, there is no overlap between the active layer A1 of the first transistor T1 and the first power line VGH.

[0242] In at least one embodiment of the display substrate shown in FIG. 38, the length of the connection wiring between the upper gate G12 of the first transistor T1 and the second electrode D6 of the sixth transistor T6, and the length of the connection wiring between the upper gate G12 of the first transistor T1 and the first electrode S9 of the ninth transistor T9 are shortened, and the wiring method is simplified. Due to such a change, the length of the shift register in the first direction can be significantly shortened, and the width of at least one power line can be shortened.

[0243] Compared with FIG. 48, in at least one embodiment of the display substrate shown in FIG. 38, by further moving the active layer A1 of the first transistor T1 in the direction closer to the second power line VGL, the width along the first direction of the shift register can be further narrowed.

[0244] Compared with FIG. 59, in at least one embodiment of the display substrate shown in FIG. 48, the positions of the bottom gate G11 of the first transistor T1 and the first electrode D1 of the first transistor T1 in the first direction are adjusted. In at least one embodiment shown in FIG. 48, there is a lot of overlap between the orthographic projection of the first power line VGH on the base substrate and the orthographic projection of the bottom gate G11 of the first transistor T1 on the base substrate. In at least one embodiment shown in FIG. 59, there is a lot of overlap between the orthographic projection of the first power line VGH onto the base substrate and the orthographic projection of the second electrode D1 of the first transistor T1 onto the base substrate.

[0245] In at least one embodiment corresponding to FIGS. 27, 38, 48, and 59, the first electrode of each P-type transistor and the active layer of the P-type transistor may be electrically connected via a via, and the second electrode of each P-type transistor and the active layer of the P-type transistor may be electrically connected via a via. The first electrode of the N-type transistor and the active layer of the N-type transistor may be electrically connected via a via, and the second electrode of the N-type transistor and the active layer of the N-type transistor may be electrically connected via a via. However, since the thickness of the oxide semiconductor layer is relatively thin, in order to prevent damage to the oxide semiconductor layer due to punching, the first electrode of the N-type transistor and the active layer of the N-type transistor are directly electrically connected, and the second electrode of the N-type transistor and the active layer of the N-type transistor are directly electrically connected.

[0246] FIG. 69 is a comparative schematic diagram of at least one embodiment corresponding to FIG. 27, at least one embodiment corresponding to FIG. 38, at least one embodiment corresponding to FIG. 48, and at least one embodiment corresponding to FIG. 59.

[0247] As shown in FIG. 69, at least one embodiment corresponding to FIG. 27, at least one embodiment corresponding to FIG. 38, at least one embodiment corresponding to FIG. 48, and at least one embodiment corresponding to FIG. 59 are arranged in order from top to bottom. The width along the first direction of at least one embodiment of the drive circuit corresponding to FIG. 27, the width along the first direction of at least one embodiment of the drive circuit corresponding to FIG. 38, and the width along the first direction of at least one embodiment of the drive circuit corresponding to FIG. 48 become narrower in order, which is advantageous for realizing a narrow frame.

[0248] FIG. 70 is a layout diagram of at least one embodiment of two adjacent stages of drive circuits, and the structural diagram of the drive circuit is shown in 59.

[0249] As shown in FIG. 70, the first electrode of the fifth transistor T5 in the driving circuit of this stage is electrically connected to the first clock signal line of the driving circuit of the next adjacent stage, and the gate signal connection line of the seventh transistor T7 in the driving circuit of the next adjacent stage is simultaneously connected to the first electrode of the fifth transistor T5 in the driving circuit of this stage. In this way, the wiring of the clock signal line can be saved.

[0250] As shown in FIG. 70, the first transfer electrode Z1 is configured to electrically connect the first electrode S5 of the fifth transistor T5 in the driving circuit of this stage and the gate G6 of the sixth transistor T6 in the driving circuit of this stage, and the first transfer electrode Z1 is configured to electrically connect the gate G6 of the sixth transistor T6 in the driving circuit of this stage and the gate of the seventh transistor T7 included in the driving circuit of the next adjacent stage.

[0251] As shown in FIG. 70, the height H0 of the driving circuit of one stage can be, but is not limited to, the distance between the upper end of the active layer of the fourth transistor in the driving circuit of this stage and the upper end of the fourth transistor in the driving circuit of the next adjacent stage.

[0252] FIG. 71 is a layout diagram of at least one embodiment of two adjacent stages of driving circuits.

[0253] The layout diagram shown in FIG. 71 is different from the layout diagram shown in FIG. 70 in that the first clock signal line K1 and the second clock signal line K2 are arranged between the first power supply line VGH and the third power supply line VGH2, the first clock signal line K1 and the second clock signal line K2 are provided in the second source-drain metal layer, the gate of the seventh transistor included in the driving circuit of this stage is electrically connected to the clock signal line close to the first power supply line VGH, and the gate of the seventh transistor in the driving circuit of the next adjacent stage is electrically connected to one clock signal line far from the first power supply line VGH.

[0254] In FIG. 71, what is denoted as VGL is the second power supply line.

[0255] At least one embodiment shown in FIG. 71 can further reduce the dimension of the driving circuit in the first direction compared with the above embodiments, and can reduce the widths of the two clock signal lines.

[0256] In at least one embodiment of the present disclosure, two adjacent driving circuits are electrically connected to the same two clock signal lines. When the gate of the seventh transistor included in the driving circuit in this stage accesses the first clock signal, the gate of the seventh transistor included in the adjacent next-stage driving circuit accesses the second clock signal.

[0257] FIG. 72 is a layout diagram of the first semiconductor layer in FIG. 71, FIG. 73 is a layout diagram of the first gate metal layer in FIG. 71, FIG. 74 is a layout diagram of the second semiconductor layer in FIG. 71, FIG. 75 is a layout diagram of the second gate metal layer in FIG. 71, FIG. 76 is a layout diagram of the third gate metal layer in FIG. 71, FIG. 77 is a layout diagram of the first source-drain metal layer in FIG. 71, and FIG. 78 is a layout diagram of the second source-drain metal layer in FIG. 71.

[0258] In FIG. 72, A3 denoted is the first active part, A41 denoted is the first second active part, A42 denoted is the second second active part, A51 denoted is the first third active part, A52 denoted is the second third active part, A8 denoted is the active layer of the eighth transistor, A10 denoted is the active layer of the tenth transistor, A6 denoted is the active layer of the sixth transistor, A7 denoted is the active layer of the seventh transistor, A9 denoted is the active layer of the ninth transistor, and A8, A10, and A6 are continuous with each other.

[0259] In FIG. 73, what is denoted as G41 is the first gate pattern of the fourth transistor, what is denoted as G42 is the second gate pattern of the fourth transistor, what is denoted as G511 is the first gate pattern of the fifth transistor, G512 is the second gate pattern of the fifth transistor, what is denoted as G521 is the third gate pattern of the fifth transistor, what is denoted as G522 is the fourth gate pattern of the fifth transistor, G41 and G42 are integrally formed, G511, G512, G521 and G522 are integrally formed. What is denoted as G21 is the bottom gate of the second transistor, what is denoted as G11 is the bottom gate of the first transistor, what is denoted as G3 is the gate of the third transistor, what is denoted as G6 is the gate of the sixth transistor, what is denoted as G7 is the gate of the seventh transistor, what is denoted as G8 is the gate of the eighth transistor, what is denoted as G9 is the gate of the ninth transistor, what is denoted as G10 is the gate of the tenth transistor.

[0260] In FIG. 74, what is denoted as A21 is the first active layer pattern of the second transistor, what is denoted as A22 is the second active layer pattern of the second transistor, and what is denoted as A1 is the active layer of the first transistor.

[0261] In FIG. 75, what is denoted as C1a is the first electrode plate of the first capacitor.

[0262] In FIG. 76, the first gate pattern included in the upper gate of the second transistor is denoted as G221, the second gate pattern included in the upper gate of the second transistor is denoted as G222, the third gate pattern included in the upper gate of the second transistor is denoted as G223, the fourth gate pattern included in the upper gate of the second transistor is denoted as G224, the fifth gate pattern included in the upper gate of the second transistor is denoted as G225, the sixth gate pattern included in the upper gate of the second transistor is denoted as G226, what is denoted as G12 is the upper gate of the first transistor, and what is denoted as C1b is the second electrode plate of the first capacitor.

[0263] In FIG. 77, the one denoted as S8 is the first electrode of T8, the one denoted as D3 is the second electrode of T3, the one denoted as S3 is the first electrode of T3, the one denoted as S4 is the first electrode of T4, the one denoted as D4 is the second electrode of T4, the one denoted as S5 is the first electrode of T5, the one denoted as D5 is the second electrode of T5, the one denoted as S7 is the first electrode of T7, the one denoted as D7 is the second electrode of T7, the one denoted as S9 is the first electrode of T9, the one denoted as D9 is the second electrode of T9, the one denoted as D6 is the second electrode of T6, the one denoted as VGH is the first power line, the one denoted as VGL is the second power line, and the one denoted as VGH2 is the third power line.

[0264] In FIG. 78, the one denoted as S2 is the first electrode of the second transistor, the one denoted as D2 is the second electrode of the second transistor, the one denoted as S1 is the first electrode of the first transistor, the one denoted as D1 is the second electrode of the first transistor, the one denoted as K1 is the first clock signal line, and the one denoted as K2 is the second clock signal line.

[0265] FIG. 79 is a cross-sectional view taken along the line A-A' in FIG. 71.

[0266] As shown in FIG. 79, the one denoted as 791 is the base substrate, the one denoted as 792 is the first insulating layer, the one denoted as 793 is the first gate metal layer, the one denoted as 794 is the second insulating layer, the one denoted as 795 is the second semiconductor layer, the one denoted as 796 is the third insulating layer, the one denoted as 797 is the third gate metal layer, the one denoted as 798 is the fourth insulating layer, the one denoted as 799 is the first source-drain metal layer, the one denoted as 7910 is the fifth insulating layer, and the one denoted as 7911 is the second source-drain metal layer.

[0267] As shown in FIG. 79, the first electrode of the first-type transistor provided in the second source-drain metal layer 7911 is electrically connected to the active layer of the first-type transistor provided in the second semiconductor layer 795, and the second electrode of the first-type transistor provided in the second source-drain metal layer 7911 is electrically connected to the active layer of the first-type transistor provided in the second semiconductor layer 795.

[0268] In at least one embodiment of the present disclosure, the second semiconductor layer 795 is an oxide semiconductor layer, and the thickness of the second semiconductor layer 795 is relatively thin. For example, the thickness of the second semiconductor layer can be one-tenth of the thickness of the first semiconductor layer. In order to prevent damage to the oxide semiconductor layer caused by punching, at least one embodiment of the present disclosure can be arranged to directly connect the second semiconductor layer and the second source-drain metal layer, but is not limited thereto.

[0269] FIG. 80 is a cross-sectional view taken along line B-B' in FIG. 59.

[0270] In FIG. 80, what is denoted as 791 is the base substrate, what is denoted as 801 is the sixth insulating layer, what is denoted as 797 is the third gate metal layer, what is denoted as 802 is the seventh insulating layer, what is denoted as 790 is the shield layer, what is denoted as 7912 is the first source-drain metal layer, and what is denoted as 803 is the eighth insulating layer.

[0271] As shown in FIG. 80, the shield layer 790 is provided between the third gate metal layer 797 and the first source-drain metal layer 7912, and the first shield portion is provided between the second electrode plate of the first capacitor and the third power line. In this way, it is possible to prevent the generation of an extra parasitic capacitance between the second electrode plate of the first capacitor and the third power line. Here, the first shield portion is provided on the shield layer 790, the second electrode plate of the first capacitor is provided on the third gate metal layer 797, and the third power line is provided on the first source-drain metal layer 7912, but is not limited thereto.

[0272] The display substrate according to an embodiment of the present disclosure includes a shift register provided on a base substrate. The shift register includes a plurality of stages of driving circuits. The driving circuit includes a first input circuit, a second input circuit, a first output circuit, a control circuit, and a second output circuit. The first output circuit is configured to provide a first scanning driving signal to a first driving signal output terminal under the control of the potentials of a first node and a second node. The first input circuit is configured to input a signal to a third node under the control of a clock signal. The second input circuit is configured to input a signal from a power supply line to the second node under the control of the potential of the third node. The control circuit is configured to control the potential of the third node and the potential of the first node. The second output circuit is configured to control to output a second scanning driving signal through a second driving signal output terminal under the control of the potential of the third node. The second input circuit includes a first transistor, and the second output circuit includes a second transistor. The driving circuit is configured to provide a scanning driving signal to a display area. The gate of the first transistor is electrically connected to the third node. The first electrode of the first transistor is electrically connected to a second power supply line. The second electrode of the first transistor is electrically connected to the second node. The gate of the second transistor is electrically connected to the third node. The first electrode of the second transistor is electrically connected to the second power supply line. The second electrode of the second transistor is electrically connected to the second driving signal output terminal. The first transistor and the second transistor are N-type transistors. The ratio of the area of the oxide active layer of the second transistor to the area of the oxide active layer of the first transistor is 8.74 or more.

[0273] In FIG. 19, what is denoted as A21 is the first active layer pattern of the second transistor T2, and what is denoted as A22 is the second active layer pattern of the second transistor T2. The active layer of the second transistor T2 includes the first active layer pattern A21 of the second transistor T2 and the second active layer pattern A22 of the second transistor T2. The active layer of the second transistor T2 is an oxide active layer, and the active layer A1 of the first transistor T1 is an oxide active layer. The area of the active layer of the second transistor T2 is equal to the sum of the area of A21 and the area of A22, and the ratio between the area of the active layer of the second transistor T2 and the area of A1 is 8.74 or more.

[0274] Optionally, the fourth transistor is a transistor that outputs a third voltage signal provided by the second output circuit. The fourth transistor is a P-type transistor, and the active layer of the fourth transistor is a low-temperature polysilicon active layer. The ratio between the area of the oxide active layer of the second transistor and the area of the active layer of the fourth transistor is 1.4 or more.

[0275] In FIG. 19, what is denoted as A41 is the first second active part, and what is denoted as A42 is the second second active part. A41 and A42 function as the active layer of the fourth transistor T4, and the area of the active layer of the fourth transistor T4 is equal to the sum of the area of A41 and the area of A42. The ratio between the area of the active layer of the second transistor T2 and the area of the active layer of the fourth transistor T4 is 1.4 or more.

[0276] In at least one embodiment of the present disclosure, the power supply line includes a first power supply line and a third power supply line. The second input circuit is configured to input a first voltage signal from the first power supply line to the second node under the control of the potential of the third node. The second output circuit is electrically connected to the third power supply line and is configured to provide a third voltage signal from the third power supply line to the second drive signal output terminal under the control of the potential of the third node. The voltage value of the third voltage signal is equal to or higher than the voltage value of the first voltage signal.

[0277] Optionally, the voltage value of the third voltage signal is 1.4 times or more of the voltage value of the first voltage signal.

[0278] Optionally, the gate of the first transistor includes a first gate and a second gate, the gate of the second transistor includes a first gate and a second gate, the first gate is a bottom gate, the second gate is a top gate, and the display substrate includes a first gate metal layer, a second gate metal layer, and a third gate metal layer stacked along the side far from the base substrate. The bottom gate is included in the first gate metal layer, the top gate is included in the second gate metal layer, or the bottom gate is included in the second gate metal layer, the top gate is included in the third gate metal layer, or the bottom gate is included in the first gate metal layer, and the top gate is included in the third gate metal layer.

[0279] In at least one embodiment of the present disclosure, the first gate of the first transistor and the first gate of the second transistor are of an integral structure, the second gate of the first transistor and the second gate of the second transistor are of an integral structure, the display substrate further includes a first source-drain metal layer and a second source-drain metal layer provided on the side far from the base substrate of the third gate metal layer, and the first source-drain metal layer is provided between the third gate metal layer and the second source-drain metal layer. The first gate of the first transistor and the second gate of the first transistor are electrically connected to each other through the connection electrode, and the connection electrode is included in the first source-drain metal layer or the second source-drain metal layer.

[0280] In the embodiment corresponding to FIGS. 27 to 34, the connection electrode may be the third transfer electrode Z3. The first gate of the first transistor T1 is the bottom gate G11 of the first transistor T1, the second gate of the first transistor T1 is the upper gate G12 of the first transistor T1, the first gate of the second transistor T2 is the bottom gate G21 of the second transistor T2, and the second gate of the second transistor T2 is the upper gate of the second transistor T2. The bottom gate G11 of the first transistor T1 and the upper gate G12 of the first transistor T1 are electrically connected via the third transfer electrode Z3, and the third transfer electrode Z3 is included in the first source-drain metal layer.

[0281] The embodiments of the present disclosure provide a series of drive circuits and corresponding layout diagrams. On the premise of realizing leakage reduction, the transistors and signal lines (including power lines and clock signal lines) are reasonably laid out, the width in the first direction is shortened, and a narrow frame is realized. In the vertical direction, the height in the second direction is shortened to realize high resolution.

[0282] The display device according to the embodiment of the present disclosure includes the above display substrate.

[0283] FIG. 81 is a structural diagram of a display device according to at least one embodiment of the present disclosure. In at least one embodiment of the display device shown in FIG. 81, the display device may be an organic light-emitting display. For example, the display device may be an OLED (organic light-emitting diode) display, a quantum dot light-emitting diode (QLED) display, a micro light-emitting diode (Micro LED) display, etc., but is not limited thereto.

[0284] In FIG. 81, what is denoted as O11 is the pixel circuit of the first column in the first row, what is denoted as O12 is the pixel circuit of the second column in the first row, what is denoted as O1m is the pixel circuit of the mth column in the first row, and m is an integer greater than 2. What is denoted as O21 is the pixel circuit in the first column of the second row, what is denoted as O22 is the pixel circuit in the second column of the second row, and what is denoted as O2m is the pixel circuit in the m-th column of the second row. What is denoted as On1 is the pixel circuit in the first column of the n-th row, what is denoted as On2 is the pixel circuit in the second column of the n-th row, and what is denoted as Onm is the pixel circuit in the m-th column of the n-th row, where n is an integer greater than 2.

[0285] In FIG. 81, what is denoted as VDD is the high voltage terminal, and each pixel circuit included in the display device is electrically connected to the high voltage terminal VDD.

[0286] As shown in FIG. 81, all the pixel circuits located in the first row are electrically connected to the scanning line GL1 of the first row, all the pixel circuits located in the second row are electrically connected to the scanning line GL2 of the second row, and all the pixel circuits located in the n-th row are electrically connected to the scanning line GLn of the n-th row. All the pixel circuits located in the first column are electrically connected to the data line DL1 of the first column, all the pixel circuits located in the second column are electrically connected to the data line DL2 of the second column, and all the pixel circuits located in the m-th column are electrically connected to the data line DLm of the m-th column.

[0287] As shown in FIG. 81, the display device according to at least one embodiment of the present disclosure further includes a timing controller 810, a scanning driver 811, and a data driver 812. The timing controller 810 is electrically connected to the scanning driver 811 and the data driver 812 respectively, and is used to provide corresponding control signals to the scanning driver 811 and the data driver 812 respectively. The scanning driver 811 is electrically connected to the scanning line GL1 of the first row, the scanning line GL2 of the second row, and the scanning line GLn of the n-th row respectively, and is used to provide corresponding scanning signals to the scanning line GL1 of the first row, the scanning line GL2 of the second row, and the scanning line GLn of the n-th row respectively. For example, the scanning driver 81 can sequentially provide corresponding scanning signals from the scanning line GL1 of the first row to the scanning line GLn of the n-th row. The data driver 812 is electrically connected to the data line DL1 of the first column, the data line DL2 of the second column, and the data line DLm of the m-th column, respectively, and is used to provide data signals corresponding to the data line DL1 of the first column, the data line DL2 of the second column, and the data line DLm of the m-th column.

[0288] In at least one embodiment of the display device shown in FIG. 81 of the present disclosure, during operation, the timing controller 81 is further used to transmit external data (not shown in FIG. 81) to the data driver 812, the scan driver 811 is used to provide a scan signal to the pixel circuit included in the display device, the data driver 812 is used to provide a data signal to the pixel circuit, the data signal is charged into the pixel circuit under the control of the scan signal, and the pixel circuit emits light accordingly.

[0289] The display device provided by the embodiments of the present disclosure can be any product or component having a display function, such as a mobile phone, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigation device, etc.

[0290] It should be pointed out that the above is a preferred embodiment of the present disclosure, and those skilled in the art can make some improvements and refinements that should be regarded as within the protection scope of the present disclosure without departing from the principle of the present disclosure.

Claims

1. A display board, The system includes a shift register provided on a base board, the shift register includes a multi-stage drive circuit, the drive circuit includes a first input circuit, a second input circuit, a first output circuit, and a control circuit, the first output circuit is configured to provide a first scanning drive signal to a first drive signal output terminal under the control of the potentials of a first node and a second node, the first input circuit is configured to input a signal to a third node under the control of a clock signal, the second input circuit is configured to input a signal from a power line to a second node under the control of the potential of the third node, and the control circuit is configured to control the potentials of the third node and the first node. The drive circuit region of the base substrate is provided with a plurality of drive circuits, and one of the plurality of drive circuits in the drive circuit region includes a first region and a second region, the first region is provided with a first type transistor of the drive circuit, and the second region is provided with a second type transistor of the drive circuit. One side of the first region is the side of the power line that is farther from the second region, and the other side of the first region is the side of the active layer of the first type transistor that is closer to the second region. A display substrate in which one side of the second region is the side furthest from the first power line region, and the other side of the second region is the side of the active layer of the first type transistor that is closer to the second region.

2. The power line includes a first power line, and the second input circuit is configured to input a first voltage signal from the first power line to the second node under the control of the potential of the third node. X1 / X3≧0.21, Here, X1 is the width of the first region in the first direction, and X3 is the width of the second region in the first direction. The display board according to claim 1, wherein the first direction is a direction intersecting the extending direction of the first power line.

3. The power line includes a second power line, and the second input circuit is configured to input a second voltage signal from the second power line to the second node under the control of the potential of the third node. X1 / X3≧0.52, Here, X1 is the width of the first region in the first direction, and X3 is the width of the second region in the first direction. The first direction is the direction that intersects with the direction of extension of the second power line. The first type of transistor is an N-type transistor, and the second type of transistor is a P-type transistor. The display board according to claim 1, wherein the distance between at least one N-type transistor and the second power line is smaller than the distance between the P-type transistor and the second power line.

4. The second input circuit includes a first transistor, the gate of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the second power line, the second electrode of the first transistor is electrically connected to the second node, and the first transistor is a first type transistor. WT1 / X1≧0.258, The display substrate according to claim 2, wherein WT1 is the width along the first direction of the active layer of the first transistor.

5. The drive circuit further includes a second output circuit, the second output circuit configured to output a second scanning drive signal via a second drive signal output terminal under the control of the potential of the third node, the second output circuit includes a second transistor, the gate of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the second power line, the second electrode of the second transistor is electrically connected to the second drive signal output terminal, and the second transistor is a first type transistor. WT2 / X1≧0.33, The display substrate according to claim 3, wherein WT2 is the width along the first direction of the active layer of the second transistor.

6. The second input circuit includes a first transistor, the gate of which is electrically connected to the third node, the first electrode of which is electrically connected to the second power line, and the second electrode of which is electrically connected to the second node; the drive circuit further includes a second output circuit, the second output circuit configured to output a second scanning drive signal via a second drive signal output terminal under the control of the potential of the third node; the second output circuit includes a second transistor, the gate of which is electrically connected to the third node, the first electrode of which is electrically connected to the second power line, and the second electrode of which is electrically connected to the second drive signal output terminal; and both the first and second transistors are first type transistors. WT2 / WT1≧3.25, The display substrate according to claim 3, wherein WT1 is the width of the active layer of the first transistor along the first direction, and WT2 is the width of the active layer of the second transistor along the first direction.

7. The display board further includes a group of clock signal lines provided in the drive circuit region, and the group of clock signal lines is configured to provide the clock signal. The active layer of at least one first type transistor is located between the clock signal lines and the power lines in a first direction. The display substrate according to claim 1, wherein the overlapping area between the orthogonal projection of the active layer of at least one first type transistor onto the base substrate and the orthogonal projection of the power lines onto the base substrate is 5 / 6 or less of the area of ​​the active layer of the at least one first type transistor.

8. The display substrate according to claim 1, wherein the ratio of the length of the active layer of at least one first type transistor along the second direction to the height of the drive circuit is 0.75 or less.

9. The display substrate further includes a first active layer provided in the second region, the first active layer includes a first active portion, two second active portions, and two third active portions, and the display substrate further includes a second output circuit. The first active portion functions as the active layer of the third transistor, the two second active portions function as the active layer of the fourth transistor, and the two third active portions function as the active layer of the fifth transistor. The third transistor is a transistor that outputs a first voltage signal provided by the first output circuit, the fifth transistor is a transistor that outputs a clock signal provided by the first output circuit, and the fourth transistor is a transistor that outputs a third voltage signal provided by the second output circuit. The channel area of ​​the nth transistor is ARn, where ARn ≥ 2(n-1)i, where n is 1, 2, or 3, and i is the unit channel area. The display substrate according to claim 1, wherein the area P1 of the first active portion is p, the sum of the areas P2 of the two second active portions is 2p or more and 3p or less, and the sum of the areas P3 of the two third active portions is 3p or more and 4p or less.

10. The display board further includes a clock signal line provided in the drive circuit region, the clock signal line is configured to provide a clock signal, and the first electrode of the fourth transistor is electrically connected to the third power line. The ratio of the first distance to the length of the active layer of the third transistor in the first direction is 10.78 or less. The display board according to claim 9, wherein the first distance is the distance between one side farther from the display area of ​​the clock signal line and one side closer to the display area of ​​the third power line.

11. The display board according to claim 9, further including a clock signal line provided in the drive circuit region, the clock signal line being configured to provide a clock signal, the first electrode of the fourth transistor being electrically connected to the third power line, the ratio of the line width of the first power line to the first distance being 0.060 or more, the line width of the first power line being the length along the first direction of the first power line, and the first distance being the distance between one side of the clock signal line far from the display region and one side of the third power line close to the display region.

12. The display board further includes a clock signal line provided in the drive circuit region, the clock signal line is configured to provide a clock signal, and the first electrode of the fourth transistor is electrically connected to the third power line. The display board according to claim 9, wherein the ratio of the line width of the third power line to the first distance is 0.045 or less, the line width of the third power line is the length along the first direction of the third power line, and the first distance is the distance between one side of the clock signal line that is farther from the display area and one side of the third power line that is closer to the display area.

13. The display board further includes a group of clock signal lines provided in the drive circuit region, the group of clock signal lines includes at least one clock signal line, the clock signal line is configured to provide a clock signal, and the display board includes at least two power lines. The display board according to claim 1, wherein the group of clock signal lines is located between two of the at least two power lines, or the group of clock signal lines is located on the side of the power line that is far from the display area.

14. The display board includes a first power line and a third power line, and the display board further includes a second output circuit, the second input circuit is configured to input a first voltage signal from the first power line to the second node under the control of the potential of the third node, and the second output circuit is configured to output a third voltage signal from the third power line to the second drive signal output terminal under the control of the potential of the third node. The ratio of the second distance to the length of the active layer of the third transistor in the first direction is 8.47 or less. The display board according to claim 13, wherein the third transistor is a transistor that outputs a first voltage signal provided by the first output circuit, and the second distance is the distance between one side of the first power line that is far from the display area and one side of the third power line that is close to the display area.

15. A display board, The system includes a shift register provided on a base board, the shift register includes a plurality of drive circuits, the drive circuits include a first input circuit, a second input circuit, a first output circuit, a control circuit and a second output circuit, the first output circuit is configured to provide a first scan drive signal to a first drive signal output terminal under control of the potentials of a first node and a second node, the first input circuit is configured to input a signal to a third node under control of a clock signal, the second input circuit is configured to input a signal from a power line to a second node under control of the potential of the third node, the control circuit is configured to control the potential of the third node and the potential of the first node, the second output circuit is configured to output a second scan drive signal via a second drive signal output terminal under control of the potential of the third node, the second input circuit includes a first transistor, and the second output circuit includes a second transistor. The aforementioned drive circuit is configured to provide a scanning drive signal to the display area. The gate of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the second power line, the second electrode of the first transistor is electrically connected to the second node, the gate of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the second power line, and the second electrode of the second transistor is electrically connected to the second drive signal output terminal. The first and second transistors are N-type transistors. A display substrate in which the ratio of the area of ​​the oxide active layer of the second transistor to the area of ​​the oxide active layer of the first transistor is 8.74 or greater.

16. The fourth transistor is a transistor that outputs the third voltage signal provided by the second output circuit, the fourth transistor is a P-type transistor, and the active layer of the fourth transistor is a low-temperature polysilicon active layer. The display substrate according to claim 15, wherein the ratio of the area of ​​the oxide active layer of the second transistor to the area of ​​the active layer of the fourth transistor is 1.4 or more.

17. The power lines include a first power line and a third power line, the second input circuit is configured to input a first voltage signal from the first power line to the second node under the control of the potential of the third node, and the second output circuit is electrically connected to the third power line and is configured to provide a third voltage signal from the third power line to the second drive signal output terminal under the control of the potential of the third node. The display board according to claim 15, wherein the voltage value of the third voltage signal is greater than or equal to the voltage value of the first voltage signal.

18. A display board, It includes a shift register provided on a base board, and the shift register includes multiple stages of drive circuits. The drive circuit includes a first input circuit, a second input circuit, a first output circuit, and a control circuit. The first output circuit is configured to provide a first scanning drive signal to the first drive signal output terminal under the control of the potentials of the first node and the second node. The first input circuit is configured to input a signal to the third node under the control of a clock signal. The second input circuit is configured to input a signal from the power line to the second node under the control of the potential of the third node. The control circuit is configured to control the potential of the third node and the potential of the first node, and is a display board.

19. The aforementioned power lines include a first power line and a second power line. The first input circuit is electrically connected to the input voltage terminal, the first clock signal line, and the third node, respectively, and is configured to write the input voltage from the input voltage terminal to the third node under the control of the first clock signal from the first clock signal line. The second input circuit is electrically connected to the third node, the second power line, the second node, and the first power line, respectively, and is configured to write a first voltage signal from the first power line to the second node and a second voltage signal from the second power line to the second node under the control of the potential of the third node. The first output circuit is electrically connected to the second node, the first node, the first power line, the second clock signal line, and the first drive signal output terminal, respectively, and is configured to output a first voltage signal from the first power line to the first drive signal output terminal under the control of the potential of the second node, and to output a second clock signal from the second clock signal line to the first drive signal output terminal under the control of the potential of the first node. The display board according to claim 18, wherein the control circuit is electrically connected to the second node, the first power line, the second clock signal line, the third node, the first node, and the second power line, respectively, and is configured to write a first voltage signal from the first power line to the third node under the control of the potential of the second node and the second clock signal from the second clock signal line, and to control the conduction between the third node and the first node under the control of the second voltage signal from the second power line.

20. It further includes a second output circuit, The second output circuit is electrically connected to the third node, the second drive signal output terminal, the third power line, and the second power line, respectively, and is configured to output a third voltage signal from the third power line to the second drive signal output terminal and a second voltage signal from the second power line to the second drive signal output terminal, under the control of the potential of the third node. The second output circuit is further electrically connected to the first control terminal, and the output terminal of the second output circuit is electrically connected to the second drive signal output terminal. The display board according to claim 19, wherein the second output circuit is further configured to output the third voltage signal to the second drive signal output terminal under the control of a first control signal from the first control terminal, and to output the second voltage signal to the second drive signal output terminal under the control of the potential of the third node and the first control signal.

21. The system further includes a constant voltage circuit, the output terminal of the second output circuit being electrically connected to the second drive signal output terminal via the constant voltage circuit, The display board according to claim 20, wherein the input terminal of the constant voltage circuit is electrically connected to the output terminal of the second output circuit, the output terminal of the constant voltage circuit is electrically connected to the second drive signal output terminal, and the constant voltage circuit is configured to constant the voltage of the signal output by the second output circuit, obtain a second scanning drive signal, and output it via the second drive signal output terminal.

22. The system further includes a first energy storage circuit and a second energy storage circuit, The first end of the first energy storage circuit is electrically connected to the output terminal of the second output circuit, and the second end of the first energy storage circuit is electrically connected to the second drive signal output terminal. The first end of the second energy storage circuit is electrically connected to the output terminal of the second output circuit, and the second end of the second energy storage circuit is electrically connected to the second drive signal output terminal. The display board according to claim 21, wherein the first energy storage circuit and the second energy storage circuit are configured to store electrical energy.

23. A display device comprising a display board according to any one of claims 1 to 22.

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