Hierarchical beamformer

Abstract

An apparatus and method for uplink and / or downlink beamforming operations are disclosed. In one embodiment, each of a plurality of distributed secondary beamformer processors is associated with a respective region of an antenna array and is associated with a respective beamforming submatrix. Each transmit or receive beamforming submatrix includes beamforming coupling weights associated with antenna elements within a respective region of the antenna array. Further, each secondary beamformer processor uses a respective beamforming submatrix and a respective set of frequency domain IQ data points (representing user data layers for transmission, or FDIQ data received from a corresponding set of transceiver ICs) to form a respective set of beamforming frequency domain IQ data points.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of U.S. Provisional Application No. 63 / 357587, filed on June 30, 2022, named "Hierarchical Beamformer" with inventors Yaniv Kaver, Efi Dror, Jongheon Kim, and Robert Irvine, which is hereby incorporated by reference in its entirety for all purposes.

Background Art

[0002] The present disclosure relates to the field of telecommunications, and more specifically, to the distribution of signals for transmission via antenna radiating elements. It can find applications in the field of wireless communications such as 2G / 3G / 4G, LTE, LTE - Advanced, and 5G.

[0003] This section is intended to introduce the reader to various aspects of the technology that may be related to the various aspects of the present disclosure described and / or claimed below. This description is considered useful in providing the reader with background information that facilitates a better understanding of the various aspects of the systems and methods described herein. Accordingly, it should be understood that these descriptions are to be read from this perspective and should not be read as an admission of prior art.

Summary of the Invention

[0004] The embodiments described herein include a hierarchical beamformer apparatus having a set of a primary beamformer processor and a secondary beamformer processor. In these embodiments, the primary beamformer processor allocates beamforming combining weights (optionally in combination with precoder combining weights) to form a complete beamforming matrix, and then distributes portions of the beamforming matrix to respective secondary beamformer processors. In some embodiments, the transceiver ICs may be partitioned according to their physical locations on the panel, and each set of transceiver ICs or transceiver IC subarrays within a given partition is serviced by and interconnected with a corresponding secondary beamformer processor, which in some embodiments may be distributed across the panel adjacent to or within the partition. Each distributed secondary beamformer processor may perform transmit beamforming, receive beamforming, or both. In the transmit direction (i.e., downlink or DL), the secondary beamformer receives frequency domain subcarrier IQ user data layers, applies respective allocated beamforming weights to the IQ user data layers, and computes complete beamforming IQ data points for distribution to respective partitioned subsets of transceiver ICs or transceiver IC subarrays. In the receive direction (i.e., uplink or UL), the secondary beamformer receives frequency domain subcarrier IQ data packets from the transceiver ICs, applies respective allocated receive beamforming weights to the IQ received packets, computes one or more partial beamforming IQ data packets, transfers them to the primary receive beamformer, where the partial beamforming IQ data is combined with other partial beamforming packets from other secondary receive beamformers. In some embodiments, each secondary receive beamformer computes one partial beamforming packet per received data layer. In other embodiments, each partial beamforming packet may correspond to a separately tilted beam.Embodiments of the secondary beamformer processor can include a digital signal processor circuit that executes software instructions to perform matrix multiplication operations, or can take the form of data registers interconnected with a hardware multiplier circuit that performs matrix operations.

[0005] According to embodiments described herein, the apparatus includes a primary receive beamformer processor and a plurality of distributed secondary receive beamformer processors connected to the primary receive beamformer processor, wherein the plurality of distributed secondary receive beamformer processors are physically distributed such that each distributed secondary receive beamformer processor is disposed within or adjacent to a respective region of an antenna array associated with one of each of a plurality of receive beamforming submatrices, each receive beamforming submatrix including receive beamforming coupling weights associated with antenna elements within a respective region of the antenna array, a plurality of sets of transceiver integrated circuit (IC) subarrays connected to the plurality of distributed secondary receive beamformer processors, wherein (i) each set of transceiver IC subarrays is connected to a corresponding one of the plurality of distributed secondary receive beamformer processors and is disposed within a respective region of an antenna array associated with the corresponding distributed secondary receive beamformer processor, and (ii) each distributed secondary receive beamformer processor is configured to receive from a set of the corresponding transceiver IC subarrays one or more respective sets of frequency domain IQ data points, and to form, using each respective set of frequency domain IQ data points and each receive beamforming submatrix, a plurality of respective sets of received partial beamforming frequency domain IQ data points and to transmit the plurality of respective sets of received partial beamforming frequency domain IQ data points to the primary receive beamformer processor.

[0006] In some embodiments, the primary receive beamformer processor is configured to combine corresponding sets of received partial beamforming frequency domain IQ data points received from all of the plurality of distributed secondary receive beamformer processors to form a plurality of complete beamforming frequency domain subcarrier IQ user data layers. Further, in some embodiments, the primary receive beamformer processor partitions the receive beamforming matrix of beamforming combining weights into a plurality of receive beamforming submatrices and is configured to transmit each respective receive beamforming submatrix to a corresponding one of the plurality of distributed secondary receive beamformer processors.

[0007] In some embodiments, each distributed secondary receive beamformer processor is further configured to form respective pluralities of partial beamforming frequency domain IQ point sets by applying the receive beamforming combining weights of the respective receive beamforming submatrices to respective sets of frequency domain IQ data points. The respective pluralities of received partial beamforming frequency domain IQ data points represent, in some embodiments, respective pluralities of partial beamforming frequency domain subcarrier IQ user data layers.

[0008] In some embodiments, each distributed secondary receive beamformer processor comprises a packet processor configured to form corresponding plural receive partial beamforming frequency domain IQ data packets for transmission to the primary receive beamformer processor using respective plural sets of receive partial beamforming frequency domain IQ data points. In this regard, in some embodiments, the corresponding plural receive partial beamforming frequency domain IQ data packets have headers indicating at least component carrier information. Further, in some embodiments, each distributed secondary receive beamformer processor comprises a serial data interface circuit for communicating with each transceiver IC or each transceiver IC subarray within a corresponding set of transceiver ICs or IC subarrays.

[0009] Further, in some embodiments, the apparatus further comprises a transmit primary beamforming processor and plural distributed secondary transmit beamformer processors connected to the transmit primary beamforming processor, wherein the primary transmit beamforming processor and the primary receive beamforming processor are implemented in a signal processor circuit, a field programmable gate array (FPGA), etc., and the plural distributed secondary transmit beamformer processors and the plural distributed secondary receive beamformer processors comprise plural distributed secondary beamformer processors, and each distributed secondary beamformer processor performs both transmit beamforming operations and receive beamforming operations.

[0010] According to the embodiments described in this specification, the method comprises receiving, in each of a plurality of distributed secondary receive beamformer processors connected to a primary receive beamformer processor, a respective set of frequency domain IQ data points from a corresponding one of a plurality of transceiver integrated circuits (ICs) or a set of transceiver IC subarrays, wherein the plurality of distributed secondary receive beamformer processors are physically distributed such that each distributed secondary receive beamformer processor is disposed within or adjacent to a respective region of an antenna array associated with a respective one of the plurality of receive beamforming submatrices, each receive beamforming submatrix includes receive beamforming coupling weights associated with antenna elements within a respective region of the antenna array, and the corresponding set of transceiver IC subarrays are disposed within a respective region of the antenna array associated with the distributed secondary receive beamformer processor, forming, by each distributed secondary receive beamformer processor, a respective plurality of sets of received partial beamforming frequency domain IQ data points using the respective sets of frequency domain IQ data points and the respective receive beamforming submatrices, and transmitting, by each distributed secondary receive beamformer processor, the respective plurality of sets of received partial beamforming frequency domain IQ data points to the primary receive beamformer processor.

[0011] In some embodiments, the method further includes combining corresponding sets of received partial beamforming frequency domain IQ data points received from all of a plurality of distributed secondary receive beamformer processors by a primary receive beamformer processor to form a plurality of frequency domain subcarrier IQ user data layers. In some embodiments, calculating, by each distributed secondary receive beamformer processor, a respective plurality of sets of partial beamforming frequency domain IQ data points using a respective set of frequency domain IQ data points and a respective receive beamforming partial matrix includes applying receive beamforming combining weights of the respective receive beamforming partial matrix to the respective set of frequency domain IQ data points. Also, in some embodiments, the respective plurality of sets of received partial beamforming frequency domain IQ data points represent respective plurality of partial beamforming frequency domain subcarrier IQ user data layers.

[0012] Further, in some embodiments, the method includes partitioning, by a primary receive beamformer processor, a receive beamforming matrix of beamforming combining weights into a plurality of receive beamforming partial matrices and conveying each respective receive beamforming partial matrix to a corresponding one of a plurality of distributed secondary receive beamformer processors. The weights may be conveyed through a control plane message including the weights or a beamforming index indicating predetermined beamformer weights stored in a secondary beamformer. In some embodiments, the corresponding plurality of received partial beamforming frequency domain IQ data packets have headers indicating at least component carrier information.

[0013] Further, in some embodiments, each distributed secondary receive beamformer processor comprises a serial data interface circuit for communicating with each corresponding set of transceiver ICs, or transceiver IC subarrays of a corresponding set of transceiver IC subarrays.

[0014] References to "one embodiment", "an embodiment", "exemplary embodiments", etc. in this specification indicate that the embodiments described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes that particular feature, structure, or characteristic. Further, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, such feature, structure, or characteristic may be used in connection with other embodiments whether or not explicitly described.

Brief Description of the Drawings

[0015]

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[0016] FIG. 1 shows an antenna array assembly 100 according to some embodiments. As shown, the antenna array assembly 102 has a grid of radiating elements (also referred to herein as antenna elements or antenna radiating elements) generally disposed in rows (e.g., row 104) and columns (e.g., column 100) on a panel 102, which can be a printed circuit board (PCB) for the radiating elements or other suitable support structure. Positions within the grid, such as position 116, have juxtaposed radiating elements, such as elements 112 and 114, which can typically provide different radiation polarization, such as horizontal and vertical polarizations, or equivalently plus 45 degrees (+45°) and minus 45 degrees (−45°). The grid of radiating elements may be arranged in a regular array pattern as shown in FIG. 1. In one embodiment, the radiating elements are spaced apart by approximately a half wavelength (λ) distance, where the wavelength (λ) is associated with the desired frequency operating range of the antenna array, which can be associated with the carrier frequency of the system, or more generally, the center frequency of the system, particularly in embodiments using a frequency division duplexing (FDD) system that utilizes multiple carrier frequencies. Some embodiments may operate within multiple frequency bands, and in such an embodiment, an array as shown in FIG. 1 may be configured to operate within a first band using a first frequency of wavelength λ1 and operate within a second frequency band having a wavelength λ2 = 2λ1. In such an embodiment, operation in the first band (λ1) can utilize adjacent antenna radiating elements spaced apart by a distance of 0.5λ1 as shown, but for operation in the second, lower frequency band (having wavelength λ2), two spaced-apart (e.g., every other row, or every other column) elements have a spacing of 0.5λ2 and can thus be used for operation in the second frequency band.

[0017] The antenna array panel may be composed of more antenna pairs (e.g., 128, 194, 256, 512, etc.) or even fewer antennas (e.g., 32, 16, etc.). However, the specific array in FIG. 1 shows 64 horizontal radiating elements and 64 vertical radiating elements arranged in an 8×8 square configuration, juxtaposed in pairs, on a panel of approximately 35 - 40 centimeters by 35 - 40 centimeters, with the radiating elements spaced approximately 4.3 centimeters apart. The antenna array assembly 100 also includes a circuit board assembly 128 that includes a power module 130, a clock distribution circuit 132, a global positioning system (GPS) receiver 134, a processor circuit 138 for performing packet protocol processing in particular, beamforming in some embodiments, a network data interface 136, a power connector 140, and a GPS connector 142.

[0018] In various embodiments described below herein, the radiating elements can be grouped into sub - arrays such as column sub - array 106 having 8 vertical radiating elements and 8 horizontal radiating elements, or smaller sub - arrays such as groups 108 and 122 each having 4 horizontal elements and 4 vertical elements, or groups 110, 120, 124, 126 each having 2 vertical radiating elements and 2 horizontal radiating elements. In some embodiments, the antenna sub - array may comprise a two - dimensional set of elements such as 4 cross - polarized radiating elements arranged in a square configuration, or 6 cross - polarized pairs arranged in a 2×3 grid. Alternative forms include a set of two or more adjacent vertically polarized elements forming one antenna element sub - array and a corresponding set of vertically polarized elements of cross - polarized pairs forming a separate sub - array. In further embodiments, each cross - polarized pair of radiating elements may be an individually driven array element.

[0019] Each subarray of the radiation elements can be driven by a radio frequency (RF) signal generated by a set of transceivers located adjacent to the antenna. As used herein, the term "antenna subarray" is functionally interrelated primarily according to the connection to the corresponding set of cooperative RF transceiver integrated circuits (ICs) used to process the RF signal associated with the radiation elements of the antenna subarray, and refers to a group of radiation elements arranged in a corresponding array pattern. In such a case, the transceiver circuit includes a first transceiver IC connected to the beamformer processor via a serial data connection (or "link"), and a set or group of serially connected transceiver integrated circuit packages (hereinafter referred to as "transceiver ICs") having a series of point-to-point serial data connections between the transceiver ICs. In some embodiments, the data path terminates at the last transceiver IC of the group. In an alternative embodiment, the transceiver ICs may be interconnected in a ring configuration, and the last transceiver IC in the chain may be connected back to the beamformer processor using an additional serial data connection, or may be connected to the last transceiver IC in a separate subarray chain of serially connected transceiver ICs.

[0020] In some embodiments, it should be noted that a given group of transceiver ICs (i.e., a set of serially connected transceiver ICs) within a transceiver IC subarray associated with a corresponding antenna subarray may be capable of processing independent RF signals for each radiating element. Thus, as used herein, the term "antenna subarray" refers to a set of antenna elements (of a possibly larger antenna element array in some cases) associated with a given set of transceiver ICs. In some embodiments described herein, a group of radiating elements can operate in a cooperative manner by transmitting the same or similar RF signals (or a set of RF signals for H and V polarizations) with possible phase differences therebetween to achieve a desired radiation pattern for beamforming, antenna tilt, or the like.

[0021] Figure 2 shows a wireless unit architecture having multiple groups of serially connected transceivers used to process RF communication signals associated with corresponding groups of antenna radiating elements, according to some embodiments. As shown in Figure 2, each serially connected transceiver IC group includes at least two serially connected transceiver ICs physically arranged within a transceiver IC subarray. Specifically, transceiver IC 222 connected to beamformer processor 202 via serial data link 206 is also serially connected to transceiver IC 232 via full-duplex serial data link 228, thereby forming a transceiver IC subarray oriented vertically along a column of a panel array such as group 110. Similarly, transceiver IC 212 is connected to transceiver IC 230, forming another transceiver IC subarray.

[0022] In embodiments that use a beamformer (primary and / or secondary) and each serial data link from a transceiver IC, as well as an IC subarray, each serial data link between transceiver ICs (e.g., 228) uses a Serdes (Serializer / Deserializer) transceiver or a set of Serdes transceivers to establish a point-to-point link. In one embodiment, each transceiver IC includes two such Serdes transceivers. Alternatively, a greater number of Serdes devices may be included to provide a higher level of interconnectivity between transceiver ICs. Serdes can be implemented as a low-voltage I / O transceiver that utilizes a standard serial data signaling format, such as a two-level pulse amplitude modulation (PAM2) non-return-to-zero (NRZ) differential signal transmitted on a pair of conductors. PAM3 and PAM4-based signaling is also suitable. Higher-level protocols, such as PCIe (Peripheral Component Interconnect Express) or USB (Universal Serial Bus), can be used in combination with the physical layer SERDES. The serial data connection can include a multi-lane link (a plurality of serial data connections operating in parallel in each link). In one embodiment, a data rate of 6 gigabits per second (Gbps) PAM2 is sufficient to carry an aggregated signal port IQ data packet (including a header) and to provide additional throughput capacity for transmitting control plane messaging to the transceiver IC. The serial link data rate can be selected to accommodate data packets between individual transceiver IC subarrays according to a desired deployment, including a desired number of independent signal ports, a desired number of component carriers, multi-band operation (thereby adding additional carriers), FDD or TDD, and the number of transceiver ICs connected within the transceiver IC subarray.

[0023] Furthermore, in some embodiments, each serial data link between the beamformer processor 202 and a given transceiver IC or transceiver IC subarray, as well as the serial data links that serially interconnect individual transceiver ICs within a given transceiver IC subarray, can have a data rate sufficient to accommodate data packets that carry IQ data in either the frequency domain or the time domain. In this regard, each transceiver IC or IC subarray may, for example, (i) receive / transmit aggregated frequency domain IQ data packets to / from the beamformer processor if frequency-time domain conversion (transmission DL side) and time-frequency domain conversion (reception UL side) are performed at the individual transceiver ICs (e.g., via respective iFFT (inverse fast Fourier transform) and FFT (fast Fourier transform) processing), or (ii) receive / transmit aggregated time domain IQ data packets to / from the beamformer processor if frequency-time domain conversion (transmission DL side) and time-frequency domain conversion (reception UL side) are instead performed at the beamformer processor (e.g., via respective iFFT and FFT processing).

[0024] As an example of a serial link data rate, one symbol of a 100 MHz OFDM 5G carrier with a 30 kHz subcarrier spacing is transmitted in a 33.33 microsecond (μs) time window. For such transmission on two signal ports (e.g., separate signals for H and V polarization) having 3300 subcarriers, 2 samples (I / Q) per subcarrier, and, for example, 12 bits / sample, the data rate required is 2×3,300×2×12 = 158.4 kbps for each of 14 OFDM symbol time slots, 14 of which are transmitted in a 0.5 millisecond transmission slot, resulting in a net required data rate of 158.4 k×14 bits / 0.5 millisecond = 4.43 Gbps. When 8b-10b encoding is used on the serial data link and an additional 10% is added for packet headers and protocol overhead, for the dual signal port case, a throughput of approximately 1.1×4.43×10 / 8 Gbps = 6.1 Gbps per carrier is required. In some embodiments, a serial data transmission capacity of 6.1 Gbps is sufficient for each transceiver IC. For a transceiver IC subarray (i.e., a set of serially linked transceiver ICs), 6.1 Gbps is still sufficient for many deployment scenarios. In other embodiments having signal ports independently controlled in each transceiver IC, a total throughput of 12 Gbps, or even on the order of 20 Gbps, is sufficient for most of the uses and configurations described herein, but 30 Gbps may be achieved if desired for some other embodiments.

[0025] For lower-capacity deployments, a lower serial data rate is sufficient. For example, a dual-polarization 20 MHz 4G LTE data signal utilizing a size 2,048 FFT that occupies a transmission slot time window of 66.67 μs requires a data throughput of 2 ports × 1,200 subcarriers x 2 (I / Q samples / subcarrier) x 12 (bits / sample) / 66.67 μs window = 1,200 x 2 x 12 / 66.67 μs = approximately 864 Mbps. If the data rate is increased by 10 / 8 to accommodate 8b-10b encoding and the overhead is 10%, the data rate is approximately 1.2 Gbps.

[0026] In a further embodiment of the transceiver IC serial data port, a 4-wire interface can be used to double the data rate. Alternatively, so-called ensemble NRZ (ENRZ) signaling, which uses correlation signals in the form of vector signal codes, may be transmitted over 4 wires to carry 3 bits per baud (i.e., per signaling interval), resulting in a 3-fold increase in data rate rather than just a 2-fold increase. Thus, using a signaling rate of 7.5 G baud / s, a data throughput of 22.5 Gbps can be reliably achieved over the distance from the beamformer to the transceiver IC subarray. As a further alternative, PAM4 signaling (in combination with NRZ or ENRZ signaling), or other vector signal formats (e.g., correlated NRZ (so-called CNRZ-5) that uses correlation signals to carry 5 bits over 6 wires), can be used to increase the data throughput without significantly increasing the signaling baud rate.

[0027] Overall, FIG. 2 shows a total of eight columns of transceiver ICs, each column having eight transceiver ICs for a total of 64 transceiver ICs, and each transceiver IC is configured to process two separate transmit signals (e.g., different RF signals on the H and V signal ports) and two separate receive signals (H / V signal ports). However, in the embodiment of FIG. 2, the first two rows of the eight transceiver ICs are connected in pairs, so these 16 transceiver ICs form a single "row" 238a of eight transceiver IC groups, also referred to herein as transceiver IC sub-arrays. Similarly, the other transceiver ICs are grouped into three further "rows" (238b, 238c, 238d) of each of the eight transceiver sub-arrays, resulting in a total of eight columns by four rows of transceiver IC groups (32 transceiver IC sub-arrays). In terms of physical dimensions, each column is the width associated with a single juxtaposed cross-polarized antenna, while each "row" of the transceiver IC group includes two rows of cross-polarized antenna elements.

[0028] FIG. 4, which is further described below, also shows the 32 transceiver IC sub-arrays within the 8×4 transceiver IC sub-array configuration. However, each transceiver IC sub-array includes three serially connected transceiver ICs. Note that the transceiver IC sub-arrays are arranged adjacent to the corresponding radiating antenna elements, element by element, in a corresponding antenna sub-array. In some embodiments, the transceiver IC sub-arrays are located on the back side of the antenna array panel 102 but are still adjacent (i.e., close) to each of the radiating elements used to transmit and / or receive the RF communication signals associated with a given transceiver IC. In some embodiments, the transceiver ICs can be coupled to the radiating elements through vias, intermediate structures, and / or circuitry, such as transmit filters and receive filters mounted on the panel or on a sub-panel located behind the structure supporting the array of antenna radiating elements.

[0029] Element-by-element adjacency refers to the relative arrangement in which a transceiver IC subarray and a corresponding antenna subarray are superimposed on each other such that each individual transceiver IC of a given transceiver IC subarray is disposed within the area of panel 102 associated with the corresponding antenna radiating element of the antenna array or subarray used to transmit and receive signals associated with that individual transceiver IC.

[0030] As a further example of element-by-element adjacency, in some embodiments such as a frequency division duplexing (FDD) system, two transceiver ICs (one dedicated to generating two transmit (H / V) signals at the transmit frequency and the other for processing two receive (H / V) signals at the receive frequency) can form a transceiver IC subarray associated with an antenna subarray consisting of a single juxtaposed cross-polarized antenna. In a dual-band FDD configuration, four transceiver ICs can be linked as a transceiver subarray and disposed adjacent to an antenna subarray consisting of a single juxtaposed cross-polarized antenna.

[0031] The element-by-element adjacency feature provides a distributed transceiver IC architecture that allows the amplified transmit RF signal generated by each given transceiver IC to experience very little power loss or noise degradation as it crosses the very short physical connection from the transceiver IC to the radiating element. In some embodiments, different ratios of transceiver ICs to radiating elements can be adjacent in pairs, such that two transceiver ICs can be disposed adjacent to each set of three cross-polarized elements.

[0032] Throughout this description, many embodiments are depicted using transceiver ICs (e.g., 212, 222, 230, 232, etc.) that include two independent full-dual transceivers each having two transmitters / amplifiers and two independent receivers, with each transceiver associated with an RF signal port (e.g., 214 or 216) interconnected to respective antenna radiating elements (e.g., 218, 220, respectively). Thus, in one embodiment, a single transceiver IC comprises an integrated circuit having two full transceivers for transmitting and receiving two independent RF signals configured such that one RF signal port (tx / rx) is associated with an H-polarized signal port (e.g., 214) and one RF signal port (tx / rx) is associated with a V-polarized signal port (e.g., 216). In such an embodiment, each transceiver IC may be referred to as a 2T2R transceiver IC and may be associated with a pair of juxtaposed cross-polarized radiating elements. As an illustrative example, each cross-polarized pair of radiating elements (218, 220), (224, 226), (234, 236) is associated with a respective single transceiver integrated circuit such as transceiver IC 212 associated with cross-polarized radiating elements (218, 220), transceiver IC 222 associated with elements (224, 226), and transceiver IC 232 associated with elements (234, 236).

[0033] In other embodiments, each transceiver IC may be configured to provide four separate analog RF transmit and receive paths, for example, through four independent signal ports (4T4R). Such embodiments may include a dual PLL for generating the carrier frequencies of both the transmit carrier and the receive carrier for full utilization of the transceiver IC when operating in FDD signaling mode. The particular number of transceivers included within a given transceiver IC may depend on factors such as the desired total output power of the panel, the use of additional external power amplifiers, FDD or TDD operation, the data transfer capacity of the serial data link providing interconnection between transceiver ICs, and many other factors.

[0034] More generally, referring to FIG. 2, the circuitry of the wireless unit 200 may all be disposed within a single active antenna panel assembly and includes a high throughput packet-based interface 252 to a base station or distributed unit (DU) (not shown). The interface 252 may comprise a plurality of separate physical network interfaces, such as four separate 25 gigabit Ethernet links provided via an optical fiber cable using a small form factor pluggable (SFP) module 242 or a quad SFP (QSFP) module. Data may be conveyed via the interface 240 using an Ethernet protocol, a CPRI / eCPRI protocol, or a similar protocol. The beamformer processor (BFP) 202 performs precoding and beamforming operations for downlink transmit data and, in response, generates an aggregated signal port IQ data packet for transmission to each transceiver IC subarray, as further described below with reference to FIGS. 8, 9, and 10. In some embodiments, the IQ data packet may comprise frequency domain IQ values of subcarriers within an OFDM (orthogonal frequency division multiplexing) communication system, such as an LTE or 5G communication system. In other embodiments, the IQ data packet may instead comprise time domain IQ values representing the sum of subcarriers within the OFDM communication system. In the uplink direction, the BFP 202 performs beamformer combining to acquire virtual beamforming antenna port signals and further combining to recover the user data layer, as further described below with reference to FIG. 11.

[0035] In the embodiment shown in FIG. 2, the beamformer processor 202 is connected to each transceiver IC subarray via a serial data link such as link 206. Depending on the length of the data links shown as four sets 204a, 204b, 204c, 204d of eight links each, each data link can utilize Serdes repeaters / retimers 208, 210 to extend the range of the serial data link from the BFP 202 to the region of panel 102 where a given transceiver IC subarray (and corresponding antenna subarray element) is located. In the alternative embodiment shown in FIG. 4, the BFP 400 is connected to a set of transceiver IC subarrays via a high-speed Serdes link 402, and then a Serdes multiplexer (MUX) 404 (and respective high-speed links to Serdes MUXes 422, 424, 426) demultiplexes (i.e., separates) the high-speed serial data stream into slower-speed serial data streams 406 directed to each individual transceiver IC subarray. The Serdes MUX devices 404, 422, 424, 426 perform a demultiplexing operation on the uplink data being conveyed from the transceiver IC subarrays to the BFP 202.

[0036] Referring to FIG. 2, one exemplary transceiver IC subarray comprises transceiver IC 222 and transceiver IC 232 coupled via serial data link 228. These two transceiver ICs are located adjacent to respective antenna radiating elements 224, 226 and 234, 236. In some embodiments, they are disposed on one side of the printed circuit board in proximity to the antenna elements and are electrically connected using through vias or by intermediate circuit elements such as filters, diplexers, quadplexers, SPDT (single-pole double-throw) TDM switches. As shown in FIG. 2, each transceiver IC generates two separate RF transmit downlink (DL) signals for H and V polarities and receives and processes two separate RF uplink (UL) signals. Also shown is an observation transceiver 260 connected to BFP202 by serial data link 256, and RF signal connection 258 is interconnected with each transceiver via a calibration network.

[0037] FIG. 3 shows one such group of serially connected transceivers arranged at the transceiver IC subarray positions adjacent to each corresponding antenna radiating element of the corresponding antenna subarray disposed within the antenna panel array 102. An incoming packet for DL transmission is received at the first transceiver IC 312 from the BFP via the serial data link 308, and at least some of the packets are propagated to other transceiver circuits within the transceiver ICs 350, 366 within the transceiver group through the serial data connections 348, 364. Similarly, the incoming RF signals on the UL are processed and packetized for sending back along the serial data transceiver IC chain 362, 346, 310. In this embodiment, each transceiver IC is configured to process two separate transmit signal paths and two separate receive signal paths via two separate signal ports typically associated with two corresponding antenna radiating elements. The transceiver subarray of FIG. 3 operating in TDD mode is configured such that the transceiver IC 312 transmits and receives RF signals on the first signal port 328 and transmits and receives RF signals on the second signal port 344. Similarly, the transceiver IC 350 is associated with the signal ports 356 and 360, and the transceiver IC 366 is associated with the signal ports 370 and 378.

[0038] As described above, the two transceiver signal ports of the transceiver IC may be interconnected to a single set of cross-polarized antenna elements. In the case of TDD operation, this provides 2T2R (two transmit and two receive) signal processing capabilities. In an alternative embodiment, the two signal ports may each be connected to corresponding radiating elements within two different cross-polarized antenna pairs. For example, the first transceiver of the transceiver IC process transmits and receives signals related to the vertical polarized element of the first cross-polarized radiating element pair, and the second transceiver of the same transceiver IC process transmits and receives signals related to the vertical polarized element of the second cross-polarized radiating element pair. Next, the second transceiver IC can be used to process signals related to the two horizontal polarized elements of the two cross-polarized pairs.

[0039] In a further alternative embodiment, the output of each signal port is split and one signal port is connected in parallel to two (or three, etc.) vertically polarized radiating elements, and the other signal port is connected in parallel to horizontally polarized radiating elements of the same two (or three, etc.) cross-polarization pairs, etc., and may be connected in parallel to a plurality of radiating elements. In further embodiments described herein below, the amplified RF signals generated by a transceiver IC or by a plurality of transceiver ICs may be provided to additional amplifier stages external to the transceiver IC and / or combined before being provided to the radiating elements.

[0040] In some embodiments, frequency domain I / Q data packets are transmitted to a set of serially connected transceiver ICs distributed on an active antenna panel. The aggregated data packets are a superposition of frequency domain sub-carrier specific data and typically represent resource blocks (RBs) allocated over many data layers and possibly many users, with different beamforming weights applied, and thus contain full beamforming (including MIMO precoding if used) sub-carrier IQ sample data for a specified band, component carrier, and signal port. Each IQ data packet may have a single header, but nevertheless may contain concatenated or interleaved data for multiple signal ports such as H and V signal ports. Such packets may be referred to as dual signal port packets. In some embodiments, the packet header may include identification data associated with a particular transceiver IC and may include IQ data for any number of signal ports processed by that transceiver IC and may generally be referred to as multi-signal port data.

[0041] The user-aggregated frequency-domain data of packet 302 in FIG. 3 represents frequency-domain IQ data packets that are commonly processed by transceivers within a given transceiver IC subarray. Packet 302 may include a header (not shown for clarity) that identifies various aspects of the type of data contained in the packet, as well as packet identification data such as one or more of a frequency band ID, a component carrier ID, a signal port ID, and / or a transceiver ID. The primary payload data within packet 302 includes subcarrier-specific IQ data for a signal port (e.g., a horizontal polarization RF signal for a particular component carrier labeled "H" in FIG. 3). The same packet (or, in some embodiments, a separate packet with a separate header and ID data fields) includes subcarrier IQ data for a second signal port (e.g., a vertical polarization RF signal for, e.g., the same component carrier labeled "V" in FIG. 3). In many of the embodiments described herein, a single transceiver IC is configured to process two separate signal port IQ packets, and the corresponding IQ data for the two signal ports may be combined into a single packet having a single header, which may sometimes be referred to herein as a "dual signal port packet." Packet 302 is shown as a concatenated IQ data set for the subcarriers of an H-polarization signal port and a V-polarization signal port, but the IQ data may be interleaved, such as an IQ sample pair for the H signal port and pair for the V signal port for subcarrier 1, followed by IQ pairs for H and V for subcarrier 2, etc. Each I and Q sample may be represented as a number of bits, such as 12, 14, or 16, depending on the desired signal resolution. Packet 302 may include IQ sample data for some number of subcarriers, such as 612, 1,596, 3,276, or more, for each signal port, for a particular carrier, and for a frequency band.

[0042] Note that the aggregated beamforming IQ data packets communicated from / to the BFP (beamformer processor) via the serial data connection (link) and between transceiver ICs can include either frequency-domain IQ data or time-domain IQ data. In this regard, note that packet data transmission of the aggregated beamforming frequency-domain IQ data packets via the serial data connection from / to the BFP and between transceiver ICs is more efficient than packet data transmission of the aggregated beamforming time-domain IQ data. In particular, the frequency-domain IQ data specifies the in-phase and quadrature (IQ) values of specific subcarriers used for data transmission (and reception) in a given communication system. However, in the case of DL signals in an OFDM communication system (e.g., an LTE or 5G communication system), 0 values may need to be inserted into the IQ data set to account for unused subcarriers (e.g., subcarriers used as guard bands) within a given component carrier before converting the frequency-domain IQ data to time-domain digital data via an iFFT, thereby resulting in a time-domain sequence of the converted IQ data having more IQ data points that need to be carried to / by the transceiver IC / transceiver IC subarray (e.g., first carried from the BFP and then distributed among the transceiver ICs within a given transceiver IC subarray accordingly). Similarly, in the case of UL signals, the frequency-domain IQ data processed via an FFT can exclude the frequency-domain values of the unused subcarriers, but the equivalent time-domain IQ data associated with the unused subcarriers is a component of the time-domain IQ data that may not be removed before transmission of the time-domain data via the serial data connection as described herein.

[0043] In this regard, depending on the bandwidth of a given communication channel, an increase in the efficiency of communicating frequency domain IQ data across the corresponding time domain IQ data can be relatively important. As an example, in the case of a 20 MHz wide LTE channel, the ratio of unused subcarriers to data modulated subcarriers will be larger than the similar ratio in the case of a 100 MHz wide LTE channel. Therefore, it is more efficient to communicate subcarrier specific IQ data in the frequency domain rather than in the time domain. More specifically, as described above, even if a subset of subcarriers remains unused (not modulated / loaded with data), their time domain representation still results in complex time domain samples, thereby increasing the amount of data that needs to be transmitted over a serial data link. Further, the serial data link between the BFP subarray and the transceiver IC subarray, as well as the serial data links interconnecting individual transceiver ICs within a given transceiver subarray, may have a limited data carrying capacity (e.g., how much data can be communicated over those links per given period (data rate)). Therefore, in some embodiments, it may be more desirable to perform IQ packet data transmission in the frequency domain, from / to the BFP and between transceiver ICs.

[0044] Nevertheless, various embodiments of the signal processing methods and apparatuses described herein can utilize time domain IQ data packets instead. More specifically, in some embodiments, a beamformer processor (BFP) (e.g., BFP202, 300, 400, etc.) can be configured to include digital signal processing architectures (e.g., iFFT and FFT processing elements) to transmit and receive time domain IQ data packets from / to transceiver IC / transceiver IC subarrays. For example, in some embodiments, the beamformer processor may include a digital signal processor (DSP) configured with appropriate programming instructions to execute algorithms for IFFT and FFT operations.

[0045] The transceiver subarray shown in FIG. 3 is one of many such subarrays on the panel, and each serially connected transceiver IC group receives a unique data stream of aggregated signal port (or dual signal port, or multi-signal port) IQ data packets. Each serially connected transceiver IC group has at least two serially connected transceiver ICs and is to be recalled as being physically located within the transceiver IC subarray. Next, the transceiver IC subarray is disposed adjacent to each corresponding radiating antenna element disposed in the corresponding antenna subarray.

[0046] Transceiver IC 312 receives a unique data stream of signal port IQ data packets aggregated in serial port receiver 314 and provides the data to split copy register 318 for further processing. In one embodiment, split copy register 318 is a packet header processor configured to examine the packet header to determine whether the IQ data is intended to be processed by its corresponding transceiver IC, and if so, transfer the packet to signal port split processor 320. Signal port split processor 320 (also labeled H / V split) is addressed to different signal ports within the transceiver IC and identifies H and V polarization signals, or packets or portions of packets that may be other configurations described herein. Signal port split processor 320 may be implemented as a register that performs a memory write operation to a digital signal processor (DSP) memory space integrated within transceiver IC 312. Further, split copy register 318 can determine that the same packet should also be transferred to the next transceiver IC in the transceiver IC subarray for processing by one or more of the serially connected transceiver ICs. To reduce latency, packet header processor or split copy register 318 does not need to buffer the entire signal port IQ data packet before making a decision to transfer the packet to the next transceiver IC by sending the data to serial data transmitter 332 for transmission via serial link 348. In a further embodiment, packet header processor 318 may be configured to operate in a transparent mode, in which case all packets are saved for local processing and transferred to a second serial transceiver without header inspection.

[0047] Regarding the signal port packet format 302, the aggregated IQ signal ports are transferred to each transceiver IC using split copy circuits 318, 352, 368 and are commonly processed by each transceiver IC. Transceiver IC 366 is the last transceiver IC in the chain and in the illustrated embodiment, note that split copy register 368 transfers the packet to the corresponding signal port split processor, but serial transceivers 372 / 374 are not used.

[0048] Next, each transceiver IC processes the packet by first separating the IQ data for the first signal port (H IQ data 322) and the second signal port (V IQ data 338) and providing the data to the transmitters within transceivers 321 and 335 to convert to the time domain via an inverse fast Fourier transform (iFFT). As previously explained, the individual IQ port specific data may be carried in separate packets, in which case the signal port data may be stored directly for further processing without any separation or deinterleaving. The iFFT processing and subsequent time domain processing generates an aggregated signal port discrete time domain baseband data signal, which is then followed by conversion to a radio frequency (RF) signal amplified at ports 328, 344. The transmitters of transceivers 321, 335, more fully described with respect to FIGS. 12A and 13A, include a DSP for calculating the iFFT, frequency domain and time domain signal processing elements (cyclic prefix addition, phase and gain adjustment, frequency offset, filtering and sample rate conversion, crest factor reduction (CFR), digital pre-distortion (DPD), etc.), and RF modulation and amplification circuitry in the form of a polyphase carrier generator and digital power amplifier. Note that in an alternative embodiment, for example, including the communication of aggregated signal port / user IQ data packets in the time domain (as described above), the iFFT processing may be performed in the beamformer processor instead of the transceiver IC itself.

[0049] Accordingly, some embodiments include receiving, in each of a plurality of serially-connected transceiver IC groups, a unique data stream of aggregated signal port IQ data packets, where each serially-connected transceiver IC group is physically disposed within a transceiver IC subarray and includes at least two serially-connected transceiver ICs disposed adjacent to each corresponding radiating antenna element disposed within a corresponding antenna subarray; transferring, within each serially-connected transceiver IC group, at least a subset of the aggregated signal port IQ data packets from a first transceiver IC to the next serially-connected transceiver IC; processing, in each transceiver IC of the at least two serially-connected transceiver ICs within each serially-connected transceiver IC group, at least a portion of the aggregated signal port IQ data packets using an integrated inverse fast Fourier transform (IFFT) processor of the transceiver IC to convert the aggregated signal port IQ data packets into an aggregated signal port discrete-time domain baseband data signal; converting the aggregated signal port discrete-time domain baseband data signal into an amplified modulated radio frequency signal using an integrated digital power amplifier and a polyphase carrier generator of the transceiver IC; and transmitting the amplified modulated radio frequency signal using at least one of the corresponding adjacent radiating antenna elements.

[0050] Furthermore, some embodiments can include an apparatus comprising a plurality of transceiver IC sub-arrays, each transceiver IC sub-array including: (i) a first serial digital data port that provides a serial data connection to a beamformer processor and is configured to receive a unique data stream of an aggregated signal port IQ data packet; and (ii) a first transceiver IC having a second serial digital data port; and a second transceiver IC connected to the second serial data port of the first transceiver IC and having a third serial digital data port that provides a serial data connection to the first transceiver IC. The first transceiver IC and the second transceiver IC are physically disposed within the transceiver IC sub-array and can be disposed adjacent to each of a plurality of radiating antenna elements disposed within an antenna sub-array. The first transceiver IC of each transceiver IC sub-array can further include a packet processor configured to transfer at least a subset of the aggregated signal port IQ data packets received from the beamformer processor to their respective second transceiver ICs. Each of the first transceiver IC and the second transceiver IC can include a digital signal processor configured to perform an inverse fast Fourier transform (IFFT) to convert the aggregated signal port IQ data packet into an aggregated signal port discrete time domain baseband data signal, a time domain processing circuit configured to convert the aggregated signal port discrete time domain baseband data signal into an oversampled signal port discrete time domain data signal, and an integrated digital power amplifier and polyphase carrier generator configured to convert the oversampled signal port discrete time domain data signal into an analog modulated radio frequency signal.

[0051] When receiving an uplink (UL) signal, the receiver portions of transceivers 321 and 335 perform frequency downconversion and analog-to-digital conversion, and then perform further time-domain processing (e.g., sample rate conversion, quadrature error correction, filtering, frequency offset correction, cyclic prefix detection and removal, etc.), and then perform an FFT conversion to frequency-domain IQ data values for each of a plurality of subcarriers in the OFDM signal. Thus, in the receive operation mode, the transceiver IC generates the IQ data packets 322 and 338 shown in FIG. 3 from the received RF signal.

[0052] In one embodiment, the transceiver IC not only performs all of the iFFT calculations to generate the downlink (DL) transmit time domain signal port signals, but also processes the received uplink (UL) data samples via the FFT to generate the received frequency domain IQ data signals associated with each of the signal ports, including a digital signal processor (DSP). Regarding the embodiment related to the packet structure 302, the UL frequency domain IQ data from each signal port can first be concatenated into a single packet in the format of packet 302, which has H and V parts representing the UL received frequency domain IQ information locally generated in the transceiver IC. However, since the received IQ packets are carried along the transceiver IC subarray, the received UL frequency domain IQ packets received via the serial data link from another transceiver IC within the subarray can be combined with the locally generated received IQ data before being transmitted to the next transceiver IC. Specifically, when transceiver IC 350 receives a UL IQ packet on link 362 from transceiver IC 366, the UL IQ packet processor 358 combines the received IQ data with its locally generated UL IQ data. As will be more fully described herein, the combining can involve sample-by-sample addition (i.e., for each subcarrier, the I data samples are added and the Q samples are added), or the I data and Q data of one packet can have phase rotation added before combining. Next, the combined UL IQ data packet received on link 346 via the Serdes receiver 330 is further combined with the locally generated UL IQ data from transceivers 321 and 335 stored in the UL signal port IQ data combiner 336. In this way, in the embodiment related to the packet data format 302, the amount of received data transmitted along links 362, 346, 310 remains the same for each serial data link along the transceiver IC subarray.

[0053] In a further embodiment, the method comprises receiving a modulated RF signal at a plurality of signal ports of each transceiver IC within a sub-array of serially connected transceiver ICs, demodulating each modulated RF signal from each signal port using an FFT processor within each transceiver IC to generate one or more frequency domain digital data packets of sub-carrier IQ data associated with each signal port, forming a plurality of combined frequency domain digital data packets from the transceiver ICs using a set of serial data links between the transceiver ICs of the sub-array of serially connected transceiver ICs, and transmitting the plurality of combined frequency domain digital data packets from the sub-array of transceiver ICs to a beamformer processor.

[0054] In some embodiments, each transceiver IC may be configured to process signals from two signal ports, such as from a cross-polarized antenna element or a set of elements connected in parallel. Other embodiments may use a transceiver IC having four distinct signal ports. In each embodiment, a given signal port may receive a plurality of modulated carriers (each having a set of sub-carriers), and the demodulated frequency domain data may be packetized according to the component carriers on which it was received. Thus, one or more frequency domain digital data packets of sub-carrier IQ data associated with each signal port may be packetized with header information identifying the signal port (such as a signal port ID), the component carrier (such as a component carrier ID), and additional identification information (e.g., a sub-carrier subset ID for use in multi-layer beamforming). Each transceiver IC can participate in the formation of a plurality of combined frequency domain digital data packets by receiving frequency domain digital data packets of sub-carrier IQ data from an adjacent transceiver IC via a serial data link and combining it with its own locally generated frequency domain digital data packets of sub-carrier IQ data. Depending on the location of a given transceiver IC within a transceiver IC sub-array, some transceiver ICs may actually receive a partially formed combination of frequency domain digital data packets.

[0055] In an embodiment related to the packet structure 304 (note that no header is shown for clarity), six separate signal port packets may be provided to the transceiver IC subarray, from which six independent transmission signals may be generated. Generally, the ability of an AAU system to generate independent RF transmission signals from separate digital IQ data associated with each radiating element is referred to herein as full-dimensional beamforming. In this embodiment, a full-dimensional digitally beamformed signal is represented, and all six packets are received at the transceiver IC 312 via the link 308 in the receive Serdes 314 and provided to the split copy processor 318. The split copy processor 308 inspects the packet header and transfers the first set of two signal port packets (the H / V portions 324, 340 at the right end of the format 304) to the signal port split processor 320 for transmission processing of the IQ data 324 (for port 328) by the transceiver 321 and transmission processing of the IQ data 340 (for port 344) by the transceiver 335, and transfers the remaining four packets to the Serdes transmitter 332. The next transceiver IC 350 receives the four packets via the link 348 at its Serdes receiver, and the split copy processor 352 performs packet header analysis and transfers two signal port packets to its signal port split processor 354 within 350, and transfers the remaining two packets to the Serdes transmitter (TX#0 of the transceiver IC 350) for transmission to the transceiver IC 366 via the link 364. The signal port split processor 354 provides the H and V signal port IQ data to its transceiver for transmission on the signal ports 356, 360 respectively. The transceiver IC 366 receives the remaining two IQ data packets and processes them in a similar manner for transmission at ports 370, 378. Note that the amount of serial data decreases along the transceiver IC subarray for the DL IQ data packets. In this embodiment, the receive processing does not include any UL IQ packet data combining.Rather, the packets are simply retransmitted from each transceiver IC (using UL IQ packet processors 358 and 334 for concatenation / resending), such that all six received UL signal port IQ packets are conveyed to the beamformer processor via link 310 (the packets may be formatted with individual headers or conveyed as a concatenated payload with a single header). Note that the amount of data increases as the packets on link 362 from transceiver IC 366 are concatenated with the IQ data from transceiver IC 350 in UL IQ packet processor 358 for transmission via link 346. The amount of data increases again on link 310 as the UL IQ data 340 and 324 from UL signal port IQ data concatenator 336 are concatenated by UL IQ packet processor 334.

[0056] In some embodiments, fully dimensional beamforming packets, unique to each signal port, may be provided for smaller bandwidth signals such as 20 MHz data bandwidth. This may be desirable in some deployments where the AAU panel is configured with lower rate serial data connections in the transceiver IC subarray. Thus, even in a system with slower serial data interconnects, it is possible to support full control of the signal port signals (and corresponding radiating elements) by concatenating the separate IQ data of the interconnected transceiver ICs and extracting the relevant data sets at each IC. This enables support for MU-MIMO in the vertical plane with much higher accuracy and supports use cases associated with flying drones (either drones with data connectivity as users within the system or drones that block interference from high altitude jamming drones).

[0057] In a third embodiment of the antenna array system, a multi-layer beamforming signaling scheme can be used to provide data transmission and reception. In this embodiment, some transmit IQ data packets are processed commonly among multiple transceiver ICs to achieve a first level of beamforming resolution, and an additional set of IQ data packets is distributed to each of the transceiver IC subarrays, and each packet of a given additional set of transmit IQ packets is processed among fewer (or even just one) transceiver ICs within the transceiver IC subarray to obtain a second, higher resolution level of beamforming. Specifically, data format 306 provides a combination of beamforming resolutions, such that two signal port IQ data packets (e.g., the first two H and V portions of 306, 326, 342) are processed for transmission by each of transceiver ICs 312, 350, and 366 in a manner similar to the signal processing described above with respect to packet format 302. Since the same IQ data is converted and transmitted by multiple corresponding radiating elements within the subarray, these IQ data packets, referred to herein as "commonly processed" IQ data, result in a first layer of beamforming resolution, and the beam is formed as a result of the phase signal contributions from other subarrays (i.e., inter-subarray beamforming). However, further, an additional set of six signal port IQ data packets (three additional sets of H / V data of 306) is distributed across a given transceiver IC subarray in a manner similar to the signal processing described above with respect to packet format 304 for full digital beamforming data. These additional packets are specific to a given signal port and / or transceiver IC and provide a unique IQ data stream for transmission by each individual signal port within a given transceiver IC subarray, thereby providing transmission and reception at a second layer of beamforming resolution.Specifically, the beam is formed as a result of the phase signal contributions emitted from other transceiver ICs within a given subarray, as well as the phase signal contributions emitted from other transceiver ICs within other transceiver IC subarrays (i.e., second layer beamforming from both in-subarray beamforming and between-subarray beamforming).

[0058] Multilayer beamforming having packets of form 306, shown in FIG. 3 and further described below with respect to FIGS. 12, 13A, and 13B, utilizes the processing of two separate signal port IQ packets, such as IQ data 326 and IQ data 327 (and similarly 342, 343), that are shown to be combined for transmission on the same signal port. In one embodiment, the beamforming IQ packets separately can include IQ data points for different subcarriers within a set of subcarriers of a single component carrier. Thus, each transceiver IC can form its own unique combined set of IQ data points for its respective signal port prior to the iFFT processing. Specifically, transceiver IC 312 combines IQ data 326 and 327 for transmission on signal port 328 and combines IQ data 342 with IQ data 343 for transmission on signal port 344 via concatenation. Transceiver IC 350, the next transceiver IC within the transceiver IC subarray, combines IQ data 326 (the same as that processed by transceiver 321 of transceiver IC 312) with signal port IQ data 355 and combines IQ data 342 (the same commonly processed IQ data as that processed by transceiver 335 of transceiver IC 312) with signal port IQ data 359. A similar unique concatenated combination is shown for transceiver IC 366, where IQ signal port data packets 326 and 342 are combined with unique signal port IQ data 369, 377, respectively. Within the transceiver IC subarray, the commonly processed IQ packets 326 and 342 provide a first layer beamforming component contributed by the subarray, and an additional set of IQ packets distributed within the transceiver IC subarray provides a second layer beamforming component associated with that subarray.

[0059] In a further embodiment, the separate IQ packets may have overlapping subcarriers, in which case the transceiver IC processing includes forming a weighted average of the overlapping subcarriers prior to the iFFT processing. In such an embodiment, the beamformer processor can carry one or more weights for the transceiver IC used when forming combinations of IQ transmit data for the overlapping subcarriers.

[0060] Thus, in one embodiment, multi-layer transmit beamforming includes receiving, in a plurality of transceiver ICs of a transceiver IC subarray, a first-layer beamforming IQ packet and a plurality of second-layer beamforming packets via a serial data connection interconnecting the transceiver ICs; forming a multi-layer beamforming packet in each transceiver IC by combining the first-layer beamforming IQ packet with at least one of the second-layer beamforming packets of the plurality of second-layer beamforming packets; generating a time-domain signal from the multi-layer beamforming packet; and transmitting a multi-layer beamforming signal by transmitting, from the transceiver ICs of the transceiver IC subarray, respective amplified radio frequency time-domain signals via corresponding adjacent antenna element subarrays.

[0061] In some embodiments, the multi-layer beamforming packet is formed by concatenating IQ samples of separate subcarriers and then processing the packet using the same iFFT operation. In other embodiments, the multi-layer beamforming packet is formed by combining overlapping subcarriers using weights provided via management plane messages and then processed by the same iFFT operation.

[0062] In yet a further embodiment, the IQ packets that carry data used for second layer beamforming can be associated with subcarriers of a separate component carrier. In such an embodiment, additional higher resolution beamforming data can be processed independently using a separate iFFT before combining the two layer time domain signals of the beamforming signal. Thus, in one embodiment, multi-layer transmission beamforming includes receiving, in a plurality of transceiver ICs of a transceiver IC subarray, a first layer beamforming IQ packet and a plurality of second layer beamforming packets via a serial data connection interconnecting the transceiver ICs; in each transceiver IC, converting the first layer (commonly processed) beamforming IQ packet into a time domain signal and separately converting, via a separate iFFT, at least one of the plurality of second layer beamforming IQ packets into a time domain signal; combining the two time domain signals to form a signal port specific multi-layer beamforming time domain signal; and transmitting, from the transceiver ICs of the transceiver IC subarray, an amplified radio frequency time domain signal generated from each signal port specific multi-layer beamforming time domain signal via a corresponding adjacent antenna element subarray, thereby transmitting a multi-layer beamforming signal. The plurality of transceiver IC subarrays and their corresponding antenna element subarrays cooperate to generate a multi-layer beamforming signal.

[0063] In multi-layer beamforming that uses the distribution of multi-layer IQ packet data among each of a plurality of transceiver IC sub-arrays, one set of users can be served by aggregated IQ signal port packets that are copied and transferred for processing by each transceiver IC along a given transceiver IC sub-array, resulting in a first level of beamforming resolution (e.g., as determined by the total number of unique independent signal port IQ packet streams transmitted to the total number of corresponding transceiver IC sub-arrays for processing by each transceiver IC). However, further, by distributing additional signal port-specific IQ data packets along the transceiver IC sub-array for separate processing by each individual transceiver IC (i.e., IQ data that is not processed in common), a separate set of users can be served by higher-resolution beamforming.

[0064] Note that in many embodiments, the IQ packets that are processed in common for multi-layer beamforming signal processing are unique to a particular transceiver IC sub-array. However, in some scenarios, in order to achieve a desired beam radiation pattern (i.e., one with a lower degree of beamforming resolution), some IQ packets that are processed in common can be the same for two or more transceiver IC sub-arrays.

[0065] The received UL signal processing for multi-layer beamforming is also a hybrid of the UL received signal processing described above, where IQ data combination can be performed for the first pair of signal port IQ packets, and IQ data concatenation can be performed for an additional set of independent UL signal port IQ data packets. Thus, the first layer beamforming is performed by each transceiver IC involved in the formation of the UL combined frequency domain digital data packet by receiving the frequency domain digital data packet of sub-carrier IQ data from an adjacent transceiver IC via a serial data link and combining it with its own locally generated frequency domain digital data packet of sub-carrier IQ data. The second layer beamformer processing includes conveying the UL received IQ packets, without combining them, rather via concatenation (either sample-by-sample or packet-by-packet without changing the IQ samples), along a transceiver IC sub-array.

[0066] In some embodiments configured as an array of N×M transceiver ICs comprising a set of N transceiver IC sub-arrays, each having M serially connected transceiver ICs, multi-layer beamforming generates N unique beamforming IQ data packets (or a set of packets such as an IQ data set for each signal port (e.g., H and V) within the transceiver IC), each assigned to one of each of the N transceiver IC sub-arrays, to process a first set of aggregated beamforming frequency domain IQ user data according to a first layer of beamforming resolution, and to generate N different sets of M unique beamforming IQ data packets (or a set of packets for a set of signal ports of each transceiver IC), to process a second set of beamforming aggregated frequency domain IQ user data sets according to a second layer of beamforming resolution, where each of the N sets of M packets is assigned to one of each of the N transceiver IC sub-arrays. Each of the various packets is transmitted to the N transceiver IC sub-arrays via respective serial data links. Each transceiver of a given sub-array processes in common the packets associated with the first layer beamforming data, combined separately with only a portion of the second layer beamforming packets.

[0067] Referring to FIG. 16, an embodiment of two-layer beamforming is shown, where the panel uses sub-array level beamforming (such as shown in 1604) with three dual-polarization elements for each sub-array 1606 and is configured to process UL and DL data according to the first layer of beamforming that provides a beam (e.g., 1612) within the scanning range 1614. In the embodiment shown, the sub-array level beamformer generates beamforming IQ packets for the frequency content 1618 that is commonly processed within each respective sub-array, as described with respect to the IQ data 326 and 342. The same panel can be configured simultaneously (as shown in 1600) to provide another or second layer of beamforming with higher phase resolution using a unique beamforming IQ data set for generating a unique signal at each cross-polarization element 1602. In the embodiment of FIG. 16, the frequency content 1616 can be assigned to a high-resolution beamforming layer such as data 327, 343, 355, 359, 369, and 377. The frequency content of the frequency range 1616 and the frequency range 1618 can correspond to different sub-carriers within a single component carrier or can be separate component carriers, etc., as described herein.

[0068] In the beamforming of the second layer, it should be noted that individual beams (e.g., 1608) can be directed over a wider scanning range 1610 due to the higher phase resolution. In contrast, the scanning angle in subarray beamforming (where multiple signal ports transmit and receive signals processed according to a common IQ beamforming packet) has a limited scanning range due to the increased quantization error in the beamforming weights, as shown in FIG. 17. In particular, the scanning angles of two representative beams represented by the slashes labeled "desired BF weights" show two individual beams with different scanning angles. In full-dimensional beamforming, the IQ data for each signal port is formed using the desired weights with phases as shown, including, for example, points 1702, 1710, and 1706 for lower-angle scanning angles, and exemplary points 1712, 1720, and 1716 for steeper scanning angles (shown as dashed lines). However, in subarray beamforming, the beamforming IQ data processed in common can be generated using the average phase for the desired beam over the elements within a given subarray, as indicated by the exemplary phases 1704, 1710, 1708 for one beam, and phases 1714, 1718, 1720 for steeper beams. The corresponding beamforming weight phase errors are indicated by the lines labeled "BF weight error". Note that steeper scanning angles have higher beamformer weight errors. As a result, the beamforming of the second layer allows for larger scanning angles because there is no quantization error and subarray beamforming has a reduced scanning range. In the case of a two-element subarray, it should be noted that the beamforming weights used in forming individual beams can be the average value between two desired phase values, or otherwise a value between two desired weight phases. Finer phase control avoids what is sometimes called a "quantization lobe" that is generated because the weights applied are constrained to be the same for several adjacent elements within the subarray. The quantization lobe increases as the scanning angle increases.

[0069] In short, full-dimensional beamforming is performed with a higher level of precision in the beamformer weights, while subarray beamforming is performed with the average of the desired weights, introducing errors. Thus, the elements configured according to 1600 with full-dimensional control have a larger scanning range than the subarray beamforming configuration 1604 that is beamformed using the average bf weights for each given beam (such as UE-specific beams or spatial multiplexing layer beams).

[0070] The multi-layer beamforming described herein can be used to provide high-quality services to a set of users, such as users located in high-rise buildings within a cell sector, without sacrificing the coverage of other user devices located at ground level (e.g., by limiting the allocated data bandwidth). Similarly, the system enables support for communication with drones and other high-altitude devices in combination with user devices at ground level. The systems described herein are configured to provide these alternative beamforming transmissions between user devices within a single radio unit.

[0071] A multi-mode beamforming system can be configured to sequentially or dynamically allocate OFDM transmissions for each slot according to two or more levels of beamforming resolution. In particular, a first time transmission time interval (TTI) or even a first OFDM symbol time slot can be allocated to a user device that is beamformed according to a first layer of sub-array level beamforming such that the transmitted IQ data packets sent to each transceiver IC sub-array are commonly processed by each of the transceiver ICs within such each sub-array during transmission signal processing. Similarly, during signal reception, the processed IQ data packets of each transceiver IC are combined as they are conveyed from transceiver IC to transceiver IC along the serially connected transceiver ICs within each sub-array. In a second or subsequent time slot, the frequency resource blocks can be allocated to the user device for higher resolution beamforming, including full control beamforming IQ data according to a second layer of higher phase resolution beamforming, where individual transmitted IQ packets are separately formed for serial data transmission and are sent to each transceiver IC sub-array for individual processing by specifically addressed transceiver ICs within each transceiver IC sub-array.

[0072] In some embodiments, the transmit bandwidth associated with a full-control digital beamforming IQ data packet (i.e., the number of IQ sample pairs corresponding to the number of modulated subcarriers) may be less than the bandwidth utilized by a commonly processed IQ data packet, such as a comparison between the commonly processed packet data of 302 and the full digital beamforming packet data of 304. In some embodiments, the method of multi-layer beamforming includes receiving, in a transceiver IC subarray having a plurality of interconnected transceiver integrated circuits (ICs), a first-layer beamforming frequency domain IQ data packet and a plurality of second-layer beamforming frequency domain IQ data packets, wherein the transceiver ICs are interconnected via a plurality of serial data connections, and combining, in each transceiver IC of the transceiver IC subarray, beamforming frequency domain IQ data from the first-layer beamforming frequency domain IQ data packet with beamforming frequency domain IQ data from a selected one of the second-layer beamforming frequency domain IQ data packets among the plurality of second-layer beamforming frequency domain IQ data packets to form a multi-layer beamforming frequency domain IQ data set, using a digital signal processor (DSP) within the transceiver IC to generate a discrete-time domain signal from the multi-layer beamforming frequency domain IQ data set, generating a modulated radio frequency (RF) signal from the discrete-time domain signal, and transmitting a multi-layer beamforming signal by transmitting each modulated RF signal from the transceiver ICs of the transceiver IC subarray via corresponding adjacent antenna element subarrays. Transmitting the multi-layer beamforming signal may be performed by transmitting each modulated RF signal from the transceiver ICs of the plurality of transceiver IC subarrays via corresponding adjacent antenna element subarrays.

[0073] In some embodiments, the method includes receiving a first layer beamforming frequency domain IQ data packet and a plurality of second layer beamforming frequency domain IQ data packets in a transceiver integrated circuit (IC) subarray, and further, for common processing, transferring the first layer beamforming frequency domain IQ data packet from a first transceiver IC of the transceiver IC subarray to an additional transceiver IC of the transceiver IC subarray, and transferring only a subset of the second layer beamforming frequency domain IQ data packets among the plurality of second layer beamforming frequency domain IQ data packets from the first transceiver IC to the additional transceiver IC. The method may include that the subset of the second layer beamforming frequency domain IQ data packets is identified according to a packet header. Some methods combine beamforming frequency domain IQ data from the first layer beamforming frequency domain IQ data packet with beamforming frequency domain IQ data from a selected one of the second layer beamforming frequency domain IQ data packets by concatenating the beamforming frequency domain IQ data from the first layer beamforming frequency domain IQ data packet with the beamforming frequency domain IQ data from a selected one of the second layer beamforming frequency domain IQ data packets before frequency-time domain conversion. Combining the beamforming frequency domain IQ data from the first layer beamforming frequency domain IQ data packet with the beamforming frequency domain IQ data from a selected one of the second layer beamforming frequency domain IQ data packets is, in some examples, performed by forming a weighted sum of the beamforming frequency domain IQ data from the first layer beamforming frequency domain IQ data packet and the beamforming frequency domain IQ data from a selected one of the second layer beamforming frequency domain IQ data packets before frequency-time domain conversion. The weighted sum may be calculated according to the beamforming weights received from the beamformer.

[0074] In a further embodiment, combining the beamforming frequency domain IQ data from the first layer beamforming frequency domain IQ data packet with the beamforming frequency domain IQ data from one of the selected second layer beamforming frequency domain IQ data packets is, in the time domain, converting the beamforming frequency domain IQ data from the first layer beamforming frequency domain IQ data packet into a first layer beamforming time domain signal, converting the beamforming frequency domain IQ data from one of the selected second layer beamforming frequency domain IQ data packets into a second layer beamforming time domain signal, and adding the first layer beamforming time domain signal and the second layer beamforming time domain signal.

[0075] The first layer beamforming frequency domain IQ data packet and one of the selected second layer beamforming frequency domain IQ data packets may be associated with different component carriers. The method can include queuing the data packets according to the intended transceiver IC position such that the second layer beamforming frequency domain IQ data packet is received for processing by the last transceiver IC of the transceiver IC subarray before being received for processing by the first transceiver IC of the transceiver IC subarray.

[0076] Some exemplary embodiments of the apparatus include a beamformer processor configured to generate a first layer beamforming frequency domain IQ data packet and a plurality of second layer beamforming frequency domain IQ data packets, a transceiver integrated circuit (IC) subarray connected to the beamformer processor and having a plurality of interconnected transceiver ICs interconnected via a plurality of serial data connections, wherein each transceiver IC of the transceiver IC subarray is configured to form a multi-layer beamforming frequency domain IQ data set and generate a discrete time domain signal from the multi-layer beamforming frequency domain IQ data set, a radio frequency modulator configured to generate a modulated radio frequency (RF) signal from the discrete time domain signal, and an antenna element subarray connected to the transceiver IC subarray and configured to transmit a multi-layer beamforming signal by transmitting respective modulated RF signals from the transceiver ICs of the transceiver IC subarray. The transceiver IC subarray can include a first transceiver IC having a packet header processor configured to transfer a first layer beamforming frequency domain IQ data packet from the first transceiver IC to additional transceiver ICs of the transceiver IC subarray for common processing and configured to transfer only a subset of the second layer beamforming frequency domain IQ data packets from the first transceiver IC to the additional transceiver ICs. The packet header processor may be configured to identify a subset of the second layer beamforming frequency domain IQ data packets according to a packet header.

[0077] Before frequency-time domain conversion, the DSP may be configured to combine the beamforming frequency-domain IQ data from the first-layer beamforming frequency-domain IQ data packet with the beamforming frequency-domain IQ data from one selected from the second-layer beamforming frequency-domain IQ data packets by concatenating the beamforming frequency-domain IQ data from the first-layer beamforming frequency-domain IQ data packet with the beamforming frequency-domain IQ data from one selected from the second-layer beamforming frequency-domain IQ data packets. Before frequency-time domain conversion, the DSP may be configured to combine the beamforming frequency-domain IQ data from the first-layer beamforming frequency-domain IQ data packet with the beamforming frequency-domain IQ data from one selected from the second-layer beamforming frequency-domain IQ data packets by forming a weighted sum of the beamforming frequency-domain IQ data from the first-layer beamforming frequency-domain IQ data packet and the beamforming frequency-domain IQ data from one selected from the second-layer beamforming frequency-domain IQ data packets. The DSP may be configured to calculate the weighted sum according to the beamforming weights received from the beamformer processor.

[0078] In some embodiments, the DSP is configured to convert the beamforming frequency-domain IQ data from the first-layer beamforming frequency-domain IQ data packet into a first-layer beamforming time-domain signal, convert the beamforming frequency-domain IQ data from one selected from the second-layer beamforming frequency-domain IQ data packets into a second-layer beamforming time-domain signal, and add the first-layer beamforming time-domain signal and the second-layer beamforming time-domain signal.

[0079] The apparatus may include a packet header processor configured to identify a separate component carrier associated with one of a first layer beamforming frequency domain IQ data packet and a second layer beamforming frequency domain IQ data packet. The beamformer processor may be configured to transmit a second layer beamforming frequency domain IQ data packet for processing by a last transceiver IC in the transceiver IC subarray before transmitting the second layer beamforming frequency domain IQ data packet for processing by a first transceiver IC in the transceiver IC subarray. The apparatus may also include a plurality of transceiver IC subarrays configured to transmit a multi-layer beamforming signal and a corresponding plurality of adjacent antenna element subarrays.

[0080] Some embodiments may utilize a full-dimensional beamforming data stream within a serially-connected transceiver array. In these embodiments, each signal port has a unique signal for complete control over the beamforming phase. Thus, a unique packet addressed to each transceiver within the subarray (via a combination of one or more field IDs or a set of ID combinations) is transmitted to each transceiver IC subarray. Packets may be time-ordered to accommodate latency such that the IQ packet addressed to the transceiver at the end of the serially-linked chain of transceiver ICs is transmitted first and thus received at the end of the array. Thus, packets may be ordered in a round-robin fashion where a first packet is transmitted to each transceiver IC so that processing may begin at each IC and then additional packets are transmitted to each transceiver IC.

[0081] Each transceiver has a serial link and a packet header analyzer circuit for performing header checks, and each stream to each subarray includes a separate data packet addressed to an individual transceiver within a set of serially connected transceivers and having unique digital beamforming data. The packet header analyzer within each transceiver Serdes can make per-packet transfer decisions. In one configuration, the packet bandwidth is equally allocated between two signal paths of each transceiver IC, such as packets for two signal ports (H and V).

[0082] When receiving signals within serially linked transceiver ICs in a subarray, the serial data rate between the ICs is limited, and thus subarray beamforming may include combining received IQ data before sending it to and back from the beamformer. In some embodiments, coupling weights are provided to the transceivers within a given subarray, and thus the transceivers adjust the phase as part of the receive coupling. Electronic tilt is one such situation.

[0083] FIG. 4 is an alternative embodiment of a radio unit architecture having a hierarchical data distribution topology to each group of serially connected transceiver ICs from a DL / UL beamformer 400 (e.g., one such transceiver IC subarray is a set of transceiver ICs connected via serial links 418 and 420). In this embodiment, the beamformer 400 has a high-speed serial data connection (e.g., 402) to an intermediate Serdes MUX device 404 (as well as connections to 422, 424, 426), each of which then provides a separate serial data connection (e.g., a set of links 406). The separate serial connections from each Serdes MUX may utilize a lower data rate for connection to each subset of transceiver IC subarrays 421a, 421b, 421c, 421d. In the embodiment of FIG. 4, the subset of transceiver IC subarray 421a includes eight transceiver IC subarrays, each subarray having three transceiver ICs connected to corresponding antenna elements. Note that the remaining sets of transceiver IC subarrays 421b, 421c, 421d are shown in a simplified form (including connectivity to a simplified set of antenna element subarrays) for clarity.

[0084] The transceiver IC subarrays of FIG. 4 are also configured in a time-division duplex (TDD) configuration having SPDT (single-pole double-throw) switches 412. Received signals may be filtered via filter 410 and amplified by a low-noise amplifier (LNA) 408. Also shown are signal couplers, such as 414, 416, that provide a signal copy of the transmitted RF signal (typically at much lower power) to a calibration port 430 for monitoring or observing by transceiver 428.

[0085] FIG. 5 shows an embodiment of a synchronization and clock distribution circuit 500 for use with transceiver ICs distributed across an active antenna array assembly. More specifically, some embodiments include a method that includes receiving a clock signal and at least one synchronization pulse signal at each transceiver IC of a plurality of transceiver IC sub-arrays, each transceiver IC sub-array including a respective set of serially-connected transceiver ICs. The method further includes, at each transceiver IC, (i) synchronizing the transceiver IC with other transceiver ICs of the respective set of serially-connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal, (ii) generating a carrier frequency signal using a phase-locked loop (PLL) circuit that includes the DSM circuit, and (iii) using the generated carrier frequency signal to process frequency-domain in-phase and quadrature (IQ) data.

[0086] Furthermore, some embodiments include a plurality of transceiver IC sub-arrays, each transceiver IC sub-array including a respective set of serially-connected transceiver ICs, a beamformer processor coupled to the plurality of transceiver IC sub-arrays and configured to generate at least one synchronization pulse signal and provide the at least one synchronization pulse signal to each transceiver IC, and a plurality of clock buffer circuits coupled to the beamformer processor via a clock distribution circuit, the plurality of clock buffer circuits being configured to output a plurality of clock signals and provide each clock signal to each transceiver IC, each transceiver IC being configured to (i) receive each clock signal and the at least one synchronization pulse signal, (ii) synchronize the transceiver IC with other transceiver ICs of the respective set of serially-connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal, (ii) generate a carrier frequency signal using a phase-locked loop (PLL) circuit including the delta-sigma modulator (DSM) circuit, and (iv) use the generated carrier frequency signal to process frequency domain IQ data.

[0087] Referring again to FIG. 5, within the beamformer processor circuit 502, the data interface circuit 506 may be used to generate a clock signal from the clock and data recovery (CDR) circuit 508, which clock signal is then provided to the dual PLL clock circuit 512 that provides clock signals 522, 524 for use by the beamformer processor 502, and the beamformer processor may then generate further clock signals on line 526. The clock signal distribution to the transceiver IC (e.g., one such transceiver IC 540 is depicted in FIG. 5) via clock line 538 is provided by a clock buffer 536 that receives input from a clock distribution circuit 534 driven by PLL2 532, PLL1, 530 based on a selection from MUX528, in conjunction with the system reference clock. Thus, in some embodiments, the clock distribution circuit 534 is driven by the clock signal (on line 526) from the beamformer processor 502 and the system reference clock.

[0088] In some embodiments, the distributed clock signal is a high frequency signal within the frequency range of 50 MHz to 150 MHz. Further, in some embodiments, the clock buffer clock circuit 536 is configured to adjust the clock signal timing at the output of each clock buffer circuit such that each clock signal is received by each transceiver IC substantially simultaneously. For example, in an exemplary embodiment, the clock buffer circuit 536 is programmable and configurable to adjust the clock signal timing at each output such that the clock signal (specifically, the rising edge transition and / or falling edge transition of the clock signal) arrives at each transceiver IC with a low relative skew to account for the signal transmission latency associated with the clock signal path. In this regard, low skew means substantially simultaneous arrival with an arrival time distribution in the range of less than 1 or 2 nanoseconds of each other. In some embodiments, low skew refers to less than 333 picoseconds (1 / 3 nanosecond). In this regard, the clock buffer 536 may be adjusted according to a calibration procedure.

[0089] In some embodiments, in addition to receiving a substantially synchronized clock signal, the transceiver IC (e.g., transceiver IC 540) is also synchronized with respect to each other at the macro timing level by at least one additional synchronization pulse signal for one or more purposes. In particular, the transceiver ICs may be interconnected within a transceiver IC subarray via an asynchronous serial data bus and may also be directly or indirectly interconnected with the beamformer processor 502 as described herein and have one or more subsystems that can benefit from further synchronization. In some embodiments, as shown in FIG. 5, such a synchronization pulse signal (shown as a "SYNC" pulse signal) is generated by the beamformer processor 502 and provided to each transceiver IC for further synchronization.

[0090] In one aspect, each of the transceiver ICs physically distributed across the antenna array assembly independently processes a low-skew spread (e.g., high-frequency) clock signal and, in response, is configured to generate a carrier frequency signal for processing transmitted and received modulated RF signals. Accordingly, the voltage-controlled oscillator (VCO) of each transceiver IC used to generate the carrier phase for modulating transmitted signals and mixing / down-converting received RF signals is closely aligned across the transceiver IC subarray distributed across the antenna array assembly.

[0091] In some embodiments, the transceiver IC VCO used herein employs a phase-locked loop (PLL) circuit including a delta-sigma modulator (DSM) 544, a multi-modulus divider (MMD) 546, a phase / frequency detector (PFD) 548, a loop filter 550, a VCO 552, and a divider 554 for a VCO adjustment loop. The fractional divider within the VCO adjustment loop functions to adjust the frequency division coefficient (i.e., the division ratio) used by the MMD 546. The MMD 546 utilizes a sequence of divisor values obtained from the DSM 544.

[0092] In this regard, as described above, some embodiments described herein synchronize a transceiver IC with other transceiver ICs of each set of serially connected transceiver ICs (within each transceiver sub-array) by resetting a DSM circuit to a predetermined state according to (in particular) at least one received synchronization pulse signal, and generate a carrier frequency signal using a PLL circuit including the DSM circuit.

[0093] Furthermore, in one embodiment, to generate a carrier frequency signal using a PLL circuit (including a DSM circuit), each transceiver IC is configured to: (i) use a DSM circuit to set a division ratio of an MMD; and (ii) provide the divided frequency signal from the MMD to a PFD to compare with a clock signal and further adjust the division ratio of the MMD. In a further embodiment, the DSM circuit includes a plurality of accumulators, and each transceiver IC is further configured to set the plurality of accumulators of the DSM circuit according to at least one received synchronization pulse signal to reset the DSM circuit to a predetermined state according to the at least one received synchronization pulse signal.

[0094] Generally speaking, various embodiments described herein utilize a DSM circuit (such as DSM544) to increase the frequency resolution of the carrier frequency signal generated by each transceiver IC for processing transmitted and received modulated RF signals. In this regard, in some embodiments, the DSM circuit is configured to use a time-varying sequence representing a fractional input part in combination with a fixed integer input part to obtain a relatively high-resolution carrier frequency. In one example, by using a DSM circuit in a PLL circuit, the VCO frequency resolution can be made as fine as about 114 Hz. The operation of the DSM circuit will be described in more detail below.

[0095] As shown in FIG. 5, DSM544 can include a fractional input (FRAC IP) block 572, a DSM accumulator (DSM ACC) 574, a fractional output (FRAC OP) block 576, and an addition circuit 578. During operation, FRAC IP receives an input 570 that includes a digital fractional input value and generates a corresponding fractional input portion that is input to DSM ACC574. As further shown, DSM accumulator 574 and FRAC OP576 form a loop. Generally, in this loop, the fractional input portion passed to the DSM accumulator 574 at the current time is also referenced back from FRAC OP576 to the accumulator. Here, the current fractional output is subtracted from the current fractional input portion value stored in accumulator 574. Although not explicitly shown in FIG. 5, in an exemplary embodiment, DSM ACC574 includes a plurality of accumulators, and each accumulator can (i) receive a version stored prior to its cumulative output, (ii) subtract the current fractional output using feedback from FRAC OP576, and (iii) pass the result to a subsequent accumulator.

[0096] As a result of the operations described above, all fractional outputs generated by FRAC OP576 are provided to addition circuit 578. Next, addition circuit 578 sums (adds) the fractional output portion with the actual integer input portion 580 to generate a desired divisor value that is provided as an input to MMD546. In some embodiments, the output of DSM544 is in the form of a divisor control word (e.g., a set of data bits) that sets which divisor to use in MMD546. Due to the time-varying characteristics of the fractional input portion, the control word also changes over time. However, over a given operating interval, on average, the desired ratio can be achieved.

[0097] As described above, in one embodiment, the transceiver IC 540 is synchronized with other transceiver ICs of its respective transceiver IC sub-array by resetting the DSM circuit (such as DSM 544) to a predetermined state according to at least one received synchronization pulse signal. In this regard, as further shown in the example of FIG. 5, the transceiver 540 is configured to receive such a synchronization pulse signal (here, the "SYNC" pulse signal from the beamformer processor 502), and the synchronization pulse signal is provided to the DSM ACC 574 to set a plurality of accumulators of the DSM ACC 574 according to the synchronization pulse signal.

[0098] In some embodiments, the reset provided by the synchronization pulse signal is a one-time event, for example, executed during startup. Thereafter, transceiver IC synchronization can be automatically obtained due to the globally shared high-speed clock distributed to each transceiver IC (as described above).

[0099] During normal operation, the MMD 546 utilizes the sequence of division ratios obtained from the DSM 544. In this way, the sequence of divisors used to divide the VCO frequency from the VCO 552 (or the already divided signal supplied by a divider such as the divider 554) is the same across all of the transceiver ICs. Thus, in some embodiments, the MMD 546 is configured to utilize the sequence of division ratios provided by the DSM 544, and the sequence of divisors is synchronized across all of the transceiver ICs according to the synchronization pulse signal.

[0100] As further shown in FIG. 5, the divided frequency signal from MMD546 is provided to PFD548 for comparison to the high frequency distribution clock signal from clock buffer 536. PFD548 generates a phase error signal, which is then filtered by loop filter 550 having a transfer function H(z). The filtered phase error signal is then supplied to VCO552 to correct the phase error. Synchronization of the VCO phase error measurement circuit, such as the DSM544 divisor sequence, across the transceiver IC provides reduction of the jitter of the carrier frequency used for transmission and reception signal processing between transceiver ICs.

[0101] Further, as shown in FIG. 5, the output carrier frequency signal from divider 554 may be provided to digital delay line (DDL) 556. In some embodiments, DDL556 is configured to generate a carrier frequency signal having multiple phases at output 558. As an example, in one embodiment, the multiple phases can include at least four phases of 0 degrees, 45 degrees, 90 degrees, and 135 degrees, and the carrier frequency is in the range of 3.6 GHz to 4 GHz. As will be described in more detail below, the generated carrier phases (and, for example, their inversions) can be used by a polyphase digital power amplifier for RF modulation. More specifically, in some embodiments, a discrete time domain signal representing DL (downlink) frequency domain IQ data may be modulated onto the generated carrier frequency signal using a polyphase DPA, and the polyphase DPA uses a selected phase of the generated carrier frequency signal for RF modulation. The phase can be selected according to the discrete time domain signal.

[0102] In another aspect, the transmit and receive signal processing circuits within the transceiver IC can use a numerically controlled oscillator (NCO), such as NCO542 shown in FIG. 5. The NCO can be used to provide frequency shifting (conversion) via time domain complex multiplication as described herein with respect to FIGS. 13A, 13B.

[0103] The NCO can also utilize components that can benefit from synchronization by the SYNC pulse signal. In some embodiments, the NCO utilizes a phase accumulator that is incremented by a frequency control word (FCW) at each clock interval. If different NCOs within different transceiver ICs have different phase accumulator values, this can introduce a phase offset in the transmit and receive signal processing. Synchronization of the NCO phase accumulator circuits across the transceiver IC provides a reduction in the phase offset in the transmit and receive signal processing between the transceiver ICs.

[0104] Referring again to the example of FIG. 5, the NCO 542 includes an FCW register 562, a phase accumulator (PACC) 564, and a phase amplitude converter (PAC) 566. As shown in FIG. 5, the FCW register 562 receives an FCW input 560 (from, e.g., a DSP, etc.) and, in response, can generate an FCW to be loaded into the PACC 564 at each clock interval. Generally, the FCW is a series of data bits that represents a phase increment value. In some embodiments, the FCW register 562 is configured to use the FCW to generate a corresponding phase increment (e.g., via a look-up table, etc.). In some embodiments, the PACC 564 is configured to add the corresponding phase increment to its internal memory register. In this way, the phase value accumulated by the PACC 564 through the stepped phase increments starts at 0 degrees, ramps up to 360 degrees, wraps around back to 0 degrees again, and is the binary representation of the angle at which everything starts again in the next cycle (clock interval). Next, the output phase value of the PACC 564 is passed to the PAC 566 to be converted into a complex sine wave output by the NCO 542. The PAC 566 is configured to convert the accumulated phase value from the PACC 564 into a dual output of a sine function and a cosine function of the angle corresponding to that phase value, representing the real and imaginary components that form the complex sine wave at the NCO output 568.

[0105] Furthermore, in some embodiments, NCO 542 receives a synchronization pulse signal and resets NCO 542 according to the synchronization pulse signal. This can synchronize the NCO phase accumulator circuit across the transceiver IC as described above. More specifically, in some embodiments, the phase accumulator of the NCO is reset according to the received synchronization pulse signal. As shown in the example of FIG. 5, the SYNC pulse signal is provided to PACC 564 of NCO 542 to reset PACC 564. Due to the benefit of such phase accumulation reset in each transceiver IC, all of the transceiver ICs distributed across the active antenna array assembly can start phase value accumulation at 0 degrees.

[0106] (As described in connection with the operation of the DSM circuit) Note that some embodiments provide the synchronization pulse signal reset as a one-time event that occurs, for example, at a certain point during startup. Thereafter, transceiver IC synchronization can be automatically obtained due to the globally shared high-speed clock distributed to each transceiver IC (as described above).

[0107] Furthermore, the synchronous NCO 542 can be used to provide a frequency shift (conversion) via time-domain complex multiplication, as described in more detail herein in connection with FIGS. 13A and 13B. For example, in the transmit-side signal processing (FIG. 13A) within transceiver 540, NCO 542 can be configured to multiply a time-domain signal by a complex sine function to perform a frequency shift of a baseband signal to a desired frequency range, such as a separate frequency range that does not overlap with other component carriers. On the receive signal processing side (FIG. 13B), the complex multiplication via NCO 542 can shift the signal received by transceiver IC 540 to a desired baseband signal.

[0108] In an additional embodiment, the synchronous NCO 542 can be used to operate on frequency domain data to provide an incremental phase rotation to sub-carrier specific frequency domain IQ data for electronic beam tilt, as described herein. Of course, multiple instances of the NCO 542 may be utilized for various signal processing functions as described herein.

[0109] Clock distribution is configured according to signal lines routed across the panel 102, as shown in various embodiments shown in FIG. 6, to provide clock signals to the transceiver IC sub-arrays to reduce clock skew. As described above, in some embodiments, multiple clock buffer circuits (e.g., 536) may be configured to adjust the clock signal timing at the output of each clock buffer circuit such that each clock signal is received substantially simultaneously by each transceiver IC. In some further embodiments, multiple transceiver IC sub-arrays, beamformer processors (e.g., 502), and multiple clock buffer circuits are all physically located in the same location within the antenna array assembly, and each clock buffer circuit is physically distributed across the antenna array assembly at a physical location corresponding to the physical location of one or more transceiver IC sub-arrays.

[0110] For illustration purposes, in one embodiment, clock signal distribution has a tree-like structure that symmetrically provides clock signals to each transceiver IC subarray, such as subarray 600 (which may be one or more transceiver IC subarrays). Specifically, in the illustrated embodiment, a given branch clock signal from clock buffer 610 is carried on clock signal conductor 606, which is split to provide clocking signals on lines 602, 608, which drive a further set of clock buffers (e.g., buffer 604 driven by line 602), and then provided to transceiver IC subarray(s), e.g., 600. In one embodiment, four clock buffers at the level of 610 may be provided by clock distribution circuit 534. Further, each clock buffer 536 is physically distributed across the antenna array assembly and serves transceiver IC subarrays that are likewise physically distributed across the antenna array assembly. In the illustrated embodiment, each clock buffer can provide eight distinct clock outputs to eight distinct transceiver ICs. In the embodiment of FIG. 6, one clock buffer circuit is shown as clock buffers 603, 604, which supply clock signals to four transceiver ICs within block 600 and four transceiver ICs below it, as shown.

[0111] FIG. 7 is a block diagram of an ORAN (Open Radio Access Network)-based system 700 including a distributed unit connected to a radio unit via a front-haul data interface and a hierarchical beamformer architecture within the radio unit, according to some embodiments. Generally, in an ORAN architecture, the base station functionality (e.g., the functionality of a 5G NR Node B (gNB)) may be split between a central unit (CU), one or more distributed units (DUs) connected to the CU via a mid-haul interface, and one or more radio units (RUs) connected to the DUs via a front-haul interface. For example, FIG. 7 shows, in particular, a DU (distributed unit) 702 having a baseband transmission unit 706, a precoding / beamforming combined weight calculation unit 710 (which receives a scheduler input 708), a channel estimation unit 714, and a baseband reception unit 716. The DU 702 includes an ORAN interface 712 for connecting to a radio unit (RU) 704 via a front-haul data interface that carries control information (C plane (control plane) 718), management information (M plane (management plane) 720), and user data (U plane (user plane) 722). Typically, an ORAN RU such as the RU 704 can act as a front-haul gateway (e.g., implemented by an FPGA) that performs various baseband processes associated with the physical (PHY) layer and RF front-end functions for RF signal transmission and reception via the air interface.

[0112] Also shown is a hierarchical beamformer architecture 722 within the wireless unit 704. The hierarchical beamformer 722 includes a main (primary) beamformer processor 724 (or simply "main (primary) beamformer 724"), and a plurality of distributed secondary beamformer processors such as BF#1 (728), BF#2 (734), BF#3 (736), and BF#4 (738) (or simply "distributed secondary (or layer 2) beamformers") connected by serial data links (e.g., link 726 from the main beamformer 724 to BF#1). In the exemplary embodiments described below, the main beamformer processor 722 includes a primary beamformer processor, and each of the distributed secondary beamformer processors 728, 734, 736, and 738 includes a corresponding distributed secondary beamformer processor connected to the primary beamformer processor, and all are configured for downlink (transmission) communication or uplink (reception) communication, or both. Thus, in some additional embodiments, in the hierarchical beamformer architecture 722, the main beamformer processor 724 can include a primary reception beamformer processor, and each of the distributed secondary beamformer processors 728, 734, 736, and 738 can also include a distributed secondary reception beamformer processor. Thus, each distributed secondary beamformer processor (e.g., 728, 734, 736, and 738) can perform both transmission beamforming operations and reception beamforming operations.

[0113] In some embodiments of the hierarchical beamformer architecture 722, the main beamformer 724 is configured to compute, for example, a complete transmit beamforming matrix (as more fully described with respect to FIGS. 8-10) and distribute portions of the transmit beamforming matrix to second layer beamformers (e.g., BF#1-4). Further, the main beamformer 724 also transmits a layer of user data in the form of frequency domain subcarrier IQ data (frequency domain subcarrier IQ user data layer) to each of the second layer beamformers 728, 734, 736, and 738. In general, the user data layer refers, herein, to a set of IQ subcarrier specific data points (values) representing actual modulation symbols. In some embodiments, the precoding / beamforming combined weight calculation unit 710 located within the DU 702 may be configured to determine beamforming weights and allocate them to the RU 702. Each second layer beamformer receives its respective transmit beamforming submatrix from the main beamformer 724 and a plurality of layers of the frequency domain subcarrier IQ user data layer (or, in some places, abbreviated as the "user data layer"), and then, by using its respective transmit beamforming submatrix and the plurality of frequency domain subcarrier IQ user data layers, forms an aggregated IQ data packet specific to each of the plurality of signal ports for the transceiver IC (or, for example, in some embodiments, a set of transceiver IC subarrays) that they serve.

[0114] In some embodiments, each transmission beamforming submatrix includes transmission beamforming coupling weights associated with antenna elements within respective regions of the antenna array (panel). Further, the distributed secondary transmission beamformer processors (e.g., secondary (layer 2) beamformers 728, 734, 736, and 738 as in this embodiment) are physically distributed such that each distributed secondary transmission beamformer processor is positioned within or adjacent to a respective region of the antenna array associated with one of the plurality of transmission beamforming submatrices. Here, main beamformer 724 may transmit a plurality of frequency domain subcarrier IQ user data layers to each of the plurality of distributed secondary transmission beamformer processors, and each distributed secondary transmission beamformer processor may be configured to receive the same frequency domain subcarrier IQ user data layer. Note that in the frequency domain, the beamforming (coupling) weights (or simply "beamforming weights") are complex values each having a real part and an imaginary part for control of the I and Q components.

[0115] As will be described in more detail, each distributed secondary (layer 2) transmission beamformer processor (e.g., BF#1-4 (728, 734, 736, and 738)) may then apply different respective transmission beamforming coupling weights (contained in each received beamforming submatrix) to their frequency domain subcarrier IQ user data layers to form respective pluralities of beamforming frequency domain IQ data packets. Further, each of the pluralities of beamforming frequency domain IQ data packets may then be distributed by the secondary transmission beamformer processor to a corresponding set of transceiver ICs or transceiver IC subarrays disposed within respective regions of the antenna array associated with that distributed secondary transmission beamformer processor. In this regard, the corresponding set of transceiver ICs or transceiver IC subarrays may be coupled to the secondary transmission beamformer processor via, for example, a serial data connection as described in various embodiments of this specification.

[0116] More specifically, some embodiments disclosed herein include an apparatus comprising: (i) a primary transmit beamformer processor configured to partition a transmit beamforming matrix of beamforming combining weights into a plurality of transmit beamforming submatrices, each transmit beamforming submatrix including transmit beamforming combining weights associated with antenna elements within respective regions of an antenna array; and (ii) a plurality of distributed secondary transmit beamformer processors connected to the primary transmit beamformer processor. In some embodiments, the plurality of distributed secondary transmit beamformer processors are physically distributed such that each distributed secondary transmit beamformer processor is disposed within or adjacent to a respective region of the antenna array associated with one of the plurality of transmit beamforming submatrices, which may be desirable to enable shorter serial data links. In this apparatus, each distributed secondary transmit beamformer processor is configured to: (i) receive from the primary transmit beamforming processor a respective transmit beamforming submatrix and a plurality of frequency domain subcarrier IQ user data layers; and (ii) use the respective transmit beamforming submatrix and the plurality of frequency domain subcarrier IQ user data layers to form respective plurality of beamforming frequency domain IQ data packets. Further, the apparatus includes a set of a plurality of transceiver ICs or transceiver integrated circuit (IC) subarrays connected to the plurality of distributed secondary transmit beamformer processors. In this regard, each set of transceiver ICs or set of transceiver IC subarrays is connected to a corresponding one of the plurality of distributed secondary transmit beamformer processors and is disposed within a respective region of the antenna array associated with the corresponding distributed secondary transmit beamformer processor.Furthermore, each set of transceiver IC sub-arrays is configured to receive respective plural beamforming frequency domain IQ data packets from a corresponding distributed secondary transmission beamformer processor, and each transceiver IC sub-array within a set of transceiver IC sub-arrays is configured to receive a given portion of the respective plural beamforming frequency domain IQ data packets.

[0117] Furthermore, in some embodiments, in a primary transmission beamformer processor, the transmission beamforming matrix of beamforming combining weights is partitioned into a plurality of transmission beamforming submatrices, each transmission beamforming submatrix including transmission beamforming combining weights associated with antenna elements within respective regions of an antenna array, and in a plurality of distributed secondary transmission beamformer processors, the plurality of transmission beamforming submatrices or beamformer weight index values, and a plurality of frequency domain subcarrier IQ user data layers are received from the primary transmission beamformer processor, the plurality of distributed secondary transmission beamformer processors being physically distributed such that each distributed secondary transmission beamformer processor is disposed within or adjacent to respective regions of an antenna array associated with respective ones of the plurality of transmission beamforming submatrices, each distributed secondary transmission beamformer processor receiving a respective transmission beamforming submatrix and the plurality of frequency domain subcarrier IQ user data layers, and each distributed secondary transmission beamformer processor using the respective transmission beamforming submatrix and the plurality of frequency domain subcarrier IQ user data layers to form respective plurality of beamforming frequency domain IQ data packets, and each distributed secondary transmission beamformer processor providing the respective plurality of beamforming frequency domain IQ data packets to a corresponding one of a plurality of sets of transceiver integrated circuit (IC) subarrays, (i) the corresponding set of transceiver IC subarrays being disposed within respective regions of an antenna array associated with the distributed secondary transmission beamformer processor, and (ii) each transceiver IC subarray within the corresponding set of transceiver IC subarrays receiving a given portion of the respective plurality of beamforming frequency domain IQ data packets from the distributed secondary transmission beamformer processor, the method including the above.

[0118] Referring back to FIG. 7, in the embodiment shown in FIG. 7, RU704 is shown as having a beamformer connection to transceiver IC element 730, where the transceiver IC element may be an individual transceiver IC having two, four, or more signal ports for driving antenna element 732, or may be a transceiver IC subarray of serially connected transceiver ICs according to various embodiments described herein. More specifically, as described above, at least two serially connected transceiver ICs may be physically disposed within a transceiver IC subarray (see, e.g., FIG. 2 and its description). Thus, in some embodiments, each transceiver IC element is a set of IC subarrays including two or more transceiver IC subarrays. Further, in some embodiments, each of secondary beamformers 728, 734, 736, and 738 may be implemented by a Serdes MUX device of FIG. 4 (e.g., 404), and each Serdes MUX device may be further configured to function as a partial beamformer processor of a hierarchical beamformer device, such as hierarchical beamformer architecture 722 shown in FIG. 7.

[0119] In an exemplary embodiment, a primary transmit beamformer processor (e.g., main beamformer 724) allocates transmit (downlink) beamforming combining weights (e.g., in combination with precoder combining weights as needed) to form a complete beamforming matrix (more fully described with respect to FIG. 8), partitions the complete beamforming matrix into partial matrices, and then distributes portions of the complete beamforming matrix to respective secondary transmit beamformer processors (e.g., secondary beamformers 728, 734, 736, and 738). Each portion of the complete beamforming matrix constitutes a respective transmit beamforming partial matrix that is distributed to each corresponding secondary (transmit) beamformer processor. The actual weights may be conveyed to the secondary beamformers, or a set of beam indices may be used to identify beamforming weights previously stored within the secondary beamformers. More specifically, in some embodiments, a plurality of transceiver IC subarrays associated with antenna elements on an antenna panel may be partitioned into a plurality of sets of transceiver IC subarrays according to their physical locations on the panel (e.g., antenna panel 102), and each set of transceiver IC subarrays within a given partition is served by and interconnected with a corresponding secondary beamformer processor, and the secondary beamformer processors (e.g., secondary beamformers 728, 734, 736, and 738) may be distributed across the panel adjacent to or within the partitions. Each distributed secondary beamformer processor also receives a frequency domain subcarrier IQ user data layer via a respective serial data link 726 and applies each allocated beamforming weight within a given transmit beamforming partial matrix to the frequency domain subcarrier IQ user data layer to calculate complete beamforming IQ data points for distribution to respective transceiver ICs or sets of transceiver IC subarrays.

[0120] More specifically, in some embodiments, each distributed secondary beamformer processor may be configured to calculate a plurality of sets of beamforming frequency domain IQ data points by applying the transmit beamforming combined weights of each transmit beamforming submatrix to the frequency domain subcarrier IQ user data layer to form respective beamforming frequency domain IQ data packets, such as the signal port specific aggregated IQ data packets described in connection with various embodiments herein. In this regard, in some embodiments, each distributed secondary transmit beamformer processor may be configured to packetize each set of beamforming frequency domain IQ data points to form a corresponding set of beamforming frequency domain IQ data packets. Further, each distributed secondary beamformer processor may be configured to distribute the corresponding set of beamforming frequency domain IQ data packets to a corresponding set of transceiver ICs or transceiver IC subarrays connected to the distributed secondary transmit beamformer processor. Due to the benefits of the distributed architecture of the beamformer processor of this embodiment, the computational processing load normally performed by the RU as the front hall gateway can be reduced by distributing the computing functions among the primary beamformer and a plurality of secondary beamformers each designated to serve a respective set of transceiver ICs / IC subarrays.

[0121] Next, each transceiver IC subarray within a corresponding set of transceiver IC subarrays can be configured to receive a respective subset of a corresponding set of beamforming frequency domain IQ data packets. In this regard, each beamforming frequency domain IQ data packet within a corresponding set of beamforming frequency domain IQ data packets can have a respective header indicating a destination signal port so as to direct individual data packets to the transceiver IC subarray designated to receive the data packet. Within each transceiver IC subarray, individual transceiver ICs can be configured as described in various embodiments herein, such as a serial data connection to a beamformer processor and / or a serial digital data port providing communication with other transceiver ICs, appropriate data and signal processing circuitry, and the like. In some embodiments, each respective subset of a corresponding set of beamforming frequency domain IQ data packets includes a single frequency domain IQ data packet (such as any of data packets 302, 304, and 306 described in connection with FIG. 3) provided to each respective transceiver IC subarray within a corresponding set of transceiver IC subarrays. Generally, the above-described operation of formulating beamforming packets for distribution to transceiver IC subarrays may be performed over a given period to generate a stream of downlink data packets, for example, where each data packet within the stream represents a symbol time within a slot (such as in an LTE communication system).

[0122] As noted above, it should be noted that the beamformer processor within the wireless unit can be configured to transmit and receive IQ data packets in either the time domain or the frequency domain. Thus, in some alternative embodiments, each distributed secondary transmit beamformer processor (e.g., each of the secondary beamformers 728, 734, 736, and 738) may be configured to (i) formulate each set of beamforming frequency domain IQ data packets (by applying the transmit beamforming combining weights within its respective transmit beamforming submatrix to the frequency domain subcarrier IQ user data layer) as described above, and (ii) further convert those beamforming frequency domain IQ data packets into a corresponding set of data packets that instead contain (beamformed) time domain IQ data. The set of beamforming time domain IQ data packets may then be distributed, as described above, among the transceiver IC / IC subarrays served by the distributed secondary transmit beamformer processors (e.g., each subset of the time domain IQ data packets (e.g., one data packet) is transmitted to each transceiver IC subarray within the set of transceiver IC subarrays associated with the distributed secondary transmit beamformer processor). In this regard, each distributed secondary transmit beamformer processor may be configured with, for example, an appropriate iFFT process (e.g., a digital signal processor (DSP) configured with appropriate programming instructions to execute an algorithm for IFFT operations) to perform the calculations involved in the conversion of frequency domain IQ data to time domain IQ data.

[0123] To perform various other functions described above, embodiments of each distributed secondary transmit beamformer processor (and optionally a distributed secondary receive beamformer processor) (e.g., each secondary beamformer 728, 734, 736, and 738) may include a digital signal processor circuit that executes software instructions to perform matrix multiplication operations (described in more detail with reference to FIG. 8), or may take the form of data registers interconnected with a hardware multiplier circuit that performs matrix operations. The hardware may include a hardware processor, a field programmable gate array (FPGA), dedicated digital logic, or combinations thereof. Further, in some embodiments, each distributed secondary transmit beamformer processor is configured to (i) packetize each set of beamforming frequency domain IQ data points within a plurality of sets of beamforming frequency domain IQ data points calculated by a given distributed secondary beamformer processor to form a corresponding set of beamforming frequency domain IQ data packets, and (ii) distribute the set of beamforming frequency domain IQ data packets to a corresponding set of transceiver IC subarrays connected to the distributed secondary beamformer processor (as described above) by a packet processor (e.g., a dedicated DSP circuit, etc.). In this regard, the distributed secondary transmit beamformer processor (and optionally the distributed secondary receive beamformer processor) can include a serial data interface circuit for communicating with each transceiver IC subarray within a corresponding set of transceiver IC subarrays. As described in more detail above, communication between the beamformer processor and the transceiver IC can be carried over a serial data connection.

[0124] In some embodiments, the packet processor may be further configured to obtain data layer information including component carrier identification information from the primary transmission beamformer processor. For example, as described in connection with FIG. 3, a data packet carrying subcarrier-specific IQ data for a transceiver IC signal port may include a header (not shown for clarity) that identifies various aspects of the type of data included in the packet, as well as packet identification data such as one or more of a frequency band ID, a component carrier ID, a signal port ID, and / or a transceiver ID.

[0125] Note that in some embodiments, the plurality of frequency domain subcarrier IQ user data layers transmitted to each distributed secondary beamformer 728, 734, 736, and 738 via the serial data link 726 may be compressed using a so-called "modulation compression" technique defined for use, for example, in ORAN. Modulation compression is a lossless compression technique used for modulated data transmitted via the user plane (e.g., U-plane 722), and more specifically, it is applied to those symbols before the DL (downlink) user plane modulated data symbols are transmitted via the fronthaul interface. Without modulation compression, both the I samples and the Q samples are generally represented by a fixed given number of bits (referred to as the "bit width") (e.g., 10, 12, 14, 16 or more bits for each I value and Q value). Modulation compression makes it possible to reduce the bit width according to the maximum modulation order used via the DL air interface. That is, in this technique, the I and Q constellation points / samples can be represented by several (data) bits corresponding to the maximum modulation order used. For example, in the case of 256QAM, the number of bits for both the I sample and the Q sample for each subcarrier can be reduced to 8-bit data (the I sample and the Q sample are each encoded with 4 bits), where the number of 8 bits corresponds to a modulation order of M = 8.

[0126] Thus, in some embodiments, DU702 may be configured using appropriate signal processing to perform modulation compression such that the amount of data included in each of the plurality of frequency domain sub-carrier IQ user data layers transmitted from the primary beamformer 724 (via the U plane 722) for distribution to each secondary beamformer (e.g., BF#1 - 4) can be substantially reduced. Further, as described above (and as will be described in more detail below), each distributed secondary beamformer may be configured to apply each respective partial transmit beamforming matrix (or transmit beamforming sub-matrix) associated with that particular beamformer to the user data layer by performing complex matrix multiplication.

[0127] When beamforming weights are applied by performing complex multiplication (described in more detail in connection with FIGS. 8 - 10), the amount of data transmitted to a set of transceiver ICs or transceiver IC sub-arrays served by a given secondary beamformer increases as a result of, for example, multiplication and addition operations normally associated with performing matrix multiplication. In one example, beamforming frequency domain IQ data points may be represented by 24 bits or 32 bits.

[0128] Furthermore, some alternative embodiments disclosed herein involve, for example, pre-storing a predetermined set of beamforming weights in each distributed secondary transmission beamformer processor (e.g., BF#1-4 (728, 734, 736, and 738)) as part of the system setup / initialization phase. Such weights can then be stored in the distributed secondary transmission beamformer processor for relatively long-term use. In some embodiments, a predetermined set of beamforming weights may be conveyed to the distributed secondary transmission beamformer processor via, for example, M-plane (e.g., M-plane 720) messages used in the ORAN to manage radio unit functions. In some other embodiments, it may be possible to communicate the beamforming weights from DU702 to RU704 via the C-plane (e.g., C-plane 718) that typically conveys data used to control user data scheduling as well as data used to control beamforming weight selection. Thus, each predetermined set of beamforming weights for a given distributed secondary transmission beamformer processor can be conveyed to the given distributed secondary transmission beamformer processor prior to reception of the user data layer for the UE served by the given distributed secondary transmission beamformer processor. Further, a predetermined set of beamforming weights for a corresponding distributed secondary transmission beamformer processor may be communicated from DU702 via the primary transmission beamformer processor, or may be directly transmitted from DU702 to each distributed secondary transmission beamformer processor using any suitable connection mechanism (e.g., DU702 may have a direct communication link to each distributed secondary transmission beamformer processor).

[0129] In some embodiments, a given set of beamforming weights may be stored in a given distributed secondary transmission beamformer processor, for example, in the form of a look-up table. Each distributed secondary transmission beamformer processor can load a given set of beamforming weights into such a table for future use. In some embodiments, the beamforming weights stored in the look-up table may be indexed using a beamforming index, and then the beamforming index may be associated with the incoming frequency domain sub-carrier IQ user data layer to indicate which beamforming weights the distributed secondary transmission beamformer processor should apply to each frequency domain sub-carrier IQ user data layer. For example, a given beamforming index or a set of given beamforming indices may be included in a message transmitted from DU702 and RU704 via the fronthaul interface to indicate which beamforming weights each distributed secondary transmission processor should apply to the incoming frequency domain sub-carrier IQ user data layer. In this regard, in some embodiments, each beamforming index may comprise a beam index corresponding to a given beam identified by a beam ID / beam index (e.g., beam ID / beam IDx as defined for a 5G / ORAN network).

[0130] Note that each of the plurality of frequency domain subcarrier IQ user data layers received by each secondary transmission beamformer processor may include a plurality of physical resource blocks (PRBs, or simply RBs) for one or more users. Also, as described above, recall that the plurality of frequency domain subcarrier IQ user data layers received by each distributed secondary transmission beamformer processor are the same. Each PRB includes frequency domain IQ data of 12 subcarriers during a given time period such as 7 symbol times (or 84 resource elements (REs) each representing one OFDM symbol). In some embodiments, each frequency domain subcarrier IQ user data layer may be provided to each distributed secondary transmission beamformer processor to form beamforming data as a whole (i.e., as a complete frequency domain subcarrier IQ user data layer). In other embodiments, each frequency domain subcarrier IQ user data layer may be provided to each distributed secondary transmission beamformer processor in a finer-grained manner, such as one PRB at a time. In this regard, a single beamforming index is used within a single PRB. However, each PRB may be assigned a different beamforming index depending on whether the PRB is for the same user device (e.g., UE) or for a different user device (e.g., UE).

[0131] In this regard, the beamforming index (e.g., beam index (beam ID)) transmitted to each distributed secondary transmission beamformer processor in relation to the frequency domain sub-carrier IQ user data layer may be specified in different ways. In some embodiments, a full set of beamforming indices may be specified for use across all PRBs for each layer (e.g., the beamforming index may be transmitted as a type of "map" for mapping indices across all PRBs in each layer). In other embodiments, the frequency domain sub-carrier IQ user data layer may be conveyed to each distributed secondary transmission beamformer processor in a finer-grained manner, such as one PRB at a time. In such a case, a data packet or data frame carrying a single PRB may specify a beamforming index for that particular PRB only. Thus, for example, if a given beamforming weight is stored in each distributed secondary transmission processor for relatively long-term use, when a given frequency domain IQ data packet (carrying IQ data for a single PRB or a full user data layer) is received by the distributed secondary transmission processor, it includes a beamforming index (for that one PRB frequency domain IQ data packet (e.g., within the packet header)), or a full set of beamforming indices (for the full data layer frequency domain IQ data packet). Next, the distributed secondary transmission beamformer processor uses those one or more beamforming indices to look up the corresponding beamforming weights and uses those weights to perform complex multiplication (as described above) to form the beamforming IQ data.

[0132] As described above, a given beamforming index or a set of given beamforming indexes can be included in a message transmitted from DU702 to RU704 via the fronthaul interface, indicating which beamforming weights should be applied to the incoming frequency domain subcarrier IQ user data layer for each distributed secondary transmit beamformer processor. As an example, in ORAN, C-plane messages (such as data frame formats) can each have multiple sections, each containing fields for "sectionId", "beamId", "startPrbc", and "numPrbc" (thus, each section can specify a given PRB and the beam ID associated with that PRB). Similarly, the U-plane data frame can also have multiple sections with multiple fields that identify the PRBs carrying IQ data and the corresponding "sectionId". In some embodiments, when the distributed secondary transmit beamformer processor in RU704 acquires a U-plane data frame, it can be configured to use the "sectionId" field in the U-plane data frame to find the corresponding section information in the C-plane data frame. The distributed secondary transmit beamformer processor can further be configured to read the beam ID (beamforming index) from the "beamId" field, retrieve the beamforming weights indexed by that value of "beamId", and apply those weights to the U-plane PRB data.

[0133] In additional embodiments, as described above, the main (primary) beamformer processor 724 may also include a primary receive beamformer processor, and each of the distributed secondary beamformer processors (distributed secondary beamformers) 728, 734, 736, and 738 may also include a distributed secondary receive beamformer processor.

[0134] In this regard, for uplink signal reception, in some embodiments, the second layer beamformers 728, 734, 736, and 738 may each have a respective receive beamforming submatrix that includes receive beamforming coupling weights associated with antenna elements within respective regions of an antenna array (panel) for each receive user data layer. Further, the distributed secondary receive beamformer processors (e.g., the secondary beamformers 728, 734, 736, and 738 as in this embodiment) are physically distributed such that each distributed secondary receive beamformer processor is disposed within or adjacent to each respective region of the antenna array associated with its respective receive beamforming submatrix. As will be described in more detail, each distributed secondary (second layer) receive beamformer processor can receive packet data that carries respective sets of frequency domain IQ data points from a corresponding set of transceiver IC subarrays that it serves. Each distributed secondary receive beamformer processor can apply different respective receive beamforming coupling weights (contained in its respective beamforming submatrix) to that set of frequency domain IQ data points to compute respective sets of received partial beamforming frequency domain IQ data points, and then can transmit the respective sets of received partial beamforming frequency domain IQ data points to the primary receive beamformer processor.

[0135] In a further embodiment, the primary receive beamformer processor then combines (e.g., sums) corresponding sets of received partial beamforming frequency domain IQ data points received from all of the plurality of distributed secondary receive beamformer processors to form a plurality of frequency domain subcarrier IQ user data layers (e.g., up to eight such layers on the uplink (receive) side). In some embodiments, each respective set of received partial beamforming frequency domain IQ data points formed in each secondary receive beamformer processor represents a respective plurality of partial beamforming frequency domain subcarrier IQ user data layers. More specifically, each set of received partial beamforming frequency domain IQ data points represents one corresponding partial frequency domain subcarrier IQ user data layer (e.g., the first set of received partial beamforming frequency domain IQ data points represents the first partial frequency domain subcarrier IQ user data layer, the second set of received partial beamforming frequency domain IQ data points represents the second different partial frequency domain subcarrier IQ user data layer, and so on (e.g., up to eight partial frequency domain subcarrier IQ user data layers)). In this way, each secondary receive beamformer processor can calculate the partial beamforming frequency domain subcarrier IQ user data layer for each frequency domain subcarrier IQ user data layer. The primary receive beamformer processor can then add the partial beamforming frequency domain IQ data points for each user data layer to obtain the corresponding full beamforming data layer.

[0136] Accordingly, some embodiments disclosed herein include an apparatus comprising: (i) a primary receive beamformer processor; (ii) a plurality of distributed secondary receive beamformer processors connected to the primary receive beamformer processor; and (iii) a plurality of sets of transceiver integrated circuits (ICs) or transceiver IC subarrays connected to the plurality of distributed secondary receive beamformer processors. In this apparatus, the plurality of distributed secondary receive beamformer processors are physically distributed such that each distributed secondary receive beamformer processor is disposed within or adjacent to a respective region of an antenna array associated with a respective one of a plurality of receive beamforming submatrices, and each receive beamforming submatrix includes receive beamforming coupling weights associated with antenna elements within a respective region of the antenna array. In this regard, each set of transceiver IC / IC subarray is connected to a corresponding one of the plurality of distributed secondary receive beamformer processors and is disposed within a respective region of the antenna array associated with the corresponding distributed secondary receive beamformer processor. Further, in the apparatus, each distributed secondary receive beamformer processor is configured to: (i) receive a respective set of frequency domain IQ data points from the corresponding set of transceiver IC / IC subarray; (ii) use the respective sets of frequency domain IQ data points and the respective receive beamforming submatrices to form a plurality of respective sets of received partial beamforming frequency domain IQ data points; and transmit the plurality of respective sets of received partial beamforming frequency domain IQ data points to the primary receive beamformer processor.

[0137] The method includes: (i) in each of a plurality of distributed secondary receive beamformer processors connected to a primary receive beamformer processor, receiving each set of frequency domain IQ data points from a corresponding one of a plurality of sets of transceiver integrated circuit (IC) subarrays, wherein the plurality of distributed secondary receive beamformer processors are physically distributed such that each distributed secondary receive beamformer processor is disposed within or adjacent to a respective region of an antenna array associated with a respective one of the plurality of receive beamforming partial matrices, each receive beamforming partial matrix includes receive beamforming coupling weights associated with antenna elements within a respective region of the antenna array, and the corresponding set of transceiver IC subarrays is disposed within a respective region of the antenna array associated with the distributed secondary receive beamformer processor; (ii) calculating, by each distributed secondary receive beamformer processor, a plurality of respective sets of received partial beamforming frequency domain IQ data points using each set of frequency domain IQ data points and each receive beamforming partial matrix; and (iii) transmitting, by each distributed secondary receive beamformer processor, the plurality of respective sets of received partial beamforming frequency domain IQ data points to the primary receive beamformer processor.

[0138] In the subarray beamforming described previously in this specification, during reception (and thus on the uplink side), each transceiver IC within a given subarray can generate frequency-domain IQ data packets aggregated at each transceiver IC, for example, when crossing a set of cascaded transceiver ICs within the subarray on the way towards the beamformer processor. As described above (see, for example, FIG. 3), the IQ packet data from each transceiver IC within the subarray may be concatenated or combined IQ data for, for example, a plurality of signal ports (such as horizontal (H) and vertical (V) ports). The received signals being commonly processed by the transceiver IC subarray are aggregated signals having components from multiple data layers, multiple individual beams, and possibly multiple users.

[0139] On the uplink side, the hierarchical beamformer 722 can receive, for example, up to eight user data layers within one symbol time (e.g., 66.7 μs). In this regard, in some embodiments, each secondary receive beamformer processor (e.g., each of the secondary beamformers 728, 734, 736, and 738) receives packets that carry IQ data points from a corresponding set of transceiver IC subarrays connected to the secondary receive beamformer processor. In some embodiments, the data packets may be in the time domain or the frequency domain. Here, each distributed secondary receive beamformer processor may be composed of, for example, an appropriate FFT process (e.g., a digital signal processor (DSP) composed of appropriate programming instructions for executing an algorithm for FFT operations) to perform calculations involved in converting time-domain IQ data to frequency-domain IQ data. Further, each distributed secondary receive beamformer processor can be configured using appropriate logic for processing the received packets to extract the IQ data.

[0140] In an exemplary embodiment, prior to restoring the full beamforming user data layer from the IQ data packets received from the transceiver IC / IC subarray across the entire antenna array, each secondary receive beamformer processor receives IQ data packets that are not combined in any way from each transceiver IC / IC subarray it serves. Due to the distributed nature of the hierarchical beamformer 722, none of the secondary receive beamformer processors can access all of the received signals (e.g., 64 uplink signals) received via a plurality of sets of transceiver IC / IC subarrays associated with the antenna elements across the entire antenna subarray. For example, in connection with the configuration shown in FIG. 2, each distributed secondary receive beamformer (e.g., each of BF#1-4) has access to only 16 received signals (8 received signals each from 8 corresponding sets of transceiver IC subarrays for the H-polarized signal port and the V-polarized signal port, respectively).

[0141] In some embodiments, as described above, each distributed secondary receive beamformer processor receives each set of frequency domain IQ data points (e.g., carried in IQ data packets) from a corresponding set of transceiver IC subarrays disposed within a given region of the antenna array associated with the distributed secondary receive beamformer processor and its respective receive beamforming submatrices, and is configured to form a plurality of sets of receive partial beamforming frequency domain IQ data points for that distributed secondary receive beamformer processor using each set of frequency domain IQ data points and its respective transmit beamforming submatrices. More specifically, in some embodiments, each distributed secondary transmit beamformer processor is further configured to compute each set of partial beamforming frequency domain IQ data points by applying the receive beamforming combining weights of its respective receive beamforming submatrices to each set of frequency domain IQ data points, e.g., by performing matrix multiplication. In some embodiments, each set of partial beamforming frequency domain IQ data points represents a given partial beamforming frequency domain subcarrier IQ user data layer for each frequency domain subcarrier IQ user data layer. By applying the receive beamforming combining weights of the receive beamforming matrix to that set of frequency domain IQ data points via matrix multiplication, each secondary receive beamformer processor can form a given number of subcombinations (partial sums) of frequency domain IQ data points that represent a corresponding number of partial beamforming frequency domain subcarrier IQ data layers.

[0142] After that, in some embodiments, each distributed secondary receive beamformer processor can send each set of received partial beamforming frequency domain IQ data points calculated by that secondary receive beamformer processor to the primary receive beamformer processor. In some embodiments, next, the primary receive beamformer processor (e.g., 722) is configured to combine corresponding sets of received partial beamforming frequency domain IQ data points received from all of the distributed secondary receive beamformer processors (e.g., 728, 734, 736, and 738) to form frequency domain subcarrier IQ user data layers (e.g., up to 8 layers). In this regard, in some embodiments, the primary receive beamformer processor can combine (e.g., add) the corresponding sets of received partial beamforming frequency domain IQ data points for each user data layer received from all of the secondary receive beamformer processors to obtain each complete beamforming frequency domain subcarrier IQ user data layer.

[0143] More specifically, the primary receive beamformer processor may add together the sets of partial beamforming frequency domain IQ data points for user data layer 1 received from each secondary receive beamformer processor to obtain a complete beamforming user data layer 1, and may add together the sets of partial beamforming frequency domain IQ data points for user data layer 2 received from each secondary receive beamformer processor to obtain a complete beamforming user data layer 2, and so on. The primary receive beamformer processor can perform this process up to a specified number of uplink user data layers to recover all of the complete beamforming uplink user data layers. In some embodiments, the primary receive beamformer processor can combine up to 8 data layers within each symbol time.

[0144] In some embodiments, each distributed secondary receive beamformer processor can transmit a set of locally formed receive partial beamforming frequency domain IQ data points to the primary receive beamformer processor as packetized data. In this regard, in some embodiments, each distributed secondary receive beamformer processor includes a packet processor (e.g., a dedicated DSP circuit, etc.) configured to form corresponding receive partial beamforming frequency domain IQ data packets using a locally formed set of receive partial beamforming frequency domain IQ data points for transmission to the primary receive beamformer processor. Further, in some embodiments, the packet has a header indicating at least component carrier information.

[0145] As noted above, it should be noted that each distributed secondary receive beamformer processor is configured to form a set of receive partial beamforming frequency domain IQ data points using a receive beamforming partial matrix. In this regard, in some embodiments, the primary receive beamformer processor divides the receive beamforming matrix of beamforming combining weights into a plurality of receive beamforming partial matrices in a manner similar to that described above for the downlink (transmission) beamforming operation, and each respective receive beamforming partial matrix may be configured to be transmitted to a corresponding one of the distributed secondary receive beamformer processors. In other embodiments, a predetermined set of receive beamforming combining weights may instead be stored in a given distributed secondary transmit beamformer processor in a form such as a look-up table in a manner similar to that described above for the downlink (transmission) beamforming operation.

[0146] Accordingly, in summary, according to the embodiments described herein, each distributed secondary receive beamformer processor has access to a given portion of the received signal (e.g., a portion of the uplink signal generated by a subset of the transceivers (e.g., 2 out of 4, 4 out of 8, 4 out of 16, or 16 out of 64, etc.)), and thus can form partial beamforming frequency domain IQ data layers for each of a plurality of specified uplink layers (e.g., 8 layers). Then, each distributed secondary receive beamformer processor (which can be 2, 3, 4, 8, or more depending on the size of the system) can send a specified number of partial beamforming frequency domain subcarrier IQ data layers to the primary receive beamformer processor (e.g., via link 726). Thereafter, the primary receive beamformer processor can combine the individual partial beamforming frequency domain subcarrier IQ data layers from all of the distributed secondary receive beamformer processors to form a specified number of complete beamforming user data layers. Accordingly, the primary receive beamformer processor can form a specified number of distinct combinations of IQ sample data, each combination corresponding to a frequency domain subcarrier IQ user data layer.

[0147] FIG. 8 is a graphical representation of downlink transmission beamforming operation. User data is represented by layers of data along dimension 818, and subcarrier-specific IQ data for each such layer is shown along dimension 816. In some embodiments, the user data layers along dimension 818 are frequency-domain IQ data layers (e.g., data layers distributed on respective links 726 to individual secondary beamformers, as described in connection with FIG. 7). Each data layer, such as layers 820, 822, etc., may actually be aggregated user data for one or more users, and different users are allocated / assigned different subsets of subcarriers represented along dimension 816. Further, a given user may be allocated one or more data layers (along dimension 818), such as in the case of spatial multiplexing. In this regard, as described above, each (user) data layer may include subcarrier-specific IQ data allocated among PRBs for one or more users (along with each RB as defined above).

[0148] In some embodiments, a beamformer (e.g., 202, 300, 400, 724 (primary beamformer), etc.) calculates beamforming weights for a set of carriers along dimension 802, for a user data layer represented by IQ data along dimension 800, and for signal ports along dimension 804. Note that in embodiments with pre-storing of beamforming weights in each of the secondary beamformers, the calculation of beamforming weights in the primary beamformer is omitted. As shown in FIG. 8, according to matrix multiplication, the beamforming weights shown in the top layer of the matrix (i.e., the horizontal slice of the matrix along dimensions 802×800) are applied to the data layer (816×818) to generate the top layer (the top of dimension 824) of beamforming IQ data having sub-carriers along dimension 826. For simplicity, the rows or layers along beamforming dimension 804 alternate between H polarization and V polarization, such that, for example, elements 806, 808 each include separate signal port weights such as "H" weights and "V" weights, which are used independently to combine data layers such as layers 820, 822, etc. Note that the H / V pairs of weights shown as being interleaved in the matrix columns in the vertical direction (dimension 804) can be associated in some operating modes or can be beams selected completely independently for the H and V components (i.e., signal ports). Columns of the beamforming matrix, such as column 807 or 809, can be applied to a given set of sub-carriers in a corresponding given data layer according to the desired beamforming operation. Note that the beamforming matrix can also incorporate precoding matrix calculations to form a linear combination of data layers according to the desired precoding matrix. In this way, the beamformer matrix is used to operate on the user data layer to generate signal port-specific IQ data.

[0149] In the embodiment shown in FIG. 8, as described with respect to FIG. 3, each set of beamforming IQ data points is packetized and transmitted to the corresponding transceiver IC / IC subarray. In some embodiments, the packetized IQ data can remain in the frequency domain. However, in other embodiments, the packetized IQ data may instead be converted to time domain IQ data. In some embodiments, the IQ data for the 64 signal ports along dimension 826 includes the IQ data for the 32H and 32V signal ports. Each of the four sections 828, 830, 832, and 834 of the 826-signal-port-specific IQ data contains 16 beamforming IQ data packets, which can be combined via concatenation into eight separate dual-signal-port H / V packets that are similar in format to packet 302 of FIG. 3. Each of these eight H / V IQ packets contains either time domain or frequency domain IQ data and is transmitted via a single serial data link to a respective transceiver IC subarray, such as one of the eight transceiver IC subarrays along the rows of subarray 238a shown in FIG. 2. The IQ data for sections 830, 832, and 834 are each similarly packetized into eight unique IQ data packet streams and transmitted to the eight corresponding transceiver subarrays within transceiver subarray rows 238b, 238c, and 238d, respectively. In this embodiment, each dual-signal-port IQ data packet can be commonly processed by two serially-connected transceiver ICs. Alternatively, each of the eight H / V packets obtained from section 828 can be transmitted to the respective transceiver IC subarray in the first row of transceiver IC subarray 421a of FIG. 4, along with a similar distribution of dual-signal-port IQ packets to the rows of transceiver IC subarrays 421b, 421c, and 421d. In the embodiment of FIG. 4, each beamforming IQ data packet is commonly processed by three serially-connected transceiver ICs.

[0150] As an example, during operation, a 64-TRX (transmit / receive) massive MIMO RU (e.g., RU704) may support 16 downlink beamforming layers and 8 uplink beamforming layers. (Note that in FIG. 8, for simplicity, only 8 layers out of 818 are shown). A downlink (DL) beamformer (e.g., one of secondary beamformers BF#1 to 4) receives a [16×1] complex vector of user data layers as input for each subcarrier, and then multiplies this complex vector by a transmit beamforming submatrix [64×16] containing complex beamforming weights to output a [64×1] complex vector for each subcarrier within each of the physical transmit (TX) antenna streams. In this regard, a stream refers to a sequence of frequency-domain IQ data packets for a given signal path (as noted above, further conversion to the time domain may be possible). Matrix calculations for one subcarrier are shown below and are actually extended across the entire set of subcarriers. For example, for one subcarrier,

[0151]

Number

[0152] [64×1] The output vector is divided into groups of physical antenna streams, and one group for the set of transmit antenna streams is designated for each transceiver IC subarray. In embodiments where each transceiver IC can generate two unique transmit signal paths (or simply signals) and each subarray has two transceiver IC devices, each group will contain packets associated with four distinct physical antenna streams. In other embodiments where each transceiver IC device can generate four unique transmit signals and each subarray has two transceiver devices, each group will contain packets associated with eight distinct physical antenna streams. In yet another embodiment where each transceiver IC device can generate four unique transmit signals and each subarray has only one transceiver IC device, each group will contain packets associated with four distinct physical antenna streams. In some embodiments, the complex beamforming weights of the beamforming matrix are designated for each PRB (physical resource block - a group of 12 subcarriers for one slot of 7 symbols, a total of 84 resource elements (RE)).

[0153] For illustration, in one exemplary embodiment, each distributed secondary beamformer within the hierarchical beamformer architecture (as described above) can be configured to (i) take as input a [16×1] complex vector of the (frequency-domain subcarrier IQ) user data layer, (ii) multiply that complex vector by a [4×16] beamforming transmit submatrix of complex beamforming weights, and (iii) output a [4×1] complex vector for each subcarrier of four physical transmit antenna (signal) streams. A calculation example is shown below.

[0154]

Number

[0155] Regarding the multi-layer beamforming IQ data packet 850 representing beamforming IQ data for one embodiment of a transceiver IC subarray, the beamformer processor, for use by a transceiver IC that processes signals according to first-layer beamforming, a commonly processed IQ data packet 864 (either in time-domain or frequency-domain format) for one signal port (e.g., representing subcarrier IQ data for all subcarriers, or a subset of subcarriers of one component carrier of the signal port), and a second commonly processed IQ data packet 866 for a second signal port (the second commonly processed IQ data packet 866 is either in time-domain or frequency-domain format, e.g., depending on the format of the commonly processed IQ data packet 864 for the first port) are generated, and at the same time, it may be configured to also generate higher-resolution beamforming of the second layer. The second-layer beamforming is performed according to the full-digital beamforming IQ packets 852, 854, 856 for processing by individual transceiver ICs and their respective horizontal signal ports (H1, H2, H3 shown in FIG. 8), and the full-digital beamforming IQ packets 858, 860, 862 for processing by individual transceiver ICs and their respective vertical signal ports (V1, V2, V3 shown in FIG. 8), as previously described with respect to FIG. 3. Further, as previously described, the second-layer beamforming IQ data packets can include subcarriers associated with the same component carrier as the commonly processed IQ data packets, or subcarriers associated with a second component carrier.

[0156] More specifically, the first beamforming IQ data packet may include IQ data 864 (labeled Hc, where "c" indicates IQ data for common processing), 866 (Vc) for common processing by all transceiver ICs (e.g., three separate transceiver ICs each capable of 2T2R operation) within a given transceiver IC subarray. Three additional packets of transceiver-IC-specific IQ data, each including data 852 concatenated with data 858, data 854 concatenated with data 860, and data 856 concatenated with data 862, are also transmitted to the transceiver IC subarray. The first transceiver IC combines the commonly processed data 864 with data 852 and the commonly processed data 866 with data 858. Another transceiver IC combines the commonly processed data 864 with data 854 and the commonly processed data 866 with data 860, and a third transceiver IC combines the commonly processed data 864 with data 856 and the commonly processed data 866 with data 862.

[0157] FIG. 9 is a graph showing the conversion of user data layers 906, 916, 918 represented by a matrix [X]900 of dimension L (i.e., the number of layers) into beamforming downlink transmission IQ data packets at a logical baseband port 926 represented by a matrix [Z]904 of dimension M. In some embodiments, the user data layers 906, 916, 918 remain in frequency domain format until the data associated therewith is beamformed. After the beamforming operation is completed, in some embodiments, the beamforming downlink transmission IQ data may be packetized to form beamforming frequency domain IQ data packets. As described above, in some further embodiments, the beamforming frequency domain IQ data packets may be further converted into beamforming time domain IQ data packets for transmission to respective transceiver ICs or transceiver IC subarrays (e.g., transceiver subarray 914 as shown in FIG. 9). According to the simplified signal processing shown in FIG. 9, the data layer [X]900 undergoes a precoding operation by the matrix PM920 according to the precoding operation to obtain a logical antenna port signal 922 represented by the matrix [Y]902, and then, using various beamforming beam indices (e.g., "beam IDx") having weights such as "beam 1"910, the beamforming operation by the digital beamforming matrix DB924 continues, applying beam weights, and distributing appropriately weighted precoded signals at node 908 (a precoded linear combination of data layers 906, 916, 918) across various logical baseband ports 926 represented by the matrix [Z]904 (also shown as IQ data 828, 830, 832, 834). Each beamforming packet of the matrix [Z], such as the IQ data packet 912, is conveyed to its corresponding transceiver IC subarray 914. As explained above, the data packet 912 may include either frequency domain IQ data or time domain IQ data.

[0158] FIG. 10 is a diagram of the conversion of user data layer beamforming IQ data streams by operation 1000 of a generalized combined precoding and beamforming matrix 1012 obtained from the matrix multiplication of a precoding matrix PM920 and a beamforming matrix DB924. User IQ data layer [X] 1004 is provided by a processor 1002 that provides user IQ data processed according to standard encoding, cyclic redundancy check (CRC), rate matching (RM), and resource element (RE) mapping. Data layer [X] 1004 is processed according to the generalized space multiplexer / beamformer matrix PM in conversion 1000 to generate a logical baseband port IQ signal packet 1014 represented by a signal port IQ data matrix [Z] 1006 for transmission via respective serial data links to transceiver IC subarrays such as subarray 1008. As used herein, the terms "beamforming" and "beamforming matrix" refer to the combined beamforming / precoding operation as described, whether implemented in a single matrix operation or in multiple separate matrix operations. As described in connection with FIG. 9, the IQ data packet carried from each respective logical baseband port 1014 to its corresponding transceiver IC subarray 1008 (and thus following the beamforming / precoding operation) can be either a frequency domain IQ data packet or a time domain IQ data packet (if converted to the time domain).

[0159] FIG. 11 is a diagram of receive uplink signal processing including receive beamforming and layer decoding. Each transceiver IC subarray 1108 provides the received IQ data to a beamformer processor as a logical baseband port 1116 represented by a matrix [Z] 1106. Virtual antenna port signals 1112 can be formed according to a matrix [Y] 1104. Finally, individual data layers 1110 represented by a matrix [X] 1102 can be restored.

[0160] FIG. 12 shows a block diagram of a transceiver IC device architecture suitable for forming a group of serially connected transceivers. The transceiver IC is suitable for operation in both FDD mode and TDD mode, and the configuration shown in FIG. 12 is connected for operation in TDD mode. Each transceiver IC 1200 includes a plurality of signal processing paths for both transmission signal processing and reception signal processing. For DL transmission signal processing, the transceiver IC 1200 includes a serial data receiver RX#0 1202 for receiving frequency domain IQ data packets via a serial data receiver 1202. The serial data receiver 1202 includes a data buffer for storing several deserialized data words, and a data analysis circuit for performing packet header analysis to determine whether the received packet is intended to be processed by the current transceiver IC and / or whether it is intended to be processed by one or more other transceiver ICs within the transceiver IC subarray. When the packet is processed locally, the packet is transferred via 1206 to the DSP memory 1210 accessible to the integrated digital signal processor (DSP) 1215, via, for example, a memory storage device or direct memory access (DMA) operation. In an alternative embodiment, the header inspection may be performed by the DSP 1215, which places the data in the DSP memory 1210 designated for retransmission via the SerDes transmitter TX#1 1262.

[0161] When executed, the DSP 1215 includes programming stored in a non-volatile memory that causes the DSP 1215 to execute an algorithm 1214 for converting frequency domain digital IQ data to time domain digital data. The stored algorithm instructions include processor instructions for the iFFT operation 1214 and further include instructions for expanding the data converted by the addition of a cyclic prefix (CP).

[0162] In the subarray beamforming described in this specification, each IC within a given subarray processes the same frequency-domain IQ packet (referred to herein as "commonly processed" IQ data) for transmission, generates a frequency-domain IQ packet during reception, and the frequency-domain IQ packet is aggregated at each transceiver IC as it crosses a cascaded set of transceiver ICs on its way to the beamformer processor. Since the signals commonly processed by the transceiver ICs are aggregated beamforming signals having components from multiple data layers and multiple individual beams, it is not possible to adjust the individual beams within a given subarray of the commonly processed IQ data packets. However, at each element (i.e., each signal port) within the subarray, it is possible to apply a unique phase rotation to the aggregated beamforming signal, which has the effect of tilting the entire synthesized / aggregated beamforming signal. Thus, when beam tilt is desired, the transceiver is configured to incrementally adjust the phase of each commonly processed IQ data packet according to the position of the radiating elements driven by the transceiver ICs within the IC subarray. Without the incremental adjustment of the phase at each subarray element, probably only one of the elements will be in alignment and the wavefronts from the remaining elements will progress (or lag) incrementally according to their positions within the subarray for a given downward (upward) tilt, so that a true tilt is not obtained. In this way, beam tilt can be obtained through baseband signal processing without directly adjusting any signal components in the analog domain (including not adjusting the VCO phase).

[0163] More specifically, when the linear array of antenna elements is physically "tilted" (either a vertical array with height tilted up / down or a horizontal array with azimuth tilted left / right), the result can be regarded as an incremental time delay in signal transmission (or reception) across the antenna elements of the array, thereby changing the direction in which the propagation wavefronts are added to reinforce each other to form the main lobe (and combined to weaken each other to form nulls). Electronic tilt is a process that imposes an appropriate signal delay without actually physically repositioning the antenna. The relationship between the time delay and the corresponding phase change of the signal depends on the tilt angle as well as the frequency of the signal. That is, a given time delay between two signals corresponds to a linear phase shift in the frequency content of the signal, and a given time delay results in a lower phase change for lower frequencies within the signal and a linearly higher phase change at higher frequencies. Thus, in the case of a narrowband signal, a specific time delay is approximately converted to a specific phase shift between the delayed signals. However, in the case of a broadband signal such as an OFDM signal of 50 or 100 MHz and above, a given time delay affects the phases of the OFDM subcarriers differently. Nevertheless, in a phased array where each subcarrier is rotated by the same phase, this results in a non-linear phase characteristic generally referred to as beam squint. A certain amount of beam squint is acceptable in an OFDM signal with a bandwidth of about 100 MHz.

[0164] Therefore, electronic beam tilt in a physically static array can be achieved by various methods performed by the individual transceivers described herein, including (i) applying an incremental phase rotation to each subcarrier frequency domain IQ data point (e.g., via an NCO), (ii) applying a constant phase rotation to each subcarrier frequency domain IQ data point (e.g., via complex multiplication), (iii) applying a constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication), (iv) imposing a time delay on the discrete time domain signal of the transmitted baseband signal, or (v) a combination of the above methods. Note that methods (ii) and (iii) result in a certain amount of beam squint distortion.

[0165] In this regard, beam tilt can be implemented by applying a linearly increasing phase rotation across subcarriers by a complex multiplier 1212 implemented as a numerically controlled oscillator (NCO) as described with respect to NCO 542 in FIG. 5. NCO 1212 is configured to provide a sequence of complex numbers with a linearly increasing phase for multiplication by a corresponding sequence of subcarrier frequency domain IQ data points. For a desired beam tilt, an initial phase and an increment rate at which the phase increases from subcarrier to subcarrier are determined and the values are loaded into NCO phase accumulator 564 and FCW register 562 respectively. The phase increment value can be determined according to one or more various factors including (i) the desired beam tilt angle, (ii) the subcarrier spacing, (iii) the carrier frequency, and (iv) the position of the particular radiating element being driven by the transceiver IC. Generally, to achieve a beam tilt of angle φ, the phase rotation θ at a given subcarrier frequency 1 / λ at position n within the array is given by the following equation,

[0166]

Equation

[0167] Alternatively, the complex multiplier 1212 can be configured to apply a constant phase rotation to each frequency domain IQ data point prior to the conversion via the iFFT 1214 in order to implement an approximate time delay to achieve beam tilt. For a desired beam tilt, a frequency domain phase rotation represented by a single complex number is determined and the value is loaded into the complex multiplier 1212. The frequency domain phase value can be determined according to one or more various factors including (i) the desired beam tilt angle, (ii) the array position of the particular radiating element being driven by the transceiver IC, and (iii) the carrier frequency. In the receive beam tilt operation, a constant phase rotation can be implemented in the complex multiplier 1238 after the FFT process.

[0168] In some embodiments, beam tilt is implemented by applying a constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication). For a desired beam tilt, a time domain phase rotation represented by a single complex number is determined and the value is loaded into the complex multiplier 1306 (which can also implement a gain function simultaneously). The time domain phase value can be determined according to one or more various factors including (i) the desired beam tilt angle, and (ii) the position of the particular radiating element being driven by the transceiver IC. In the receive beam tilt operation, a constant phase rotation can be implemented in the complex multiplier 1386 (while also implementing a gain function) prior to the FFT process.

[0169] In some embodiments, beam tilt is implemented by imposing a time delay on the discrete time domain signal of the transmit baseband signal. For a desired beam tilt, a time domain delay is determined and the value is loaded into the delay buffer 1312. The time domain delay value can be determined according to one or more various factors including (i) the desired beam tilt angle, (ii) the time domain sample rate, and (iii) the position of the particular radiating element being driven by the transceiver IC. In the receive beam tilt operation, the time delay can be implemented in the delay buffer 1378.

[0170] In a further embodiment, a combination of the above methods may be used. In a particular embodiment, the electronic beam tilt may be composed of a coarse adjustment and a fine adjustment. The coarse beam tilt may be implemented by applying a phase rotation that linearly increases across subcarriers by a complex multiplier 1212 implemented as an NCO using a limited resolution or a limited number of bits. The fine resolution may be implemented by further adjustment in the time domain, such as a time delay or a phase rotation with a constant time domain.

[0171] In various embodiments of the beam tilt phase adjustment, the phase rotation may be specified by a control message provided to the transceiver IC. A specific phase value may be provided, or a phase index value may be included in the control message, or may be included in the header of the IQ data packet itself. The phase index value may be used, for example, to retrieve a pre-computed phase value from a look-up table. In some embodiments, the transceiver IC may combine coefficients to calculate the specific rotation to be applied (e.g., a desired tilt angle may be provided, and the transceiver IC may adjust the phase rotation according to its predetermined position within the array and / or transceiver IC sub-array). Such a phase rotation may be used to implement the beam tilt phase rotation.

[0172] In some embodiments, the beam tilt may be implemented using a combination of a linear phase rotation applied in the frequency domain, followed by either a constant phase rotation in the time domain or a time delay in the time domain after the iFFT transform. In some embodiments, the frequency domain rotation can achieve a coarse tilt or an approximation of the desired beam tilt, while the time domain rotation may be a fine tilt. This can be particularly useful when a larger tilt angle is desired.

[0173] In a further embodiment, the dynamic adjustment of the tilt angle may be implemented for each slot, significantly improving the available scan range and coverage from a panel array using sub - array beamforming. In such an embodiment, beam tilt information is shown, as well as which time slots, sub - carriers, or component carriers can be specified via a control message.

[0174] In one embodiment, for common processing by the transceiver, electronic antenna beam tilt is implemented in a transceiver sub - array by distributing beamforming IQ data packets to a plurality of serially connected transceiver ICs. The IQ data packets have individual IQ values for each of a plurality of sub - carriers. In each transceiver IC, an electronic beam tilt phase rotation is applied. In some embodiments, applying the beam tilt phase rotation is done by changing the phase of each IQ - modulated sub - carrier based on the desired antenna tilt and array position. The phase change may be a constant phase rotation applied to all sub - carriers, or a linear increasing phase rotation increasing from sub - carrier to sub - carrier. The phase adjustment may be specified according to one or more control messages. The control message may be specific to a given sub - array, a transceiver IC within the sub - array, or an individual transceiver IC. The phase adjustment may be specified with respect to time delay, frequency domain multiplication rotation, or time domain complex rotation, or equivalent data. A given transceiver IC can also calculate the final phase adjustment by combining the phase adjustment data with array position data unique to the transceiver IC.

[0175] Referring back to FIG. 12, the time domain IQ data is stored in a DSP memory 1216 accessible by a transmit time domain signal processing circuit 1217 (further described with respect to FIG. 13A). In the embodiment of FIG. 12, the circuit 1217 includes two parallel component carrier processing circuits 1218, 1228 and corresponding time domain signal processing circuits 1220, 1230, each providing a baseband time domain OFDM signal (each being a single or multi-component carrier signal) to corresponding digital power amplifier (DPA) circuits 1222, 1232.

[0176] In one embodiment, the DPAs 1220, 1232 perform simultaneous RF modulation and amplification, which may be the final power amplification of the RF signal. In some embodiments, the DPA provides pre-amplification of the RF signal applied to an external power amplifier that drives a radiating antenna element. The external power amplifiers are distributed across the active antenna panel assembly adjacent to each element. The DPAs 1220, 1232 are provided with a plurality of RF carrier phases resulting from a system phase lock loop (SYSPLL) and are further processed by a synchronous RF PLL 1262 that drives an RF carrier generator VCO 1260. The selected RF carrier phases are used to switch amplifier cells within the DPA. As described herein, the particular RF carrier phases and the respective number of activated cells that determine their relative magnitudes are selected according to the time domain IQ data points provided by the circuits 1220, 1230.

[0177] The transceiver IC 1200 also includes a receive time domain signal processing circuit 1241 (further described with respect to FIG. 13B) for down-converting an analog RF signal via an IQ mixer driven by the VCO 1260 and generating separate baseband I and Q analog signals for sampling by analog-to-digital converters (ADCs) in circuits 1244, 1252. The sampled signals are then processed by time domain filtering and downsampling circuits 1242, 1250. The processed time domain signals are then stored in the DSP memory 1216 for further processing including removal of the CP and conversion to subcarrier specific frequency domain IQ data by the FFT algorithm (“FFT” 1240 in FIG. 12). The DSP 1215 includes programming stored in non-volatile memory that, when executed, causes the DSP 1215 to execute an algorithm for converting time domain digital data to frequency domain digital IQ data. Next, an NCO (e.g., 1238) can be used to apply a linearly increasing phase rotation to each frequency domain IQ (i.e., subcarrier) value, which is also one embodiment of electronic beam tilt. Next, the received IQ frequency domain data is processed by the MUX / combining circuit 1264 for transmission to the serial data bus via the serial transmitter TX#0 1204.

[0178] FIG. 13A is a block diagram 1300 of a time domain signal processing circuit 1217. The frequency domain IQ data is received from the DSP memory via line 1302 (and similarly, 1304, 1344, 1346) and applied to a signal path power detector and a gain unit 1306 for adjusting the power level. In some embodiments, the gain multiplier may also include a complex phase that rotates each time domain value by the same phase. This time domain phase rotation can be used to apply an approximate time delay that can be used to implement an electronic beam tilt. This corresponds to a phase rotation of each constituent subcarrier by the same phase, rather than a linearly incremented phase rotation, and is accurate enough for a bandwidth of about 100 MHz within the frequency range of the bands used for LTE and 5G signals. The signal is filtered by an FIR filter stage 1308 that also includes one or more interpolation stages to increase the sample rate of the discrete time domain signal. The discrete time digital UL signal is then processed by a numerically controlled oscillator (NCO) 1310. The NCO (e.g., 1310) can be configured to multiply the time domain signal by a complex sine function to perform a frequency shift of the baseband signal to a desired frequency range, such as a separate frequency range that does not overlap with other component carriers. In some embodiments, one transmit signal can be shifted slightly up in frequency so that two time domain signals representing, for example, two component carriers can be added together without the frequency content of one signal overlapping with the frequency content of the other signal, while another transmit signal, such as a separate component carrier provided on connection 1304, can be shifted slightly down using the corresponding NCO. The signal is further processed by a delay buffer 1312 that enables precise time offset adjustment of the transmit signal. In some embodiments, the delay buffer 1312 is used to provide delay adjustment for each carrier. The delay buffer 1312 compensates for different processing times for different supported subcarrier spacings (SCS) and bandwidths. Assuming that all filtering is performed using FIR filters for all carriers, the adjustable delay per carrier is the difference between the larger delay and the shortest delay, which is on the order of 10 μs.However, sharing that function with windowing relaxes that requirement.

[0179] Other discrete-time domain signals 1304, 1344, 1346 resulting from the frequency domain to time domain conversion from DSP1215 are similarly processed. The signal is then coupled and / or routed via MUX / ADD circuit 1314 to transmit signal processing circuits 1316, 1348 for crest factor reduction (e.g., CFR1318), further FIR filtering (including further upsampling / interpolation), and IQ multiplication (e.g., FIR IQ circuit 1322) for phase adjustment and / or correction. The signal may also receive digital pre-distortion (DPD, e.g., DPD circuit 1324) to correct the phase and amplitude distortion present in modulators / amplifiers DPA1328a, 1328b with respect to the first signal port 1342 from RF signal adder 1340 (and with respect to DPA1328c, 1328d, with respect to signal port 1350). Each section 1328a - d of the DPA includes a clock domain crossing circuit 1330, a cascaded integrator-comb (CIC) filter 1332, a mapper circuit 1334, a delay circuit 1336, and a final DPA stage 1338.

[0180] FIG. 13B shows the receive signal processing portion of the transceiver. Digital samples from the ADC are received by the clock domain crossing circuit 1362 and adjusted for DC offset by the DC offset circuit 1364. The IQ multiplier 1366 can be used to provide automatic gain control of the baseband time domain signal in response to the power measured by the power detector PD 1368. The quadrature error compensation circuit (QEC 1370) provides compensation for frequency-dependent quadrature errors in the RX analog front end. In one embodiment, the QEC block 1370 divides a time domain signal (e.g., having a sample rate of 245.76 MHz) into 16 frequency bins each of 15.36 MHz. Each frequency bin is added to the mirror frequency bin content shaped by a complex multiplier. The notch filter 1372 can be used to reduce any unwanted out-of-band signals.

[0181] MUX1374 can be configured to selectively direct received signal samples from either path RX0 (1360) or RX1 (1394) to any or all of RX signal paths 1376, 1392, 1396, or 1398. Some examples of the different possibilities are all four RX signal paths from RX0, all four RX signal paths from RX1, RX0 to RX signal paths 1376 and 1392, RX1 to RX signal paths 1396 and 1398, RX0 to RX signal path 1376, and RX1 to RX signal paths 1392, 1396, and 1398. Each RX signal path includes a delay buffer (e.g., 1378), an NCO (e.g., 1380), a FIR filter and a downsampler (e.g., 1384, 1382), and a power detector (e.g., PD1390). Note that gain multiplier (e.g., 1386) can also implement a fixed phase rotation on the time domain signal. In such embodiments, this is equivalent to a fixed phase shift applied to each subcarrier, rather than a linearly increasing phase shift across subcarriers, but still provides a suitable approximation of time delay for the purpose of implementing electronic beam tilt. FIR1382 can also include a notch filter to remove component carriers not being processed by a given signal path. In some embodiments, NCO1380 can be used to apply a time domain frequency shift that moves the desired component carrier into the low pass passband of notch filter 1382.

[0182] FIG. 14 is a diagram showing a generalized configuration of exemplary signal processing via the transceiver IC devices of FIGS. 12 and 13 for dual-carrier, dual-polarization communication signals according to some embodiments. More specifically, the example of the signal processing configuration shown in FIG. 14 may be applicable in embodiments involving the communication of data packets associated with two different carriers (e.g., two component carriers), where each carrier signal has two polarizations (e.g., horizontal and vertical polarizations as described previously herein). In an exemplary embodiment, the transceiver device is a transceiver IC. Further, in the exemplary configuration of FIG. 14, the transceiver IC operates in TDD mode within an OFDM-modulated wireless network such as an LTE- or 5G-based communication system.

[0183] As shown in FIG. 14, the transceiver device (IC) 1400 includes a first serial communication port 1406 (e.g., a first serial port transmitter / receiver such as a Serdes transmitter / receiver) (shown as "Link 0" in FIG. 14) and a second serial communication port 1434 (e.g., a second serial port transmitter / receiver such as a Serdes transmitter / receiver) (shown as "Link 1" in FIG. 14). However, although the transceiver IC is shown as having two separate serial communication ports (1406 and 1434), it should be noted that in the embodiment of FIG. 14, only one of ports 1406 and 1436 is being used. More specifically, as shown, only serial communication port 1406 is connected to serial data links 1402 and 1404 to communicate data to / from the transceiver IC, and serial communication port 1434 is not being actively used. However, in some embodiments, the transceiver IC may be further serially connected to a second transceiver IC via port 1434 (e.g., as in the various embodiments described herein).

[0184] Generally, as described above, the transceiver IC can be configured to process four separate transmit component carriers and four separate receive component carriers. The transceiver IC is composed of at least two separate transmit signal port paths (chains) and at least two separate receive signal port paths (chains), and is typically associated with two corresponding antenna radiating elements. However, as described herein, other configurations are also possible. Also generally, the transceiver IC includes a number of signal processing elements, particularly an integrated digital signal processor (DSP) for converting frequency domain digital data to / from time domain digital data (via some iFFTs and FFTs), a plurality of integrated modulation digital power amplifiers (DPAs) for converting digital baseband time domain signals with cyclic prefix addition and removal to amplified analog RF signals, an analog RF downconverter, an analog-to-digital converter, etc.

[0185] Referring to FIG. 14, in some embodiments, serial communication port 1406 can receive, via serial data link 1402, a data packet stream (e.g., four multiplexed data packet streams) for DL (downlink) transmission (e.g., from a beamformer processor), where the packets include, for each of horizontal (H) polarization and vertical (V) polarization, a packet for a first component carrier (hereinafter, "carrier C1") and an IQ data packet for a second different component carrier (hereinafter, "carrier C2"). For the sake of brevity, in this specification, the combinations of two different component carriers and horizontal and vertical polarizations are respectively denoted as "C1H", "C2H", "C1V", and "C2V". In the UL (uplink) direction, serial communication port 1406 can receive, for each of the two carriers C1 and C2, for each of the two H polarizations and V polarizations, an IQ data packet stream (e.g., four multiplexed sets of IQ data for four sets of OFDM subcarriers) and transmit them (e.g., to a beamformer processor) via serial data link 1404. In an exemplary embodiment, the packets received at or transmitted from serial port communication port 1406 include frequency domain subcarrier specific digital IQ data. In some embodiments, different carrier packets addressed to the same transceiver IC can include a unique carrier ID and can be addressed to the same transceiver IC.

[0186] As shown in FIG. 14, serial communication port 1406 may be coupled to a signal processing unit 1408 that includes several elements configured to provide various digital signal processing functions, as previously described in connection with FIGS. 12 and 13, for example. In some embodiments, signal processing unit 1408 may be a single digital signal processor (DSP) that performs all of the iFFT and FFT calculations, as well as other signal processing functions (not explicitly shown) associated with frequency domain / time domain I / Q data signals, for example.

[0187] During operation, in the downlink (DL) transmission direction, the IQ packet data stream received via link 0 (1406) for DL transmission can be provided to a demultiplexer (or a similar element such as a section of memory by memory mapping) 1410 that can separate the received data into two respective data streams for two separate transmission chains, namely, one stream of IQ data for the dual-carrier horizontal polarization signal (C1H / C2H signal) transmitted from the signal port coupled to radiating element 1430 and another stream of IQ data for the dual-carrier vertical polarization signal (C1V / C2V signal) transmitted from the signal port coupled to radiating element 1422. An element 1412 (in the form of, for example, DSP memory) can further separate the horizontal and vertical frequency domain components (data points) for the subcarriers of each respective component carrier C1 and C2, which are then transmitted to four separate iFFT / CP (IFFT / cyclic prefix) elements 1414 for conversion from the frequency domain to the time domain to generate four separate discrete-time domain baseband data signals (two for each carrier frequency and two for each signal polarization). Although not explicitly shown, additional time domain and frequency domain processing may include, for example, cyclic prefix addition, frequency offset, phase and gain adjustment, filtering, and sample rate conversion.

[0188] In reality, as described above, the incoming data is split into four separate transmission paths. More specifically, as shown in FIG. 14, the output of unit 1408 includes (i) two separate discrete-time domain-based band data signals 1416 and 1418 shown as C1H(1416) and C2H(1418), and (ii) two separate discrete-time domain-based band data signals 1426 and 1428 shown as C1V(1426) and C2V(1428). As shown, following the conversion from the frequency domain to the time domain, the time domain signals C1H(1416) and C2H(1418) are added (summed) in time, and C1V(1426) and C2V(1428) are added (summed) in time, and the results of the signal addition are supplied to respective TX / DPA elements 1420, which generally represent the transmission RF chain and the digital power amplifier, to generate the amplified analog RF signal C1H / C2H(1424) for the horizontal signal port and the amplified analog RF signal C1V / C2V(1432) for the vertical signal port. Then, signals 1424 and 1432 are provided to the corresponding radiating elements 1422 and 1430 via respective SPDTs for transmission. Although not explicitly shown, it should be noted that additional time domain processing may include, for example, additional sample rate conversion, crest factor reduction (CFR), digital pre-distortion (DPD), etc., as previously described herein.

[0189] During operation, in the receive direction, the data-modulated dual-component carrier RF uplink signal can be received by transceiver IC (1400) at the horizontal and vertical signal ports via radiating elements 1422 and 1430. For ease of explanation and by way of example only, the amplified analog RF signals C1H / C2H (1424) and the amplified analog RF signals C1V / C2V (1432) are assumed herein to be the uplink signals received by the transceiver IC. As shown in FIG. 14, the horizontally polarized RF signal and the vertically polarized RF signal can be provided to separate LNA / DC / ADC elements 1446 via their respective SPDTs. The LNA / DC / ADC elements 1446 perform the conversion from RF to baseband signal and from analog to digital signal, and then, for example, can perform further time-domain processing (such as quadrature error correction, filtering, etc. (not explicitly shown)).

[0190] As further shown, the output of element 1446 includes two copies of the discrete-time domain baseband data signal. The two signals are filtered by FIR filters 1442, 1444, but one of the signals has its frequency first shifted by an NCO (either within filter 1442 or 1444) to separate the component carriers. The separated carriers are shown as C1H (1442) and C2H (1444). Two additional identical discrete-time domain baseband data signals are provided to filters 1426 and 1428 to generate time-domain signals representing the component carrier time-domain signals of C1V (provided by filter 1448) and C2V (provided by filter 1450) after NCO conversion and FIR filtering. These four separate time-domain baseband signals 1442, 1444, 1148, and 1450 (two for each carrier, two for each polarization) are then input to DSP 1408 for signal processing including CP removal and conversion from the time-domain IQ signal samples to frequency-domain IQ data representing the magnitude and phase of the respective sub-carriers of the corresponding component carriers.

[0191] Thus, the received RF signal is effectively split into four discrete-time domain based band data signals that are processed on four separate receive paths. More specifically, the C1H signal (1442), the C2H signal (1444), the C1V signal (1448), and the C2V signal (1450) are analyzed for four separate FFT signal processing operations (e.g., 1440) for conversion from the time domain to the frequency domain (by FFT), such as by memory mapping, and for each of the two component carrier frequencies, for each signal polarization, four separate frequency domain IQ data packets (or a stream of packets, where each packet in the stream represents a symbol time within a slot) are generated.

[0192] Although not explicitly shown, other time-frequency pre-conversion signal processing may include, for example, sample rate conversion, filtering, cyclic prefix detection and removal, etc., as described above. Following the conversion performed by the FFT element 1440, the elements 1436, 1438 (e.g., in the form of DSP memory and digital logic) can then formulate IQ data packets for different component carriers associated with both component carriers C1 and C2 for each polarization (H or V).

[0193] As a further illustration of other embodiments, FIG. 15 shows a generalized configuration of exemplary signal processing through two serially connected transceiver devices of FIGS. 12 and 13 for generating a 4-carrier dual-polarization communication signal according to some embodiments. More specifically, FIG. 15 shows a transceiver device architecture 1500 that includes a first transceiver device 1504a and a second transceiver device 1504b. As in FIG. 14, in an exemplary embodiment, the transceiver device is a transceiver IC and operates in TDD mode within an OFDM modulation system such as a 5G or LTE-based communication system. It should be noted that the various operating principles and nomenclatures described in connection with FIG. 14 apply to the embodiment of FIG. 15, and thus, some details of the operations are omitted or generalized for ease of explanation.

[0194] Referring to FIG. 15, the first transceiver device (IC) 1504a includes a first serial communication port 1506 (e.g., a first serial port transmitter / receiver such as a Serdes transmitter / receiver), shown as "Link 0" in FIG. 15, and a second serial communication port 1530 (e.g., a second serial port transmitter / receiver such as a Serdes transmitter / receiver), shown as "Link 1" in FIG. 15. Similarly, the second transceiver device (IC) 1504b includes a first serial communication port 1546 (e.g., a first serial port transmitter / receiver such as a Serdes transmitter / receiver), shown as "Link 0" in FIG. 15, and a second serial communication port 1562 (e.g., a second serial port transmitter / receiver such as a Serdes transmitter / receiver), shown as "Link 1" in FIG. 15. The transceiver devices (ICs) 1504a and 1504b are serially connected via a bidirectional serial data link 1544.

[0195] In some embodiments, serial communication port 1506 can receive, via bidirectional serial data link 1502, an IQ data packet stream for DL transmission (eight sets of IQ data packetized in four carrier-specific H / V combinations or, in the illustrated embodiment, as eight separate data packet streams), where the packets include IQ sub-carrier data for four different component carriers (hereinafter, "carrier C1", "carrier C2", "carrier C3", and "carrier C4") for each of horizontal (H) polarization and vertical (V) polarization. For the sake of brevity, the combinations of the four different carriers on horizontal and vertical polarizations are herein shown as "C1H", "C2H", "C3H", "C4H", "C1V", "C2V", "C3V", and "C4V", respectively. In the UL (uplink) direction, serial communication port 1506 can receive data packet streams (e.g., eight multiplexed data packet streams) for each of the four carriers C1, C2, C3, and C4 for each of two H polarizations and V polarizations and transmit them (e.g., to a beamformer processor) via the same bidirectional serial data link 1502. In an exemplary embodiment, the packets received at or transmitted from serial port communication port 1506 include frequency-domain digital IQ data.

[0196] During operation, in the DL transmission direction, the first transceiver IC (1504a) receives the packetized IQ data stream via port 1506 for DL transmission. The first transceiver IC is configured to process data related to the first two carriers for each polarization, i.e., C1H, C2H, C1V, and C2V. Similar to the transmission operation described in relation to FIG. 14, the first transceiver IC separates the received IQ data for carriers C1 and C2 into respective data sets for two separate transmission paths, i.e., one stream of IQ data for the dual-carrier horizontal polarization signal (C1H / C2H signal) and another stream of IQ data for the dual-carrier vertical polarization signal (C1V / C2V signal) (via a demultiplexer or similar element (1508)). As shown generally by elements 1510 and 1520 (shown as "C1H / C2H" and "C1V / C2"), the horizontal and vertical frequency domain components for the sub-carriers of each respective component carrier C1 and C2 are further split and processed by four separate iFFT / CP elements to generate four separate discrete-time domain baseband data signals (two for each component carrier, two for each signal polarization), which are then time-wise paired and added, and the results of the signal addition (C1H + C2H, and C1V + C2V) are provided to the respective TX / DPA elements 1512 and 1522 to generate the modulated and amplified analog RF signal C1H / C2H for the horizontal signal port of transceiver IC 1504a and the amplified analog RF signal C1V / C2V for the vertical signal port of transceiver IC 1504a.

[0197] Unlike the embodiment of FIG. 14, packet data related to the other two carriers C3 and C4 received at port 1506 is transferred to a second transceiver IC (1504b) for processing. More specifically, the first transceiver IC may be configured to transfer IQ data packets for carriers C3 and C4 for each polarization, i.e., C3H, C4H, C3V, and C4V, to the second transceiver IC 1504b for processing. In some embodiments, different carrier packets addressed to either the first or second transceiver IC may include a unique carrier ID and may be addressed to each transceiver IC via one or more identification fields within the IQ data packet. Accordingly, the first transceiver may be configured to inspect incoming packets to determine which packets are addressed to the first transceiver IC and which packets should be transferred to the second transceiver IC.

[0198] In some embodiments, the first transceiver IC may transfer these packets serially to its second serial communication port 1530, which is serially interconnected via internal path 1532 to the serial communication port 1546 within the second transceiver IC (i.e., the second transceiver IC) via serial data link 1544. The second transceiver IC performs signal processing similar to that of the first transceiver IC (with respect to carriers C3 and C4) via elements 1548, 1550, 1556, 1552, and 1558 to output amplified analog RF signals C3H / C4H and C3V / C4V on two signal ports of transceiver IC 1504b.

[0199] Subsequently, (i) the two signals C1H / C2H and C3H / C4H for horizontal polarization are combined via an adder element 1514 to generate a combined signal 1518 that is provided to a radiating element 1526 via a first SPDT for transmission, and (ii) the two signals C1V / C2V and C3V / C4V for vertical polarization are combined via an adder element 1524 to generate a combined signal 1528 that is provided to a radiating element 1516 via a second SPDT for transmission.

[0200] Similarly, in the receiving direction, a data-modulated 4-carrier dual-polarization RF uplink signal can be received by two serially-connected transceiver ICs (1504a and 1504b) via radiating elements 1516 and 1526 that respectively correspond to the horizontal and vertical signal ports. Similar to the case of FIG. 14, for ease of explanation and merely by way of example, it is assumed that the analog RF signals C1H / C2H / C3H / C4H (1518) and the analog RF signals C1V / C2V / C3V / C4V (1628) are the current received uplink signals.

[0201] As shown in FIG. 15, the RF signal (1518) received by the horizontal polarization antenna element 1516 is supplied via respective SPDTs to the RX / LNA element 1538 in the first transceiver IC (1504a), and the RF signal (1528) received by the vertical polarization antenna element is supplied via respective SPDTs to the RX / LNA element 1570 in the second transceiver IC (1504b). Similar to the process shown in FIG. 14, each of the respective horizontal receive RX / LNA chains and vertical receive RX / LNA chains is configured to perform signal conversion from RF to baseband, signal conversion from analog to digital, etc., to output a first 4-carrier discrete time domain signal on the horizontal receive path and a second 4-carrier discrete time domain signal on the vertical path. Thus, in some embodiments, the output of the RX / LNA 1538 element can be the first 4-carrier discrete time domain signal on the horizontal polarization receive path, and the output of the RX / LNA element 1570 can be the second 4-carrier discrete time domain signal on the vertical polarization receive path. Note that in this embodiment, each transceiver IC processes four component carriers in one of the RX / LNA elements, and the other RX / LNA elements (1542, 1576) are disabled.

[0202] Referring back to the signal processing shown in FIG. 15, with respect to horizontal polarization, the output of the RX / LNA element 1538 includes discrete time domain baseband data signals 1536 and 1540 that are processed on two separate signal processing branches, where (i) carriers C1 and C2, shown as C1H / C2H (1536), are processed on one branch, and (ii) carriers C3 and C4, shown as C3H / C4H (1540), are processed on the other branch. Similarly, with respect to vertical polarization, the output of the RX / LNA element 1570 can include discrete time domain baseband data signals 1568 and 1574 to be processed on two separate signal processing branches, where (i) carriers C1 and C2, shown as C1V / C2V (1568), are processed on one branch, and carriers C3 and C4, shown as C3V / C4V (1574), are processed on the other branch.

[0203] The various principles of the operation of the received signal processing (including the conversion from the time-domain signal to the frequency-domain IQ data) are similarly applicable to the receive path of the arrangement of FIG. 15 as described in connection with FIG. 14 and will not be repeated in detail here. For purposes of illustration, in some embodiments, the received C1H / C2H signals (1536) for horizontal polarization are separated from C3H / C4H by time-domain FIR filtering, notch filtering, etc., and further separated into the constituent carrier C1H and C2H by time-domain filtering in one signal path to remove the C2H component to obtain C1H. Another path includes complex multiplication via a numerically controlled oscillator (NCO) frequency to shift the C2H component to the desired baseband signal, followed by additional filtering to remove the residual component of C1H. Thus, one transceiver IC1504a can receive four component carriers on a single receive RF signal port (e.g., via either one of the H-polarization antenna elements or the V-polarization antenna elements) and decompose the signal into four separate component carriers. In the illustrated embodiment, the four separate component carriers C1H, C2H, C3H, C4H are all separated using time-domain signal processing and then transmitted to four separate FFT operations (in some embodiments, all executed by a single DSP processor) for the conversion from the time domain to the frequency domain. Similarly, the C1V / C2V / C3V / C4V signals (1528) for vertical polarization, first processed by a single LNA and ADC1570, are processed through filtering, frequency offset (i.e., NCO modulation), and further filtering and adjusted for four separate FFT operations for the conversion from the time domain to the frequency domain. Although not explicitly shown, other time-frequency pre-conversion signal processing may include, for example, sample rate conversion, filtering, cyclic prefix detection and removal, etc., as described above.

[0204] Following the time-frequency domain conversion, elements 1534 and 1566 (on the horizontal and vertical paths respectively) then route and / or store IQ data points for sub-carriers associated with the individual component carriers C1, C2, C3, and C4 for each respective polarization (H or V). The frequency domain IQ data for all four component carriers can be further combined into a packet data stream (e.g., eight packet data streams, or four combined V / H packet streams) for transmission (e.g., to a beamformer processor) via the bidirectional serial link 1502 from two serially connected transceiver ICs (1504a and 1504b) for each polarization.

[0205] More specifically, in this regard, the frequency domain IQ packet data corresponding to the vertical polarization signal for the four carriers C1, C2, C3, and C4 can be received at the serial communication port 1562 of the second transceiver IC (1504b). The second transceiver IC can be configured to transfer those data packets serially to another serial communication port 1530 that is serially interconnected via the internal link 1564 to the serial communication port 1546 within the first transceiver IC (i.e., the first transceiver IC) via the serial data link 1544. Although not explicitly shown in FIG. 15, in some embodiments, by multiplexing the packet data corresponding to the vertical polarization signals of the four carriers C1, C2, C3, and C4 received at the serial communication port 1530, the packet data output by the element 1534 (for the horizontal polarization of all four carriers C1, C2, C3, and C4) can be combined to generate an IQ data packet stream that is transmitted to the serial data link transceiver 1506 on the data link 1532 for communication to the beamformer processor via the serial communication link 1502.

[0206] In the embodiment of FIG. 15, DL and UL signal processing is not executed symmetrically across the serially connected transceiver ICs. DL transmission signal processing is split according to component carriers (both the H and V polarities of C1 and C2 are processed by transceiver IC 1504a, and both the polarities of C3 and C4 are processed by transceiver IC 1504b), while UL reception signal processing is split according to polarity (all the H polarities of C1, C2, C3, and C4 are processed by transceiver IC 1504a, and all the V polarities of C1, C2, C3, and C4 are processed by transceiver IC 1504b). It should be noted that this has the advantage of relaxing the bandwidth requirements in the transmission modulator so as to span only two component carriers (C1, C2 processed by transceiver IC 1504a and C3, C4 processed by transceiver IC 1504b) on the transmission side, while on the reception side, it has the advantage of not splitting the received signal into two different signal ports of two different transceiver ICs before processing by downconversion and sampling by the ADC. Thus, in the described embodiment, a dual-polarization four-component carrier system can be implemented by using the wideband capabilities of the receiver part of the transceiver IC to process a received signal having a four-component carrier bandwidth while relaxing the transmission modulator / amplifier bandwidth requirements to accommodate a transmission signal having a bandwidth of only two component carriers.

Claims

Claim 1 An apparatus comprising: a primary beamformer processor; and a plurality of secondary beamformer processors connected to the primary beamformer processor, each of the plurality of secondary beamformer processors being associated with a respective region of an antenna array and further associated with a respective one of a plurality of beamforming submatrices, each beamforming submatrix including beamforming coupling weights associated with antenna elements within the respective region of the antenna array, the plurality of secondary beamformer processors; a plurality of sets of transceiver integrated circuits (ICs) connected to the plurality of distributed secondary beamformer processors, each set of transceiver ICs being connected to a corresponding one of the plurality of secondary beamformer processors and disposed within the respective region of the antenna array associated with the corresponding secondary beamformer processor, each secondary beamformer processor being configured to receive a respective set of frequency domain IQ data points and form a respective plurality of sets of beamformed frequency domain IQ data points using the respective set of frequency domain IQ data points and the respective beamforming submatrices. Claim 2 The apparatus of claim 1, wherein the primary beamformer processor is configured as a transmit beamformer processor, the secondary beamformer processors are configured as secondary transmit beamformer processors having beamforming submatrices for transmit beamforming, the frequency domain IQ data packets are user data layers, and the secondary transmit beamformer generates beamformed frequency domain IQ data points. Claim 3 The primary beamformer processor is configured as a primary reception beamformer processor, the plurality of secondary reception beamformer processors are configured as secondary reception beamformer processors, and are composed of beamforming partial matrices for reception beamforming. The frequency domain IQ data packet is frequency domain IQ data received from a transceiver IC. The secondary transmission beamformer is configured to generate partial beamforming frequency domain IQ data points. The primary reception beamformer processor is configured to combine corresponding sets of received partial beamforming frequency domain IQ data points received from all the secondary reception beamformer processors to form a plurality of complete beamforming frequency domain subcarrier IQ user data layers. The apparatus according to claim 1.

4. The primary reception beamformer processor is configured to divide a reception beamforming matrix of beamforming combination weights into the plurality of reception beamforming partial matrices, and transmit each respective reception beamforming partial matrix to a corresponding one of the plurality of secondary reception beamformer processors. The apparatus according to claim 3.

5. Each distributed secondary reception beamformer processor is further configured to form respective plural sets of partial beamforming frequency domain IQ data points by applying the reception beamforming combination weights of the respective reception beamforming partial matrices to the respective sets of frequency domain IQ data points. The apparatus according to claim 3.

6. The transceiver IC is serially connected to a transceiver IC sub-array. The apparatus according to claim 1.

7. A method, comprising: In each of a plurality of distributed secondary receive beamformer processors connected to a primary receive beamformer processor, receiving each set of frequency domain IQ data points from a corresponding one of a plurality of sets of transceiver integrated circuits (ICs), wherein the plurality of secondary receive beamformer processors are associated with respective regions of an antenna array associated with each one of a plurality of receive beamforming submatrices, each receive beamforming submatrix includes receive beamforming coupling weights associated with antenna elements within the respective region of the antenna array, and the corresponding set of transceiver ICs are disposed within the respective regions of the antenna array associated with the secondary receive beamformer processor, and forming, by each secondary receive beamformer processor, a plurality of sets of received partial beamforming frequency domain IQ data points using each set of the frequency domain IQ data points and the respective receive beamforming submatrices, and transmitting, by each distributed secondary receive beamformer processor, the respective plurality of sets of received partial beamforming frequency domain IQ data points to the primary receive beamformer processor, a method comprising.

8. The method of claim 7, further comprising combining, by the primary receive beamformer processor, corresponding sets of received partial beamforming frequency domain IQ data points received from all of the plurality of distributed secondary receive beamformer processors to form a plurality of frequency domain IQ user data layers.

9. The method of claim 7, further comprising partitioning, by the primary receive beamformer processor, a receive beamforming matrix of beamforming coupling weights into the plurality of receive beamforming submatrices and transmitting each respective receive beamforming submatrix to a corresponding one of the plurality of secondary receive beamformer processors.

10. A method comprising In a primary transmission beamforming processor, dividing a transmission beamforming matrix of beamforming combining weights into a plurality of transmission beamforming submatrices, each transmission beamforming submatrix including beamforming combining weights associated with antenna elements within respective regions of an antenna array, providing (i) the transmission beamforming submatrices and (ii) one or more frequency domain IQ (FDIQ) user data layers to a plurality of secondary transmission beamformer processors connected to the primary transmission beamforming processor, in each secondary transmission beamformer processor, calculating a beamforming transmission FDIQ data packet, transmitting the beamforming transmission FDIQ data packet to a plurality of sets of transceiver integrated circuits, each set of transceiver integrated circuits being disposed within a respective one of the regions of the array panel and connected to a corresponding secondary transmission beamformer processor among the plurality of secondary transmission beamformer processors, the method comprising: **Claim 11** The method according to claim 10, wherein the primary transmission beamformer processor is configured to transmit the transmission beamforming submatrices to corresponding secondary transmission beamformer processors and to transmit a frequency domain subcarrier IQ user data layer to all of the distributed secondary transmission beamformer processors. **Claim 12** The method according to claim 11, wherein each distributed secondary transmission beamformer processor is configured to receive the frequency domain subcarrier IQ user data layer and the respective transmission beamforming submatrices, calculate a set of beamforming frequency domain IQ data points by applying the respective beamforming weights of the beamforming submatrices to the IQ user data layer, and distribute the set of beamforming frequency domain IQ data points to respective sets of transceiver ICs disposed in a transceiver IC subarray located within a respective region of the secondary beamformer processor.

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