Display panel and display device

Abstract

Regarding the technical field of display, a display panel and a display device are provided. The display area of the display panel includes a main display area and a sub-display area. The driving backplane included in the display panel includes a substrate, a plurality of pixel circuits, and a first power bus connected to a second electrode. One first electrode is connected to one pixel circuit. The driving backplane includes a substrate and a plurality of circuit units. The circuit units include two pixel circuits distributed along the row direction. The light-emitting element includes a first electrode, a light-emitting layer, and a second electrode. One first electrode is connected to one pixel circuit. The line group includes two data lines distributed along the row direction. The two data lines of one line group are connected to the two columns of pixel circuits of one column of circuit units. Each data line includes a plurality of first data lines and second data lines. The first data line extends from the main display area to the extraction area. The second data line is located in the sub-display area. The power line extends from the display area to the extraction area along the column direction. The two columns of pixel circuits of one column of circuit units are connected to one power line.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and specifically, to a display panel and a display device.

Background Art

[0002] OLED (organic electroluminescence diode) display panels have advantages such as self-luminescence, wide color gamut, high contrast, flexibility, and high response flexibility, and have future potential for a wide range of applications. However, current display panels consume a large amount of power.

[0003] Note that the information disclosed in the above background art part is only used to enhance the understanding of the background of the present disclosure, and may include information that does not constitute prior art known to those skilled in the art.

Summary of the Invention

[0004] The present disclosure provides a display panel and a display device.

[0005] One aspect of the present disclosure provides a display panel including a display area and a peripheral area outside the display area. The peripheral area includes a lead-out area extending along a direction away from the display area. The lead-out area has a binding portion. The display area and the lead-out area are distributed along the column direction. The display area includes a main display area and sub-display areas provided on both sides of the main display area along the row direction. The display panel includes a driving backplane and a plurality of light-emitting elements provided on one side of the driving backplane. The driving backplane includes a substrate and a plurality of circuit units located on one side of the substrate. The circuit units include two pixel circuits distributed along the row direction. The two pixel circuits of the same circuit unit are symmetrically provided. The light-emitting element includes a first electrode laminated along a direction away from the driving backplane, a light-emitting layer, and a second electrode. One of the first electrodes is connected to one of the pixel circuits. including the drive backplate, the first power bus, a plurality of data lines, a plurality of power lines, a plurality of first connection lines, and a plurality of second connection lines; The first power bus is provided in the peripheral region and connected to the second electrode. The plurality of data lines extend along the column direction and are divided into a plurality of line groups distributed in the row direction. Each line group includes two of the data lines distributed in the row direction. The two data lines of one line group are respectively connected to two rows of the pixel circuits of one column of the circuit units. Each data line includes a plurality of first data lines and second data lines. The first data line extends from the main display area to the extraction area and is connected to the binding portion. The second data line is located in the sub-display area. The plurality of power lines extend from the display area to the extraction area along the column direction. Two rows of the pixel circuits of one column of the circuit units are connected to one of the power lines. The plurality of first connection lines extend along the row direction. At least some of the first connection lines include a first relay line and a first dummy line provided at intervals. The first relay line extends from the sub-display area to the main display area. The plurality of second connection lines extend along the column direction. One of the second connection lines is located between two adjacent line groups. The data lines of two adjacent line groups are provided symmetrically with respect to the second connection line between the two line groups. At least some of the second connection lines include a second relay line and a second dummy line provided at intervals. The second relay line extends from the main display area to the extraction area and is connected to the binding portion. One of the first relay lines is connected to one of the second relay lines to form one relay line. One of the second data lines is connected to the binding portion via at least one of the relay lines. The first connection line is provided insulated from the data line. At least some of the first dummy lines are connected to at least some of the second dummy lines and are connected to the first power bus.

[0006] In an exemplary embodiment of the present disclosure, the first relay line and the first dummy line are provided in the same layer on the side of the power line closer to the substrate, and the second relay line and the second dummy line are provided in the same layer on the side where the first connection line is away from the substrate. Among the same first connection lines, the adjacent first relay line and the first dummy line are provided with a gap through a break, and among the same second connection lines, the adjacent second relay line and the second dummy line are provided with a gap through a break. At least a part of the breaks of the first connection line overlap with the second connection line or the power line.

[0007] In an exemplary embodiment of the present disclosure, the first connection line is located on the side of the data line closer to the substrate.

[0008] In an exemplary embodiment of the present disclosure, at least a part of the breaks overlap with some of the first electrodes.

[0009] In an exemplary embodiment of the present disclosure, the display panel further includes a touch layer. The touch layer is provided on the side where the light-emitting element is away from the substrate, includes a touch electrode layer, the touch electrode layer has a network structure surrounded by a plurality of channel lines, and at least a part of the breaks overlap with some of the channel lines.

[0010] In an exemplary embodiment of the present disclosure, the break of the first connection line is the first break, and the break of the second connection line is the second break. Some of the first breaks overlap with the second connection line, and some other of the first breaks overlap with the power line. The second break overlaps with the first electrode or the channel line.

[0011] In an exemplary embodiment of the present disclosure, some of the first relay lines continuously extend to the peripheral region along the row direction, and some of the second relay lines continuously extend to the extraction region along the column direction.

[0012] In an exemplary embodiment of the present disclosure, the second connection line is provided on the same layer as the data line and the power line, and is located on the side away from the substrate where the first connection line is located. The driving backplate further includes an array-distributed first relay portion and an array-distributed second relay portion, and the first relay portion, the second relay portion, and the first connection line are provided on the same layer. One row of the first relay portions overlaps with one of the data lines, and one of the data lines is respectively connected to each of the pixel circuits in one row of the pixel circuits through each of the first relay portions overlapping therewith. One of the first relay lines is connected to one of the second data lines through one of the first relay portions. One row of the second relay portions overlaps with one of the second connection lines, and one of the second relay lines is connected to one of the first relay lines through one of the second relay portions.

[0013] In an exemplary embodiment of the present disclosure, at least a part of the second dummy lines is connected to at least a part of the first dummy lines through at least a part of the second relay portions.

[0014] In an exemplary embodiment of the present disclosure, the first relay portion is connected to the data line through a first contact hole, and the second relay portion is connected to the second connection line through a second contact hole. Each of the first contact holes and the second contact holes is divided into a plurality of hole groups distributed in an array. One row of the hole groups is located between the power lines connected to two adjacent circuit units. One of the hole groups includes two of the first contact holes and one of the second contact holes, and the two of the first contact holes are provided symmetrically with respect to the second contact hole.

[0015] In one exemplary embodiment of the present disclosure, two of the first contact holes and one of the second contact holes of the same hole group are distributed in a triangular shape.

[0016] In one exemplary embodiment of the present disclosure, the driving backplate further includes a first electrode relay portion distributed in an array and a second electrode relay portion distributed in an array. The first electrode relay portion is provided in the same layer as the first relay portion and the second relay portion. The second electrode relay portion is located on the side where the first electrode relay portion is away from the substrate. One of the first electrode relay portions overlaps with one of the second electrode relay portions and is connected via a third contact hole. The first electrode is connected to the pixel circuit via the second electrode relay portion, the third contact hole, and the first electrode relay portion. The hole group further includes the third contact hole. In the same hole group, the first contact hole is connected to the pixel circuit in the (n + 1)-th row, the third contact hole is connected to the pixel circuit in the n-th row, and two of the third contact holes are located on both sides of the second contact hole and are distributed along the column direction.

[0017] In one exemplary embodiment of the present disclosure, the pixel circuit includes a driving transistor, a writing transistor, a compensation transistor, a first reset transistor, a second reset transistor, a third reset transistor, a first light emission control transistor, a second light emission control transistor, and a storage capacitor. The driving backplate further includes a first reset control line, a first reset signal line, a second reset control line, a second reset signal line, a third reset signal line, a first scanning line, a second scanning line, and a light emission control line. The gate of the driving transistor is connected to the first node, the first pole is connected to one of the power supply lines via the first light emission control transistor, the second pole is connected to the first electrode of one of the light emitting elements via the second light emission control transistor, and the gates of the first light emission control transistor and the second light emission control transistor are connected to the light emission control line. The gate of the first reset transistor is connected to the first reset control line, the first pole is connected to the first reset signal line, and the second pole is connected to the first node. The gate of the writing transistor is connected to the first scanning line, the first pole is connected to one of the data lines, and the second pole is connected to the first pole of the driving transistor. The gate of the compensation transistor is connected to the second scanning line, the first pole is connected to the second pole of the driving transistor, and the second pole is connected to the first node. The gates of the two reset transistors are connected to the second reset control line, the first poles are connected to the second reset signal line, and the second poles are connected to the first electrode. The gate of the third reset transistor is connected to the second reset control line, the first pole is connected to the third reset signal line, and the second pole is connected to the first pole of the driving transistor. The first electrode plate of the storage capacitor is connected to the power supply line, and the second electrode plate is connected to the first node. The first reset transistor and the compensation transistor are metal oxide transistors, and the driving transistor, the writing transistor, the second reset transistor, the third reset transistor, the first light emission control transistor, and the second light emission control transistor are polysilicon transistors.

[0018] In one embodiment of the present disclosure, the driving backplate further includes a first semiconductor layer, a first gate insulating layer, a first gate layer, a first insulating layer, a second gate layer, a second insulating layer, a second semiconductor layer, a second gate insulating layer, a third gate layer, a third insulating layer, a first source-drain layer, a first flat layer, a second source-drain layer, a second flat layer, a third source-drain layer, and a third flat layer. The first semiconductor layer is provided on one side of the substrate and includes channels of the driving transistor, the writing transistor, the second reset transistor, the third reset transistor, the first light emission control transistor, and the second light emission control transistor. The first gate insulating layer covers the first semiconductor layer. The first gate layer is provided on the surface of the first gate insulating layer away from the substrate and overlaps at least a part of the region of the first semiconductor layer. The first gate layer includes the second reset control line, the light emission control line, the first scanning line, and the first electrode plate. The first insulating layer covers the first gate layer. The second gate layer is provided on the surface of the first insulating layer away from the substrate and includes the second electrode plate that overlaps the first electrode plate. The second insulating layer covers the second gate layer. The second semiconductor layer is provided on the surface of the second insulating layer away from the substrate and includes channels of the first reset transistor and the compensation transistor. The second gate insulating layer covers the second semiconductor layer. The third gate layer is provided on the surface of the third gate insulating layer away from the substrate and overlaps at least a part of the region of the second semiconductor layer. The third gate layer includes the first reset control line, the first reset signal line, the second scanning line, and at least a part of the third reset signal line. The third insulating layer covers the third gate layer. The first source-drain layer is provided on the surface of the third insulating layer away from the substrate, and includes the second reset signal line and at least a part of the third reset signal line. The first flat layer is provided on the side of the first source-drain layer away from the substrate. The second source-drain layer is provided on the surface of the first flat layer away from the substrate, and includes the first connection line. The second flat layer covers the second source-drain layer. The third source-drain layer is provided on the surface of the second flat layer away from the substrate, and includes the data line, the power line, and the second connection line. The third flat layer covers the third source-drain layer, and the first electrode is provided on the surface of the third flat layer away from the substrate.

[0019] In an embodiment of the present disclosure, the second semiconductor layer includes an oxide active portion extending along the column direction, the oxide active portion is located between the first reset signal line and the third reset signal line, the first reset control line overlaps with the oxide active portion to form the first reset transistor, and the second reset control line overlaps with the oxide active portion to form the compensation transistor. The first source-drain layer includes a first connection portion, one end of the first connection portion is connected to the first electrode plate, and the other end is connected to the oxide active portion between the first reset transistor and the channel of the second reset control line. The driving backplate further includes a plurality of shield portions located in the second source-drain layer. One of the shield portions overlaps with the first connection portion of one of the pixel circuits and the channel of the compensation transistor, and is connected to the power line connected to the pixel circuit.

[0020] In an embodiment of the present disclosure, in a circuit unit having one of the shield portions and the first connection portion overlapping therewith, the two second electrode plates of the pixel circuit of the circuit unit are both connected in an overlapping manner with the shield portion.

[0021] In one exemplary embodiment of the present disclosure, the first source-drain layer includes a second connection portion and a third connection portion. The second connection portion is connected to the two second electrode plates, and one of the third connection portions is connected to one of the second electrode plates and the first pole of the first light-emitting control transistor.

[0022] In one exemplary embodiment of the present disclosure, in a circuit unit having a shield portion and a first connection portion overlapping therewith, two data lines connected to the circuit unit are located on both sides of the shield portion, and a power supply line connected to the circuit unit is located between the two data lines and is connected overlapping the shield portion.

[0023] In one exemplary embodiment of the present disclosure, in a circuit unit having one power supply line and a circuit unit connected thereto, the power supply line has protruding portions protruding on both sides along the row direction, and the two protruding portions respectively overlap with the channels of the first reset transistors of the two pixel circuits.

[0024] In one exemplary embodiment of the present disclosure, the first reset control line, the first reset signal line, the second reset control line, the second reset signal line, the third reset signal line, the first scanning line, the second scanning line, and the light-emitting control line connected to the pixel circuits in the same row all extend along the row direction and are distributed along the column direction. The first reset control line, the first scanning line, the second scanning line, the third reset signal line, the light-emitting control line, and the second reset control line are located between the first reset signal line and the second reset signal line. The first scanning line, the second scanning line, at least a part of the third reset signal line, and the light-emitting control line are located between the first reset control line and the second reset control line. The second scanning line is located between the first scanning line and the light-emitting control line. The second electrode plate is located between the second scanning line and at least a part of the third reset signal line. The light-emitting control line overlaps at least a part of the third reset signal line. The first reset signal line connected to the pixel circuit in the (n + 1)-th row overlaps with the second reset control line connected to the pixel circuit in the n-th row.

[0025] In one embodiment example of the present disclosure, the second reset signal line connected to the pixel circuit in the (n + 1)-th row overlaps with the first reset control line and the first scanning line connected to the pixel circuit in the n-th row at the same time.

[0026] In one embodiment example of the present disclosure, the third reset signal line includes a line body extending along the row direction and a line branch connected to the side of the line body close to the second reset signal line. The line body and the line branch are located in different layers. The line body is located between the second scanning line and the second reset control line, overlaps with the light emission control line, the line branch extends to between the second reset control line and the second reset signal line, and is connected to the first pole of the third reset transistor.

[0027] In one embodiment example of the present disclosure, the line body is located in the third gate layer, and the line branch is located in the first source-drain layer.

[0028] In one embodiment example of the present disclosure, one of the first reset signal lines overlaps with one of the first connection lines.

[0029] In one embodiment example of the present disclosure, the oxide active part has a capacitance part extending along the row direction. The capacitance part is connected between the first reset transistor and the channels of the compensation transistors, overlaps with the first scanning line, and is connected to the first connection part.

[0030] In one embodiment example of the present disclosure, the second gate layer further includes an auxiliary control line and an auxiliary scanning line extending along the row direction. The auxiliary control line is connected in overlap with the first reset control line, and the auxiliary scanning line is connected in overlap with the second scanning line.

[0031] One aspect of the present disclosure provides a display device including any of the above display panels.

[0032] It should be understood that the above general description and the detailed description below are merely exemplary and explanatory, and do not limit the present disclosure.

Brief Description of the Drawings

[0033] Here, the drawings are incorporated into the specification, showing embodiments that conform to the present disclosure, and are used to explain the principles of the present disclosure together with the specification. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings based on these drawings without creative labor.

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Embodiments for Carrying out the Invention

[0034] Next, with reference to the drawings, exemplary embodiments will be described in more detail. However, the exemplary embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein. In contrast, these embodiments are provided so that the present disclosure is comprehensive and complete, and can fully convey the concept of the exemplary embodiments to those skilled in the art. Since the same reference numerals in the drawings represent the same or similar structures, detailed descriptions will be omitted. Also, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0035] The terms "one", "a", "the", "said" and "at least one" are used to represent the existence of one or more elements / components / etc., and the terms "comprising" and "having" are used to mean open inclusion and mean elements / components / etc. that can exist in addition to the listed elements / components / etc. The terms "first", "second", "third", etc. are only used as marks and are not quantity limitations on the object.

[0036] The row direction X and the column direction Y in the present text are merely two perpendicular directions. In the drawings of the present disclosure, the row direction X may be the horizontal direction and the column direction Y may be the vertical direction, but not limited thereto. When the display panel rotates, the actual directions of the row direction X and the column direction Y may change.

[0037] The "overlap" of feature A and feature B in this specification means that the orthographic projection of feature A on the substrate and the orthographic projection of feature B on the substrate overlap at least partially.

[0038] As used herein, the “same layer” of Feature A and Feature B means that Feature A and Feature B may be formed simultaneously, and both are discontinuous or continuous different regions in the same film layer, and in the direction perpendicular to the substrate, both are not separated by other film layers. The “different layers” means that Feature A and Feature B are distributed at intervals in the direction perpendicular to the substrate, and both are separated by other film layers.

[0039] As used herein, “adjacent” Feature A means that there is no other Feature A between two Feature As.

[0040] Embodiments of the present disclosure provide a display panel. As shown in FIGS. 1 and 2, the display panel can have a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA can be a continuous or discontinuous annular area surrounding the display area AA. Here, the shape of the peripheral area WA is not particularly limited.

[0041] The peripheral area WA can include a lead-out area FA extending in a direction away from the display area AA. The display area AA and the lead-out area FA can be distributed along the column direction Y. The lead-out area FA has a binding portion PA. The binding portion PA includes a plurality of pads that can be coupled to a flexible circuit board, and can control the display area AA of the display panel to emit light to display an image through a control circuit board coupled to the flexible circuit board.

[0042] The display area AA can include a main display area MA and sub-display areas SA provided on both sides of the main display area MA along the row direction X. That is, there are two sub-display areas SA, which are arranged on both sides of the display area MA. For example, the shape of the display area AA may be a quadrilateral, and the four corners of this quadrilateral are fillets. The width of the sub-display area SA in the row direction X is not greater than the width of the fillet in the row direction X.

[0043] As shown in FIG. 3, the display panel can include a driving backplane BP having a driving circuit and a plurality of light-emitting elements LD. Each light-emitting element LD is provided on one side of the driving backplane BP and can be located within the display area AA. Light-emitting elements LD are provided in both the main display area MA and the sub-display area SA. The light-emitting element LD can include a first electrode ANO laminated in a direction away from the driving backplane BP, a light-emitting layer EL, and a second electrode CAT. The light-emitting element LD may be an OLED (organic light-emitting diode), and of course, it may also be a Micro LED (micro light-emitting diode), a Mini LED (sub-millimeter light-emitting diode), or a light-emitting element such as a QLED (quantum dot diode).

[0044] As shown in FIG. 3, the first electrode ANO may be provided on one side of the driving backplane BP. The light-emitting layer EL may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer laminated in a direction away from the driving backplane BP. Each light-emitting element LD can share the second electrode CAT. That is, the second electrode CAT has a continuous all-layer structure. The second electrode CAT extends to the peripheral region and can receive the first power signal VSS. The first electrodes ANO are distributed in an array to ensure that each light-emitting element LD can emit light independently. Also, in order to limit the light-emitting range of the light-emitting element LD and prevent crosstalk, a pixel definition layer PDL can be provided on the surface where each first electrode ANO is provided, and an opening for exposing the first electrode ANO is provided therein. The light-emitting layer EL is laminated with the first electrode ANO within the opening.

[0045] Each light-emitting element LD can share at least the light-emitting material layer so that the emission colors of the respective light-emitting elements LD are the same. In this case, in order to achieve color display, a color filter layer is provided on the side away from the substrate SU of the light-emitting element LD, and color display can be achieved by the filter portions corresponding to the respective light-emitting elements LD in the color filter layer. Of course, the light-emitting material layers of the respective light-emitting elements LD may be independent, and the light-emitting element LD can directly emit monochromatic light, and color display can be achieved by the different emission colors of the different light-emitting elements LD.

[0046] Also, as shown in FIG. 3, the display panel can also include a sealing layer TFE that covers each light-emitting element LD, and thin-film encapsulation can be employed, and can include a first inorganic layer, an organic layer, and a second inorganic layer. Here, the first inorganic layer can cover each light-emitting element, that is, the first inorganic layer can cover the surface of the second electrode CAT away from the substrate SU. The material of the first inorganic layer can include inorganic insulating materials such as silicon nitride and silicon oxide. The organic layer may be provided on the surface of the first inorganic layer away from the substrate Su, and the boundary of the organic layer can be limited inside the boundary of the first inorganic layer by the barrier dams located in the peripheral region WA. The material of the organic layer can use organic materials such as resins.

[0047] The second inorganic layer can cover the organic layer and the first inorganic layer not covered by the organic layer, shield the intrusion of water and oxygen by the second inorganic layer, and planarization can be achieved by the organic layer having fluidity (during the manufacturing process). The material of the second inorganic layer can include inorganic insulating materials such as silicon nitride and silicon oxide.

[0048] Also, as shown in FIG. 3, the display panel may include other film layers such as a touch layer TSP and a transparent cover provided on the side where the sealing layer TFE is away from the substrate SU, which will not be described in detail here.

[0049] Taking the example that the touch layer TPS adopts a mutual capacitance touch structure, the touch layer TPS can include a plurality of first touch electrodes Tx and a plurality of second touch electrodes Rx. Each first touch electrode Tx can be distributed at intervals along the row direction X. One first touch electrode Tx can include a plurality of first electrode blocks Txc distributed at intervals along the column direction Y and a relay bridge BR connecting two adjacent first electrode blocks Txc. Each second touch electrode Rx can be distributed at intervals along the column direction Y. One second touch electrode Rx includes a plurality of second electrode blocks Rxc connected in series along the row direction X. One relay bridge BR intersects with one second touch electrode Rx and is arranged in an insulated manner. One of the first touch electrode Tx and the second touch electrode Rx can be used as a transmitting electrode, and the other can be used as a receiving electrode, and both are connected to the surrounding touch driving circuit.

[0050] Furthermore, the touch layer can include a barrier layer TLD, a bridge layer, a spacer layer SEP, a touch electrode layer TMB, and a protection layer TOC. Here, The barrier layer TLD can be provided on the surface away from the driving backplate BP of the sealing layer TFE. Its material can use insulating materials such as silicon nitride and silicon oxide, and is not particularly limited here. The relay layer can be provided on the surface where the barrier layer TLD is away from the driving backplate BP and includes a plurality of array-distributed transfer bridges BR. The bridge layer can use metal or other conductive materials and includes each transfer bridge BR. The spacer layer SEP can cover the bridge layer. The material of the spacer layer SEP can use insulating materials such as silicon nitride and silicon oxide, and is not particularly limited here. The touch electrode layer TMB is provided on the surface where the spacer layer SEP is away from the driving backplate BP and can include the first electrode block Txc and the second touch electrode Rx described above.

[0051] Furthermore, as shown in FIG. 25, the touch electrode layer TMB of the touch layer TSP can adopt a mesh structure having a plurality of meshes surrounded by a plurality of channel lines TL. One mesh can correspond to one or more light-emitting elements LD, that is, the orthographic projection of one or more light-emitting elements LD onto the substrate SU can be within the orthographic projection of the mesh onto the substrate SU, and the channel lines TL can be prevented from shielding the light-emitting elements LD.

[0052] As shown in FIG. 3, it can be connected to the light-emitting element LD, and each light-emitting element LD can emit light independently. Specifically, the driving backplate BP can include a substrate SU and a driving circuit located on one side of the substrate SU. The driving circuit includes a plurality of pixel circuits PC and peripheral circuits. Each pixel circuit PC can be arranged within the display area AA and may be connected to the first electrode ANO of the light-emitting element LD. Of course, a part of some pixel circuits PC may be arranged and exist in the peripheral area WA.

[0053] As shown in FIG. 2, the peripheral circuit is located within the peripheral area WA. The peripheral circuit can include a first power supply bus VSL and a second power supply bus BVDL. The second power supply bus BVDL is connected to the first electrode ANO of the light-emitting element LD through the pixel circuit PC, applies a second power supply signal VDD to the pixel circuit PC. The first power supply bus VSL is connected to the second electrode CAT of the light-emitting element LD, applies a first power supply signal VSS to the second electrode CAT, and controls the current passing through the light-emitting element LD by controlling the pixel circuit PC, thereby controlling the luminance of the light-emitting element LD. The peripheral circuit can include a gate driving circuit, a light-emitting control circuit, etc. Of course, it can also include other circuits not particularly limited to the specific structure of the peripheral circuit.

[0054] Each pixel circuit PC can include a plurality of transistors and capacitors. The channels of each transistor can be arranged in the same layer and are all semiconductor materials such as polysilicon. These are pixel circuits such as 3T1C, 7T1C, 8T1C, etc. Here, nTmC means that one pixel circuit PC includes n transistors (represented by the alphabet "T") and m capacitors (represented by the alphabet "C"). The number of pixel circuits PC may be plural, and the array distribution is in multiple rows and multiple columns. One pixel circuit PC can connect to one light-emitting element LD. Of course, there may be a case where one pixel circuit PC connects to a plurality of light-emitting elements LD. Here, the one-to-one connection between the pixel circuit PC and the light-emitting element LD will be taken as an example for explanation.

[0055] Next, the pixel circuit with an 8T1C structure will be described as an example.

[0056] As shown in FIGS. 4 to 11, the transistors of the pixel circuit PC include a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, a third reset transistor T8, and a storage capacitor Cst. Each transistor includes a gate, a first pole, and a second pole, and the first pole and the second pole can be turned on or off by applying a control signal to the gate. The storage capacitor Cst includes a first electrode plate Cst1 and a second electrode plate Cst2.

[0057] As shown in FIG. 4, the gate of the first light-emitting control transistor T5 is for inputting a light-emitting control signal EM, the first pole is for inputting a second power supply signal VDD, and the second pole is connected to the first pole of the driving transistor T3. The gate of the driving transistor T3 is connected to the first node N1, the second pole and the first pole of the second light-emitting control transistor T6 are connected to the second node N2, the second pole of the second light-emitting control transistor T6 is connected to the first electrode ANO of one light-emitting element LD, and the gate of the second light-emitting control transistor T6 is used for inputting a light-emitting control signal EM.

[0058] The gate of the first reset transistor T1 is used to input the first reset control signal RE1, the first pole is used to input the first reset signal VI1, and the second pole is connected to the first node N1.

[0059] The gate of the write transistor T4 is for inputting the first scan signal Gate1, the first pole is used for inputting the data signal DA, and the second pole, the first pole of the drive transistor T3, and the second pole of the first light emission control transistor T5 are connected to the third node N3.

[0060] The gate of the compensation transistor T2 is used to input the second scan signal Gate2, the first pole is connected to the second node N2, and the second pole is connected to the first node N1.

[0061] The gate of the second reset transistor T7 is used to input the second reset control signal RE2, the first pole is used to input the second reset signal VI2, and the second pole, the second pole of the second light emission control transistor T6, and the first electrode ANO are connected to the fourth node N4.

[0062] The gate of the third reset transistor T8 is used to input the second reset control signal RE2, the first pole is used to input the third reset signal VI3, and the second pole is connected to the third node N3.

[0063] The first electrode plate Cst1 of the storage capacitor Cst is used to input the second power supply signal VDD, and the second electrode plate Cst2 is connected to the first node N1.

[0064] Next, the operation principle of the above pixel circuit will be described.

[0065] In the reset stage t1, the first reset transistor T1 can be turned on by the first reset control signal RE1, and the first reset signal VI1 can be written to the first node N1. At the same time, the second reset transistor T7 and the third reset transistor T8 are turned on by the second reset control signal RE2, the second reset signal VI2 is written to the fourth node N4, and the third reset signal VI3 is written to the third node N3. Thereby, the gate, the first pole, and the first electrode ANO of the driving transistor T3 can be reset.

[0066] In the writing stage t2, the writing transistor T4 and the compensation transistor T2 are turned on by the first scanning signal Gate1 and the second scanning signal Gate2, and the data signal DA is written to the first node N1 through the third node N3 and the second node N2 until the potential reaches Vdata + vth, where Vdata is the voltage of the data signal DA and Vth is the threshold voltage of the driving transistor T3. The first scanning signal Gate1 and the second scanning signal Gate2 may be the same signal or two synchronized signals. Also, the first scanning signal Gate1 and the second scanning signal Gate2 may be high-frequency signals, which is advantageous for reducing the load of the source signal of the driving transistor T3.

[0067] Emission stage t3: The first emission control transistor T5 and the second emission control transistor T6 are turned on by the emission control signal EM, the driving transistor T3 is turned on by the voltage Vdata + Vth stored in the storage capacitor Cst and the second power supply signal VDD, and the light-emitting element LD is caused to emit light by the second power supply signal VDD and the first power supply signal VSS. In this process, the first pole of the driving transistor T3 is used as the source and the second pole is used as the drain.

[0068] The current of the output of the driving transistor T3 satisfies the following equation: I = (μWCox / 2L)(Vgs - Vth) 2 Here, I is the output current of the driving transistor T3, μ is the carrier mobility, Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor T3, L is the channel length of the driving transistor T3, Vgs is the gate-source voltage difference (voltage difference between the gate and the source) of the driving transistor T3, and Vth is the threshold voltage of the driving transistor T3.

[0069] Based on the formula for the output current of the driving transistor T3 above, when the gate voltage Vdata + Vth and the source voltage VDD of the driving transistor T3 in the pixel circuit of the present disclosure are introduced into the above formula, the output current I of the driving transistor T3 = (μWCox / 2L)(Vdata + Vth - VDD - Vth) 2 That is. It can be seen that the output current of this pixel circuit is independent of the threshold voltage Vth of the driving transistor T3 and is only related to Vdata. Thereby, the influence of the threshold voltage of the driving transistor T3 on its output current is eliminated, and the control of the output current is realized only by the voltage Vdata of the data signal DA, and the luminance of the light-emitting element LD can be controlled.

[0070] Note that the above-described third reset transistor T8 and the first reset transistor T1 can be turned on and off synchronously. That is, the third reset signal VI3 and the first reset signal VI1 can be input synchronously. In the reset stage t1, the gate and the first pole of the driving transistor T3 can be reset via the first reset signal VI1 and the third reset signal VI3. That is, the gate-source voltage difference of the driving transistor T3 can be reset, which is advantageous for reducing the influence of the hysteresis effect of the driving transistor T3 on the current of the driving transistor T3 and improving the afterimage phenomenon. Of course, the third reset signal VI3 and the first reset signal VI1 may be input asynchronously, but it is necessary to complete the reset before the writing stage t2.

[0071] Each transistor in the pixel circuit described above can use a polycrystalline silicon transistor in which the channel of the transistor, such as a P-type low-temperature polycrystalline silicon transistor or an N-type low-temperature polycrystalline silicon transistor, is polysilicon. Of course, a metal oxide transistor, that is, the channel of the transistor may be a metal oxide such as indium gallium zinc oxide. Here, when a high level is input to the gate of the P-type low-temperature polycrystalline silicon transistor, it turns off, and when a low-level signal is input, it turns on. When a low level is input to the gate of the N-type low-temperature polycrystalline silicon transistor, it turns off, and when a high-level signal is input, it can turn on. The metal oxide transistor may be an N-type metal oxide transistor that can turn on at a high gate input level and turn off at a low level.

[0072] In some embodiments of the present disclosure, the above-described 8T1C pixel circuit can adopt LTPO (LTPS + Oxide) technology. Specifically, the driving transistor T3, the writing transistor T4, the second reset transistor T7, the third reset transistor T8, the first light emission control transistor T5, and the second light emission control transistor T6 can adopt P-type low-temperature polycrystalline silicon transistors, and the first reset transistor T1 and the compensation transistor T2 can use N-type metal oxide transistors. Since the P-type low-temperature polycrystalline silicon transistor has a high carrier mobility, it is advantageous for realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. A high carrier mobility can be obtained, and the response speed can be increased. At the same time, leakage can be reduced by the N-type metal oxide transistor.

[0073] All signals input to the above pixel circuit can be transmitted by wiring. The wiring for transmitting each of the above signals will be described below: As shown in FIGS. 5 to 11, the driving backplate BP may include a plurality of row wirings that at least partially extend along the row direction X. Any of the row wirings may be connected to a pixel circuit of one row. These row wirings may include a first reset control line REL1, a first reset signal line VIL1, a second reset control line REL2, a second reset signal line VIL2, a third reset signal line VIL3, a first scanning line GAL1, a second reset signal line VIL2, a third reset signal line VIL3, a first scanning line GAL1, a second scanning line GAL2, and an emission control line EML. Here, For one pixel circuit PC: The first reset control line REL1 can be connected to the gate of the first reset transistor T1 to transmit the first reset control signal RE1. The first reset signal line VIL1 may be connected to the first pole of the first reset transistor T1 to transmit the first reset signal VI1.

[0074] The second reset control line REL2 can be connected to the gates of the second reset transistor T7 and the third reset transistor T8 to transmit the second reset control signal RE2. The second reset signal line VIL2 is connected to the first pole of the second reset transistor T7 to transmit the second reset signal VI2. The third reset signal line VIL3 may be connected to the first pole of the third reset transistor T8 to transmit the third reset signal VI3.

[0075] The first scanning line GA1 may be connected to the gate of the writing transistor T4 to transmit the first scanning signal Gate1. The second scanning line GA2 may be connected to the gate of the compensation transistor T2 to transmit the second scanning signal Gate2.

[0076] The emission control line EML can be connected to the gates of the first emission control transistor T5 and the second emission control transistor T6 to transmit the emission control signal.

[0077] In addition to the row wirings described above, the driving backplate BP includes column wirings extending in the column direction Y, and includes a data line DAL and a power supply line VDL for transmitting a data signal DA. One data line DAL is connected to a first pole of a writing transistor T4 of each pixel circuit in one column of pixel circuits. One power supply line VDL may be connected to a second pole plate Cst2 of each pixel circuit in one column of pixel circuits and a first pole of a first light emission control transistor T5 for transmitting a second power supply signal VDD.

[0078] As shown in FIG. 5, in some embodiments of the present disclosure, each pixel circuit PC of the driving backplate BP can be divided to obtain a plurality of circuit units CU distributed in an array. One circuit unit CU can include two adjacent pixel circuits PC distributed in the row direction X. Therefore, one column of circuit units CU can include two adjacent columns of pixel circuits PC distributed along the row direction X. At the same time, the two pixel circuits PC of the same circuit unit CU are symmetrically arranged, that is, the two pixel circuits PC of the same circuit unit CU are mirror arranged with respect to a straight line extending in the column direction Y. Therefore, the data line DAL and the power supply line VDL to which the two columns of pixel circuits PC of one column of circuit units CU are connected are also symmetrically arranged. Further, two adjacent circuit units CU in the row direction X may be symmetrically arranged with respect to a straight line extending in the column direction Y, that is, the pixel circuits of the two circuit units CU may be symmetrically arranged with respect to the straight line.

[0079] Note that the "symmetric arrangement" of two pixel circuits means that the patterns of all film layers of the two pixel circuits on the driving backplane BP are symmetric with respect to a straight line, that the patterns of some film layers of the two pixel circuits including semiconductor layers (for example, the first semiconductor layer POL and the second semiconductor layer IGL) on the driving backplane are symmetric with respect to a straight line, and that the patterns of each film layer of the two pixel circuits on the driving backplane BP are symmetric as a whole. However, the local patterns of some film layers may be locally asymmetric due to reasons such as processes and spatial constraints. Similarly, the "symmetric arrangement" of two data lines DAL and the "symmetric arrangement" of two power supply lines VDL not only mean that the patterns of the two data lines DAL or power supply lines VDL are completely symmetric, but also that the patterns of each film layer of the two data lines DAL or power supply lines VDL on the driving backplane BP are symmetric as a whole. However, it has been shown that they are locally asymmetric due to reasons such as processes and spatial limitations.

[0080] As shown in FIG. 5, in some embodiments, the power supply line VDL to which a column of circuit units CU is connected is located between two data lines DAL, and the two power supply lines VDL may have an integral structure. Of course, it may also be considered that two columns of pixel circuits PC of a column of circuit units CU share the same power supply line VDL. Further, the data lines DAL can be divided into a group of lines DU distributed along a plurality of row directions X. Each group of lines DU includes data lines DAL distributed along two row directions X, and the two data lines DAL of one group of lines DU are respectively connected to two columns of pixel circuits PC of a column of circuit units CU. Each transistor and capacitor of a column of circuit units CU can be located between the two connected data lines DAL.

[0081] Also, as shown in FIG. 2, the second electrode CAT of each light-emitting element LD can be connected to the first power supply bus VSL in the peripheral region WA, and the first power supply bus VSL can be connected to the binding portion PA. The first power supply signal VSS can be input to the second electrode CAT of the light-emitting element LD via the first power supply bus VSL. At the same time, the power supply line VDL can be connected to the second power supply bus BVDL in the peripheral region WA, and the second power supply bus BVDL can be connected to the binding portion PA to input the second power supply signal VDD to each power supply line VDL via the second power supply bus BVDL.

[0082] Each data line DAL may be connected to the binding portion PA to input the data signal DA to each data line DAL. Here, the data line DAL located in the main display area MA can be defined as the first data line DAL1 that extends from the main display area MA to the extraction area FA and is connected to the binding portion PA. Of course, the portion extending to the extraction area FA and the portion in the main display area MA can form a certain angle to converge at the binding portion PA. At the same time, the data line DAL located in the sub-display area SA can be defined as the second data line DAL2 that directly extends into the extraction area FA and can be connected to the binding portion PA. However, when the second data line DAL2 extends to the extraction area FA, it is necessary to provide a sufficient width to the area where the peripheral region WA is located at the corner of the display panel. Therefore, the width of the peripheral region WA is large, which is disadvantageous for reducing the peripheral region WA.

[0083] As shown in FIG. 2, in order to reduce the width of the peripheral region WA, the relay line CL can be used to connect the second data line DAL2 to the binding portion PA, and the relay line CL can extend from the sub-display region SA to the main display region MA, extend from the main display region MA to the extraction region FA, and be connected to the binding portion PA, thereby avoiding the second data line DAL2 from directly extending to the extraction region FA. One second data line DAL2 can be connected to the binding portion PA via at least one relay line CL. The relay line CL can include a first relay line CL1 and a second relay line CL2. The first relay line CL1 can extend from the sub-display region SA into the main display region MA along the row direction X. The first relay line CL1 can be connected to one second data line DAL2. The second relay line CL2 can be connected to the first relay line CL1, extend from the main display region MA to the extraction region FA along the column direction Y, and be connected to the binding portion PA. The second data line DAL2 is connected to the binding portion PA via the first relay line CL1 and the second relay line CL2.

[0084] Furthermore, as shown in FIGS. 2, 21 to 23, the driving backplate BP can include a plurality of first connection lines BL1 and a plurality of second connection lines BL2 in order to enhance the uniformity of the film layer where the relay line is located. Here, The first connection line BL1 can extend along the row direction X and be distributed at intervals along the column direction Y. At least a part of the first connection line BL1 includes a first relay line CL1 and a first dummy line DL1 provided at intervals. For example, among the same first connection lines BL1, the adjacent first relay line CL1 and the first dummy line DL1 are located on the same side, are separated by a break, and one first connection line BL1 may have up to two breaks Gap, one first relay line CL1 divided by the break, and at least one first dummy line DL1.

[0085] The second connection line BL2 extends in the column direction Y and can be distributed at intervals along the row direction X. At least a part of the second connection line BL2 includes a second connection line CL2 and a second dummy line DL2 provided at intervals. For example, among the same second connection lines BL2, the adjacent second connection line CL2 and the second dummy line DL2 are located in the same layer, arranged at intervals via a break, and one second connection line BL2 can have one break Gap and one second relay line CL2 and one second dummy line DL2 divided by the break Gap. The second relay line CL2 extends from the main display area MA to the extraction area FA and is connected to the binding portion PA.

[0086] Each break Gap of each second connection line BL2 connected to each second data line DAL2 located in the same sub-display area SA can be distributed at intervals along a straight-line trajectory, and the extending direction of this straight-line trajectory intersects the row direction X and the column direction Y.

[0087] Note that a part of the first connection line BL1 may have no break Gap and there may be a continuous wiring for extending to the peripheral area WA, which is not connected to the data line DAL and may function to enhance the uniformity of the second source-drain layer SD2 layer. These first connection lines BL1 without break Gaps are the first dummy lines DL1. At the same time, some second connection lines BL2 may have no break Gap and there may be a continuous wiring for extending to the extraction area FA, which is not connected to the first relay line CL1 but can be connected to the first dummy line DL1 and the first connection line BL1 without break Gap, enhancing the uniformity of the third source-drain layer SD3 layer and reducing the voltage drop uniformity of the first power supply signal VSS signal. These second connection lines BL2 without break Gaps are the second dummy lines DL2.

[0088] In the column direction Y, the first connection line BL1 on the side where the first connection line BL1 having a break Gap leaves the extraction area FA may all be first connection lines BL1 without a break Gap. In the row direction X, the second connection line BL2 having a break Gap is divided into two parts distributed along the row direction X. One part is connected to the second data line DAL2 in one sub-display area SA, and the other part is connected to the second data line DAL2 in another sub-display area SA. The two parts are arranged symmetrically with respect to the central axis in the column direction Y of the main display area MA. There may be a second connection line BL2 without a break Gap between the two parts.

[0089] The above-mentioned second connection line BL2 and the first connection line BL1 are located in different layers and intersect in space. Also, the first connection line BL1 and the data line DAL are located in different layers, and the second connection line BL2 is arranged insulatingly from the data line DAL. Therefore, any relay line CL is connected to one second data line DAL2 and not connected to the other second data line DAL2 and the first data line DAL1. For example, the second connection line BL2, the data line DAL, and the power supply line VDL may be located in the same layer, may be located on the side away from the substrate SU of the first connection line BL1, one second connection line BL2 may be located between two adjacent line groups DU, and may be arranged at an interval from the two data lines DAL of the line group DU.

[0090] Since the first dummy line DL1 and the second dummy line DL2 are arranged at intervals from the first relay line CL1 and the second relay line CL2 respectively, the first dummy line DL1 and the second dummy line DL2 do not access the data signal DA. Based on this, the inventors proposed to connect at least a part of the first dummy line DL1 and at least a part of the second dummy line DL2 to form a mesh structure, and connect this mesh structure to the first power supply bus VSL, so as to access the first power supply signal VSS, and there is a wiring for transmitting the first power supply signal VSS within the display area AA, making the voltage drop distribution of the first power supply signal VSS more uniform, reducing the cross voltage of the display panel, and reducing the power consumption.

[0091] Furthermore, in some embodiments of the present disclosure, both the first connection line BL1 and the second connection line BL2 may be provided in different layers. That is, the first relay line CL1 and the first dummy line DL1 may be arranged in different layers, thereby separating the two. The second relay line CL2 and the second dummy line DL2 may be arranged in different layers, thereby separating the two. The first relay line CL1 and the second relay line CL2 may be arranged in the same layer or in different layers as long as they can be connected to form the relay line CL. The first dummy line DL1 and the second dummy line DL2 may be arranged in the same layer or in different layers as long as they can be connected to the first power supply bus VSL.

[0092] Next, an exemplary description will be given of the connection method between the first connection line BL1 and the second connection line BL2.

[0093] As shown in FIGS. 21 to 23, in some embodiments of the present disclosure, the driving backplane BP further includes an array-distributed first relay part CP1 and an array-distributed second relay part CP2. The first relay part CP1, the second relay part CP2 and the first connection line BL1 may be arranged in the same layer and may be located on the side closer to the substrate SU of the data line DAL. The shapes of the first relay part CP1 and the second relay part CP2 may be circular, elliptical, polygonal or other regular or irregular shapes.

[0094] As shown in FIG. 22, the number of the first relay parts CP1 in one column is the same as the number of the pixel circuits PC in one column, and the first relay parts CP1 in one column may be connected to the first electrodes of the writing transistors T4 of the pixel circuits PC in one column in a one-to-one correspondence. Further, the first relay parts CP1 in one column may overlap with the data lines DAL in one column, and the data lines DAL and the first relay parts CP1 overlapping therewith are connected via contact holes. One data line DAL is connected to the pixel circuits PC in one column via the first relay parts CP1, and at the same time, a data signal DA can be input to the pixel circuits PC in one column. Here, since one second data line DAL2 can be connected to one first relay line CL1, one first relay part CP1 of the second data line DAL2 can be connected to one first relay line CL1. By making one first relay line CL1 and one first relay part CP1 into an integral structure, the second data line DAL2 and the first relay line CL1 can be connected via the first relay part CP1. The connected second data line DAL and the first relay line CL1 can both be realized by the connection between the first relay part CP1 and the first relay line CL1.

[0095] The second relay parts CP2 in one column can overlap with one second connection line BL2. One second relay line CL2 is connected to one first relay line CP1 in an integral structure and overlaps and is connected to one second relay part CP2. One first relay line CL1 and one second relay line CL2 can be connected via one second relay part CP2. That is, one relay line CL includes the first relay part CP1 connecting the second data line DAL2, the first relay line CL1, the second relay part CP2 connecting the first relay line CL1 and the second relay line CL2, and the second relay line CL2. Through this path, the second data line DAL2 can be connected to the binding part PA without passing through the corner position of the peripheral area WA.

[0096] Regarding the mesh structure formed by the above-described first dummy line DL1 and second dummy line DL2, connection can also be achieved by the second relay portion CP2. Specifically, at least a part of the second relay portion CP2 is integrally connected to the first dummy line DL1, and at least a part of the second dummy line DL2 is connected to the second relay portion CP2 that is connected to the first dummy line DL1. By doing so, the first dummy line DL1 and the second dummy line DL2 can be connected via a part of the second relay portion CP2 to form a mesh structure. Of course, the second relay portion CP2 that connects the first dummy line DL1 and the second dummy line DL2 and the second relay portion CP2 in the relay line CL are different second relay portions CP2. Also, there may be a portion of the second relay portion CP2 to which the first relay line CL1 and the first dummy line DL1 are not connected. The second relay portion CP2 of this portion and the first connection line BL1 may be provided at an interval as long as they do not affect the formation of the mesh structure accessible by the relay line CL and the first power supply signal VSS.

[0097] Next, as shown in FIGS. 22 to 23, the distribution patterns of the first relay portion CP1 and the second relay portion CP2 will be described in detail.

[0098] As shown in FIG. 22, in some embodiments of the present disclosure, each of the first relay portions CP1 and the second relay portions CP2 can be divided into a plurality of relay groups CP distributed in an array. One column of relay groups CP is located between two adjacent line groups DU, and one first connection line BL1 can pass through one row of relay groups CP. One relay group CP can include two first relay portions CP1 distributed in a triangle and one second relay portion CP2. Here, the triangular distribution means that the center lines of the two first relay portions CP1 and the one second relay portion CP2 form a triangle, and this triangle may be an isosceles triangle or the like and is not particularly limited here. The two second relay portions CP2 can be arranged symmetrically with respect to the center line extending in the column direction Y between two adjacent line groups DU.

[0099] For one relay group CP and a first connection line BL1 passing through it, two first relay parts CP1 are located on the side closer to the extraction area FA of the first connection line BL1, and a second relay part CP2 is located on the side where the first connection line BL1 leaves the extraction area FA.

[0100] Based on the above embodiments, the inventors have found that the existence of the above-mentioned gap Gap affects the uniformity of the screen of the display panel, and proposed to shield at least a partial gap Gap. Hereinafter, the shielding of the gap Gap will be described in detail.

[0101] As shown in FIG. 21, in some embodiments of the present disclosure, the data line DAL and the power supply line VDL are located on the side away from the substrate SU of the first connection line BL1, and at least a partial gap Gap can be shielded by using the data line DAL and the power supply line VDL. For example, the gap Gap can be classified, and the gap Gap located on the first connection line BL1 can be defined as the first gap Gap1, and the gap Gap of the second connection line BL2 can be defined as the second gap Gap2. Here, A part of the first gap Gap1 can overlap with the second connection line BL2 so as to be blocked by the second connection line BL2, and a part of the first gap Gap1 can overlap with the power supply line VDL so as to be blocked by the power supply line VDL. Also, when there are two first cut gaps Gap1 on the same first connection line BL1, both of the two first gaps Gap1 may be blocked by the second connection line BL2 or may be blocked by the power supply line VDL. Also, since the second gap Gap2 is in the same layer as the second connection line BL2 and the power supply line VDL, it is not blocked by the second connection line BL2 and the power supply line VDL. Of course, a part of the data line DAL can be overlapped with a part of the first gap Gap1 to shield the first gap Gap1 by using the data line DAL.

[0102] Furthermore, the orthographic projection of the first notch Gap1 onto the substrate SU can be located within the orthographic projection of the shielded power line VDL, the second connection line BL2, or the data line DAL onto the substrate SU, so as to completely shield the first notch Gap1.

[0103] Furthermore, the second notch Gap2 can be shielded using the first electrode ANO of the light-emitting element or the channel line TL of the touch layer TSP, as exemplified below.

[0104] As shown in FIG. 24, in some embodiments of the present disclosure, at least a part of the second notch Gap2 can overlap with a part of the first electrode ANO so as to be shielded by the first electrode ANO. The orthographic projection of the second notch Gap2 onto the substrate SU can be located within the orthographic projection of the shielded first electrode ANO onto the substrate SU so as to completely shield the second notch Gap2. However, since the distribution pattern of the first electrode ANO needs to meet certain pixel array requirements, the structure of the first electrode ANO can be improved to provide an extension for shielding the second notch Gap2. Specifically, The first electrode ANO may be a single-layer or multi-layer structure and may also be a light-shielding structure. The first electrode ANO can include an electrode portion A0, a first extension portion A1 and a second extension portion A2 extending outward from the edge of the electrode portion A0. That is, the first extension portion A1 and the second extension portion A2 may be radially connected to the edge of the electrode portion A0. Here, the first extension portion A1 can be connected to the second pole of the second light-emitting control transistor T6 and the second pole of the second reset transistor T7 of the pixel circuit through a contact hole. The second extension portion A2 can overlap with the second notch Gap2, and the second notch Gap2 can be shielded through the second extension portion A2.

[0105] As shown in FIG. 25, in other embodiments of the present disclosure, at least a partial break Gap can overlap with a partial channel line TL of the touch electrode layer TMB. For example, the channel line TL can overlap with at least a part of the second break Gap2, whereby the second break Gap2 can be shielded via the channel line TL. The positive projection of the second break Gap2 onto the substrate SU can be located within the positive projection of the channel line TL that it shields, and thus, the second break Gap2 can be completely blocked.

[0106] For example, the intersection of adjacent channel lines TL can be used to shield the second break Gap2. To increase the shielding range, intersection portions TLs can be formed at the intersections of the channel lines TL, that is, the mutually connected channel lines TL can converge at the intersection portions TLs. The width of the intersection portion is larger than the width of the channel line TL, and the positive projection of the second break Gap2 onto the substrate SU is located within the positive projection of one intersection portion TLs onto the substrate SU.

[0107] In other embodiments of the present disclosure, the manner of shielding the break Gap can be combined in manners other than the above embodiments. For example, the same break Gap can be shielded by at least one of the second connection line BL2, the data line DAL, and the power supply line VDL, and then also be shielded by at least one of the first electrode ANO and the channel line TL. The first electrode ANO and the channel line TL can shield not only the second break Gap2 but also the first break Gap1.

[0108] As shown in FIGS. 5 to 11, FIG. 19, and FIG. 22, based on the above-described embodiments, in some embodiments of the present disclosure, the driving backplane BP further includes a plurality of shield portions SL provided in the same layer. The shield portion SL is located on the side where the pixel circuit PC is away from the substrate SU, the data line DAL and the power supply line VDL are located on the side close to the substrate SU, and can be arranged in the same layer as the first connection line BL1. The shield portion SL is provided one-to-one for each pixel circuit PC in a direction perpendicular to the substrate SU. One shield portion SL overlaps with the first node N1 of one pixel circuit PC and the channel of the compensation transistor T2, and can shield the first node N1 and the channel of the compensation transistor T2. Further, the shield portion SL can be connected to the power supply line VDL connected to the corresponding pixel circuit PC, and the second power supply signal VDD can be input to the shield portion SL. Therefore, by shielding the signals on the side of the first node N1 and the channel of the compensation transistor T2 away from the substrate SU in the shield portion SL, interference between the signals of the gates of the driving transistor T3 and the compensation transistor T2 can be prevented. Thereby, shielding of the first node N1 and the compensation transistor T2 due to widening the power supply line VDL can be avoided, the parasitic capacitance between the power supply line VDL and the data line DAL can be reduced, the distance between the data line DAL and the power supply line VDL can be reduced, the occupied space can be reduced, and the resolution can be increased. Further, the shield portion SL can also shield light for the compensation transistor T2, which is advantageous for ensuring the stabilization of the electrical characteristics of the compensation transistor T2.

[0109] Next, the film layer of the driving backplane BP will be described in detail using the above-described pixel circuit.

[0110] As shown in FIGS. 3, 5, and 13 to 20, in addition to the substrate SU, the driving backplane BP further includes a first semiconductor layer POL, a first gate insulating layer GI1, a first gate layer GA1, a first insulating layer ILD0, a second gate layer GA2, a second insulating layer IL1, a second semiconductor layer IGL, a second gate insulating layer GI2, a third gate layer GA3, a third insulating layer IL2, a first source-drain layer SD1, a first planarization layer PLN1, a second source-drain layer SD2, a second planarization layer PLN2, a third source-drain layer SD3, and a third planarization layer PLN3. Here, The first semiconductor layer POL is provided on one side of the substrate SU and includes channels of driving transistors T3, writing transistors T4, second reset transistors T7, third reset transistors T8, first light emission control transistors T5, and second light emission control transistors T6 in the pixel circuit PC. The material of the first semiconductor layer POL may be polycrystalline silicon.

[0111] The first gate insulating layer GI1 can cover the first semiconductor layer POL, and the material of the first gate insulating layer GI1 can be an insulating material such as silicon nitride or silicon oxide.

[0112] The first gate layer GA1 is provided on the surface of the first gate insulating layer GI1 away from the substrate SU and can include a second reset control line REL2, a light emission control line EML, a first scanning line GAL1, and a first electrode plate Cst1 of the storage capacitor Cst. Here, The first electrode plate Cst1 overlaps with a partial region of the first semiconductor layer POL. The first semiconductor layer POL at the overlapping portion serves as the channel of the drive transistor T3, and the first electrode plate Cst1 is multiplexed as the gate of the drive transistor T3. The second reset control line REL2 overlaps with a part of the first semiconductor layer POL. The first semiconductor layer POL at the overlapping portion serves as the channels of the second reset transistor T7 and the third reset transistor T8, and the second reset control line REL2 at the overlapping portion serves as the gates of the second reset transistor T7 and the third reset transistor T8. The first scanning line GAL1 overlaps with a part of the first semiconductor layer POL. The first semiconductor layer POL at the overlapping portion serves as the channel of the writing transistor T4, and the first scanning line GAL1 at the overlapping portion serves as the gate of the writing transistor T4. The emission control line EML overlaps with a part of the first semiconductor layer POL. The first semiconductor layer POL at the overlapping portion serves as the channels of the first emission control transistor T5 and the second emission control transistor T6, and the emission control line EML at the overlapping portion serves as the gates of the first emission control transistor T5 and the second emission control transistor T6.

[0113] The first insulating layer ILD0 may cover the first gate layer GA1 and may be made of an insulating material such as silicon nitride or silicon oxide.

[0114] The second gate layer GA2 may be provided on the surface of the first insulating layer ILD0 away from the substrate SU, includes the second electrode plate Cst2, and the second electrode plate Cst2 overlaps with the first electrode plate Cst1 to form the storage capacitor Cst.

[0115] The second insulating layer IL1 covers the second gate layer GA2 and may have a single-layer structure or a multi-layer structure. Its material may include an inorganic insulating material such as silicon nitride or silicon oxide, or an organic insulating material such as an insulating resin. For example, the second insulating layer IL1 may include a dielectric layer and a buffer layer stacked in sequence along the direction away from the substrate SU.

[0116] The second semiconductor layer IGL may be disposed on the surface of the second insulating layer IL1 away from the substrate SU, and includes the channels of the first reset transistor T1 and the compensation transistor T2. The material of the second semiconductor layer IGL can include semiconductor metal oxides such as indium gallium zinc oxide (IGZO).

[0117] The second gate insulating layer GI2 may cover the second semiconductor layer IGL and may be made of an insulating material such as silicon nitride or silicon oxide.

[0118] The third gate layer GA3 is provided on the surface of the third gate insulating layer GI3 away from the substrate SU, and includes the first reset control line REL1, the first reset signal line VIL1, the second scanning line GAL2, and at least a part of the third reset signal line VIL3.

[0119] The first reset control line REL1 overlaps with a part of the second semiconductor layer IGL. The second semiconductor layer IGL at the overlapping portion is the channel of the first reset transistor T1, and the first reset control line REL1 at the overlapping portion is the gate of the first reset transistor T1. The second scanning line GAL2 overlaps with a part of the second semiconductor layer IGL. The second scanning line GAL2 at the overlapping portion is the channel of the compensation transistor T2, and the second scanning line GAL2 at the overlapping portion is the gate of the compensation transistor T2.

[0120] The third insulating layer IL2 can cover the third gate layer GA3, may have a single-layer or multi-layer structure, can include inorganic insulating materials such as silicon nitride or silicon oxide, and can include organic insulating materials such as insulating resins. For example, the third insulating layer IL2 can include a dielectric layer and a multi-layer inorganic insulating layer sequentially laminated in a direction away from the substrate SU.

[0121] The first source-drain layer SD1 can be provided on the surface of the third insulating layer IL2 away from the substrate SU, and includes at least a part of the second reset signal line VIL2 and the third reset signal line VIL3, that is, different regions of the third reset signal line VIL3 can be located in different layers.

[0122] The first flat layer PLN1 may be provided on the side of the first source-drain layer SD1 away from the substrate SU, and its material may be an insulating material such as resin. For example, the first source-drain layer SD1 can be coated with a passivation layer of an insulating material such as silicon nitride, and then the passivation layer can be coated with the first flat layer PLN1.

[0123] The second source-drain layer SD2 is provided on the surface of the first flat layer PLN1 away from the substrate, and can include the first connection line BL1, the shield part SL, the first relay part CP1, and the second relay part CP2.

[0124] The second flat layer PLN2 can cover the second source-drain layer SD2 and can be an insulating material such as resin.

[0125] The third source-drain layer SD3 is provided on the surface of the second flat layer PLN2 away from the substrate SU, and can include the data line DAL, the power supply line VDL, and the second connection line BL2.

[0126] The third flat layer PLN3 can cover the third source-drain layer SD3 and may be an insulating material such as resin. The first electrode ANO can be provided on the surface of the third flat layer PLN3 away from the substrate SU.

[0127] Also, as shown in FIGS. 5 and 12, a light-shielding layer BSM may be provided between the substrate SU and the first semiconductor layer POL. A light-shielding metal or other material may be used, and it may have a single-layer or multi-layer structure. At least a part of the region of the light-shielding layer BSM can shield the light irradiated to the transistor and overlap at least a part of the channel region of the transistor so that the electrical characteristics of the transistor are stabilized. For example, the light-shielding layer BSM can include a plurality of array-distributed light-shielding units BSM1 that shield the channel of the driving transistor T3. At the same time, each light-shielding unit BSM1 can be connected via the light-shielding line BSM2 to form an integral structure of the light-shielding layer BSM. By connecting the light-shielding layer BSM to the first power bus VSL or the second power bus BVDL, a first power signal VSS or a second power signal VDD can be input to the light-shielding layer BSM to play a role of electrostatic shielding through the light-shielding layer BSM.

[0128] Furthermore, as shown in FIG. 3, the light-shielding layer BSM can be covered by an insulating buffer layer BUF, and the first semiconductor layer POL can be provided on the surface of the buffer layer BUF away from the substrate SU. The buffer layer BUF may have a single-layer or multi-layer structure, and its material can include insulating materials such as silicon nitride and silicon oxide.

[0129] In other embodiments of the present disclosure, based on each film layer of the driving backplate BP described above, the first connection line BL1 is provided with the first source-drain layer SD1, and the second connection line BL2 is located in the second source-drain layer SD2. Alternatively, the first connection line BL1 can be located in the third source-drain layer SD3, the second connection line BL2 can be located in the second source-drain layer SD2, and the data line DAL and the power line VDL can be located in the first source-drain layer SD1 or the third source-drain layer SD3. Further, the first connection line BL1 may be provided in the third source-drain layer SD3, and the second connection line BL2 may be located in the first source-drain layer SD1 or the second source-drain layer SD2. Here, when the first connection line BL1 and the second connection line BL2 intersect with other wirings in the same layer, these wirings can be cut, and the cut portions can be connected using connection means located in other film layers.

[0130] Next, the pattern of each film layer of the driving backplate BP will be described in detail.

[0131] Taking each film layer of the pixel circuit PC as an example, As shown in FIGS. 5 to 11 and FIG. 13, the first semiconductor layer POL includes an integrated first active portion ACT1, a second active portion ACT2, a third active portion ACT3, a fourth active portion ACT4, and an independent fifth active portion ACT5. Here, The first active portion ACT1 is provided along the row direction X. The channel T31 of the driving transistor T3 is located in the first active portion ACT1, and a partial region of the channel T31 is bent in a direction away from the extraction region FA along the column direction Y. The channel T31 may have a shape of "S" or "n" or "I", and the first electrode plate Cst1 overlaps the channel T31 to form the driving transistor T3.

[0132] The second active part ACT2 extends in the column direction Y, with one end connected to one end of the first active part ACT1 and the other end extending in a direction away from the extraction region FA of the first active part ACT1. The first scanning line GA1 can intersect the second active part ACT2 along the row direction X, and the first active part ACT1 corresponding to the intersection point is the channel T41 of the write transistor T4.

[0133] The third active part ACT3 extends in the column direction Y, with one end connected to one end of the first active part ACT1 and the second active part ACT2, and the other end extending in a direction approaching the extraction region FA of the first active part ACT1. The emission control line EML can intersect the third active part ACT3 along the row direction X, and the third active part ACT3 corresponding to the intersection point is the channel T51 of the first emission control transistor T5.

[0134] The fourth active part ACT4 is provided in the column direction Y, with one end connected to the first active part ACT1, and the second active part ACT2 and the fourth active part ACT4 are connected to both ends of the first active part ACT1. The emission control line EML can intersect the fourth active part ACT4 along the row direction X, and the fourth active part ACT4 corresponding to the intersection point is the channel T61 of the second emission control transistor T6. The second reset control line REL2 is located on the side closer to the extraction region FA of the emission control line EML and can intersect the fourth active part ACT4 along the row direction X. The fourth active part ACT4 corresponding to the intersection point is the channel T71 of the second reset transistor T7.

[0135] The fifth active part ACT5 and the third active part ACT3 are distributed in the column direction Y and are located on the side closer to the extraction region FA of the first active part ACT1. The second reset control line REL2 can intersect the fifth active part ACT5 along the row direction X, and the fifth active part ACT5 corresponding to the intersection point is the channel T81 of the third reset transistor T8.

[0136] In the first semiconductor layer POL, regions other than the channels of the respective transistors are doping regions for forming the first and second electrodes of each transistor. Here, the specific positions of the first and second electrodes are not particularly limited, and they may be used as long as they can realize the connection relationship of the aforementioned 8T1C pixel circuit.

[0137] As shown in FIG. 14, the first gate layer GA1 includes a first scanning line GAL1, a light emission control line EML, and a second reset control line REL2, all of which extend along the row direction X. The first electrode plate Cst1 is distributed in the column direction Y. The first electrode plate Cst1 is located between the first scanning line GAL1 and the light emission control line EML. The first scanning line GAL1 is located on the side where the first electrode plate Cst1 is away from the extraction region FA, and the second reset control line REL2 is located on the side where the light emission control line EML approaches the extraction region FA.

[0138] As shown in FIG. 15, the second electrode plate Cst2 of the second gate layer GA2 overlaps with the first electrode plate Cst1 to form a storage capacitor Cst. In some embodiments of the present disclosure, two circuit units CU adjacent in the row direction X are symmetrically arranged, and their second electrode plates Cst2 are also symmetrically arranged. Among the second electrode plates Cst2 of two adjacent circuit units CU, the two adjacent second electrode plates Cst2 located in the middle can be connected through a protruding extension Cst21 extending in the row direction X. The second connection line BL2 can intersect with this protruding extension Cst21 and can be connected through a contact hole, and can be connected to the two second electrode plates Cst2 at the same time. The number of this contact hole is one or more. When spatially permitted, providing a plurality of contact holes is advantageous for reducing resistance.

[0139] As shown in FIG. 16, the second semiconductor layer IGL may include an oxide active portion ACT6 extending along the column direction Y. The oxide active portion ACT6 is disposed between the first reset control line REL1 and the third reset signal line VIL3, that is, the orthographic projection of the oxide active portion ACT6 onto the substrate SU is disposed between the orthographic projections of the first reset signal line VIL1 and the third reset signal line VIL3 onto the substrate SU.

[0140] As shown in FIG. 17, the first reset control line REL1 of the third gate layer GA3 can intersect the oxide active portion ACT6 along the row direction X, and the oxide active portion ACT6 corresponding to the intersection is the channel T11 of the first reset transistor T1. The second reset control line REL2 is located on the side closer to the extraction region FA of the first reset control line REL1 and is distributed at intervals along the column direction Y with the first reset control line REL1. The second reset control line REL2 can intersect the oxide active portion ACT6 along the row direction X, and the oxide active portion ACT6 corresponding to the intersection is the channel T21 of the compensation transistor T2. The first scanning line GA1 is located between the first reset control line REL1 and the second reset control line REL2 and intersects the region where the oxide active portion ACT6 is located between the channel T11 and the channel T21.

[0141] As shown in FIG. 16, the oxide active portions ACT6 of the two pixel circuits PC of the same circuit cell CU are provided in parallel, and one end away from the extraction regions FA of both is connected so that the first poles of the first reset transistors T1 of the two pixel circuits PC are connected.

[0142] As shown in FIGS. 15 and 9, in some embodiments of the present disclosure, the second gate layer GA2 further includes auxiliary reset lines REL1s and auxiliary scan lines GAL2s extending in the row direction X. The auxiliary reset lines REL1s may overlap with the first reset control line REL1. For example, the orthographic projection of the auxiliary reset lines REL1s onto the substrate SU is located within the orthographic projection of the first reset control line REL1 onto the substrate SU, and their extension trajectories are the same. The first reset control line REL1 also intersects with the oxide active portion ACT6, and the oxide active portion ACT6 corresponding to the intersection point is still the channel T11 of the first reset transistor T1. The auxiliary reset lines REL1s at the intersection point are also the gates of the first reset transistor T1. At the same time, the auxiliary reset lines REL1s may be connected to the first reset control line REL1 through contact holes within the display area AA, or may extend to the peripheral area WA to connect the two, which can increase the gate area of the first reset transistor T1.

[0143] The auxiliary scan lines GAL2s may overlap with the second scan line GAL2. For example, the orthographic projection of the auxiliary scan lines GAL2s onto the substrate SU is located within the orthographic projection of the second scan line GAL2 onto the substrate SU, and their extension trajectories are the same. The second scan line GAL2 also intersects with the oxide active portion ACT6, and the oxide active portion ACT6 corresponding to the intersection point is still the channel T21 of the compensation transistor T2. The auxiliary scan lines GAL2s at the intersection point are also the gates of the compensation transistor T2. At the same time, the auxiliary scan lines GAL2s may be connected to the second scan line GAL2 through contact holes within the display area AA, or may be connected after extending to the peripheral area WA, thereby increasing the gate area of the compensation transistor T2.

[0144] Furthermore, in some embodiments of the present disclosure, as shown in FIG. 7, in order to increase the channel length of the first reset transistor T1, the auxiliary reset line REL1s has a first auxiliary overlapping portion REL1s1 that protrudes in a direction away from the auxiliary scan line GAL2s along the column direction Y. The first auxiliary overlapping portion REL1s1 overlaps with the oxide active portion ACT6, and the region where the first auxiliary overlapping portion REL1s1 overlaps with the oxide active portion ACT6 serves as the gate of the first reset transistor T1. At the same time, in order to increase the channel length of the compensation transistor T2, the second auxiliary scan line GAL2s has a second auxiliary overlapping portion GAL2s1 that protrudes in the column direction Y toward the auxiliary reset line REL1s. The second auxiliary overlapping portion GAL2s1 overlaps with the oxide active portion ACT6, and the region where the second auxiliary overlapping portion GAL2s1 overlaps with the oxide active portion ACT6 is the gate of the compensation transistor T2.

[0145] As shown in FIG. 14, due to the presence of the second auxiliary overlapping portion GA2s1, the first scan line GA1 can form a notch GAL12 in order to avoid the second auxiliary scan line GA2s1, and at least a part of the orthographic projection of the second auxiliary overlapping portion GA2s1 on the substrate SU is located within the orthographic projection of the notch GAL12 on the substrate SU. As shown in FIG. 16, the capacitor portion C1 may form a notch C11 at a position corresponding to this notch GAL12.

[0146] Also, as shown in FIGS. 9 and 16, the oxide active portion ACT6 can form a capacitor portion C1 extending in the row direction X in the region between the channel T11 and the channel T21. This capacitor portion C1 can overlap with the first scan line GAL1, form a capacitance therebetween, and can overlap and connect with the first node N1. With this capacitance, when the display panel is in a black state, the voltage of the data signal DA can be lowered, preventing it from exceeding the maximum value of the voltage of the circuit chips in the peripheral circuit and the control circuit board. For one circuit unit CU, the capacitor portions C1 of the oxide active portions ACT6 of the two pixel circuits can extend in opposite directions.

[0147] The first reset control line REL1 in the third gate layer GA3 overlaps with a partial region of the oxide active part ACT6. The oxide active part ACT6 at the overlapping position serves as the channel of the first reset transistor T1, and the first reset control line REL1 at the overlapping position serves as the gate of the first reset transistor T1. The second scanning line GAL2 overlaps with a partial region of the oxide active part ACT6. The second scanning line GAL2 at the overlapping position serves as the channel of the compensation transistor T2, and the second scanning line GAL2 at the overlapping position serves as the gate of the compensation transistor T2. The first scanning line GAL1 is located between the first reset control line REL1 and the second scanning line GAL2, and the first reset signal line VIL1 is located on the side where the first reset control line REL1 is away from the second scanning line GAL2.

[0148] Furthermore, in some embodiments of the present disclosure, as shown in FIGS. 9 and 17, in order to increase the length of the channel of the first reset transistor T1, the first reset control line REL1 has a first overlapping portion REL11 that protrudes in a direction away from the second scanning line GAL2 along the column direction Y. The first overlapping portion REL11 overlaps with the oxide active part ACT6. The region where the first overlapping portion REL11 and the oxide active part ACT6 overlap serves as the gate of the first reset transistor T1. The first overlapping portion REL11 overlaps with the first auxiliary overlapping portion REL1s1, and the orthographic projection of the first overlapping portion REL11 on the substrate SU is located within the orthographic projection of the first auxiliary overlapping portion REL1s1 on the substrate SU. Also, in order to increase the length of the channel of the compensation transistor T2, the second scanning line GAL2 has a second overlapping portion GAL21 that protrudes in the column direction Y toward the first reset control line REL1. The second overlapping portion GAL21 overlaps with the oxide active part ACT6. The region where the second overlapping portion GAL21 and the oxide active part ACT6 overlap serves as the gate of the compensation transistor T2. The second overlapping portion GAL21 overlaps with the second auxiliary overlapping portion GAL2s1, and the orthographic projection of the second overlapping portion GAL21 on the substrate SU is located within the orthographic projection of the second auxiliary overlapping portion GAL2s1 on the substrate SU.

[0149] As shown in FIGS. 10 and 18, the first source-drain layer SD1 may include a first connection portion SDL1, a second connection portion SDL2, a third connection portion SDL3, a fourth connection portion SDL4, a fifth connection portion SDL5, a sixth connection portion SDL6, a seventh connection portion SDL7, and a second reset signal line VIL2. Here, The second connection portion SDL2 extends in the row direction X, overlaps with two second polar plates Cst2 of two pixel circuits of the same circuit unit CU, and by connecting to the two second polar plates Cst2 through contact holes, the two second polar plates Cst2 of the same circuit unit CU can be connected as one conductive whole.

[0150] The third connection portion SDL3 can extend in the column direction Y. One end of one third connection portion SDL3 can be connected to one second polar plate Cst2 through a contact hole, and the other end can be connected to a region for forming the first pole of the first light emission control transistor T5 in the third active portion ACT3 through a contact hole.

[0151] Furthermore, in some embodiments of the present disclosure, two circuit units CU adjacent in the row direction X are symmetrically arranged, and two adjacent second polar plates Cst2 between each second polar plate Cst2 of the two adjacent circuit units CU can be connected through a protruding extension portion Cst21 extending in the row direction X. The protruding extension portion Cst21 connecting the two second polar plates Cst2 can be connected to the same third connection portion SDL3 through a contact hole. Therefore, the first power supply signal VDD can be transmitted to the two second polar plates Cst2 simultaneously through the same third connection portion SDL3, that is, the pixel circuits PC to which the two second polar plates Cst2 belong share the same third connection portion SDL3.

[0152] Of course, in other embodiments of the present disclosure, the protruding extension portion Cst21 described above may be divided and set. That is, the two second electrode plates Cst2 extend the protruding extension portion Cst21 oppositely, but the protruding extension portions Cst21 are not directly connected. The two protruding extension portions Cst21 are respectively connected to one third connection portion SDL3 through contact holes and do not share the third connection portion SDL3.

[0153] The first connection portion SDL1 can extend in the column direction Y and is located between the second connection portion SDL2 and the third connection portion SDL3. One end of the first connection portion SDL1 overlaps with the capacitor portion C1 and is connected through a contact hole. The other end of the first connection portion SDL1 overlaps with the first electrode plate Cst1 and is connected through a contact hole that penetrates the second electrode plate Cst2. In order to facilitate the connection between the first connection portion SDL1 and the first electrode plate Cst1, a through hole Hc is opened in the second electrode plate Cst2, and the contact hole connecting the first connection portion SDL1 and the first electrode plate Cst1 can pass through the through hole Hc.

[0154] The fourth connection portion SDL4 can extend in the column direction Y and is located between the third connection portion SDL3 and the first connection portion SDL1. One end of the fourth connection portion SDL4 is connected to the region that becomes the second pole of the write transistor T4 of the third active portion ACT3 through a contact hole, and the other end is connected to the region that becomes the second pole of the third reset transistor T8 of the fifth active portion ACT5 through a contact hole. In some embodiments of the present disclosure, in the aspect where the pixel circuits PC to which the above-described second electrode plate Cst2 belongs share the same first connection portion SDL1, the fourth connection portions SDL4 of the two pixel circuits PC may be symmetric with respect to the third connection portion SDL3 so as to save space and be advantageous for achieving high resolution.

[0155] The fifth connection part SDL5 can extend in the column direction Y. One end is connected to the first reset signal line VIL1 via the contact hole h1, and the other end is connected to the first pole of the first reset transistor T1 of the oxide active part ACT6 via the contact hole h2. Since two oxide active parts ACT6 of the same circuit unit CU are connected as one end of the first pole of the first reset transistor T1, one first reset signal line VIL1 can be connected to the first reset transistors T1 of the two pixel circuits of one circuit unit CU simultaneously via one fifth connection part SDL5. The fifth connection part SDL5 may be a pattern that extends along the symmetry axis of the two pixel circuits of one circuit unit CU and is symmetric with respect to the symmetry axis.

[0156] Furthermore, in some embodiments of the present disclosure, two oxide active parts ACT6 of the same circuit unit CU are connected via the oxide connection part ACT61. The oxide connection part ACT61 can protrude in a direction away from the oxide active part ACT6 along the column direction Y. The contact hole h2 can be made to correspond to the oxide connection part ACT61, and it can be prevented that the contact hole h2 exceeds the boundary of the oxide connection part ACT61. At the same time, the first reset signal line VIL1 is bent in a direction away from the oxide connection part ACT61 in the region corresponding to the oxide connection part ACT61 in the column direction Y, and a bent part VIL11 is formed. The contact hole h1 is correspondingly connected to this bent part VIL11. By providing this bent part VIL11, while avoiding overlap with the oxide connection part ACT61, the region of the first reset signal line VIL1 other than the bent part VIL11 can be brought closer to the oxide active part ACT6 and the first reset control line REL1 in the column direction Y, which is advantageous for making the wiring and the pixel circuit more compact and saving space. At the same time, the bent part VIL11 can be connected to the contact hole h1 while avoiding the contact hole h2.

[0157] The sixth connection part SDL6 can extend in the column direction Y and is located on the side away from the fourth connection part SDL4 of the first connection part SDL1. One end of the sixth connection part SDL6 can be connected to the region serving as the first pole of the compensation transistor T2 of the oxide active part ACT6 through a contact hole, and the other end can be connected to the region serving as the second pole of the drive transistor T3 of the first active part ACT1 through a contact hole.

[0158] The seventh connection part SDL7 can be connected to the region serving as the first pole of the write transistor T4 of the second active part ACT2 through a contact hole. The shape of the seventh connection part SDL7 may be circular, elliptical, polygonal, or other regular or irregular shapes, and is not particularly limited here.

[0159] Furthermore, in some embodiments of the present disclosure, the capacitor part C1 can extend to the contact hole connecting the seventh connection part SDL7 and the second active part ACT2. However, in order to avoid this contact hole, the contour of one end of the capacitor part C1 close to the contact hole may be arc-shaped, does not overlap with the seventh connection part SDL7, and is advantageous for maximizing the area of the capacitor part C1 without overlapping with this contact hole. Therefore, the first scanning line GAL1 has a second capacitor part GAL11 protruding in the direction away from the second scanning line GAL2 along the column direction Y in order to form a capacitor according to the shape of the first capacitor C1. The second capacitor part GAL11 overlaps with the capacitor part C1 to form a capacitor, and the orthographic projection of the capacitor part C1 on the substrate SU is located within the orthographic projection of the second capacitor part GAL11 on the substrate SU. The side of the second capacitor part GA11 close to the second active part ACT2 may be arc-shaped with the same shape as the capacitor part C1. Of course, the first capacitor C1 may be rectangular or other shapes, and the second capacitor part GA11 may have the same shape as the first capacitor C1.

[0160] The eighth connection part SDL8 can be connected to the region between channel T61 and channel T71 in the fourth active part ACT4 via a contact hole, and the second pole of the second reset transistor T7 and the second pole of the second light emission control transistor T6 can be connected. The shape of the eighth connection part SDL8 may be circular, elliptical, polygonal, or other regular or irregular shapes, and is not particularly limited here.

[0161] As shown in FIGS. 11 and 19, in the second source-drain layer SD2, the shield part SL may overlap with one end (the first node N1) where the first connection part SDL1 and the capacitor part C1 are connected, and may also overlap with the channel T21 of the compensation transistor T2. Also, in the circuit unit CU where the shield part SL and the overlapping first connection part SDL1 are located, the shield part SL can be connected via a contact hole while overlapping with the second connection part SDL2. The second connection part SDL2 can simultaneously connect two second electrode plates Cst2 of the same circuit unit CU via a contact hole, and the shield part SL and two second electrode plates Cst2 of one circuit unit CU can be connected as one conductive whole. The first relay part CP1 is located between the first connection line BL1 and the shield part SL.

[0162] In the circuit unit CU where the shield part SL and the overlapping third connection part SDL3 are located, the two data lines DAL to which the circuit unit CU is connected are located on both sides of the shield part SL, and the power supply line VDL to which the circuit unit CU is connected is located between the two data lines DAL and overlaps with the shield part SL.

[0163] The second source-drain layer SD2 can further include a first electrode relay part CP3 connected to the eighth connection part SDL8, and can be connected to the first electrode ANO via the second electrode relay part CP4 in the third source-drain layer SD3. The first electrode relay part CP3 may include a main body part CP31 and a relay extension part CP32 connected to the edge of the main body part CP31. The relay extension part CP32 may extend along a straight line, and its direction may be the row direction X or the column direction Y, or may be another direction different from the row direction X and the column direction Y. The main body parts CP31 of the two first electrode relay parts CP3 to which two eighth connection parts SDL8 to which two pixel circuits PC of the same pixel unit CU are connected can extend along the row direction X, and the extension directions of the relay extension parts CP32 of the two first electrode relay parts CP3 can be different. For example, one relay extension part CP32 can extend along the row direction X, and the other can form an angle of less than 90° with the row direction X and the column direction Y. That is, these two first electrode relay parts CP3 may be asymmetric or, of course, symmetric.

[0164] As shown in FIGS. 5 and 20, the data line DAL located in the third source-drain layer SD3 and the seventh connection part SDL7 are connected via a contact hole, and the data line DAL can be connected to the first pole of the write transistor T4. In one power supply line VDL and its connected circuit unit CU, the power supply line VDL has protruding parts VDL1 protruding on both sides along the row direction X, and the two protruding parts VDL1 respectively overlap the channels T11 of the first reset transistors of the two pixel circuits PC, so that the protruding parts VDL1 can play the role of shielding and light shielding. The first power supply bus VSL can be at least partially located in the third source-drain layer SD3, and the second power supply bus BVDL can be located in the extraction region FA, located between the binding part PA and the display region AA. The second power supply bus BVDL can extend in the row direction. The third source-drain layer SD3 is located on the side close to the substrate SU and can be connected to the part extending into the extraction region FA of each power supply line VDL via a contact hole, and can avoid short circuit with the data line DAL.

[0165] Furthermore, the power supply line VDL may be connected to the first electrode (a part of the fifth active part ACT5) of the first light emission control transistor T5 via the shield part SL, the second connection part SDL2, the second electrode plate Cst2, and the third connection part SDL3. Here, the second electrode plate Cst2 transmits the first power supply signal VDD. The third connection part SDL3 does not need to transmit the first power supply signal VDD in the row direction X, and only needs to connect the second electrode plate Cst2 to the fifth active part ACT5. This is advantageous for reducing the width of the third connection part SDL3 in the row direction X. This width may be twice the width of the data line DAL. Thus, while ensuring the dimensional requirements of the contact hole, the width of the third connection part SDL3 can be minimized, contributing to space saving. Also, the power supply line VDL is connected to two second electrode plates Cst2 of the same circuit unit CU via the shield part SL and the second connection part SDL2, and can form one network for transmitting the first power supply signal VDD, which is advantageous for reducing the resistance-capacitance load (RC loading).

[0166] Furthermore, in some embodiments of the present disclosure, the data line DAL and the power supply line VDL connected to the same circuit unit CU may have a data line bending part DAL11 that bends in a direction away from the power supply line CDL along the row direction X. The data line bending part DAL11 is linearly arranged along the row direction X with the capacitance part C1 so as to avoid the capacitance part C1 and not overlap with the capacitance part C1. Also, the data line bending part DAL11 bends in a direction away from the first connection part SDL1 to increase the distance from the first connection part SDL1, avoiding crosstalk of the data signal DA to the first node N1 of the pixel circuit PC.

[0167] Further, the third source-drain layer SD3 includes a second electrode relay portion CP4 connected to the first electrode relay portion CP3 via a contact hole. The second electrode relay portion CP4 is connected to the first electrode ANO via a contact hole, and is connected to a region between the channel T71 of the second reset transistor T7 and the channel T61 of the second light emission control transistor T6 in the fourth active portion ACT4 via the second electrode relay portion CP4, the first electrode relay portion CP3, and the eighth connection portion SDL8. That is, it is connected to the second pole of the second reset transistor T7 and the second pole of the second light emission control transistor T61 of the second light emission control transistor T6.

[0168] Also, as shown in FIG. 24, in some embodiments of the present disclosure, the shield portions SL adjacent to the pixel circuits PC in the same row can be connected via connection segments SL1, further expanding the range of the conductive network accessible to the first power supply signal VDD, which is advantageous for reducing resistance-capacitance loading.

[0169] Next, the distribution method of the wiring connected to the pixel circuits PC in one row will be described in detail.

[0170] As shown in FIG. 27, the first reset control line REL1, the first reset signal line VIL1, the second reset control line REL2, the second reset signal line VIL2, the third reset signal line VIL3, the first scan line GAL1, the second scan line GAL2, and the light emission control line EML connected to the pixel circuits PC in the same row all extend in the row direction X and are distributed along the column direction Y.

[0171] The first reset control line REL1, the first scanning line GAL1, the second scanning line GAL2, the third reset signal line VIL3, the light emission control line EML, and the second reset control line REL2 are located between the first reset signal line VIL1 and the second reset signal line VIL2. The first scanning line GAL1, the second scanning line GAL2, at least a part of the third reset signal line VIL3 (line body VIL31), and the light emission control line EML are located between the first reset control line REL1 and the second reset control line REL2. The second scanning line GAL2 is located between the first scanning line GAL1 and the light emission control line EML. The second electrode plate Cst2 is located between the second scanning line GAL2 and at least a part of the third reset signal line VIL3 (line body VIL31). The light emission control line EML overlaps at least a part of the third reset signal line VIL3 (line branch VIL32).

[0172] To save space and improve resolution, some scanning lines of different film layers can be overlapped. For example, In some embodiments of the present disclosure, the first reset signal line VIL1 connecting the pixel circuit PC in the n + 1-th row overlaps with the second reset control line REL2 connecting the pixel circuit PC in the n-th row, and their orthographic projections onto the substrate SU overlap at least partially along the row direction X. Also, one first reset signal line VIL1 overlaps with one first connection line BL1.

[0173] In some embodiments of the present disclosure, the second reset signal line VIL2 connecting the pixel circuit PC in the n + 1-th row overlaps with both the first reset control line REL1 and the first scanning line GAL1 connecting the pixel circuit PC in the n-th row. That is, their orthographic projections onto the substrate SU are overlapped at least partially along the row direction X.

[0174] In some embodiments of the present disclosure, the second reset signal line VIL2 has a bent portion VIL21 curved in the column direction Y, and a partial region of the shield portion SL connecting the pixel circuit PC in the n+1-th row can be located within the bent portion VIL21 of the second reset signal line VIL2 connecting the pixel circuit PC in the n-th row. That is, the orthographic projection of the partial region of the shield portion SL on the substrate SU can be located within the orthographic projection of the bent portion VIL21 on the substrate SU. Therefore, the shield portion SL can be avoided via the bent portion VIL21. The fourth active portions ACT4 of the two pixel circuits PC of the same circuit unit CU are both connected to the bent portion VIL21 of the second reset signal line VIL2 via contact holes.

[0175] Next, the configuration of the third reset signal line VIL3 will be described in detail.

[0176] As shown in FIGS. 9 to 11 and FIG. 18, the third reset signal line VIL3 includes a line body VIL31 extending in the row direction X and a line branch VIL32 connected to the side of the line body VIL31 close to the second reset signal line VIL2. The line body VIL31 and the line branch VIL32 are located in different layers. The line body VIL31 is located between the second scanning line GA2 and the second reset control line REL2 and overlaps with the emission control line EM. The line branch VIL32 extends to between the second reset control line REL2 and the second reset signal line VIL2 and can be connected to the first pole of the third reset transistor T8. The line body VIL31 is located in the third gate layer GA3, and the line branch VIL32 is located in the first source-drain layer SD1.

[0177] Furthermore, the line branch VIL32 includes a first segment VIL321 extending in the column direction Y, a second segment VIL322, and a third segment VIL323 extending in the row direction X. The second segment VIL322 forms a certain angle with the first segment VIL321 and the third segment VIL323. The second segment VIL322 overlaps with the second reset control line REL2. The third segment VIL323 is located on the side where the second reset control line REL2 is away from the first segment VIL321 and the line body VIL31.

[0178] One end of the first segment VIL321 is connected to the line body VIL31 via a contact hole, and the other end is connected to one end of the second segment VIL322. The other end of the second segment VIL322 is connected to one end of the third segment VIL323. The other end of the third segment VIL323 is connected to a part of the fifth active part ACT5 via a contact hole, connecting the line body VIL31 and the third reset transistor T3 to transmit the third reset signal VI3. Here, by making the second segment VIL322, the first segment VIL321, and the third segment VIL323 all form a certain angle and be greater than 90°, the bent portion VIL21 of the second reset signal line VIL2 and the contact hole where the fourth connection part SDL4 is connected to the fifth active part ACT5 can be avoided. The fifth active part ACT5 has a region extending in the row direction X. This region serves as the first pole of the third reset transistor T3, and the third segment VIL323 can overlap with this region. The first segment VIL321 can overlap with a partial region forming the second reset transistor T7 in the fourth active part ACT4.

[0179] Further, the second segment VIL322 may have the same fixed angle with the first segment VIL321 and the third segment VIL323, and may be 120°, 125°, 130°, 135°, etc., and is not particularly limited herein. Of course, the angles formed by the second segment VIL322 with the first segment VIL321 and the third segment VIL323 may be different.

[0180] Next, the distribution patterns of the first relay portion CP1, the second relay portion CP2, the first electrode relay portion CP3, and the second electrode relay portion CP4 will be described.

[0181] As shown in FIGS. 19, 21, 22, and 25, in addition to the first relay portion CP1 and the second relay portion CP2, the relay group CP can include two first electrode relay portions CP3 respectively belonging to two circuit units CU adjacent to each other in the row direction X. The first relay portion CP1 is connected to the writing transistor T4 of the pixel circuit PC in the (n + 1)-th row. The first electrode relay portion CP3 is connected to the second electrodes of the second light emission control transistor T6 and the second reset transistor T7 of the pixel circuit PC in the n-th row.

[0182] The two first electrode relay portions CP3 may be located on both sides of one second relay portion CP2 and connected to two second electrode relay portions CP4 via the third contact hole H3. The first relay portion CP1 in the relay group CP can be connected to the data line DAL via the first contact hole H1, and the second relay portion CP2 can be connected to the second connection line BL2 (the second relay line CL2 or the second dummy line DL2) via the second contact hole H2. Here, the two first electrode relay portions CP3 are asymmetric with respect to the second relay portion CP2.

[0183] Furthermore, as shown in FIGS. 21 and 22, each of the first contact holes H1 and the second contact holes H2 can be divided into a plurality of hole groups H distributed in an array, and one row of hole groups H is located between power lines VDL connected to two adjacent circuit units CU. Note that the power lines VDL connected to the same circuit unit CU, that is, the power lines VDL connected to the two pixel circuits PC of this circuit unit CU. The power lines VDL connected to the same circuit unit CU can be regarded as one whole, and one row of hole groups H is actually located between two wholes. Of course, when the power lines VDL connected to the same circuit unit CU are of an integral structure, one row of hole groups H is located between the two power lines VDL. One hole group H includes two first contact holes H1, one second contact hole H2, and two third contact holes H3. The two first contact holes H1 and one second contact hole H2 can be distributed in a triangle. One first connection line BL1 passes through one row of hole groups H, divides the two first contact holes H1 on the same side of the two first connection lines BL1, and divides the two third contact holes H3 and the second contact hole H2 on the other side of the first connection line BL1.

[0184] In the same hole group H, the first contact hole H1 is connected to the pixel circuit in the (n + 1)-th row, the third contact hole H3 is connected to the pixel circuit in the n-th row, the two third contact holes H3 are located on both sides of the second contact hole H2, and are distributed along the column direction Y. The distances in the row direction of the two third contact holes H3 are approximately equal. The two third contact holes H3 and the first contact hole H1 also exhibit a triangular distribution to blur the visual effect, make the first contact hole H1 less conspicuous, and help improve the display uniformity. Also, the two first contact holes H1 can be arranged symmetrically with respect to the second contact hole H2.

[0185] Also, as shown in FIG. 21, the power supply line VDL connected to the same circuit unit CU is connected via the fourth contact hole H4 and the shield portion SL overlapping with this circuit unit CU, and the fourth contact holes are distributed in an array. Two fourth contact holes H4 adjacent in the row direction X can be distributed along the column direction Y, further blurring the visual effect and improving the display uniformity. Of course, the two fourth contact holes H4 adjacent in the row direction X may be provided symmetrically with respect to one second contact hole H2 between the power supply lines VDL to which they are connected.

[0186] Exemplarily, the second contact hole H2 may be located between the first scanning line GA1 and the first reset signal line VIL1, the third contact hole H3 can be located between the emission control line EML and the second reset signal line REL2, and the fourth contact hole H4 can be located between the second scanning line GA2 and the emission control line EML.

[0187] The present disclosure also provides a display device including the display panel of any of the above embodiments, and its specific configuration and beneficial effects can be referred to the above embodiments of the display panel, and the description is omitted here. The display device of the present disclosure may be a mobile phone, a television, a tablet, and of course, it may also be used in electronic devices having a display function such as a wristwatch and a handle, but they are not enumerated one by one here.

[0188] Those skilled in the art will easily come up with other embodiments of the present disclosure after considering the specification and practicing the invention disclosed in this specification. This application aims to cover any modifications, uses or adaptive changes of the present disclosure, including the common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure, in accordance with the general principles of the present disclosure. The specification and embodiments are regarded as merely exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A display panel including a display area and a peripheral area outside the display area, wherein the peripheral area includes a pull-out area extending along a direction away from the display area, the pull-out area has a binding portion, the display area and the pull-out area are distributed along a column direction, and the display area includes a main display area and sub-display areas provided on both sides of the main display area along a row direction; the display panel includes a driving backplate and a plurality of light-emitting elements provided on one side of the driving backplate, the driving backplate includes a substrate and a plurality of circuit units located on one side of the substrate, the circuit units include two pixel circuits distributed along a row direction, and the two pixel circuits of the same circuit unit are symmetrically provided; the light-emitting element includes a first electrode, a light-emitting layer, and a second electrode laminated along a direction away from the driving backplate, and one of the first electrodes is connected to one of the pixel circuits; the driving backplate includes a first power bus, a plurality of data lines, a plurality of power lines, a plurality of first connection lines, and a plurality of second connection lines; the first power bus is provided in the peripheral area and is connected to the second electrode; the plurality of data lines extend along the column direction and are divided into a plurality of line groups distributed along the row direction, each line group includes two data lines distributed along the row direction, the two data lines of one line group are respectively connected to two columns of pixel circuits of one column of circuit units, each data line includes a plurality of first data lines and second data lines, the first data lines extend from the main display area to the pull-out area and are connected to the binding portion, and the second data lines are located in the sub-display areas; the plurality of power lines extend from the display area to the pull-out area along the column direction, and two columns of pixel circuits of one column of circuit units are connected to one of the power lines; the plurality of first connection lines extend along the row direction, and at least a part of the first connection lines includes a first relay line and a first dummy line provided at intervals, and the first relay line extends from the sub-display area to the main display area; The plurality of second connection lines extend along the column direction. One of the second connection lines is located between two adjacent line groups. The data lines of two adjacent line groups are provided symmetrically with respect to the second connection line between the two line groups. At least some of the second connection lines include second relay lines and second dummy lines provided at intervals. The second relay lines extend from the main display area to the extraction area and are connected to the binding portion. One of the first relay lines is connected to one of the second relay lines to form one relay line. One of the second data lines is connected to the binding portion via at least one of the relay lines. The first connection line is provided insulated from the data line. At least some of the first dummy lines are connected to at least some of the second dummy lines and are connected to the first power bus. A display panel characterized by the above.

2. The first relay line and the first dummy line are provided in the same layer on the side of the power line closer to the substrate. The second relay line and the second dummy line are provided in the same layer on the side where the first connection line is away from the substrate. Among the adjacent first relay lines and first dummy lines of the same first connection line, they are provided at intervals via a break. Among the adjacent second relay lines and second dummy lines of the same second connection line, they are provided at intervals via a break. At least some of the breaks of the first connection line overlap with the second connection line or the power line. The display panel according to claim 1, characterized by the above.

3. The first connection line is located on the side of the data line closer to the substrate. The display panel according to claim 2, characterized by the above.

4. At least some of the breaks overlap with some of the first electrodes. The display panel according to claim 3, characterized by the above.

5. The display panel further includes a touch layer. The touch layer is provided on the side where the light-emitting element is away from the substrate and includes a touch electrode layer. The touch electrode layer has a network structure surrounded by a plurality of channel lines. At least some of the breaks overlap with some of the channel lines. The display panel according to claim 2, characterized by the above.

6. The break of the first connection line is a first break, and the break of the second connection line is a second break. One of the first cuts overlaps with the second connection line, and some of the other first cuts overlap with the power line. The second cut overlaps with the first electrode or the channel line. The display panel according to claim 5, characterized in that.

7. Some of the first relay lines continuously extend along the row direction to the peripheral region, and some of the second relay lines continuously extend along the column direction to the extraction region. The display panel according to claim 1, characterized in that.

8. The second connection line is provided on the same layer as the data line and the power line, and the first connection line is located on the side away from the substrate. The driving backplate further includes an array-distributed first relay part and an array-distributed second relay part, and the first relay part, the second relay part, and the first connection line are provided on the same layer. One row of the first relay parts overlaps with one of the data lines, and one of the data lines is respectively connected to each of the pixel circuits in one row of the pixel circuits through each of the first relay parts overlapping therewith. One of the first relay lines is connected to one of the second data lines through one of the first relay parts. One row of the second relay parts overlaps with one of the second connection lines, and one of the second relay lines is connected to one of the first relay lines through one of the second relay parts. The display panel according to claim 3, characterized in that.

9. At least a part of the second dummy lines is connected to at least a part of the first dummy lines through at least a part of the second relay parts. The display panel according to claim 8, characterized in that.

10. The first relay part is connected to the data line through a first contact hole, and the second relay part is connected to the second connection line through a second contact hole. Each of the first contact holes and the second contact holes is divided into a plurality of hole groups distributed in an array. One row of the hole groups is located between the power lines connected to two adjacent circuit units. One of the hole groups includes two of the first contact holes and one of the second contact holes, and the two first contact holes are provided symmetrically with respect to the second contact hole. The display panel according to claim 9, characterized in that.

11. Two of the first contact holes and one of the second contact holes in the same hole group are distributed in a triangle shape. The display panel according to claim 10, characterized in that.

12. The driving backplate further includes an array-distributed first electrode relay part and an array-distributed second electrode relay part. The first electrode relay part is provided on the same layer as the first relay part and the second relay part. The second electrode relay part is located on the side where the first electrode relay part is away from the substrate. One of the first electrode relay parts overlaps with one of the second electrode relay parts and is connected through a third contact hole. The first electrode is connected to the pixel circuit through the second electrode relay part, the third contact hole, and the first electrode relay part. The hole group further includes the third contact hole. In the same hole group, the first contact hole is connected to the pixel circuit in the (n + 1)-th row, the third contact hole is connected to the pixel circuit in the n-th row, and two of the third contact holes are located on both sides of the second contact hole and are distributed along the column direction. The display panel according to claim 11, characterized in that.

13. The pixel circuit includes a driving transistor, a writing transistor, a compensation transistor, a first reset transistor, a second reset transistor, a third reset transistor, a first light emission control transistor, a second light emission control transistor, and a storage capacitor. The driving backplate further includes a first reset control line, a first reset signal line, a second reset control line, a second reset signal line, a third reset signal line, a first scanning line, a second scanning line, and a light emission control line. The gate of the driving transistor is connected to a first node. The first pole is connected to one of the power lines through the first light emission control transistor. The second pole is connected to the first electrode of one of the light emitting elements through the second light emission control transistor. The gates of the first light emission control transistor and the second light emission control transistor are connected to the light emission control line. The gate of the first reset transistor is connected to the first reset control line. The first pole is connected to the first reset signal line. The second pole is connected to the first node. The gate of the writing transistor is connected to the first scanning line, the first pole is connected to one of the data lines, and the second pole is connected to the first pole of the driving transistor. The gate of the compensation transistor is connected to the second scanning line, the first pole is connected to the second pole of the driving transistor, and the second pole is connected to the first node. The gates of the two reset transistors are connected to the second reset control line, the first poles are connected to the second reset signal line, and the second poles are connected to the first electrode. The gate of the third reset transistor is connected to the second reset control line, the first pole is connected to the third reset signal line, and the second pole is connected to the first pole of the driving transistor. The first electrode plate of the storage capacitor is connected to the power supply line, and the second electrode plate is connected to the first node. The first reset transistor and the compensation transistor are metal oxide transistors, and the driving transistor, writing transistor, second reset transistor, third reset transistor, first light emission control transistor, and second light emission control transistor are polysilicon transistors. The display panel according to any one of claims 1 to 12, characterized in that.

14. The driving backplane further includes a first semiconductor layer, a first gate insulating layer, a first gate layer, a first insulating layer, a second gate layer, a second insulating layer, a second semiconductor layer, a second gate insulating layer, a third gate layer, a third insulating layer, a first source-drain layer, a first flat layer, a second source-drain layer, a second flat layer, a third source-drain layer, and a third flat layer. The first semiconductor layer is provided on one side of the substrate and includes channels of the driving transistor, writing transistor, second reset transistor, third reset transistor, first light emission control transistor, and second light emission control transistor. The first gate insulating layer covers the first semiconductor layer. The first gate layer is provided on the surface of the first gate insulating layer away from the substrate and overlaps at least a part of the region of the first semiconductor layer. The first gate layer includes the second reset control line, the light emission control line, the first scanning line, and the first electrode plate. The first insulating layer covers the first gate layer, The second gate layer is provided on a surface of the first insulating layer away from the substrate, and includes a second electrode plate overlapping with the first electrode plate, The second insulating layer covers the second gate layer, The second semiconductor layer is provided on a surface of the second insulating layer away from the substrate, and includes channels of the first reset transistor and the compensation transistor, The second gate insulating layer covers the second semiconductor layer, The third gate layer is provided on a surface of the third gate insulating layer away from the substrate, overlaps with at least a part of the area of the second semiconductor layer, and the third gate layer includes the first reset control line, the first reset signal line, the second scanning line, and at least a part of the third reset signal line, The third insulating layer covers the third gate layer, The first source-drain layer is provided on a surface of the third insulating layer away from the substrate, and includes the second reset signal line and at least a part of the third reset signal line, The first planarization layer is provided on a side of the first source-drain layer away from the substrate, The second source-drain layer is provided on a surface of the first planarization layer away from the substrate, and includes the first connection line, The second planarization layer covers the second source-drain layer, The third source-drain layer is provided on a surface of the second planarization layer away from the substrate, and includes the data line, the power line, and the second connection line, The third planarization layer covers the third source-drain layer, and the first electrode is provided on a surface of the third planarization layer away from the substrate. The display panel according to claim 13, characterized in that.

15. The second semiconductor layer includes an oxide active portion extending along the column direction, the oxide active portion is located between the first reset signal line and the third reset signal line, the first reset control line overlaps with the oxide active portion to form the first reset transistor, and the second reset control line overlaps with the oxide active portion to form the compensation transistor, The first source-drain layer includes a first connection portion, one end of the first connection portion is connected to the first electrode plate, and the other end is connected to the oxide active portion between the first reset transistor and the channel of the second reset control line. The driving back plate further includes a plurality of shield portions located in the second source-drain layer. One of the shield portions overlaps with the first connection portion of one of the pixel circuits and the channel of the compensation transistor, and is connected to a power line connected to the pixel circuit. The display panel according to claim 14, characterized in that.

16. In a circuit unit having one of the shield portions and a first connection portion overlapping therewith, the two second electrode plates of the pixel circuit of the circuit unit are both connected overlapping the shield portion. The display panel according to claim 15, characterized in that.

17. The first source-drain layer includes a second connection portion and a third connection portion. The second connection portion is connected to the two second electrode plates, and one of the third connection portions is connected to one of the second electrode plates and the first electrode of the first light emission control transistor. The display panel according to claim 16, characterized in that.

18. In a circuit unit having one of the shield portions and a first connection portion overlapping therewith, two data lines connected to the circuit unit are located on both sides of the shield portion, and a power line connected to the circuit unit is located between the two data lines and is connected overlapping the shield portion. The display panel according to claim 15, characterized in that.

19. In one of the power lines and the circuit unit connected thereto, the power line has protruding portions protruding on both sides along the row direction, and the two protruding portions respectively overlap with the channels of the first reset transistors of the two pixel circuits. The display panel according to claim 14, characterized in that.

20. The first reset control line, the first reset signal line, the second reset control line, the second reset signal line, the third reset signal line, the first scanning line, the second scanning line and the light emission control line connected to the pixel circuits in the same row all extend along the row direction and are distributed along the column direction. The first reset control line, the first scanning line, the second scanning line, the third reset signal line, the light emission control line, and the second reset control line are located between the first reset signal line and the second reset signal line. The first scanning line, the second scanning line, at least a part of the third reset signal line, and the light emission control line are located between the first reset control line and the second reset control line. The second scanning line is located between the first scanning line and the light emission control line. The second electrode plate is located between the second scanning line and at least a part of the third reset signal line. The light emission control line overlaps at least a part of the third reset signal line. The first reset signal line connected to the pixel circuit in the (n + 1)-th row overlaps with the second reset control line connected to the pixel circuit in the n-th row. The display panel according to claim 15, characterized in that.

21. The second reset signal line connected to the pixel circuit in the (n + 1)-th row overlaps with the first reset control line and the first scanning line connected to the pixel circuit in the n-th row at the same time. The display panel according to claim 20, characterized in that.

22. The third reset signal line includes a line body extending along the row direction and a line branch connected to a side of the line body close to the second reset signal line. The line body and the line branch are located in different layers. The line body is located between the second scanning line and the second reset control line and overlaps with the light emission control line. The line branch extends to between the second reset control line and the second reset signal line and is connected to the first electrode of the third reset transistor. The display panel according to claim 20, characterized in that.

23. The line body is located in the third gate layer, and the line branch is located in the first source-drain layer. The display panel according to claim 22, characterized in that.

24. One of the first reset signal lines overlaps with one of the first connection lines. The display panel according to claim 20, characterized in that.

25. The oxide active part has a capacitive part extending along the row direction. The capacitive part is connected between the first reset transistor and the channels of the compensation transistors. The capacitive part overlaps with the first scanning line and is connected to the first connection part. The display panel according to claim 20, characterized in that.

26. A display device comprising the display panel according to any one of claims 1 to 25 characterized in that.

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